qcedev.c 73 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QTI CE device driver.
  4. *
  5. * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
  6. */
  7. #include <linux/mman.h>
  8. #include <linux/module.h>
  9. #include <linux/device.h>
  10. #include <linux/types.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/kernel.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/fs.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/scatterlist.h>
  23. #include <linux/crypto.h>
  24. #include "linux/platform_data/qcom_crypto_device.h"
  25. #include "linux/qcedev.h"
  26. #include <linux/interconnect.h>
  27. #include <crypto/hash.h>
  28. #include "qcedevi.h"
  29. #include "qce.h"
  30. #include "qcedev_smmu.h"
  31. #include "compat_qcedev.h"
  32. #include <linux/compat.h>
  33. #define CACHE_LINE_SIZE 64
  34. #define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
  35. #define MAX_CEHW_REQ_TRANSFER_SIZE (128*32*1024)
  36. /*
  37. * Max wait time once a crypto request is done.
  38. * Assuming 5ms per crypto operation, this is calculated for
  39. * the scenario of having 3 offload reqs + 1 tz req + buffer.
  40. */
  41. #define MAX_CRYPTO_WAIT_TIME 25
  42. #define MAX_REQUEST_TIME 5000
  43. enum qcedev_req_status {
  44. QCEDEV_REQ_CURRENT = 0,
  45. QCEDEV_REQ_WAITING = 1,
  46. QCEDEV_REQ_SUBMITTED = 2,
  47. };
  48. static uint8_t _std_init_vector_sha1_uint8[] = {
  49. 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
  50. 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
  51. 0xC3, 0xD2, 0xE1, 0xF0
  52. };
  53. /* standard initialization vector for SHA-256, source: FIPS 180-2 */
  54. static uint8_t _std_init_vector_sha256_uint8[] = {
  55. 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
  56. 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
  57. 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
  58. 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
  59. };
  60. #define QCEDEV_CTX_KEY_MASK 0x000000ff
  61. #define QCEDEV_CTX_USE_HW_KEY 0x00000001
  62. #define QCEDEV_CTX_USE_PIPE_KEY 0x00000002
  63. // Key timer expiry for pipes 1-15 (Status3)
  64. #define PIPE_KEY_TIMER_EXPIRED_STATUS3_MASK 0x000000FF
  65. // Key timer expiry for pipes 16-19 (Status6)
  66. #define PIPE_KEY_TIMER_EXPIRED_STATUS6_MASK 0x00000003
  67. // Key pause for pipes 1-15 (Status3)
  68. #define PIPE_KEY_PAUSE_STATUS3_MASK 0xFF0000
  69. // Key pause for pipes 16-19 (Status6)
  70. #define PIPE_KEY_PAUSE_STATUS6_MASK 0x30000
  71. #define QCEDEV_STATUS1_ERR_INTR_MASK 0x10
  72. static DEFINE_MUTEX(send_cmd_lock);
  73. static DEFINE_MUTEX(qcedev_sent_bw_req);
  74. static DEFINE_MUTEX(hash_access_lock);
  75. static dev_t qcedev_device_no;
  76. static struct class *driver_class;
  77. static struct device *class_dev;
  78. static const struct of_device_id qcedev_match[] = {
  79. { .compatible = "qcom,qcedev"},
  80. { .compatible = "qcom,qcedev,context-bank"},
  81. {}
  82. };
  83. MODULE_DEVICE_TABLE(of, qcedev_match);
  84. static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
  85. {
  86. unsigned int control_flag;
  87. int ret = 0;
  88. if (podev->ce_support.req_bw_before_clk) {
  89. if (enable)
  90. control_flag = QCE_BW_REQUEST_FIRST;
  91. else
  92. control_flag = QCE_CLK_DISABLE_FIRST;
  93. } else {
  94. if (enable)
  95. control_flag = QCE_CLK_ENABLE_FIRST;
  96. else
  97. control_flag = QCE_BW_REQUEST_RESET_FIRST;
  98. }
  99. switch (control_flag) {
  100. case QCE_CLK_ENABLE_FIRST:
  101. ret = qce_enable_clk(podev->qce);
  102. if (ret) {
  103. pr_err("%s Unable enable clk\n", __func__);
  104. return ret;
  105. }
  106. ret = icc_set_bw(podev->icc_path,
  107. podev->icc_avg_bw, podev->icc_peak_bw);
  108. if (ret) {
  109. pr_err("%s Unable to set high bw\n", __func__);
  110. ret = qce_disable_clk(podev->qce);
  111. if (ret)
  112. pr_err("%s Unable disable clk\n", __func__);
  113. return ret;
  114. }
  115. break;
  116. case QCE_BW_REQUEST_FIRST:
  117. ret = icc_set_bw(podev->icc_path,
  118. podev->icc_avg_bw, podev->icc_peak_bw);
  119. if (ret) {
  120. pr_err("%s Unable to set high bw\n", __func__);
  121. return ret;
  122. }
  123. ret = qce_enable_clk(podev->qce);
  124. if (ret) {
  125. pr_err("%s Unable enable clk\n", __func__);
  126. ret = icc_set_bw(podev->icc_path, 0, 0);
  127. if (ret)
  128. pr_err("%s Unable to set low bw\n", __func__);
  129. return ret;
  130. }
  131. break;
  132. case QCE_CLK_DISABLE_FIRST:
  133. ret = qce_disable_clk(podev->qce);
  134. if (ret) {
  135. pr_err("%s Unable to disable clk\n", __func__);
  136. return ret;
  137. }
  138. ret = icc_set_bw(podev->icc_path, 0, 0);
  139. if (ret) {
  140. pr_err("%s Unable to set low bw\n", __func__);
  141. ret = qce_enable_clk(podev->qce);
  142. if (ret)
  143. pr_err("%s Unable enable clk\n", __func__);
  144. return ret;
  145. }
  146. break;
  147. case QCE_BW_REQUEST_RESET_FIRST:
  148. ret = icc_set_bw(podev->icc_path, 0, 0);
  149. if (ret) {
  150. pr_err("%s Unable to set low bw\n", __func__);
  151. return ret;
  152. }
  153. ret = qce_disable_clk(podev->qce);
  154. if (ret) {
  155. pr_err("%s Unable to disable clk\n", __func__);
  156. ret = icc_set_bw(podev->icc_path,
  157. podev->icc_avg_bw, podev->icc_peak_bw);
  158. if (ret)
  159. pr_err("%s Unable to set high bw\n", __func__);
  160. return ret;
  161. }
  162. break;
  163. default:
  164. return -ENOENT;
  165. }
  166. return 0;
  167. }
  168. static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
  169. bool high_bw_req)
  170. {
  171. int ret = 0;
  172. mutex_lock(&qcedev_sent_bw_req);
  173. if (high_bw_req) {
  174. if (podev->high_bw_req_count == 0) {
  175. ret = qcedev_control_clocks(podev, true);
  176. if (ret)
  177. goto exit_unlock_mutex;
  178. }
  179. podev->high_bw_req_count++;
  180. } else {
  181. if (podev->high_bw_req_count == 1) {
  182. ret = qcedev_control_clocks(podev, false);
  183. if (ret)
  184. goto exit_unlock_mutex;
  185. }
  186. podev->high_bw_req_count--;
  187. }
  188. exit_unlock_mutex:
  189. mutex_unlock(&qcedev_sent_bw_req);
  190. }
  191. #define QCEDEV_MAGIC 0x56434544 /* "qced" */
  192. static int qcedev_open(struct inode *inode, struct file *file);
  193. static int qcedev_release(struct inode *inode, struct file *file);
  194. static int start_cipher_req(struct qcedev_control *podev,
  195. int *current_req_info);
  196. static int start_offload_cipher_req(struct qcedev_control *podev,
  197. int *current_req_info);
  198. static int start_sha_req(struct qcedev_control *podev,
  199. int *current_req_info);
  200. static const struct file_operations qcedev_fops = {
  201. .owner = THIS_MODULE,
  202. .unlocked_ioctl = qcedev_ioctl,
  203. #ifdef CONFIG_COMPAT
  204. .compat_ioctl = compat_qcedev_ioctl,
  205. #endif
  206. .open = qcedev_open,
  207. .release = qcedev_release,
  208. };
  209. static struct qcedev_control qce_dev[] = {
  210. {
  211. .magic = QCEDEV_MAGIC,
  212. },
  213. };
  214. #define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
  215. #define DEBUG_MAX_FNAME 16
  216. #define DEBUG_MAX_RW_BUF 1024
  217. struct qcedev_stat {
  218. u32 qcedev_dec_success;
  219. u32 qcedev_dec_fail;
  220. u32 qcedev_enc_success;
  221. u32 qcedev_enc_fail;
  222. u32 qcedev_sha_success;
  223. u32 qcedev_sha_fail;
  224. };
  225. static struct qcedev_stat _qcedev_stat;
  226. static struct dentry *_debug_dent;
  227. static char _debug_read_buf[DEBUG_MAX_RW_BUF];
  228. static int _debug_qcedev;
  229. static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
  230. {
  231. int i;
  232. for (i = 0; i < MAX_QCE_DEVICE; i++) {
  233. if (qce_dev[i].minor == n)
  234. return &qce_dev[n];
  235. }
  236. return NULL;
  237. }
  238. static int qcedev_open(struct inode *inode, struct file *file)
  239. {
  240. struct qcedev_handle *handle;
  241. struct qcedev_control *podev;
  242. podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
  243. if (podev == NULL) {
  244. pr_err("%s: no such device %d\n", __func__,
  245. MINOR(inode->i_rdev));
  246. return -ENOENT;
  247. }
  248. handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
  249. if (handle == NULL)
  250. return -ENOMEM;
  251. handle->cntl = podev;
  252. file->private_data = handle;
  253. qcedev_ce_high_bw_req(podev, true);
  254. mutex_init(&handle->registeredbufs.lock);
  255. INIT_LIST_HEAD(&handle->registeredbufs.list);
  256. return 0;
  257. }
  258. static int qcedev_release(struct inode *inode, struct file *file)
  259. {
  260. struct qcedev_control *podev;
  261. struct qcedev_handle *handle;
  262. handle = file->private_data;
  263. podev = handle->cntl;
  264. if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
  265. pr_err("%s: invalid handle %pK\n",
  266. __func__, podev);
  267. }
  268. qcedev_ce_high_bw_req(podev, false);
  269. if (qcedev_unmap_all_buffers(handle))
  270. pr_err("%s: failed to unmap all ion buffers\n", __func__);
  271. kfree_sensitive(handle);
  272. file->private_data = NULL;
  273. return 0;
  274. }
  275. static void req_done(unsigned long data)
  276. {
  277. struct qcedev_control *podev = (struct qcedev_control *)data;
  278. struct qcedev_async_req *areq;
  279. unsigned long flags = 0;
  280. struct qcedev_async_req *new_req = NULL;
  281. spin_lock_irqsave(&podev->lock, flags);
  282. areq = podev->active_command;
  283. podev->active_command = NULL;
  284. if (areq && !areq->timed_out)
  285. complete(&areq->complete);
  286. /* Look through queued requests and wake up the corresponding thread */
  287. if (!list_empty(&podev->ready_commands)) {
  288. new_req = container_of(podev->ready_commands.next,
  289. struct qcedev_async_req, list);
  290. list_del(&new_req->list);
  291. new_req->state = QCEDEV_REQ_CURRENT;
  292. wake_up_interruptible(&new_req->wait_q);
  293. }
  294. spin_unlock_irqrestore(&podev->lock, flags);
  295. }
  296. void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
  297. unsigned char *authdata, int ret)
  298. {
  299. struct qcedev_sha_req *areq;
  300. struct qcedev_control *pdev;
  301. struct qcedev_handle *handle;
  302. uint32_t *auth32 = (uint32_t *)authdata;
  303. areq = (struct qcedev_sha_req *) cookie;
  304. if (!areq || !areq->cookie)
  305. return;
  306. handle = (struct qcedev_handle *) areq->cookie;
  307. pdev = handle->cntl;
  308. if (!pdev)
  309. return;
  310. if (digest)
  311. memcpy(&handle->sha_ctxt.digest[0], digest, 32);
  312. if (authdata) {
  313. handle->sha_ctxt.auth_data[0] = auth32[0];
  314. handle->sha_ctxt.auth_data[1] = auth32[1];
  315. }
  316. tasklet_schedule(&pdev->done_tasklet);
  317. };
  318. void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
  319. unsigned char *iv, int ret)
  320. {
  321. struct qcedev_cipher_req *areq;
  322. struct qcedev_handle *handle;
  323. struct qcedev_control *podev;
  324. struct qcedev_async_req *qcedev_areq;
  325. areq = (struct qcedev_cipher_req *) cookie;
  326. if (!areq || !areq->cookie)
  327. return;
  328. handle = (struct qcedev_handle *) areq->cookie;
  329. podev = handle->cntl;
  330. if (!podev)
  331. return;
  332. qcedev_areq = podev->active_command;
  333. if (iv)
  334. memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
  335. qcedev_areq->cipher_op_req.ivlen);
  336. tasklet_schedule(&podev->done_tasklet);
  337. };
  338. static int start_cipher_req(struct qcedev_control *podev,
  339. int *current_req_info)
  340. {
  341. struct qcedev_async_req *qcedev_areq;
  342. struct qce_req creq;
  343. int ret = 0;
  344. memset(&creq, 0, sizeof(creq));
  345. /* start the command on the podev->active_command */
  346. qcedev_areq = podev->active_command;
  347. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  348. if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
  349. pr_err("%s: Use of PMEM is not supported\n", __func__);
  350. goto unsupported;
  351. }
  352. creq.pmem = NULL;
  353. switch (qcedev_areq->cipher_op_req.alg) {
  354. case QCEDEV_ALG_DES:
  355. creq.alg = CIPHER_ALG_DES;
  356. break;
  357. case QCEDEV_ALG_3DES:
  358. creq.alg = CIPHER_ALG_3DES;
  359. break;
  360. case QCEDEV_ALG_AES:
  361. creq.alg = CIPHER_ALG_AES;
  362. break;
  363. default:
  364. return -EINVAL;
  365. }
  366. switch (qcedev_areq->cipher_op_req.mode) {
  367. case QCEDEV_AES_MODE_CBC:
  368. case QCEDEV_DES_MODE_CBC:
  369. creq.mode = QCE_MODE_CBC;
  370. break;
  371. case QCEDEV_AES_MODE_ECB:
  372. case QCEDEV_DES_MODE_ECB:
  373. creq.mode = QCE_MODE_ECB;
  374. break;
  375. case QCEDEV_AES_MODE_CTR:
  376. creq.mode = QCE_MODE_CTR;
  377. break;
  378. case QCEDEV_AES_MODE_XTS:
  379. creq.mode = QCE_MODE_XTS;
  380. break;
  381. default:
  382. return -EINVAL;
  383. }
  384. if ((creq.alg == CIPHER_ALG_AES) &&
  385. (creq.mode == QCE_MODE_CTR)) {
  386. creq.dir = QCE_ENCRYPT;
  387. } else {
  388. if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
  389. creq.dir = QCE_ENCRYPT;
  390. else
  391. creq.dir = QCE_DECRYPT;
  392. }
  393. creq.iv = &qcedev_areq->cipher_op_req.iv[0];
  394. creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
  395. creq.iv_ctr_size = 0;
  396. creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
  397. creq.encklen = qcedev_areq->cipher_op_req.encklen;
  398. creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
  399. if (qcedev_areq->cipher_op_req.encklen == 0) {
  400. if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
  401. || (qcedev_areq->cipher_op_req.op ==
  402. QCEDEV_OPER_DEC_NO_KEY))
  403. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  404. else {
  405. int i;
  406. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  407. if (qcedev_areq->cipher_op_req.enckey[i] != 0)
  408. break;
  409. }
  410. if ((podev->platform_support.hw_key_support == 1) &&
  411. (i == QCEDEV_MAX_KEY_SIZE))
  412. creq.op = QCE_REQ_ABLK_CIPHER;
  413. else {
  414. ret = -EINVAL;
  415. goto unsupported;
  416. }
  417. }
  418. } else {
  419. creq.op = QCE_REQ_ABLK_CIPHER;
  420. }
  421. creq.qce_cb = qcedev_cipher_req_cb;
  422. creq.areq = (void *)&qcedev_areq->cipher_req;
  423. creq.flags = 0;
  424. creq.offload_op = QCE_OFFLOAD_NONE;
  425. ret = qce_ablk_cipher_req(podev->qce, &creq);
  426. *current_req_info = creq.current_req_info;
  427. unsupported:
  428. qcedev_areq->err = ret ? -ENXIO : 0;
  429. return ret;
  430. };
  431. void qcedev_offload_cipher_req_cb(void *cookie, unsigned char *icv,
  432. unsigned char *iv, int ret)
  433. {
  434. struct qcedev_cipher_req *areq;
  435. struct qcedev_handle *handle;
  436. struct qcedev_control *podev;
  437. struct qcedev_async_req *qcedev_areq;
  438. areq = (struct qcedev_cipher_req *) cookie;
  439. if (!areq || !areq->cookie)
  440. return;
  441. handle = (struct qcedev_handle *) areq->cookie;
  442. podev = handle->cntl;
  443. if (!podev)
  444. return;
  445. qcedev_areq = podev->active_command;
  446. if (iv)
  447. memcpy(&qcedev_areq->offload_cipher_op_req.iv[0], iv,
  448. qcedev_areq->offload_cipher_op_req.ivlen);
  449. tasklet_schedule(&podev->done_tasklet);
  450. }
  451. static int start_offload_cipher_req(struct qcedev_control *podev,
  452. int *current_req_info)
  453. {
  454. struct qcedev_async_req *qcedev_areq;
  455. struct qce_req creq;
  456. u8 patt_sz = 0, proc_data_sz = 0;
  457. int ret = 0;
  458. memset(&creq, 0, sizeof(creq));
  459. /* Start the command on the podev->active_command */
  460. qcedev_areq = podev->active_command;
  461. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  462. switch (qcedev_areq->offload_cipher_op_req.alg) {
  463. case QCEDEV_ALG_AES:
  464. creq.alg = CIPHER_ALG_AES;
  465. break;
  466. default:
  467. return -EINVAL;
  468. }
  469. switch (qcedev_areq->offload_cipher_op_req.mode) {
  470. case QCEDEV_AES_MODE_CBC:
  471. creq.mode = QCE_MODE_CBC;
  472. break;
  473. case QCEDEV_AES_MODE_CTR:
  474. creq.mode = QCE_MODE_CTR;
  475. break;
  476. default:
  477. return -EINVAL;
  478. }
  479. if (qcedev_areq->offload_cipher_op_req.is_copy_op) {
  480. creq.dir = QCE_ENCRYPT;
  481. } else {
  482. switch(qcedev_areq->offload_cipher_op_req.op) {
  483. case QCEDEV_OFFLOAD_HLOS_HLOS:
  484. case QCEDEV_OFFLOAD_HLOS_CPB:
  485. creq.dir = QCE_DECRYPT;
  486. break;
  487. case QCEDEV_OFFLOAD_CPB_HLOS:
  488. creq.dir = QCE_ENCRYPT;
  489. break;
  490. default:
  491. return -EINVAL;
  492. }
  493. }
  494. creq.iv = &qcedev_areq->offload_cipher_op_req.iv[0];
  495. creq.ivsize = qcedev_areq->offload_cipher_op_req.ivlen;
  496. creq.iv_ctr_size = qcedev_areq->offload_cipher_op_req.iv_ctr_size;
  497. creq.encklen = qcedev_areq->offload_cipher_op_req.encklen;
  498. /* OFFLOAD use cases use PIPE keys so no need to set keys */
  499. creq.flags = QCEDEV_CTX_USE_PIPE_KEY;
  500. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  501. creq.offload_op = (int)qcedev_areq->offload_cipher_op_req.op;
  502. if (qcedev_areq->offload_cipher_op_req.is_copy_op)
  503. creq.is_copy_op = true;
  504. creq.cryptlen = qcedev_areq->offload_cipher_op_req.data_len;
  505. creq.qce_cb = qcedev_offload_cipher_req_cb;
  506. creq.areq = (void *)&qcedev_areq->cipher_req;
  507. patt_sz = qcedev_areq->offload_cipher_op_req.pattern_info.patt_sz;
  508. proc_data_sz =
  509. qcedev_areq->offload_cipher_op_req.pattern_info.proc_data_sz;
  510. creq.is_pattern_valid =
  511. qcedev_areq->offload_cipher_op_req.is_pattern_valid;
  512. if (creq.is_pattern_valid) {
  513. creq.pattern_info = 0x1;
  514. if (patt_sz)
  515. creq.pattern_info |= (patt_sz - 1) << 4;
  516. if (proc_data_sz)
  517. creq.pattern_info |= (proc_data_sz - 1) << 8;
  518. creq.pattern_info |=
  519. qcedev_areq->offload_cipher_op_req.pattern_info.patt_offset << 12;
  520. }
  521. creq.block_offset = qcedev_areq->offload_cipher_op_req.block_offset;
  522. ret = qce_ablk_cipher_req(podev->qce, &creq);
  523. *current_req_info = creq.current_req_info;
  524. qcedev_areq->err = ret ? -ENXIO : 0;
  525. return ret;
  526. }
  527. static int start_sha_req(struct qcedev_control *podev,
  528. int *current_req_info)
  529. {
  530. struct qcedev_async_req *qcedev_areq;
  531. struct qce_sha_req sreq;
  532. int ret = 0;
  533. struct qcedev_handle *handle;
  534. /* start the command on the podev->active_command */
  535. qcedev_areq = podev->active_command;
  536. handle = qcedev_areq->handle;
  537. switch (qcedev_areq->sha_op_req.alg) {
  538. case QCEDEV_ALG_SHA1:
  539. sreq.alg = QCE_HASH_SHA1;
  540. break;
  541. case QCEDEV_ALG_SHA256:
  542. sreq.alg = QCE_HASH_SHA256;
  543. break;
  544. case QCEDEV_ALG_SHA1_HMAC:
  545. if (podev->ce_support.sha_hmac) {
  546. sreq.alg = QCE_HASH_SHA1_HMAC;
  547. sreq.authkey = &handle->sha_ctxt.authkey[0];
  548. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  549. } else {
  550. sreq.alg = QCE_HASH_SHA1;
  551. sreq.authkey = NULL;
  552. }
  553. break;
  554. case QCEDEV_ALG_SHA256_HMAC:
  555. if (podev->ce_support.sha_hmac) {
  556. sreq.alg = QCE_HASH_SHA256_HMAC;
  557. sreq.authkey = &handle->sha_ctxt.authkey[0];
  558. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  559. } else {
  560. sreq.alg = QCE_HASH_SHA256;
  561. sreq.authkey = NULL;
  562. }
  563. break;
  564. case QCEDEV_ALG_AES_CMAC:
  565. sreq.alg = QCE_HASH_AES_CMAC;
  566. sreq.authkey = &handle->sha_ctxt.authkey[0];
  567. sreq.authklen = qcedev_areq->sha_op_req.authklen;
  568. break;
  569. default:
  570. pr_err("Algorithm %d not supported, exiting\n",
  571. qcedev_areq->sha_op_req.alg);
  572. return -EINVAL;
  573. }
  574. qcedev_areq->sha_req.cookie = handle;
  575. sreq.qce_cb = qcedev_sha_req_cb;
  576. if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
  577. sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
  578. sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
  579. sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
  580. sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
  581. sreq.digest = &handle->sha_ctxt.digest[0];
  582. sreq.first_blk = handle->sha_ctxt.first_blk;
  583. sreq.last_blk = handle->sha_ctxt.last_blk;
  584. }
  585. sreq.size = qcedev_areq->sha_req.sreq.nbytes;
  586. sreq.src = qcedev_areq->sha_req.sreq.src;
  587. sreq.areq = (void *)&qcedev_areq->sha_req;
  588. sreq.flags = 0;
  589. ret = qce_process_sha_req(podev->qce, &sreq);
  590. *current_req_info = sreq.current_req_info;
  591. qcedev_areq->err = ret ? -ENXIO : 0;
  592. return ret;
  593. };
  594. static void qcedev_check_crypto_status(
  595. struct qcedev_async_req *qcedev_areq, void *handle,
  596. bool print_err)
  597. {
  598. unsigned int s1, s2, s3, s4, s5, s6;
  599. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  600. qce_get_crypto_status(handle, &s1, &s2, &s3, &s4, &s5, &s6);
  601. if (print_err) {
  602. pr_err("%s: sts = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", __func__,
  603. s1, s2, s3, s4, s5, s6);
  604. }
  605. // Check for key timer expiry
  606. if ((s6 & PIPE_KEY_TIMER_EXPIRED_STATUS6_MASK) ||
  607. (s3 & PIPE_KEY_TIMER_EXPIRED_STATUS3_MASK)) {
  608. pr_info("%s: crypto timer expired\n", __func__);
  609. pr_info("%s: sts = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", __func__,
  610. s1, s2, s3, s4, s5, s6);
  611. qcedev_areq->offload_cipher_op_req.err =
  612. QCEDEV_OFFLOAD_KEY_TIMER_EXPIRED_ERROR;
  613. return;
  614. }
  615. // Check for key pause
  616. if ((s6 & PIPE_KEY_PAUSE_STATUS6_MASK) ||
  617. (s3 & PIPE_KEY_PAUSE_STATUS3_MASK)) {
  618. pr_info("%s: crypto key paused\n", __func__);
  619. pr_info("%s: sts = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", __func__,
  620. s1, s2, s3, s4, s5, s6);
  621. qcedev_areq->offload_cipher_op_req.err =
  622. QCEDEV_OFFLOAD_KEY_PAUSE_ERROR;
  623. return;
  624. }
  625. // Check for generic error
  626. if (s1 & QCEDEV_STATUS1_ERR_INTR_MASK) {
  627. pr_err("%s: generic crypto error\n", __func__);
  628. pr_info("%s: sts = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", __func__,
  629. s1, s2, s3, s4, s5, s6);
  630. qcedev_areq->offload_cipher_op_req.err =
  631. QCEDEV_OFFLOAD_GENERIC_ERROR;
  632. return;
  633. }
  634. }
  635. static int submit_req(struct qcedev_async_req *qcedev_areq,
  636. struct qcedev_handle *handle)
  637. {
  638. struct qcedev_control *podev;
  639. unsigned long flags = 0;
  640. int ret = 0;
  641. struct qcedev_stat *pstat;
  642. int current_req_info = 0;
  643. int wait = MAX_CRYPTO_WAIT_TIME;
  644. bool print_sts = false;
  645. struct qcedev_async_req *new_req = NULL;
  646. qcedev_areq->err = 0;
  647. podev = handle->cntl;
  648. init_waitqueue_head(&qcedev_areq->wait_q);
  649. spin_lock_irqsave(&podev->lock, flags);
  650. /*
  651. * Service only one crypto request at a time.
  652. * Any other new requests are queued in ready_commands and woken up
  653. * only when the active command has finished successfully or when the
  654. * request times out or when the command failed when setting up.
  655. */
  656. do {
  657. if (podev->active_command == NULL) {
  658. podev->active_command = qcedev_areq;
  659. qcedev_areq->state = QCEDEV_REQ_SUBMITTED;
  660. switch (qcedev_areq->op_type) {
  661. case QCEDEV_CRYPTO_OPER_CIPHER:
  662. ret = start_cipher_req(podev,
  663. &current_req_info);
  664. break;
  665. case QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER:
  666. ret = start_offload_cipher_req(podev,
  667. &current_req_info);
  668. break;
  669. default:
  670. ret = start_sha_req(podev,
  671. &current_req_info);
  672. break;
  673. }
  674. } else {
  675. list_add_tail(&qcedev_areq->list,
  676. &podev->ready_commands);
  677. qcedev_areq->state = QCEDEV_REQ_WAITING;
  678. if (wait_event_interruptible_lock_irq_timeout(
  679. qcedev_areq->wait_q,
  680. (qcedev_areq->state == QCEDEV_REQ_CURRENT),
  681. podev->lock,
  682. msecs_to_jiffies(MAX_REQUEST_TIME)) == 0) {
  683. pr_err("%s: request timed out\n", __func__);
  684. return qcedev_areq->err;
  685. }
  686. }
  687. } while (qcedev_areq->state != QCEDEV_REQ_SUBMITTED);
  688. if (ret != 0) {
  689. podev->active_command = NULL;
  690. /*
  691. * Look through queued requests and wake up the corresponding
  692. * thread.
  693. */
  694. if (!list_empty(&podev->ready_commands)) {
  695. new_req = container_of(podev->ready_commands.next,
  696. struct qcedev_async_req, list);
  697. list_del(&new_req->list);
  698. new_req->state = QCEDEV_REQ_CURRENT;
  699. wake_up_interruptible(&new_req->wait_q);
  700. }
  701. }
  702. spin_unlock_irqrestore(&podev->lock, flags);
  703. qcedev_areq->timed_out = false;
  704. if (ret == 0)
  705. wait = wait_for_completion_timeout(&qcedev_areq->complete,
  706. msecs_to_jiffies(MAX_CRYPTO_WAIT_TIME));
  707. if (!wait) {
  708. /*
  709. * This means wait timed out, and the callback routine was not
  710. * exercised. The callback sequence does some housekeeping which
  711. * would be missed here, hence having a call to qce here to do
  712. * that.
  713. */
  714. pr_err("%s: wait timed out, req info = %d\n", __func__,
  715. current_req_info);
  716. print_sts = true;
  717. qcedev_check_crypto_status(qcedev_areq, podev->qce, print_sts);
  718. qcedev_areq->timed_out = true;
  719. ret = qce_manage_timeout(podev->qce, current_req_info);
  720. if (ret) {
  721. pr_err("%s: error during manage timeout", __func__);
  722. qcedev_areq->err = -EIO;
  723. return qcedev_areq->err;
  724. }
  725. tasklet_schedule(&podev->done_tasklet);
  726. if (qcedev_areq->offload_cipher_op_req.err !=
  727. QCEDEV_OFFLOAD_NO_ERROR)
  728. return 0;
  729. }
  730. if (ret)
  731. qcedev_areq->err = -EIO;
  732. pstat = &_qcedev_stat;
  733. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
  734. switch (qcedev_areq->cipher_op_req.op) {
  735. case QCEDEV_OPER_DEC:
  736. if (qcedev_areq->err)
  737. pstat->qcedev_dec_fail++;
  738. else
  739. pstat->qcedev_dec_success++;
  740. break;
  741. case QCEDEV_OPER_ENC:
  742. if (qcedev_areq->err)
  743. pstat->qcedev_enc_fail++;
  744. else
  745. pstat->qcedev_enc_success++;
  746. break;
  747. default:
  748. break;
  749. }
  750. } else if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER) {
  751. //Do nothing
  752. } else {
  753. if (qcedev_areq->err)
  754. pstat->qcedev_sha_fail++;
  755. else
  756. pstat->qcedev_sha_success++;
  757. }
  758. return qcedev_areq->err;
  759. }
  760. static int qcedev_sha_init(struct qcedev_async_req *areq,
  761. struct qcedev_handle *handle)
  762. {
  763. struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
  764. memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
  765. sha_ctxt->first_blk = 1;
  766. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  767. (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
  768. memcpy(&sha_ctxt->digest[0],
  769. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  770. sha_ctxt->diglen = SHA1_DIGEST_SIZE;
  771. } else {
  772. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
  773. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
  774. memcpy(&sha_ctxt->digest[0],
  775. &_std_init_vector_sha256_uint8[0],
  776. SHA256_DIGEST_SIZE);
  777. sha_ctxt->diglen = SHA256_DIGEST_SIZE;
  778. }
  779. }
  780. sha_ctxt->init_done = true;
  781. return 0;
  782. }
  783. static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
  784. struct qcedev_handle *handle,
  785. struct scatterlist *sg_src)
  786. {
  787. int err = 0;
  788. int i = 0;
  789. uint32_t total;
  790. uint8_t *user_src = NULL;
  791. uint8_t *k_src = NULL;
  792. uint8_t *k_buf_src = NULL;
  793. uint8_t *k_align_src = NULL;
  794. uint32_t sha_pad_len = 0;
  795. uint32_t trailing_buf_len = 0;
  796. uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
  797. uint32_t sha_block_size;
  798. total = qcedev_areq->sha_op_req.data_len + t_buf;
  799. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
  800. sha_block_size = SHA1_BLOCK_SIZE;
  801. else
  802. sha_block_size = SHA256_BLOCK_SIZE;
  803. if (total <= sha_block_size) {
  804. uint32_t len = qcedev_areq->sha_op_req.data_len;
  805. i = 0;
  806. k_src = &handle->sha_ctxt.trailing_buf[t_buf];
  807. /* Copy data from user src(s) */
  808. while (len > 0) {
  809. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  810. if (user_src && copy_from_user(k_src,
  811. (void __user *)user_src,
  812. qcedev_areq->sha_op_req.data[i].len))
  813. return -EFAULT;
  814. len -= qcedev_areq->sha_op_req.data[i].len;
  815. k_src += qcedev_areq->sha_op_req.data[i].len;
  816. i++;
  817. }
  818. handle->sha_ctxt.trailing_buf_len = total;
  819. return 0;
  820. }
  821. k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
  822. GFP_KERNEL);
  823. if (k_buf_src == NULL)
  824. return -ENOMEM;
  825. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  826. CACHE_LINE_SIZE);
  827. k_src = k_align_src;
  828. /* check for trailing buffer from previous updates and append it */
  829. if (t_buf > 0) {
  830. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  831. t_buf);
  832. k_src += t_buf;
  833. }
  834. /* Copy data from user src(s) */
  835. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  836. if (user_src && copy_from_user(k_src,
  837. (void __user *)user_src,
  838. qcedev_areq->sha_op_req.data[0].len)) {
  839. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  840. kfree(k_buf_src);
  841. return -EFAULT;
  842. }
  843. k_src += qcedev_areq->sha_op_req.data[0].len;
  844. for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
  845. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  846. if (user_src && copy_from_user(k_src,
  847. (void __user *)user_src,
  848. qcedev_areq->sha_op_req.data[i].len)) {
  849. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  850. kfree(k_buf_src);
  851. return -EFAULT;
  852. }
  853. k_src += qcedev_areq->sha_op_req.data[i].len;
  854. }
  855. /* get new trailing buffer */
  856. sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
  857. trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
  858. qcedev_areq->sha_req.sreq.src = sg_src;
  859. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src,
  860. total-trailing_buf_len);
  861. qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
  862. /* update sha_ctxt trailing buf content to new trailing buf */
  863. if (trailing_buf_len > 0) {
  864. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  865. memcpy(&handle->sha_ctxt.trailing_buf[0],
  866. (k_src - trailing_buf_len),
  867. trailing_buf_len);
  868. }
  869. handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
  870. err = submit_req(qcedev_areq, handle);
  871. handle->sha_ctxt.last_blk = 0;
  872. handle->sha_ctxt.first_blk = 0;
  873. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  874. kfree(k_buf_src);
  875. return err;
  876. }
  877. static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
  878. struct qcedev_handle *handle,
  879. struct scatterlist *sg_src)
  880. {
  881. int err = 0;
  882. int i = 0;
  883. int j = 0;
  884. int k = 0;
  885. int num_entries = 0;
  886. uint32_t total = 0;
  887. if (!handle->sha_ctxt.init_done) {
  888. pr_err("%s Init was not called\n", __func__);
  889. return -EINVAL;
  890. }
  891. if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
  892. struct qcedev_sha_op_req *saved_req;
  893. struct qcedev_sha_op_req req;
  894. struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
  895. /* save the original req structure */
  896. saved_req =
  897. kmalloc(sizeof(struct qcedev_sha_op_req), GFP_KERNEL);
  898. if (saved_req == NULL) {
  899. pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
  900. __func__, (uintptr_t)saved_req);
  901. return -ENOMEM;
  902. }
  903. memcpy(&req, sreq, sizeof(struct qcedev_sha_op_req));
  904. memcpy(saved_req, sreq, sizeof(struct qcedev_sha_op_req));
  905. i = 0;
  906. /* Address 32 KB at a time */
  907. while ((i < req.entries) && (err == 0)) {
  908. if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
  909. sreq->data[0].len = QCE_MAX_OPER_DATA;
  910. if (i > 0) {
  911. sreq->data[0].vaddr =
  912. sreq->data[i].vaddr;
  913. }
  914. sreq->data_len = QCE_MAX_OPER_DATA;
  915. sreq->entries = 1;
  916. err = qcedev_sha_update_max_xfer(qcedev_areq,
  917. handle, sg_src);
  918. sreq->data[i].len = req.data[i].len -
  919. QCE_MAX_OPER_DATA;
  920. sreq->data[i].vaddr = req.data[i].vaddr +
  921. QCE_MAX_OPER_DATA;
  922. req.data[i].vaddr = sreq->data[i].vaddr;
  923. req.data[i].len = sreq->data[i].len;
  924. } else {
  925. total = 0;
  926. for (j = i; j < req.entries; j++) {
  927. num_entries++;
  928. if ((total + sreq->data[j].len) >=
  929. QCE_MAX_OPER_DATA) {
  930. sreq->data[j].len =
  931. (QCE_MAX_OPER_DATA - total);
  932. total = QCE_MAX_OPER_DATA;
  933. break;
  934. }
  935. total += sreq->data[j].len;
  936. }
  937. sreq->data_len = total;
  938. if (i > 0)
  939. for (k = 0; k < num_entries; k++) {
  940. sreq->data[k].len =
  941. sreq->data[i+k].len;
  942. sreq->data[k].vaddr =
  943. sreq->data[i+k].vaddr;
  944. }
  945. sreq->entries = num_entries;
  946. i = j;
  947. err = qcedev_sha_update_max_xfer(qcedev_areq,
  948. handle, sg_src);
  949. num_entries = 0;
  950. sreq->data[i].vaddr = req.data[i].vaddr +
  951. sreq->data[i].len;
  952. sreq->data[i].len = req.data[i].len -
  953. sreq->data[i].len;
  954. req.data[i].vaddr = sreq->data[i].vaddr;
  955. req.data[i].len = sreq->data[i].len;
  956. if (sreq->data[i].len == 0)
  957. i++;
  958. }
  959. } /* end of while ((i < req.entries) && (err == 0)) */
  960. /* Restore the original req structure */
  961. for (i = 0; i < saved_req->entries; i++) {
  962. sreq->data[i].len = saved_req->data[i].len;
  963. sreq->data[i].vaddr = saved_req->data[i].vaddr;
  964. }
  965. sreq->entries = saved_req->entries;
  966. sreq->data_len = saved_req->data_len;
  967. memset(saved_req, 0, ksize((void *)saved_req));
  968. kfree(saved_req);
  969. } else
  970. err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
  971. return err;
  972. }
  973. static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
  974. struct qcedev_handle *handle)
  975. {
  976. int err = 0;
  977. struct scatterlist sg_src;
  978. uint32_t total;
  979. uint8_t *k_buf_src = NULL;
  980. uint8_t *k_align_src = NULL;
  981. if (!handle->sha_ctxt.init_done) {
  982. pr_err("%s Init was not called\n", __func__);
  983. return -EINVAL;
  984. }
  985. handle->sha_ctxt.last_blk = 1;
  986. total = handle->sha_ctxt.trailing_buf_len;
  987. k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
  988. GFP_KERNEL);
  989. if (k_buf_src == NULL)
  990. return -ENOMEM;
  991. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  992. CACHE_LINE_SIZE);
  993. memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
  994. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  995. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src, total);
  996. qcedev_areq->sha_req.sreq.nbytes = total;
  997. err = submit_req(qcedev_areq, handle);
  998. handle->sha_ctxt.first_blk = 0;
  999. handle->sha_ctxt.last_blk = 0;
  1000. handle->sha_ctxt.auth_data[0] = 0;
  1001. handle->sha_ctxt.auth_data[1] = 0;
  1002. handle->sha_ctxt.trailing_buf_len = 0;
  1003. handle->sha_ctxt.init_done = false;
  1004. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  1005. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  1006. kfree(k_buf_src);
  1007. qcedev_areq->sha_req.sreq.src = NULL;
  1008. return err;
  1009. }
  1010. static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
  1011. struct qcedev_handle *handle,
  1012. struct scatterlist *sg_src)
  1013. {
  1014. int err = 0;
  1015. int i = 0;
  1016. uint32_t total;
  1017. uint8_t *user_src = NULL;
  1018. uint8_t *k_src = NULL;
  1019. uint8_t *k_buf_src = NULL;
  1020. total = qcedev_areq->sha_op_req.data_len;
  1021. if ((qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_128) &&
  1022. (qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_256)) {
  1023. pr_err("%s: unsupported key length\n", __func__);
  1024. return -EINVAL;
  1025. }
  1026. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1027. (void __user *)qcedev_areq->sha_op_req.authkey,
  1028. qcedev_areq->sha_op_req.authklen))
  1029. return -EFAULT;
  1030. if (total > U32_MAX - CACHE_LINE_SIZE * 2)
  1031. return -EINVAL;
  1032. k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2, GFP_KERNEL);
  1033. if (k_buf_src == NULL)
  1034. return -ENOMEM;
  1035. k_src = k_buf_src;
  1036. /* Copy data from user src(s) */
  1037. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  1038. for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
  1039. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  1040. if (user_src && copy_from_user(k_src, (void __user *)user_src,
  1041. qcedev_areq->sha_op_req.data[i].len)) {
  1042. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  1043. kfree(k_buf_src);
  1044. return -EFAULT;
  1045. }
  1046. k_src += qcedev_areq->sha_op_req.data[i].len;
  1047. }
  1048. qcedev_areq->sha_req.sreq.src = sg_src;
  1049. sg_init_one(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
  1050. qcedev_areq->sha_req.sreq.nbytes = total;
  1051. handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
  1052. err = submit_req(qcedev_areq, handle);
  1053. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  1054. kfree(k_buf_src);
  1055. return err;
  1056. }
  1057. static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
  1058. struct qcedev_handle *handle,
  1059. struct scatterlist *sg_src)
  1060. {
  1061. int err = 0;
  1062. if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
  1063. qcedev_sha_init(areq, handle);
  1064. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1065. (void __user *)areq->sha_op_req.authkey,
  1066. areq->sha_op_req.authklen))
  1067. return -EFAULT;
  1068. } else {
  1069. struct qcedev_async_req authkey_areq;
  1070. uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
  1071. init_completion(&authkey_areq.complete);
  1072. authkey_areq.sha_op_req.entries = 1;
  1073. authkey_areq.sha_op_req.data[0].vaddr =
  1074. areq->sha_op_req.authkey;
  1075. authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
  1076. authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
  1077. authkey_areq.sha_op_req.diglen = 0;
  1078. authkey_areq.handle = handle;
  1079. memset(&authkey_areq.sha_op_req.digest[0], 0,
  1080. QCEDEV_MAX_SHA_DIGEST);
  1081. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1082. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
  1083. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
  1084. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
  1085. authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1086. qcedev_sha_init(&authkey_areq, handle);
  1087. err = qcedev_sha_update(&authkey_areq, handle, sg_src);
  1088. if (!err)
  1089. err = qcedev_sha_final(&authkey_areq, handle);
  1090. else
  1091. return err;
  1092. memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
  1093. handle->sha_ctxt.diglen);
  1094. qcedev_sha_init(areq, handle);
  1095. memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
  1096. handle->sha_ctxt.diglen);
  1097. }
  1098. return err;
  1099. }
  1100. static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
  1101. struct qcedev_handle *handle)
  1102. {
  1103. int err = 0;
  1104. struct scatterlist sg_src;
  1105. uint8_t *k_src = NULL;
  1106. uint32_t sha_block_size = 0;
  1107. uint32_t sha_digest_size = 0;
  1108. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1109. sha_digest_size = SHA1_DIGEST_SIZE;
  1110. sha_block_size = SHA1_BLOCK_SIZE;
  1111. } else {
  1112. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1113. sha_digest_size = SHA256_DIGEST_SIZE;
  1114. sha_block_size = SHA256_BLOCK_SIZE;
  1115. }
  1116. }
  1117. k_src = kmalloc(sha_block_size, GFP_KERNEL);
  1118. if (k_src == NULL)
  1119. return -ENOMEM;
  1120. /* check for trailing buffer from previous updates and append it */
  1121. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  1122. handle->sha_ctxt.trailing_buf_len);
  1123. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1124. sg_init_one(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
  1125. qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
  1126. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1127. memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
  1128. sha_digest_size);
  1129. handle->sha_ctxt.trailing_buf_len = sha_digest_size;
  1130. handle->sha_ctxt.first_blk = 1;
  1131. handle->sha_ctxt.last_blk = 0;
  1132. handle->sha_ctxt.auth_data[0] = 0;
  1133. handle->sha_ctxt.auth_data[1] = 0;
  1134. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1135. memcpy(&handle->sha_ctxt.digest[0],
  1136. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  1137. handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
  1138. }
  1139. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1140. memcpy(&handle->sha_ctxt.digest[0],
  1141. &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
  1142. handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
  1143. }
  1144. err = submit_req(qcedev_areq, handle);
  1145. handle->sha_ctxt.last_blk = 0;
  1146. handle->sha_ctxt.first_blk = 0;
  1147. memset(k_src, 0, ksize((void *)k_src));
  1148. kfree(k_src);
  1149. qcedev_areq->sha_req.sreq.src = NULL;
  1150. return err;
  1151. }
  1152. static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
  1153. struct qcedev_handle *handle, bool ikey)
  1154. {
  1155. int i;
  1156. uint32_t constant;
  1157. uint32_t sha_block_size;
  1158. if (ikey)
  1159. constant = 0x36;
  1160. else
  1161. constant = 0x5c;
  1162. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1163. sha_block_size = SHA1_BLOCK_SIZE;
  1164. else
  1165. sha_block_size = SHA256_BLOCK_SIZE;
  1166. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1167. for (i = 0; i < sha_block_size; i++)
  1168. handle->sha_ctxt.trailing_buf[i] =
  1169. (handle->sha_ctxt.authkey[i] ^ constant);
  1170. handle->sha_ctxt.trailing_buf_len = sha_block_size;
  1171. return 0;
  1172. }
  1173. static int qcedev_hmac_init(struct qcedev_async_req *areq,
  1174. struct qcedev_handle *handle,
  1175. struct scatterlist *sg_src)
  1176. {
  1177. int err;
  1178. struct qcedev_control *podev = handle->cntl;
  1179. err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
  1180. if (err)
  1181. return err;
  1182. if (!podev->ce_support.sha_hmac)
  1183. qcedev_hmac_update_iokey(areq, handle, true);
  1184. return 0;
  1185. }
  1186. static int qcedev_hmac_final(struct qcedev_async_req *areq,
  1187. struct qcedev_handle *handle)
  1188. {
  1189. int err;
  1190. struct qcedev_control *podev = handle->cntl;
  1191. err = qcedev_sha_final(areq, handle);
  1192. if (podev->ce_support.sha_hmac)
  1193. return err;
  1194. qcedev_hmac_update_iokey(areq, handle, false);
  1195. err = qcedev_hmac_get_ohash(areq, handle);
  1196. if (err)
  1197. return err;
  1198. err = qcedev_sha_final(areq, handle);
  1199. return err;
  1200. }
  1201. static int qcedev_hash_init(struct qcedev_async_req *areq,
  1202. struct qcedev_handle *handle,
  1203. struct scatterlist *sg_src)
  1204. {
  1205. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1206. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1207. return qcedev_sha_init(areq, handle);
  1208. else
  1209. return qcedev_hmac_init(areq, handle, sg_src);
  1210. }
  1211. static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
  1212. struct qcedev_handle *handle,
  1213. struct scatterlist *sg_src)
  1214. {
  1215. return qcedev_sha_update(qcedev_areq, handle, sg_src);
  1216. }
  1217. static int qcedev_hash_final(struct qcedev_async_req *areq,
  1218. struct qcedev_handle *handle)
  1219. {
  1220. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1221. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1222. return qcedev_sha_final(areq, handle);
  1223. else
  1224. return qcedev_hmac_final(areq, handle);
  1225. }
  1226. static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
  1227. int *di, struct qcedev_handle *handle,
  1228. uint8_t *k_align_src)
  1229. {
  1230. int err = 0;
  1231. int i = 0;
  1232. int dst_i = *di;
  1233. struct scatterlist sg_src;
  1234. uint32_t byteoffset = 0;
  1235. uint8_t *user_src = NULL;
  1236. uint8_t *k_align_dst = k_align_src;
  1237. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1238. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1239. byteoffset = areq->cipher_op_req.byteoffset;
  1240. user_src = areq->cipher_op_req.vbuf.src[0].vaddr;
  1241. if (user_src && copy_from_user((k_align_src + byteoffset),
  1242. (void __user *)user_src,
  1243. areq->cipher_op_req.vbuf.src[0].len))
  1244. return -EFAULT;
  1245. k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
  1246. for (i = 1; i < areq->cipher_op_req.entries; i++) {
  1247. user_src = areq->cipher_op_req.vbuf.src[i].vaddr;
  1248. if (user_src && copy_from_user(k_align_src,
  1249. (void __user *)user_src,
  1250. areq->cipher_op_req.vbuf.src[i].len)) {
  1251. return -EFAULT;
  1252. }
  1253. k_align_src += areq->cipher_op_req.vbuf.src[i].len;
  1254. }
  1255. /* restore src beginning */
  1256. k_align_src = k_align_dst;
  1257. areq->cipher_op_req.data_len += byteoffset;
  1258. areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
  1259. areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
  1260. /* In place encryption/decryption */
  1261. sg_init_one(areq->cipher_req.creq.src,
  1262. k_align_dst,
  1263. areq->cipher_op_req.data_len);
  1264. areq->cipher_req.creq.cryptlen = areq->cipher_op_req.data_len;
  1265. areq->cipher_req.creq.iv = areq->cipher_op_req.iv;
  1266. areq->cipher_op_req.entries = 1;
  1267. err = submit_req(areq, handle);
  1268. /* copy data to destination buffer*/
  1269. creq->data_len -= byteoffset;
  1270. while (creq->data_len > 0) {
  1271. if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
  1272. if (err == 0 && copy_to_user(
  1273. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1274. (k_align_dst + byteoffset),
  1275. creq->vbuf.dst[dst_i].len)) {
  1276. err = -EFAULT;
  1277. goto exit;
  1278. }
  1279. k_align_dst += creq->vbuf.dst[dst_i].len;
  1280. creq->data_len -= creq->vbuf.dst[dst_i].len;
  1281. dst_i++;
  1282. } else {
  1283. if (err == 0 && copy_to_user(
  1284. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1285. (k_align_dst + byteoffset),
  1286. creq->data_len)) {
  1287. err = -EFAULT;
  1288. goto exit;
  1289. }
  1290. k_align_dst += creq->data_len;
  1291. creq->vbuf.dst[dst_i].len -= creq->data_len;
  1292. creq->vbuf.dst[dst_i].vaddr += creq->data_len;
  1293. creq->data_len = 0;
  1294. }
  1295. }
  1296. *di = dst_i;
  1297. exit:
  1298. areq->cipher_req.creq.src = NULL;
  1299. areq->cipher_req.creq.dst = NULL;
  1300. return err;
  1301. };
  1302. static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
  1303. struct qcedev_handle *handle)
  1304. {
  1305. int err = 0;
  1306. int di = 0;
  1307. int i = 0;
  1308. int j = 0;
  1309. int k = 0;
  1310. uint32_t byteoffset = 0;
  1311. int num_entries = 0;
  1312. uint32_t total = 0;
  1313. uint32_t len;
  1314. uint8_t *k_buf_src = NULL;
  1315. uint8_t *k_align_src = NULL;
  1316. uint32_t max_data_xfer;
  1317. struct qcedev_cipher_op_req *saved_req;
  1318. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1319. total = 0;
  1320. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1321. byteoffset = areq->cipher_op_req.byteoffset;
  1322. k_buf_src = kmalloc(QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2,
  1323. GFP_KERNEL);
  1324. if (k_buf_src == NULL)
  1325. return -ENOMEM;
  1326. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1327. CACHE_LINE_SIZE);
  1328. max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
  1329. saved_req = kmemdup(creq, sizeof(struct qcedev_cipher_op_req),
  1330. GFP_KERNEL);
  1331. if (saved_req == NULL) {
  1332. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  1333. kfree(k_buf_src);
  1334. return -ENOMEM;
  1335. }
  1336. if (areq->cipher_op_req.data_len > max_data_xfer) {
  1337. struct qcedev_cipher_op_req req;
  1338. /* save the original req structure */
  1339. memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
  1340. i = 0;
  1341. /* Address 32 KB at a time */
  1342. while ((i < req.entries) && (err == 0)) {
  1343. if (creq->vbuf.src[i].len > max_data_xfer) {
  1344. creq->vbuf.src[0].len = max_data_xfer;
  1345. if (i > 0) {
  1346. creq->vbuf.src[0].vaddr =
  1347. creq->vbuf.src[i].vaddr;
  1348. }
  1349. creq->data_len = max_data_xfer;
  1350. creq->entries = 1;
  1351. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1352. &di, handle, k_align_src);
  1353. if (err < 0) {
  1354. memset(saved_req, 0,
  1355. ksize((void *)saved_req));
  1356. memset(k_buf_src, 0,
  1357. ksize((void *)k_buf_src));
  1358. kfree(k_buf_src);
  1359. kfree(saved_req);
  1360. return err;
  1361. }
  1362. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1363. max_data_xfer;
  1364. creq->vbuf.src[i].vaddr =
  1365. req.vbuf.src[i].vaddr +
  1366. max_data_xfer;
  1367. req.vbuf.src[i].vaddr =
  1368. creq->vbuf.src[i].vaddr;
  1369. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1370. } else {
  1371. total = areq->cipher_op_req.byteoffset;
  1372. for (j = i; j < req.entries; j++) {
  1373. num_entries++;
  1374. if ((total + creq->vbuf.src[j].len)
  1375. >= max_data_xfer) {
  1376. creq->vbuf.src[j].len =
  1377. max_data_xfer - total;
  1378. total = max_data_xfer;
  1379. break;
  1380. }
  1381. total += creq->vbuf.src[j].len;
  1382. }
  1383. creq->data_len = total;
  1384. if (i > 0)
  1385. for (k = 0; k < num_entries; k++) {
  1386. creq->vbuf.src[k].len =
  1387. creq->vbuf.src[i+k].len;
  1388. creq->vbuf.src[k].vaddr =
  1389. creq->vbuf.src[i+k].vaddr;
  1390. }
  1391. creq->entries = num_entries;
  1392. i = j;
  1393. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1394. &di, handle, k_align_src);
  1395. if (err < 0) {
  1396. memset(saved_req, 0,
  1397. ksize((void *)saved_req));
  1398. memset(k_buf_src, 0,
  1399. ksize((void *)k_buf_src));
  1400. kfree(k_buf_src);
  1401. kfree(saved_req);
  1402. return err;
  1403. }
  1404. num_entries = 0;
  1405. areq->cipher_op_req.byteoffset = 0;
  1406. creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
  1407. + creq->vbuf.src[i].len;
  1408. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1409. creq->vbuf.src[i].len;
  1410. req.vbuf.src[i].vaddr =
  1411. creq->vbuf.src[i].vaddr;
  1412. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1413. if (creq->vbuf.src[i].len == 0)
  1414. i++;
  1415. }
  1416. areq->cipher_op_req.byteoffset = 0;
  1417. max_data_xfer = QCE_MAX_OPER_DATA;
  1418. byteoffset = 0;
  1419. } /* end of while ((i < req.entries) && (err == 0)) */
  1420. } else
  1421. err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
  1422. k_align_src);
  1423. /* Restore the original req structure */
  1424. for (i = 0; i < saved_req->entries; i++) {
  1425. creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
  1426. creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
  1427. }
  1428. for (len = 0, i = 0; len < saved_req->data_len; i++) {
  1429. creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
  1430. creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
  1431. len += saved_req->vbuf.dst[i].len;
  1432. }
  1433. creq->entries = saved_req->entries;
  1434. creq->data_len = saved_req->data_len;
  1435. creq->byteoffset = saved_req->byteoffset;
  1436. memset(saved_req, 0, ksize((void *)saved_req));
  1437. memset(k_buf_src, 0, ksize((void *)k_buf_src));
  1438. kfree(saved_req);
  1439. kfree(k_buf_src);
  1440. return err;
  1441. }
  1442. static int qcedev_smmu_ablk_offload_cipher(struct qcedev_async_req *areq,
  1443. struct qcedev_handle *handle)
  1444. {
  1445. int i = 0;
  1446. int err = 0;
  1447. size_t byteoffset = 0;
  1448. size_t transfer_data_len = 0;
  1449. size_t pending_data_len = 0;
  1450. size_t max_data_xfer = MAX_CEHW_REQ_TRANSFER_SIZE - byteoffset;
  1451. uint8_t *user_src = NULL;
  1452. uint8_t *user_dst = NULL;
  1453. struct scatterlist sg_src;
  1454. struct scatterlist sg_dst;
  1455. if (areq->offload_cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1456. byteoffset = areq->offload_cipher_op_req.byteoffset;
  1457. /*
  1458. * areq has two components:
  1459. * a) Request that comes from userspace i.e. offload_cipher_op_req
  1460. * b) Request that QCE understands - skcipher i.e. cipher_req.creq
  1461. * skcipher has sglist pointers src and dest that would carry
  1462. * data to/from CE.
  1463. */
  1464. areq->cipher_req.creq.src = &sg_src;
  1465. areq->cipher_req.creq.dst = &sg_dst;
  1466. sg_init_table(&sg_src, 1);
  1467. sg_init_table(&sg_dst, 1);
  1468. for (i = 0; i < areq->offload_cipher_op_req.entries; i++) {
  1469. transfer_data_len = 0;
  1470. pending_data_len = areq->offload_cipher_op_req.vbuf.src[i].len;
  1471. user_src = areq->offload_cipher_op_req.vbuf.src[i].vaddr;
  1472. user_src += byteoffset;
  1473. user_dst = areq->offload_cipher_op_req.vbuf.dst[i].vaddr;
  1474. user_dst += byteoffset;
  1475. areq->cipher_req.creq.iv = areq->offload_cipher_op_req.iv;
  1476. while (pending_data_len) {
  1477. transfer_data_len = min(max_data_xfer,
  1478. pending_data_len);
  1479. sg_src.dma_address = (dma_addr_t)user_src;
  1480. sg_dst.dma_address = (dma_addr_t)user_dst;
  1481. areq->cipher_req.creq.cryptlen = transfer_data_len;
  1482. sg_src.length = transfer_data_len;
  1483. sg_dst.length = transfer_data_len;
  1484. err = submit_req(areq, handle);
  1485. if (err) {
  1486. pr_err("%s: Error processing req, err = %d\n",
  1487. __func__, err);
  1488. goto exit;
  1489. }
  1490. /* update data len to be processed */
  1491. pending_data_len -= transfer_data_len;
  1492. user_src += transfer_data_len;
  1493. user_dst += transfer_data_len;
  1494. }
  1495. }
  1496. exit:
  1497. return err;
  1498. }
  1499. static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
  1500. struct qcedev_control *podev)
  1501. {
  1502. /* if intending to use HW key make sure key fields are set
  1503. * correctly and HW key is indeed supported in target
  1504. */
  1505. if (req->encklen == 0) {
  1506. int i;
  1507. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  1508. if (req->enckey[i]) {
  1509. pr_err("%s: Invalid key: non-zero key input\n",
  1510. __func__);
  1511. goto error;
  1512. }
  1513. }
  1514. if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
  1515. (req->op != QCEDEV_OPER_DEC_NO_KEY))
  1516. if (!podev->platform_support.hw_key_support) {
  1517. pr_err("%s: Invalid op %d\n", __func__,
  1518. (uint32_t)req->op);
  1519. goto error;
  1520. }
  1521. } else {
  1522. if (req->encklen == QCEDEV_AES_KEY_192) {
  1523. if (!podev->ce_support.aes_key_192) {
  1524. pr_err("%s: AES-192 not supported\n", __func__);
  1525. goto error;
  1526. }
  1527. } else {
  1528. /* if not using HW key make sure key
  1529. * length is valid
  1530. */
  1531. if (req->mode == QCEDEV_AES_MODE_XTS) {
  1532. if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
  1533. (req->encklen != QCEDEV_AES_KEY_256*2)) {
  1534. pr_err("%s: unsupported key size: %d\n",
  1535. __func__, req->encklen);
  1536. goto error;
  1537. }
  1538. } else {
  1539. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1540. (req->encklen != QCEDEV_AES_KEY_256)) {
  1541. pr_err("%s: unsupported key size %d\n",
  1542. __func__, req->encklen);
  1543. goto error;
  1544. }
  1545. }
  1546. }
  1547. }
  1548. return 0;
  1549. error:
  1550. return -EINVAL;
  1551. }
  1552. static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
  1553. struct qcedev_control *podev)
  1554. {
  1555. uint32_t total = 0;
  1556. uint32_t i;
  1557. if (req->use_pmem) {
  1558. pr_err("%s: Use of PMEM is not supported\n", __func__);
  1559. goto error;
  1560. }
  1561. if ((req->entries == 0) || (req->data_len == 0) ||
  1562. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1563. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1564. goto error;
  1565. }
  1566. if ((req->alg >= QCEDEV_ALG_LAST) ||
  1567. (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
  1568. pr_err("%s: Invalid algorithm %d\n", __func__,
  1569. (uint32_t)req->alg);
  1570. goto error;
  1571. }
  1572. if ((req->mode == QCEDEV_AES_MODE_XTS) &&
  1573. (!podev->ce_support.aes_xts)) {
  1574. pr_err("%s: XTS algorithm is not supported\n", __func__);
  1575. goto error;
  1576. }
  1577. if (req->alg == QCEDEV_ALG_AES) {
  1578. if (qcedev_check_cipher_key(req, podev))
  1579. goto error;
  1580. }
  1581. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1582. if (req->byteoffset) {
  1583. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1584. pr_err("%s: Operation on byte offset not supported\n",
  1585. __func__);
  1586. goto error;
  1587. }
  1588. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1589. pr_err("%s: Invalid byte offset\n", __func__);
  1590. goto error;
  1591. }
  1592. total = req->byteoffset;
  1593. for (i = 0; i < req->entries; i++) {
  1594. if (total > U32_MAX - req->vbuf.src[i].len) {
  1595. pr_err("%s:Integer overflow on total src len\n",
  1596. __func__);
  1597. goto error;
  1598. }
  1599. total += req->vbuf.src[i].len;
  1600. }
  1601. }
  1602. if (req->data_len < req->byteoffset) {
  1603. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1604. __func__, req->data_len, req->byteoffset);
  1605. goto error;
  1606. }
  1607. /* Ensure IV size */
  1608. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1609. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1610. goto error;
  1611. }
  1612. /* Ensure Key size */
  1613. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1614. pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
  1615. goto error;
  1616. }
  1617. /* Ensure zer ivlen for ECB mode */
  1618. if (req->ivlen > 0) {
  1619. if ((req->mode == QCEDEV_AES_MODE_ECB) ||
  1620. (req->mode == QCEDEV_DES_MODE_ECB)) {
  1621. pr_err("%s: Expecting a zero length IV\n", __func__);
  1622. goto error;
  1623. }
  1624. } else {
  1625. if ((req->mode != QCEDEV_AES_MODE_ECB) &&
  1626. (req->mode != QCEDEV_DES_MODE_ECB)) {
  1627. pr_err("%s: Expecting a non-zero ength IV\n", __func__);
  1628. goto error;
  1629. }
  1630. }
  1631. /* Check for sum of all dst length is equal to data_len */
  1632. for (i = 0, total = 0; i < req->entries; i++) {
  1633. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1634. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1635. __func__, i, req->vbuf.dst[i].len);
  1636. goto error;
  1637. }
  1638. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1639. pr_err("%s: Integer overflow on total req dst vbuf length\n",
  1640. __func__);
  1641. goto error;
  1642. }
  1643. total += req->vbuf.dst[i].len;
  1644. }
  1645. if (total != req->data_len) {
  1646. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1647. __func__, i, total, req->data_len);
  1648. goto error;
  1649. }
  1650. /* Check for sum of all src length is equal to data_len */
  1651. for (i = 0, total = 0; i < req->entries; i++) {
  1652. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1653. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1654. __func__, i, req->vbuf.src[i].len);
  1655. goto error;
  1656. }
  1657. if (req->vbuf.src[i].len > U32_MAX - total) {
  1658. pr_err("%s: Integer overflow on total req src vbuf length\n",
  1659. __func__);
  1660. goto error;
  1661. }
  1662. total += req->vbuf.src[i].len;
  1663. }
  1664. if (total != req->data_len) {
  1665. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1666. __func__, total, req->data_len);
  1667. goto error;
  1668. }
  1669. return 0;
  1670. error:
  1671. return -EINVAL;
  1672. }
  1673. static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
  1674. struct qcedev_control *podev)
  1675. {
  1676. uint32_t total = 0;
  1677. uint32_t i;
  1678. if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
  1679. (!podev->ce_support.cmac)) {
  1680. pr_err("%s: CMAC not supported\n", __func__);
  1681. goto sha_error;
  1682. }
  1683. if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
  1684. pr_err("%s: Invalid num entries (%d)\n",
  1685. __func__, req->entries);
  1686. goto sha_error;
  1687. }
  1688. if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
  1689. pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
  1690. goto sha_error;
  1691. }
  1692. if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
  1693. (req->alg == QCEDEV_ALG_SHA256_HMAC)) {
  1694. if (req->authkey == NULL) {
  1695. pr_err("%s: Invalid authkey pointer\n", __func__);
  1696. goto sha_error;
  1697. }
  1698. if (req->authklen <= 0) {
  1699. pr_err("%s: Invalid authkey length (%d)\n",
  1700. __func__, req->authklen);
  1701. goto sha_error;
  1702. }
  1703. }
  1704. if (req->alg == QCEDEV_ALG_AES_CMAC) {
  1705. if ((req->authklen != QCEDEV_AES_KEY_128) &&
  1706. (req->authklen != QCEDEV_AES_KEY_256)) {
  1707. pr_err("%s: unsupported key length\n", __func__);
  1708. goto sha_error;
  1709. }
  1710. }
  1711. /* Check for sum of all src length is equal to data_len */
  1712. for (i = 0, total = 0; i < req->entries; i++) {
  1713. if (req->data[i].len > U32_MAX - total) {
  1714. pr_err("%s: Integer overflow on total req buf length\n",
  1715. __func__);
  1716. goto sha_error;
  1717. }
  1718. total += req->data[i].len;
  1719. }
  1720. if (total != req->data_len) {
  1721. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1722. __func__, total, req->data_len);
  1723. goto sha_error;
  1724. }
  1725. return 0;
  1726. sha_error:
  1727. return -EINVAL;
  1728. }
  1729. static int qcedev_check_offload_cipher_key(struct qcedev_offload_cipher_op_req *req,
  1730. struct qcedev_control *podev)
  1731. {
  1732. if (req->encklen == 0)
  1733. return -EINVAL;
  1734. /* AES-192 is not a valid option for OFFLOAD use case */
  1735. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1736. (req->encklen != QCEDEV_AES_KEY_256)) {
  1737. pr_err("%s: unsupported key size %d\n",
  1738. __func__, req->encklen);
  1739. goto error;
  1740. }
  1741. return 0;
  1742. error:
  1743. return -EINVAL;
  1744. }
  1745. static int qcedev_check_offload_cipher_params(struct qcedev_offload_cipher_op_req *req,
  1746. struct qcedev_control *podev)
  1747. {
  1748. uint32_t total = 0;
  1749. int i = 0;
  1750. if ((req->entries == 0) || (req->data_len == 0) ||
  1751. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1752. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1753. goto error;
  1754. }
  1755. if ((req->alg != QCEDEV_ALG_AES) ||
  1756. (req->mode > QCEDEV_AES_MODE_CTR)) {
  1757. pr_err("%s: Invalid algorithm %d\n", __func__,
  1758. (uint32_t)req->alg);
  1759. goto error;
  1760. }
  1761. if (qcedev_check_offload_cipher_key(req, podev))
  1762. goto error;
  1763. if (req->block_offset >= AES_CE_BLOCK_SIZE)
  1764. goto error;
  1765. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1766. if (req->byteoffset) {
  1767. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1768. pr_err("%s: Operation on byte offset not supported\n",
  1769. __func__);
  1770. goto error;
  1771. }
  1772. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1773. pr_err("%s: Invalid byte offset\n", __func__);
  1774. goto error;
  1775. }
  1776. total = req->byteoffset;
  1777. for (i = 0; i < req->entries; i++) {
  1778. if (total > U32_MAX - req->vbuf.src[i].len) {
  1779. pr_err("%s:Int overflow on total src len\n",
  1780. __func__);
  1781. goto error;
  1782. }
  1783. total += req->vbuf.src[i].len;
  1784. }
  1785. }
  1786. if (req->data_len < req->byteoffset) {
  1787. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1788. __func__, req->data_len, req->byteoffset);
  1789. goto error;
  1790. }
  1791. /* Ensure IV size */
  1792. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1793. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1794. goto error;
  1795. }
  1796. /* Ensure Key size */
  1797. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1798. pr_err("%s: Klen is not correct: %u\n", __func__,
  1799. req->encklen);
  1800. goto error;
  1801. }
  1802. /* Check for sum of all dst length is equal to data_len */
  1803. for (i = 0, total = 0; i < req->entries; i++) {
  1804. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1805. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1806. __func__, i, req->vbuf.dst[i].len);
  1807. goto error;
  1808. }
  1809. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1810. pr_err("%s: Int overflow on total req dst vbuf len\n",
  1811. __func__);
  1812. goto error;
  1813. }
  1814. total += req->vbuf.dst[i].len;
  1815. }
  1816. if (total != req->data_len) {
  1817. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1818. __func__, i, total, req->data_len);
  1819. goto error;
  1820. }
  1821. /* Check for sum of all src length is equal to data_len */
  1822. for (i = 0, total = 0; i < req->entries; i++) {
  1823. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1824. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1825. __func__, i, req->vbuf.src[i].len);
  1826. goto error;
  1827. }
  1828. if (req->vbuf.src[i].len > U32_MAX - total) {
  1829. pr_err("%s: Int overflow on total req src vbuf len\n",
  1830. __func__);
  1831. goto error;
  1832. }
  1833. total += req->vbuf.src[i].len;
  1834. }
  1835. if (total != req->data_len) {
  1836. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1837. __func__, total, req->data_len);
  1838. goto error;
  1839. }
  1840. return 0;
  1841. error:
  1842. return -EINVAL;
  1843. }
  1844. long qcedev_ioctl(struct file *file,
  1845. unsigned int cmd, unsigned long arg)
  1846. {
  1847. int err = 0;
  1848. struct qcedev_handle *handle;
  1849. struct qcedev_control *podev;
  1850. struct qcedev_async_req *qcedev_areq;
  1851. struct qcedev_stat *pstat;
  1852. qcedev_areq = kzalloc(sizeof(struct qcedev_async_req), GFP_KERNEL);
  1853. if (!qcedev_areq)
  1854. return -ENOMEM;
  1855. handle = file->private_data;
  1856. podev = handle->cntl;
  1857. qcedev_areq->handle = handle;
  1858. if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
  1859. pr_err("%s: invalid handle %pK\n",
  1860. __func__, podev);
  1861. err = -ENOENT;
  1862. goto exit_free_qcedev_areq;
  1863. }
  1864. /* Verify user arguments. */
  1865. if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC) {
  1866. err = -ENOTTY;
  1867. goto exit_free_qcedev_areq;
  1868. }
  1869. init_completion(&qcedev_areq->complete);
  1870. pstat = &_qcedev_stat;
  1871. switch (cmd) {
  1872. case QCEDEV_IOCTL_ENC_REQ:
  1873. case QCEDEV_IOCTL_DEC_REQ:
  1874. if (copy_from_user(&qcedev_areq->cipher_op_req,
  1875. (void __user *)arg,
  1876. sizeof(struct qcedev_cipher_op_req))) {
  1877. err = -EFAULT;
  1878. goto exit_free_qcedev_areq;
  1879. }
  1880. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_CIPHER;
  1881. if (qcedev_check_cipher_params(&qcedev_areq->cipher_op_req,
  1882. podev)) {
  1883. err = -EINVAL;
  1884. goto exit_free_qcedev_areq;
  1885. }
  1886. err = qcedev_vbuf_ablk_cipher(qcedev_areq, handle);
  1887. if (err)
  1888. goto exit_free_qcedev_areq;
  1889. if (copy_to_user((void __user *)arg,
  1890. &qcedev_areq->cipher_op_req,
  1891. sizeof(struct qcedev_cipher_op_req))) {
  1892. err = -EFAULT;
  1893. goto exit_free_qcedev_areq;
  1894. }
  1895. break;
  1896. case QCEDEV_IOCTL_OFFLOAD_OP_REQ:
  1897. if (copy_from_user(&qcedev_areq->offload_cipher_op_req,
  1898. (void __user *)arg,
  1899. sizeof(struct qcedev_offload_cipher_op_req))) {
  1900. err = -EFAULT;
  1901. goto exit_free_qcedev_areq;
  1902. }
  1903. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER;
  1904. if (qcedev_check_offload_cipher_params(
  1905. &qcedev_areq->offload_cipher_op_req, podev)) {
  1906. err = -EINVAL;
  1907. goto exit_free_qcedev_areq;
  1908. }
  1909. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  1910. err = qcedev_smmu_ablk_offload_cipher(qcedev_areq, handle);
  1911. if (err)
  1912. goto exit_free_qcedev_areq;
  1913. if (copy_to_user((void __user *)arg,
  1914. &qcedev_areq->offload_cipher_op_req,
  1915. sizeof(struct qcedev_offload_cipher_op_req))) {
  1916. err = -EFAULT;
  1917. goto exit_free_qcedev_areq;
  1918. }
  1919. break;
  1920. case QCEDEV_IOCTL_SHA_INIT_REQ:
  1921. {
  1922. struct scatterlist sg_src;
  1923. if (copy_from_user(&qcedev_areq->sha_op_req,
  1924. (void __user *)arg,
  1925. sizeof(struct qcedev_sha_op_req))) {
  1926. err = -EFAULT;
  1927. goto exit_free_qcedev_areq;
  1928. }
  1929. mutex_lock(&hash_access_lock);
  1930. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1931. mutex_unlock(&hash_access_lock);
  1932. err = -EINVAL;
  1933. goto exit_free_qcedev_areq;
  1934. }
  1935. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1936. err = qcedev_hash_init(qcedev_areq, handle, &sg_src);
  1937. if (err) {
  1938. mutex_unlock(&hash_access_lock);
  1939. goto exit_free_qcedev_areq;
  1940. }
  1941. mutex_unlock(&hash_access_lock);
  1942. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  1943. sizeof(struct qcedev_sha_op_req))) {
  1944. err = -EFAULT;
  1945. goto exit_free_qcedev_areq;
  1946. }
  1947. handle->sha_ctxt.init_done = true;
  1948. }
  1949. break;
  1950. case QCEDEV_IOCTL_GET_CMAC_REQ:
  1951. if (!podev->ce_support.cmac) {
  1952. err = -ENOTTY;
  1953. goto exit_free_qcedev_areq;
  1954. }
  1955. /* Fall-through */
  1956. case QCEDEV_IOCTL_SHA_UPDATE_REQ:
  1957. {
  1958. struct scatterlist sg_src;
  1959. if (copy_from_user(&qcedev_areq->sha_op_req,
  1960. (void __user *)arg,
  1961. sizeof(struct qcedev_sha_op_req))) {
  1962. err = -EFAULT;
  1963. goto exit_free_qcedev_areq;
  1964. }
  1965. mutex_lock(&hash_access_lock);
  1966. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1967. mutex_unlock(&hash_access_lock);
  1968. err = -EINVAL;
  1969. goto exit_free_qcedev_areq;
  1970. }
  1971. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1972. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
  1973. err = qcedev_hash_cmac(qcedev_areq, handle, &sg_src);
  1974. if (err) {
  1975. mutex_unlock(&hash_access_lock);
  1976. goto exit_free_qcedev_areq;
  1977. }
  1978. } else {
  1979. if (!handle->sha_ctxt.init_done) {
  1980. pr_err("%s Init was not called\n", __func__);
  1981. mutex_unlock(&hash_access_lock);
  1982. err = -EINVAL;
  1983. goto exit_free_qcedev_areq;
  1984. }
  1985. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  1986. if (err) {
  1987. mutex_unlock(&hash_access_lock);
  1988. goto exit_free_qcedev_areq;
  1989. }
  1990. }
  1991. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  1992. pr_err("Invalid sha_ctxt.diglen %d\n",
  1993. handle->sha_ctxt.diglen);
  1994. mutex_unlock(&hash_access_lock);
  1995. err = -EINVAL;
  1996. goto exit_free_qcedev_areq;
  1997. }
  1998. memcpy(&qcedev_areq->sha_op_req.digest[0],
  1999. &handle->sha_ctxt.digest[0],
  2000. handle->sha_ctxt.diglen);
  2001. mutex_unlock(&hash_access_lock);
  2002. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2003. sizeof(struct qcedev_sha_op_req))) {
  2004. err = -EFAULT;
  2005. goto exit_free_qcedev_areq;
  2006. }
  2007. }
  2008. break;
  2009. case QCEDEV_IOCTL_SHA_FINAL_REQ:
  2010. if (!handle->sha_ctxt.init_done) {
  2011. pr_err("%s Init was not called\n", __func__);
  2012. err = -EINVAL;
  2013. goto exit_free_qcedev_areq;
  2014. }
  2015. if (copy_from_user(&qcedev_areq->sha_op_req,
  2016. (void __user *)arg,
  2017. sizeof(struct qcedev_sha_op_req))) {
  2018. err = -EFAULT;
  2019. goto exit_free_qcedev_areq;
  2020. }
  2021. mutex_lock(&hash_access_lock);
  2022. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2023. mutex_unlock(&hash_access_lock);
  2024. err = -EINVAL;
  2025. goto exit_free_qcedev_areq;
  2026. }
  2027. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2028. err = qcedev_hash_final(qcedev_areq, handle);
  2029. if (err) {
  2030. mutex_unlock(&hash_access_lock);
  2031. goto exit_free_qcedev_areq;
  2032. }
  2033. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2034. pr_err("Invalid sha_ctxt.diglen %d\n",
  2035. handle->sha_ctxt.diglen);
  2036. mutex_unlock(&hash_access_lock);
  2037. err = -EINVAL;
  2038. goto exit_free_qcedev_areq;
  2039. }
  2040. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2041. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2042. &handle->sha_ctxt.digest[0],
  2043. handle->sha_ctxt.diglen);
  2044. mutex_unlock(&hash_access_lock);
  2045. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2046. sizeof(struct qcedev_sha_op_req))) {
  2047. err = -EFAULT;
  2048. goto exit_free_qcedev_areq;
  2049. }
  2050. handle->sha_ctxt.init_done = false;
  2051. break;
  2052. case QCEDEV_IOCTL_GET_SHA_REQ:
  2053. {
  2054. struct scatterlist sg_src;
  2055. if (copy_from_user(&qcedev_areq->sha_op_req,
  2056. (void __user *)arg,
  2057. sizeof(struct qcedev_sha_op_req))) {
  2058. err = -EFAULT;
  2059. goto exit_free_qcedev_areq;
  2060. }
  2061. mutex_lock(&hash_access_lock);
  2062. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2063. mutex_unlock(&hash_access_lock);
  2064. err = -EINVAL;
  2065. goto exit_free_qcedev_areq;
  2066. }
  2067. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2068. qcedev_hash_init(qcedev_areq, handle, &sg_src);
  2069. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2070. if (err) {
  2071. mutex_unlock(&hash_access_lock);
  2072. goto exit_free_qcedev_areq;
  2073. }
  2074. err = qcedev_hash_final(qcedev_areq, handle);
  2075. if (err) {
  2076. mutex_unlock(&hash_access_lock);
  2077. goto exit_free_qcedev_areq;
  2078. }
  2079. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2080. pr_err("Invalid sha_ctxt.diglen %d\n",
  2081. handle->sha_ctxt.diglen);
  2082. mutex_unlock(&hash_access_lock);
  2083. err = -EINVAL;
  2084. goto exit_free_qcedev_areq;
  2085. }
  2086. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2087. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2088. &handle->sha_ctxt.digest[0],
  2089. handle->sha_ctxt.diglen);
  2090. mutex_unlock(&hash_access_lock);
  2091. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2092. sizeof(struct qcedev_sha_op_req))) {
  2093. err = -EFAULT;
  2094. goto exit_free_qcedev_areq;
  2095. }
  2096. }
  2097. break;
  2098. case QCEDEV_IOCTL_MAP_BUF_REQ:
  2099. {
  2100. unsigned long long vaddr = 0;
  2101. struct qcedev_map_buf_req map_buf = { {0} };
  2102. int i = 0;
  2103. if (copy_from_user(&map_buf,
  2104. (void __user *)arg, sizeof(map_buf))) {
  2105. err = -EFAULT;
  2106. goto exit_free_qcedev_areq;
  2107. }
  2108. if (map_buf.num_fds > QCEDEV_MAX_BUFFERS) {
  2109. err = -EINVAL;
  2110. goto exit_free_qcedev_areq;
  2111. }
  2112. for (i = 0; i < map_buf.num_fds; i++) {
  2113. err = qcedev_check_and_map_buffer(handle,
  2114. map_buf.fd[i],
  2115. map_buf.fd_offset[i],
  2116. map_buf.fd_size[i],
  2117. &vaddr);
  2118. if (err) {
  2119. pr_err(
  2120. "%s: err: failed to map fd(%d) - %d\n",
  2121. __func__, map_buf.fd[i], err);
  2122. goto exit_free_qcedev_areq;
  2123. }
  2124. map_buf.buf_vaddr[i] = vaddr;
  2125. pr_info("%s: info: vaddr = %llx\n, fd = %d",
  2126. __func__, vaddr, map_buf.fd[i]);
  2127. }
  2128. if (copy_to_user((void __user *)arg, &map_buf,
  2129. sizeof(map_buf))) {
  2130. err = -EFAULT;
  2131. goto exit_free_qcedev_areq;
  2132. }
  2133. break;
  2134. }
  2135. case QCEDEV_IOCTL_UNMAP_BUF_REQ:
  2136. {
  2137. struct qcedev_unmap_buf_req unmap_buf = { { 0 } };
  2138. int i = 0;
  2139. if (copy_from_user(&unmap_buf,
  2140. (void __user *)arg, sizeof(unmap_buf))) {
  2141. err = -EFAULT;
  2142. goto exit_free_qcedev_areq;
  2143. }
  2144. for (i = 0; i < unmap_buf.num_fds; i++) {
  2145. err = qcedev_check_and_unmap_buffer(handle,
  2146. unmap_buf.fd[i]);
  2147. if (err) {
  2148. pr_err(
  2149. "%s: err: failed to unmap fd(%d) - %d\n",
  2150. __func__,
  2151. unmap_buf.fd[i], err);
  2152. goto exit_free_qcedev_areq;
  2153. }
  2154. }
  2155. break;
  2156. }
  2157. default:
  2158. err = -ENOTTY;
  2159. goto exit_free_qcedev_areq;
  2160. }
  2161. exit_free_qcedev_areq:
  2162. kfree(qcedev_areq);
  2163. return err;
  2164. }
  2165. static int qcedev_probe_device(struct platform_device *pdev)
  2166. {
  2167. void *handle = NULL;
  2168. int rc = 0;
  2169. struct qcedev_control *podev;
  2170. struct msm_ce_hw_support *platform_support;
  2171. podev = &qce_dev[0];
  2172. rc = alloc_chrdev_region(&qcedev_device_no, 0, 1, QCEDEV_DEV);
  2173. if (rc < 0) {
  2174. pr_err("alloc_chrdev_region failed %d\n", rc);
  2175. return rc;
  2176. }
  2177. driver_class = class_create(THIS_MODULE, QCEDEV_DEV);
  2178. if (IS_ERR(driver_class)) {
  2179. rc = -ENOMEM;
  2180. pr_err("class_create failed %d\n", rc);
  2181. goto exit_unreg_chrdev_region;
  2182. }
  2183. class_dev = device_create(driver_class, NULL, qcedev_device_no, NULL,
  2184. QCEDEV_DEV);
  2185. if (IS_ERR(class_dev)) {
  2186. pr_err("class_device_create failed %d\n", rc);
  2187. rc = -ENOMEM;
  2188. goto exit_destroy_class;
  2189. }
  2190. cdev_init(&podev->cdev, &qcedev_fops);
  2191. podev->cdev.owner = THIS_MODULE;
  2192. rc = cdev_add(&podev->cdev, MKDEV(MAJOR(qcedev_device_no), 0), 1);
  2193. if (rc < 0) {
  2194. pr_err("cdev_add failed %d\n", rc);
  2195. goto exit_destroy_device;
  2196. }
  2197. podev->minor = 0;
  2198. podev->high_bw_req_count = 0;
  2199. INIT_LIST_HEAD(&podev->ready_commands);
  2200. podev->active_command = NULL;
  2201. INIT_LIST_HEAD(&podev->context_banks);
  2202. spin_lock_init(&podev->lock);
  2203. tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
  2204. podev->icc_path = of_icc_get(&pdev->dev, "data_path");
  2205. if (IS_ERR(podev->icc_path)) {
  2206. rc = PTR_ERR(podev->icc_path);
  2207. pr_err("%s Failed to get icc path with error %d\n",
  2208. __func__, rc);
  2209. goto exit_del_cdev;
  2210. }
  2211. /*
  2212. * HLOS crypto vote values from DTSI. If no values specified, use
  2213. * nominal values.
  2214. */
  2215. if (of_property_read_u32((&pdev->dev)->of_node,
  2216. "qcom,icc_avg_bw",
  2217. &podev->icc_avg_bw)) {
  2218. pr_warn("%s: No icc avg BW set, using default\n", __func__);
  2219. podev->icc_avg_bw = CRYPTO_AVG_BW;
  2220. }
  2221. if (of_property_read_u32((&pdev->dev)->of_node,
  2222. "qcom,icc_peak_bw",
  2223. &podev->icc_peak_bw)) {
  2224. pr_warn("%s: No icc peak BW set, using default\n", __func__);
  2225. podev->icc_peak_bw = CRYPTO_PEAK_BW;
  2226. }
  2227. rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
  2228. podev->icc_peak_bw);
  2229. if (rc) {
  2230. pr_err("%s Unable to set high bandwidth\n", __func__);
  2231. goto exit_unregister_bus_scale;
  2232. }
  2233. handle = qce_open(pdev, &rc);
  2234. if (handle == NULL) {
  2235. rc = -ENODEV;
  2236. goto exit_scale_busbandwidth;
  2237. }
  2238. rc = icc_set_bw(podev->icc_path, 0, 0);
  2239. if (rc) {
  2240. pr_err("%s Unable to set to low bandwidth\n", __func__);
  2241. goto exit_qce_close;
  2242. }
  2243. podev->qce = handle;
  2244. podev->pdev = pdev;
  2245. platform_set_drvdata(pdev, podev);
  2246. qce_hw_support(podev->qce, &podev->ce_support);
  2247. if (podev->ce_support.bam) {
  2248. podev->platform_support.ce_shared = 0;
  2249. podev->platform_support.shared_ce_resource = 0;
  2250. podev->platform_support.hw_key_support =
  2251. podev->ce_support.hw_key;
  2252. podev->platform_support.sha_hmac = 1;
  2253. } else {
  2254. platform_support =
  2255. (struct msm_ce_hw_support *)pdev->dev.platform_data;
  2256. podev->platform_support.ce_shared = platform_support->ce_shared;
  2257. podev->platform_support.shared_ce_resource =
  2258. platform_support->shared_ce_resource;
  2259. podev->platform_support.hw_key_support =
  2260. platform_support->hw_key_support;
  2261. podev->platform_support.sha_hmac = platform_support->sha_hmac;
  2262. }
  2263. podev->mem_client = qcedev_mem_new_client(MEM_ION);
  2264. if (!podev->mem_client) {
  2265. pr_err("%s: err: qcedev_mem_new_client failed\n", __func__);
  2266. goto exit_qce_close;
  2267. }
  2268. rc = of_platform_populate(pdev->dev.of_node, qcedev_match,
  2269. NULL, &pdev->dev);
  2270. if (rc) {
  2271. pr_err("%s: err: of_platform_populate failed: %d\n",
  2272. __func__, rc);
  2273. goto exit_mem_new_client;
  2274. }
  2275. return 0;
  2276. exit_mem_new_client:
  2277. if (podev->mem_client)
  2278. qcedev_mem_delete_client(podev->mem_client);
  2279. podev->mem_client = NULL;
  2280. exit_qce_close:
  2281. if (handle)
  2282. qce_close(handle);
  2283. exit_scale_busbandwidth:
  2284. icc_set_bw(podev->icc_path, 0, 0);
  2285. exit_unregister_bus_scale:
  2286. if (podev->icc_path)
  2287. icc_put(podev->icc_path);
  2288. exit_del_cdev:
  2289. cdev_del(&podev->cdev);
  2290. exit_destroy_device:
  2291. device_destroy(driver_class, qcedev_device_no);
  2292. exit_destroy_class:
  2293. class_destroy(driver_class);
  2294. exit_unreg_chrdev_region:
  2295. unregister_chrdev_region(qcedev_device_no, 1);
  2296. podev->icc_path = NULL;
  2297. platform_set_drvdata(pdev, NULL);
  2298. podev->pdev = NULL;
  2299. podev->qce = NULL;
  2300. return rc;
  2301. }
  2302. static int qcedev_probe(struct platform_device *pdev)
  2303. {
  2304. if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcedev"))
  2305. return qcedev_probe_device(pdev);
  2306. else if (of_device_is_compatible(pdev->dev.of_node,
  2307. "qcom,qcedev,context-bank"))
  2308. return qcedev_parse_context_bank(pdev);
  2309. return -EINVAL;
  2310. };
  2311. static int qcedev_remove(struct platform_device *pdev)
  2312. {
  2313. struct qcedev_control *podev;
  2314. podev = platform_get_drvdata(pdev);
  2315. if (!podev)
  2316. return 0;
  2317. if (podev->qce)
  2318. qce_close(podev->qce);
  2319. if (podev->icc_path)
  2320. icc_put(podev->icc_path);
  2321. tasklet_kill(&podev->done_tasklet);
  2322. cdev_del(&podev->cdev);
  2323. device_destroy(driver_class, qcedev_device_no);
  2324. class_destroy(driver_class);
  2325. unregister_chrdev_region(qcedev_device_no, 1);
  2326. return 0;
  2327. };
  2328. static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
  2329. {
  2330. struct qcedev_control *podev;
  2331. int ret;
  2332. podev = platform_get_drvdata(pdev);
  2333. if (!podev)
  2334. return 0;
  2335. mutex_lock(&qcedev_sent_bw_req);
  2336. if (podev->high_bw_req_count) {
  2337. ret = qcedev_control_clocks(podev, false);
  2338. if (ret)
  2339. goto suspend_exit;
  2340. }
  2341. suspend_exit:
  2342. mutex_unlock(&qcedev_sent_bw_req);
  2343. return 0;
  2344. }
  2345. static int qcedev_resume(struct platform_device *pdev)
  2346. {
  2347. struct qcedev_control *podev;
  2348. int ret;
  2349. podev = platform_get_drvdata(pdev);
  2350. if (!podev)
  2351. return 0;
  2352. mutex_lock(&qcedev_sent_bw_req);
  2353. if (podev->high_bw_req_count) {
  2354. ret = qcedev_control_clocks(podev, true);
  2355. if (ret)
  2356. goto resume_exit;
  2357. }
  2358. resume_exit:
  2359. mutex_unlock(&qcedev_sent_bw_req);
  2360. return 0;
  2361. }
  2362. static struct platform_driver qcedev_plat_driver = {
  2363. .probe = qcedev_probe,
  2364. .remove = qcedev_remove,
  2365. .suspend = qcedev_suspend,
  2366. .resume = qcedev_resume,
  2367. .driver = {
  2368. .name = "qce",
  2369. .of_match_table = qcedev_match,
  2370. },
  2371. };
  2372. static int _disp_stats(int id)
  2373. {
  2374. struct qcedev_stat *pstat;
  2375. int len = 0;
  2376. pstat = &_qcedev_stat;
  2377. len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
  2378. "\nQTI QCE dev driver %d Statistics:\n",
  2379. id + 1);
  2380. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2381. " Encryption operation success : %d\n",
  2382. pstat->qcedev_enc_success);
  2383. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2384. " Encryption operation fail : %d\n",
  2385. pstat->qcedev_enc_fail);
  2386. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2387. " Decryption operation success : %d\n",
  2388. pstat->qcedev_dec_success);
  2389. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2390. " Encryption operation fail : %d\n",
  2391. pstat->qcedev_dec_fail);
  2392. return len;
  2393. }
  2394. static ssize_t _debug_stats_read(struct file *file, char __user *buf,
  2395. size_t count, loff_t *ppos)
  2396. {
  2397. ssize_t rc = -EINVAL;
  2398. int qcedev = *((int *) file->private_data);
  2399. int len;
  2400. len = _disp_stats(qcedev);
  2401. if (len <= count)
  2402. rc = simple_read_from_buffer((void __user *) buf, len,
  2403. ppos, (void *) _debug_read_buf, len);
  2404. return rc;
  2405. }
  2406. static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
  2407. size_t count, loff_t *ppos)
  2408. {
  2409. memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
  2410. return count;
  2411. };
  2412. static const struct file_operations _debug_stats_ops = {
  2413. .open = simple_open,
  2414. .read = _debug_stats_read,
  2415. .write = _debug_stats_write,
  2416. };
  2417. static int _qcedev_debug_init(void)
  2418. {
  2419. int rc;
  2420. char name[DEBUG_MAX_FNAME];
  2421. struct dentry *dent;
  2422. _debug_dent = debugfs_create_dir("qcedev", NULL);
  2423. if (IS_ERR(_debug_dent)) {
  2424. pr_debug("qcedev debugfs_create_dir fail, error %ld\n",
  2425. PTR_ERR(_debug_dent));
  2426. return PTR_ERR(_debug_dent);
  2427. }
  2428. snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
  2429. _debug_qcedev = 0;
  2430. dent = debugfs_create_file(name, 0644, _debug_dent,
  2431. &_debug_qcedev, &_debug_stats_ops);
  2432. if (dent == NULL) {
  2433. pr_debug("qcedev debugfs_create_file fail, error %ld\n",
  2434. PTR_ERR(dent));
  2435. rc = PTR_ERR(dent);
  2436. goto err;
  2437. }
  2438. return 0;
  2439. err:
  2440. debugfs_remove_recursive(_debug_dent);
  2441. return rc;
  2442. }
  2443. static int qcedev_init(void)
  2444. {
  2445. _qcedev_debug_init();
  2446. return platform_driver_register(&qcedev_plat_driver);
  2447. }
  2448. static void qcedev_exit(void)
  2449. {
  2450. debugfs_remove_recursive(_debug_dent);
  2451. platform_driver_unregister(&qcedev_plat_driver);
  2452. }
  2453. MODULE_LICENSE("GPL v2");
  2454. MODULE_DESCRIPTION("QTI DEV Crypto driver");
  2455. module_init(qcedev_init);
  2456. module_exit(qcedev_exit);