dp_tx.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include "qdf_module.h"
  30. #include <wlan_cfg.h>
  31. #include "dp_ipa.h"
  32. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  33. #include "if_meta_hdr.h"
  34. #endif
  35. #include "enet.h"
  36. #include "dp_internal.h"
  37. #ifdef ATH_SUPPORT_IQUE
  38. #include "dp_txrx_me.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  42. #include <dp_swlm.h>
  43. #endif
  44. #ifdef WIFI_MONITOR_SUPPORT
  45. #include <dp_mon.h>
  46. #endif
  47. #ifdef FEATURE_WDS
  48. #include "dp_txrx_wds.h"
  49. #endif
  50. /* Flag to skip CCE classify when mesh or tid override enabled */
  51. #define DP_TX_SKIP_CCE_CLASSIFY \
  52. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  53. /* TODO Add support in TSO */
  54. #define DP_DESC_NUM_FRAG(x) 0
  55. /* disable TQM_BYPASS */
  56. #define TQM_BYPASS_WAR 0
  57. /* invalid peer id for reinject*/
  58. #define DP_INVALID_PEER 0XFFFE
  59. /*mapping between hal encrypt type and cdp_sec_type*/
  60. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  61. HAL_TX_ENCRYPT_TYPE_WEP_128,
  62. HAL_TX_ENCRYPT_TYPE_WEP_104,
  63. HAL_TX_ENCRYPT_TYPE_WEP_40,
  64. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  65. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  67. HAL_TX_ENCRYPT_TYPE_WAPI,
  68. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  70. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  71. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  72. qdf_export_symbol(sec_type_map);
  73. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  74. /**
  75. * dp_update_tx_desc_stats - Update the increase or decrease in
  76. * outstanding tx desc count
  77. * values on pdev and soc
  78. * @vdev: DP pdev handle
  79. *
  80. * Return: void
  81. */
  82. static inline void
  83. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  84. {
  85. int32_t tx_descs_cnt =
  86. qdf_atomic_read(&pdev->num_tx_outstanding);
  87. if (pdev->tx_descs_max < tx_descs_cnt)
  88. pdev->tx_descs_max = tx_descs_cnt;
  89. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  90. pdev->tx_descs_max);
  91. }
  92. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  93. static inline void
  94. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  95. {
  96. }
  97. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  98. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  99. static inline
  100. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  101. {
  102. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  103. QDF_DMA_TO_DEVICE,
  104. desc->nbuf->len);
  105. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  106. }
  107. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  108. {
  109. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  110. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  111. QDF_DMA_TO_DEVICE,
  112. desc->nbuf->len);
  113. }
  114. #else
  115. static inline
  116. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  117. {
  118. }
  119. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  120. {
  121. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  122. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  123. }
  124. #endif
  125. #ifdef QCA_TX_LIMIT_CHECK
  126. /**
  127. * dp_tx_limit_check - Check if allocated tx descriptors reached
  128. * soc max limit and pdev max limit
  129. * @vdev: DP vdev handle
  130. *
  131. * Return: true if allocated tx descriptors reached max configured value, else
  132. * false
  133. */
  134. static inline bool
  135. dp_tx_limit_check(struct dp_vdev *vdev)
  136. {
  137. struct dp_pdev *pdev = vdev->pdev;
  138. struct dp_soc *soc = pdev->soc;
  139. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  140. soc->num_tx_allowed) {
  141. dp_tx_info("queued packets are more than max tx, drop the frame");
  142. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  143. return true;
  144. }
  145. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  146. pdev->num_tx_allowed) {
  147. dp_tx_info("queued packets are more than max tx, drop the frame");
  148. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  149. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  150. return true;
  151. }
  152. return false;
  153. }
  154. /**
  155. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  156. * reached soc max limit
  157. * @vdev: DP vdev handle
  158. *
  159. * Return: true if allocated tx descriptors reached max configured value, else
  160. * false
  161. */
  162. static inline bool
  163. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  164. {
  165. struct dp_pdev *pdev = vdev->pdev;
  166. struct dp_soc *soc = pdev->soc;
  167. if (qdf_atomic_read(&soc->num_tx_exception) >=
  168. soc->num_msdu_exception_desc) {
  169. dp_info("exc packets are more than max drop the exc pkt");
  170. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  171. return true;
  172. }
  173. return false;
  174. }
  175. /**
  176. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  177. * @vdev: DP pdev handle
  178. *
  179. * Return: void
  180. */
  181. static inline void
  182. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  183. {
  184. struct dp_soc *soc = pdev->soc;
  185. qdf_atomic_inc(&pdev->num_tx_outstanding);
  186. qdf_atomic_inc(&soc->num_tx_outstanding);
  187. dp_update_tx_desc_stats(pdev);
  188. }
  189. /**
  190. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  191. * @vdev: DP pdev handle
  192. *
  193. * Return: void
  194. */
  195. static inline void
  196. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  197. {
  198. struct dp_soc *soc = pdev->soc;
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. qdf_atomic_dec(&soc->num_tx_outstanding);
  201. dp_update_tx_desc_stats(pdev);
  202. }
  203. #else //QCA_TX_LIMIT_CHECK
  204. static inline bool
  205. dp_tx_limit_check(struct dp_vdev *vdev)
  206. {
  207. return false;
  208. }
  209. static inline bool
  210. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  211. {
  212. return false;
  213. }
  214. static inline void
  215. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  216. {
  217. qdf_atomic_inc(&pdev->num_tx_outstanding);
  218. dp_update_tx_desc_stats(pdev);
  219. }
  220. static inline void
  221. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  222. {
  223. qdf_atomic_dec(&pdev->num_tx_outstanding);
  224. dp_update_tx_desc_stats(pdev);
  225. }
  226. #endif //QCA_TX_LIMIT_CHECK
  227. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  228. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  229. {
  230. enum dp_tx_event_type type;
  231. if (flags & DP_TX_DESC_FLAG_FLUSH)
  232. type = DP_TX_DESC_FLUSH;
  233. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  234. type = DP_TX_COMP_UNMAP_ERR;
  235. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  236. type = DP_TX_COMP_UNMAP;
  237. else
  238. type = DP_TX_DESC_UNMAP;
  239. return type;
  240. }
  241. static inline void
  242. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  243. qdf_nbuf_t skb, uint32_t sw_cookie,
  244. enum dp_tx_event_type type)
  245. {
  246. struct dp_tx_desc_event *entry;
  247. uint32_t idx;
  248. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  249. return;
  250. switch (type) {
  251. case DP_TX_COMP_UNMAP:
  252. case DP_TX_COMP_UNMAP_ERR:
  253. case DP_TX_COMP_MSDU_EXT:
  254. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  255. DP_TX_COMP_HISTORY_SIZE);
  256. entry = &soc->tx_comp_history->entry[idx];
  257. break;
  258. case DP_TX_DESC_MAP:
  259. case DP_TX_DESC_UNMAP:
  260. case DP_TX_DESC_COOKIE:
  261. case DP_TX_DESC_FLUSH:
  262. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  263. DP_TX_TCL_HISTORY_SIZE);
  264. entry = &soc->tx_tcl_history->entry[idx];
  265. break;
  266. default:
  267. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  268. return;
  269. }
  270. entry->skb = skb;
  271. entry->paddr = paddr;
  272. entry->sw_cookie = sw_cookie;
  273. entry->type = type;
  274. entry->ts = qdf_get_log_timestamp();
  275. }
  276. static inline void
  277. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  278. struct qdf_tso_seg_elem_t *tso_seg,
  279. qdf_nbuf_t skb, uint32_t sw_cookie,
  280. enum dp_tx_event_type type)
  281. {
  282. int i;
  283. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  284. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  285. skb, sw_cookie, type);
  286. }
  287. if (!tso_seg->next)
  288. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  289. skb, 0xFFFFFFFF, type);
  290. }
  291. static inline void
  292. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  293. qdf_nbuf_t skb, uint32_t sw_cookie,
  294. enum dp_tx_event_type type)
  295. {
  296. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  297. uint32_t num_segs = tso_info.num_segs;
  298. while (num_segs) {
  299. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  300. curr_seg = curr_seg->next;
  301. num_segs--;
  302. }
  303. }
  304. #else
  305. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  306. {
  307. return DP_TX_DESC_INVAL_EVT;
  308. }
  309. static inline void
  310. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  311. qdf_nbuf_t skb, uint32_t sw_cookie,
  312. enum dp_tx_event_type type)
  313. {
  314. }
  315. static inline void
  316. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *tso_seg,
  318. qdf_nbuf_t skb, uint32_t sw_cookie,
  319. enum dp_tx_event_type type)
  320. {
  321. }
  322. static inline void
  323. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  324. qdf_nbuf_t skb, uint32_t sw_cookie,
  325. enum dp_tx_event_type type)
  326. {
  327. }
  328. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  329. #if defined(FEATURE_TSO)
  330. /**
  331. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  332. *
  333. * @soc - core txrx main context
  334. * @seg_desc - tso segment descriptor
  335. * @num_seg_desc - tso number segment descriptor
  336. */
  337. static void dp_tx_tso_unmap_segment(
  338. struct dp_soc *soc,
  339. struct qdf_tso_seg_elem_t *seg_desc,
  340. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  341. {
  342. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  343. if (qdf_unlikely(!seg_desc)) {
  344. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  345. __func__, __LINE__);
  346. qdf_assert(0);
  347. } else if (qdf_unlikely(!num_seg_desc)) {
  348. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  349. __func__, __LINE__);
  350. qdf_assert(0);
  351. } else {
  352. bool is_last_seg;
  353. /* no tso segment left to do dma unmap */
  354. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  355. return;
  356. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  357. true : false;
  358. qdf_nbuf_unmap_tso_segment(soc->osdev,
  359. seg_desc, is_last_seg);
  360. num_seg_desc->num_seg.tso_cmn_num_seg--;
  361. }
  362. }
  363. /**
  364. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  365. * back to the freelist
  366. *
  367. * @soc - soc device handle
  368. * @tx_desc - Tx software descriptor
  369. */
  370. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  371. struct dp_tx_desc_s *tx_desc)
  372. {
  373. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  374. if (qdf_unlikely(!tx_desc->tso_desc)) {
  375. dp_tx_err("SO desc is NULL!");
  376. qdf_assert(0);
  377. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  378. dp_tx_err("TSO num desc is NULL!");
  379. qdf_assert(0);
  380. } else {
  381. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  382. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  383. /* Add the tso num segment into the free list */
  384. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  385. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  386. tx_desc->tso_num_desc);
  387. tx_desc->tso_num_desc = NULL;
  388. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  389. }
  390. /* Add the tso segment into the free list*/
  391. dp_tx_tso_desc_free(soc,
  392. tx_desc->pool_id, tx_desc->tso_desc);
  393. tx_desc->tso_desc = NULL;
  394. }
  395. }
  396. #else
  397. static void dp_tx_tso_unmap_segment(
  398. struct dp_soc *soc,
  399. struct qdf_tso_seg_elem_t *seg_desc,
  400. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  401. {
  402. }
  403. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  404. struct dp_tx_desc_s *tx_desc)
  405. {
  406. }
  407. #endif
  408. /**
  409. * dp_tx_desc_release() - Release Tx Descriptor
  410. * @tx_desc : Tx Descriptor
  411. * @desc_pool_id: Descriptor Pool ID
  412. *
  413. * Deallocate all resources attached to Tx descriptor and free the Tx
  414. * descriptor.
  415. *
  416. * Return:
  417. */
  418. static void
  419. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  420. {
  421. struct dp_pdev *pdev = tx_desc->pdev;
  422. struct dp_soc *soc;
  423. uint8_t comp_status = 0;
  424. qdf_assert(pdev);
  425. soc = pdev->soc;
  426. dp_tx_outstanding_dec(pdev);
  427. if (tx_desc->frm_type == dp_tx_frm_tso)
  428. dp_tx_tso_desc_release(soc, tx_desc);
  429. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  430. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  431. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  432. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  433. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  434. qdf_atomic_dec(&soc->num_tx_exception);
  435. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  436. tx_desc->buffer_src)
  437. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  438. soc->hal_soc);
  439. else
  440. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  441. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  442. tx_desc->id, comp_status,
  443. qdf_atomic_read(&pdev->num_tx_outstanding));
  444. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  445. return;
  446. }
  447. /**
  448. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  449. * @vdev: DP vdev Handle
  450. * @nbuf: skb
  451. * @msdu_info: msdu_info required to create HTT metadata
  452. *
  453. * Prepares and fills HTT metadata in the frame pre-header for special frames
  454. * that should be transmitted using varying transmit parameters.
  455. * There are 2 VDEV modes that currently needs this special metadata -
  456. * 1) Mesh Mode
  457. * 2) DSRC Mode
  458. *
  459. * Return: HTT metadata size
  460. *
  461. */
  462. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  463. struct dp_tx_msdu_info_s *msdu_info)
  464. {
  465. uint32_t *meta_data = msdu_info->meta_data;
  466. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  467. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  468. uint8_t htt_desc_size;
  469. /* Size rounded of multiple of 8 bytes */
  470. uint8_t htt_desc_size_aligned;
  471. uint8_t *hdr = NULL;
  472. /*
  473. * Metadata - HTT MSDU Extension header
  474. */
  475. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  476. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  477. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  478. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  479. meta_data[0])) {
  480. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  481. htt_desc_size_aligned)) {
  482. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  483. htt_desc_size_aligned);
  484. if (!nbuf) {
  485. /*
  486. * qdf_nbuf_realloc_headroom won't do skb_clone
  487. * as skb_realloc_headroom does. so, no free is
  488. * needed here.
  489. */
  490. DP_STATS_INC(vdev,
  491. tx_i.dropped.headroom_insufficient,
  492. 1);
  493. qdf_print(" %s[%d] skb_realloc_headroom failed",
  494. __func__, __LINE__);
  495. return 0;
  496. }
  497. }
  498. /* Fill and add HTT metaheader */
  499. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  500. if (!hdr) {
  501. dp_tx_err("Error in filling HTT metadata");
  502. return 0;
  503. }
  504. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  505. } else if (vdev->opmode == wlan_op_mode_ocb) {
  506. /* Todo - Add support for DSRC */
  507. }
  508. return htt_desc_size_aligned;
  509. }
  510. /**
  511. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  512. * @tso_seg: TSO segment to process
  513. * @ext_desc: Pointer to MSDU extension descriptor
  514. *
  515. * Return: void
  516. */
  517. #if defined(FEATURE_TSO)
  518. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  519. void *ext_desc)
  520. {
  521. uint8_t num_frag;
  522. uint32_t tso_flags;
  523. /*
  524. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  525. * tcp_flag_mask
  526. *
  527. * Checksum enable flags are set in TCL descriptor and not in Extension
  528. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  529. */
  530. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  531. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  532. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  533. tso_seg->tso_flags.ip_len);
  534. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  535. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  536. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  537. uint32_t lo = 0;
  538. uint32_t hi = 0;
  539. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  540. (tso_seg->tso_frags[num_frag].length));
  541. qdf_dmaaddr_to_32s(
  542. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  543. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  544. tso_seg->tso_frags[num_frag].length);
  545. }
  546. return;
  547. }
  548. #else
  549. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  550. void *ext_desc)
  551. {
  552. return;
  553. }
  554. #endif
  555. #if defined(FEATURE_TSO)
  556. /**
  557. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  558. * allocated and free them
  559. *
  560. * @soc: soc handle
  561. * @free_seg: list of tso segments
  562. * @msdu_info: msdu descriptor
  563. *
  564. * Return - void
  565. */
  566. static void dp_tx_free_tso_seg_list(
  567. struct dp_soc *soc,
  568. struct qdf_tso_seg_elem_t *free_seg,
  569. struct dp_tx_msdu_info_s *msdu_info)
  570. {
  571. struct qdf_tso_seg_elem_t *next_seg;
  572. while (free_seg) {
  573. next_seg = free_seg->next;
  574. dp_tx_tso_desc_free(soc,
  575. msdu_info->tx_queue.desc_pool_id,
  576. free_seg);
  577. free_seg = next_seg;
  578. }
  579. }
  580. /**
  581. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  582. * allocated and free them
  583. *
  584. * @soc: soc handle
  585. * @free_num_seg: list of tso number segments
  586. * @msdu_info: msdu descriptor
  587. * Return - void
  588. */
  589. static void dp_tx_free_tso_num_seg_list(
  590. struct dp_soc *soc,
  591. struct qdf_tso_num_seg_elem_t *free_num_seg,
  592. struct dp_tx_msdu_info_s *msdu_info)
  593. {
  594. struct qdf_tso_num_seg_elem_t *next_num_seg;
  595. while (free_num_seg) {
  596. next_num_seg = free_num_seg->next;
  597. dp_tso_num_seg_free(soc,
  598. msdu_info->tx_queue.desc_pool_id,
  599. free_num_seg);
  600. free_num_seg = next_num_seg;
  601. }
  602. }
  603. /**
  604. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  605. * do dma unmap for each segment
  606. *
  607. * @soc: soc handle
  608. * @free_seg: list of tso segments
  609. * @num_seg_desc: tso number segment descriptor
  610. *
  611. * Return - void
  612. */
  613. static void dp_tx_unmap_tso_seg_list(
  614. struct dp_soc *soc,
  615. struct qdf_tso_seg_elem_t *free_seg,
  616. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  617. {
  618. struct qdf_tso_seg_elem_t *next_seg;
  619. if (qdf_unlikely(!num_seg_desc)) {
  620. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  621. return;
  622. }
  623. while (free_seg) {
  624. next_seg = free_seg->next;
  625. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  626. free_seg = next_seg;
  627. }
  628. }
  629. #ifdef FEATURE_TSO_STATS
  630. /**
  631. * dp_tso_get_stats_idx: Retrieve the tso packet id
  632. * @pdev - pdev handle
  633. *
  634. * Return: id
  635. */
  636. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  637. {
  638. uint32_t stats_idx;
  639. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  640. % CDP_MAX_TSO_PACKETS);
  641. return stats_idx;
  642. }
  643. #else
  644. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  645. {
  646. return 0;
  647. }
  648. #endif /* FEATURE_TSO_STATS */
  649. /**
  650. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  651. * free the tso segments descriptor and
  652. * tso num segments descriptor
  653. *
  654. * @soc: soc handle
  655. * @msdu_info: msdu descriptor
  656. * @tso_seg_unmap: flag to show if dma unmap is necessary
  657. *
  658. * Return - void
  659. */
  660. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  661. struct dp_tx_msdu_info_s *msdu_info,
  662. bool tso_seg_unmap)
  663. {
  664. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  665. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  666. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  667. tso_info->tso_num_seg_list;
  668. /* do dma unmap for each segment */
  669. if (tso_seg_unmap)
  670. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  671. /* free all tso number segment descriptor though looks only have 1 */
  672. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  673. /* free all tso segment descriptor */
  674. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  675. }
  676. /**
  677. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  678. * @vdev: virtual device handle
  679. * @msdu: network buffer
  680. * @msdu_info: meta data associated with the msdu
  681. *
  682. * Return: QDF_STATUS_SUCCESS success
  683. */
  684. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  685. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  686. {
  687. struct qdf_tso_seg_elem_t *tso_seg;
  688. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  689. struct dp_soc *soc = vdev->pdev->soc;
  690. struct dp_pdev *pdev = vdev->pdev;
  691. struct qdf_tso_info_t *tso_info;
  692. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  693. tso_info = &msdu_info->u.tso_info;
  694. tso_info->curr_seg = NULL;
  695. tso_info->tso_seg_list = NULL;
  696. tso_info->num_segs = num_seg;
  697. msdu_info->frm_type = dp_tx_frm_tso;
  698. tso_info->tso_num_seg_list = NULL;
  699. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  700. while (num_seg) {
  701. tso_seg = dp_tx_tso_desc_alloc(
  702. soc, msdu_info->tx_queue.desc_pool_id);
  703. if (tso_seg) {
  704. tso_seg->next = tso_info->tso_seg_list;
  705. tso_info->tso_seg_list = tso_seg;
  706. num_seg--;
  707. } else {
  708. dp_err_rl("Failed to alloc tso seg desc");
  709. DP_STATS_INC_PKT(vdev->pdev,
  710. tso_stats.tso_no_mem_dropped, 1,
  711. qdf_nbuf_len(msdu));
  712. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  713. return QDF_STATUS_E_NOMEM;
  714. }
  715. }
  716. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  717. tso_num_seg = dp_tso_num_seg_alloc(soc,
  718. msdu_info->tx_queue.desc_pool_id);
  719. if (tso_num_seg) {
  720. tso_num_seg->next = tso_info->tso_num_seg_list;
  721. tso_info->tso_num_seg_list = tso_num_seg;
  722. } else {
  723. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  724. __func__);
  725. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  726. return QDF_STATUS_E_NOMEM;
  727. }
  728. msdu_info->num_seg =
  729. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  730. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  731. msdu_info->num_seg);
  732. if (!(msdu_info->num_seg)) {
  733. /*
  734. * Free allocated TSO seg desc and number seg desc,
  735. * do unmap for segments if dma map has done.
  736. */
  737. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  738. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  739. return QDF_STATUS_E_INVAL;
  740. }
  741. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  742. msdu, 0, DP_TX_DESC_MAP);
  743. tso_info->curr_seg = tso_info->tso_seg_list;
  744. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  745. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  746. msdu, msdu_info->num_seg);
  747. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  748. tso_info->msdu_stats_idx);
  749. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  750. return QDF_STATUS_SUCCESS;
  751. }
  752. #else
  753. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  754. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  755. {
  756. return QDF_STATUS_E_NOMEM;
  757. }
  758. #endif
  759. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  760. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  761. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  762. /**
  763. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  764. * @vdev: DP Vdev handle
  765. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  766. * @desc_pool_id: Descriptor Pool ID
  767. *
  768. * Return:
  769. */
  770. static
  771. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  772. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  773. {
  774. uint8_t i;
  775. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  776. struct dp_tx_seg_info_s *seg_info;
  777. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  778. struct dp_soc *soc = vdev->pdev->soc;
  779. /* Allocate an extension descriptor */
  780. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  781. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  782. if (!msdu_ext_desc) {
  783. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  784. return NULL;
  785. }
  786. if (msdu_info->exception_fw &&
  787. qdf_unlikely(vdev->mesh_vdev)) {
  788. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  789. &msdu_info->meta_data[0],
  790. sizeof(struct htt_tx_msdu_desc_ext2_t));
  791. qdf_atomic_inc(&soc->num_tx_exception);
  792. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  793. }
  794. switch (msdu_info->frm_type) {
  795. case dp_tx_frm_sg:
  796. case dp_tx_frm_me:
  797. case dp_tx_frm_raw:
  798. seg_info = msdu_info->u.sg_info.curr_seg;
  799. /* Update the buffer pointers in MSDU Extension Descriptor */
  800. for (i = 0; i < seg_info->frag_cnt; i++) {
  801. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  802. seg_info->frags[i].paddr_lo,
  803. seg_info->frags[i].paddr_hi,
  804. seg_info->frags[i].len);
  805. }
  806. break;
  807. case dp_tx_frm_tso:
  808. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  809. &cached_ext_desc[0]);
  810. break;
  811. default:
  812. break;
  813. }
  814. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  815. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  816. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  817. msdu_ext_desc->vaddr);
  818. return msdu_ext_desc;
  819. }
  820. /**
  821. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  822. *
  823. * @skb: skb to be traced
  824. * @msdu_id: msdu_id of the packet
  825. * @vdev_id: vdev_id of the packet
  826. *
  827. * Return: None
  828. */
  829. #ifdef DP_DISABLE_TX_PKT_TRACE
  830. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  831. uint8_t vdev_id)
  832. {
  833. }
  834. #else
  835. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  836. uint8_t vdev_id)
  837. {
  838. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  839. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  840. DPTRACE(qdf_dp_trace_ptr(skb,
  841. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  842. QDF_TRACE_DEFAULT_PDEV_ID,
  843. qdf_nbuf_data_addr(skb),
  844. sizeof(qdf_nbuf_data(skb)),
  845. msdu_id, vdev_id, 0));
  846. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  847. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  848. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  849. msdu_id, QDF_TX));
  850. }
  851. #endif
  852. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  853. /**
  854. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  855. * exception by the upper layer (OS_IF)
  856. * @soc: DP soc handle
  857. * @nbuf: packet to be transmitted
  858. *
  859. * Returns: 1 if the packet is marked as exception,
  860. * 0, if the packet is not marked as exception.
  861. */
  862. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  863. qdf_nbuf_t nbuf)
  864. {
  865. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  866. }
  867. #else
  868. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  869. qdf_nbuf_t nbuf)
  870. {
  871. return 0;
  872. }
  873. #endif
  874. /**
  875. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  876. * @vdev: DP vdev handle
  877. * @nbuf: skb
  878. * @desc_pool_id: Descriptor pool ID
  879. * @meta_data: Metadata to the fw
  880. * @tx_exc_metadata: Handle that holds exception path metadata
  881. * Allocate and prepare Tx descriptor with msdu information.
  882. *
  883. * Return: Pointer to Tx Descriptor on success,
  884. * NULL on failure
  885. */
  886. static
  887. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  888. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  889. struct dp_tx_msdu_info_s *msdu_info,
  890. struct cdp_tx_exception_metadata *tx_exc_metadata)
  891. {
  892. uint8_t align_pad;
  893. uint8_t is_exception = 0;
  894. uint8_t htt_hdr_size;
  895. struct dp_tx_desc_s *tx_desc;
  896. struct dp_pdev *pdev = vdev->pdev;
  897. struct dp_soc *soc = pdev->soc;
  898. if (dp_tx_limit_check(vdev))
  899. return NULL;
  900. /* Allocate software Tx descriptor */
  901. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  902. if (qdf_unlikely(!tx_desc)) {
  903. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  904. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  905. return NULL;
  906. }
  907. dp_tx_outstanding_inc(pdev);
  908. /* Initialize the SW tx descriptor */
  909. tx_desc->nbuf = nbuf;
  910. tx_desc->frm_type = dp_tx_frm_std;
  911. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  912. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  913. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  914. tx_desc->vdev_id = vdev->vdev_id;
  915. tx_desc->pdev = pdev;
  916. tx_desc->msdu_ext_desc = NULL;
  917. tx_desc->pkt_offset = 0;
  918. tx_desc->length = qdf_nbuf_headlen(nbuf);
  919. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  920. if (qdf_unlikely(vdev->multipass_en)) {
  921. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  922. goto failure;
  923. }
  924. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  925. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  926. is_exception = 1;
  927. /*
  928. * For special modes (vdev_type == ocb or mesh), data frames should be
  929. * transmitted using varying transmit parameters (tx spec) which include
  930. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  931. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  932. * These frames are sent as exception packets to firmware.
  933. *
  934. * HW requirement is that metadata should always point to a
  935. * 8-byte aligned address. So we add alignment pad to start of buffer.
  936. * HTT Metadata should be ensured to be multiple of 8-bytes,
  937. * to get 8-byte aligned start address along with align_pad added
  938. *
  939. * |-----------------------------|
  940. * | |
  941. * |-----------------------------| <-----Buffer Pointer Address given
  942. * | | ^ in HW descriptor (aligned)
  943. * | HTT Metadata | |
  944. * | | |
  945. * | | | Packet Offset given in descriptor
  946. * | | |
  947. * |-----------------------------| |
  948. * | Alignment Pad | v
  949. * |-----------------------------| <----- Actual buffer start address
  950. * | SKB Data | (Unaligned)
  951. * | |
  952. * | |
  953. * | |
  954. * | |
  955. * | |
  956. * |-----------------------------|
  957. */
  958. if (qdf_unlikely((msdu_info->exception_fw)) ||
  959. (vdev->opmode == wlan_op_mode_ocb) ||
  960. (tx_exc_metadata &&
  961. tx_exc_metadata->is_tx_sniffer)) {
  962. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  963. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  964. DP_STATS_INC(vdev,
  965. tx_i.dropped.headroom_insufficient, 1);
  966. goto failure;
  967. }
  968. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  969. dp_tx_err("qdf_nbuf_push_head failed");
  970. goto failure;
  971. }
  972. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  973. msdu_info);
  974. if (htt_hdr_size == 0)
  975. goto failure;
  976. tx_desc->length = qdf_nbuf_headlen(nbuf);
  977. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  978. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  979. is_exception = 1;
  980. tx_desc->length -= tx_desc->pkt_offset;
  981. }
  982. #if !TQM_BYPASS_WAR
  983. if (is_exception || tx_exc_metadata)
  984. #endif
  985. {
  986. /* Temporary WAR due to TQM VP issues */
  987. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  988. qdf_atomic_inc(&soc->num_tx_exception);
  989. }
  990. return tx_desc;
  991. failure:
  992. dp_tx_desc_release(tx_desc, desc_pool_id);
  993. return NULL;
  994. }
  995. /**
  996. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  997. * @vdev: DP vdev handle
  998. * @nbuf: skb
  999. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1000. * @desc_pool_id : Descriptor Pool ID
  1001. *
  1002. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1003. * information. For frames wth fragments, allocate and prepare
  1004. * an MSDU extension descriptor
  1005. *
  1006. * Return: Pointer to Tx Descriptor on success,
  1007. * NULL on failure
  1008. */
  1009. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1010. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1011. uint8_t desc_pool_id)
  1012. {
  1013. struct dp_tx_desc_s *tx_desc;
  1014. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1015. struct dp_pdev *pdev = vdev->pdev;
  1016. struct dp_soc *soc = pdev->soc;
  1017. if (dp_tx_limit_check(vdev))
  1018. return NULL;
  1019. /* Allocate software Tx descriptor */
  1020. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1021. if (!tx_desc) {
  1022. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1023. return NULL;
  1024. }
  1025. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1026. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1027. dp_tx_outstanding_inc(pdev);
  1028. /* Initialize the SW tx descriptor */
  1029. tx_desc->nbuf = nbuf;
  1030. tx_desc->frm_type = msdu_info->frm_type;
  1031. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1032. tx_desc->vdev_id = vdev->vdev_id;
  1033. tx_desc->pdev = pdev;
  1034. tx_desc->pkt_offset = 0;
  1035. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1036. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1037. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  1038. /* Handle scattered frames - TSO/SG/ME */
  1039. /* Allocate and prepare an extension descriptor for scattered frames */
  1040. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1041. if (!msdu_ext_desc) {
  1042. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1043. goto failure;
  1044. }
  1045. #if TQM_BYPASS_WAR
  1046. /* Temporary WAR due to TQM VP issues */
  1047. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1048. qdf_atomic_inc(&soc->num_tx_exception);
  1049. #endif
  1050. if (qdf_unlikely(msdu_info->exception_fw))
  1051. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1052. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1053. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1054. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1055. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1056. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1057. else
  1058. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1059. return tx_desc;
  1060. failure:
  1061. dp_tx_desc_release(tx_desc, desc_pool_id);
  1062. return NULL;
  1063. }
  1064. /**
  1065. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1066. * @vdev: DP vdev handle
  1067. * @nbuf: buffer pointer
  1068. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1069. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1070. * descriptor
  1071. *
  1072. * Return:
  1073. */
  1074. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1075. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1076. {
  1077. qdf_nbuf_t curr_nbuf = NULL;
  1078. uint16_t total_len = 0;
  1079. qdf_dma_addr_t paddr;
  1080. int32_t i;
  1081. int32_t mapped_buf_num = 0;
  1082. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1083. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1084. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1085. /* Continue only if frames are of DATA type */
  1086. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1087. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1088. dp_tx_debug("Pkt. recd is of not data type");
  1089. goto error;
  1090. }
  1091. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1092. if (vdev->raw_mode_war &&
  1093. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1094. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1095. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1096. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1097. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1098. /*
  1099. * Number of nbuf's must not exceed the size of the frags
  1100. * array in seg_info.
  1101. */
  1102. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1103. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1104. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1105. goto error;
  1106. }
  1107. if (QDF_STATUS_SUCCESS !=
  1108. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1109. curr_nbuf,
  1110. QDF_DMA_TO_DEVICE,
  1111. curr_nbuf->len)) {
  1112. dp_tx_err("%s dma map error ", __func__);
  1113. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1114. goto error;
  1115. }
  1116. /* Update the count of mapped nbuf's */
  1117. mapped_buf_num++;
  1118. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1119. seg_info->frags[i].paddr_lo = paddr;
  1120. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1121. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1122. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1123. total_len += qdf_nbuf_len(curr_nbuf);
  1124. }
  1125. seg_info->frag_cnt = i;
  1126. seg_info->total_len = total_len;
  1127. seg_info->next = NULL;
  1128. sg_info->curr_seg = seg_info;
  1129. msdu_info->frm_type = dp_tx_frm_raw;
  1130. msdu_info->num_seg = 1;
  1131. return nbuf;
  1132. error:
  1133. i = 0;
  1134. while (nbuf) {
  1135. curr_nbuf = nbuf;
  1136. if (i < mapped_buf_num) {
  1137. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1138. QDF_DMA_TO_DEVICE,
  1139. curr_nbuf->len);
  1140. i++;
  1141. }
  1142. nbuf = qdf_nbuf_next(nbuf);
  1143. qdf_nbuf_free(curr_nbuf);
  1144. }
  1145. return NULL;
  1146. }
  1147. /**
  1148. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1149. * @soc: DP soc handle
  1150. * @nbuf: Buffer pointer
  1151. *
  1152. * unmap the chain of nbufs that belong to this RAW frame.
  1153. *
  1154. * Return: None
  1155. */
  1156. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1157. qdf_nbuf_t nbuf)
  1158. {
  1159. qdf_nbuf_t cur_nbuf = nbuf;
  1160. do {
  1161. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1162. QDF_DMA_TO_DEVICE,
  1163. cur_nbuf->len);
  1164. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1165. } while (cur_nbuf);
  1166. }
  1167. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1168. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1169. qdf_nbuf_t nbuf)
  1170. {
  1171. qdf_nbuf_t nbuf_local;
  1172. struct dp_vdev *vdev_local = vdev_hdl;
  1173. do {
  1174. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1175. break;
  1176. nbuf_local = nbuf;
  1177. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1178. htt_cmn_pkt_type_raw))
  1179. break;
  1180. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1181. break;
  1182. else if (qdf_nbuf_is_tso((nbuf_local)))
  1183. break;
  1184. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1185. (nbuf_local),
  1186. NULL, 1, 0);
  1187. } while (0);
  1188. }
  1189. #endif
  1190. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1191. /**
  1192. * dp_tx_update_stats() - Update soc level tx stats
  1193. * @soc: DP soc handle
  1194. * @nbuf: packet being transmitted
  1195. *
  1196. * Returns: none
  1197. */
  1198. void dp_tx_update_stats(struct dp_soc *soc,
  1199. qdf_nbuf_t nbuf)
  1200. {
  1201. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1202. }
  1203. int
  1204. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1205. struct dp_tx_desc_s *tx_desc,
  1206. uint8_t tid)
  1207. {
  1208. struct dp_swlm *swlm = &soc->swlm;
  1209. union swlm_data swlm_query_data;
  1210. struct dp_swlm_tcl_data tcl_data;
  1211. QDF_STATUS status;
  1212. int ret;
  1213. if (qdf_unlikely(!swlm->is_enabled))
  1214. return 0;
  1215. tcl_data.nbuf = tx_desc->nbuf;
  1216. tcl_data.tid = tid;
  1217. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1218. swlm_query_data.tcl_data = &tcl_data;
  1219. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1220. if (QDF_IS_STATUS_ERROR(status)) {
  1221. dp_swlm_tcl_reset_session_data(soc);
  1222. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1223. return 0;
  1224. }
  1225. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1226. if (ret) {
  1227. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1228. } else {
  1229. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1230. }
  1231. return ret;
  1232. }
  1233. void
  1234. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1235. int coalesce)
  1236. {
  1237. if (coalesce)
  1238. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1239. else
  1240. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1241. }
  1242. #endif
  1243. #ifdef FEATURE_RUNTIME_PM
  1244. /**
  1245. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1246. * @soc: Datapath soc handle
  1247. * @hal_ring_hdl: HAL ring handle
  1248. * @coalesce: Coalesce the current write or not
  1249. *
  1250. * Wrapper for HAL ring access end for data transmission for
  1251. * FEATURE_RUNTIME_PM
  1252. *
  1253. * Returns: none
  1254. */
  1255. void
  1256. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1257. hal_ring_handle_t hal_ring_hdl,
  1258. int coalesce)
  1259. {
  1260. int ret;
  1261. ret = hif_pm_runtime_get(soc->hif_handle,
  1262. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1263. switch (ret) {
  1264. case 0:
  1265. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1266. hif_pm_runtime_put(soc->hif_handle,
  1267. RTPM_ID_DW_TX_HW_ENQUEUE);
  1268. break;
  1269. /*
  1270. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1271. * take the dp runtime refcount using dp_runtime_get,
  1272. * check link state,if up, write TX ring HP, else just set flush event.
  1273. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1274. * zero or time out, then flush pending tx.
  1275. */
  1276. case -EBUSY:
  1277. case -EINPROGRESS:
  1278. dp_runtime_get(soc);
  1279. if (hif_pm_get_link_state(soc->hif_handle) ==
  1280. HIF_PM_LINK_STATE_UP) {
  1281. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1282. } else {
  1283. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1284. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1285. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1286. }
  1287. dp_runtime_put(soc);
  1288. break;
  1289. default:
  1290. dp_runtime_get(soc);
  1291. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1292. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1293. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1294. dp_runtime_put(soc);
  1295. }
  1296. }
  1297. #endif
  1298. /**
  1299. * dp_cce_classify() - Classify the frame based on CCE rules
  1300. * @vdev: DP vdev handle
  1301. * @nbuf: skb
  1302. *
  1303. * Classify frames based on CCE rules
  1304. * Return: bool( true if classified,
  1305. * else false)
  1306. */
  1307. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1308. {
  1309. qdf_ether_header_t *eh = NULL;
  1310. uint16_t ether_type;
  1311. qdf_llc_t *llcHdr;
  1312. qdf_nbuf_t nbuf_clone = NULL;
  1313. qdf_dot3_qosframe_t *qos_wh = NULL;
  1314. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1315. /*
  1316. * In case of mesh packets or hlos tid override enabled,
  1317. * don't do any classification
  1318. */
  1319. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1320. & DP_TX_SKIP_CCE_CLASSIFY))
  1321. return false;
  1322. }
  1323. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1324. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1325. ether_type = eh->ether_type;
  1326. llcHdr = (qdf_llc_t *)(nbuf->data +
  1327. sizeof(qdf_ether_header_t));
  1328. } else {
  1329. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1330. /* For encrypted packets don't do any classification */
  1331. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1332. return false;
  1333. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1334. if (qdf_unlikely(
  1335. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1336. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1337. ether_type = *(uint16_t *)(nbuf->data
  1338. + QDF_IEEE80211_4ADDR_HDR_LEN
  1339. + sizeof(qdf_llc_t)
  1340. - sizeof(ether_type));
  1341. llcHdr = (qdf_llc_t *)(nbuf->data +
  1342. QDF_IEEE80211_4ADDR_HDR_LEN);
  1343. } else {
  1344. ether_type = *(uint16_t *)(nbuf->data
  1345. + QDF_IEEE80211_3ADDR_HDR_LEN
  1346. + sizeof(qdf_llc_t)
  1347. - sizeof(ether_type));
  1348. llcHdr = (qdf_llc_t *)(nbuf->data +
  1349. QDF_IEEE80211_3ADDR_HDR_LEN);
  1350. }
  1351. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1352. && (ether_type ==
  1353. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1354. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1355. return true;
  1356. }
  1357. }
  1358. return false;
  1359. }
  1360. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1361. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1362. sizeof(*llcHdr));
  1363. nbuf_clone = qdf_nbuf_clone(nbuf);
  1364. if (qdf_unlikely(nbuf_clone)) {
  1365. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1366. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1367. qdf_nbuf_pull_head(nbuf_clone,
  1368. sizeof(qdf_net_vlanhdr_t));
  1369. }
  1370. }
  1371. } else {
  1372. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1373. nbuf_clone = qdf_nbuf_clone(nbuf);
  1374. if (qdf_unlikely(nbuf_clone)) {
  1375. qdf_nbuf_pull_head(nbuf_clone,
  1376. sizeof(qdf_net_vlanhdr_t));
  1377. }
  1378. }
  1379. }
  1380. if (qdf_unlikely(nbuf_clone))
  1381. nbuf = nbuf_clone;
  1382. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1383. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1384. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1385. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1386. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1387. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1388. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1389. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1390. if (qdf_unlikely(nbuf_clone))
  1391. qdf_nbuf_free(nbuf_clone);
  1392. return true;
  1393. }
  1394. if (qdf_unlikely(nbuf_clone))
  1395. qdf_nbuf_free(nbuf_clone);
  1396. return false;
  1397. }
  1398. /**
  1399. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1400. * @vdev: DP vdev handle
  1401. * @nbuf: skb
  1402. *
  1403. * Extract the DSCP or PCP information from frame and map into TID value.
  1404. *
  1405. * Return: void
  1406. */
  1407. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1408. struct dp_tx_msdu_info_s *msdu_info)
  1409. {
  1410. uint8_t tos = 0, dscp_tid_override = 0;
  1411. uint8_t *hdr_ptr, *L3datap;
  1412. uint8_t is_mcast = 0;
  1413. qdf_ether_header_t *eh = NULL;
  1414. qdf_ethervlan_header_t *evh = NULL;
  1415. uint16_t ether_type;
  1416. qdf_llc_t *llcHdr;
  1417. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1418. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1419. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1420. eh = (qdf_ether_header_t *)nbuf->data;
  1421. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1422. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1423. } else {
  1424. qdf_dot3_qosframe_t *qos_wh =
  1425. (qdf_dot3_qosframe_t *) nbuf->data;
  1426. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1427. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1428. return;
  1429. }
  1430. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1431. ether_type = eh->ether_type;
  1432. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1433. /*
  1434. * Check if packet is dot3 or eth2 type.
  1435. */
  1436. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1437. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1438. sizeof(*llcHdr));
  1439. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1440. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1441. sizeof(*llcHdr);
  1442. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1443. + sizeof(*llcHdr) +
  1444. sizeof(qdf_net_vlanhdr_t));
  1445. } else {
  1446. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1447. sizeof(*llcHdr);
  1448. }
  1449. } else {
  1450. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1451. evh = (qdf_ethervlan_header_t *) eh;
  1452. ether_type = evh->ether_type;
  1453. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1454. }
  1455. }
  1456. /*
  1457. * Find priority from IP TOS DSCP field
  1458. */
  1459. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1460. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1461. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1462. /* Only for unicast frames */
  1463. if (!is_mcast) {
  1464. /* send it on VO queue */
  1465. msdu_info->tid = DP_VO_TID;
  1466. }
  1467. } else {
  1468. /*
  1469. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1470. * from TOS byte.
  1471. */
  1472. tos = ip->ip_tos;
  1473. dscp_tid_override = 1;
  1474. }
  1475. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1476. /* TODO
  1477. * use flowlabel
  1478. *igmpmld cases to be handled in phase 2
  1479. */
  1480. unsigned long ver_pri_flowlabel;
  1481. unsigned long pri;
  1482. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1483. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1484. DP_IPV6_PRIORITY_SHIFT;
  1485. tos = pri;
  1486. dscp_tid_override = 1;
  1487. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1488. msdu_info->tid = DP_VO_TID;
  1489. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1490. /* Only for unicast frames */
  1491. if (!is_mcast) {
  1492. /* send ucast arp on VO queue */
  1493. msdu_info->tid = DP_VO_TID;
  1494. }
  1495. }
  1496. /*
  1497. * Assign all MCAST packets to BE
  1498. */
  1499. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1500. if (is_mcast) {
  1501. tos = 0;
  1502. dscp_tid_override = 1;
  1503. }
  1504. }
  1505. if (dscp_tid_override == 1) {
  1506. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1507. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1508. }
  1509. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1510. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1511. return;
  1512. }
  1513. /**
  1514. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1515. * @vdev: DP vdev handle
  1516. * @nbuf: skb
  1517. *
  1518. * Software based TID classification is required when more than 2 DSCP-TID
  1519. * mapping tables are needed.
  1520. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1521. *
  1522. * Return: void
  1523. */
  1524. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1525. struct dp_tx_msdu_info_s *msdu_info)
  1526. {
  1527. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1528. /*
  1529. * skip_sw_tid_classification flag will set in below cases-
  1530. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1531. * 2. hlos_tid_override enabled for vdev
  1532. * 3. mesh mode enabled for vdev
  1533. */
  1534. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1535. /* Update tid in msdu_info from skb priority */
  1536. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1537. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1538. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1539. return;
  1540. }
  1541. return;
  1542. }
  1543. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1544. }
  1545. #ifdef FEATURE_WLAN_TDLS
  1546. /**
  1547. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1548. * @soc: datapath SOC
  1549. * @vdev: datapath vdev
  1550. * @tx_desc: TX descriptor
  1551. *
  1552. * Return: None
  1553. */
  1554. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1555. struct dp_vdev *vdev,
  1556. struct dp_tx_desc_s *tx_desc)
  1557. {
  1558. if (vdev) {
  1559. if (vdev->is_tdls_frame) {
  1560. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1561. vdev->is_tdls_frame = false;
  1562. }
  1563. }
  1564. }
  1565. /**
  1566. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1567. * @soc: dp_soc handle
  1568. * @tx_desc: TX descriptor
  1569. * @vdev: datapath vdev handle
  1570. *
  1571. * Return: None
  1572. */
  1573. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1574. struct dp_tx_desc_s *tx_desc)
  1575. {
  1576. struct hal_tx_completion_status ts = {0};
  1577. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1578. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1579. DP_MOD_ID_TDLS);
  1580. if (qdf_unlikely(!vdev)) {
  1581. dp_err_rl("vdev is null!");
  1582. goto error;
  1583. }
  1584. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1585. if (vdev->tx_non_std_data_callback.func) {
  1586. qdf_nbuf_set_next(nbuf, NULL);
  1587. vdev->tx_non_std_data_callback.func(
  1588. vdev->tx_non_std_data_callback.ctxt,
  1589. nbuf, ts.status);
  1590. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1591. return;
  1592. } else {
  1593. dp_err_rl("callback func is null");
  1594. }
  1595. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1596. error:
  1597. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1598. qdf_nbuf_free(nbuf);
  1599. }
  1600. /**
  1601. * dp_tx_msdu_single_map() - do nbuf map
  1602. * @vdev: DP vdev handle
  1603. * @tx_desc: DP TX descriptor pointer
  1604. * @nbuf: skb pointer
  1605. *
  1606. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1607. * operation done in other component.
  1608. *
  1609. * Return: QDF_STATUS
  1610. */
  1611. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1612. struct dp_tx_desc_s *tx_desc,
  1613. qdf_nbuf_t nbuf)
  1614. {
  1615. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1616. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1617. nbuf,
  1618. QDF_DMA_TO_DEVICE,
  1619. nbuf->len);
  1620. else
  1621. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1622. QDF_DMA_TO_DEVICE);
  1623. }
  1624. #else
  1625. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1626. struct dp_vdev *vdev,
  1627. struct dp_tx_desc_s *tx_desc)
  1628. {
  1629. }
  1630. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1631. struct dp_tx_desc_s *tx_desc)
  1632. {
  1633. }
  1634. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1635. struct dp_tx_desc_s *tx_desc,
  1636. qdf_nbuf_t nbuf)
  1637. {
  1638. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1639. nbuf,
  1640. QDF_DMA_TO_DEVICE,
  1641. nbuf->len);
  1642. }
  1643. #endif
  1644. #ifdef MESH_MODE_SUPPORT
  1645. /**
  1646. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1647. * @soc: datapath SOC
  1648. * @vdev: datapath vdev
  1649. * @tx_desc: TX descriptor
  1650. *
  1651. * Return: None
  1652. */
  1653. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1654. struct dp_vdev *vdev,
  1655. struct dp_tx_desc_s *tx_desc)
  1656. {
  1657. if (qdf_unlikely(vdev->mesh_vdev))
  1658. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1659. }
  1660. /**
  1661. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1662. * @soc: dp_soc handle
  1663. * @tx_desc: TX descriptor
  1664. * @vdev: datapath vdev handle
  1665. *
  1666. * Return: None
  1667. */
  1668. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1669. struct dp_tx_desc_s *tx_desc)
  1670. {
  1671. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1672. struct dp_vdev *vdev = NULL;
  1673. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1674. qdf_nbuf_free(nbuf);
  1675. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1676. } else {
  1677. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1678. DP_MOD_ID_MESH);
  1679. if (vdev && vdev->osif_tx_free_ext)
  1680. vdev->osif_tx_free_ext((nbuf));
  1681. else
  1682. qdf_nbuf_free(nbuf);
  1683. if (vdev)
  1684. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1685. }
  1686. }
  1687. #else
  1688. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1689. struct dp_vdev *vdev,
  1690. struct dp_tx_desc_s *tx_desc)
  1691. {
  1692. }
  1693. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1694. struct dp_tx_desc_s *tx_desc)
  1695. {
  1696. }
  1697. #endif
  1698. /**
  1699. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1700. * @vdev: DP vdev handle
  1701. * @nbuf: skb
  1702. *
  1703. * Return: 1 if frame needs to be dropped else 0
  1704. */
  1705. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1706. {
  1707. struct dp_pdev *pdev = NULL;
  1708. struct dp_ast_entry *src_ast_entry = NULL;
  1709. struct dp_ast_entry *dst_ast_entry = NULL;
  1710. struct dp_soc *soc = NULL;
  1711. qdf_assert(vdev);
  1712. pdev = vdev->pdev;
  1713. qdf_assert(pdev);
  1714. soc = pdev->soc;
  1715. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1716. (soc, dstmac, vdev->pdev->pdev_id);
  1717. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1718. (soc, srcmac, vdev->pdev->pdev_id);
  1719. if (dst_ast_entry && src_ast_entry) {
  1720. if (dst_ast_entry->peer_id ==
  1721. src_ast_entry->peer_id)
  1722. return 1;
  1723. }
  1724. return 0;
  1725. }
  1726. /**
  1727. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1728. * @vdev: DP vdev handle
  1729. * @nbuf: skb
  1730. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1731. * @meta_data: Metadata to the fw
  1732. * @tx_q: Tx queue to be used for this Tx frame
  1733. * @peer_id: peer_id of the peer in case of NAWDS frames
  1734. * @tx_exc_metadata: Handle that holds exception path metadata
  1735. *
  1736. * Return: NULL on success,
  1737. * nbuf when it fails to send
  1738. */
  1739. qdf_nbuf_t
  1740. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1741. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1742. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1743. {
  1744. struct dp_pdev *pdev = vdev->pdev;
  1745. struct dp_soc *soc = pdev->soc;
  1746. struct dp_tx_desc_s *tx_desc;
  1747. QDF_STATUS status;
  1748. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1749. uint16_t htt_tcl_metadata = 0;
  1750. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1751. uint8_t tid = msdu_info->tid;
  1752. struct cdp_tid_tx_stats *tid_stats = NULL;
  1753. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1754. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1755. msdu_info, tx_exc_metadata);
  1756. if (!tx_desc) {
  1757. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1758. vdev, tx_q->desc_pool_id);
  1759. drop_code = TX_DESC_ERR;
  1760. goto fail_return;
  1761. }
  1762. if (qdf_unlikely(soc->cce_disable)) {
  1763. if (dp_cce_classify(vdev, nbuf) == true) {
  1764. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1765. tid = DP_VO_TID;
  1766. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1767. }
  1768. }
  1769. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1770. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1771. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1772. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1773. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1774. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1775. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1776. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1777. peer_id);
  1778. } else
  1779. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1780. if (msdu_info->exception_fw)
  1781. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1782. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1783. !pdev->enhanced_stats_en);
  1784. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1785. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1786. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1787. /* Handle failure */
  1788. dp_err("qdf_nbuf_map failed");
  1789. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1790. drop_code = TX_DMA_MAP_ERR;
  1791. goto release_desc;
  1792. }
  1793. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1794. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1795. tx_desc->id, DP_TX_DESC_MAP);
  1796. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1797. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1798. htt_tcl_metadata,
  1799. tx_exc_metadata, msdu_info);
  1800. if (status != QDF_STATUS_SUCCESS) {
  1801. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1802. tx_desc, tx_q->ring_id);
  1803. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1804. tx_desc->id, DP_TX_DESC_UNMAP);
  1805. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1806. QDF_DMA_TO_DEVICE,
  1807. nbuf->len);
  1808. drop_code = TX_HW_ENQUEUE;
  1809. goto release_desc;
  1810. }
  1811. return NULL;
  1812. release_desc:
  1813. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1814. fail_return:
  1815. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1816. tid_stats = &pdev->stats.tid_stats.
  1817. tid_tx_stats[tx_q->ring_id][tid];
  1818. tid_stats->swdrop_cnt[drop_code]++;
  1819. return nbuf;
  1820. }
  1821. /**
  1822. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1823. * @soc: Soc handle
  1824. * @desc: software Tx descriptor to be processed
  1825. *
  1826. * Return: none
  1827. */
  1828. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1829. struct dp_tx_desc_s *desc)
  1830. {
  1831. qdf_nbuf_t nbuf = desc->nbuf;
  1832. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1833. /* nbuf already freed in vdev detach path */
  1834. if (!nbuf)
  1835. return;
  1836. /* If it is TDLS mgmt, don't unmap or free the frame */
  1837. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1838. return dp_non_std_tx_comp_free_buff(soc, desc);
  1839. /* 0 : MSDU buffer, 1 : MLE */
  1840. if (desc->msdu_ext_desc) {
  1841. /* TSO free */
  1842. if (hal_tx_ext_desc_get_tso_enable(
  1843. desc->msdu_ext_desc->vaddr)) {
  1844. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1845. desc->id, DP_TX_COMP_MSDU_EXT);
  1846. dp_tx_tso_seg_history_add(soc, desc->tso_desc,
  1847. desc->nbuf, desc->id, type);
  1848. /* unmap eash TSO seg before free the nbuf */
  1849. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1850. desc->tso_num_desc);
  1851. qdf_nbuf_free(nbuf);
  1852. return;
  1853. }
  1854. }
  1855. /* If it's ME frame, dont unmap the cloned nbuf's */
  1856. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1857. goto nbuf_free;
  1858. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1859. dp_tx_unmap(soc, desc);
  1860. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1861. return dp_mesh_tx_comp_free_buff(soc, desc);
  1862. nbuf_free:
  1863. qdf_nbuf_free(nbuf);
  1864. }
  1865. /**
  1866. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1867. * @vdev: DP vdev handle
  1868. * @nbuf: skb
  1869. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1870. *
  1871. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1872. *
  1873. * Return: NULL on success,
  1874. * nbuf when it fails to send
  1875. */
  1876. #if QDF_LOCK_STATS
  1877. noinline
  1878. #else
  1879. #endif
  1880. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1881. struct dp_tx_msdu_info_s *msdu_info)
  1882. {
  1883. uint32_t i;
  1884. struct dp_pdev *pdev = vdev->pdev;
  1885. struct dp_soc *soc = pdev->soc;
  1886. struct dp_tx_desc_s *tx_desc;
  1887. bool is_cce_classified = false;
  1888. QDF_STATUS status;
  1889. uint16_t htt_tcl_metadata = 0;
  1890. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1891. struct cdp_tid_tx_stats *tid_stats = NULL;
  1892. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1893. if (qdf_unlikely(soc->cce_disable)) {
  1894. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1895. if (is_cce_classified) {
  1896. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1897. msdu_info->tid = DP_VO_TID;
  1898. }
  1899. }
  1900. if (msdu_info->frm_type == dp_tx_frm_me)
  1901. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1902. i = 0;
  1903. /* Print statement to track i and num_seg */
  1904. /*
  1905. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1906. * descriptors using information in msdu_info
  1907. */
  1908. while (i < msdu_info->num_seg) {
  1909. /*
  1910. * Setup Tx descriptor for an MSDU, and MSDU extension
  1911. * descriptor
  1912. */
  1913. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1914. tx_q->desc_pool_id);
  1915. if (!tx_desc) {
  1916. if (msdu_info->frm_type == dp_tx_frm_me) {
  1917. prep_desc_fail++;
  1918. dp_tx_me_free_buf(pdev,
  1919. (void *)(msdu_info->u.sg_info
  1920. .curr_seg->frags[0].vaddr));
  1921. if (prep_desc_fail == msdu_info->num_seg) {
  1922. /*
  1923. * Unmap is needed only if descriptor
  1924. * preparation failed for all segments.
  1925. */
  1926. qdf_nbuf_unmap(soc->osdev,
  1927. msdu_info->u.sg_info.
  1928. curr_seg->nbuf,
  1929. QDF_DMA_TO_DEVICE);
  1930. }
  1931. /*
  1932. * Free the nbuf for the current segment
  1933. * and make it point to the next in the list.
  1934. * For me, there are as many segments as there
  1935. * are no of clients.
  1936. */
  1937. qdf_nbuf_free(msdu_info->u.sg_info
  1938. .curr_seg->nbuf);
  1939. if (msdu_info->u.sg_info.curr_seg->next) {
  1940. msdu_info->u.sg_info.curr_seg =
  1941. msdu_info->u.sg_info
  1942. .curr_seg->next;
  1943. nbuf = msdu_info->u.sg_info
  1944. .curr_seg->nbuf;
  1945. }
  1946. i++;
  1947. continue;
  1948. }
  1949. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1950. dp_tx_tso_seg_history_add(
  1951. soc,
  1952. msdu_info->u.tso_info.curr_seg,
  1953. nbuf, 0, DP_TX_DESC_UNMAP);
  1954. dp_tx_tso_unmap_segment(soc,
  1955. msdu_info->u.tso_info.
  1956. curr_seg,
  1957. msdu_info->u.tso_info.
  1958. tso_num_seg_list);
  1959. if (msdu_info->u.tso_info.curr_seg->next) {
  1960. msdu_info->u.tso_info.curr_seg =
  1961. msdu_info->u.tso_info.curr_seg->next;
  1962. i++;
  1963. continue;
  1964. }
  1965. }
  1966. goto done;
  1967. }
  1968. if (msdu_info->frm_type == dp_tx_frm_me) {
  1969. tx_desc->me_buffer =
  1970. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1971. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1972. }
  1973. if (is_cce_classified)
  1974. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1975. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1976. if (msdu_info->exception_fw) {
  1977. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1978. }
  1979. /*
  1980. * For frames with multiple segments (TSO, ME), jump to next
  1981. * segment.
  1982. */
  1983. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1984. if (msdu_info->u.tso_info.curr_seg->next) {
  1985. msdu_info->u.tso_info.curr_seg =
  1986. msdu_info->u.tso_info.curr_seg->next;
  1987. /*
  1988. * If this is a jumbo nbuf, then increment the
  1989. * number of nbuf users for each additional
  1990. * segment of the msdu. This will ensure that
  1991. * the skb is freed only after receiving tx
  1992. * completion for all segments of an nbuf
  1993. */
  1994. qdf_nbuf_inc_users(nbuf);
  1995. /* Check with MCL if this is needed */
  1996. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1997. */
  1998. }
  1999. }
  2000. /*
  2001. * Enqueue the Tx MSDU descriptor to HW for transmit
  2002. */
  2003. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2004. htt_tcl_metadata,
  2005. NULL, msdu_info);
  2006. if (status != QDF_STATUS_SUCCESS) {
  2007. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2008. tx_desc, tx_q->ring_id);
  2009. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2010. tid_stats = &pdev->stats.tid_stats.
  2011. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2012. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2013. if (msdu_info->frm_type == dp_tx_frm_me) {
  2014. hw_enq_fail++;
  2015. if (hw_enq_fail == msdu_info->num_seg) {
  2016. /*
  2017. * Unmap is needed only if enqueue
  2018. * failed for all segments.
  2019. */
  2020. qdf_nbuf_unmap(soc->osdev,
  2021. msdu_info->u.sg_info.
  2022. curr_seg->nbuf,
  2023. QDF_DMA_TO_DEVICE);
  2024. }
  2025. /*
  2026. * Free the nbuf for the current segment
  2027. * and make it point to the next in the list.
  2028. * For me, there are as many segments as there
  2029. * are no of clients.
  2030. */
  2031. qdf_nbuf_free(msdu_info->u.sg_info
  2032. .curr_seg->nbuf);
  2033. if (msdu_info->u.sg_info.curr_seg->next) {
  2034. msdu_info->u.sg_info.curr_seg =
  2035. msdu_info->u.sg_info
  2036. .curr_seg->next;
  2037. nbuf = msdu_info->u.sg_info
  2038. .curr_seg->nbuf;
  2039. } else
  2040. break;
  2041. i++;
  2042. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2043. continue;
  2044. }
  2045. /*
  2046. * For TSO frames, the nbuf users increment done for
  2047. * the current segment has to be reverted, since the
  2048. * hw enqueue for this segment failed
  2049. */
  2050. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2051. msdu_info->u.tso_info.curr_seg) {
  2052. /*
  2053. * unmap and free current,
  2054. * retransmit remaining segments
  2055. */
  2056. dp_tx_comp_free_buf(soc, tx_desc);
  2057. i++;
  2058. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2059. continue;
  2060. }
  2061. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2062. goto done;
  2063. }
  2064. /*
  2065. * TODO
  2066. * if tso_info structure can be modified to have curr_seg
  2067. * as first element, following 2 blocks of code (for TSO and SG)
  2068. * can be combined into 1
  2069. */
  2070. /*
  2071. * For Multicast-Unicast converted packets,
  2072. * each converted frame (for a client) is represented as
  2073. * 1 segment
  2074. */
  2075. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2076. (msdu_info->frm_type == dp_tx_frm_me)) {
  2077. if (msdu_info->u.sg_info.curr_seg->next) {
  2078. msdu_info->u.sg_info.curr_seg =
  2079. msdu_info->u.sg_info.curr_seg->next;
  2080. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2081. } else
  2082. break;
  2083. }
  2084. i++;
  2085. }
  2086. nbuf = NULL;
  2087. done:
  2088. return nbuf;
  2089. }
  2090. /**
  2091. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2092. * for SG frames
  2093. * @vdev: DP vdev handle
  2094. * @nbuf: skb
  2095. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2096. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2097. *
  2098. * Return: NULL on success,
  2099. * nbuf when it fails to send
  2100. */
  2101. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2102. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2103. {
  2104. uint32_t cur_frag, nr_frags, i;
  2105. qdf_dma_addr_t paddr;
  2106. struct dp_tx_sg_info_s *sg_info;
  2107. sg_info = &msdu_info->u.sg_info;
  2108. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2109. if (QDF_STATUS_SUCCESS !=
  2110. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2111. QDF_DMA_TO_DEVICE,
  2112. qdf_nbuf_headlen(nbuf))) {
  2113. dp_tx_err("dma map error");
  2114. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2115. qdf_nbuf_free(nbuf);
  2116. return NULL;
  2117. }
  2118. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2119. seg_info->frags[0].paddr_lo = paddr;
  2120. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2121. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2122. seg_info->frags[0].vaddr = (void *) nbuf;
  2123. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2124. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2125. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2126. dp_tx_err("frag dma map error");
  2127. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2128. goto map_err;
  2129. }
  2130. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2131. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2132. seg_info->frags[cur_frag + 1].paddr_hi =
  2133. ((uint64_t) paddr) >> 32;
  2134. seg_info->frags[cur_frag + 1].len =
  2135. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2136. }
  2137. seg_info->frag_cnt = (cur_frag + 1);
  2138. seg_info->total_len = qdf_nbuf_len(nbuf);
  2139. seg_info->next = NULL;
  2140. sg_info->curr_seg = seg_info;
  2141. msdu_info->frm_type = dp_tx_frm_sg;
  2142. msdu_info->num_seg = 1;
  2143. return nbuf;
  2144. map_err:
  2145. /* restore paddr into nbuf before calling unmap */
  2146. qdf_nbuf_mapped_paddr_set(nbuf,
  2147. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2148. ((uint64_t)
  2149. seg_info->frags[0].paddr_hi) << 32));
  2150. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2151. QDF_DMA_TO_DEVICE,
  2152. seg_info->frags[0].len);
  2153. for (i = 1; i <= cur_frag; i++) {
  2154. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2155. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2156. seg_info->frags[i].paddr_hi) << 32),
  2157. seg_info->frags[i].len,
  2158. QDF_DMA_TO_DEVICE);
  2159. }
  2160. qdf_nbuf_free(nbuf);
  2161. return NULL;
  2162. }
  2163. /**
  2164. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2165. * @vdev: DP vdev handle
  2166. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2167. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2168. *
  2169. * Return: NULL on failure,
  2170. * nbuf when extracted successfully
  2171. */
  2172. static
  2173. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2174. struct dp_tx_msdu_info_s *msdu_info,
  2175. uint16_t ppdu_cookie)
  2176. {
  2177. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2178. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2179. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2180. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2181. (msdu_info->meta_data[5], 1);
  2182. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2183. (msdu_info->meta_data[5], 1);
  2184. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2185. (msdu_info->meta_data[6], ppdu_cookie);
  2186. msdu_info->exception_fw = 1;
  2187. msdu_info->is_tx_sniffer = 1;
  2188. }
  2189. #ifdef MESH_MODE_SUPPORT
  2190. /**
  2191. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2192. and prepare msdu_info for mesh frames.
  2193. * @vdev: DP vdev handle
  2194. * @nbuf: skb
  2195. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2196. *
  2197. * Return: NULL on failure,
  2198. * nbuf when extracted successfully
  2199. */
  2200. static
  2201. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2202. struct dp_tx_msdu_info_s *msdu_info)
  2203. {
  2204. struct meta_hdr_s *mhdr;
  2205. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2206. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2207. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2208. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2209. msdu_info->exception_fw = 0;
  2210. goto remove_meta_hdr;
  2211. }
  2212. msdu_info->exception_fw = 1;
  2213. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2214. meta_data->host_tx_desc_pool = 1;
  2215. meta_data->update_peer_cache = 1;
  2216. meta_data->learning_frame = 1;
  2217. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2218. meta_data->power = mhdr->power;
  2219. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2220. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2221. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2222. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2223. meta_data->dyn_bw = 1;
  2224. meta_data->valid_pwr = 1;
  2225. meta_data->valid_mcs_mask = 1;
  2226. meta_data->valid_nss_mask = 1;
  2227. meta_data->valid_preamble_type = 1;
  2228. meta_data->valid_retries = 1;
  2229. meta_data->valid_bw_info = 1;
  2230. }
  2231. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2232. meta_data->encrypt_type = 0;
  2233. meta_data->valid_encrypt_type = 1;
  2234. meta_data->learning_frame = 0;
  2235. }
  2236. meta_data->valid_key_flags = 1;
  2237. meta_data->key_flags = (mhdr->keyix & 0x3);
  2238. remove_meta_hdr:
  2239. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2240. dp_tx_err("qdf_nbuf_pull_head failed");
  2241. qdf_nbuf_free(nbuf);
  2242. return NULL;
  2243. }
  2244. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2245. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2246. " tid %d to_fw %d",
  2247. msdu_info->meta_data[0],
  2248. msdu_info->meta_data[1],
  2249. msdu_info->meta_data[2],
  2250. msdu_info->meta_data[3],
  2251. msdu_info->meta_data[4],
  2252. msdu_info->meta_data[5],
  2253. msdu_info->tid, msdu_info->exception_fw);
  2254. return nbuf;
  2255. }
  2256. #else
  2257. static
  2258. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2259. struct dp_tx_msdu_info_s *msdu_info)
  2260. {
  2261. return nbuf;
  2262. }
  2263. #endif
  2264. /**
  2265. * dp_check_exc_metadata() - Checks if parameters are valid
  2266. * @tx_exc - holds all exception path parameters
  2267. *
  2268. * Returns true when all the parameters are valid else false
  2269. *
  2270. */
  2271. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2272. {
  2273. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2274. HTT_INVALID_TID);
  2275. bool invalid_encap_type =
  2276. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2277. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2278. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2279. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2280. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2281. tx_exc->ppdu_cookie == 0);
  2282. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2283. invalid_cookie) {
  2284. return false;
  2285. }
  2286. return true;
  2287. }
  2288. #ifdef ATH_SUPPORT_IQUE
  2289. /**
  2290. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2291. * @vdev: vdev handle
  2292. * @nbuf: skb
  2293. *
  2294. * Return: true on success,
  2295. * false on failure
  2296. */
  2297. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2298. {
  2299. qdf_ether_header_t *eh;
  2300. /* Mcast to Ucast Conversion*/
  2301. if (qdf_likely(!vdev->mcast_enhancement_en))
  2302. return true;
  2303. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2304. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2305. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2306. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2307. qdf_nbuf_set_next(nbuf, NULL);
  2308. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2309. qdf_nbuf_len(nbuf));
  2310. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2311. QDF_STATUS_SUCCESS) {
  2312. return false;
  2313. }
  2314. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2315. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2316. QDF_STATUS_SUCCESS) {
  2317. return false;
  2318. }
  2319. }
  2320. }
  2321. return true;
  2322. }
  2323. #else
  2324. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2325. {
  2326. return true;
  2327. }
  2328. #endif
  2329. /**
  2330. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2331. * @nbuf: qdf_nbuf_t
  2332. * @vdev: struct dp_vdev *
  2333. *
  2334. * Allow packet for processing only if it is for peer client which is
  2335. * connected with same vap. Drop packet if client is connected to
  2336. * different vap.
  2337. *
  2338. * Return: QDF_STATUS
  2339. */
  2340. static inline QDF_STATUS
  2341. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2342. {
  2343. struct dp_ast_entry *dst_ast_entry = NULL;
  2344. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2345. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2346. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2347. return QDF_STATUS_SUCCESS;
  2348. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2349. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2350. eh->ether_dhost,
  2351. vdev->vdev_id);
  2352. /* If there is no ast entry, return failure */
  2353. if (qdf_unlikely(!dst_ast_entry)) {
  2354. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2355. return QDF_STATUS_E_FAILURE;
  2356. }
  2357. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2358. return QDF_STATUS_SUCCESS;
  2359. }
  2360. /**
  2361. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2362. * @soc: DP soc handle
  2363. * @vdev_id: id of DP vdev handle
  2364. * @nbuf: skb
  2365. * @tx_exc_metadata: Handle that holds exception path meta data
  2366. *
  2367. * Entry point for Core Tx layer (DP_TX) invoked from
  2368. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2369. *
  2370. * Return: NULL on success,
  2371. * nbuf when it fails to send
  2372. */
  2373. qdf_nbuf_t
  2374. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2375. qdf_nbuf_t nbuf,
  2376. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2377. {
  2378. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2379. qdf_ether_header_t *eh = NULL;
  2380. struct dp_tx_msdu_info_s msdu_info;
  2381. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2382. DP_MOD_ID_TX_EXCEPTION);
  2383. if (qdf_unlikely(!vdev))
  2384. goto fail;
  2385. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2386. if (!tx_exc_metadata)
  2387. goto fail;
  2388. msdu_info.tid = tx_exc_metadata->tid;
  2389. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2390. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2391. QDF_MAC_ADDR_REF(nbuf->data));
  2392. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2393. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2394. dp_tx_err("Invalid parameters in exception path");
  2395. goto fail;
  2396. }
  2397. /* Basic sanity checks for unsupported packets */
  2398. /* MESH mode */
  2399. if (qdf_unlikely(vdev->mesh_vdev)) {
  2400. dp_tx_err("Mesh mode is not supported in exception path");
  2401. goto fail;
  2402. }
  2403. /*
  2404. * Classify the frame and call corresponding
  2405. * "prepare" function which extracts the segment (TSO)
  2406. * and fragmentation information (for TSO , SG, ME, or Raw)
  2407. * into MSDU_INFO structure which is later used to fill
  2408. * SW and HW descriptors.
  2409. */
  2410. if (qdf_nbuf_is_tso(nbuf)) {
  2411. dp_verbose_debug("TSO frame %pK", vdev);
  2412. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2413. qdf_nbuf_len(nbuf));
  2414. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2415. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2416. qdf_nbuf_len(nbuf));
  2417. goto fail;
  2418. }
  2419. goto send_multiple;
  2420. }
  2421. /* SG */
  2422. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2423. struct dp_tx_seg_info_s seg_info = {0};
  2424. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2425. if (!nbuf)
  2426. goto fail;
  2427. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2428. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2429. qdf_nbuf_len(nbuf));
  2430. goto send_multiple;
  2431. }
  2432. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2433. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2434. qdf_nbuf_len(nbuf));
  2435. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2436. tx_exc_metadata->ppdu_cookie);
  2437. }
  2438. /*
  2439. * Get HW Queue to use for this frame.
  2440. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2441. * dedicated for data and 1 for command.
  2442. * "queue_id" maps to one hardware ring.
  2443. * With each ring, we also associate a unique Tx descriptor pool
  2444. * to minimize lock contention for these resources.
  2445. */
  2446. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2447. /*
  2448. * Check exception descriptors
  2449. */
  2450. if (dp_tx_exception_limit_check(vdev))
  2451. goto fail;
  2452. /* Single linear frame */
  2453. /*
  2454. * If nbuf is a simple linear frame, use send_single function to
  2455. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2456. * SRNG. There is no need to setup a MSDU extension descriptor.
  2457. */
  2458. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2459. tx_exc_metadata->peer_id, tx_exc_metadata);
  2460. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2461. return nbuf;
  2462. send_multiple:
  2463. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2464. fail:
  2465. if (vdev)
  2466. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2467. dp_verbose_debug("pkt send failed");
  2468. return nbuf;
  2469. }
  2470. /**
  2471. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2472. * in exception path in special case to avoid regular exception path chk.
  2473. * @soc: DP soc handle
  2474. * @vdev_id: id of DP vdev handle
  2475. * @nbuf: skb
  2476. * @tx_exc_metadata: Handle that holds exception path meta data
  2477. *
  2478. * Entry point for Core Tx layer (DP_TX) invoked from
  2479. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2480. *
  2481. * Return: NULL on success,
  2482. * nbuf when it fails to send
  2483. */
  2484. qdf_nbuf_t
  2485. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2486. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2487. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2488. {
  2489. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2490. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2491. DP_MOD_ID_TX_EXCEPTION);
  2492. if (qdf_unlikely(!vdev))
  2493. goto fail;
  2494. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2495. == QDF_STATUS_E_FAILURE)) {
  2496. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2497. goto fail;
  2498. }
  2499. /* Unref count as it will agin be taken inside dp_tx_exception */
  2500. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2501. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2502. fail:
  2503. if (vdev)
  2504. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2505. dp_verbose_debug("pkt send failed");
  2506. return nbuf;
  2507. }
  2508. /**
  2509. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2510. * @soc: DP soc handle
  2511. * @vdev_id: DP vdev handle
  2512. * @nbuf: skb
  2513. *
  2514. * Entry point for Core Tx layer (DP_TX) invoked from
  2515. * hard_start_xmit in OSIF/HDD
  2516. *
  2517. * Return: NULL on success,
  2518. * nbuf when it fails to send
  2519. */
  2520. #ifdef MESH_MODE_SUPPORT
  2521. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2522. qdf_nbuf_t nbuf)
  2523. {
  2524. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2525. struct meta_hdr_s *mhdr;
  2526. qdf_nbuf_t nbuf_mesh = NULL;
  2527. qdf_nbuf_t nbuf_clone = NULL;
  2528. struct dp_vdev *vdev;
  2529. uint8_t no_enc_frame = 0;
  2530. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2531. if (!nbuf_mesh) {
  2532. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2533. "qdf_nbuf_unshare failed");
  2534. return nbuf;
  2535. }
  2536. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2537. if (!vdev) {
  2538. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2539. "vdev is NULL for vdev_id %d", vdev_id);
  2540. return nbuf;
  2541. }
  2542. nbuf = nbuf_mesh;
  2543. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2544. if ((vdev->sec_type != cdp_sec_type_none) &&
  2545. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2546. no_enc_frame = 1;
  2547. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2548. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2549. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2550. !no_enc_frame) {
  2551. nbuf_clone = qdf_nbuf_clone(nbuf);
  2552. if (!nbuf_clone) {
  2553. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2554. "qdf_nbuf_clone failed");
  2555. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2556. return nbuf;
  2557. }
  2558. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2559. }
  2560. if (nbuf_clone) {
  2561. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2562. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2563. } else {
  2564. qdf_nbuf_free(nbuf_clone);
  2565. }
  2566. }
  2567. if (no_enc_frame)
  2568. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2569. else
  2570. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2571. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2572. if ((!nbuf) && no_enc_frame) {
  2573. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2574. }
  2575. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2576. return nbuf;
  2577. }
  2578. #else
  2579. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2580. qdf_nbuf_t nbuf)
  2581. {
  2582. return dp_tx_send(soc, vdev_id, nbuf);
  2583. }
  2584. #endif
  2585. /**
  2586. * dp_tx_nawds_handler() - NAWDS handler
  2587. *
  2588. * @soc: DP soc handle
  2589. * @vdev_id: id of DP vdev handle
  2590. * @msdu_info: msdu_info required to create HTT metadata
  2591. * @nbuf: skb
  2592. *
  2593. * This API transfers the multicast frames with the peer id
  2594. * on NAWDS enabled peer.
  2595. * Return: none
  2596. */
  2597. static inline
  2598. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2599. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2600. {
  2601. struct dp_peer *peer = NULL;
  2602. qdf_nbuf_t nbuf_clone = NULL;
  2603. uint16_t peer_id = DP_INVALID_PEER;
  2604. uint16_t sa_peer_id = DP_INVALID_PEER;
  2605. struct dp_ast_entry *ast_entry = NULL;
  2606. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2607. qdf_spin_lock_bh(&soc->ast_lock);
  2608. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2609. (soc,
  2610. (uint8_t *)(eh->ether_shost),
  2611. vdev->pdev->pdev_id);
  2612. if (ast_entry)
  2613. sa_peer_id = ast_entry->peer_id;
  2614. qdf_spin_unlock_bh(&soc->ast_lock);
  2615. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2616. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2617. if (!peer->bss_peer && peer->nawds_enabled) {
  2618. peer_id = peer->peer_id;
  2619. /* Multicast packets needs to be
  2620. * dropped in case of intra bss forwarding
  2621. */
  2622. if (sa_peer_id == peer->peer_id) {
  2623. dp_tx_debug("multicast packet");
  2624. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2625. continue;
  2626. }
  2627. nbuf_clone = qdf_nbuf_clone(nbuf);
  2628. if (!nbuf_clone) {
  2629. QDF_TRACE(QDF_MODULE_ID_DP,
  2630. QDF_TRACE_LEVEL_ERROR,
  2631. FL("nbuf clone failed"));
  2632. break;
  2633. }
  2634. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2635. msdu_info, peer_id,
  2636. NULL);
  2637. if (nbuf_clone) {
  2638. dp_tx_debug("pkt send failed");
  2639. qdf_nbuf_free(nbuf_clone);
  2640. } else {
  2641. if (peer_id != DP_INVALID_PEER)
  2642. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2643. 1, qdf_nbuf_len(nbuf));
  2644. }
  2645. }
  2646. }
  2647. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2648. }
  2649. /**
  2650. * dp_tx_send() - Transmit a frame on a given VAP
  2651. * @soc: DP soc handle
  2652. * @vdev_id: id of DP vdev handle
  2653. * @nbuf: skb
  2654. *
  2655. * Entry point for Core Tx layer (DP_TX) invoked from
  2656. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2657. * cases
  2658. *
  2659. * Return: NULL on success,
  2660. * nbuf when it fails to send
  2661. */
  2662. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2663. qdf_nbuf_t nbuf)
  2664. {
  2665. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2666. uint16_t peer_id = HTT_INVALID_PEER;
  2667. /*
  2668. * doing a memzero is causing additional function call overhead
  2669. * so doing static stack clearing
  2670. */
  2671. struct dp_tx_msdu_info_s msdu_info = {0};
  2672. struct dp_vdev *vdev = NULL;
  2673. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2674. return nbuf;
  2675. /*
  2676. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2677. * this in per packet path.
  2678. *
  2679. * As in this path vdev memory is already protected with netdev
  2680. * tx lock
  2681. */
  2682. vdev = soc->vdev_id_map[vdev_id];
  2683. if (qdf_unlikely(!vdev))
  2684. return nbuf;
  2685. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2686. QDF_MAC_ADDR_REF(nbuf->data));
  2687. /*
  2688. * Set Default Host TID value to invalid TID
  2689. * (TID override disabled)
  2690. */
  2691. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2692. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2693. if (qdf_unlikely(vdev->mesh_vdev)) {
  2694. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2695. &msdu_info);
  2696. if (!nbuf_mesh) {
  2697. dp_verbose_debug("Extracting mesh metadata failed");
  2698. return nbuf;
  2699. }
  2700. nbuf = nbuf_mesh;
  2701. }
  2702. /*
  2703. * Get HW Queue to use for this frame.
  2704. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2705. * dedicated for data and 1 for command.
  2706. * "queue_id" maps to one hardware ring.
  2707. * With each ring, we also associate a unique Tx descriptor pool
  2708. * to minimize lock contention for these resources.
  2709. */
  2710. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2711. /*
  2712. * TCL H/W supports 2 DSCP-TID mapping tables.
  2713. * Table 1 - Default DSCP-TID mapping table
  2714. * Table 2 - 1 DSCP-TID override table
  2715. *
  2716. * If we need a different DSCP-TID mapping for this vap,
  2717. * call tid_classify to extract DSCP/ToS from frame and
  2718. * map to a TID and store in msdu_info. This is later used
  2719. * to fill in TCL Input descriptor (per-packet TID override).
  2720. */
  2721. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2722. /*
  2723. * Classify the frame and call corresponding
  2724. * "prepare" function which extracts the segment (TSO)
  2725. * and fragmentation information (for TSO , SG, ME, or Raw)
  2726. * into MSDU_INFO structure which is later used to fill
  2727. * SW and HW descriptors.
  2728. */
  2729. if (qdf_nbuf_is_tso(nbuf)) {
  2730. dp_verbose_debug("TSO frame %pK", vdev);
  2731. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2732. qdf_nbuf_len(nbuf));
  2733. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2734. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2735. qdf_nbuf_len(nbuf));
  2736. return nbuf;
  2737. }
  2738. goto send_multiple;
  2739. }
  2740. /* SG */
  2741. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2742. struct dp_tx_seg_info_s seg_info = {0};
  2743. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2744. if (!nbuf)
  2745. return NULL;
  2746. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2747. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2748. qdf_nbuf_len(nbuf));
  2749. goto send_multiple;
  2750. }
  2751. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2752. return NULL;
  2753. /* RAW */
  2754. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2755. struct dp_tx_seg_info_s seg_info = {0};
  2756. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2757. if (!nbuf)
  2758. return NULL;
  2759. dp_verbose_debug("Raw frame %pK", vdev);
  2760. goto send_multiple;
  2761. }
  2762. if (qdf_unlikely(vdev->nawds_enabled)) {
  2763. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2764. qdf_nbuf_data(nbuf);
  2765. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2766. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2767. peer_id = DP_INVALID_PEER;
  2768. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2769. 1, qdf_nbuf_len(nbuf));
  2770. }
  2771. /* Single linear frame */
  2772. /*
  2773. * If nbuf is a simple linear frame, use send_single function to
  2774. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2775. * SRNG. There is no need to setup a MSDU extension descriptor.
  2776. */
  2777. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2778. return nbuf;
  2779. send_multiple:
  2780. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2781. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2782. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2783. return nbuf;
  2784. }
  2785. /**
  2786. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2787. * case to vaoid check in perpkt path.
  2788. * @soc: DP soc handle
  2789. * @vdev_id: id of DP vdev handle
  2790. * @nbuf: skb
  2791. *
  2792. * Entry point for Core Tx layer (DP_TX) invoked from
  2793. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2794. * with special condition to avoid per pkt check in dp_tx_send
  2795. *
  2796. * Return: NULL on success,
  2797. * nbuf when it fails to send
  2798. */
  2799. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2800. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2801. {
  2802. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2803. struct dp_vdev *vdev = NULL;
  2804. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2805. return nbuf;
  2806. /*
  2807. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2808. * this in per packet path.
  2809. *
  2810. * As in this path vdev memory is already protected with netdev
  2811. * tx lock
  2812. */
  2813. vdev = soc->vdev_id_map[vdev_id];
  2814. if (qdf_unlikely(!vdev))
  2815. return nbuf;
  2816. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2817. == QDF_STATUS_E_FAILURE)) {
  2818. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2819. return nbuf;
  2820. }
  2821. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2822. }
  2823. #ifdef UMAC_SUPPORT_PROXY_ARP
  2824. /**
  2825. * dp_tx_proxy_arp() - Tx proxy arp handler
  2826. * @vdev: datapath vdev handle
  2827. * @buf: sk buffer
  2828. *
  2829. * Return: status
  2830. */
  2831. static inline
  2832. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2833. {
  2834. if (vdev->osif_proxy_arp)
  2835. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2836. /*
  2837. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2838. * osif_proxy_arp has a valid function pointer assigned
  2839. * to it
  2840. */
  2841. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2842. return QDF_STATUS_NOT_INITIALIZED;
  2843. }
  2844. #else
  2845. /**
  2846. * dp_tx_proxy_arp() - Tx proxy arp handler
  2847. * @vdev: datapath vdev handle
  2848. * @buf: sk buffer
  2849. *
  2850. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2851. * is not defined.
  2852. *
  2853. * Return: status
  2854. */
  2855. static inline
  2856. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2857. {
  2858. return QDF_STATUS_SUCCESS;
  2859. }
  2860. #endif
  2861. /**
  2862. * dp_tx_reinject_handler() - Tx Reinject Handler
  2863. * @soc: datapath soc handle
  2864. * @vdev: datapath vdev handle
  2865. * @tx_desc: software descriptor head pointer
  2866. * @status : Tx completion status from HTT descriptor
  2867. *
  2868. * This function reinjects frames back to Target.
  2869. * Todo - Host queue needs to be added
  2870. *
  2871. * Return: none
  2872. */
  2873. static
  2874. void dp_tx_reinject_handler(struct dp_soc *soc,
  2875. struct dp_vdev *vdev,
  2876. struct dp_tx_desc_s *tx_desc,
  2877. uint8_t *status)
  2878. {
  2879. struct dp_peer *peer = NULL;
  2880. uint32_t peer_id = HTT_INVALID_PEER;
  2881. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2882. qdf_nbuf_t nbuf_copy = NULL;
  2883. struct dp_tx_msdu_info_s msdu_info;
  2884. #ifdef WDS_VENDOR_EXTENSION
  2885. int is_mcast = 0, is_ucast = 0;
  2886. int num_peers_3addr = 0;
  2887. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2888. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2889. #endif
  2890. qdf_assert(vdev);
  2891. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2892. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2893. dp_tx_debug("Tx reinject path");
  2894. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2895. qdf_nbuf_len(tx_desc->nbuf));
  2896. #ifdef WDS_VENDOR_EXTENSION
  2897. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2898. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2899. } else {
  2900. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2901. }
  2902. is_ucast = !is_mcast;
  2903. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2904. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2905. if (peer->bss_peer)
  2906. continue;
  2907. /* Detect wds peers that use 3-addr framing for mcast.
  2908. * if there are any, the bss_peer is used to send the
  2909. * the mcast frame using 3-addr format. all wds enabled
  2910. * peers that use 4-addr framing for mcast frames will
  2911. * be duplicated and sent as 4-addr frames below.
  2912. */
  2913. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2914. num_peers_3addr = 1;
  2915. break;
  2916. }
  2917. }
  2918. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2919. #endif
  2920. if (qdf_unlikely(vdev->mesh_vdev)) {
  2921. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2922. } else {
  2923. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2924. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2925. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2926. #ifdef WDS_VENDOR_EXTENSION
  2927. /*
  2928. * . if 3-addr STA, then send on BSS Peer
  2929. * . if Peer WDS enabled and accept 4-addr mcast,
  2930. * send mcast on that peer only
  2931. * . if Peer WDS enabled and accept 4-addr ucast,
  2932. * send ucast on that peer only
  2933. */
  2934. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2935. (peer->wds_enabled &&
  2936. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2937. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2938. #else
  2939. (peer->bss_peer &&
  2940. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  2941. #endif
  2942. peer_id = DP_INVALID_PEER;
  2943. nbuf_copy = qdf_nbuf_copy(nbuf);
  2944. if (!nbuf_copy) {
  2945. dp_tx_debug("nbuf copy failed");
  2946. break;
  2947. }
  2948. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2949. nbuf_copy,
  2950. &msdu_info,
  2951. peer_id,
  2952. NULL);
  2953. if (nbuf_copy) {
  2954. dp_tx_debug("pkt send failed");
  2955. qdf_nbuf_free(nbuf_copy);
  2956. }
  2957. }
  2958. }
  2959. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2960. }
  2961. qdf_nbuf_free(nbuf);
  2962. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2963. }
  2964. /**
  2965. * dp_tx_inspect_handler() - Tx Inspect Handler
  2966. * @soc: datapath soc handle
  2967. * @vdev: datapath vdev handle
  2968. * @tx_desc: software descriptor head pointer
  2969. * @status : Tx completion status from HTT descriptor
  2970. *
  2971. * Handles Tx frames sent back to Host for inspection
  2972. * (ProxyARP)
  2973. *
  2974. * Return: none
  2975. */
  2976. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2977. struct dp_vdev *vdev,
  2978. struct dp_tx_desc_s *tx_desc,
  2979. uint8_t *status)
  2980. {
  2981. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2982. "%s Tx inspect path",
  2983. __func__);
  2984. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2985. qdf_nbuf_len(tx_desc->nbuf));
  2986. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2987. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2988. }
  2989. #ifdef MESH_MODE_SUPPORT
  2990. /**
  2991. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2992. * in mesh meta header
  2993. * @tx_desc: software descriptor head pointer
  2994. * @ts: pointer to tx completion stats
  2995. * Return: none
  2996. */
  2997. static
  2998. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2999. struct hal_tx_completion_status *ts)
  3000. {
  3001. struct meta_hdr_s *mhdr;
  3002. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3003. if (!tx_desc->msdu_ext_desc) {
  3004. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3006. "netbuf %pK offset %d",
  3007. netbuf, tx_desc->pkt_offset);
  3008. return;
  3009. }
  3010. }
  3011. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3012. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3013. "netbuf %pK offset %zu", netbuf,
  3014. sizeof(struct meta_hdr_s));
  3015. return;
  3016. }
  3017. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3018. mhdr->rssi = ts->ack_frame_rssi;
  3019. mhdr->band = tx_desc->pdev->operating_channel.band;
  3020. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3021. }
  3022. #else
  3023. static
  3024. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3025. struct hal_tx_completion_status *ts)
  3026. {
  3027. }
  3028. #endif
  3029. #ifdef QCA_PEER_EXT_STATS
  3030. /*
  3031. * dp_tx_compute_tid_delay() - Compute per TID delay
  3032. * @stats: Per TID delay stats
  3033. * @tx_desc: Software Tx descriptor
  3034. *
  3035. * Compute the software enqueue and hw enqueue delays and
  3036. * update the respective histograms
  3037. *
  3038. * Return: void
  3039. */
  3040. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3041. struct dp_tx_desc_s *tx_desc)
  3042. {
  3043. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3044. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3045. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3046. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3047. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3048. timestamp_hw_enqueue = tx_desc->timestamp;
  3049. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3050. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3051. timestamp_hw_enqueue);
  3052. /*
  3053. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3054. */
  3055. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3056. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3057. }
  3058. /*
  3059. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3060. * @peer: DP peer context
  3061. * @tx_desc: Tx software descriptor
  3062. * @tid: Transmission ID
  3063. * @ring_id: Rx CPU context ID/CPU_ID
  3064. *
  3065. * Update the peer extended stats. These are enhanced other
  3066. * delay stats per msdu level.
  3067. *
  3068. * Return: void
  3069. */
  3070. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3071. struct dp_tx_desc_s *tx_desc,
  3072. uint8_t tid, uint8_t ring_id)
  3073. {
  3074. struct dp_pdev *pdev = peer->vdev->pdev;
  3075. struct dp_soc *soc = NULL;
  3076. struct cdp_peer_ext_stats *pext_stats = NULL;
  3077. soc = pdev->soc;
  3078. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3079. return;
  3080. pext_stats = peer->pext_stats;
  3081. qdf_assert(pext_stats);
  3082. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3083. /*
  3084. * For non-TID packets use the TID 9
  3085. */
  3086. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3087. tid = CDP_MAX_DATA_TIDS - 1;
  3088. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3089. tx_desc);
  3090. }
  3091. #else
  3092. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3093. struct dp_tx_desc_s *tx_desc,
  3094. uint8_t tid, uint8_t ring_id)
  3095. {
  3096. }
  3097. #endif
  3098. /**
  3099. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3100. * to pass in correct fields
  3101. *
  3102. * @vdev: pdev handle
  3103. * @tx_desc: tx descriptor
  3104. * @tid: tid value
  3105. * @ring_id: TCL or WBM ring number for transmit path
  3106. * Return: none
  3107. */
  3108. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3109. struct dp_tx_desc_s *tx_desc,
  3110. uint8_t tid, uint8_t ring_id)
  3111. {
  3112. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3113. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3114. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3115. return;
  3116. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3117. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3118. timestamp_hw_enqueue = tx_desc->timestamp;
  3119. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3120. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3121. timestamp_hw_enqueue);
  3122. interframe_delay = (uint32_t)(timestamp_ingress -
  3123. vdev->prev_tx_enq_tstamp);
  3124. /*
  3125. * Delay in software enqueue
  3126. */
  3127. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3128. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3129. /*
  3130. * Delay between packet enqueued to HW and Tx completion
  3131. */
  3132. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3133. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3134. /*
  3135. * Update interframe delay stats calculated at hardstart receive point.
  3136. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3137. * interframe delay will not be calculate correctly for 1st frame.
  3138. * On the other side, this will help in avoiding extra per packet check
  3139. * of !vdev->prev_tx_enq_tstamp.
  3140. */
  3141. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3142. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3143. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3144. }
  3145. #ifdef DISABLE_DP_STATS
  3146. static
  3147. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3148. {
  3149. }
  3150. #else
  3151. static
  3152. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3153. {
  3154. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3155. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3156. if (subtype != QDF_PROTO_INVALID)
  3157. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3158. }
  3159. #endif
  3160. /**
  3161. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3162. * per wbm ring
  3163. *
  3164. * @tx_desc: software descriptor head pointer
  3165. * @ts: Tx completion status
  3166. * @peer: peer handle
  3167. * @ring_id: ring number
  3168. *
  3169. * Return: None
  3170. */
  3171. static inline void
  3172. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3173. struct hal_tx_completion_status *ts,
  3174. struct dp_peer *peer, uint8_t ring_id)
  3175. {
  3176. struct dp_pdev *pdev = peer->vdev->pdev;
  3177. struct dp_soc *soc = NULL;
  3178. uint8_t mcs, pkt_type;
  3179. uint8_t tid = ts->tid;
  3180. uint32_t length;
  3181. struct cdp_tid_tx_stats *tid_stats;
  3182. if (!pdev)
  3183. return;
  3184. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3185. tid = CDP_MAX_DATA_TIDS - 1;
  3186. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3187. soc = pdev->soc;
  3188. mcs = ts->mcs;
  3189. pkt_type = ts->pkt_type;
  3190. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3191. dp_err("Release source is not from TQM");
  3192. return;
  3193. }
  3194. length = qdf_nbuf_len(tx_desc->nbuf);
  3195. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3196. if (qdf_unlikely(pdev->delay_stats_flag))
  3197. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3198. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3199. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3200. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3201. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3202. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3203. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3204. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3205. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3206. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3207. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3208. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3209. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3210. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3211. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3212. /*
  3213. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3214. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3215. * are no completions for failed cases. Hence updating tx_failed from
  3216. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3217. * then this has to be removed
  3218. */
  3219. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3220. peer->stats.tx.dropped.fw_rem_notx +
  3221. peer->stats.tx.dropped.fw_rem_tx +
  3222. peer->stats.tx.dropped.age_out +
  3223. peer->stats.tx.dropped.fw_reason1 +
  3224. peer->stats.tx.dropped.fw_reason2 +
  3225. peer->stats.tx.dropped.fw_reason3;
  3226. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3227. tid_stats->tqm_status_cnt[ts->status]++;
  3228. }
  3229. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3230. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3231. return;
  3232. }
  3233. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3234. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3235. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3236. /*
  3237. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3238. * Return from here if HTT PPDU events are enabled.
  3239. */
  3240. if (!(soc->process_tx_status))
  3241. return;
  3242. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3243. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3244. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3245. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3246. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3247. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3248. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3249. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3250. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3251. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3252. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3253. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3254. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3255. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3256. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3257. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3258. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3259. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3260. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3261. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3262. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3263. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3264. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3265. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3266. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3267. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3268. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3269. }
  3270. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3271. /**
  3272. * dp_tx_flow_pool_lock() - take flow pool lock
  3273. * @soc: core txrx main context
  3274. * @tx_desc: tx desc
  3275. *
  3276. * Return: None
  3277. */
  3278. static inline
  3279. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3280. struct dp_tx_desc_s *tx_desc)
  3281. {
  3282. struct dp_tx_desc_pool_s *pool;
  3283. uint8_t desc_pool_id;
  3284. desc_pool_id = tx_desc->pool_id;
  3285. pool = &soc->tx_desc[desc_pool_id];
  3286. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3287. }
  3288. /**
  3289. * dp_tx_flow_pool_unlock() - release flow pool lock
  3290. * @soc: core txrx main context
  3291. * @tx_desc: tx desc
  3292. *
  3293. * Return: None
  3294. */
  3295. static inline
  3296. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3297. struct dp_tx_desc_s *tx_desc)
  3298. {
  3299. struct dp_tx_desc_pool_s *pool;
  3300. uint8_t desc_pool_id;
  3301. desc_pool_id = tx_desc->pool_id;
  3302. pool = &soc->tx_desc[desc_pool_id];
  3303. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3304. }
  3305. #else
  3306. static inline
  3307. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3308. {
  3309. }
  3310. static inline
  3311. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3312. {
  3313. }
  3314. #endif
  3315. /**
  3316. * dp_tx_notify_completion() - Notify tx completion for this desc
  3317. * @soc: core txrx main context
  3318. * @vdev: datapath vdev handle
  3319. * @tx_desc: tx desc
  3320. * @netbuf: buffer
  3321. * @status: tx status
  3322. *
  3323. * Return: none
  3324. */
  3325. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3326. struct dp_vdev *vdev,
  3327. struct dp_tx_desc_s *tx_desc,
  3328. qdf_nbuf_t netbuf,
  3329. uint8_t status)
  3330. {
  3331. void *osif_dev;
  3332. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3333. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3334. qdf_assert(tx_desc);
  3335. dp_tx_flow_pool_lock(soc, tx_desc);
  3336. if (!vdev ||
  3337. !vdev->osif_vdev) {
  3338. dp_tx_flow_pool_unlock(soc, tx_desc);
  3339. return;
  3340. }
  3341. osif_dev = vdev->osif_vdev;
  3342. tx_compl_cbk = vdev->tx_comp;
  3343. dp_tx_flow_pool_unlock(soc, tx_desc);
  3344. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3345. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3346. if (tx_compl_cbk)
  3347. tx_compl_cbk(netbuf, osif_dev, flag);
  3348. }
  3349. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3350. * @pdev: pdev handle
  3351. * @tid: tid value
  3352. * @txdesc_ts: timestamp from txdesc
  3353. * @ppdu_id: ppdu id
  3354. *
  3355. * Return: none
  3356. */
  3357. #ifdef FEATURE_PERPKT_INFO
  3358. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3359. struct dp_peer *peer,
  3360. uint8_t tid,
  3361. uint64_t txdesc_ts,
  3362. uint32_t ppdu_id)
  3363. {
  3364. uint64_t delta_ms;
  3365. struct cdp_tx_sojourn_stats *sojourn_stats;
  3366. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3367. return;
  3368. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3369. tid >= CDP_DATA_TID_MAX))
  3370. return;
  3371. if (qdf_unlikely(!pdev->sojourn_buf))
  3372. return;
  3373. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3374. qdf_nbuf_data(pdev->sojourn_buf);
  3375. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3376. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3377. txdesc_ts;
  3378. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3379. delta_ms);
  3380. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3381. sojourn_stats->num_msdus[tid] = 1;
  3382. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3383. peer->avg_sojourn_msdu[tid].internal;
  3384. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3385. pdev->sojourn_buf, HTT_INVALID_PEER,
  3386. WDI_NO_VAL, pdev->pdev_id);
  3387. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3388. sojourn_stats->num_msdus[tid] = 0;
  3389. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3390. }
  3391. #else
  3392. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3393. struct dp_peer *peer,
  3394. uint8_t tid,
  3395. uint64_t txdesc_ts,
  3396. uint32_t ppdu_id)
  3397. {
  3398. }
  3399. #endif
  3400. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3401. /**
  3402. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3403. * @soc: dp_soc handle
  3404. * @desc: Tx Descriptor
  3405. * @ts: HAL Tx completion descriptor contents
  3406. *
  3407. * This function is used to send tx completion to packet capture
  3408. */
  3409. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3410. struct dp_tx_desc_s *desc,
  3411. struct hal_tx_completion_status *ts)
  3412. {
  3413. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3414. desc, ts->peer_id,
  3415. WDI_NO_VAL, desc->pdev->pdev_id);
  3416. }
  3417. #endif
  3418. /**
  3419. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3420. * @soc: DP Soc handle
  3421. * @tx_desc: software Tx descriptor
  3422. * @ts : Tx completion status from HAL/HTT descriptor
  3423. *
  3424. * Return: none
  3425. */
  3426. static inline void
  3427. dp_tx_comp_process_desc(struct dp_soc *soc,
  3428. struct dp_tx_desc_s *desc,
  3429. struct hal_tx_completion_status *ts,
  3430. struct dp_peer *peer)
  3431. {
  3432. uint64_t time_latency = 0;
  3433. /*
  3434. * m_copy/tx_capture modes are not supported for
  3435. * scatter gather packets
  3436. */
  3437. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3438. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3439. desc->timestamp);
  3440. }
  3441. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3442. if (!(desc->msdu_ext_desc)) {
  3443. dp_tx_enh_unmap(soc, desc);
  3444. if (QDF_STATUS_SUCCESS ==
  3445. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3446. return;
  3447. }
  3448. if (QDF_STATUS_SUCCESS ==
  3449. dp_get_completion_indication_for_stack(soc,
  3450. desc->pdev,
  3451. peer, ts,
  3452. desc->nbuf,
  3453. time_latency)) {
  3454. dp_send_completion_to_stack(soc,
  3455. desc->pdev,
  3456. ts->peer_id,
  3457. ts->ppdu_id,
  3458. desc->nbuf);
  3459. return;
  3460. }
  3461. }
  3462. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3463. dp_tx_comp_free_buf(soc, desc);
  3464. }
  3465. #ifdef DISABLE_DP_STATS
  3466. /**
  3467. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3468. * @soc: core txrx main context
  3469. * @tx_desc: tx desc
  3470. * @status: tx status
  3471. *
  3472. * Return: none
  3473. */
  3474. static inline
  3475. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3476. struct dp_vdev *vdev,
  3477. struct dp_tx_desc_s *tx_desc,
  3478. uint8_t status)
  3479. {
  3480. }
  3481. #else
  3482. static inline
  3483. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3484. struct dp_vdev *vdev,
  3485. struct dp_tx_desc_s *tx_desc,
  3486. uint8_t status)
  3487. {
  3488. void *osif_dev;
  3489. ol_txrx_stats_rx_fp stats_cbk;
  3490. uint8_t pkt_type;
  3491. qdf_assert(tx_desc);
  3492. if (!vdev ||
  3493. !vdev->osif_vdev ||
  3494. !vdev->stats_cb)
  3495. return;
  3496. osif_dev = vdev->osif_vdev;
  3497. stats_cbk = vdev->stats_cb;
  3498. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3499. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3500. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3501. &pkt_type);
  3502. }
  3503. #endif
  3504. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3505. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3506. uint32_t delta_tsf)
  3507. {
  3508. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3509. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3510. DP_MOD_ID_CDP);
  3511. if (!vdev) {
  3512. dp_err_rl("vdev %d does not exist", vdev_id);
  3513. return;
  3514. }
  3515. vdev->delta_tsf = delta_tsf;
  3516. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3517. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3518. }
  3519. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3520. uint8_t vdev_id, bool enable)
  3521. {
  3522. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3523. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3524. DP_MOD_ID_CDP);
  3525. if (!vdev) {
  3526. dp_err_rl("vdev %d does not exist", vdev_id);
  3527. return QDF_STATUS_E_FAILURE;
  3528. }
  3529. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3530. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3531. return QDF_STATUS_SUCCESS;
  3532. }
  3533. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3534. uint32_t *val)
  3535. {
  3536. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3537. struct dp_vdev *vdev;
  3538. uint32_t delay_accum;
  3539. uint32_t pkts_accum;
  3540. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3541. if (!vdev) {
  3542. dp_err_rl("vdev %d does not exist", vdev_id);
  3543. return QDF_STATUS_E_FAILURE;
  3544. }
  3545. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3546. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3547. return QDF_STATUS_E_FAILURE;
  3548. }
  3549. /* Average uplink delay based on current accumulated values */
  3550. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3551. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3552. *val = delay_accum / pkts_accum;
  3553. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3554. delay_accum, pkts_accum);
  3555. /* Reset accumulated values to 0 */
  3556. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3557. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3558. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3559. return QDF_STATUS_SUCCESS;
  3560. }
  3561. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3562. struct hal_tx_completion_status *ts)
  3563. {
  3564. uint32_t buffer_ts;
  3565. uint32_t delta_tsf;
  3566. uint32_t ul_delay;
  3567. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3568. if (!ts->valid)
  3569. return;
  3570. if (qdf_unlikely(!vdev)) {
  3571. dp_info_rl("vdev is null or delete in progrss");
  3572. return;
  3573. }
  3574. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3575. return;
  3576. delta_tsf = vdev->delta_tsf;
  3577. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3578. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3579. * valid up to 29 bits.
  3580. */
  3581. buffer_ts = ts->buffer_timestamp << 10;
  3582. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3583. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3584. if (ul_delay > 0x1000000) {
  3585. dp_info_rl("----------------------\n"
  3586. "Tx completion status:\n"
  3587. "----------------------\n"
  3588. "release_src = %d\n"
  3589. "ppdu_id = 0x%x\n"
  3590. "release_reason = %d\n"
  3591. "tsf = %u (0x%x)\n"
  3592. "buffer_timestamp = %u (0x%x)\n"
  3593. "delta_tsf = %u (0x%x)\n",
  3594. ts->release_src, ts->ppdu_id, ts->status,
  3595. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3596. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3597. return;
  3598. }
  3599. ul_delay /= 1000; /* in unit of ms */
  3600. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3601. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3602. }
  3603. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3604. static inline
  3605. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3606. struct hal_tx_completion_status *ts)
  3607. {
  3608. }
  3609. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3610. /**
  3611. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3612. * @soc: DP soc handle
  3613. * @tx_desc: software descriptor head pointer
  3614. * @ts: Tx completion status
  3615. * @peer: peer handle
  3616. * @ring_id: ring number
  3617. *
  3618. * Return: none
  3619. */
  3620. static inline
  3621. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3622. struct dp_tx_desc_s *tx_desc,
  3623. struct hal_tx_completion_status *ts,
  3624. struct dp_peer *peer, uint8_t ring_id)
  3625. {
  3626. uint32_t length;
  3627. qdf_ether_header_t *eh;
  3628. struct dp_vdev *vdev = NULL;
  3629. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3630. enum qdf_dp_tx_rx_status dp_status;
  3631. if (!nbuf) {
  3632. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3633. goto out;
  3634. }
  3635. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3636. length = qdf_nbuf_len(nbuf);
  3637. dp_status = dp_tx_hw_to_qdf(ts->status);
  3638. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3639. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3640. QDF_TRACE_DEFAULT_PDEV_ID,
  3641. qdf_nbuf_data_addr(nbuf),
  3642. sizeof(qdf_nbuf_data(nbuf)),
  3643. tx_desc->id, ts->status, dp_status));
  3644. dp_tx_comp_debug("-------------------- \n"
  3645. "Tx Completion Stats: \n"
  3646. "-------------------- \n"
  3647. "ack_frame_rssi = %d \n"
  3648. "first_msdu = %d \n"
  3649. "last_msdu = %d \n"
  3650. "msdu_part_of_amsdu = %d \n"
  3651. "rate_stats valid = %d \n"
  3652. "bw = %d \n"
  3653. "pkt_type = %d \n"
  3654. "stbc = %d \n"
  3655. "ldpc = %d \n"
  3656. "sgi = %d \n"
  3657. "mcs = %d \n"
  3658. "ofdma = %d \n"
  3659. "tones_in_ru = %d \n"
  3660. "tsf = %d \n"
  3661. "ppdu_id = %d \n"
  3662. "transmit_cnt = %d \n"
  3663. "tid = %d \n"
  3664. "peer_id = %d\n",
  3665. ts->ack_frame_rssi, ts->first_msdu,
  3666. ts->last_msdu, ts->msdu_part_of_amsdu,
  3667. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3668. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3669. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3670. ts->transmit_cnt, ts->tid, ts->peer_id);
  3671. /* Update SoC level stats */
  3672. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3673. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3674. if (!peer) {
  3675. dp_info_rl("peer is null or deletion in progress");
  3676. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3677. goto out;
  3678. }
  3679. vdev = peer->vdev;
  3680. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3681. dp_tx_update_uplink_delay(soc, vdev, ts);
  3682. /* Update per-packet stats for mesh mode */
  3683. if (qdf_unlikely(vdev->mesh_vdev) &&
  3684. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3685. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3686. /* Update peer level stats */
  3687. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3688. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3689. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3690. if ((peer->vdev->tx_encap_type ==
  3691. htt_cmn_pkt_type_ethernet) &&
  3692. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3693. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3694. }
  3695. }
  3696. } else {
  3697. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3698. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3699. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3700. if (qdf_unlikely(peer->in_twt)) {
  3701. DP_STATS_INC_PKT(peer,
  3702. tx.tx_success_twt,
  3703. 1, length);
  3704. }
  3705. }
  3706. }
  3707. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3708. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3709. #ifdef QCA_SUPPORT_RDK_STATS
  3710. if (soc->rdkstats_enabled)
  3711. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3712. tx_desc->timestamp,
  3713. ts->ppdu_id);
  3714. #endif
  3715. out:
  3716. return;
  3717. }
  3718. /**
  3719. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3720. * @soc: core txrx main context
  3721. * @comp_head: software descriptor head pointer
  3722. * @ring_id: ring number
  3723. *
  3724. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3725. * and release the software descriptors after processing is complete
  3726. *
  3727. * Return: none
  3728. */
  3729. static void
  3730. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3731. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3732. {
  3733. struct dp_tx_desc_s *desc;
  3734. struct dp_tx_desc_s *next;
  3735. struct hal_tx_completion_status ts;
  3736. struct dp_peer *peer = NULL;
  3737. uint16_t peer_id = DP_INVALID_PEER;
  3738. qdf_nbuf_t netbuf;
  3739. desc = comp_head;
  3740. while (desc) {
  3741. if (peer_id != desc->peer_id) {
  3742. if (peer)
  3743. dp_peer_unref_delete(peer,
  3744. DP_MOD_ID_TX_COMP);
  3745. peer_id = desc->peer_id;
  3746. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3747. DP_MOD_ID_TX_COMP);
  3748. }
  3749. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3750. struct dp_pdev *pdev = desc->pdev;
  3751. if (qdf_likely(peer)) {
  3752. /*
  3753. * Increment peer statistics
  3754. * Minimal statistics update done here
  3755. */
  3756. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3757. desc->length);
  3758. if (desc->tx_status !=
  3759. HAL_TX_TQM_RR_FRAME_ACKED)
  3760. DP_STATS_INC(peer, tx.tx_failed, 1);
  3761. }
  3762. qdf_assert(pdev);
  3763. dp_tx_outstanding_dec(pdev);
  3764. /*
  3765. * Calling a QDF WRAPPER here is creating signifcant
  3766. * performance impact so avoided the wrapper call here
  3767. */
  3768. next = desc->next;
  3769. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3770. desc->id, DP_TX_COMP_UNMAP);
  3771. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3772. desc->nbuf,
  3773. desc->dma_addr,
  3774. QDF_DMA_TO_DEVICE,
  3775. desc->length);
  3776. qdf_nbuf_free(desc->nbuf);
  3777. dp_tx_desc_free(soc, desc, desc->pool_id);
  3778. desc = next;
  3779. continue;
  3780. }
  3781. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3782. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3783. netbuf = desc->nbuf;
  3784. /* check tx complete notification */
  3785. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3786. dp_tx_notify_completion(soc, peer->vdev, desc,
  3787. netbuf, ts.status);
  3788. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3789. next = desc->next;
  3790. dp_tx_desc_release(desc, desc->pool_id);
  3791. desc = next;
  3792. }
  3793. if (peer)
  3794. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3795. }
  3796. /**
  3797. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3798. * @soc: Handle to DP soc structure
  3799. * @tx_desc: software descriptor head pointer
  3800. * @status : Tx completion status from HTT descriptor
  3801. * @ring_id: ring number
  3802. *
  3803. * This function will process HTT Tx indication messages from Target
  3804. *
  3805. * Return: none
  3806. */
  3807. static
  3808. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3809. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3810. uint8_t ring_id)
  3811. {
  3812. uint8_t tx_status;
  3813. struct dp_pdev *pdev;
  3814. struct dp_vdev *vdev;
  3815. struct hal_tx_completion_status ts = {0};
  3816. uint32_t *htt_desc = (uint32_t *)status;
  3817. struct dp_peer *peer;
  3818. struct cdp_tid_tx_stats *tid_stats = NULL;
  3819. struct htt_soc *htt_handle;
  3820. uint8_t vdev_id;
  3821. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3822. htt_handle = (struct htt_soc *)soc->htt_handle;
  3823. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3824. /*
  3825. * There can be scenario where WBM consuming descriptor enqueued
  3826. * from TQM2WBM first and TQM completion can happen before MEC
  3827. * notification comes from FW2WBM. Avoid access any field of tx
  3828. * descriptor in case of MEC notify.
  3829. */
  3830. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3831. /*
  3832. * Get vdev id from HTT status word in case of MEC
  3833. * notification
  3834. */
  3835. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3836. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3837. return;
  3838. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3839. DP_MOD_ID_HTT_COMP);
  3840. if (!vdev)
  3841. return;
  3842. dp_tx_mec_handler(vdev, status);
  3843. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3844. return;
  3845. }
  3846. /*
  3847. * If the descriptor is already freed in vdev_detach,
  3848. * continue to next descriptor
  3849. */
  3850. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3851. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3852. return;
  3853. }
  3854. pdev = tx_desc->pdev;
  3855. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3856. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3857. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3858. dp_tx_comp_free_buf(soc, tx_desc);
  3859. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3860. return;
  3861. }
  3862. qdf_assert(tx_desc->pdev);
  3863. vdev_id = tx_desc->vdev_id;
  3864. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3865. DP_MOD_ID_HTT_COMP);
  3866. if (!vdev)
  3867. return;
  3868. switch (tx_status) {
  3869. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3870. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3871. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3872. {
  3873. uint8_t tid;
  3874. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3875. ts.peer_id =
  3876. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3877. htt_desc[2]);
  3878. ts.tid =
  3879. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3880. htt_desc[2]);
  3881. } else {
  3882. ts.peer_id = HTT_INVALID_PEER;
  3883. ts.tid = HTT_INVALID_TID;
  3884. }
  3885. ts.ppdu_id =
  3886. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3887. htt_desc[1]);
  3888. ts.ack_frame_rssi =
  3889. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3890. htt_desc[1]);
  3891. ts.tsf = htt_desc[3];
  3892. ts.first_msdu = 1;
  3893. ts.last_msdu = 1;
  3894. tid = ts.tid;
  3895. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3896. tid = CDP_MAX_DATA_TIDS - 1;
  3897. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3898. if (qdf_unlikely(pdev->delay_stats_flag))
  3899. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3900. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3901. tid_stats->htt_status_cnt[tx_status]++;
  3902. }
  3903. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3904. DP_MOD_ID_HTT_COMP);
  3905. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3906. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3907. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3908. if (qdf_likely(peer))
  3909. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3910. break;
  3911. }
  3912. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3913. {
  3914. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3915. break;
  3916. }
  3917. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3918. {
  3919. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3920. break;
  3921. }
  3922. default:
  3923. dp_tx_comp_debug("Invalid HTT tx_status %d\n",
  3924. tx_status);
  3925. break;
  3926. }
  3927. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3928. }
  3929. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3930. static inline
  3931. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3932. int max_reap_limit)
  3933. {
  3934. bool limit_hit = false;
  3935. limit_hit =
  3936. (num_reaped >= max_reap_limit) ? true : false;
  3937. if (limit_hit)
  3938. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3939. return limit_hit;
  3940. }
  3941. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3942. {
  3943. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3944. }
  3945. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3946. {
  3947. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3948. return cfg->tx_comp_loop_pkt_limit;
  3949. }
  3950. #else
  3951. static inline
  3952. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3953. int max_reap_limit)
  3954. {
  3955. return false;
  3956. }
  3957. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3958. {
  3959. return false;
  3960. }
  3961. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3962. {
  3963. return 0;
  3964. }
  3965. #endif
  3966. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  3967. static inline int
  3968. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3969. int *max_reap_limit)
  3970. {
  3971. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  3972. max_reap_limit);
  3973. }
  3974. #else
  3975. static inline int
  3976. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3977. int *max_reap_limit)
  3978. {
  3979. return 0;
  3980. }
  3981. #endif
  3982. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3983. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3984. uint32_t quota)
  3985. {
  3986. void *tx_comp_hal_desc;
  3987. uint8_t buffer_src;
  3988. struct dp_tx_desc_s *tx_desc = NULL;
  3989. struct dp_tx_desc_s *head_desc = NULL;
  3990. struct dp_tx_desc_s *tail_desc = NULL;
  3991. uint32_t num_processed = 0;
  3992. uint32_t count;
  3993. uint32_t num_avail_for_reap = 0;
  3994. bool force_break = false;
  3995. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  3996. int max_reap_limit, ring_near_full;
  3997. DP_HIST_INIT();
  3998. more_data:
  3999. /* Re-initialize local variables to be re-used */
  4000. head_desc = NULL;
  4001. tail_desc = NULL;
  4002. count = 0;
  4003. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4004. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4005. &max_reap_limit);
  4006. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4007. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4008. return 0;
  4009. }
  4010. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  4011. if (num_avail_for_reap >= quota)
  4012. num_avail_for_reap = quota;
  4013. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4014. /* Find head descriptor from completion ring */
  4015. while (qdf_likely(num_avail_for_reap--)) {
  4016. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4017. if (qdf_unlikely(!tx_comp_hal_desc))
  4018. break;
  4019. buffer_src = hal_tx_comp_get_buffer_source(soc->hal_soc,
  4020. tx_comp_hal_desc);
  4021. /* If this buffer was not released by TQM or FW, then it is not
  4022. * Tx completion indication, assert */
  4023. if (qdf_unlikely(buffer_src !=
  4024. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4025. (qdf_unlikely(buffer_src !=
  4026. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4027. uint8_t wbm_internal_error;
  4028. dp_err_rl(
  4029. "Tx comp release_src != TQM | FW but from %d",
  4030. buffer_src);
  4031. hal_dump_comp_desc(tx_comp_hal_desc);
  4032. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4033. /* When WBM sees NULL buffer_addr_info in any of
  4034. * ingress rings it sends an error indication,
  4035. * with wbm_internal_error=1, to a specific ring.
  4036. * The WBM2SW ring used to indicate these errors is
  4037. * fixed in HW, and that ring is being used as Tx
  4038. * completion ring. These errors are not related to
  4039. * Tx completions, and should just be ignored
  4040. */
  4041. wbm_internal_error = hal_get_wbm_internal_error(
  4042. soc->hal_soc,
  4043. tx_comp_hal_desc);
  4044. if (wbm_internal_error) {
  4045. dp_err_rl("Tx comp wbm_internal_error!!");
  4046. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4047. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4048. buffer_src)
  4049. dp_handle_wbm_internal_error(
  4050. soc,
  4051. tx_comp_hal_desc,
  4052. hal_tx_comp_get_buffer_type(
  4053. tx_comp_hal_desc));
  4054. } else {
  4055. dp_err_rl("Tx comp wbm_internal_error false");
  4056. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4057. }
  4058. continue;
  4059. }
  4060. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4061. tx_comp_hal_desc,
  4062. &tx_desc);
  4063. if (!tx_desc) {
  4064. dp_err("unable to retrieve tx_desc!");
  4065. QDF_BUG(0);
  4066. continue;
  4067. }
  4068. tx_desc->buffer_src = buffer_src;
  4069. /*
  4070. * If the release source is FW, process the HTT status
  4071. */
  4072. if (qdf_unlikely(buffer_src ==
  4073. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4074. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4075. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4076. htt_tx_status);
  4077. dp_tx_process_htt_completion(soc, tx_desc,
  4078. htt_tx_status, ring_id);
  4079. } else {
  4080. tx_desc->peer_id =
  4081. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  4082. tx_desc->tx_status =
  4083. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4084. tx_desc->buffer_src = buffer_src;
  4085. /*
  4086. * If the fast completion mode is enabled extended
  4087. * metadata from descriptor is not copied
  4088. */
  4089. if (qdf_likely(tx_desc->flags &
  4090. DP_TX_DESC_FLAG_SIMPLE))
  4091. goto add_to_pool;
  4092. /*
  4093. * If the descriptor is already freed in vdev_detach,
  4094. * continue to next descriptor
  4095. */
  4096. if (qdf_unlikely
  4097. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4098. !tx_desc->flags)) {
  4099. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4100. tx_desc->id);
  4101. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4102. continue;
  4103. }
  4104. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4105. dp_tx_comp_info_rl("pdev in down state %d",
  4106. tx_desc->id);
  4107. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4108. dp_tx_comp_free_buf(soc, tx_desc);
  4109. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4110. goto next_desc;
  4111. }
  4112. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4113. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4114. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4115. tx_desc->flags, tx_desc->id);
  4116. qdf_assert_always(0);
  4117. }
  4118. /* Collect hw completion contents */
  4119. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4120. &tx_desc->comp, 1);
  4121. add_to_pool:
  4122. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4123. /* First ring descriptor on the cycle */
  4124. if (!head_desc) {
  4125. head_desc = tx_desc;
  4126. tail_desc = tx_desc;
  4127. }
  4128. tail_desc->next = tx_desc;
  4129. tx_desc->next = NULL;
  4130. tail_desc = tx_desc;
  4131. }
  4132. next_desc:
  4133. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4134. /*
  4135. * Processed packet count is more than given quota
  4136. * stop to processing
  4137. */
  4138. count++;
  4139. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4140. break;
  4141. }
  4142. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4143. /* Process the reaped descriptors */
  4144. if (head_desc)
  4145. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4146. /*
  4147. * If we are processing in near-full condition, there are 3 scenario
  4148. * 1) Ring entries has reached critical state
  4149. * 2) Ring entries are still near high threshold
  4150. * 3) Ring entries are below the safe level
  4151. *
  4152. * One more loop will move te state to normal processing and yield
  4153. */
  4154. if (ring_near_full)
  4155. goto more_data;
  4156. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4157. if (num_processed >= quota)
  4158. force_break = true;
  4159. if (!force_break &&
  4160. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4161. hal_ring_hdl)) {
  4162. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4163. if (!hif_exec_should_yield(soc->hif_handle,
  4164. int_ctx->dp_intr_id))
  4165. goto more_data;
  4166. }
  4167. }
  4168. DP_TX_HIST_STATS_PER_PDEV();
  4169. return num_processed;
  4170. }
  4171. #ifdef FEATURE_WLAN_TDLS
  4172. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4173. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4174. {
  4175. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4176. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4177. DP_MOD_ID_TDLS);
  4178. if (!vdev) {
  4179. dp_err("vdev handle for id %d is NULL", vdev_id);
  4180. return NULL;
  4181. }
  4182. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4183. vdev->is_tdls_frame = true;
  4184. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4185. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4186. }
  4187. #endif
  4188. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4189. {
  4190. struct wlan_cfg_dp_soc_ctxt *cfg;
  4191. struct dp_soc *soc;
  4192. soc = vdev->pdev->soc;
  4193. if (!soc)
  4194. return;
  4195. cfg = soc->wlan_cfg_ctx;
  4196. if (!cfg)
  4197. return;
  4198. if (vdev->opmode == wlan_op_mode_ndi)
  4199. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4200. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4201. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4202. (vdev->subtype == wlan_op_subtype_p2p_go))
  4203. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4204. else
  4205. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4206. }
  4207. /**
  4208. * dp_tx_vdev_attach() - attach vdev to dp tx
  4209. * @vdev: virtual device instance
  4210. *
  4211. * Return: QDF_STATUS_SUCCESS: success
  4212. * QDF_STATUS_E_RESOURCES: Error return
  4213. */
  4214. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4215. {
  4216. int pdev_id;
  4217. /*
  4218. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4219. */
  4220. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4221. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4222. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4223. vdev->vdev_id);
  4224. pdev_id =
  4225. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4226. vdev->pdev->pdev_id);
  4227. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4228. /*
  4229. * Set HTT Extension Valid bit to 0 by default
  4230. */
  4231. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4232. dp_tx_vdev_update_search_flags(vdev);
  4233. dp_tx_vdev_update_feature_flags(vdev);
  4234. return QDF_STATUS_SUCCESS;
  4235. }
  4236. #ifndef FEATURE_WDS
  4237. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4238. {
  4239. return false;
  4240. }
  4241. #endif
  4242. /**
  4243. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4244. * @vdev: virtual device instance
  4245. *
  4246. * Return: void
  4247. *
  4248. */
  4249. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4250. {
  4251. struct dp_soc *soc = vdev->pdev->soc;
  4252. /*
  4253. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4254. * for TDLS link
  4255. *
  4256. * Enable AddrY (SA based search) only for non-WDS STA and
  4257. * ProxySTA VAP (in HKv1) modes.
  4258. *
  4259. * In all other VAP modes, only DA based search should be
  4260. * enabled
  4261. */
  4262. if (vdev->opmode == wlan_op_mode_sta &&
  4263. vdev->tdls_link_connected)
  4264. vdev->hal_desc_addr_search_flags =
  4265. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4266. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4267. !dp_tx_da_search_override(vdev))
  4268. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4269. else
  4270. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4271. /* Set search type only when peer map v2 messaging is enabled
  4272. * as we will have the search index (AST hash) only when v2 is
  4273. * enabled
  4274. */
  4275. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4276. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4277. else
  4278. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4279. }
  4280. static inline bool
  4281. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4282. struct dp_vdev *vdev,
  4283. struct dp_tx_desc_s *tx_desc)
  4284. {
  4285. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4286. return false;
  4287. /*
  4288. * if vdev is given, then only check whether desc
  4289. * vdev match. if vdev is NULL, then check whether
  4290. * desc pdev match.
  4291. */
  4292. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4293. (tx_desc->pdev == pdev);
  4294. }
  4295. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4296. /**
  4297. * dp_tx_desc_flush() - release resources associated
  4298. * to TX Desc
  4299. *
  4300. * @dp_pdev: Handle to DP pdev structure
  4301. * @vdev: virtual device instance
  4302. * NULL: no specific Vdev is required and check all allcated TX desc
  4303. * on this pdev.
  4304. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4305. *
  4306. * @force_free:
  4307. * true: flush the TX desc.
  4308. * false: only reset the Vdev in each allocated TX desc
  4309. * that associated to current Vdev.
  4310. *
  4311. * This function will go through the TX desc pool to flush
  4312. * the outstanding TX data or reset Vdev to NULL in associated TX
  4313. * Desc.
  4314. */
  4315. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4316. bool force_free)
  4317. {
  4318. uint8_t i;
  4319. uint32_t j;
  4320. uint32_t num_desc, page_id, offset;
  4321. uint16_t num_desc_per_page;
  4322. struct dp_soc *soc = pdev->soc;
  4323. struct dp_tx_desc_s *tx_desc = NULL;
  4324. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4325. if (!vdev && !force_free) {
  4326. dp_err("Reset TX desc vdev, Vdev param is required!");
  4327. return;
  4328. }
  4329. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4330. tx_desc_pool = &soc->tx_desc[i];
  4331. if (!(tx_desc_pool->pool_size) ||
  4332. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4333. !(tx_desc_pool->desc_pages.cacheable_pages))
  4334. continue;
  4335. /*
  4336. * Add flow pool lock protection in case pool is freed
  4337. * due to all tx_desc is recycled when handle TX completion.
  4338. * this is not necessary when do force flush as:
  4339. * a. double lock will happen if dp_tx_desc_release is
  4340. * also trying to acquire it.
  4341. * b. dp interrupt has been disabled before do force TX desc
  4342. * flush in dp_pdev_deinit().
  4343. */
  4344. if (!force_free)
  4345. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4346. num_desc = tx_desc_pool->pool_size;
  4347. num_desc_per_page =
  4348. tx_desc_pool->desc_pages.num_element_per_page;
  4349. for (j = 0; j < num_desc; j++) {
  4350. page_id = j / num_desc_per_page;
  4351. offset = j % num_desc_per_page;
  4352. if (qdf_unlikely(!(tx_desc_pool->
  4353. desc_pages.cacheable_pages)))
  4354. break;
  4355. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4356. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4357. /*
  4358. * Free TX desc if force free is
  4359. * required, otherwise only reset vdev
  4360. * in this TX desc.
  4361. */
  4362. if (force_free) {
  4363. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4364. dp_tx_comp_free_buf(soc, tx_desc);
  4365. dp_tx_desc_release(tx_desc, i);
  4366. } else {
  4367. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4368. }
  4369. }
  4370. }
  4371. if (!force_free)
  4372. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4373. }
  4374. }
  4375. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4376. /**
  4377. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4378. *
  4379. * @soc: Handle to DP soc structure
  4380. * @tx_desc: pointer of one TX desc
  4381. * @desc_pool_id: TX Desc pool id
  4382. */
  4383. static inline void
  4384. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4385. uint8_t desc_pool_id)
  4386. {
  4387. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4388. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4389. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4390. }
  4391. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4392. bool force_free)
  4393. {
  4394. uint8_t i, num_pool;
  4395. uint32_t j;
  4396. uint32_t num_desc, page_id, offset;
  4397. uint16_t num_desc_per_page;
  4398. struct dp_soc *soc = pdev->soc;
  4399. struct dp_tx_desc_s *tx_desc = NULL;
  4400. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4401. if (!vdev && !force_free) {
  4402. dp_err("Reset TX desc vdev, Vdev param is required!");
  4403. return;
  4404. }
  4405. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4406. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4407. for (i = 0; i < num_pool; i++) {
  4408. tx_desc_pool = &soc->tx_desc[i];
  4409. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4410. continue;
  4411. num_desc_per_page =
  4412. tx_desc_pool->desc_pages.num_element_per_page;
  4413. for (j = 0; j < num_desc; j++) {
  4414. page_id = j / num_desc_per_page;
  4415. offset = j % num_desc_per_page;
  4416. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4417. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4418. if (force_free) {
  4419. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4420. dp_tx_comp_free_buf(soc, tx_desc);
  4421. dp_tx_desc_release(tx_desc, i);
  4422. } else {
  4423. dp_tx_desc_reset_vdev(soc, tx_desc,
  4424. i);
  4425. }
  4426. }
  4427. }
  4428. }
  4429. }
  4430. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4431. /**
  4432. * dp_tx_vdev_detach() - detach vdev from dp tx
  4433. * @vdev: virtual device instance
  4434. *
  4435. * Return: QDF_STATUS_SUCCESS: success
  4436. * QDF_STATUS_E_RESOURCES: Error return
  4437. */
  4438. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4439. {
  4440. struct dp_pdev *pdev = vdev->pdev;
  4441. /* Reset TX desc associated to this Vdev as NULL */
  4442. dp_tx_desc_flush(pdev, vdev, false);
  4443. return QDF_STATUS_SUCCESS;
  4444. }
  4445. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4446. /* Pools will be allocated dynamically */
  4447. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4448. int num_desc)
  4449. {
  4450. uint8_t i;
  4451. for (i = 0; i < num_pool; i++) {
  4452. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4453. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4454. }
  4455. return QDF_STATUS_SUCCESS;
  4456. }
  4457. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4458. int num_desc)
  4459. {
  4460. return QDF_STATUS_SUCCESS;
  4461. }
  4462. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4463. {
  4464. }
  4465. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4466. {
  4467. uint8_t i;
  4468. for (i = 0; i < num_pool; i++)
  4469. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4470. }
  4471. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4472. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4473. int num_desc)
  4474. {
  4475. uint8_t i, count;
  4476. /* Allocate software Tx descriptor pools */
  4477. for (i = 0; i < num_pool; i++) {
  4478. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4480. FL("Tx Desc Pool alloc %d failed %pK"),
  4481. i, soc);
  4482. goto fail;
  4483. }
  4484. }
  4485. return QDF_STATUS_SUCCESS;
  4486. fail:
  4487. for (count = 0; count < i; count++)
  4488. dp_tx_desc_pool_free(soc, count);
  4489. return QDF_STATUS_E_NOMEM;
  4490. }
  4491. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4492. int num_desc)
  4493. {
  4494. uint8_t i;
  4495. for (i = 0; i < num_pool; i++) {
  4496. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4498. FL("Tx Desc Pool init %d failed %pK"),
  4499. i, soc);
  4500. return QDF_STATUS_E_NOMEM;
  4501. }
  4502. }
  4503. return QDF_STATUS_SUCCESS;
  4504. }
  4505. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4506. {
  4507. uint8_t i;
  4508. for (i = 0; i < num_pool; i++)
  4509. dp_tx_desc_pool_deinit(soc, i);
  4510. }
  4511. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4512. {
  4513. uint8_t i;
  4514. for (i = 0; i < num_pool; i++)
  4515. dp_tx_desc_pool_free(soc, i);
  4516. }
  4517. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4518. /**
  4519. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4520. * @soc: core txrx main context
  4521. * @num_pool: number of pools
  4522. *
  4523. */
  4524. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4525. {
  4526. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4527. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4528. }
  4529. /**
  4530. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4531. * @soc: core txrx main context
  4532. * @num_pool: number of pools
  4533. *
  4534. */
  4535. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4536. {
  4537. dp_tx_tso_desc_pool_free(soc, num_pool);
  4538. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4539. }
  4540. /**
  4541. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4542. * @soc: core txrx main context
  4543. *
  4544. * This function frees all tx related descriptors as below
  4545. * 1. Regular TX descriptors (static pools)
  4546. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4547. * 3. TSO descriptors
  4548. *
  4549. */
  4550. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4551. {
  4552. uint8_t num_pool;
  4553. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4554. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4555. dp_tx_ext_desc_pool_free(soc, num_pool);
  4556. dp_tx_delete_static_pools(soc, num_pool);
  4557. }
  4558. /**
  4559. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4560. * @soc: core txrx main context
  4561. *
  4562. * This function de-initializes all tx related descriptors as below
  4563. * 1. Regular TX descriptors (static pools)
  4564. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4565. * 3. TSO descriptors
  4566. *
  4567. */
  4568. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4569. {
  4570. uint8_t num_pool;
  4571. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4572. dp_tx_flow_control_deinit(soc);
  4573. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4574. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4575. dp_tx_deinit_static_pools(soc, num_pool);
  4576. }
  4577. /**
  4578. * dp_tso_attach() - TSO attach handler
  4579. * @txrx_soc: Opaque Dp handle
  4580. *
  4581. * Reserve TSO descriptor buffers
  4582. *
  4583. * Return: QDF_STATUS_E_FAILURE on failure or
  4584. * QDF_STATUS_SUCCESS on success
  4585. */
  4586. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4587. uint8_t num_pool,
  4588. uint16_t num_desc)
  4589. {
  4590. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4591. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4592. return QDF_STATUS_E_FAILURE;
  4593. }
  4594. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4595. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4596. num_pool, soc);
  4597. return QDF_STATUS_E_FAILURE;
  4598. }
  4599. return QDF_STATUS_SUCCESS;
  4600. }
  4601. /**
  4602. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4603. * @soc: DP soc handle
  4604. * @num_pool: Number of pools
  4605. * @num_desc: Number of descriptors
  4606. *
  4607. * Initialize TSO descriptor pools
  4608. *
  4609. * Return: QDF_STATUS_E_FAILURE on failure or
  4610. * QDF_STATUS_SUCCESS on success
  4611. */
  4612. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4613. uint8_t num_pool,
  4614. uint16_t num_desc)
  4615. {
  4616. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4617. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4618. return QDF_STATUS_E_FAILURE;
  4619. }
  4620. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4621. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4622. num_pool, soc);
  4623. return QDF_STATUS_E_FAILURE;
  4624. }
  4625. return QDF_STATUS_SUCCESS;
  4626. }
  4627. /**
  4628. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4629. * @soc: core txrx main context
  4630. *
  4631. * This function allocates memory for following descriptor pools
  4632. * 1. regular sw tx descriptor pools (static pools)
  4633. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4634. * 3. TSO descriptor pools
  4635. *
  4636. * Return: QDF_STATUS_SUCCESS: success
  4637. * QDF_STATUS_E_RESOURCES: Error return
  4638. */
  4639. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4640. {
  4641. uint8_t num_pool;
  4642. uint32_t num_desc;
  4643. uint32_t num_ext_desc;
  4644. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4645. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4646. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4648. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4649. __func__, num_pool, num_desc);
  4650. if ((num_pool > MAX_TXDESC_POOLS) ||
  4651. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4652. goto fail1;
  4653. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4654. goto fail1;
  4655. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4656. goto fail2;
  4657. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4658. return QDF_STATUS_SUCCESS;
  4659. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4660. goto fail3;
  4661. return QDF_STATUS_SUCCESS;
  4662. fail3:
  4663. dp_tx_ext_desc_pool_free(soc, num_pool);
  4664. fail2:
  4665. dp_tx_delete_static_pools(soc, num_pool);
  4666. fail1:
  4667. return QDF_STATUS_E_RESOURCES;
  4668. }
  4669. /**
  4670. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4671. * @soc: core txrx main context
  4672. *
  4673. * This function initializes the following TX descriptor pools
  4674. * 1. regular sw tx descriptor pools (static pools)
  4675. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4676. * 3. TSO descriptor pools
  4677. *
  4678. * Return: QDF_STATUS_SUCCESS: success
  4679. * QDF_STATUS_E_RESOURCES: Error return
  4680. */
  4681. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4682. {
  4683. uint8_t num_pool;
  4684. uint32_t num_desc;
  4685. uint32_t num_ext_desc;
  4686. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4687. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4688. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4689. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4690. goto fail1;
  4691. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4692. goto fail2;
  4693. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4694. return QDF_STATUS_SUCCESS;
  4695. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4696. goto fail3;
  4697. dp_tx_flow_control_init(soc);
  4698. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4699. return QDF_STATUS_SUCCESS;
  4700. fail3:
  4701. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4702. fail2:
  4703. dp_tx_deinit_static_pools(soc, num_pool);
  4704. fail1:
  4705. return QDF_STATUS_E_RESOURCES;
  4706. }
  4707. /**
  4708. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4709. * @txrx_soc: dp soc handle
  4710. *
  4711. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4712. * QDF_STATUS_E_FAILURE
  4713. */
  4714. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4715. {
  4716. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4717. uint8_t num_pool;
  4718. uint32_t num_desc;
  4719. uint32_t num_ext_desc;
  4720. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4721. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4722. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4723. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4724. return QDF_STATUS_E_FAILURE;
  4725. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4726. return QDF_STATUS_E_FAILURE;
  4727. return QDF_STATUS_SUCCESS;
  4728. }
  4729. /**
  4730. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4731. * @txrx_soc: dp soc handle
  4732. *
  4733. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4734. */
  4735. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4736. {
  4737. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4738. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4739. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4740. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4741. return QDF_STATUS_SUCCESS;
  4742. }