rx_msdu_end.h 83 KB

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  1. /*
  2. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _RX_MSDU_END_H_
  19. #define _RX_MSDU_END_H_
  20. #if !defined(__ASSEMBLER__)
  21. #endif
  22. #define NUM_OF_DWORDS_RX_MSDU_END 32
  23. #define NUM_OF_QWORDS_RX_MSDU_END 16
  24. struct rx_msdu_end {
  25. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  26. uint32_t rxpcu_mpdu_filter_in_category : 2,
  27. sw_frame_group_id : 7,
  28. reserved_0 : 7,
  29. phy_ppdu_id : 16;
  30. uint32_t ip_hdr_chksum : 16,
  31. reported_mpdu_length : 14,
  32. reserved_1a : 2;
  33. uint32_t reserved_2a : 8,
  34. cce_super_rule : 6,
  35. cce_classify_not_done_truncate : 1,
  36. cce_classify_not_done_cce_dis : 1,
  37. cumulative_l3_checksum : 16;
  38. uint32_t rule_indication_31_0 : 32;
  39. uint32_t ipv6_options_crc : 32;
  40. uint32_t da_offset : 6,
  41. sa_offset : 6,
  42. da_offset_valid : 1,
  43. sa_offset_valid : 1,
  44. reserved_5a : 2,
  45. l3_type : 16;
  46. uint32_t rule_indication_63_32 : 32;
  47. uint32_t tcp_seq_number : 32;
  48. uint32_t tcp_ack_number : 32;
  49. uint32_t tcp_flag : 9,
  50. lro_eligible : 1,
  51. reserved_9a : 6,
  52. window_size : 16;
  53. uint32_t sa_sw_peer_id : 16,
  54. sa_idx_timeout : 1,
  55. da_idx_timeout : 1,
  56. to_ds : 1,
  57. tid : 4,
  58. sa_is_valid : 1,
  59. da_is_valid : 1,
  60. da_is_mcbc : 1,
  61. l3_header_padding : 2,
  62. first_msdu : 1,
  63. last_msdu : 1,
  64. fr_ds : 1,
  65. ip_chksum_fail_copy : 1;
  66. uint32_t sa_idx : 16,
  67. da_idx_or_sw_peer_id : 16;
  68. uint32_t msdu_drop : 1,
  69. reo_destination_indication : 5,
  70. flow_idx : 20,
  71. use_ppe : 1,
  72. __reserved_g_0003 : 2,
  73. vlan_ctag_stripped : 1,
  74. vlan_stag_stripped : 1,
  75. fragment_flag : 1;
  76. uint32_t fse_metadata : 32;
  77. uint32_t cce_metadata : 16,
  78. tcp_udp_chksum : 16;
  79. uint32_t aggregation_count : 8,
  80. flow_aggregation_continuation : 1,
  81. fisa_timeout : 1,
  82. tcp_udp_chksum_fail_copy : 1,
  83. msdu_limit_error : 1,
  84. flow_idx_timeout : 1,
  85. flow_idx_invalid : 1,
  86. cce_match : 1,
  87. amsdu_parser_error : 1,
  88. cumulative_ip_length : 16;
  89. uint32_t key_id_octet : 8,
  90. reserved_16a : 24;
  91. uint32_t reserved_17a : 6,
  92. service_code : 9,
  93. priority_valid : 1,
  94. intra_bss : 1,
  95. dest_chip_id : 2,
  96. multicast_echo : 1,
  97. wds_learning_event : 1,
  98. wds_roaming_event : 1,
  99. wds_keep_alive_event : 1,
  100. reserved_17b : 9;
  101. uint32_t msdu_length : 14,
  102. stbc : 1,
  103. ipsec_esp : 1,
  104. l3_offset : 7,
  105. ipsec_ah : 1,
  106. l4_offset : 8;
  107. uint32_t msdu_number : 8,
  108. decap_format : 2,
  109. ipv4_proto : 1,
  110. ipv6_proto : 1,
  111. tcp_proto : 1,
  112. udp_proto : 1,
  113. ip_frag : 1,
  114. tcp_only_ack : 1,
  115. da_is_bcast_mcast : 1,
  116. toeplitz_hash_sel : 2,
  117. ip_fixed_header_valid : 1,
  118. ip_extn_header_valid : 1,
  119. tcp_udp_header_valid : 1,
  120. mesh_control_present : 1,
  121. ldpc : 1,
  122. ip4_protocol_ip6_next_header : 8;
  123. uint32_t vlan_ctag_ci : 16,
  124. vlan_stag_ci : 16;
  125. uint32_t peer_meta_data : 32;
  126. uint32_t user_rssi : 8,
  127. pkt_type : 4,
  128. sgi : 2,
  129. rate_mcs : 4,
  130. receive_bandwidth : 3,
  131. reception_type : 3,
  132. mimo_ss_bitmap : 7,
  133. msdu_done_copy : 1;
  134. uint32_t flow_id_toeplitz : 32;
  135. uint32_t ppdu_start_timestamp_63_32 : 32;
  136. uint32_t sw_phy_meta_data : 32;
  137. uint32_t ppdu_start_timestamp_31_0 : 32;
  138. uint32_t toeplitz_hash_2_or_4 : 32;
  139. uint32_t reserved_28a : 16,
  140. sa_15_0 : 16;
  141. uint32_t sa_47_16 : 32;
  142. uint32_t first_mpdu : 1,
  143. reserved_30a : 1,
  144. mcast_bcast : 1,
  145. ast_index_not_found : 1,
  146. ast_index_timeout : 1,
  147. power_mgmt : 1,
  148. non_qos : 1,
  149. null_data : 1,
  150. mgmt_type : 1,
  151. ctrl_type : 1,
  152. more_data : 1,
  153. eosp : 1,
  154. a_msdu_error : 1,
  155. reserved_30b : 1,
  156. order : 1,
  157. wifi_parser_error : 1,
  158. overflow_err : 1,
  159. msdu_length_err : 1,
  160. tcp_udp_chksum_fail : 1,
  161. ip_chksum_fail : 1,
  162. sa_idx_invalid : 1,
  163. da_idx_invalid : 1,
  164. amsdu_addr_mismatch : 1,
  165. rx_in_tx_decrypt_byp : 1,
  166. encrypt_required : 1,
  167. directed : 1,
  168. buffer_fragment : 1,
  169. mpdu_length_err : 1,
  170. tkip_mic_err : 1,
  171. decrypt_err : 1,
  172. unencrypted_frame_err : 1,
  173. fcs_err : 1;
  174. uint32_t reserved_31a : 10,
  175. decrypt_status_code : 3,
  176. rx_bitmap_not_updated : 1,
  177. reserved_31b : 17,
  178. msdu_done : 1;
  179. #else
  180. uint32_t phy_ppdu_id : 16,
  181. reserved_0 : 7,
  182. sw_frame_group_id : 7,
  183. rxpcu_mpdu_filter_in_category : 2;
  184. uint32_t reserved_1a : 2,
  185. reported_mpdu_length : 14,
  186. ip_hdr_chksum : 16;
  187. uint32_t cumulative_l3_checksum : 16,
  188. cce_classify_not_done_cce_dis : 1,
  189. cce_classify_not_done_truncate : 1,
  190. cce_super_rule : 6,
  191. reserved_2a : 8;
  192. uint32_t rule_indication_31_0 : 32;
  193. uint32_t ipv6_options_crc : 32;
  194. uint32_t l3_type : 16,
  195. reserved_5a : 2,
  196. sa_offset_valid : 1,
  197. da_offset_valid : 1,
  198. sa_offset : 6,
  199. da_offset : 6;
  200. uint32_t rule_indication_63_32 : 32;
  201. uint32_t tcp_seq_number : 32;
  202. uint32_t tcp_ack_number : 32;
  203. uint32_t window_size : 16,
  204. reserved_9a : 6,
  205. lro_eligible : 1,
  206. tcp_flag : 9;
  207. uint32_t ip_chksum_fail_copy : 1,
  208. fr_ds : 1,
  209. last_msdu : 1,
  210. first_msdu : 1,
  211. l3_header_padding : 2,
  212. da_is_mcbc : 1,
  213. da_is_valid : 1,
  214. sa_is_valid : 1,
  215. tid : 4,
  216. to_ds : 1,
  217. da_idx_timeout : 1,
  218. sa_idx_timeout : 1,
  219. sa_sw_peer_id : 16;
  220. uint32_t da_idx_or_sw_peer_id : 16,
  221. sa_idx : 16;
  222. uint32_t fragment_flag : 1,
  223. vlan_stag_stripped : 1,
  224. vlan_ctag_stripped : 1,
  225. __reserved_g_0003 : 2,
  226. use_ppe : 1,
  227. flow_idx : 20,
  228. reo_destination_indication : 5,
  229. msdu_drop : 1;
  230. uint32_t fse_metadata : 32;
  231. uint32_t tcp_udp_chksum : 16,
  232. cce_metadata : 16;
  233. uint32_t cumulative_ip_length : 16,
  234. amsdu_parser_error : 1,
  235. cce_match : 1,
  236. flow_idx_invalid : 1,
  237. flow_idx_timeout : 1,
  238. msdu_limit_error : 1,
  239. tcp_udp_chksum_fail_copy : 1,
  240. fisa_timeout : 1,
  241. flow_aggregation_continuation : 1,
  242. aggregation_count : 8;
  243. uint32_t reserved_16a : 24,
  244. key_id_octet : 8;
  245. uint32_t reserved_17b : 9,
  246. wds_keep_alive_event : 1,
  247. wds_roaming_event : 1,
  248. wds_learning_event : 1,
  249. multicast_echo : 1,
  250. dest_chip_id : 2,
  251. intra_bss : 1,
  252. priority_valid : 1,
  253. service_code : 9,
  254. reserved_17a : 6;
  255. uint32_t l4_offset : 8,
  256. ipsec_ah : 1,
  257. l3_offset : 7,
  258. ipsec_esp : 1,
  259. stbc : 1,
  260. msdu_length : 14;
  261. uint32_t ip4_protocol_ip6_next_header : 8,
  262. ldpc : 1,
  263. mesh_control_present : 1,
  264. tcp_udp_header_valid : 1,
  265. ip_extn_header_valid : 1,
  266. ip_fixed_header_valid : 1,
  267. toeplitz_hash_sel : 2,
  268. da_is_bcast_mcast : 1,
  269. tcp_only_ack : 1,
  270. ip_frag : 1,
  271. udp_proto : 1,
  272. tcp_proto : 1,
  273. ipv6_proto : 1,
  274. ipv4_proto : 1,
  275. decap_format : 2,
  276. msdu_number : 8;
  277. uint32_t vlan_stag_ci : 16,
  278. vlan_ctag_ci : 16;
  279. uint32_t peer_meta_data : 32;
  280. uint32_t msdu_done_copy : 1,
  281. mimo_ss_bitmap : 7,
  282. reception_type : 3,
  283. receive_bandwidth : 3,
  284. rate_mcs : 4,
  285. sgi : 2,
  286. pkt_type : 4,
  287. user_rssi : 8;
  288. uint32_t flow_id_toeplitz : 32;
  289. uint32_t ppdu_start_timestamp_63_32 : 32;
  290. uint32_t sw_phy_meta_data : 32;
  291. uint32_t ppdu_start_timestamp_31_0 : 32;
  292. uint32_t toeplitz_hash_2_or_4 : 32;
  293. uint32_t sa_15_0 : 16,
  294. reserved_28a : 16;
  295. uint32_t sa_47_16 : 32;
  296. uint32_t fcs_err : 1,
  297. unencrypted_frame_err : 1,
  298. decrypt_err : 1,
  299. tkip_mic_err : 1,
  300. mpdu_length_err : 1,
  301. buffer_fragment : 1,
  302. directed : 1,
  303. encrypt_required : 1,
  304. rx_in_tx_decrypt_byp : 1,
  305. amsdu_addr_mismatch : 1,
  306. da_idx_invalid : 1,
  307. sa_idx_invalid : 1,
  308. ip_chksum_fail : 1,
  309. tcp_udp_chksum_fail : 1,
  310. msdu_length_err : 1,
  311. overflow_err : 1,
  312. wifi_parser_error : 1,
  313. order : 1,
  314. reserved_30b : 1,
  315. a_msdu_error : 1,
  316. eosp : 1,
  317. more_data : 1,
  318. ctrl_type : 1,
  319. mgmt_type : 1,
  320. null_data : 1,
  321. non_qos : 1,
  322. power_mgmt : 1,
  323. ast_index_timeout : 1,
  324. ast_index_not_found : 1,
  325. mcast_bcast : 1,
  326. reserved_30a : 1,
  327. first_mpdu : 1;
  328. uint32_t msdu_done : 1,
  329. reserved_31b : 17,
  330. rx_bitmap_not_updated : 1,
  331. decrypt_status_code : 3,
  332. reserved_31a : 10;
  333. #endif
  334. };
  335. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
  336. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  337. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
  338. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
  339. #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
  340. #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2
  341. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8
  342. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
  343. #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000
  344. #define RX_MSDU_END_RESERVED_0_LSB 9
  345. #define RX_MSDU_END_RESERVED_0_MSB 15
  346. #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00
  347. #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000
  348. #define RX_MSDU_END_PHY_PPDU_ID_LSB 16
  349. #define RX_MSDU_END_PHY_PPDU_ID_MSB 31
  350. #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000
  351. #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000
  352. #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32
  353. #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47
  354. #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000
  355. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000
  356. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48
  357. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61
  358. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000
  359. #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000
  360. #define RX_MSDU_END_RESERVED_1A_LSB 62
  361. #define RX_MSDU_END_RESERVED_1A_MSB 63
  362. #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000
  363. #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008
  364. #define RX_MSDU_END_RESERVED_2A_LSB 0
  365. #define RX_MSDU_END_RESERVED_2A_MSB 7
  366. #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff
  367. #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008
  368. #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8
  369. #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13
  370. #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00
  371. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008
  372. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
  373. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14
  374. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000
  375. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008
  376. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
  377. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15
  378. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000
  379. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008
  380. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16
  381. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31
  382. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000
  383. #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008
  384. #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32
  385. #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63
  386. #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000
  387. #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010
  388. #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0
  389. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31
  390. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff
  391. #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010
  392. #define RX_MSDU_END_DA_OFFSET_LSB 32
  393. #define RX_MSDU_END_DA_OFFSET_MSB 37
  394. #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000
  395. #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010
  396. #define RX_MSDU_END_SA_OFFSET_LSB 38
  397. #define RX_MSDU_END_SA_OFFSET_MSB 43
  398. #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000
  399. #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010
  400. #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44
  401. #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44
  402. #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000
  403. #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010
  404. #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45
  405. #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45
  406. #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000
  407. #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010
  408. #define RX_MSDU_END_RESERVED_5A_LSB 46
  409. #define RX_MSDU_END_RESERVED_5A_MSB 47
  410. #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000
  411. #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010
  412. #define RX_MSDU_END_L3_TYPE_LSB 48
  413. #define RX_MSDU_END_L3_TYPE_MSB 63
  414. #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000
  415. #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018
  416. #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0
  417. #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31
  418. #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff
  419. #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018
  420. #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32
  421. #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63
  422. #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000
  423. #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020
  424. #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0
  425. #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31
  426. #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff
  427. #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020
  428. #define RX_MSDU_END_TCP_FLAG_LSB 32
  429. #define RX_MSDU_END_TCP_FLAG_MSB 40
  430. #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000
  431. #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020
  432. #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41
  433. #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41
  434. #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000
  435. #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020
  436. #define RX_MSDU_END_RESERVED_9A_LSB 42
  437. #define RX_MSDU_END_RESERVED_9A_MSB 47
  438. #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000
  439. #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020
  440. #define RX_MSDU_END_WINDOW_SIZE_LSB 48
  441. #define RX_MSDU_END_WINDOW_SIZE_MSB 63
  442. #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000
  443. #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028
  444. #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0
  445. #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15
  446. #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff
  447. #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028
  448. #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16
  449. #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16
  450. #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000
  451. #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028
  452. #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17
  453. #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17
  454. #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000
  455. #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028
  456. #define RX_MSDU_END_TO_DS_LSB 18
  457. #define RX_MSDU_END_TO_DS_MSB 18
  458. #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000
  459. #define RX_MSDU_END_TID_OFFSET 0x0000000000000028
  460. #define RX_MSDU_END_TID_LSB 19
  461. #define RX_MSDU_END_TID_MSB 22
  462. #define RX_MSDU_END_TID_MASK 0x0000000000780000
  463. #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028
  464. #define RX_MSDU_END_SA_IS_VALID_LSB 23
  465. #define RX_MSDU_END_SA_IS_VALID_MSB 23
  466. #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000
  467. #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028
  468. #define RX_MSDU_END_DA_IS_VALID_LSB 24
  469. #define RX_MSDU_END_DA_IS_VALID_MSB 24
  470. #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000
  471. #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028
  472. #define RX_MSDU_END_DA_IS_MCBC_LSB 25
  473. #define RX_MSDU_END_DA_IS_MCBC_MSB 25
  474. #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000
  475. #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028
  476. #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26
  477. #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27
  478. #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000
  479. #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028
  480. #define RX_MSDU_END_FIRST_MSDU_LSB 28
  481. #define RX_MSDU_END_FIRST_MSDU_MSB 28
  482. #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000
  483. #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028
  484. #define RX_MSDU_END_LAST_MSDU_LSB 29
  485. #define RX_MSDU_END_LAST_MSDU_MSB 29
  486. #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000
  487. #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028
  488. #define RX_MSDU_END_FR_DS_LSB 30
  489. #define RX_MSDU_END_FR_DS_MSB 30
  490. #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000
  491. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028
  492. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31
  493. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31
  494. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000
  495. #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028
  496. #define RX_MSDU_END_SA_IDX_LSB 32
  497. #define RX_MSDU_END_SA_IDX_MSB 47
  498. #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000
  499. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028
  500. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48
  501. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63
  502. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000
  503. #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030
  504. #define RX_MSDU_END_MSDU_DROP_LSB 0
  505. #define RX_MSDU_END_MSDU_DROP_MSB 0
  506. #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001
  507. #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030
  508. #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1
  509. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5
  510. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e
  511. #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030
  512. #define RX_MSDU_END_FLOW_IDX_LSB 6
  513. #define RX_MSDU_END_FLOW_IDX_MSB 25
  514. #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0
  515. #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030
  516. #define RX_MSDU_END_USE_PPE_LSB 26
  517. #define RX_MSDU_END_USE_PPE_MSB 26
  518. #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000
  519. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030
  520. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29
  521. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29
  522. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000
  523. #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030
  524. #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30
  525. #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30
  526. #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000
  527. #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030
  528. #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31
  529. #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31
  530. #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000
  531. #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030
  532. #define RX_MSDU_END_FSE_METADATA_LSB 32
  533. #define RX_MSDU_END_FSE_METADATA_MSB 63
  534. #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000
  535. #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038
  536. #define RX_MSDU_END_CCE_METADATA_LSB 0
  537. #define RX_MSDU_END_CCE_METADATA_MSB 15
  538. #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff
  539. #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038
  540. #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16
  541. #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31
  542. #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000
  543. #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038
  544. #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32
  545. #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39
  546. #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000
  547. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038
  548. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40
  549. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40
  550. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000
  551. #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038
  552. #define RX_MSDU_END_FISA_TIMEOUT_LSB 41
  553. #define RX_MSDU_END_FISA_TIMEOUT_MSB 41
  554. #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000
  555. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038
  556. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42
  557. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42
  558. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000
  559. #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038
  560. #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43
  561. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43
  562. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000
  563. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038
  564. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44
  565. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44
  566. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000
  567. #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038
  568. #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45
  569. #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45
  570. #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000
  571. #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038
  572. #define RX_MSDU_END_CCE_MATCH_LSB 46
  573. #define RX_MSDU_END_CCE_MATCH_MSB 46
  574. #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000
  575. #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038
  576. #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47
  577. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47
  578. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000
  579. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038
  580. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48
  581. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63
  582. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000
  583. #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040
  584. #define RX_MSDU_END_KEY_ID_OCTET_LSB 0
  585. #define RX_MSDU_END_KEY_ID_OCTET_MSB 7
  586. #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff
  587. #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040
  588. #define RX_MSDU_END_RESERVED_16A_LSB 8
  589. #define RX_MSDU_END_RESERVED_16A_MSB 31
  590. #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00
  591. #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040
  592. #define RX_MSDU_END_RESERVED_17A_LSB 32
  593. #define RX_MSDU_END_RESERVED_17A_MSB 37
  594. #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000
  595. #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040
  596. #define RX_MSDU_END_SERVICE_CODE_LSB 38
  597. #define RX_MSDU_END_SERVICE_CODE_MSB 46
  598. #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000
  599. #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040
  600. #define RX_MSDU_END_PRIORITY_VALID_LSB 47
  601. #define RX_MSDU_END_PRIORITY_VALID_MSB 47
  602. #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000
  603. #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040
  604. #define RX_MSDU_END_INTRA_BSS_LSB 48
  605. #define RX_MSDU_END_INTRA_BSS_MSB 48
  606. #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000
  607. #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040
  608. #define RX_MSDU_END_DEST_CHIP_ID_LSB 49
  609. #define RX_MSDU_END_DEST_CHIP_ID_MSB 50
  610. #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000
  611. #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040
  612. #define RX_MSDU_END_MULTICAST_ECHO_LSB 51
  613. #define RX_MSDU_END_MULTICAST_ECHO_MSB 51
  614. #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000
  615. #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040
  616. #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52
  617. #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52
  618. #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000
  619. #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040
  620. #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53
  621. #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53
  622. #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000
  623. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040
  624. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54
  625. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54
  626. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000
  627. #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040
  628. #define RX_MSDU_END_RESERVED_17B_LSB 55
  629. #define RX_MSDU_END_RESERVED_17B_MSB 63
  630. #define RX_MSDU_END_RESERVED_17B_MASK 0xff80000000000000
  631. #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048
  632. #define RX_MSDU_END_MSDU_LENGTH_LSB 0
  633. #define RX_MSDU_END_MSDU_LENGTH_MSB 13
  634. #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff
  635. #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048
  636. #define RX_MSDU_END_STBC_LSB 14
  637. #define RX_MSDU_END_STBC_MSB 14
  638. #define RX_MSDU_END_STBC_MASK 0x0000000000004000
  639. #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048
  640. #define RX_MSDU_END_IPSEC_ESP_LSB 15
  641. #define RX_MSDU_END_IPSEC_ESP_MSB 15
  642. #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000
  643. #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048
  644. #define RX_MSDU_END_L3_OFFSET_LSB 16
  645. #define RX_MSDU_END_L3_OFFSET_MSB 22
  646. #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000
  647. #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048
  648. #define RX_MSDU_END_IPSEC_AH_LSB 23
  649. #define RX_MSDU_END_IPSEC_AH_MSB 23
  650. #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000
  651. #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048
  652. #define RX_MSDU_END_L4_OFFSET_LSB 24
  653. #define RX_MSDU_END_L4_OFFSET_MSB 31
  654. #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000
  655. #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048
  656. #define RX_MSDU_END_MSDU_NUMBER_LSB 32
  657. #define RX_MSDU_END_MSDU_NUMBER_MSB 39
  658. #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000
  659. #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048
  660. #define RX_MSDU_END_DECAP_FORMAT_LSB 40
  661. #define RX_MSDU_END_DECAP_FORMAT_MSB 41
  662. #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000
  663. #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048
  664. #define RX_MSDU_END_IPV4_PROTO_LSB 42
  665. #define RX_MSDU_END_IPV4_PROTO_MSB 42
  666. #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000
  667. #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048
  668. #define RX_MSDU_END_IPV6_PROTO_LSB 43
  669. #define RX_MSDU_END_IPV6_PROTO_MSB 43
  670. #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000
  671. #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048
  672. #define RX_MSDU_END_TCP_PROTO_LSB 44
  673. #define RX_MSDU_END_TCP_PROTO_MSB 44
  674. #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000
  675. #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048
  676. #define RX_MSDU_END_UDP_PROTO_LSB 45
  677. #define RX_MSDU_END_UDP_PROTO_MSB 45
  678. #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000
  679. #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048
  680. #define RX_MSDU_END_IP_FRAG_LSB 46
  681. #define RX_MSDU_END_IP_FRAG_MSB 46
  682. #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000
  683. #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048
  684. #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47
  685. #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47
  686. #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000
  687. #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048
  688. #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48
  689. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48
  690. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000
  691. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048
  692. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49
  693. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50
  694. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000
  695. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048
  696. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51
  697. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51
  698. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000
  699. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048
  700. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52
  701. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52
  702. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000
  703. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048
  704. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53
  705. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53
  706. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000
  707. #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048
  708. #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54
  709. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54
  710. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000
  711. #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048
  712. #define RX_MSDU_END_LDPC_LSB 55
  713. #define RX_MSDU_END_LDPC_MSB 55
  714. #define RX_MSDU_END_LDPC_MASK 0x0080000000000000
  715. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048
  716. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56
  717. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63
  718. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000
  719. #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050
  720. #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0
  721. #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15
  722. #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff
  723. #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050
  724. #define RX_MSDU_END_VLAN_STAG_CI_LSB 16
  725. #define RX_MSDU_END_VLAN_STAG_CI_MSB 31
  726. #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000
  727. #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050
  728. #define RX_MSDU_END_PEER_META_DATA_LSB 32
  729. #define RX_MSDU_END_PEER_META_DATA_MSB 63
  730. #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000
  731. #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058
  732. #define RX_MSDU_END_USER_RSSI_LSB 0
  733. #define RX_MSDU_END_USER_RSSI_MSB 7
  734. #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff
  735. #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058
  736. #define RX_MSDU_END_PKT_TYPE_LSB 8
  737. #define RX_MSDU_END_PKT_TYPE_MSB 11
  738. #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00
  739. #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058
  740. #define RX_MSDU_END_SGI_LSB 12
  741. #define RX_MSDU_END_SGI_MSB 13
  742. #define RX_MSDU_END_SGI_MASK 0x0000000000003000
  743. #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058
  744. #define RX_MSDU_END_RATE_MCS_LSB 14
  745. #define RX_MSDU_END_RATE_MCS_MSB 17
  746. #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000
  747. #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058
  748. #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18
  749. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20
  750. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000
  751. #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058
  752. #define RX_MSDU_END_RECEPTION_TYPE_LSB 21
  753. #define RX_MSDU_END_RECEPTION_TYPE_MSB 23
  754. #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000
  755. #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058
  756. #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24
  757. #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30
  758. #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000
  759. #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058
  760. #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31
  761. #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31
  762. #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000
  763. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058
  764. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32
  765. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63
  766. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000
  767. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060
  768. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0
  769. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31
  770. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff
  771. #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060
  772. #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32
  773. #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63
  774. #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000
  775. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068
  776. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0
  777. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31
  778. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff
  779. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068
  780. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32
  781. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63
  782. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000
  783. #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070
  784. #define RX_MSDU_END_RESERVED_28A_LSB 0
  785. #define RX_MSDU_END_RESERVED_28A_MSB 15
  786. #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff
  787. #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070
  788. #define RX_MSDU_END_SA_15_0_LSB 16
  789. #define RX_MSDU_END_SA_15_0_MSB 31
  790. #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000
  791. #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070
  792. #define RX_MSDU_END_SA_47_16_LSB 32
  793. #define RX_MSDU_END_SA_47_16_MSB 63
  794. #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000
  795. #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078
  796. #define RX_MSDU_END_FIRST_MPDU_LSB 0
  797. #define RX_MSDU_END_FIRST_MPDU_MSB 0
  798. #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001
  799. #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078
  800. #define RX_MSDU_END_RESERVED_30A_LSB 1
  801. #define RX_MSDU_END_RESERVED_30A_MSB 1
  802. #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002
  803. #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078
  804. #define RX_MSDU_END_MCAST_BCAST_LSB 2
  805. #define RX_MSDU_END_MCAST_BCAST_MSB 2
  806. #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004
  807. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078
  808. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3
  809. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3
  810. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008
  811. #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078
  812. #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4
  813. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4
  814. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010
  815. #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078
  816. #define RX_MSDU_END_POWER_MGMT_LSB 5
  817. #define RX_MSDU_END_POWER_MGMT_MSB 5
  818. #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020
  819. #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078
  820. #define RX_MSDU_END_NON_QOS_LSB 6
  821. #define RX_MSDU_END_NON_QOS_MSB 6
  822. #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040
  823. #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078
  824. #define RX_MSDU_END_NULL_DATA_LSB 7
  825. #define RX_MSDU_END_NULL_DATA_MSB 7
  826. #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080
  827. #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078
  828. #define RX_MSDU_END_MGMT_TYPE_LSB 8
  829. #define RX_MSDU_END_MGMT_TYPE_MSB 8
  830. #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100
  831. #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078
  832. #define RX_MSDU_END_CTRL_TYPE_LSB 9
  833. #define RX_MSDU_END_CTRL_TYPE_MSB 9
  834. #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200
  835. #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078
  836. #define RX_MSDU_END_MORE_DATA_LSB 10
  837. #define RX_MSDU_END_MORE_DATA_MSB 10
  838. #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400
  839. #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078
  840. #define RX_MSDU_END_EOSP_LSB 11
  841. #define RX_MSDU_END_EOSP_MSB 11
  842. #define RX_MSDU_END_EOSP_MASK 0x0000000000000800
  843. #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078
  844. #define RX_MSDU_END_A_MSDU_ERROR_LSB 12
  845. #define RX_MSDU_END_A_MSDU_ERROR_MSB 12
  846. #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000
  847. #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078
  848. #define RX_MSDU_END_RESERVED_30B_LSB 13
  849. #define RX_MSDU_END_RESERVED_30B_MSB 13
  850. #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000
  851. #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078
  852. #define RX_MSDU_END_ORDER_LSB 14
  853. #define RX_MSDU_END_ORDER_MSB 14
  854. #define RX_MSDU_END_ORDER_MASK 0x0000000000004000
  855. #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078
  856. #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15
  857. #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15
  858. #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000
  859. #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078
  860. #define RX_MSDU_END_OVERFLOW_ERR_LSB 16
  861. #define RX_MSDU_END_OVERFLOW_ERR_MSB 16
  862. #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000
  863. #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078
  864. #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17
  865. #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17
  866. #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000
  867. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078
  868. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18
  869. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18
  870. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000
  871. #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078
  872. #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19
  873. #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19
  874. #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000
  875. #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078
  876. #define RX_MSDU_END_SA_IDX_INVALID_LSB 20
  877. #define RX_MSDU_END_SA_IDX_INVALID_MSB 20
  878. #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000
  879. #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078
  880. #define RX_MSDU_END_DA_IDX_INVALID_LSB 21
  881. #define RX_MSDU_END_DA_IDX_INVALID_MSB 21
  882. #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000
  883. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078
  884. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22
  885. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22
  886. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000
  887. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078
  888. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23
  889. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23
  890. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000
  891. #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078
  892. #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24
  893. #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24
  894. #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000
  895. #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078
  896. #define RX_MSDU_END_DIRECTED_LSB 25
  897. #define RX_MSDU_END_DIRECTED_MSB 25
  898. #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000
  899. #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078
  900. #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26
  901. #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26
  902. #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000
  903. #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078
  904. #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27
  905. #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27
  906. #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000
  907. #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078
  908. #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28
  909. #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28
  910. #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000
  911. #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078
  912. #define RX_MSDU_END_DECRYPT_ERR_LSB 29
  913. #define RX_MSDU_END_DECRYPT_ERR_MSB 29
  914. #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000
  915. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078
  916. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30
  917. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30
  918. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000
  919. #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078
  920. #define RX_MSDU_END_FCS_ERR_LSB 31
  921. #define RX_MSDU_END_FCS_ERR_MSB 31
  922. #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000
  923. #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078
  924. #define RX_MSDU_END_RESERVED_31A_LSB 32
  925. #define RX_MSDU_END_RESERVED_31A_MSB 41
  926. #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000
  927. #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078
  928. #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42
  929. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44
  930. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000
  931. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078
  932. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45
  933. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45
  934. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000
  935. #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078
  936. #define RX_MSDU_END_RESERVED_31B_LSB 46
  937. #define RX_MSDU_END_RESERVED_31B_MSB 62
  938. #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000
  939. #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078
  940. #define RX_MSDU_END_MSDU_DONE_LSB 63
  941. #define RX_MSDU_END_MSDU_DONE_MSB 63
  942. #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000
  943. #endif