cam_soc_util.h 27 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _CAM_SOC_UTIL_H_
  6. #define _CAM_SOC_UTIL_H_
  7. #include <linux/version.h>
  8. #include <linux/types.h>
  9. #include <linux/slab.h>
  10. #include <linux/clk.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/i2c.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/debugfs.h>
  18. #include <linux/of_fdt.h>
  19. #include "cam_io_util.h"
  20. #include <media/cam_defs.h>
  21. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  22. #include <linux/soc/qcom/msm_mmrm.h>
  23. #endif
  24. #define NO_SET_RATE -1
  25. #define INIT_RATE -2
  26. /* maximum number of device block */
  27. #define CAM_SOC_MAX_BLOCK 7
  28. /* maximum number of device base */
  29. #define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK
  30. /* maximum number of device regulator */
  31. #define CAM_SOC_MAX_REGULATOR 10
  32. /* maximum number of device clock */
  33. #define CAM_SOC_MAX_CLK 32
  34. /* maximum number of optional device clock */
  35. #define CAM_SOC_MAX_OPT_CLK 2
  36. /* maximum number of pinctrl mapping */
  37. #define CAM_SOC_MAX_PINCTRL_MAP 2
  38. /* DDR device types */
  39. #define DDR_TYPE_LPDDR4 6
  40. #define DDR_TYPE_LPDDR4X 7
  41. #define DDR_TYPE_LPDDR5 8
  42. #define DDR_TYPE_LPDDR5X 9
  43. /* Maximum length of tag while dumping */
  44. #define CAM_SOC_HW_DUMP_TAG_MAX_LEN 32
  45. /**
  46. * enum cam_vote_level - Enum for voting level
  47. *
  48. * @CAM_SUSPEND_VOTE : Suspend vote
  49. * @CAM_MINSVS_VOTE : Min SVS vote
  50. * @CAM_LOWSVS_VOTE : Low SVS vote
  51. * @CAM_SVS_VOTE : SVS vote
  52. * @CAM_SVSL1_VOTE : SVS Plus vote
  53. * @CAM_NOMINAL_VOTE : Nominal vote
  54. * @CAM_NOMINALL1_VOTE: Nominal plus vote
  55. * @CAM_TURBO_VOTE : Turbo vote
  56. * @CAM_MAX_VOTE : Max voting level, This is invalid level.
  57. */
  58. enum cam_vote_level {
  59. CAM_SUSPEND_VOTE,
  60. CAM_MINSVS_VOTE,
  61. CAM_LOWSVS_VOTE,
  62. CAM_SVS_VOTE,
  63. CAM_SVSL1_VOTE,
  64. CAM_NOMINAL_VOTE,
  65. CAM_NOMINALL1_VOTE,
  66. CAM_TURBO_VOTE,
  67. CAM_MAX_VOTE,
  68. };
  69. /* pinctrl states */
  70. #define CAM_SOC_PINCTRL_STATE_SLEEP "cam_suspend"
  71. #define CAM_SOC_PINCTRL_STATE_DEFAULT "cam_default"
  72. /**
  73. * struct cam_soc_reg_map: Information about the mapped register space
  74. *
  75. * @mem_base: Starting location of MAPPED register space
  76. * @mem_cam_base: Starting offset of this register space compared
  77. * to ENTIRE Camera register space
  78. * @size: Size of register space
  79. **/
  80. struct cam_soc_reg_map {
  81. void __iomem *mem_base;
  82. uint32_t mem_cam_base;
  83. resource_size_t size;
  84. };
  85. /**
  86. * struct cam_soc_pinctrl_state: Information about pinctrl state
  87. *
  88. * @gpio_state_active: default pinctrl state
  89. * @gpio_state_suspend: suspend state of pinctrl
  90. * @is_active: to identify if pinctrl is in use.
  91. **/
  92. struct cam_soc_pinctrl_state {
  93. struct pinctrl_state *gpio_state_active;
  94. struct pinctrl_state *gpio_state_suspend;
  95. bool is_active;
  96. };
  97. /**
  98. * struct cam_soc_pinctrl_info: Information about pinctrl data
  99. *
  100. * @pinctrl: pintrl object
  101. * @pctrl_state: pinctrl state montior map
  102. **/
  103. struct cam_soc_pinctrl_info {
  104. struct pinctrl *pinctrl;
  105. struct cam_soc_pinctrl_state pctrl_state[
  106. CAM_SOC_MAX_PINCTRL_MAP];
  107. };
  108. /**
  109. * struct cam_soc_gpio_data: Information about the gpio pins
  110. *
  111. * @cam_gpio_common_tbl: It is list of al the gpios present in gpios node
  112. * @cam_gpio_common_tbl_size: It is equal to number of gpios prsent in
  113. * gpios node in DTSI
  114. * @cam_gpio_req_tbl It is list of al the requesetd gpios
  115. * @cam_gpio_req_tbl_size: It is size of requested gpios
  116. **/
  117. struct cam_soc_gpio_data {
  118. struct gpio *cam_gpio_common_tbl;
  119. uint8_t cam_gpio_common_tbl_size;
  120. struct gpio *cam_gpio_req_tbl;
  121. uint8_t cam_gpio_req_tbl_size;
  122. };
  123. /**
  124. * struct cam_hw_soc_info: Soc information pertaining to specific instance of
  125. * Camera hardware driver module
  126. *
  127. * @pdev: Platform device pointer
  128. * @device: Device pointer
  129. * @hw_version: Camera device version
  130. * @index: Instance id for the camera device
  131. * @dev_name: Device Name
  132. * @is_nrt_dev: Whether this is a non-real time device
  133. * @irq_name: Name of the irq associated with the device
  134. * @label_name: label name
  135. * @irq_line: Irq resource
  136. * @irq_data: Private data that is passed when IRQ is requested
  137. * @compatible: Compatible string associated with the device
  138. * @num_mem_block: Number of entry in the "reg-names"
  139. * @mem_block_name: Array of the reg block name
  140. * @mem_block_cam_base: Array of offset of this register space compared
  141. * to ENTIRE Camera register space
  142. * @mem_block: Associated resource structs
  143. * @reg_map: Array of Mapped register info for the "reg-names"
  144. * @num_reg_map: Number of mapped register space associated
  145. * with mem_block. num_reg_map = num_mem_block in
  146. * most cases
  147. * @reserve_mem: Whether to reserve memory for Mem blocks
  148. * @num_rgltr: Number of regulators
  149. * @rgltr_name: Array of regulator names
  150. * @rgltr_ctrl_support: Whether regulator control is supported
  151. * @rgltr_min_volt: Array of minimum regulator voltage
  152. * @rgltr_max_volt: Array of maximum regulator voltage
  153. * @rgltr_op_mode: Array of regulator operation mode
  154. * @rgltr_type: Array of regulator names
  155. * @rgltr: Array of associated regulator resources
  156. * @rgltr_delay: Array of regulator delay values
  157. * @num_clk: Number of clocks
  158. * @clk_name: Array of clock names
  159. * @clk: Array of associated clock resources
  160. * @clk_rate: 2D array of clock rates representing clock rate
  161. * values at different vote levels
  162. * @clk_id Clock IDs
  163. * @shared_clk_mask Mask indicating which of the clocks are shared with
  164. * other devices. Set rate on these clocks needs to go
  165. * through camera clk wrapper for aggregation.
  166. * @prev_clk_level Last vote level
  167. * @src_clk_idx: Source clock index that is rate-controllable
  168. * @applied_src_clk_rate Current clock rate of the core source clk
  169. * @clk_level_valid: Indicates whether corresponding level is valid
  170. * @lowest_clk_level: Lowest clock level that has valid freq info
  171. * @scl_clk_count: Number of scalable clocks present
  172. * @scl_clk_idx: Index of scalable clocks
  173. * @optional_clk_name: Array of clock names
  174. * @optional_clk: Array of associated clock resources
  175. * @optional_clk_rate: Optional clock's clk rate
  176. * @optional_clk_id Clock IDs
  177. * @optional_shared_clk_mask Mask indicating which of the clocks are shared with
  178. * other devices. Set rate on these clocks needs to go
  179. * through camera clk wrapper for aggregation.
  180. * @gpio_data: Pointer to gpio info
  181. * @mmrm_handle: MMRM Client handle for src clock
  182. * @pinctrl_info: Pointer to pinctrl info
  183. * @dentry: Debugfs entry
  184. * @clk_level_override: Clk level set from debugfs
  185. * @clk_control: Enable/disable clk rate control through debugfs
  186. * @cam_cx_ipeak_enable cx-ipeak enable/disable flag
  187. * @cam_cx_ipeak_bit cx-ipeak mask for driver
  188. * @soc_private: Soc private data
  189. */
  190. struct cam_hw_soc_info {
  191. struct platform_device *pdev;
  192. struct device *dev;
  193. uint32_t hw_version;
  194. uint32_t index;
  195. const char *dev_name;
  196. bool is_nrt_dev;
  197. const char *irq_name;
  198. const char *label_name;
  199. struct resource *irq_line;
  200. void *irq_data;
  201. const char *compatible;
  202. uint32_t num_mem_block;
  203. const char *mem_block_name[CAM_SOC_MAX_BLOCK];
  204. uint32_t mem_block_cam_base[CAM_SOC_MAX_BLOCK];
  205. struct resource *mem_block[CAM_SOC_MAX_BLOCK];
  206. struct cam_soc_reg_map reg_map[CAM_SOC_MAX_BASE];
  207. uint32_t num_reg_map;
  208. uint32_t reserve_mem;
  209. uint32_t num_rgltr;
  210. const char *rgltr_name[CAM_SOC_MAX_REGULATOR];
  211. uint32_t rgltr_ctrl_support;
  212. uint32_t rgltr_min_volt[CAM_SOC_MAX_REGULATOR];
  213. uint32_t rgltr_max_volt[CAM_SOC_MAX_REGULATOR];
  214. uint32_t rgltr_op_mode[CAM_SOC_MAX_REGULATOR];
  215. uint32_t rgltr_type[CAM_SOC_MAX_REGULATOR];
  216. struct regulator *rgltr[CAM_SOC_MAX_REGULATOR];
  217. uint32_t rgltr_delay[CAM_SOC_MAX_REGULATOR];
  218. uint32_t use_shared_clk;
  219. uint32_t num_clk;
  220. const char *clk_name[CAM_SOC_MAX_CLK];
  221. struct clk *clk[CAM_SOC_MAX_CLK];
  222. int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
  223. uint32_t clk_id[CAM_SOC_MAX_CLK];
  224. uint32_t shared_clk_mask;
  225. int32_t prev_clk_level;
  226. int32_t src_clk_idx;
  227. unsigned long applied_src_clk_rate;
  228. bool clk_level_valid[CAM_MAX_VOTE];
  229. uint32_t lowest_clk_level;
  230. int32_t scl_clk_count;
  231. int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
  232. const char *optional_clk_name[CAM_SOC_MAX_OPT_CLK];
  233. struct clk *optional_clk[CAM_SOC_MAX_OPT_CLK];
  234. int32_t optional_clk_rate[CAM_SOC_MAX_OPT_CLK];
  235. uint32_t optional_clk_id[CAM_SOC_MAX_OPT_CLK];
  236. uint32_t optional_shared_clk_mask;
  237. void *mmrm_handle;
  238. struct cam_soc_gpio_data *gpio_data;
  239. struct cam_soc_pinctrl_info pinctrl_info;
  240. struct dentry *dentry;
  241. uint32_t clk_level_override;
  242. bool clk_control_enable;
  243. bool cam_cx_ipeak_enable;
  244. int32_t cam_cx_ipeak_bit;
  245. void *soc_private;
  246. };
  247. /**
  248. * struct cam_hw_soc_dump_header - SOC dump header
  249. *
  250. * @Brief: soc hw dump header
  251. *
  252. * @tag: Tag name for the header
  253. * @word_size: Size of each word
  254. * @size: Total size of dumped data
  255. */
  256. struct cam_hw_soc_dump_header {
  257. uint8_t tag[CAM_SOC_HW_DUMP_TAG_MAX_LEN];
  258. uint64_t size;
  259. uint32_t word_size;
  260. };
  261. /**
  262. * struct cam_hw_soc_dump_args: SOC Dump args
  263. *
  264. * @request_id: Issue request id
  265. * @offset: Buffer offset, updated as the informaton is dumped
  266. * @buf_handle: Buffer handle of the out buffer
  267. */
  268. struct cam_hw_soc_dump_args {
  269. uint64_t request_id;
  270. size_t offset;
  271. uint32_t buf_handle;
  272. };
  273. /*
  274. * CAM_SOC_GET_REG_MAP_START
  275. *
  276. * @brief: This MACRO will get the mapped starting address
  277. * where the register space can be accessed
  278. *
  279. * @__soc_info: Device soc information
  280. * @__base_index: Index of register space in the HW block
  281. *
  282. * @return: Returns a pointer to the mapped register memory
  283. */
  284. #define CAM_SOC_GET_REG_MAP_START(__soc_info, __base_index) \
  285. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  286. NULL : __soc_info->reg_map[__base_index].mem_base)
  287. /*
  288. * CAM_SOC_GET_REG_MAP_CAM_BASE
  289. *
  290. * @brief: This MACRO will get the cam_base of the
  291. * register space
  292. *
  293. * @__soc_info: Device soc information
  294. * @__base_index: Index of register space in the HW block
  295. *
  296. * @return: Returns an int32_t value.
  297. * Failure: -1
  298. * Success: Starting offset of register space compared
  299. * to entire Camera Register Map
  300. */
  301. #define CAM_SOC_GET_REG_MAP_CAM_BASE(__soc_info, __base_index) \
  302. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  303. -1 : __soc_info->reg_map[__base_index].mem_cam_base)
  304. /*
  305. * CAM_SOC_GET_REG_MAP_SIZE
  306. *
  307. * @brief: This MACRO will get the size of the mapped
  308. * register space
  309. *
  310. * @__soc_info: Device soc information
  311. * @__base_index: Index of register space in the HW block
  312. *
  313. * @return: Returns a uint32_t value.
  314. * Failure: 0
  315. * Success: Non-zero size of mapped register space
  316. */
  317. #define CAM_SOC_GET_REG_MAP_SIZE(__soc_info, __base_index) \
  318. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  319. 0 : __soc_info->reg_map[__base_index].size)
  320. /**
  321. * cam_soc_util_get_level_from_string()
  322. *
  323. * @brief: Get the associated vote level for the input string
  324. *
  325. * @string: Input string to compare with.
  326. * @level: Vote level corresponds to input string.
  327. *
  328. * @return: Success or failure
  329. */
  330. int cam_soc_util_get_level_from_string(const char *string,
  331. enum cam_vote_level *level);
  332. /**
  333. * cam_soc_util_get_dt_properties()
  334. *
  335. * @brief: Parse the DT and populate the common properties that
  336. * are part of the soc_info structure - register map,
  337. * clocks, regulators, irq, etc.
  338. *
  339. * @soc_info: Device soc struct to be populated
  340. *
  341. * @return: Success or failure
  342. */
  343. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info);
  344. /**
  345. * cam_soc_util_request_platform_resource()
  346. *
  347. * @brief: Request regulator, irq, and clock resources
  348. *
  349. * @soc_info: Device soc information
  350. * @handler: Irq handler function pointer
  351. * @irq_data: Irq handler function CB data
  352. *
  353. * @return: Success or failure
  354. */
  355. int cam_soc_util_request_platform_resource(struct cam_hw_soc_info *soc_info,
  356. irq_handler_t handler, void *irq_data);
  357. /**
  358. * cam_soc_util_release_platform_resource()
  359. *
  360. * @brief: Release regulator, irq, and clock resources
  361. *
  362. * @soc_info: Device soc information
  363. *
  364. * @return: Success or failure
  365. */
  366. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info);
  367. /**
  368. * cam_soc_util_enable_platform_resource()
  369. *
  370. * @brief: Enable regulator, irq resources
  371. *
  372. * @soc_info: Device soc information
  373. * @enable_clocks: Boolean flag:
  374. * TRUE: Enable all clocks in soc_info Now.
  375. * False: Don't enable clocks Now. Driver will
  376. * enable independently.
  377. * @clk_level: Clock level to be applied.
  378. * Applicable only if enable_clocks is true
  379. * Valid range : 0 to (CAM_MAX_VOTE - 1)
  380. * @enable_irq: Boolean flag:
  381. * TRUE: Enable IRQ in soc_info Now.
  382. * False: Don't enable IRQ Now. Driver will
  383. * enable independently.
  384. *
  385. * @return: Success or failure
  386. */
  387. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  388. bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq);
  389. /**
  390. * cam_soc_util_disable_platform_resource()
  391. *
  392. * @brief: Disable regulator, irq resources
  393. *
  394. * @soc_info: Device soc information
  395. * @disable_irq: Boolean flag:
  396. * TRUE: Disable IRQ in soc_info Now.
  397. * False: Don't disable IRQ Now. Driver will
  398. * disable independently.
  399. *
  400. * @return: Success or failure
  401. */
  402. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  403. bool disable_clocks, bool disable_irq);
  404. /**
  405. * cam_soc_util_get_clk_round_rate()
  406. *
  407. * @brief: Get the rounded clock rate for the given clock's
  408. * clock rate value
  409. *
  410. * @soc_info: Device soc information
  411. * @clk_index: Clock index in soc_info for which round rate is needed
  412. * @clk_rate: Input clock rate for which rounded rate is needed
  413. *
  414. * @return: Rounded clock rate
  415. */
  416. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  417. uint32_t clk_index, unsigned long clk_rate);
  418. /**
  419. * cam_soc_util_set_src_clk_rate()
  420. *
  421. * @brief: Set the rate on the source clock.
  422. *
  423. * @soc_info: Device soc information
  424. * @clk_rate: Clock rate associated with the src clk
  425. *
  426. * @return: success or failure
  427. */
  428. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
  429. int64_t clk_rate);
  430. /**
  431. * cam_soc_util_get_option_clk_by_name()
  432. *
  433. * @brief: Get reference to optional clk using name
  434. *
  435. * @soc_info: Device soc information
  436. * @clk_name: Name of clock to find reference for
  437. * @clk_index: Clk index in the option clk array to be returned
  438. *
  439. * @return: 0: Success
  440. * Negative: Failure
  441. */
  442. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  443. const char *clk_name, int32_t *clk_index);
  444. /**
  445. * cam_soc_util_put_optional_clk()
  446. *
  447. * @brief: Put clock corresponding to index specified in params
  448. *
  449. * @soc_info: Device soc information
  450. * @clk_idx: Clock index in optional clocks to put
  451. *
  452. * @return: Success or failure
  453. */
  454. int cam_soc_util_put_optional_clk(struct cam_hw_soc_info *soc_info,
  455. int32_t clk_idx);
  456. /**
  457. * cam_soc_util_clk_enable()
  458. *
  459. * @brief: Enable clock specified in params
  460. *
  461. * @soc_info: Device soc information
  462. * @optional_clk: Whether to set optional clk or normal clk with
  463. * the idx given
  464. * @clk_idx: Clock index to set
  465. * @apply_level: Apply level.
  466. * -1 for 0 rate
  467. * any other value indicate level for normal clocks
  468. * For optional clocks any other value means the rate saved
  469. * in soc_info
  470. * @applied_clock_rate Final Clock rate applied to the clk
  471. *
  472. * @return: Success or failure
  473. */
  474. int cam_soc_util_clk_enable(struct cam_hw_soc_info *soc_info,
  475. bool optional_clk, int32_t clk_idx, int32_t apply_level,
  476. unsigned long *applied_clock_rate);
  477. /**
  478. * cam_soc_util_set_clk_rate_level()
  479. *
  480. * @brief: Apply clock rates for the requested level.
  481. * This applies the new requested level for all
  482. * the clocks listed in DT based on their values.
  483. *
  484. * @soc_info: Device soc information
  485. * @clk_level: Clock level number to set
  486. * @do_not_set_src_clk: If true, set clock rates except the src clk
  487. *
  488. * @return: Success or failure
  489. */
  490. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  491. enum cam_vote_level clk_level, bool do_not_set_src_clk);
  492. /**
  493. * cam_soc_util_clk_disable()
  494. *
  495. * @brief: Disable clock specified in params
  496. *
  497. * @soc_info: Device soc information
  498. * @optional_clk: Whether to set optional clk or normal clk with
  499. * the idx given
  500. * @clk_idx: Clock index to disable
  501. *
  502. * @return: Success or failure
  503. */
  504. int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info,
  505. bool optional_clk, int32_t clk_idx);
  506. /**
  507. * cam_soc_util_irq_enable()
  508. *
  509. * @brief: Enable IRQ in SOC
  510. *
  511. * @soc_info: Device soc information
  512. *
  513. * @return: Success or failure
  514. */
  515. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info);
  516. /**
  517. * cam_soc_util_irq_disable()
  518. *
  519. * @brief: Disable IRQ in SOC
  520. *
  521. * @soc_info: Device soc information
  522. *
  523. * @return: Success or failure
  524. */
  525. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info);
  526. /**
  527. * cam_soc_util_regulator_enable()
  528. *
  529. * @brief: Enable single regulator
  530. *
  531. * @rgltr Regulator that needs to be turned ON
  532. * @rgltr_name Associated Regulator name
  533. * @rgltr_min_volt: Requested minimum volatage
  534. * @rgltr_max_volt: Requested maximum volatage
  535. * @rgltr_op_mode: Requested Load
  536. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  537. *
  538. * @return: Success or failure
  539. */
  540. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  541. const char *rgltr_name,
  542. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  543. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  544. /**
  545. * cam_soc_util_regulator_enable()
  546. *
  547. * @brief: Disable single regulator
  548. *
  549. * @rgltr Regulator that needs to be turned ON
  550. * @rgltr_name Associated Regulator name
  551. * @rgltr_min_volt: Requested minimum volatage
  552. * @rgltr_max_volt: Requested maximum volatage
  553. * @rgltr_op_mode: Requested Load
  554. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  555. *
  556. * @return: Success or failure
  557. */
  558. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  559. const char *rgltr_name,
  560. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  561. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  562. /**
  563. * cam_soc_util_w()
  564. *
  565. * @brief: Camera SOC util for register write
  566. *
  567. * @soc_info: Device soc information
  568. * @base_index: Index of register space in the HW block
  569. * @offset: Offset of register to be read
  570. * @data: Value to be written
  571. *
  572. * @return: Success or Failure
  573. */
  574. static inline int cam_soc_util_w(struct cam_hw_soc_info *soc_info,
  575. uint32_t base_index, uint32_t offset, uint32_t data)
  576. {
  577. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  578. return -EINVAL;
  579. return cam_io_w(data,
  580. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  581. }
  582. /**
  583. * cam_soc_util_w_mb()
  584. *
  585. * @brief: Camera SOC util for register write with memory barrier.
  586. * Memory Barrier is only before the write to ensure the
  587. * order. If need to ensure this write is also flushed
  588. * call wmb() independently in the caller.
  589. *
  590. * @soc_info: Device soc information
  591. * @base_index: Index of register space in the HW block
  592. * @offset: Offset of register to be read
  593. * @data: Value to be written
  594. *
  595. * @return: Success or Failure
  596. */
  597. static inline int cam_soc_util_w_mb(struct cam_hw_soc_info *soc_info,
  598. uint32_t base_index, uint32_t offset, uint32_t data)
  599. {
  600. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  601. return -EINVAL;
  602. return cam_io_w_mb(data,
  603. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  604. }
  605. /**
  606. * cam_soc_util_r()
  607. *
  608. * @brief: Camera SOC util for register read
  609. *
  610. * @soc_info: Device soc information
  611. * @base_index: Index of register space in the HW block
  612. * @offset: Offset of register to be read
  613. *
  614. * @return: Value read from the register address
  615. */
  616. static inline uint32_t cam_soc_util_r(struct cam_hw_soc_info *soc_info,
  617. uint32_t base_index, uint32_t offset)
  618. {
  619. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  620. return 0;
  621. return cam_io_r(
  622. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  623. }
  624. /**
  625. * cam_soc_util_r_mb()
  626. *
  627. * @brief: Camera SOC util for register read with memory barrier.
  628. * Memory Barrier is only before the write to ensure the
  629. * order. If need to ensure this write is also flushed
  630. * call rmb() independently in the caller.
  631. *
  632. * @soc_info: Device soc information
  633. * @base_index: Index of register space in the HW block
  634. * @offset: Offset of register to be read
  635. *
  636. * @return: Value read from the register address
  637. */
  638. static inline uint32_t cam_soc_util_r_mb(struct cam_hw_soc_info *soc_info,
  639. uint32_t base_index, uint32_t offset)
  640. {
  641. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  642. return 0;
  643. return cam_io_r_mb(
  644. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  645. }
  646. /**
  647. * cam_soc_util_reg_dump()
  648. *
  649. * @brief: Camera SOC util for dumping a range of register
  650. *
  651. * @soc_info: Device soc information
  652. * @base_index: Index of register space in the HW block
  653. * @offset: Start register offset for the dump
  654. * @size: Size specifying the range for dump
  655. *
  656. * @return: Success or Failure
  657. */
  658. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  659. uint32_t base_index, uint32_t offset, int size);
  660. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info);
  661. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  662. enum cam_vote_level clk_level);
  663. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  664. int64_t clk_rate, int clk_idx, int32_t *clk_lvl);
  665. /* Callback to get reg space data for specific HW */
  666. typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type,
  667. void *ctx, struct cam_hw_soc_info **soc_info_ptr,
  668. uint32_t *reg_base_idx);
  669. /**
  670. * cam_soc_util_reg_dump_to_cmd_buf()
  671. *
  672. * @brief: Camera SOC util for dumping sets of register ranges
  673. * command buffer
  674. *
  675. * @ctx: Context info from specific hardware manager
  676. * @cmd_desc: Command buffer descriptor
  677. * @req_id: Last applied req id for which reg dump is required
  678. * @reg_data_cb: Callback function to get reg space info based on type
  679. * in command buffer
  680. * @soc_dump_args: Dump buffer args to dump the soc information.
  681. * @user_triggered_dump: Flag to indicate if the dump request is issued by
  682. * user.
  683. * @return: Success or Failure
  684. */
  685. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  686. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  687. cam_soc_util_regspace_data_cb reg_data_cb,
  688. struct cam_hw_soc_dump_args *soc_dump_args,
  689. bool user_triggered_dump);
  690. /**
  691. * cam_soc_util_print_clk_freq()
  692. *
  693. * @brief: This function gets the clk rates for each clk from clk
  694. * driver and prints in log
  695. *
  696. * @soc_info: Device soc struct to be populated
  697. *
  698. * @return: success or failure
  699. */
  700. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info);
  701. /**
  702. * cam_soc_util_select_pinctrl_state()
  703. *
  704. * @brief: This function gets the pinctrl handle
  705. *
  706. * @soc_info: Device soc struct to be populated
  707. * @active: True for active and false for suspend state
  708. *
  709. * @return: success or failure
  710. */
  711. int cam_soc_util_select_pinctrl_state(
  712. struct cam_hw_soc_info *soc_info, int idx, bool active);
  713. #endif /* _CAM_SOC_UTIL_H_ */