dp_tx.c 164 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  115. /**
  116. * dp_update_tx_desc_stats - Update the increase or decrease in
  117. * outstanding tx desc count
  118. * values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  125. {
  126. int32_t tx_descs_cnt =
  127. qdf_atomic_read(&pdev->num_tx_outstanding);
  128. if (pdev->tx_descs_max < tx_descs_cnt)
  129. pdev->tx_descs_max = tx_descs_cnt;
  130. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  131. pdev->tx_descs_max);
  132. }
  133. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  134. static inline void
  135. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  136. {
  137. }
  138. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  139. #ifdef QCA_TX_LIMIT_CHECK
  140. /**
  141. * dp_tx_limit_check - Check if allocated tx descriptors reached
  142. * soc max limit and pdev max limit
  143. * @vdev: DP vdev handle
  144. *
  145. * Return: true if allocated tx descriptors reached max configured value, else
  146. * false
  147. */
  148. static inline bool
  149. dp_tx_limit_check(struct dp_vdev *vdev)
  150. {
  151. struct dp_pdev *pdev = vdev->pdev;
  152. struct dp_soc *soc = pdev->soc;
  153. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  154. soc->num_tx_allowed) {
  155. dp_tx_info("queued packets are more than max tx, drop the frame");
  156. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  157. return true;
  158. }
  159. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  160. pdev->num_tx_allowed) {
  161. dp_tx_info("queued packets are more than max tx, drop the frame");
  162. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  163. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  164. return true;
  165. }
  166. return false;
  167. }
  168. /**
  169. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  170. * reached soc max limit
  171. * @vdev: DP vdev handle
  172. *
  173. * Return: true if allocated tx descriptors reached max configured value, else
  174. * false
  175. */
  176. static inline bool
  177. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  178. {
  179. struct dp_pdev *pdev = vdev->pdev;
  180. struct dp_soc *soc = pdev->soc;
  181. if (qdf_atomic_read(&soc->num_tx_exception) >=
  182. soc->num_msdu_exception_desc) {
  183. dp_info("exc packets are more than max drop the exc pkt");
  184. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  185. return true;
  186. }
  187. return false;
  188. }
  189. /**
  190. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  191. * @vdev: DP pdev handle
  192. *
  193. * Return: void
  194. */
  195. static inline void
  196. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  197. {
  198. struct dp_soc *soc = pdev->soc;
  199. qdf_atomic_inc(&pdev->num_tx_outstanding);
  200. qdf_atomic_inc(&soc->num_tx_outstanding);
  201. dp_update_tx_desc_stats(pdev);
  202. }
  203. /**
  204. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  205. * @vdev: DP pdev handle
  206. *
  207. * Return: void
  208. */
  209. static inline void
  210. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  211. {
  212. struct dp_soc *soc = pdev->soc;
  213. qdf_atomic_dec(&pdev->num_tx_outstanding);
  214. qdf_atomic_dec(&soc->num_tx_outstanding);
  215. dp_update_tx_desc_stats(pdev);
  216. }
  217. #else //QCA_TX_LIMIT_CHECK
  218. static inline bool
  219. dp_tx_limit_check(struct dp_vdev *vdev)
  220. {
  221. return false;
  222. }
  223. static inline bool
  224. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  225. {
  226. return false;
  227. }
  228. static inline void
  229. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  230. {
  231. qdf_atomic_inc(&pdev->num_tx_outstanding);
  232. dp_update_tx_desc_stats(pdev);
  233. }
  234. static inline void
  235. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  236. {
  237. qdf_atomic_dec(&pdev->num_tx_outstanding);
  238. dp_update_tx_desc_stats(pdev);
  239. }
  240. #endif //QCA_TX_LIMIT_CHECK
  241. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  242. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  243. {
  244. enum dp_tx_event_type type;
  245. if (flags & DP_TX_DESC_FLAG_FLUSH)
  246. type = DP_TX_DESC_FLUSH;
  247. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  248. type = DP_TX_COMP_UNMAP_ERR;
  249. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  250. type = DP_TX_COMP_UNMAP;
  251. else
  252. type = DP_TX_DESC_UNMAP;
  253. return type;
  254. }
  255. static inline void
  256. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  257. qdf_nbuf_t skb, uint32_t sw_cookie,
  258. enum dp_tx_event_type type)
  259. {
  260. struct dp_tx_desc_event *entry;
  261. uint32_t idx;
  262. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  263. return;
  264. switch (type) {
  265. case DP_TX_COMP_UNMAP:
  266. case DP_TX_COMP_UNMAP_ERR:
  267. case DP_TX_COMP_MSDU_EXT:
  268. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  269. DP_TX_COMP_HISTORY_SIZE);
  270. entry = &soc->tx_comp_history->entry[idx];
  271. break;
  272. case DP_TX_DESC_MAP:
  273. case DP_TX_DESC_UNMAP:
  274. case DP_TX_DESC_COOKIE:
  275. case DP_TX_DESC_FLUSH:
  276. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  277. DP_TX_TCL_HISTORY_SIZE);
  278. entry = &soc->tx_tcl_history->entry[idx];
  279. break;
  280. default:
  281. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  282. return;
  283. }
  284. entry->skb = skb;
  285. entry->paddr = paddr;
  286. entry->sw_cookie = sw_cookie;
  287. entry->type = type;
  288. entry->ts = qdf_get_log_timestamp();
  289. }
  290. static inline void
  291. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  292. struct qdf_tso_seg_elem_t *tso_seg,
  293. qdf_nbuf_t skb, uint32_t sw_cookie,
  294. enum dp_tx_event_type type)
  295. {
  296. int i;
  297. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  298. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  299. skb, sw_cookie, type);
  300. }
  301. if (!tso_seg->next)
  302. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  303. skb, 0xFFFFFFFF, type);
  304. }
  305. static inline void
  306. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  307. qdf_nbuf_t skb, uint32_t sw_cookie,
  308. enum dp_tx_event_type type)
  309. {
  310. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  311. uint32_t num_segs = tso_info.num_segs;
  312. while (num_segs) {
  313. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  314. curr_seg = curr_seg->next;
  315. num_segs--;
  316. }
  317. }
  318. #else
  319. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  320. {
  321. return DP_TX_DESC_INVAL_EVT;
  322. }
  323. static inline void
  324. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  325. qdf_nbuf_t skb, uint32_t sw_cookie,
  326. enum dp_tx_event_type type)
  327. {
  328. }
  329. static inline void
  330. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  331. struct qdf_tso_seg_elem_t *tso_seg,
  332. qdf_nbuf_t skb, uint32_t sw_cookie,
  333. enum dp_tx_event_type type)
  334. {
  335. }
  336. static inline void
  337. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  338. qdf_nbuf_t skb, uint32_t sw_cookie,
  339. enum dp_tx_event_type type)
  340. {
  341. }
  342. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  343. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  344. /**
  345. * dp_is_tput_high() - Check if throughput is high
  346. *
  347. * @soc - core txrx main context
  348. *
  349. * The current function is based of the RTPM tput policy variable where RTPM is
  350. * avoided based on throughput.
  351. */
  352. static inline int dp_is_tput_high(struct dp_soc *soc)
  353. {
  354. return dp_get_rtpm_tput_policy_requirement(soc);
  355. }
  356. #if defined(FEATURE_TSO)
  357. /**
  358. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  359. *
  360. * @soc - core txrx main context
  361. * @seg_desc - tso segment descriptor
  362. * @num_seg_desc - tso number segment descriptor
  363. */
  364. static void dp_tx_tso_unmap_segment(
  365. struct dp_soc *soc,
  366. struct qdf_tso_seg_elem_t *seg_desc,
  367. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  368. {
  369. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  370. if (qdf_unlikely(!seg_desc)) {
  371. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  372. __func__, __LINE__);
  373. qdf_assert(0);
  374. } else if (qdf_unlikely(!num_seg_desc)) {
  375. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  376. __func__, __LINE__);
  377. qdf_assert(0);
  378. } else {
  379. bool is_last_seg;
  380. /* no tso segment left to do dma unmap */
  381. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  382. return;
  383. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  384. true : false;
  385. qdf_nbuf_unmap_tso_segment(soc->osdev,
  386. seg_desc, is_last_seg);
  387. num_seg_desc->num_seg.tso_cmn_num_seg--;
  388. }
  389. }
  390. /**
  391. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  392. * back to the freelist
  393. *
  394. * @soc - soc device handle
  395. * @tx_desc - Tx software descriptor
  396. */
  397. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  398. struct dp_tx_desc_s *tx_desc)
  399. {
  400. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  401. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  402. dp_tx_err("SO desc is NULL!");
  403. qdf_assert(0);
  404. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  405. dp_tx_err("TSO num desc is NULL!");
  406. qdf_assert(0);
  407. } else {
  408. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  409. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  410. msdu_ext_desc->tso_num_desc;
  411. /* Add the tso num segment into the free list */
  412. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  413. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  414. tx_desc->msdu_ext_desc->
  415. tso_num_desc);
  416. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  417. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  418. }
  419. /* Add the tso segment into the free list*/
  420. dp_tx_tso_desc_free(soc,
  421. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  422. tso_desc);
  423. tx_desc->msdu_ext_desc->tso_desc = NULL;
  424. }
  425. }
  426. #else
  427. static void dp_tx_tso_unmap_segment(
  428. struct dp_soc *soc,
  429. struct qdf_tso_seg_elem_t *seg_desc,
  430. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  431. {
  432. }
  433. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  434. struct dp_tx_desc_s *tx_desc)
  435. {
  436. }
  437. #endif
  438. /**
  439. * dp_tx_desc_release() - Release Tx Descriptor
  440. * @tx_desc : Tx Descriptor
  441. * @desc_pool_id: Descriptor Pool ID
  442. *
  443. * Deallocate all resources attached to Tx descriptor and free the Tx
  444. * descriptor.
  445. *
  446. * Return:
  447. */
  448. void
  449. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  450. {
  451. struct dp_pdev *pdev = tx_desc->pdev;
  452. struct dp_soc *soc;
  453. uint8_t comp_status = 0;
  454. qdf_assert(pdev);
  455. soc = pdev->soc;
  456. dp_tx_outstanding_dec(pdev);
  457. if (tx_desc->msdu_ext_desc) {
  458. if (tx_desc->frm_type == dp_tx_frm_tso)
  459. dp_tx_tso_desc_release(soc, tx_desc);
  460. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  461. dp_tx_me_free_buf(tx_desc->pdev,
  462. tx_desc->msdu_ext_desc->me_buffer);
  463. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  464. }
  465. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  466. qdf_atomic_dec(&soc->num_tx_exception);
  467. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  468. tx_desc->buffer_src)
  469. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  470. soc->hal_soc);
  471. else
  472. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  473. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  474. tx_desc->id, comp_status,
  475. qdf_atomic_read(&pdev->num_tx_outstanding));
  476. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  477. return;
  478. }
  479. /**
  480. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  481. * @vdev: DP vdev Handle
  482. * @nbuf: skb
  483. * @msdu_info: msdu_info required to create HTT metadata
  484. *
  485. * Prepares and fills HTT metadata in the frame pre-header for special frames
  486. * that should be transmitted using varying transmit parameters.
  487. * There are 2 VDEV modes that currently needs this special metadata -
  488. * 1) Mesh Mode
  489. * 2) DSRC Mode
  490. *
  491. * Return: HTT metadata size
  492. *
  493. */
  494. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  495. struct dp_tx_msdu_info_s *msdu_info)
  496. {
  497. uint32_t *meta_data = msdu_info->meta_data;
  498. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  499. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  500. uint8_t htt_desc_size;
  501. /* Size rounded of multiple of 8 bytes */
  502. uint8_t htt_desc_size_aligned;
  503. uint8_t *hdr = NULL;
  504. /*
  505. * Metadata - HTT MSDU Extension header
  506. */
  507. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  508. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  509. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  510. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  511. meta_data[0]) ||
  512. msdu_info->exception_fw) {
  513. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  514. htt_desc_size_aligned)) {
  515. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  516. htt_desc_size_aligned);
  517. if (!nbuf) {
  518. /*
  519. * qdf_nbuf_realloc_headroom won't do skb_clone
  520. * as skb_realloc_headroom does. so, no free is
  521. * needed here.
  522. */
  523. DP_STATS_INC(vdev,
  524. tx_i.dropped.headroom_insufficient,
  525. 1);
  526. qdf_print(" %s[%d] skb_realloc_headroom failed",
  527. __func__, __LINE__);
  528. return 0;
  529. }
  530. }
  531. /* Fill and add HTT metaheader */
  532. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  533. if (!hdr) {
  534. dp_tx_err("Error in filling HTT metadata");
  535. return 0;
  536. }
  537. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  538. } else if (vdev->opmode == wlan_op_mode_ocb) {
  539. /* Todo - Add support for DSRC */
  540. }
  541. return htt_desc_size_aligned;
  542. }
  543. /**
  544. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  545. * @tso_seg: TSO segment to process
  546. * @ext_desc: Pointer to MSDU extension descriptor
  547. *
  548. * Return: void
  549. */
  550. #if defined(FEATURE_TSO)
  551. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  552. void *ext_desc)
  553. {
  554. uint8_t num_frag;
  555. uint32_t tso_flags;
  556. /*
  557. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  558. * tcp_flag_mask
  559. *
  560. * Checksum enable flags are set in TCL descriptor and not in Extension
  561. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  562. */
  563. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  564. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  565. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  566. tso_seg->tso_flags.ip_len);
  567. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  568. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  569. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  570. uint32_t lo = 0;
  571. uint32_t hi = 0;
  572. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  573. (tso_seg->tso_frags[num_frag].length));
  574. qdf_dmaaddr_to_32s(
  575. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  576. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  577. tso_seg->tso_frags[num_frag].length);
  578. }
  579. return;
  580. }
  581. #else
  582. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  583. void *ext_desc)
  584. {
  585. return;
  586. }
  587. #endif
  588. #if defined(FEATURE_TSO)
  589. /**
  590. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  591. * allocated and free them
  592. *
  593. * @soc: soc handle
  594. * @free_seg: list of tso segments
  595. * @msdu_info: msdu descriptor
  596. *
  597. * Return - void
  598. */
  599. static void dp_tx_free_tso_seg_list(
  600. struct dp_soc *soc,
  601. struct qdf_tso_seg_elem_t *free_seg,
  602. struct dp_tx_msdu_info_s *msdu_info)
  603. {
  604. struct qdf_tso_seg_elem_t *next_seg;
  605. while (free_seg) {
  606. next_seg = free_seg->next;
  607. dp_tx_tso_desc_free(soc,
  608. msdu_info->tx_queue.desc_pool_id,
  609. free_seg);
  610. free_seg = next_seg;
  611. }
  612. }
  613. /**
  614. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  615. * allocated and free them
  616. *
  617. * @soc: soc handle
  618. * @free_num_seg: list of tso number segments
  619. * @msdu_info: msdu descriptor
  620. * Return - void
  621. */
  622. static void dp_tx_free_tso_num_seg_list(
  623. struct dp_soc *soc,
  624. struct qdf_tso_num_seg_elem_t *free_num_seg,
  625. struct dp_tx_msdu_info_s *msdu_info)
  626. {
  627. struct qdf_tso_num_seg_elem_t *next_num_seg;
  628. while (free_num_seg) {
  629. next_num_seg = free_num_seg->next;
  630. dp_tso_num_seg_free(soc,
  631. msdu_info->tx_queue.desc_pool_id,
  632. free_num_seg);
  633. free_num_seg = next_num_seg;
  634. }
  635. }
  636. /**
  637. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  638. * do dma unmap for each segment
  639. *
  640. * @soc: soc handle
  641. * @free_seg: list of tso segments
  642. * @num_seg_desc: tso number segment descriptor
  643. *
  644. * Return - void
  645. */
  646. static void dp_tx_unmap_tso_seg_list(
  647. struct dp_soc *soc,
  648. struct qdf_tso_seg_elem_t *free_seg,
  649. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  650. {
  651. struct qdf_tso_seg_elem_t *next_seg;
  652. if (qdf_unlikely(!num_seg_desc)) {
  653. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  654. return;
  655. }
  656. while (free_seg) {
  657. next_seg = free_seg->next;
  658. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  659. free_seg = next_seg;
  660. }
  661. }
  662. #ifdef FEATURE_TSO_STATS
  663. /**
  664. * dp_tso_get_stats_idx: Retrieve the tso packet id
  665. * @pdev - pdev handle
  666. *
  667. * Return: id
  668. */
  669. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  670. {
  671. uint32_t stats_idx;
  672. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  673. % CDP_MAX_TSO_PACKETS);
  674. return stats_idx;
  675. }
  676. #else
  677. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  678. {
  679. return 0;
  680. }
  681. #endif /* FEATURE_TSO_STATS */
  682. /**
  683. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  684. * free the tso segments descriptor and
  685. * tso num segments descriptor
  686. *
  687. * @soc: soc handle
  688. * @msdu_info: msdu descriptor
  689. * @tso_seg_unmap: flag to show if dma unmap is necessary
  690. *
  691. * Return - void
  692. */
  693. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  694. struct dp_tx_msdu_info_s *msdu_info,
  695. bool tso_seg_unmap)
  696. {
  697. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  698. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  699. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  700. tso_info->tso_num_seg_list;
  701. /* do dma unmap for each segment */
  702. if (tso_seg_unmap)
  703. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  704. /* free all tso number segment descriptor though looks only have 1 */
  705. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  706. /* free all tso segment descriptor */
  707. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  708. }
  709. /**
  710. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  711. * @vdev: virtual device handle
  712. * @msdu: network buffer
  713. * @msdu_info: meta data associated with the msdu
  714. *
  715. * Return: QDF_STATUS_SUCCESS success
  716. */
  717. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  718. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  719. {
  720. struct qdf_tso_seg_elem_t *tso_seg;
  721. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  722. struct dp_soc *soc = vdev->pdev->soc;
  723. struct dp_pdev *pdev = vdev->pdev;
  724. struct qdf_tso_info_t *tso_info;
  725. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  726. tso_info = &msdu_info->u.tso_info;
  727. tso_info->curr_seg = NULL;
  728. tso_info->tso_seg_list = NULL;
  729. tso_info->num_segs = num_seg;
  730. msdu_info->frm_type = dp_tx_frm_tso;
  731. tso_info->tso_num_seg_list = NULL;
  732. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  733. while (num_seg) {
  734. tso_seg = dp_tx_tso_desc_alloc(
  735. soc, msdu_info->tx_queue.desc_pool_id);
  736. if (tso_seg) {
  737. tso_seg->next = tso_info->tso_seg_list;
  738. tso_info->tso_seg_list = tso_seg;
  739. num_seg--;
  740. } else {
  741. dp_err_rl("Failed to alloc tso seg desc");
  742. DP_STATS_INC_PKT(vdev->pdev,
  743. tso_stats.tso_no_mem_dropped, 1,
  744. qdf_nbuf_len(msdu));
  745. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  746. return QDF_STATUS_E_NOMEM;
  747. }
  748. }
  749. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  750. tso_num_seg = dp_tso_num_seg_alloc(soc,
  751. msdu_info->tx_queue.desc_pool_id);
  752. if (tso_num_seg) {
  753. tso_num_seg->next = tso_info->tso_num_seg_list;
  754. tso_info->tso_num_seg_list = tso_num_seg;
  755. } else {
  756. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  757. __func__);
  758. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  759. return QDF_STATUS_E_NOMEM;
  760. }
  761. msdu_info->num_seg =
  762. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  763. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  764. msdu_info->num_seg);
  765. if (!(msdu_info->num_seg)) {
  766. /*
  767. * Free allocated TSO seg desc and number seg desc,
  768. * do unmap for segments if dma map has done.
  769. */
  770. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  771. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  772. return QDF_STATUS_E_INVAL;
  773. }
  774. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  775. msdu, 0, DP_TX_DESC_MAP);
  776. tso_info->curr_seg = tso_info->tso_seg_list;
  777. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  778. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  779. msdu, msdu_info->num_seg);
  780. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  781. tso_info->msdu_stats_idx);
  782. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  783. return QDF_STATUS_SUCCESS;
  784. }
  785. #else
  786. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  787. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  788. {
  789. return QDF_STATUS_E_NOMEM;
  790. }
  791. #endif
  792. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  793. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  794. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  795. /**
  796. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  797. * @vdev: DP Vdev handle
  798. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  799. * @desc_pool_id: Descriptor Pool ID
  800. *
  801. * Return:
  802. */
  803. static
  804. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  805. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  806. {
  807. uint8_t i;
  808. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  809. struct dp_tx_seg_info_s *seg_info;
  810. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  811. struct dp_soc *soc = vdev->pdev->soc;
  812. /* Allocate an extension descriptor */
  813. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  814. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  815. if (!msdu_ext_desc) {
  816. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  817. return NULL;
  818. }
  819. if (msdu_info->exception_fw &&
  820. qdf_unlikely(vdev->mesh_vdev)) {
  821. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  822. &msdu_info->meta_data[0],
  823. sizeof(struct htt_tx_msdu_desc_ext2_t));
  824. qdf_atomic_inc(&soc->num_tx_exception);
  825. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  826. }
  827. switch (msdu_info->frm_type) {
  828. case dp_tx_frm_sg:
  829. case dp_tx_frm_me:
  830. case dp_tx_frm_raw:
  831. seg_info = msdu_info->u.sg_info.curr_seg;
  832. /* Update the buffer pointers in MSDU Extension Descriptor */
  833. for (i = 0; i < seg_info->frag_cnt; i++) {
  834. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  835. seg_info->frags[i].paddr_lo,
  836. seg_info->frags[i].paddr_hi,
  837. seg_info->frags[i].len);
  838. }
  839. break;
  840. case dp_tx_frm_tso:
  841. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  842. &cached_ext_desc[0]);
  843. break;
  844. default:
  845. break;
  846. }
  847. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  848. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  849. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  850. msdu_ext_desc->vaddr);
  851. return msdu_ext_desc;
  852. }
  853. /**
  854. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  855. *
  856. * @skb: skb to be traced
  857. * @msdu_id: msdu_id of the packet
  858. * @vdev_id: vdev_id of the packet
  859. *
  860. * Return: None
  861. */
  862. #ifdef DP_DISABLE_TX_PKT_TRACE
  863. static void dp_tx_trace_pkt(struct dp_soc *soc,
  864. qdf_nbuf_t skb, uint16_t msdu_id,
  865. uint8_t vdev_id)
  866. {
  867. }
  868. #else
  869. static void dp_tx_trace_pkt(struct dp_soc *soc,
  870. qdf_nbuf_t skb, uint16_t msdu_id,
  871. uint8_t vdev_id)
  872. {
  873. if (dp_is_tput_high(soc))
  874. return;
  875. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  876. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  877. DPTRACE(qdf_dp_trace_ptr(skb,
  878. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  879. QDF_TRACE_DEFAULT_PDEV_ID,
  880. qdf_nbuf_data_addr(skb),
  881. sizeof(qdf_nbuf_data(skb)),
  882. msdu_id, vdev_id, 0));
  883. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  884. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  885. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  886. msdu_id, QDF_TX));
  887. }
  888. #endif
  889. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  890. /**
  891. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  892. * exception by the upper layer (OS_IF)
  893. * @soc: DP soc handle
  894. * @nbuf: packet to be transmitted
  895. *
  896. * Returns: 1 if the packet is marked as exception,
  897. * 0, if the packet is not marked as exception.
  898. */
  899. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  900. qdf_nbuf_t nbuf)
  901. {
  902. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  903. }
  904. #else
  905. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  906. qdf_nbuf_t nbuf)
  907. {
  908. return 0;
  909. }
  910. #endif
  911. #ifdef DP_TRAFFIC_END_INDICATION
  912. /**
  913. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  914. * as indication to fw to inform that
  915. * data stream has ended
  916. * @vdev: DP vdev handle
  917. * @nbuf: original buffer from network stack
  918. *
  919. * Return: NULL on failure,
  920. * nbuf on success
  921. */
  922. static inline qdf_nbuf_t
  923. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  924. qdf_nbuf_t nbuf)
  925. {
  926. /* Packet length should be enough to copy upto L3 header */
  927. uint8_t end_nbuf_len = 64;
  928. uint8_t htt_desc_size_aligned;
  929. uint8_t htt_desc_size;
  930. qdf_nbuf_t end_nbuf;
  931. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  932. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  933. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  934. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  935. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  936. if (!end_nbuf) {
  937. end_nbuf = qdf_nbuf_alloc(NULL,
  938. (htt_desc_size_aligned +
  939. end_nbuf_len),
  940. htt_desc_size_aligned,
  941. 8, false);
  942. if (!end_nbuf) {
  943. dp_err("Packet allocation failed");
  944. goto out;
  945. }
  946. } else {
  947. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  948. }
  949. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  950. end_nbuf_len);
  951. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  952. return end_nbuf;
  953. }
  954. out:
  955. return NULL;
  956. }
  957. /**
  958. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  959. * via exception path.
  960. * @vdev: DP vdev handle
  961. * @end_nbuf: skb to send as indication
  962. * @msdu_info: msdu_info of original nbuf
  963. * @peer_id: peer id
  964. *
  965. * Return: None
  966. */
  967. static inline void
  968. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  969. qdf_nbuf_t end_nbuf,
  970. struct dp_tx_msdu_info_s *msdu_info,
  971. uint16_t peer_id)
  972. {
  973. struct dp_tx_msdu_info_s e_msdu_info = {0};
  974. qdf_nbuf_t nbuf;
  975. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  976. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  977. e_msdu_info.tx_queue = msdu_info->tx_queue;
  978. e_msdu_info.tid = msdu_info->tid;
  979. e_msdu_info.exception_fw = 1;
  980. desc_ext->host_tx_desc_pool = 1;
  981. desc_ext->traffic_end_indication = 1;
  982. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  983. peer_id, NULL);
  984. if (nbuf) {
  985. dp_err("Traffic end indication packet tx failed");
  986. qdf_nbuf_free(nbuf);
  987. }
  988. }
  989. /**
  990. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  991. * mark it trafic end indication
  992. * packet.
  993. * @tx_desc: Tx descriptor pointer
  994. * @msdu_info: msdu_info structure pointer
  995. *
  996. * Return: None
  997. */
  998. static inline void
  999. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  1000. struct dp_tx_msdu_info_s *msdu_info)
  1001. {
  1002. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  1003. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  1004. if (qdf_unlikely(desc_ext->traffic_end_indication))
  1005. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  1006. }
  1007. /**
  1008. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  1009. * freeing which are associated
  1010. * with traffic end indication
  1011. * flagged descriptor.
  1012. * @soc: dp soc handle
  1013. * @desc: Tx descriptor pointer
  1014. * @nbuf: buffer pointer
  1015. *
  1016. * Return: True if packet gets enqueued else false
  1017. */
  1018. static bool
  1019. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  1020. struct dp_tx_desc_s *desc,
  1021. qdf_nbuf_t nbuf)
  1022. {
  1023. struct dp_vdev *vdev = NULL;
  1024. if (qdf_unlikely((desc->flags &
  1025. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  1026. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  1027. DP_MOD_ID_TX_COMP);
  1028. if (vdev) {
  1029. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  1030. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  1031. return true;
  1032. }
  1033. }
  1034. return false;
  1035. }
  1036. /**
  1037. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  1038. * enable/disable status
  1039. * @vdev: dp vdev handle
  1040. *
  1041. * Return: True if feature is enable else false
  1042. */
  1043. static inline bool
  1044. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  1045. {
  1046. return qdf_unlikely(vdev->traffic_end_ind_en);
  1047. }
  1048. static inline qdf_nbuf_t
  1049. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1050. struct dp_tx_msdu_info_s *msdu_info,
  1051. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  1052. {
  1053. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  1054. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  1055. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  1056. if (qdf_unlikely(end_nbuf))
  1057. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  1058. msdu_info, peer_id);
  1059. return nbuf;
  1060. }
  1061. #else
  1062. static inline qdf_nbuf_t
  1063. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  1064. qdf_nbuf_t nbuf)
  1065. {
  1066. return NULL;
  1067. }
  1068. static inline void
  1069. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  1070. qdf_nbuf_t end_nbuf,
  1071. struct dp_tx_msdu_info_s *msdu_info,
  1072. uint16_t peer_id)
  1073. {}
  1074. static inline void
  1075. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  1076. struct dp_tx_msdu_info_s *msdu_info)
  1077. {}
  1078. static inline bool
  1079. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  1080. struct dp_tx_desc_s *desc,
  1081. qdf_nbuf_t nbuf)
  1082. {
  1083. return false;
  1084. }
  1085. static inline bool
  1086. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  1087. {
  1088. return false;
  1089. }
  1090. static inline qdf_nbuf_t
  1091. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1092. struct dp_tx_msdu_info_s *msdu_info,
  1093. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  1094. {
  1095. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  1096. }
  1097. #endif
  1098. /**
  1099. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  1100. * @vdev: DP vdev handle
  1101. * @nbuf: skb
  1102. * @desc_pool_id: Descriptor pool ID
  1103. * @meta_data: Metadata to the fw
  1104. * @tx_exc_metadata: Handle that holds exception path metadata
  1105. * Allocate and prepare Tx descriptor with msdu information.
  1106. *
  1107. * Return: Pointer to Tx Descriptor on success,
  1108. * NULL on failure
  1109. */
  1110. static
  1111. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1112. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1113. struct dp_tx_msdu_info_s *msdu_info,
  1114. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1115. {
  1116. uint8_t align_pad;
  1117. uint8_t is_exception = 0;
  1118. uint8_t htt_hdr_size;
  1119. struct dp_tx_desc_s *tx_desc;
  1120. struct dp_pdev *pdev = vdev->pdev;
  1121. struct dp_soc *soc = pdev->soc;
  1122. if (dp_tx_limit_check(vdev))
  1123. return NULL;
  1124. /* Allocate software Tx descriptor */
  1125. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1126. if (qdf_unlikely(!tx_desc)) {
  1127. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1128. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1129. return NULL;
  1130. }
  1131. dp_tx_outstanding_inc(pdev);
  1132. /* Initialize the SW tx descriptor */
  1133. tx_desc->nbuf = nbuf;
  1134. tx_desc->frm_type = dp_tx_frm_std;
  1135. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1136. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1137. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1138. tx_desc->vdev_id = vdev->vdev_id;
  1139. tx_desc->pdev = pdev;
  1140. tx_desc->msdu_ext_desc = NULL;
  1141. tx_desc->pkt_offset = 0;
  1142. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1143. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1144. if (qdf_unlikely(vdev->multipass_en)) {
  1145. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1146. goto failure;
  1147. }
  1148. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1149. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1150. is_exception = 1;
  1151. /*
  1152. * For special modes (vdev_type == ocb or mesh), data frames should be
  1153. * transmitted using varying transmit parameters (tx spec) which include
  1154. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1155. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1156. * These frames are sent as exception packets to firmware.
  1157. *
  1158. * HW requirement is that metadata should always point to a
  1159. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1160. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1161. * to get 8-byte aligned start address along with align_pad added
  1162. *
  1163. * |-----------------------------|
  1164. * | |
  1165. * |-----------------------------| <-----Buffer Pointer Address given
  1166. * | | ^ in HW descriptor (aligned)
  1167. * | HTT Metadata | |
  1168. * | | |
  1169. * | | | Packet Offset given in descriptor
  1170. * | | |
  1171. * |-----------------------------| |
  1172. * | Alignment Pad | v
  1173. * |-----------------------------| <----- Actual buffer start address
  1174. * | SKB Data | (Unaligned)
  1175. * | |
  1176. * | |
  1177. * | |
  1178. * | |
  1179. * | |
  1180. * |-----------------------------|
  1181. */
  1182. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1183. (vdev->opmode == wlan_op_mode_ocb) ||
  1184. (tx_exc_metadata &&
  1185. tx_exc_metadata->is_tx_sniffer)) {
  1186. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1187. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1188. DP_STATS_INC(vdev,
  1189. tx_i.dropped.headroom_insufficient, 1);
  1190. goto failure;
  1191. }
  1192. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1193. dp_tx_err("qdf_nbuf_push_head failed");
  1194. goto failure;
  1195. }
  1196. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1197. msdu_info);
  1198. if (htt_hdr_size == 0)
  1199. goto failure;
  1200. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1201. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1202. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1203. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1204. msdu_info);
  1205. is_exception = 1;
  1206. tx_desc->length -= tx_desc->pkt_offset;
  1207. }
  1208. #if !TQM_BYPASS_WAR
  1209. if (is_exception || tx_exc_metadata)
  1210. #endif
  1211. {
  1212. /* Temporary WAR due to TQM VP issues */
  1213. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1214. qdf_atomic_inc(&soc->num_tx_exception);
  1215. }
  1216. return tx_desc;
  1217. failure:
  1218. dp_tx_desc_release(tx_desc, desc_pool_id);
  1219. return NULL;
  1220. }
  1221. /**
  1222. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1223. * @vdev: DP vdev handle
  1224. * @nbuf: skb
  1225. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1226. * @desc_pool_id : Descriptor Pool ID
  1227. *
  1228. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1229. * information. For frames wth fragments, allocate and prepare
  1230. * an MSDU extension descriptor
  1231. *
  1232. * Return: Pointer to Tx Descriptor on success,
  1233. * NULL on failure
  1234. */
  1235. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1236. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1237. uint8_t desc_pool_id)
  1238. {
  1239. struct dp_tx_desc_s *tx_desc;
  1240. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1241. struct dp_pdev *pdev = vdev->pdev;
  1242. struct dp_soc *soc = pdev->soc;
  1243. if (dp_tx_limit_check(vdev))
  1244. return NULL;
  1245. /* Allocate software Tx descriptor */
  1246. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1247. if (!tx_desc) {
  1248. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1249. return NULL;
  1250. }
  1251. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1252. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1253. dp_tx_outstanding_inc(pdev);
  1254. /* Initialize the SW tx descriptor */
  1255. tx_desc->nbuf = nbuf;
  1256. tx_desc->frm_type = msdu_info->frm_type;
  1257. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1258. tx_desc->vdev_id = vdev->vdev_id;
  1259. tx_desc->pdev = pdev;
  1260. tx_desc->pkt_offset = 0;
  1261. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1262. /* Handle scattered frames - TSO/SG/ME */
  1263. /* Allocate and prepare an extension descriptor for scattered frames */
  1264. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1265. if (!msdu_ext_desc) {
  1266. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1267. goto failure;
  1268. }
  1269. #if TQM_BYPASS_WAR
  1270. /* Temporary WAR due to TQM VP issues */
  1271. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1272. qdf_atomic_inc(&soc->num_tx_exception);
  1273. #endif
  1274. if (qdf_unlikely(msdu_info->exception_fw))
  1275. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1276. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1277. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1278. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1279. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1280. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1281. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1282. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1283. else
  1284. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1285. return tx_desc;
  1286. failure:
  1287. dp_tx_desc_release(tx_desc, desc_pool_id);
  1288. return NULL;
  1289. }
  1290. /**
  1291. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1292. * @vdev: DP vdev handle
  1293. * @nbuf: buffer pointer
  1294. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1295. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1296. * descriptor
  1297. *
  1298. * Return:
  1299. */
  1300. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1301. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1302. {
  1303. qdf_nbuf_t curr_nbuf = NULL;
  1304. uint16_t total_len = 0;
  1305. qdf_dma_addr_t paddr;
  1306. int32_t i;
  1307. int32_t mapped_buf_num = 0;
  1308. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1309. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1310. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1311. /* Continue only if frames are of DATA type */
  1312. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1313. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1314. dp_tx_debug("Pkt. recd is of not data type");
  1315. goto error;
  1316. }
  1317. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1318. if (vdev->raw_mode_war &&
  1319. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1320. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1321. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1322. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1323. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1324. /*
  1325. * Number of nbuf's must not exceed the size of the frags
  1326. * array in seg_info.
  1327. */
  1328. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1329. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1330. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1331. goto error;
  1332. }
  1333. if (QDF_STATUS_SUCCESS !=
  1334. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1335. curr_nbuf,
  1336. QDF_DMA_TO_DEVICE,
  1337. curr_nbuf->len)) {
  1338. dp_tx_err("%s dma map error ", __func__);
  1339. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1340. goto error;
  1341. }
  1342. /* Update the count of mapped nbuf's */
  1343. mapped_buf_num++;
  1344. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1345. seg_info->frags[i].paddr_lo = paddr;
  1346. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1347. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1348. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1349. total_len += qdf_nbuf_len(curr_nbuf);
  1350. }
  1351. seg_info->frag_cnt = i;
  1352. seg_info->total_len = total_len;
  1353. seg_info->next = NULL;
  1354. sg_info->curr_seg = seg_info;
  1355. msdu_info->frm_type = dp_tx_frm_raw;
  1356. msdu_info->num_seg = 1;
  1357. return nbuf;
  1358. error:
  1359. i = 0;
  1360. while (nbuf) {
  1361. curr_nbuf = nbuf;
  1362. if (i < mapped_buf_num) {
  1363. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1364. QDF_DMA_TO_DEVICE,
  1365. curr_nbuf->len);
  1366. i++;
  1367. }
  1368. nbuf = qdf_nbuf_next(nbuf);
  1369. qdf_nbuf_free(curr_nbuf);
  1370. }
  1371. return NULL;
  1372. }
  1373. /**
  1374. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1375. * @soc: DP soc handle
  1376. * @nbuf: Buffer pointer
  1377. *
  1378. * unmap the chain of nbufs that belong to this RAW frame.
  1379. *
  1380. * Return: None
  1381. */
  1382. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1383. qdf_nbuf_t nbuf)
  1384. {
  1385. qdf_nbuf_t cur_nbuf = nbuf;
  1386. do {
  1387. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1388. QDF_DMA_TO_DEVICE,
  1389. cur_nbuf->len);
  1390. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1391. } while (cur_nbuf);
  1392. }
  1393. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1394. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1395. qdf_nbuf_t nbuf)
  1396. {
  1397. qdf_nbuf_t nbuf_local;
  1398. struct dp_vdev *vdev_local = vdev_hdl;
  1399. do {
  1400. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1401. break;
  1402. nbuf_local = nbuf;
  1403. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1404. htt_cmn_pkt_type_raw))
  1405. break;
  1406. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1407. break;
  1408. else if (qdf_nbuf_is_tso((nbuf_local)))
  1409. break;
  1410. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1411. (nbuf_local),
  1412. NULL, 1, 0);
  1413. } while (0);
  1414. }
  1415. #endif
  1416. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1417. /**
  1418. * dp_tx_update_stats() - Update soc level tx stats
  1419. * @soc: DP soc handle
  1420. * @tx_desc: TX descriptor reference
  1421. * @ring_id: TCL ring id
  1422. *
  1423. * Returns: none
  1424. */
  1425. void dp_tx_update_stats(struct dp_soc *soc,
  1426. struct dp_tx_desc_s *tx_desc,
  1427. uint8_t ring_id)
  1428. {
  1429. uint32_t stats_len = 0;
  1430. if (tx_desc->frm_type == dp_tx_frm_tso)
  1431. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1432. else
  1433. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1434. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1435. }
  1436. int
  1437. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1438. struct dp_tx_desc_s *tx_desc,
  1439. uint8_t tid,
  1440. struct dp_tx_msdu_info_s *msdu_info,
  1441. uint8_t ring_id)
  1442. {
  1443. struct dp_swlm *swlm = &soc->swlm;
  1444. union swlm_data swlm_query_data;
  1445. struct dp_swlm_tcl_data tcl_data;
  1446. QDF_STATUS status;
  1447. int ret;
  1448. if (!swlm->is_enabled)
  1449. return msdu_info->skip_hp_update;
  1450. tcl_data.nbuf = tx_desc->nbuf;
  1451. tcl_data.tid = tid;
  1452. tcl_data.ring_id = ring_id;
  1453. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1454. tcl_data.pkt_len =
  1455. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1456. } else {
  1457. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1458. }
  1459. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1460. swlm_query_data.tcl_data = &tcl_data;
  1461. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1462. if (QDF_IS_STATUS_ERROR(status)) {
  1463. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1464. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1465. return 0;
  1466. }
  1467. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1468. if (ret) {
  1469. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1470. } else {
  1471. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1472. }
  1473. return ret;
  1474. }
  1475. void
  1476. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1477. int coalesce)
  1478. {
  1479. if (coalesce)
  1480. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1481. else
  1482. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1483. }
  1484. static inline void
  1485. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1486. {
  1487. if (((i + 1) < msdu_info->num_seg))
  1488. msdu_info->skip_hp_update = 1;
  1489. else
  1490. msdu_info->skip_hp_update = 0;
  1491. }
  1492. static inline void
  1493. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1494. {
  1495. hal_ring_handle_t hal_ring_hdl =
  1496. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1497. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1498. dp_err("Fillmore: SRNG access start failed");
  1499. return;
  1500. }
  1501. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1502. }
  1503. static inline void
  1504. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1505. QDF_STATUS status,
  1506. struct dp_tx_msdu_info_s *msdu_info)
  1507. {
  1508. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1509. dp_flush_tcp_hp(soc,
  1510. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1511. }
  1512. }
  1513. #else
  1514. static inline void
  1515. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1516. {
  1517. }
  1518. static inline void
  1519. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1520. QDF_STATUS status,
  1521. struct dp_tx_msdu_info_s *msdu_info)
  1522. {
  1523. }
  1524. #endif
  1525. #ifdef FEATURE_RUNTIME_PM
  1526. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1527. {
  1528. int ret;
  1529. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1530. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1531. return ret;
  1532. }
  1533. /**
  1534. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1535. * @soc: Datapath soc handle
  1536. * @hal_ring_hdl: HAL ring handle
  1537. * @coalesce: Coalesce the current write or not
  1538. *
  1539. * Wrapper for HAL ring access end for data transmission for
  1540. * FEATURE_RUNTIME_PM
  1541. *
  1542. * Returns: none
  1543. */
  1544. void
  1545. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1546. hal_ring_handle_t hal_ring_hdl,
  1547. int coalesce)
  1548. {
  1549. int ret;
  1550. /*
  1551. * Avoid runtime get and put APIs under high throughput scenarios.
  1552. */
  1553. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1554. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1555. return;
  1556. }
  1557. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1558. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1559. if (hif_system_pm_state_check(soc->hif_handle)) {
  1560. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1561. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1562. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1563. } else {
  1564. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1565. }
  1566. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1567. } else {
  1568. dp_runtime_get(soc);
  1569. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1570. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1571. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1572. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1573. dp_runtime_put(soc);
  1574. }
  1575. }
  1576. #else
  1577. #ifdef DP_POWER_SAVE
  1578. void
  1579. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1580. hal_ring_handle_t hal_ring_hdl,
  1581. int coalesce)
  1582. {
  1583. if (hif_system_pm_state_check(soc->hif_handle)) {
  1584. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1585. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1586. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1587. } else {
  1588. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1589. }
  1590. }
  1591. #endif
  1592. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1593. {
  1594. return 0;
  1595. }
  1596. #endif
  1597. /**
  1598. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1599. * @vdev: DP vdev handle
  1600. * @nbuf: skb
  1601. *
  1602. * Extract the DSCP or PCP information from frame and map into TID value.
  1603. *
  1604. * Return: void
  1605. */
  1606. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1607. struct dp_tx_msdu_info_s *msdu_info)
  1608. {
  1609. uint8_t tos = 0, dscp_tid_override = 0;
  1610. uint8_t *hdr_ptr, *L3datap;
  1611. uint8_t is_mcast = 0;
  1612. qdf_ether_header_t *eh = NULL;
  1613. qdf_ethervlan_header_t *evh = NULL;
  1614. uint16_t ether_type;
  1615. qdf_llc_t *llcHdr;
  1616. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1617. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1618. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1619. eh = (qdf_ether_header_t *)nbuf->data;
  1620. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1621. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1622. } else {
  1623. qdf_dot3_qosframe_t *qos_wh =
  1624. (qdf_dot3_qosframe_t *) nbuf->data;
  1625. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1626. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1627. return;
  1628. }
  1629. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1630. ether_type = eh->ether_type;
  1631. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1632. /*
  1633. * Check if packet is dot3 or eth2 type.
  1634. */
  1635. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1636. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1637. sizeof(*llcHdr));
  1638. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1639. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1640. sizeof(*llcHdr);
  1641. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1642. + sizeof(*llcHdr) +
  1643. sizeof(qdf_net_vlanhdr_t));
  1644. } else {
  1645. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1646. sizeof(*llcHdr);
  1647. }
  1648. } else {
  1649. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1650. evh = (qdf_ethervlan_header_t *) eh;
  1651. ether_type = evh->ether_type;
  1652. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1653. }
  1654. }
  1655. /*
  1656. * Find priority from IP TOS DSCP field
  1657. */
  1658. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1659. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1660. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1661. /* Only for unicast frames */
  1662. if (!is_mcast) {
  1663. /* send it on VO queue */
  1664. msdu_info->tid = DP_VO_TID;
  1665. }
  1666. } else {
  1667. /*
  1668. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1669. * from TOS byte.
  1670. */
  1671. tos = ip->ip_tos;
  1672. dscp_tid_override = 1;
  1673. }
  1674. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1675. /* TODO
  1676. * use flowlabel
  1677. *igmpmld cases to be handled in phase 2
  1678. */
  1679. unsigned long ver_pri_flowlabel;
  1680. unsigned long pri;
  1681. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1682. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1683. DP_IPV6_PRIORITY_SHIFT;
  1684. tos = pri;
  1685. dscp_tid_override = 1;
  1686. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1687. msdu_info->tid = DP_VO_TID;
  1688. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1689. /* Only for unicast frames */
  1690. if (!is_mcast) {
  1691. /* send ucast arp on VO queue */
  1692. msdu_info->tid = DP_VO_TID;
  1693. }
  1694. }
  1695. /*
  1696. * Assign all MCAST packets to BE
  1697. */
  1698. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1699. if (is_mcast) {
  1700. tos = 0;
  1701. dscp_tid_override = 1;
  1702. }
  1703. }
  1704. if (dscp_tid_override == 1) {
  1705. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1706. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1707. }
  1708. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1709. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1710. return;
  1711. }
  1712. /**
  1713. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1714. * @vdev: DP vdev handle
  1715. * @nbuf: skb
  1716. *
  1717. * Software based TID classification is required when more than 2 DSCP-TID
  1718. * mapping tables are needed.
  1719. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1720. *
  1721. * Return: void
  1722. */
  1723. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1724. struct dp_tx_msdu_info_s *msdu_info)
  1725. {
  1726. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1727. /*
  1728. * skip_sw_tid_classification flag will set in below cases-
  1729. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1730. * 2. hlos_tid_override enabled for vdev
  1731. * 3. mesh mode enabled for vdev
  1732. */
  1733. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1734. /* Update tid in msdu_info from skb priority */
  1735. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1736. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1737. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1738. if (tid == DP_TX_INVALID_QOS_TAG)
  1739. return;
  1740. msdu_info->tid = tid;
  1741. return;
  1742. }
  1743. return;
  1744. }
  1745. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1746. }
  1747. #ifdef FEATURE_WLAN_TDLS
  1748. /**
  1749. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1750. * @soc: datapath SOC
  1751. * @vdev: datapath vdev
  1752. * @tx_desc: TX descriptor
  1753. *
  1754. * Return: None
  1755. */
  1756. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1757. struct dp_vdev *vdev,
  1758. struct dp_tx_desc_s *tx_desc)
  1759. {
  1760. if (vdev) {
  1761. if (vdev->is_tdls_frame) {
  1762. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1763. vdev->is_tdls_frame = false;
  1764. }
  1765. }
  1766. }
  1767. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1768. {
  1769. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1770. switch (soc->arch_id) {
  1771. case CDP_ARCH_TYPE_LI:
  1772. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1773. break;
  1774. case CDP_ARCH_TYPE_BE:
  1775. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1776. break;
  1777. default:
  1778. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1779. QDF_BUG(0);
  1780. }
  1781. return tx_status;
  1782. }
  1783. /**
  1784. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1785. * @soc: dp_soc handle
  1786. * @tx_desc: TX descriptor
  1787. * @vdev: datapath vdev handle
  1788. *
  1789. * Return: None
  1790. */
  1791. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1792. struct dp_tx_desc_s *tx_desc)
  1793. {
  1794. uint8_t tx_status = 0;
  1795. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1796. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1797. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1798. DP_MOD_ID_TDLS);
  1799. if (qdf_unlikely(!vdev)) {
  1800. dp_err_rl("vdev is null!");
  1801. goto error;
  1802. }
  1803. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1804. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1805. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1806. if (vdev->tx_non_std_data_callback.func) {
  1807. qdf_nbuf_set_next(nbuf, NULL);
  1808. vdev->tx_non_std_data_callback.func(
  1809. vdev->tx_non_std_data_callback.ctxt,
  1810. nbuf, tx_status);
  1811. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1812. return;
  1813. } else {
  1814. dp_err_rl("callback func is null");
  1815. }
  1816. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1817. error:
  1818. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1819. qdf_nbuf_free(nbuf);
  1820. }
  1821. /**
  1822. * dp_tx_msdu_single_map() - do nbuf map
  1823. * @vdev: DP vdev handle
  1824. * @tx_desc: DP TX descriptor pointer
  1825. * @nbuf: skb pointer
  1826. *
  1827. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1828. * operation done in other component.
  1829. *
  1830. * Return: QDF_STATUS
  1831. */
  1832. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1833. struct dp_tx_desc_s *tx_desc,
  1834. qdf_nbuf_t nbuf)
  1835. {
  1836. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1837. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1838. nbuf,
  1839. QDF_DMA_TO_DEVICE,
  1840. nbuf->len);
  1841. else
  1842. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1843. QDF_DMA_TO_DEVICE);
  1844. }
  1845. #else
  1846. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1847. struct dp_vdev *vdev,
  1848. struct dp_tx_desc_s *tx_desc)
  1849. {
  1850. }
  1851. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1852. struct dp_tx_desc_s *tx_desc)
  1853. {
  1854. }
  1855. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1856. struct dp_tx_desc_s *tx_desc,
  1857. qdf_nbuf_t nbuf)
  1858. {
  1859. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1860. nbuf,
  1861. QDF_DMA_TO_DEVICE,
  1862. nbuf->len);
  1863. }
  1864. #endif
  1865. static inline
  1866. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1867. struct dp_tx_desc_s *tx_desc,
  1868. qdf_nbuf_t nbuf)
  1869. {
  1870. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1871. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1872. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1873. return 0;
  1874. return qdf_nbuf_mapped_paddr_get(nbuf);
  1875. }
  1876. static inline
  1877. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1878. {
  1879. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1880. desc->nbuf,
  1881. desc->dma_addr,
  1882. QDF_DMA_TO_DEVICE,
  1883. desc->length);
  1884. }
  1885. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1886. static inline
  1887. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1888. struct dp_tx_desc_s *tx_desc,
  1889. qdf_nbuf_t nbuf)
  1890. {
  1891. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1892. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1893. (void *)(nbuf->data + nbuf->len));
  1894. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1895. } else {
  1896. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1897. }
  1898. }
  1899. static inline
  1900. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1901. struct dp_tx_desc_s *desc)
  1902. {
  1903. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1904. return dp_tx_nbuf_unmap_regular(soc, desc);
  1905. }
  1906. #else
  1907. static inline
  1908. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1909. struct dp_tx_desc_s *tx_desc,
  1910. qdf_nbuf_t nbuf)
  1911. {
  1912. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1913. }
  1914. static inline
  1915. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1916. struct dp_tx_desc_s *desc)
  1917. {
  1918. return dp_tx_nbuf_unmap_regular(soc, desc);
  1919. }
  1920. #endif
  1921. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1922. static inline
  1923. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1924. {
  1925. dp_tx_nbuf_unmap(soc, desc);
  1926. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1927. }
  1928. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1929. {
  1930. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1931. dp_tx_nbuf_unmap(soc, desc);
  1932. }
  1933. #else
  1934. static inline
  1935. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1936. {
  1937. }
  1938. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1939. {
  1940. dp_tx_nbuf_unmap(soc, desc);
  1941. }
  1942. #endif
  1943. #ifdef MESH_MODE_SUPPORT
  1944. /**
  1945. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1946. * @soc: datapath SOC
  1947. * @vdev: datapath vdev
  1948. * @tx_desc: TX descriptor
  1949. *
  1950. * Return: None
  1951. */
  1952. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1953. struct dp_vdev *vdev,
  1954. struct dp_tx_desc_s *tx_desc)
  1955. {
  1956. if (qdf_unlikely(vdev->mesh_vdev))
  1957. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1958. }
  1959. /**
  1960. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1961. * @soc: dp_soc handle
  1962. * @tx_desc: TX descriptor
  1963. * @vdev: datapath vdev handle
  1964. *
  1965. * Return: None
  1966. */
  1967. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1968. struct dp_tx_desc_s *tx_desc)
  1969. {
  1970. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1971. struct dp_vdev *vdev = NULL;
  1972. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1973. qdf_nbuf_free(nbuf);
  1974. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1975. } else {
  1976. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1977. DP_MOD_ID_MESH);
  1978. if (vdev && vdev->osif_tx_free_ext)
  1979. vdev->osif_tx_free_ext((nbuf));
  1980. else
  1981. qdf_nbuf_free(nbuf);
  1982. if (vdev)
  1983. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1984. }
  1985. }
  1986. #else
  1987. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1988. struct dp_vdev *vdev,
  1989. struct dp_tx_desc_s *tx_desc)
  1990. {
  1991. }
  1992. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1993. struct dp_tx_desc_s *tx_desc)
  1994. {
  1995. }
  1996. #endif
  1997. /**
  1998. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1999. * @vdev: DP vdev handle
  2000. * @nbuf: skb
  2001. *
  2002. * Return: 1 if frame needs to be dropped else 0
  2003. */
  2004. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  2005. {
  2006. struct dp_pdev *pdev = NULL;
  2007. struct dp_ast_entry *src_ast_entry = NULL;
  2008. struct dp_ast_entry *dst_ast_entry = NULL;
  2009. struct dp_soc *soc = NULL;
  2010. qdf_assert(vdev);
  2011. pdev = vdev->pdev;
  2012. qdf_assert(pdev);
  2013. soc = pdev->soc;
  2014. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  2015. (soc, dstmac, vdev->pdev->pdev_id);
  2016. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  2017. (soc, srcmac, vdev->pdev->pdev_id);
  2018. if (dst_ast_entry && src_ast_entry) {
  2019. if (dst_ast_entry->peer_id ==
  2020. src_ast_entry->peer_id)
  2021. return 1;
  2022. }
  2023. return 0;
  2024. }
  2025. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  2026. defined(WLAN_MCAST_MLO)
  2027. /* MLO peer id for reinject*/
  2028. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  2029. /* MLO vdev id inc offset */
  2030. #define DP_MLO_VDEV_ID_OFFSET 0x80
  2031. static inline void
  2032. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2033. {
  2034. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  2035. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2036. qdf_atomic_inc(&soc->num_tx_exception);
  2037. }
  2038. }
  2039. static inline void
  2040. dp_tx_update_mcast_param(uint16_t peer_id,
  2041. uint16_t *htt_tcl_metadata,
  2042. struct dp_vdev *vdev,
  2043. struct dp_tx_msdu_info_s *msdu_info)
  2044. {
  2045. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2046. *htt_tcl_metadata = 0;
  2047. DP_TX_TCL_METADATA_TYPE_SET(
  2048. *htt_tcl_metadata,
  2049. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2050. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2051. msdu_info->gsn);
  2052. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2053. if (qdf_unlikely(vdev->nawds_enabled))
  2054. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2055. *htt_tcl_metadata, 1);
  2056. } else {
  2057. msdu_info->vdev_id = vdev->vdev_id;
  2058. }
  2059. }
  2060. #else
  2061. static inline void
  2062. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2063. {
  2064. }
  2065. static inline void
  2066. dp_tx_update_mcast_param(uint16_t peer_id,
  2067. uint16_t *htt_tcl_metadata,
  2068. struct dp_vdev *vdev,
  2069. struct dp_tx_msdu_info_s *msdu_info)
  2070. {
  2071. }
  2072. #endif
  2073. /**
  2074. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2075. * @vdev: DP vdev handle
  2076. * @nbuf: skb
  2077. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2078. * @meta_data: Metadata to the fw
  2079. * @tx_q: Tx queue to be used for this Tx frame
  2080. * @peer_id: peer_id of the peer in case of NAWDS frames
  2081. * @tx_exc_metadata: Handle that holds exception path metadata
  2082. *
  2083. * Return: NULL on success,
  2084. * nbuf when it fails to send
  2085. */
  2086. qdf_nbuf_t
  2087. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2088. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2089. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2090. {
  2091. struct dp_pdev *pdev = vdev->pdev;
  2092. struct dp_soc *soc = pdev->soc;
  2093. struct dp_tx_desc_s *tx_desc;
  2094. QDF_STATUS status;
  2095. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2096. uint16_t htt_tcl_metadata = 0;
  2097. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2098. uint8_t tid = msdu_info->tid;
  2099. struct cdp_tid_tx_stats *tid_stats = NULL;
  2100. qdf_dma_addr_t paddr;
  2101. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2102. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2103. msdu_info, tx_exc_metadata);
  2104. if (!tx_desc) {
  2105. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  2106. vdev, tx_q->desc_pool_id);
  2107. drop_code = TX_DESC_ERR;
  2108. goto fail_return;
  2109. }
  2110. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2111. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2112. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2113. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2114. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2115. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2116. DP_TCL_METADATA_TYPE_PEER_BASED);
  2117. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2118. peer_id);
  2119. dp_tx_bypass_reinjection(soc, tx_desc);
  2120. } else
  2121. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2122. if (msdu_info->exception_fw)
  2123. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2124. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2125. !pdev->enhanced_stats_en);
  2126. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2127. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2128. if (!paddr) {
  2129. /* Handle failure */
  2130. dp_err("qdf_nbuf_map failed");
  2131. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2132. drop_code = TX_DMA_MAP_ERR;
  2133. goto release_desc;
  2134. }
  2135. tx_desc->dma_addr = paddr;
  2136. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2137. tx_desc->id, DP_TX_DESC_MAP);
  2138. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2139. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2140. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2141. htt_tcl_metadata,
  2142. tx_exc_metadata, msdu_info);
  2143. if (status != QDF_STATUS_SUCCESS) {
  2144. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2145. tx_desc, tx_q->ring_id);
  2146. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2147. tx_desc->id, DP_TX_DESC_UNMAP);
  2148. dp_tx_nbuf_unmap(soc, tx_desc);
  2149. drop_code = TX_HW_ENQUEUE;
  2150. goto release_desc;
  2151. }
  2152. return NULL;
  2153. release_desc:
  2154. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2155. fail_return:
  2156. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2157. tid_stats = &pdev->stats.tid_stats.
  2158. tid_tx_stats[tx_q->ring_id][tid];
  2159. tid_stats->swdrop_cnt[drop_code]++;
  2160. return nbuf;
  2161. }
  2162. /**
  2163. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2164. * @soc: Soc handle
  2165. * @desc: software Tx descriptor to be processed
  2166. *
  2167. * Return: none
  2168. */
  2169. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2170. {
  2171. qdf_nbuf_t nbuf = desc->nbuf;
  2172. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2173. /* nbuf already freed in vdev detach path */
  2174. if (!nbuf)
  2175. return;
  2176. /* If it is TDLS mgmt, don't unmap or free the frame */
  2177. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2178. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2179. /* 0 : MSDU buffer, 1 : MLE */
  2180. if (desc->msdu_ext_desc) {
  2181. /* TSO free */
  2182. if (hal_tx_ext_desc_get_tso_enable(
  2183. desc->msdu_ext_desc->vaddr)) {
  2184. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2185. desc->id, DP_TX_COMP_MSDU_EXT);
  2186. dp_tx_tso_seg_history_add(soc,
  2187. desc->msdu_ext_desc->tso_desc,
  2188. desc->nbuf, desc->id, type);
  2189. /* unmap eash TSO seg before free the nbuf */
  2190. dp_tx_tso_unmap_segment(soc,
  2191. desc->msdu_ext_desc->tso_desc,
  2192. desc->msdu_ext_desc->
  2193. tso_num_desc);
  2194. qdf_nbuf_free(nbuf);
  2195. return;
  2196. }
  2197. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2198. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2199. qdf_dma_addr_t iova;
  2200. uint32_t frag_len;
  2201. uint32_t i;
  2202. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2203. QDF_DMA_TO_DEVICE,
  2204. qdf_nbuf_headlen(nbuf));
  2205. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2206. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2207. &iova,
  2208. &frag_len);
  2209. if (!iova || !frag_len)
  2210. break;
  2211. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2212. QDF_DMA_TO_DEVICE);
  2213. }
  2214. qdf_nbuf_free(nbuf);
  2215. return;
  2216. }
  2217. }
  2218. /* If it's ME frame, dont unmap the cloned nbuf's */
  2219. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2220. goto nbuf_free;
  2221. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2222. dp_tx_unmap(soc, desc);
  2223. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2224. return dp_mesh_tx_comp_free_buff(soc, desc);
  2225. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2226. return;
  2227. nbuf_free:
  2228. qdf_nbuf_free(nbuf);
  2229. }
  2230. /**
  2231. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2232. * @soc: DP soc handle
  2233. * @nbuf: skb
  2234. * @msdu_info: MSDU info
  2235. *
  2236. * Return: None
  2237. */
  2238. static inline void
  2239. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2240. struct dp_tx_msdu_info_s *msdu_info)
  2241. {
  2242. uint32_t cur_idx;
  2243. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2244. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2245. qdf_nbuf_headlen(nbuf));
  2246. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2247. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2248. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2249. seg->frags[cur_idx].paddr_hi) << 32),
  2250. seg->frags[cur_idx].len,
  2251. QDF_DMA_TO_DEVICE);
  2252. }
  2253. /**
  2254. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2255. * @vdev: DP vdev handle
  2256. * @nbuf: skb
  2257. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2258. *
  2259. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2260. *
  2261. * Return: NULL on success,
  2262. * nbuf when it fails to send
  2263. */
  2264. #if QDF_LOCK_STATS
  2265. noinline
  2266. #else
  2267. #endif
  2268. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2269. struct dp_tx_msdu_info_s *msdu_info)
  2270. {
  2271. uint32_t i;
  2272. struct dp_pdev *pdev = vdev->pdev;
  2273. struct dp_soc *soc = pdev->soc;
  2274. struct dp_tx_desc_s *tx_desc;
  2275. bool is_cce_classified = false;
  2276. QDF_STATUS status;
  2277. uint16_t htt_tcl_metadata = 0;
  2278. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2279. struct cdp_tid_tx_stats *tid_stats = NULL;
  2280. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2281. if (msdu_info->frm_type == dp_tx_frm_me)
  2282. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2283. i = 0;
  2284. /* Print statement to track i and num_seg */
  2285. /*
  2286. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2287. * descriptors using information in msdu_info
  2288. */
  2289. while (i < msdu_info->num_seg) {
  2290. /*
  2291. * Setup Tx descriptor for an MSDU, and MSDU extension
  2292. * descriptor
  2293. */
  2294. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2295. tx_q->desc_pool_id);
  2296. if (!tx_desc) {
  2297. if (msdu_info->frm_type == dp_tx_frm_me) {
  2298. prep_desc_fail++;
  2299. dp_tx_me_free_buf(pdev,
  2300. (void *)(msdu_info->u.sg_info
  2301. .curr_seg->frags[0].vaddr));
  2302. if (prep_desc_fail == msdu_info->num_seg) {
  2303. /*
  2304. * Unmap is needed only if descriptor
  2305. * preparation failed for all segments.
  2306. */
  2307. qdf_nbuf_unmap(soc->osdev,
  2308. msdu_info->u.sg_info.
  2309. curr_seg->nbuf,
  2310. QDF_DMA_TO_DEVICE);
  2311. }
  2312. /*
  2313. * Free the nbuf for the current segment
  2314. * and make it point to the next in the list.
  2315. * For me, there are as many segments as there
  2316. * are no of clients.
  2317. */
  2318. qdf_nbuf_free(msdu_info->u.sg_info
  2319. .curr_seg->nbuf);
  2320. if (msdu_info->u.sg_info.curr_seg->next) {
  2321. msdu_info->u.sg_info.curr_seg =
  2322. msdu_info->u.sg_info
  2323. .curr_seg->next;
  2324. nbuf = msdu_info->u.sg_info
  2325. .curr_seg->nbuf;
  2326. }
  2327. i++;
  2328. continue;
  2329. }
  2330. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2331. dp_tx_tso_seg_history_add(
  2332. soc,
  2333. msdu_info->u.tso_info.curr_seg,
  2334. nbuf, 0, DP_TX_DESC_UNMAP);
  2335. dp_tx_tso_unmap_segment(soc,
  2336. msdu_info->u.tso_info.
  2337. curr_seg,
  2338. msdu_info->u.tso_info.
  2339. tso_num_seg_list);
  2340. if (msdu_info->u.tso_info.curr_seg->next) {
  2341. msdu_info->u.tso_info.curr_seg =
  2342. msdu_info->u.tso_info.curr_seg->next;
  2343. i++;
  2344. continue;
  2345. }
  2346. }
  2347. if (msdu_info->frm_type == dp_tx_frm_sg)
  2348. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2349. goto done;
  2350. }
  2351. if (msdu_info->frm_type == dp_tx_frm_me) {
  2352. tx_desc->msdu_ext_desc->me_buffer =
  2353. (struct dp_tx_me_buf_t *)msdu_info->
  2354. u.sg_info.curr_seg->frags[0].vaddr;
  2355. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2356. }
  2357. if (is_cce_classified)
  2358. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2359. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2360. if (msdu_info->exception_fw) {
  2361. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2362. }
  2363. dp_tx_is_hp_update_required(i, msdu_info);
  2364. /*
  2365. * For frames with multiple segments (TSO, ME), jump to next
  2366. * segment.
  2367. */
  2368. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2369. if (msdu_info->u.tso_info.curr_seg->next) {
  2370. msdu_info->u.tso_info.curr_seg =
  2371. msdu_info->u.tso_info.curr_seg->next;
  2372. /*
  2373. * If this is a jumbo nbuf, then increment the
  2374. * number of nbuf users for each additional
  2375. * segment of the msdu. This will ensure that
  2376. * the skb is freed only after receiving tx
  2377. * completion for all segments of an nbuf
  2378. */
  2379. qdf_nbuf_inc_users(nbuf);
  2380. /* Check with MCL if this is needed */
  2381. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2382. */
  2383. }
  2384. }
  2385. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2386. &htt_tcl_metadata,
  2387. vdev,
  2388. msdu_info);
  2389. /*
  2390. * Enqueue the Tx MSDU descriptor to HW for transmit
  2391. */
  2392. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2393. htt_tcl_metadata,
  2394. NULL, msdu_info);
  2395. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2396. if (status != QDF_STATUS_SUCCESS) {
  2397. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2398. tx_desc, tx_q->ring_id);
  2399. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2400. tid_stats = &pdev->stats.tid_stats.
  2401. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2402. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2403. if (msdu_info->frm_type == dp_tx_frm_me) {
  2404. hw_enq_fail++;
  2405. if (hw_enq_fail == msdu_info->num_seg) {
  2406. /*
  2407. * Unmap is needed only if enqueue
  2408. * failed for all segments.
  2409. */
  2410. qdf_nbuf_unmap(soc->osdev,
  2411. msdu_info->u.sg_info.
  2412. curr_seg->nbuf,
  2413. QDF_DMA_TO_DEVICE);
  2414. }
  2415. /*
  2416. * Free the nbuf for the current segment
  2417. * and make it point to the next in the list.
  2418. * For me, there are as many segments as there
  2419. * are no of clients.
  2420. */
  2421. qdf_nbuf_free(msdu_info->u.sg_info
  2422. .curr_seg->nbuf);
  2423. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2424. if (msdu_info->u.sg_info.curr_seg->next) {
  2425. msdu_info->u.sg_info.curr_seg =
  2426. msdu_info->u.sg_info
  2427. .curr_seg->next;
  2428. nbuf = msdu_info->u.sg_info
  2429. .curr_seg->nbuf;
  2430. } else
  2431. break;
  2432. i++;
  2433. continue;
  2434. }
  2435. /*
  2436. * For TSO frames, the nbuf users increment done for
  2437. * the current segment has to be reverted, since the
  2438. * hw enqueue for this segment failed
  2439. */
  2440. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2441. msdu_info->u.tso_info.curr_seg) {
  2442. /*
  2443. * unmap and free current,
  2444. * retransmit remaining segments
  2445. */
  2446. dp_tx_comp_free_buf(soc, tx_desc);
  2447. i++;
  2448. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2449. continue;
  2450. }
  2451. if (msdu_info->frm_type == dp_tx_frm_sg)
  2452. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2453. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2454. goto done;
  2455. }
  2456. /*
  2457. * TODO
  2458. * if tso_info structure can be modified to have curr_seg
  2459. * as first element, following 2 blocks of code (for TSO and SG)
  2460. * can be combined into 1
  2461. */
  2462. /*
  2463. * For Multicast-Unicast converted packets,
  2464. * each converted frame (for a client) is represented as
  2465. * 1 segment
  2466. */
  2467. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2468. (msdu_info->frm_type == dp_tx_frm_me)) {
  2469. if (msdu_info->u.sg_info.curr_seg->next) {
  2470. msdu_info->u.sg_info.curr_seg =
  2471. msdu_info->u.sg_info.curr_seg->next;
  2472. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2473. } else
  2474. break;
  2475. }
  2476. i++;
  2477. }
  2478. nbuf = NULL;
  2479. done:
  2480. return nbuf;
  2481. }
  2482. /**
  2483. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2484. * for SG frames
  2485. * @vdev: DP vdev handle
  2486. * @nbuf: skb
  2487. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2488. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2489. *
  2490. * Return: NULL on success,
  2491. * nbuf when it fails to send
  2492. */
  2493. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2494. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2495. {
  2496. uint32_t cur_frag, nr_frags, i;
  2497. qdf_dma_addr_t paddr;
  2498. struct dp_tx_sg_info_s *sg_info;
  2499. sg_info = &msdu_info->u.sg_info;
  2500. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2501. if (QDF_STATUS_SUCCESS !=
  2502. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2503. QDF_DMA_TO_DEVICE,
  2504. qdf_nbuf_headlen(nbuf))) {
  2505. dp_tx_err("dma map error");
  2506. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2507. qdf_nbuf_free(nbuf);
  2508. return NULL;
  2509. }
  2510. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2511. seg_info->frags[0].paddr_lo = paddr;
  2512. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2513. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2514. seg_info->frags[0].vaddr = (void *) nbuf;
  2515. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2516. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2517. nbuf, 0,
  2518. QDF_DMA_TO_DEVICE,
  2519. cur_frag)) {
  2520. dp_tx_err("frag dma map error");
  2521. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2522. goto map_err;
  2523. }
  2524. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2525. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2526. seg_info->frags[cur_frag + 1].paddr_hi =
  2527. ((uint64_t) paddr) >> 32;
  2528. seg_info->frags[cur_frag + 1].len =
  2529. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2530. }
  2531. seg_info->frag_cnt = (cur_frag + 1);
  2532. seg_info->total_len = qdf_nbuf_len(nbuf);
  2533. seg_info->next = NULL;
  2534. sg_info->curr_seg = seg_info;
  2535. msdu_info->frm_type = dp_tx_frm_sg;
  2536. msdu_info->num_seg = 1;
  2537. return nbuf;
  2538. map_err:
  2539. /* restore paddr into nbuf before calling unmap */
  2540. qdf_nbuf_mapped_paddr_set(nbuf,
  2541. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2542. ((uint64_t)
  2543. seg_info->frags[0].paddr_hi) << 32));
  2544. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2545. QDF_DMA_TO_DEVICE,
  2546. seg_info->frags[0].len);
  2547. for (i = 1; i <= cur_frag; i++) {
  2548. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2549. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2550. seg_info->frags[i].paddr_hi) << 32),
  2551. seg_info->frags[i].len,
  2552. QDF_DMA_TO_DEVICE);
  2553. }
  2554. qdf_nbuf_free(nbuf);
  2555. return NULL;
  2556. }
  2557. /**
  2558. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2559. * @vdev: DP vdev handle
  2560. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2561. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2562. *
  2563. * Return: NULL on failure,
  2564. * nbuf when extracted successfully
  2565. */
  2566. static
  2567. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2568. struct dp_tx_msdu_info_s *msdu_info,
  2569. uint16_t ppdu_cookie)
  2570. {
  2571. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2572. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2573. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2574. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2575. (msdu_info->meta_data[5], 1);
  2576. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2577. (msdu_info->meta_data[5], 1);
  2578. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2579. (msdu_info->meta_data[6], ppdu_cookie);
  2580. msdu_info->exception_fw = 1;
  2581. msdu_info->is_tx_sniffer = 1;
  2582. }
  2583. #ifdef MESH_MODE_SUPPORT
  2584. /**
  2585. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2586. and prepare msdu_info for mesh frames.
  2587. * @vdev: DP vdev handle
  2588. * @nbuf: skb
  2589. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2590. *
  2591. * Return: NULL on failure,
  2592. * nbuf when extracted successfully
  2593. */
  2594. static
  2595. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2596. struct dp_tx_msdu_info_s *msdu_info)
  2597. {
  2598. struct meta_hdr_s *mhdr;
  2599. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2600. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2601. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2602. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2603. msdu_info->exception_fw = 0;
  2604. goto remove_meta_hdr;
  2605. }
  2606. msdu_info->exception_fw = 1;
  2607. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2608. meta_data->host_tx_desc_pool = 1;
  2609. meta_data->update_peer_cache = 1;
  2610. meta_data->learning_frame = 1;
  2611. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2612. meta_data->power = mhdr->power;
  2613. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2614. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2615. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2616. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2617. meta_data->dyn_bw = 1;
  2618. meta_data->valid_pwr = 1;
  2619. meta_data->valid_mcs_mask = 1;
  2620. meta_data->valid_nss_mask = 1;
  2621. meta_data->valid_preamble_type = 1;
  2622. meta_data->valid_retries = 1;
  2623. meta_data->valid_bw_info = 1;
  2624. }
  2625. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2626. meta_data->encrypt_type = 0;
  2627. meta_data->valid_encrypt_type = 1;
  2628. meta_data->learning_frame = 0;
  2629. }
  2630. meta_data->valid_key_flags = 1;
  2631. meta_data->key_flags = (mhdr->keyix & 0x3);
  2632. remove_meta_hdr:
  2633. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2634. dp_tx_err("qdf_nbuf_pull_head failed");
  2635. qdf_nbuf_free(nbuf);
  2636. return NULL;
  2637. }
  2638. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2639. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2640. " tid %d to_fw %d",
  2641. msdu_info->meta_data[0],
  2642. msdu_info->meta_data[1],
  2643. msdu_info->meta_data[2],
  2644. msdu_info->meta_data[3],
  2645. msdu_info->meta_data[4],
  2646. msdu_info->meta_data[5],
  2647. msdu_info->tid, msdu_info->exception_fw);
  2648. return nbuf;
  2649. }
  2650. #else
  2651. static
  2652. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2653. struct dp_tx_msdu_info_s *msdu_info)
  2654. {
  2655. return nbuf;
  2656. }
  2657. #endif
  2658. /**
  2659. * dp_check_exc_metadata() - Checks if parameters are valid
  2660. * @tx_exc - holds all exception path parameters
  2661. *
  2662. * Returns true when all the parameters are valid else false
  2663. *
  2664. */
  2665. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2666. {
  2667. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2668. HTT_INVALID_TID);
  2669. bool invalid_encap_type =
  2670. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2671. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2672. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2673. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2674. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2675. tx_exc->ppdu_cookie == 0);
  2676. if (tx_exc->is_intrabss_fwd)
  2677. return true;
  2678. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2679. invalid_cookie) {
  2680. return false;
  2681. }
  2682. return true;
  2683. }
  2684. #ifdef ATH_SUPPORT_IQUE
  2685. /**
  2686. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2687. * @vdev: vdev handle
  2688. * @nbuf: skb
  2689. *
  2690. * Return: true on success,
  2691. * false on failure
  2692. */
  2693. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2694. {
  2695. qdf_ether_header_t *eh;
  2696. /* Mcast to Ucast Conversion*/
  2697. if (qdf_likely(!vdev->mcast_enhancement_en))
  2698. return true;
  2699. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2700. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2701. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2702. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2703. qdf_nbuf_set_next(nbuf, NULL);
  2704. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2705. qdf_nbuf_len(nbuf));
  2706. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2707. QDF_STATUS_SUCCESS) {
  2708. return false;
  2709. }
  2710. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2711. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2712. QDF_STATUS_SUCCESS) {
  2713. return false;
  2714. }
  2715. }
  2716. }
  2717. return true;
  2718. }
  2719. #else
  2720. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2721. {
  2722. return true;
  2723. }
  2724. #endif
  2725. /**
  2726. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2727. * @nbuf: qdf_nbuf_t
  2728. * @vdev: struct dp_vdev *
  2729. *
  2730. * Allow packet for processing only if it is for peer client which is
  2731. * connected with same vap. Drop packet if client is connected to
  2732. * different vap.
  2733. *
  2734. * Return: QDF_STATUS
  2735. */
  2736. static inline QDF_STATUS
  2737. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2738. {
  2739. struct dp_ast_entry *dst_ast_entry = NULL;
  2740. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2741. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2742. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2743. return QDF_STATUS_SUCCESS;
  2744. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2745. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2746. eh->ether_dhost,
  2747. vdev->vdev_id);
  2748. /* If there is no ast entry, return failure */
  2749. if (qdf_unlikely(!dst_ast_entry)) {
  2750. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2751. return QDF_STATUS_E_FAILURE;
  2752. }
  2753. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2754. return QDF_STATUS_SUCCESS;
  2755. }
  2756. /**
  2757. * dp_tx_nawds_handler() - NAWDS handler
  2758. *
  2759. * @soc: DP soc handle
  2760. * @vdev_id: id of DP vdev handle
  2761. * @msdu_info: msdu_info required to create HTT metadata
  2762. * @nbuf: skb
  2763. *
  2764. * This API transfers the multicast frames with the peer id
  2765. * on NAWDS enabled peer.
  2766. * Return: none
  2767. */
  2768. static inline
  2769. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2770. struct dp_tx_msdu_info_s *msdu_info,
  2771. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2772. {
  2773. struct dp_peer *peer = NULL;
  2774. qdf_nbuf_t nbuf_clone = NULL;
  2775. uint16_t peer_id = DP_INVALID_PEER;
  2776. struct dp_txrx_peer *txrx_peer;
  2777. /* This check avoids pkt forwarding which is entered
  2778. * in the ast table but still doesn't have valid peerid.
  2779. */
  2780. if (sa_peer_id == HTT_INVALID_PEER)
  2781. return;
  2782. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2783. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2784. txrx_peer = dp_get_txrx_peer(peer);
  2785. if (!txrx_peer)
  2786. continue;
  2787. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2788. peer_id = peer->peer_id;
  2789. if (!dp_peer_is_primary_link_peer(peer))
  2790. continue;
  2791. /* Multicast packets needs to be
  2792. * dropped in case of intra bss forwarding
  2793. */
  2794. if (sa_peer_id == txrx_peer->peer_id) {
  2795. dp_tx_debug("multicast packet");
  2796. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2797. tx.nawds_mcast_drop,
  2798. 1);
  2799. continue;
  2800. }
  2801. nbuf_clone = qdf_nbuf_clone(nbuf);
  2802. if (!nbuf_clone) {
  2803. QDF_TRACE(QDF_MODULE_ID_DP,
  2804. QDF_TRACE_LEVEL_ERROR,
  2805. FL("nbuf clone failed"));
  2806. break;
  2807. }
  2808. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2809. msdu_info, peer_id,
  2810. NULL);
  2811. if (nbuf_clone) {
  2812. dp_tx_debug("pkt send failed");
  2813. qdf_nbuf_free(nbuf_clone);
  2814. } else {
  2815. if (peer_id != DP_INVALID_PEER)
  2816. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2817. tx.nawds_mcast,
  2818. 1, qdf_nbuf_len(nbuf));
  2819. }
  2820. }
  2821. }
  2822. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2823. }
  2824. /**
  2825. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2826. * @soc: DP soc handle
  2827. * @vdev_id: id of DP vdev handle
  2828. * @nbuf: skb
  2829. * @tx_exc_metadata: Handle that holds exception path meta data
  2830. *
  2831. * Entry point for Core Tx layer (DP_TX) invoked from
  2832. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2833. *
  2834. * Return: NULL on success,
  2835. * nbuf when it fails to send
  2836. */
  2837. qdf_nbuf_t
  2838. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2839. qdf_nbuf_t nbuf,
  2840. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2841. {
  2842. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2843. qdf_ether_header_t *eh = NULL;
  2844. struct dp_tx_msdu_info_s msdu_info;
  2845. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2846. DP_MOD_ID_TX_EXCEPTION);
  2847. if (qdf_unlikely(!vdev))
  2848. goto fail;
  2849. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2850. if (!tx_exc_metadata)
  2851. goto fail;
  2852. msdu_info.tid = tx_exc_metadata->tid;
  2853. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2854. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2855. QDF_MAC_ADDR_REF(nbuf->data));
  2856. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2857. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2858. dp_tx_err("Invalid parameters in exception path");
  2859. goto fail;
  2860. }
  2861. /* Basic sanity checks for unsupported packets */
  2862. /* MESH mode */
  2863. if (qdf_unlikely(vdev->mesh_vdev)) {
  2864. dp_tx_err("Mesh mode is not supported in exception path");
  2865. goto fail;
  2866. }
  2867. /*
  2868. * Classify the frame and call corresponding
  2869. * "prepare" function which extracts the segment (TSO)
  2870. * and fragmentation information (for TSO , SG, ME, or Raw)
  2871. * into MSDU_INFO structure which is later used to fill
  2872. * SW and HW descriptors.
  2873. */
  2874. if (qdf_nbuf_is_tso(nbuf)) {
  2875. dp_verbose_debug("TSO frame %pK", vdev);
  2876. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2877. qdf_nbuf_len(nbuf));
  2878. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2879. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2880. qdf_nbuf_len(nbuf));
  2881. goto fail;
  2882. }
  2883. goto send_multiple;
  2884. }
  2885. /* SG */
  2886. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2887. struct dp_tx_seg_info_s seg_info = {0};
  2888. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2889. if (!nbuf)
  2890. goto fail;
  2891. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2892. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2893. qdf_nbuf_len(nbuf));
  2894. goto send_multiple;
  2895. }
  2896. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2897. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2898. qdf_nbuf_len(nbuf));
  2899. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2900. tx_exc_metadata->ppdu_cookie);
  2901. }
  2902. /*
  2903. * Get HW Queue to use for this frame.
  2904. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2905. * dedicated for data and 1 for command.
  2906. * "queue_id" maps to one hardware ring.
  2907. * With each ring, we also associate a unique Tx descriptor pool
  2908. * to minimize lock contention for these resources.
  2909. */
  2910. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2911. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2912. if (qdf_unlikely(vdev->nawds_enabled)) {
  2913. /*
  2914. * This is a multicast packet
  2915. */
  2916. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2917. tx_exc_metadata->peer_id);
  2918. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2919. 1, qdf_nbuf_len(nbuf));
  2920. }
  2921. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2922. DP_INVALID_PEER, NULL);
  2923. } else {
  2924. /*
  2925. * Check exception descriptors
  2926. */
  2927. if (dp_tx_exception_limit_check(vdev))
  2928. goto fail;
  2929. /* Single linear frame */
  2930. /*
  2931. * If nbuf is a simple linear frame, use send_single function to
  2932. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2933. * SRNG. There is no need to setup a MSDU extension descriptor.
  2934. */
  2935. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2936. tx_exc_metadata->peer_id,
  2937. tx_exc_metadata);
  2938. }
  2939. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2940. return nbuf;
  2941. send_multiple:
  2942. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2943. fail:
  2944. if (vdev)
  2945. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2946. dp_verbose_debug("pkt send failed");
  2947. return nbuf;
  2948. }
  2949. /**
  2950. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2951. * in exception path in special case to avoid regular exception path chk.
  2952. * @soc: DP soc handle
  2953. * @vdev_id: id of DP vdev handle
  2954. * @nbuf: skb
  2955. * @tx_exc_metadata: Handle that holds exception path meta data
  2956. *
  2957. * Entry point for Core Tx layer (DP_TX) invoked from
  2958. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2959. *
  2960. * Return: NULL on success,
  2961. * nbuf when it fails to send
  2962. */
  2963. qdf_nbuf_t
  2964. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2965. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2966. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2967. {
  2968. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2969. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2970. DP_MOD_ID_TX_EXCEPTION);
  2971. if (qdf_unlikely(!vdev))
  2972. goto fail;
  2973. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2974. == QDF_STATUS_E_FAILURE)) {
  2975. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2976. goto fail;
  2977. }
  2978. /* Unref count as it will agin be taken inside dp_tx_exception */
  2979. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2980. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2981. fail:
  2982. if (vdev)
  2983. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2984. dp_verbose_debug("pkt send failed");
  2985. return nbuf;
  2986. }
  2987. /**
  2988. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2989. * @soc: DP soc handle
  2990. * @vdev_id: DP vdev handle
  2991. * @nbuf: skb
  2992. *
  2993. * Entry point for Core Tx layer (DP_TX) invoked from
  2994. * hard_start_xmit in OSIF/HDD
  2995. *
  2996. * Return: NULL on success,
  2997. * nbuf when it fails to send
  2998. */
  2999. #ifdef MESH_MODE_SUPPORT
  3000. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3001. qdf_nbuf_t nbuf)
  3002. {
  3003. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3004. struct meta_hdr_s *mhdr;
  3005. qdf_nbuf_t nbuf_mesh = NULL;
  3006. qdf_nbuf_t nbuf_clone = NULL;
  3007. struct dp_vdev *vdev;
  3008. uint8_t no_enc_frame = 0;
  3009. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3010. if (!nbuf_mesh) {
  3011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3012. "qdf_nbuf_unshare failed");
  3013. return nbuf;
  3014. }
  3015. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3016. if (!vdev) {
  3017. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3018. "vdev is NULL for vdev_id %d", vdev_id);
  3019. return nbuf;
  3020. }
  3021. nbuf = nbuf_mesh;
  3022. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3023. if ((vdev->sec_type != cdp_sec_type_none) &&
  3024. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3025. no_enc_frame = 1;
  3026. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3027. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3028. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3029. !no_enc_frame) {
  3030. nbuf_clone = qdf_nbuf_clone(nbuf);
  3031. if (!nbuf_clone) {
  3032. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3033. "qdf_nbuf_clone failed");
  3034. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3035. return nbuf;
  3036. }
  3037. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3038. }
  3039. if (nbuf_clone) {
  3040. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3041. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3042. } else {
  3043. qdf_nbuf_free(nbuf_clone);
  3044. }
  3045. }
  3046. if (no_enc_frame)
  3047. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3048. else
  3049. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3050. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3051. if ((!nbuf) && no_enc_frame) {
  3052. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3053. }
  3054. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3055. return nbuf;
  3056. }
  3057. #else
  3058. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3059. qdf_nbuf_t nbuf)
  3060. {
  3061. return dp_tx_send(soc, vdev_id, nbuf);
  3062. }
  3063. #endif
  3064. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3065. static inline
  3066. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3067. {
  3068. if (nbuf) {
  3069. qdf_prefetch(&nbuf->len);
  3070. qdf_prefetch(&nbuf->data);
  3071. }
  3072. }
  3073. #else
  3074. static inline
  3075. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3076. {
  3077. }
  3078. #endif
  3079. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3080. /*
  3081. * dp_tx_drop() - Drop the frame on a given VAP
  3082. * @soc: DP soc handle
  3083. * @vdev_id: id of DP vdev handle
  3084. * @nbuf: skb
  3085. *
  3086. * Drop all the incoming packets
  3087. *
  3088. * Return: nbuf
  3089. *
  3090. */
  3091. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3092. qdf_nbuf_t nbuf)
  3093. {
  3094. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3095. struct dp_vdev *vdev = NULL;
  3096. vdev = soc->vdev_id_map[vdev_id];
  3097. if (qdf_unlikely(!vdev))
  3098. return nbuf;
  3099. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3100. return nbuf;
  3101. }
  3102. /*
  3103. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3104. * @soc: DP soc handle
  3105. * @vdev_id: id of DP vdev handle
  3106. * @nbuf: skb
  3107. * @tx_exc_metadata: Handle that holds exception path meta data
  3108. *
  3109. * Drop all the incoming packets
  3110. *
  3111. * Return: nbuf
  3112. *
  3113. */
  3114. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3115. qdf_nbuf_t nbuf,
  3116. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3117. {
  3118. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3119. }
  3120. #endif
  3121. /*
  3122. * dp_tx_send() - Transmit a frame on a given VAP
  3123. * @soc: DP soc handle
  3124. * @vdev_id: id of DP vdev handle
  3125. * @nbuf: skb
  3126. *
  3127. * Entry point for Core Tx layer (DP_TX) invoked from
  3128. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3129. * cases
  3130. *
  3131. * Return: NULL on success,
  3132. * nbuf when it fails to send
  3133. */
  3134. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3135. qdf_nbuf_t nbuf)
  3136. {
  3137. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3138. uint16_t peer_id = HTT_INVALID_PEER;
  3139. /*
  3140. * doing a memzero is causing additional function call overhead
  3141. * so doing static stack clearing
  3142. */
  3143. struct dp_tx_msdu_info_s msdu_info = {0};
  3144. struct dp_vdev *vdev = NULL;
  3145. qdf_nbuf_t end_nbuf = NULL;
  3146. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3147. return nbuf;
  3148. /*
  3149. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3150. * this in per packet path.
  3151. *
  3152. * As in this path vdev memory is already protected with netdev
  3153. * tx lock
  3154. */
  3155. vdev = soc->vdev_id_map[vdev_id];
  3156. if (qdf_unlikely(!vdev))
  3157. return nbuf;
  3158. /*
  3159. * Set Default Host TID value to invalid TID
  3160. * (TID override disabled)
  3161. */
  3162. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3163. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3164. if (qdf_unlikely(vdev->mesh_vdev)) {
  3165. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3166. &msdu_info);
  3167. if (!nbuf_mesh) {
  3168. dp_verbose_debug("Extracting mesh metadata failed");
  3169. return nbuf;
  3170. }
  3171. nbuf = nbuf_mesh;
  3172. }
  3173. /*
  3174. * Get HW Queue to use for this frame.
  3175. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3176. * dedicated for data and 1 for command.
  3177. * "queue_id" maps to one hardware ring.
  3178. * With each ring, we also associate a unique Tx descriptor pool
  3179. * to minimize lock contention for these resources.
  3180. */
  3181. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3182. /*
  3183. * TCL H/W supports 2 DSCP-TID mapping tables.
  3184. * Table 1 - Default DSCP-TID mapping table
  3185. * Table 2 - 1 DSCP-TID override table
  3186. *
  3187. * If we need a different DSCP-TID mapping for this vap,
  3188. * call tid_classify to extract DSCP/ToS from frame and
  3189. * map to a TID and store in msdu_info. This is later used
  3190. * to fill in TCL Input descriptor (per-packet TID override).
  3191. */
  3192. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3193. /*
  3194. * Classify the frame and call corresponding
  3195. * "prepare" function which extracts the segment (TSO)
  3196. * and fragmentation information (for TSO , SG, ME, or Raw)
  3197. * into MSDU_INFO structure which is later used to fill
  3198. * SW and HW descriptors.
  3199. */
  3200. if (qdf_nbuf_is_tso(nbuf)) {
  3201. dp_verbose_debug("TSO frame %pK", vdev);
  3202. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3203. qdf_nbuf_len(nbuf));
  3204. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3205. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3206. qdf_nbuf_len(nbuf));
  3207. return nbuf;
  3208. }
  3209. goto send_multiple;
  3210. }
  3211. /* SG */
  3212. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3213. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3214. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3215. return nbuf;
  3216. } else {
  3217. struct dp_tx_seg_info_s seg_info = {0};
  3218. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3219. &msdu_info);
  3220. if (!nbuf)
  3221. return NULL;
  3222. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3223. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3224. qdf_nbuf_len(nbuf));
  3225. goto send_multiple;
  3226. }
  3227. }
  3228. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3229. return NULL;
  3230. /* RAW */
  3231. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3232. struct dp_tx_seg_info_s seg_info = {0};
  3233. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3234. if (!nbuf)
  3235. return NULL;
  3236. dp_verbose_debug("Raw frame %pK", vdev);
  3237. goto send_multiple;
  3238. }
  3239. if (qdf_unlikely(vdev->nawds_enabled)) {
  3240. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3241. qdf_nbuf_data(nbuf);
  3242. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3243. uint16_t sa_peer_id = DP_INVALID_PEER;
  3244. if (!soc->ast_offload_support) {
  3245. struct dp_ast_entry *ast_entry = NULL;
  3246. qdf_spin_lock_bh(&soc->ast_lock);
  3247. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3248. (soc,
  3249. (uint8_t *)(eh->ether_shost),
  3250. vdev->pdev->pdev_id);
  3251. if (ast_entry)
  3252. sa_peer_id = ast_entry->peer_id;
  3253. qdf_spin_unlock_bh(&soc->ast_lock);
  3254. }
  3255. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3256. sa_peer_id);
  3257. }
  3258. peer_id = DP_INVALID_PEER;
  3259. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3260. 1, qdf_nbuf_len(nbuf));
  3261. }
  3262. /* Single linear frame */
  3263. /*
  3264. * If nbuf is a simple linear frame, use send_single function to
  3265. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3266. * SRNG. There is no need to setup a MSDU extension descriptor.
  3267. */
  3268. dp_tx_prefetch_nbuf_data(nbuf);
  3269. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3270. peer_id, end_nbuf);
  3271. return nbuf;
  3272. send_multiple:
  3273. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3274. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3275. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3276. return nbuf;
  3277. }
  3278. /**
  3279. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3280. * case to vaoid check in perpkt path.
  3281. * @soc: DP soc handle
  3282. * @vdev_id: id of DP vdev handle
  3283. * @nbuf: skb
  3284. *
  3285. * Entry point for Core Tx layer (DP_TX) invoked from
  3286. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3287. * with special condition to avoid per pkt check in dp_tx_send
  3288. *
  3289. * Return: NULL on success,
  3290. * nbuf when it fails to send
  3291. */
  3292. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3293. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3294. {
  3295. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3296. struct dp_vdev *vdev = NULL;
  3297. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3298. return nbuf;
  3299. /*
  3300. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3301. * this in per packet path.
  3302. *
  3303. * As in this path vdev memory is already protected with netdev
  3304. * tx lock
  3305. */
  3306. vdev = soc->vdev_id_map[vdev_id];
  3307. if (qdf_unlikely(!vdev))
  3308. return nbuf;
  3309. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3310. == QDF_STATUS_E_FAILURE)) {
  3311. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3312. return nbuf;
  3313. }
  3314. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3315. }
  3316. #ifdef UMAC_SUPPORT_PROXY_ARP
  3317. /**
  3318. * dp_tx_proxy_arp() - Tx proxy arp handler
  3319. * @vdev: datapath vdev handle
  3320. * @buf: sk buffer
  3321. *
  3322. * Return: status
  3323. */
  3324. static inline
  3325. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3326. {
  3327. if (vdev->osif_proxy_arp)
  3328. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3329. /*
  3330. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3331. * osif_proxy_arp has a valid function pointer assigned
  3332. * to it
  3333. */
  3334. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3335. return QDF_STATUS_NOT_INITIALIZED;
  3336. }
  3337. #else
  3338. /**
  3339. * dp_tx_proxy_arp() - Tx proxy arp handler
  3340. * @vdev: datapath vdev handle
  3341. * @buf: sk buffer
  3342. *
  3343. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3344. * is not defined.
  3345. *
  3346. * Return: status
  3347. */
  3348. static inline
  3349. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3350. {
  3351. return QDF_STATUS_SUCCESS;
  3352. }
  3353. #endif
  3354. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3355. #ifdef WLAN_MCAST_MLO
  3356. static bool
  3357. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3358. struct dp_tx_desc_s *tx_desc,
  3359. qdf_nbuf_t nbuf,
  3360. uint8_t reinject_reason)
  3361. {
  3362. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3363. if (soc->arch_ops.dp_tx_mcast_handler)
  3364. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3365. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3366. return true;
  3367. }
  3368. return false;
  3369. }
  3370. #else /* WLAN_MCAST_MLO */
  3371. static inline bool
  3372. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3373. struct dp_tx_desc_s *tx_desc,
  3374. qdf_nbuf_t nbuf,
  3375. uint8_t reinject_reason)
  3376. {
  3377. return false;
  3378. }
  3379. #endif /* WLAN_MCAST_MLO */
  3380. #else
  3381. static inline bool
  3382. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3383. struct dp_tx_desc_s *tx_desc,
  3384. qdf_nbuf_t nbuf,
  3385. uint8_t reinject_reason)
  3386. {
  3387. return false;
  3388. }
  3389. #endif
  3390. /**
  3391. * dp_tx_reinject_handler() - Tx Reinject Handler
  3392. * @soc: datapath soc handle
  3393. * @vdev: datapath vdev handle
  3394. * @tx_desc: software descriptor head pointer
  3395. * @status : Tx completion status from HTT descriptor
  3396. * @reinject_reason : reinject reason from HTT descriptor
  3397. *
  3398. * This function reinjects frames back to Target.
  3399. * Todo - Host queue needs to be added
  3400. *
  3401. * Return: none
  3402. */
  3403. void dp_tx_reinject_handler(struct dp_soc *soc,
  3404. struct dp_vdev *vdev,
  3405. struct dp_tx_desc_s *tx_desc,
  3406. uint8_t *status,
  3407. uint8_t reinject_reason)
  3408. {
  3409. struct dp_peer *peer = NULL;
  3410. uint32_t peer_id = HTT_INVALID_PEER;
  3411. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3412. qdf_nbuf_t nbuf_copy = NULL;
  3413. struct dp_tx_msdu_info_s msdu_info;
  3414. #ifdef WDS_VENDOR_EXTENSION
  3415. int is_mcast = 0, is_ucast = 0;
  3416. int num_peers_3addr = 0;
  3417. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3418. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3419. #endif
  3420. struct dp_txrx_peer *txrx_peer;
  3421. qdf_assert(vdev);
  3422. dp_tx_debug("Tx reinject path");
  3423. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3424. qdf_nbuf_len(tx_desc->nbuf));
  3425. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3426. return;
  3427. #ifdef WDS_VENDOR_EXTENSION
  3428. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3429. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3430. } else {
  3431. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3432. }
  3433. is_ucast = !is_mcast;
  3434. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3435. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3436. txrx_peer = dp_get_txrx_peer(peer);
  3437. if (!txrx_peer || txrx_peer->bss_peer)
  3438. continue;
  3439. /* Detect wds peers that use 3-addr framing for mcast.
  3440. * if there are any, the bss_peer is used to send the
  3441. * the mcast frame using 3-addr format. all wds enabled
  3442. * peers that use 4-addr framing for mcast frames will
  3443. * be duplicated and sent as 4-addr frames below.
  3444. */
  3445. if (!txrx_peer->wds_enabled ||
  3446. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3447. num_peers_3addr = 1;
  3448. break;
  3449. }
  3450. }
  3451. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3452. #endif
  3453. if (qdf_unlikely(vdev->mesh_vdev)) {
  3454. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3455. } else {
  3456. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3457. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3458. txrx_peer = dp_get_txrx_peer(peer);
  3459. if (!txrx_peer)
  3460. continue;
  3461. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3462. #ifdef WDS_VENDOR_EXTENSION
  3463. /*
  3464. * . if 3-addr STA, then send on BSS Peer
  3465. * . if Peer WDS enabled and accept 4-addr mcast,
  3466. * send mcast on that peer only
  3467. * . if Peer WDS enabled and accept 4-addr ucast,
  3468. * send ucast on that peer only
  3469. */
  3470. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3471. (txrx_peer->wds_enabled &&
  3472. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3473. (is_ucast &&
  3474. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3475. #else
  3476. (txrx_peer->bss_peer &&
  3477. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3478. #endif
  3479. peer_id = DP_INVALID_PEER;
  3480. nbuf_copy = qdf_nbuf_copy(nbuf);
  3481. if (!nbuf_copy) {
  3482. dp_tx_debug("nbuf copy failed");
  3483. break;
  3484. }
  3485. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3486. dp_tx_get_queue(vdev, nbuf,
  3487. &msdu_info.tx_queue);
  3488. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3489. nbuf_copy,
  3490. &msdu_info,
  3491. peer_id,
  3492. NULL);
  3493. if (nbuf_copy) {
  3494. dp_tx_debug("pkt send failed");
  3495. qdf_nbuf_free(nbuf_copy);
  3496. }
  3497. }
  3498. }
  3499. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3500. }
  3501. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE,
  3502. nbuf->len);
  3503. qdf_nbuf_free(nbuf);
  3504. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3505. }
  3506. /**
  3507. * dp_tx_inspect_handler() - Tx Inspect Handler
  3508. * @soc: datapath soc handle
  3509. * @vdev: datapath vdev handle
  3510. * @tx_desc: software descriptor head pointer
  3511. * @status : Tx completion status from HTT descriptor
  3512. *
  3513. * Handles Tx frames sent back to Host for inspection
  3514. * (ProxyARP)
  3515. *
  3516. * Return: none
  3517. */
  3518. void dp_tx_inspect_handler(struct dp_soc *soc,
  3519. struct dp_vdev *vdev,
  3520. struct dp_tx_desc_s *tx_desc,
  3521. uint8_t *status)
  3522. {
  3523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3524. "%s Tx inspect path",
  3525. __func__);
  3526. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3527. qdf_nbuf_len(tx_desc->nbuf));
  3528. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3529. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3530. }
  3531. #ifdef MESH_MODE_SUPPORT
  3532. /**
  3533. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3534. * in mesh meta header
  3535. * @tx_desc: software descriptor head pointer
  3536. * @ts: pointer to tx completion stats
  3537. * Return: none
  3538. */
  3539. static
  3540. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3541. struct hal_tx_completion_status *ts)
  3542. {
  3543. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3544. if (!tx_desc->msdu_ext_desc) {
  3545. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3547. "netbuf %pK offset %d",
  3548. netbuf, tx_desc->pkt_offset);
  3549. return;
  3550. }
  3551. }
  3552. }
  3553. #else
  3554. static
  3555. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3556. struct hal_tx_completion_status *ts)
  3557. {
  3558. }
  3559. #endif
  3560. #ifdef CONFIG_SAWF
  3561. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3562. struct dp_vdev *vdev,
  3563. struct dp_txrx_peer *txrx_peer,
  3564. struct dp_tx_desc_s *tx_desc,
  3565. struct hal_tx_completion_status *ts,
  3566. uint8_t tid)
  3567. {
  3568. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3569. ts, tid);
  3570. }
  3571. #else
  3572. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3573. struct dp_vdev *vdev,
  3574. struct dp_txrx_peer *txrx_peer,
  3575. struct dp_tx_desc_s *tx_desc,
  3576. struct hal_tx_completion_status *ts,
  3577. uint8_t tid)
  3578. {
  3579. }
  3580. #endif
  3581. #ifdef QCA_PEER_EXT_STATS
  3582. /*
  3583. * dp_tx_compute_tid_delay() - Compute per TID delay
  3584. * @stats: Per TID delay stats
  3585. * @tx_desc: Software Tx descriptor
  3586. *
  3587. * Compute the software enqueue and hw enqueue delays and
  3588. * update the respective histograms
  3589. *
  3590. * Return: void
  3591. */
  3592. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3593. struct dp_tx_desc_s *tx_desc)
  3594. {
  3595. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3596. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3597. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3598. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3599. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3600. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3601. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3602. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3603. timestamp_hw_enqueue);
  3604. /*
  3605. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3606. */
  3607. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3608. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3609. }
  3610. /*
  3611. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3612. * @txrx_peer: DP peer context
  3613. * @tx_desc: Tx software descriptor
  3614. * @tid: Transmission ID
  3615. * @ring_id: Rx CPU context ID/CPU_ID
  3616. *
  3617. * Update the peer extended stats. These are enhanced other
  3618. * delay stats per msdu level.
  3619. *
  3620. * Return: void
  3621. */
  3622. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3623. struct dp_tx_desc_s *tx_desc,
  3624. uint8_t tid, uint8_t ring_id)
  3625. {
  3626. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3627. struct dp_soc *soc = NULL;
  3628. struct dp_peer_delay_stats *delay_stats = NULL;
  3629. soc = pdev->soc;
  3630. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3631. return;
  3632. delay_stats = txrx_peer->delay_stats;
  3633. qdf_assert(delay_stats);
  3634. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3635. /*
  3636. * For non-TID packets use the TID 9
  3637. */
  3638. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3639. tid = CDP_MAX_DATA_TIDS - 1;
  3640. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3641. tx_desc);
  3642. }
  3643. #else
  3644. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3645. struct dp_tx_desc_s *tx_desc,
  3646. uint8_t tid, uint8_t ring_id)
  3647. {
  3648. }
  3649. #endif
  3650. #ifdef HW_TX_DELAY_STATS_ENABLE
  3651. /**
  3652. * dp_update_tx_delay_stats() - update the delay stats
  3653. * @vdev: vdev handle
  3654. * @delay: delay in ms or us based on the flag delay_in_us
  3655. * @tid: tid value
  3656. * @mode: type of tx delay mode
  3657. * @ring id: ring number
  3658. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3659. *
  3660. * Return: none
  3661. */
  3662. static inline
  3663. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3664. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3665. {
  3666. struct cdp_tid_tx_stats *tstats =
  3667. &vdev->stats.tid_tx_stats[ring_id][tid];
  3668. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3669. delay_in_us);
  3670. }
  3671. #else
  3672. static inline
  3673. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3674. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3675. {
  3676. struct cdp_tid_tx_stats *tstats =
  3677. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3678. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3679. delay_in_us);
  3680. }
  3681. #endif
  3682. /**
  3683. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3684. * to pass in correct fields
  3685. *
  3686. * @vdev: pdev handle
  3687. * @tx_desc: tx descriptor
  3688. * @tid: tid value
  3689. * @ring_id: TCL or WBM ring number for transmit path
  3690. * Return: none
  3691. */
  3692. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3693. uint8_t tid, uint8_t ring_id)
  3694. {
  3695. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3696. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3697. uint32_t fwhw_transmit_delay_us;
  3698. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3699. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3700. return;
  3701. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3702. fwhw_transmit_delay_us =
  3703. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3704. qdf_ktime_to_us(tx_desc->timestamp);
  3705. /*
  3706. * Delay between packet enqueued to HW and Tx completion in us
  3707. */
  3708. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3709. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3710. ring_id, true);
  3711. /*
  3712. * For MCL, only enqueue to completion delay is required
  3713. * so return if the vdev flag is enabled.
  3714. */
  3715. return;
  3716. }
  3717. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3718. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3719. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3720. timestamp_hw_enqueue);
  3721. /*
  3722. * Delay between packet enqueued to HW and Tx completion in ms
  3723. */
  3724. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3725. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3726. false);
  3727. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3728. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3729. interframe_delay = (uint32_t)(timestamp_ingress -
  3730. vdev->prev_tx_enq_tstamp);
  3731. /*
  3732. * Delay in software enqueue
  3733. */
  3734. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3735. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3736. false);
  3737. /*
  3738. * Update interframe delay stats calculated at hardstart receive point.
  3739. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3740. * interframe delay will not be calculate correctly for 1st frame.
  3741. * On the other side, this will help in avoiding extra per packet check
  3742. * of !vdev->prev_tx_enq_tstamp.
  3743. */
  3744. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3745. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3746. false);
  3747. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3748. }
  3749. #ifdef DISABLE_DP_STATS
  3750. static
  3751. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3752. struct dp_txrx_peer *txrx_peer)
  3753. {
  3754. }
  3755. #else
  3756. static inline void
  3757. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3758. {
  3759. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3760. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3761. if (subtype != QDF_PROTO_INVALID)
  3762. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3763. 1);
  3764. }
  3765. #endif
  3766. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3767. /**
  3768. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3769. *
  3770. * @ts: Tx compltion status
  3771. * @txrx_peer: datapath txrx_peer handle
  3772. *
  3773. * Return: void
  3774. */
  3775. static inline void
  3776. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3777. struct dp_txrx_peer *txrx_peer)
  3778. {
  3779. uint8_t mcs, pkt_type, dst_mcs_idx;
  3780. uint8_t retry_threshold = txrx_peer->mpdu_retry_threshold;
  3781. mcs = ts->mcs;
  3782. pkt_type = ts->pkt_type;
  3783. /* do HW to SW pkt type conversion */
  3784. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3785. hal_2_dp_pkt_type_map[pkt_type]);
  3786. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3787. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3788. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3789. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3790. 1);
  3791. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3792. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3793. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3794. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3795. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3796. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3797. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3798. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3799. if (ts->first_msdu) {
  3800. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3801. ts->transmit_cnt > 1);
  3802. if (!retry_threshold)
  3803. return;
  3804. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3805. qdf_do_div(ts->transmit_cnt,
  3806. retry_threshold),
  3807. ts->transmit_cnt > retry_threshold);
  3808. }
  3809. }
  3810. #else
  3811. static inline void
  3812. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3813. struct dp_txrx_peer *txrx_peer)
  3814. {
  3815. }
  3816. #endif
  3817. /**
  3818. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3819. * per wbm ring
  3820. *
  3821. * @tx_desc: software descriptor head pointer
  3822. * @ts: Tx completion status
  3823. * @peer: peer handle
  3824. * @ring_id: ring number
  3825. *
  3826. * Return: None
  3827. */
  3828. static inline void
  3829. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3830. struct hal_tx_completion_status *ts,
  3831. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3832. {
  3833. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3834. uint8_t tid = ts->tid;
  3835. uint32_t length;
  3836. struct cdp_tid_tx_stats *tid_stats;
  3837. if (!pdev)
  3838. return;
  3839. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3840. tid = CDP_MAX_DATA_TIDS - 1;
  3841. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3842. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3843. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3844. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3845. return;
  3846. }
  3847. length = qdf_nbuf_len(tx_desc->nbuf);
  3848. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3849. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3850. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3851. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3852. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3853. tid_stats->tqm_status_cnt[ts->status]++;
  3854. }
  3855. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3856. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3857. ts->transmit_cnt > 1);
  3858. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3859. 1, ts->transmit_cnt > 2);
  3860. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3861. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3862. ts->msdu_part_of_amsdu);
  3863. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3864. !ts->msdu_part_of_amsdu);
  3865. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3866. qdf_system_ticks();
  3867. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3868. return;
  3869. }
  3870. /*
  3871. * tx_failed is ideally supposed to be updated from HTT ppdu
  3872. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3873. * hw limitation there are no completions for failed cases.
  3874. * Hence updating tx_failed from data path. Please note that
  3875. * if tx_failed is fixed to be from ppdu, then this has to be
  3876. * removed
  3877. */
  3878. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3879. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3880. ts->transmit_cnt > DP_RETRY_COUNT);
  3881. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3882. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3883. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3884. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3885. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3886. length);
  3887. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3888. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3889. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3890. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3891. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3892. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3893. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3894. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3895. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3896. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3897. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3898. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3899. tx.dropped.fw_rem_queue_disable, 1);
  3900. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3901. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3902. tx.dropped.fw_rem_no_match, 1);
  3903. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3904. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3905. tx.dropped.drop_threshold, 1);
  3906. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3907. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3908. tx.dropped.drop_link_desc_na, 1);
  3909. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3910. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3911. tx.dropped.invalid_drop, 1);
  3912. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3913. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3914. tx.dropped.mcast_vdev_drop, 1);
  3915. } else {
  3916. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3917. }
  3918. }
  3919. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3920. /**
  3921. * dp_tx_flow_pool_lock() - take flow pool lock
  3922. * @soc: core txrx main context
  3923. * @tx_desc: tx desc
  3924. *
  3925. * Return: None
  3926. */
  3927. static inline
  3928. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3929. struct dp_tx_desc_s *tx_desc)
  3930. {
  3931. struct dp_tx_desc_pool_s *pool;
  3932. uint8_t desc_pool_id;
  3933. desc_pool_id = tx_desc->pool_id;
  3934. pool = &soc->tx_desc[desc_pool_id];
  3935. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3936. }
  3937. /**
  3938. * dp_tx_flow_pool_unlock() - release flow pool lock
  3939. * @soc: core txrx main context
  3940. * @tx_desc: tx desc
  3941. *
  3942. * Return: None
  3943. */
  3944. static inline
  3945. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3946. struct dp_tx_desc_s *tx_desc)
  3947. {
  3948. struct dp_tx_desc_pool_s *pool;
  3949. uint8_t desc_pool_id;
  3950. desc_pool_id = tx_desc->pool_id;
  3951. pool = &soc->tx_desc[desc_pool_id];
  3952. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3953. }
  3954. #else
  3955. static inline
  3956. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3957. {
  3958. }
  3959. static inline
  3960. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3961. {
  3962. }
  3963. #endif
  3964. /**
  3965. * dp_tx_notify_completion() - Notify tx completion for this desc
  3966. * @soc: core txrx main context
  3967. * @vdev: datapath vdev handle
  3968. * @tx_desc: tx desc
  3969. * @netbuf: buffer
  3970. * @status: tx status
  3971. *
  3972. * Return: none
  3973. */
  3974. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3975. struct dp_vdev *vdev,
  3976. struct dp_tx_desc_s *tx_desc,
  3977. qdf_nbuf_t netbuf,
  3978. uint8_t status)
  3979. {
  3980. void *osif_dev;
  3981. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3982. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3983. qdf_assert(tx_desc);
  3984. if (!vdev ||
  3985. !vdev->osif_vdev) {
  3986. return;
  3987. }
  3988. osif_dev = vdev->osif_vdev;
  3989. tx_compl_cbk = vdev->tx_comp;
  3990. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3991. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3992. if (tx_compl_cbk)
  3993. tx_compl_cbk(netbuf, osif_dev, flag);
  3994. }
  3995. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3996. * @pdev: pdev handle
  3997. * @tid: tid value
  3998. * @txdesc_ts: timestamp from txdesc
  3999. * @ppdu_id: ppdu id
  4000. *
  4001. * Return: none
  4002. */
  4003. #ifdef FEATURE_PERPKT_INFO
  4004. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4005. struct dp_txrx_peer *txrx_peer,
  4006. uint8_t tid,
  4007. uint64_t txdesc_ts,
  4008. uint32_t ppdu_id)
  4009. {
  4010. uint64_t delta_ms;
  4011. struct cdp_tx_sojourn_stats *sojourn_stats;
  4012. struct dp_peer *primary_link_peer = NULL;
  4013. struct dp_soc *link_peer_soc = NULL;
  4014. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4015. return;
  4016. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4017. tid >= CDP_DATA_TID_MAX))
  4018. return;
  4019. if (qdf_unlikely(!pdev->sojourn_buf))
  4020. return;
  4021. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4022. txrx_peer->peer_id,
  4023. DP_MOD_ID_TX_COMP);
  4024. if (qdf_unlikely(!primary_link_peer))
  4025. return;
  4026. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4027. qdf_nbuf_data(pdev->sojourn_buf);
  4028. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4029. sojourn_stats->cookie = (void *)
  4030. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4031. primary_link_peer);
  4032. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4033. txdesc_ts;
  4034. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4035. delta_ms);
  4036. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4037. sojourn_stats->num_msdus[tid] = 1;
  4038. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4039. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4040. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4041. pdev->sojourn_buf, HTT_INVALID_PEER,
  4042. WDI_NO_VAL, pdev->pdev_id);
  4043. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4044. sojourn_stats->num_msdus[tid] = 0;
  4045. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4046. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4047. }
  4048. #else
  4049. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4050. struct dp_txrx_peer *txrx_peer,
  4051. uint8_t tid,
  4052. uint64_t txdesc_ts,
  4053. uint32_t ppdu_id)
  4054. {
  4055. }
  4056. #endif
  4057. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4058. /**
  4059. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4060. * @soc: dp_soc handle
  4061. * @desc: Tx Descriptor
  4062. * @ts: HAL Tx completion descriptor contents
  4063. *
  4064. * This function is used to send tx completion to packet capture
  4065. */
  4066. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4067. struct dp_tx_desc_s *desc,
  4068. struct hal_tx_completion_status *ts)
  4069. {
  4070. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4071. desc, ts->peer_id,
  4072. WDI_NO_VAL, desc->pdev->pdev_id);
  4073. }
  4074. #endif
  4075. /**
  4076. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4077. * @soc: DP Soc handle
  4078. * @tx_desc: software Tx descriptor
  4079. * @ts : Tx completion status from HAL/HTT descriptor
  4080. *
  4081. * Return: none
  4082. */
  4083. void
  4084. dp_tx_comp_process_desc(struct dp_soc *soc,
  4085. struct dp_tx_desc_s *desc,
  4086. struct hal_tx_completion_status *ts,
  4087. struct dp_txrx_peer *txrx_peer)
  4088. {
  4089. uint64_t time_latency = 0;
  4090. uint16_t peer_id = DP_INVALID_PEER_ID;
  4091. /*
  4092. * m_copy/tx_capture modes are not supported for
  4093. * scatter gather packets
  4094. */
  4095. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4096. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4097. qdf_ktime_to_ms(desc->timestamp));
  4098. }
  4099. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4100. if (dp_tx_pkt_tracepoints_enabled())
  4101. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4102. desc->msdu_ext_desc ?
  4103. desc->msdu_ext_desc->tso_desc : NULL,
  4104. qdf_ktime_to_ms(desc->timestamp));
  4105. if (!(desc->msdu_ext_desc)) {
  4106. dp_tx_enh_unmap(soc, desc);
  4107. if (txrx_peer)
  4108. peer_id = txrx_peer->peer_id;
  4109. if (QDF_STATUS_SUCCESS ==
  4110. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4111. return;
  4112. }
  4113. if (QDF_STATUS_SUCCESS ==
  4114. dp_get_completion_indication_for_stack(soc,
  4115. desc->pdev,
  4116. txrx_peer, ts,
  4117. desc->nbuf,
  4118. time_latency)) {
  4119. dp_send_completion_to_stack(soc,
  4120. desc->pdev,
  4121. ts->peer_id,
  4122. ts->ppdu_id,
  4123. desc->nbuf);
  4124. return;
  4125. }
  4126. }
  4127. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4128. dp_tx_comp_free_buf(soc, desc);
  4129. }
  4130. #ifdef DISABLE_DP_STATS
  4131. /**
  4132. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4133. * @soc: core txrx main context
  4134. * @tx_desc: tx desc
  4135. * @status: tx status
  4136. *
  4137. * Return: none
  4138. */
  4139. static inline
  4140. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4141. struct dp_vdev *vdev,
  4142. struct dp_tx_desc_s *tx_desc,
  4143. uint8_t status)
  4144. {
  4145. }
  4146. #else
  4147. static inline
  4148. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4149. struct dp_vdev *vdev,
  4150. struct dp_tx_desc_s *tx_desc,
  4151. uint8_t status)
  4152. {
  4153. void *osif_dev;
  4154. ol_txrx_stats_rx_fp stats_cbk;
  4155. uint8_t pkt_type;
  4156. qdf_assert(tx_desc);
  4157. if (!vdev ||
  4158. !vdev->osif_vdev ||
  4159. !vdev->stats_cb)
  4160. return;
  4161. osif_dev = vdev->osif_vdev;
  4162. stats_cbk = vdev->stats_cb;
  4163. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4164. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4165. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4166. &pkt_type);
  4167. }
  4168. #endif
  4169. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4170. QDF_STATUS
  4171. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4172. uint32_t delta_tsf,
  4173. uint32_t *delay_us)
  4174. {
  4175. uint32_t buffer_ts;
  4176. uint32_t delay;
  4177. if (!delay_us)
  4178. return QDF_STATUS_E_INVAL;
  4179. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4180. if (!ts->valid)
  4181. return QDF_STATUS_E_INVAL;
  4182. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4183. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4184. * valid up to 29 bits.
  4185. */
  4186. buffer_ts = ts->buffer_timestamp << 10;
  4187. delay = ts->tsf - buffer_ts - delta_tsf;
  4188. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4189. if (delay > 0x1000000) {
  4190. dp_info_rl("----------------------\n"
  4191. "Tx completion status:\n"
  4192. "----------------------\n"
  4193. "release_src = %d\n"
  4194. "ppdu_id = 0x%x\n"
  4195. "release_reason = %d\n"
  4196. "tsf = %u (0x%x)\n"
  4197. "buffer_timestamp = %u (0x%x)\n"
  4198. "delta_tsf = %u (0x%x)\n",
  4199. ts->release_src, ts->ppdu_id, ts->status,
  4200. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4201. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4202. return QDF_STATUS_E_FAILURE;
  4203. }
  4204. *delay_us = delay;
  4205. return QDF_STATUS_SUCCESS;
  4206. }
  4207. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4208. uint32_t delta_tsf)
  4209. {
  4210. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4211. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4212. DP_MOD_ID_CDP);
  4213. if (!vdev) {
  4214. dp_err_rl("vdev %d does not exist", vdev_id);
  4215. return;
  4216. }
  4217. vdev->delta_tsf = delta_tsf;
  4218. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4219. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4220. }
  4221. #endif
  4222. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4223. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4224. uint8_t vdev_id, bool enable)
  4225. {
  4226. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4227. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4228. DP_MOD_ID_CDP);
  4229. if (!vdev) {
  4230. dp_err_rl("vdev %d does not exist", vdev_id);
  4231. return QDF_STATUS_E_FAILURE;
  4232. }
  4233. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4234. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4235. return QDF_STATUS_SUCCESS;
  4236. }
  4237. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4238. uint32_t *val)
  4239. {
  4240. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4241. struct dp_vdev *vdev;
  4242. uint32_t delay_accum;
  4243. uint32_t pkts_accum;
  4244. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4245. if (!vdev) {
  4246. dp_err_rl("vdev %d does not exist", vdev_id);
  4247. return QDF_STATUS_E_FAILURE;
  4248. }
  4249. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4250. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4251. return QDF_STATUS_E_FAILURE;
  4252. }
  4253. /* Average uplink delay based on current accumulated values */
  4254. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4255. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4256. *val = delay_accum / pkts_accum;
  4257. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4258. delay_accum, pkts_accum);
  4259. /* Reset accumulated values to 0 */
  4260. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4261. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4262. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4263. return QDF_STATUS_SUCCESS;
  4264. }
  4265. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4266. struct hal_tx_completion_status *ts)
  4267. {
  4268. uint32_t ul_delay;
  4269. if (qdf_unlikely(!vdev)) {
  4270. dp_info_rl("vdev is null or delete in progrss");
  4271. return;
  4272. }
  4273. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4274. return;
  4275. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4276. vdev->delta_tsf,
  4277. &ul_delay)))
  4278. return;
  4279. ul_delay /= 1000; /* in unit of ms */
  4280. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4281. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4282. }
  4283. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4284. static inline
  4285. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4286. struct hal_tx_completion_status *ts)
  4287. {
  4288. }
  4289. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4290. /**
  4291. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4292. * @soc: DP soc handle
  4293. * @tx_desc: software descriptor head pointer
  4294. * @ts: Tx completion status
  4295. * @txrx_peer: txrx peer handle
  4296. * @ring_id: ring number
  4297. *
  4298. * Return: none
  4299. */
  4300. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4301. struct dp_tx_desc_s *tx_desc,
  4302. struct hal_tx_completion_status *ts,
  4303. struct dp_txrx_peer *txrx_peer,
  4304. uint8_t ring_id)
  4305. {
  4306. uint32_t length;
  4307. qdf_ether_header_t *eh;
  4308. struct dp_vdev *vdev = NULL;
  4309. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4310. enum qdf_dp_tx_rx_status dp_status;
  4311. if (!nbuf) {
  4312. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4313. goto out;
  4314. }
  4315. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4316. length = qdf_nbuf_len(nbuf);
  4317. dp_status = dp_tx_hw_to_qdf(ts->status);
  4318. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4319. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4320. QDF_TRACE_DEFAULT_PDEV_ID,
  4321. qdf_nbuf_data_addr(nbuf),
  4322. sizeof(qdf_nbuf_data(nbuf)),
  4323. tx_desc->id, ts->status, dp_status));
  4324. dp_tx_comp_debug("-------------------- \n"
  4325. "Tx Completion Stats: \n"
  4326. "-------------------- \n"
  4327. "ack_frame_rssi = %d \n"
  4328. "first_msdu = %d \n"
  4329. "last_msdu = %d \n"
  4330. "msdu_part_of_amsdu = %d \n"
  4331. "rate_stats valid = %d \n"
  4332. "bw = %d \n"
  4333. "pkt_type = %d \n"
  4334. "stbc = %d \n"
  4335. "ldpc = %d \n"
  4336. "sgi = %d \n"
  4337. "mcs = %d \n"
  4338. "ofdma = %d \n"
  4339. "tones_in_ru = %d \n"
  4340. "tsf = %d \n"
  4341. "ppdu_id = %d \n"
  4342. "transmit_cnt = %d \n"
  4343. "tid = %d \n"
  4344. "peer_id = %d\n"
  4345. "tx_status = %d\n",
  4346. ts->ack_frame_rssi, ts->first_msdu,
  4347. ts->last_msdu, ts->msdu_part_of_amsdu,
  4348. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4349. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4350. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4351. ts->transmit_cnt, ts->tid, ts->peer_id,
  4352. ts->status);
  4353. /* Update SoC level stats */
  4354. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4355. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4356. if (!txrx_peer) {
  4357. dp_info_rl("peer is null or deletion in progress");
  4358. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4359. goto out;
  4360. }
  4361. vdev = txrx_peer->vdev;
  4362. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4363. dp_tx_update_uplink_delay(soc, vdev, ts);
  4364. /* check tx complete notification */
  4365. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4366. dp_tx_notify_completion(soc, vdev, tx_desc,
  4367. nbuf, ts->status);
  4368. /* Update per-packet stats for mesh mode */
  4369. if (qdf_unlikely(vdev->mesh_vdev) &&
  4370. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4371. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4372. /* Update peer level stats */
  4373. if (qdf_unlikely(txrx_peer->bss_peer &&
  4374. vdev->opmode == wlan_op_mode_ap)) {
  4375. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4376. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4377. length);
  4378. if (txrx_peer->vdev->tx_encap_type ==
  4379. htt_cmn_pkt_type_ethernet &&
  4380. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4381. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4382. tx.bcast, 1,
  4383. length);
  4384. }
  4385. }
  4386. } else {
  4387. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4388. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4389. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4390. 1, length);
  4391. if (qdf_unlikely(txrx_peer->in_twt)) {
  4392. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4393. tx.tx_success_twt,
  4394. 1, length);
  4395. }
  4396. }
  4397. }
  4398. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4399. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4400. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4401. ts, ts->tid);
  4402. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4403. #ifdef QCA_SUPPORT_RDK_STATS
  4404. if (soc->peerstats_enabled)
  4405. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4406. qdf_ktime_to_ms(tx_desc->timestamp),
  4407. ts->ppdu_id);
  4408. #endif
  4409. out:
  4410. return;
  4411. }
  4412. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4413. defined(QCA_ENHANCED_STATS_SUPPORT)
  4414. /*
  4415. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4416. * @txrx_peer: Datapath txrx_peer handle
  4417. * @length: Length of the packet
  4418. * @tx_status: Tx status from TQM/FW
  4419. * @update: enhanced flag value present in dp_pdev
  4420. *
  4421. * Return: none
  4422. */
  4423. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4424. uint32_t length, uint8_t tx_status,
  4425. bool update)
  4426. {
  4427. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  4428. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4429. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4430. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4431. }
  4432. }
  4433. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4434. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4435. uint32_t length, uint8_t tx_status,
  4436. bool update)
  4437. {
  4438. if (!peer->hw_txrx_stats_en) {
  4439. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4440. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4441. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4442. }
  4443. }
  4444. #else
  4445. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4446. uint32_t length, uint8_t tx_status,
  4447. bool update)
  4448. {
  4449. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4450. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4451. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4452. }
  4453. #endif
  4454. /*
  4455. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4456. * @nbuf: skb buffer
  4457. *
  4458. * Return: none
  4459. */
  4460. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4461. static inline
  4462. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4463. {
  4464. qdf_nbuf_t nbuf = NULL;
  4465. if (next)
  4466. nbuf = next->nbuf;
  4467. if (nbuf) {
  4468. /* prefetch skb->next and first few bytes of skb->cb */
  4469. qdf_prefetch(nbuf);
  4470. /* prefetch skb fields present in different cachelines */
  4471. qdf_prefetch(&nbuf->len);
  4472. qdf_prefetch(&nbuf->users);
  4473. qdf_prefetch(skb_end_pointer(nbuf));
  4474. }
  4475. }
  4476. #else
  4477. static inline
  4478. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4479. {
  4480. }
  4481. #endif
  4482. /**
  4483. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4484. * @soc: core txrx main context
  4485. * @desc: software descriptor
  4486. *
  4487. * Return: true when packet is reinjected
  4488. */
  4489. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4490. defined(WLAN_MCAST_MLO)
  4491. static inline bool
  4492. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4493. {
  4494. struct dp_vdev *vdev = NULL;
  4495. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4496. if (!soc->arch_ops.dp_tx_mcast_handler)
  4497. return false;
  4498. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4499. DP_MOD_ID_REINJECT);
  4500. if (qdf_unlikely(!vdev)) {
  4501. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4502. desc->id);
  4503. return false;
  4504. }
  4505. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4506. qdf_nbuf_len(desc->nbuf));
  4507. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4508. dp_tx_desc_release(desc, desc->pool_id);
  4509. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4510. return true;
  4511. }
  4512. return false;
  4513. }
  4514. #else
  4515. static inline bool
  4516. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4517. {
  4518. return false;
  4519. }
  4520. #endif
  4521. /**
  4522. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4523. * @soc: core txrx main context
  4524. * @comp_head: software descriptor head pointer
  4525. * @ring_id: ring number
  4526. *
  4527. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4528. * and release the software descriptors after processing is complete
  4529. *
  4530. * Return: none
  4531. */
  4532. static void
  4533. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4534. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4535. {
  4536. struct dp_tx_desc_s *desc;
  4537. struct dp_tx_desc_s *next;
  4538. struct hal_tx_completion_status ts;
  4539. struct dp_txrx_peer *txrx_peer = NULL;
  4540. uint16_t peer_id = DP_INVALID_PEER;
  4541. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4542. desc = comp_head;
  4543. while (desc) {
  4544. next = desc->next;
  4545. dp_tx_prefetch_next_nbuf_data(next);
  4546. if (peer_id != desc->peer_id) {
  4547. if (txrx_peer)
  4548. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4549. DP_MOD_ID_TX_COMP);
  4550. peer_id = desc->peer_id;
  4551. txrx_peer =
  4552. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4553. &txrx_ref_handle,
  4554. DP_MOD_ID_TX_COMP);
  4555. }
  4556. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4557. desc = next;
  4558. continue;
  4559. }
  4560. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4561. struct dp_pdev *pdev = desc->pdev;
  4562. if (qdf_likely(txrx_peer))
  4563. dp_tx_update_peer_basic_stats(txrx_peer,
  4564. desc->length,
  4565. desc->tx_status,
  4566. false);
  4567. qdf_assert(pdev);
  4568. dp_tx_outstanding_dec(pdev);
  4569. /*
  4570. * Calling a QDF WRAPPER here is creating signifcant
  4571. * performance impact so avoided the wrapper call here
  4572. */
  4573. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4574. desc->id, DP_TX_COMP_UNMAP);
  4575. dp_tx_nbuf_unmap(soc, desc);
  4576. qdf_nbuf_free_simple(desc->nbuf);
  4577. dp_tx_desc_free(soc, desc, desc->pool_id);
  4578. desc = next;
  4579. continue;
  4580. }
  4581. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4582. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4583. ring_id);
  4584. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4585. dp_tx_desc_release(desc, desc->pool_id);
  4586. desc = next;
  4587. }
  4588. if (txrx_peer)
  4589. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4590. }
  4591. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4592. static inline
  4593. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4594. int max_reap_limit)
  4595. {
  4596. bool limit_hit = false;
  4597. limit_hit =
  4598. (num_reaped >= max_reap_limit) ? true : false;
  4599. if (limit_hit)
  4600. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4601. return limit_hit;
  4602. }
  4603. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4604. {
  4605. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4606. }
  4607. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4608. {
  4609. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4610. return cfg->tx_comp_loop_pkt_limit;
  4611. }
  4612. #else
  4613. static inline
  4614. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4615. int max_reap_limit)
  4616. {
  4617. return false;
  4618. }
  4619. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4620. {
  4621. return false;
  4622. }
  4623. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4624. {
  4625. return 0;
  4626. }
  4627. #endif
  4628. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4629. static inline int
  4630. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4631. int *max_reap_limit)
  4632. {
  4633. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4634. max_reap_limit);
  4635. }
  4636. #else
  4637. static inline int
  4638. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4639. int *max_reap_limit)
  4640. {
  4641. return 0;
  4642. }
  4643. #endif
  4644. #ifdef DP_TX_TRACKING
  4645. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4646. {
  4647. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4648. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4649. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4650. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4651. }
  4652. }
  4653. #endif
  4654. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4655. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4656. uint32_t quota)
  4657. {
  4658. void *tx_comp_hal_desc;
  4659. void *last_prefetched_hw_desc = NULL;
  4660. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4661. hal_soc_handle_t hal_soc;
  4662. uint8_t buffer_src;
  4663. struct dp_tx_desc_s *tx_desc = NULL;
  4664. struct dp_tx_desc_s *head_desc = NULL;
  4665. struct dp_tx_desc_s *tail_desc = NULL;
  4666. uint32_t num_processed = 0;
  4667. uint32_t count;
  4668. uint32_t num_avail_for_reap = 0;
  4669. bool force_break = false;
  4670. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4671. int max_reap_limit, ring_near_full;
  4672. DP_HIST_INIT();
  4673. more_data:
  4674. hal_soc = soc->hal_soc;
  4675. /* Re-initialize local variables to be re-used */
  4676. head_desc = NULL;
  4677. tail_desc = NULL;
  4678. count = 0;
  4679. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4680. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4681. &max_reap_limit);
  4682. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4683. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4684. return 0;
  4685. }
  4686. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4687. if (num_avail_for_reap >= quota)
  4688. num_avail_for_reap = quota;
  4689. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4690. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4691. num_avail_for_reap);
  4692. /* Find head descriptor from completion ring */
  4693. while (qdf_likely(num_avail_for_reap--)) {
  4694. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4695. if (qdf_unlikely(!tx_comp_hal_desc))
  4696. break;
  4697. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4698. tx_comp_hal_desc);
  4699. /* If this buffer was not released by TQM or FW, then it is not
  4700. * Tx completion indication, assert */
  4701. if (qdf_unlikely(buffer_src !=
  4702. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4703. (qdf_unlikely(buffer_src !=
  4704. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4705. uint8_t wbm_internal_error;
  4706. dp_err_rl(
  4707. "Tx comp release_src != TQM | FW but from %d",
  4708. buffer_src);
  4709. hal_dump_comp_desc(tx_comp_hal_desc);
  4710. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4711. /* When WBM sees NULL buffer_addr_info in any of
  4712. * ingress rings it sends an error indication,
  4713. * with wbm_internal_error=1, to a specific ring.
  4714. * The WBM2SW ring used to indicate these errors is
  4715. * fixed in HW, and that ring is being used as Tx
  4716. * completion ring. These errors are not related to
  4717. * Tx completions, and should just be ignored
  4718. */
  4719. wbm_internal_error = hal_get_wbm_internal_error(
  4720. hal_soc,
  4721. tx_comp_hal_desc);
  4722. if (wbm_internal_error) {
  4723. dp_err_rl("Tx comp wbm_internal_error!!");
  4724. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4725. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4726. buffer_src)
  4727. dp_handle_wbm_internal_error(
  4728. soc,
  4729. tx_comp_hal_desc,
  4730. hal_tx_comp_get_buffer_type(
  4731. tx_comp_hal_desc));
  4732. } else {
  4733. dp_err_rl("Tx comp wbm_internal_error false");
  4734. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4735. }
  4736. continue;
  4737. }
  4738. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4739. tx_comp_hal_desc,
  4740. &tx_desc);
  4741. if (!tx_desc) {
  4742. dp_err("unable to retrieve tx_desc!");
  4743. QDF_BUG(0);
  4744. continue;
  4745. }
  4746. tx_desc->buffer_src = buffer_src;
  4747. /*
  4748. * If the release source is FW, process the HTT status
  4749. */
  4750. if (qdf_unlikely(buffer_src ==
  4751. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4752. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4753. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4754. htt_tx_status);
  4755. /* Collect hw completion contents */
  4756. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4757. &tx_desc->comp, 1);
  4758. soc->arch_ops.dp_tx_process_htt_completion(
  4759. soc,
  4760. tx_desc,
  4761. htt_tx_status,
  4762. ring_id);
  4763. } else {
  4764. tx_desc->tx_status =
  4765. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4766. tx_desc->buffer_src = buffer_src;
  4767. /*
  4768. * If the fast completion mode is enabled extended
  4769. * metadata from descriptor is not copied
  4770. */
  4771. if (qdf_likely(tx_desc->flags &
  4772. DP_TX_DESC_FLAG_SIMPLE))
  4773. goto add_to_pool;
  4774. /*
  4775. * If the descriptor is already freed in vdev_detach,
  4776. * continue to next descriptor
  4777. */
  4778. if (qdf_unlikely
  4779. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4780. !tx_desc->flags)) {
  4781. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4782. tx_desc->id);
  4783. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4784. dp_tx_desc_check_corruption(tx_desc);
  4785. continue;
  4786. }
  4787. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4788. dp_tx_comp_info_rl("pdev in down state %d",
  4789. tx_desc->id);
  4790. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4791. dp_tx_comp_free_buf(soc, tx_desc);
  4792. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4793. goto next_desc;
  4794. }
  4795. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4796. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4797. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4798. tx_desc->flags, tx_desc->id);
  4799. qdf_assert_always(0);
  4800. }
  4801. /* Collect hw completion contents */
  4802. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4803. &tx_desc->comp, 1);
  4804. add_to_pool:
  4805. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4806. /* First ring descriptor on the cycle */
  4807. if (!head_desc) {
  4808. head_desc = tx_desc;
  4809. tail_desc = tx_desc;
  4810. }
  4811. tail_desc->next = tx_desc;
  4812. tx_desc->next = NULL;
  4813. tail_desc = tx_desc;
  4814. }
  4815. next_desc:
  4816. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4817. /*
  4818. * Processed packet count is more than given quota
  4819. * stop to processing
  4820. */
  4821. count++;
  4822. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4823. num_avail_for_reap,
  4824. hal_ring_hdl,
  4825. &last_prefetched_hw_desc,
  4826. &last_prefetched_sw_desc);
  4827. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4828. break;
  4829. }
  4830. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4831. /* Process the reaped descriptors */
  4832. if (head_desc)
  4833. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4834. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4835. /*
  4836. * If we are processing in near-full condition, there are 3 scenario
  4837. * 1) Ring entries has reached critical state
  4838. * 2) Ring entries are still near high threshold
  4839. * 3) Ring entries are below the safe level
  4840. *
  4841. * One more loop will move te state to normal processing and yield
  4842. */
  4843. if (ring_near_full)
  4844. goto more_data;
  4845. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4846. if (num_processed >= quota)
  4847. force_break = true;
  4848. if (!force_break &&
  4849. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4850. hal_ring_hdl)) {
  4851. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4852. if (!hif_exec_should_yield(soc->hif_handle,
  4853. int_ctx->dp_intr_id))
  4854. goto more_data;
  4855. }
  4856. }
  4857. DP_TX_HIST_STATS_PER_PDEV();
  4858. return num_processed;
  4859. }
  4860. #ifdef FEATURE_WLAN_TDLS
  4861. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4862. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4863. {
  4864. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4865. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4866. DP_MOD_ID_TDLS);
  4867. if (!vdev) {
  4868. dp_err("vdev handle for id %d is NULL", vdev_id);
  4869. return NULL;
  4870. }
  4871. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4872. vdev->is_tdls_frame = true;
  4873. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4874. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4875. }
  4876. #endif
  4877. /**
  4878. * dp_tx_vdev_attach() - attach vdev to dp tx
  4879. * @vdev: virtual device instance
  4880. *
  4881. * Return: QDF_STATUS_SUCCESS: success
  4882. * QDF_STATUS_E_RESOURCES: Error return
  4883. */
  4884. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4885. {
  4886. int pdev_id;
  4887. /*
  4888. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4889. */
  4890. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4891. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4892. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4893. vdev->vdev_id);
  4894. pdev_id =
  4895. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4896. vdev->pdev->pdev_id);
  4897. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4898. /*
  4899. * Set HTT Extension Valid bit to 0 by default
  4900. */
  4901. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4902. dp_tx_vdev_update_search_flags(vdev);
  4903. return QDF_STATUS_SUCCESS;
  4904. }
  4905. #ifndef FEATURE_WDS
  4906. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4907. {
  4908. return false;
  4909. }
  4910. #endif
  4911. /**
  4912. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4913. * @vdev: virtual device instance
  4914. *
  4915. * Return: void
  4916. *
  4917. */
  4918. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4919. {
  4920. struct dp_soc *soc = vdev->pdev->soc;
  4921. /*
  4922. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4923. * for TDLS link
  4924. *
  4925. * Enable AddrY (SA based search) only for non-WDS STA and
  4926. * ProxySTA VAP (in HKv1) modes.
  4927. *
  4928. * In all other VAP modes, only DA based search should be
  4929. * enabled
  4930. */
  4931. if (vdev->opmode == wlan_op_mode_sta &&
  4932. vdev->tdls_link_connected)
  4933. vdev->hal_desc_addr_search_flags =
  4934. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4935. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4936. !dp_tx_da_search_override(vdev))
  4937. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4938. else
  4939. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4940. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4941. vdev->search_type = soc->sta_mode_search_policy;
  4942. else
  4943. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4944. }
  4945. static inline bool
  4946. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4947. struct dp_vdev *vdev,
  4948. struct dp_tx_desc_s *tx_desc)
  4949. {
  4950. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4951. return false;
  4952. /*
  4953. * if vdev is given, then only check whether desc
  4954. * vdev match. if vdev is NULL, then check whether
  4955. * desc pdev match.
  4956. */
  4957. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4958. (tx_desc->pdev == pdev);
  4959. }
  4960. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4961. /**
  4962. * dp_tx_desc_flush() - release resources associated
  4963. * to TX Desc
  4964. *
  4965. * @dp_pdev: Handle to DP pdev structure
  4966. * @vdev: virtual device instance
  4967. * NULL: no specific Vdev is required and check all allcated TX desc
  4968. * on this pdev.
  4969. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4970. *
  4971. * @force_free:
  4972. * true: flush the TX desc.
  4973. * false: only reset the Vdev in each allocated TX desc
  4974. * that associated to current Vdev.
  4975. *
  4976. * This function will go through the TX desc pool to flush
  4977. * the outstanding TX data or reset Vdev to NULL in associated TX
  4978. * Desc.
  4979. */
  4980. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4981. bool force_free)
  4982. {
  4983. uint8_t i;
  4984. uint32_t j;
  4985. uint32_t num_desc, page_id, offset;
  4986. uint16_t num_desc_per_page;
  4987. struct dp_soc *soc = pdev->soc;
  4988. struct dp_tx_desc_s *tx_desc = NULL;
  4989. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4990. if (!vdev && !force_free) {
  4991. dp_err("Reset TX desc vdev, Vdev param is required!");
  4992. return;
  4993. }
  4994. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4995. tx_desc_pool = &soc->tx_desc[i];
  4996. if (!(tx_desc_pool->pool_size) ||
  4997. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4998. !(tx_desc_pool->desc_pages.cacheable_pages))
  4999. continue;
  5000. /*
  5001. * Add flow pool lock protection in case pool is freed
  5002. * due to all tx_desc is recycled when handle TX completion.
  5003. * this is not necessary when do force flush as:
  5004. * a. double lock will happen if dp_tx_desc_release is
  5005. * also trying to acquire it.
  5006. * b. dp interrupt has been disabled before do force TX desc
  5007. * flush in dp_pdev_deinit().
  5008. */
  5009. if (!force_free)
  5010. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5011. num_desc = tx_desc_pool->pool_size;
  5012. num_desc_per_page =
  5013. tx_desc_pool->desc_pages.num_element_per_page;
  5014. for (j = 0; j < num_desc; j++) {
  5015. page_id = j / num_desc_per_page;
  5016. offset = j % num_desc_per_page;
  5017. if (qdf_unlikely(!(tx_desc_pool->
  5018. desc_pages.cacheable_pages)))
  5019. break;
  5020. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5021. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5022. /*
  5023. * Free TX desc if force free is
  5024. * required, otherwise only reset vdev
  5025. * in this TX desc.
  5026. */
  5027. if (force_free) {
  5028. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5029. dp_tx_comp_free_buf(soc, tx_desc);
  5030. dp_tx_desc_release(tx_desc, i);
  5031. } else {
  5032. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5033. }
  5034. }
  5035. }
  5036. if (!force_free)
  5037. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5038. }
  5039. }
  5040. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5041. /**
  5042. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5043. *
  5044. * @soc: Handle to DP soc structure
  5045. * @tx_desc: pointer of one TX desc
  5046. * @desc_pool_id: TX Desc pool id
  5047. */
  5048. static inline void
  5049. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5050. uint8_t desc_pool_id)
  5051. {
  5052. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5053. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5054. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5055. }
  5056. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5057. bool force_free)
  5058. {
  5059. uint8_t i, num_pool;
  5060. uint32_t j;
  5061. uint32_t num_desc, page_id, offset;
  5062. uint16_t num_desc_per_page;
  5063. struct dp_soc *soc = pdev->soc;
  5064. struct dp_tx_desc_s *tx_desc = NULL;
  5065. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5066. if (!vdev && !force_free) {
  5067. dp_err("Reset TX desc vdev, Vdev param is required!");
  5068. return;
  5069. }
  5070. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5071. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5072. for (i = 0; i < num_pool; i++) {
  5073. tx_desc_pool = &soc->tx_desc[i];
  5074. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5075. continue;
  5076. num_desc_per_page =
  5077. tx_desc_pool->desc_pages.num_element_per_page;
  5078. for (j = 0; j < num_desc; j++) {
  5079. page_id = j / num_desc_per_page;
  5080. offset = j % num_desc_per_page;
  5081. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5082. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5083. if (force_free) {
  5084. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5085. dp_tx_comp_free_buf(soc, tx_desc);
  5086. dp_tx_desc_release(tx_desc, i);
  5087. } else {
  5088. dp_tx_desc_reset_vdev(soc, tx_desc,
  5089. i);
  5090. }
  5091. }
  5092. }
  5093. }
  5094. }
  5095. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5096. /**
  5097. * dp_tx_vdev_detach() - detach vdev from dp tx
  5098. * @vdev: virtual device instance
  5099. *
  5100. * Return: QDF_STATUS_SUCCESS: success
  5101. * QDF_STATUS_E_RESOURCES: Error return
  5102. */
  5103. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5104. {
  5105. struct dp_pdev *pdev = vdev->pdev;
  5106. /* Reset TX desc associated to this Vdev as NULL */
  5107. dp_tx_desc_flush(pdev, vdev, false);
  5108. return QDF_STATUS_SUCCESS;
  5109. }
  5110. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5111. /* Pools will be allocated dynamically */
  5112. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5113. int num_desc)
  5114. {
  5115. uint8_t i;
  5116. for (i = 0; i < num_pool; i++) {
  5117. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5118. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5119. }
  5120. return QDF_STATUS_SUCCESS;
  5121. }
  5122. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5123. uint32_t num_desc)
  5124. {
  5125. return QDF_STATUS_SUCCESS;
  5126. }
  5127. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5128. {
  5129. }
  5130. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5131. {
  5132. uint8_t i;
  5133. for (i = 0; i < num_pool; i++)
  5134. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5135. }
  5136. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5137. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5138. uint32_t num_desc)
  5139. {
  5140. uint8_t i, count;
  5141. /* Allocate software Tx descriptor pools */
  5142. for (i = 0; i < num_pool; i++) {
  5143. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5144. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5145. FL("Tx Desc Pool alloc %d failed %pK"),
  5146. i, soc);
  5147. goto fail;
  5148. }
  5149. }
  5150. return QDF_STATUS_SUCCESS;
  5151. fail:
  5152. for (count = 0; count < i; count++)
  5153. dp_tx_desc_pool_free(soc, count);
  5154. return QDF_STATUS_E_NOMEM;
  5155. }
  5156. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5157. uint32_t num_desc)
  5158. {
  5159. uint8_t i;
  5160. for (i = 0; i < num_pool; i++) {
  5161. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5162. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5163. FL("Tx Desc Pool init %d failed %pK"),
  5164. i, soc);
  5165. return QDF_STATUS_E_NOMEM;
  5166. }
  5167. }
  5168. return QDF_STATUS_SUCCESS;
  5169. }
  5170. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5171. {
  5172. uint8_t i;
  5173. for (i = 0; i < num_pool; i++)
  5174. dp_tx_desc_pool_deinit(soc, i);
  5175. }
  5176. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5177. {
  5178. uint8_t i;
  5179. for (i = 0; i < num_pool; i++)
  5180. dp_tx_desc_pool_free(soc, i);
  5181. }
  5182. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5183. /**
  5184. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5185. * @soc: core txrx main context
  5186. * @num_pool: number of pools
  5187. *
  5188. */
  5189. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5190. {
  5191. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5192. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5193. }
  5194. /**
  5195. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5196. * @soc: core txrx main context
  5197. * @num_pool: number of pools
  5198. *
  5199. */
  5200. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5201. {
  5202. dp_tx_tso_desc_pool_free(soc, num_pool);
  5203. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5204. }
  5205. /**
  5206. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5207. * @soc: core txrx main context
  5208. *
  5209. * This function frees all tx related descriptors as below
  5210. * 1. Regular TX descriptors (static pools)
  5211. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5212. * 3. TSO descriptors
  5213. *
  5214. */
  5215. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5216. {
  5217. uint8_t num_pool;
  5218. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5219. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5220. dp_tx_ext_desc_pool_free(soc, num_pool);
  5221. dp_tx_delete_static_pools(soc, num_pool);
  5222. }
  5223. /**
  5224. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5225. * @soc: core txrx main context
  5226. *
  5227. * This function de-initializes all tx related descriptors as below
  5228. * 1. Regular TX descriptors (static pools)
  5229. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5230. * 3. TSO descriptors
  5231. *
  5232. */
  5233. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5234. {
  5235. uint8_t num_pool;
  5236. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5237. dp_tx_flow_control_deinit(soc);
  5238. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5239. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5240. dp_tx_deinit_static_pools(soc, num_pool);
  5241. }
  5242. /**
  5243. * dp_tso_attach() - TSO attach handler
  5244. * @txrx_soc: Opaque Dp handle
  5245. *
  5246. * Reserve TSO descriptor buffers
  5247. *
  5248. * Return: QDF_STATUS_E_FAILURE on failure or
  5249. * QDF_STATUS_SUCCESS on success
  5250. */
  5251. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5252. uint8_t num_pool,
  5253. uint32_t num_desc)
  5254. {
  5255. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5256. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5257. return QDF_STATUS_E_FAILURE;
  5258. }
  5259. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5260. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5261. num_pool, soc);
  5262. return QDF_STATUS_E_FAILURE;
  5263. }
  5264. return QDF_STATUS_SUCCESS;
  5265. }
  5266. /**
  5267. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5268. * @soc: DP soc handle
  5269. * @num_pool: Number of pools
  5270. * @num_desc: Number of descriptors
  5271. *
  5272. * Initialize TSO descriptor pools
  5273. *
  5274. * Return: QDF_STATUS_E_FAILURE on failure or
  5275. * QDF_STATUS_SUCCESS on success
  5276. */
  5277. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5278. uint8_t num_pool,
  5279. uint32_t num_desc)
  5280. {
  5281. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5282. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5283. return QDF_STATUS_E_FAILURE;
  5284. }
  5285. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5286. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5287. num_pool, soc);
  5288. return QDF_STATUS_E_FAILURE;
  5289. }
  5290. return QDF_STATUS_SUCCESS;
  5291. }
  5292. /**
  5293. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5294. * @soc: core txrx main context
  5295. *
  5296. * This function allocates memory for following descriptor pools
  5297. * 1. regular sw tx descriptor pools (static pools)
  5298. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5299. * 3. TSO descriptor pools
  5300. *
  5301. * Return: QDF_STATUS_SUCCESS: success
  5302. * QDF_STATUS_E_RESOURCES: Error return
  5303. */
  5304. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5305. {
  5306. uint8_t num_pool;
  5307. uint32_t num_desc;
  5308. uint32_t num_ext_desc;
  5309. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5310. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5311. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5313. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5314. __func__, num_pool, num_desc);
  5315. if ((num_pool > MAX_TXDESC_POOLS) ||
  5316. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5317. goto fail1;
  5318. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5319. goto fail1;
  5320. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5321. goto fail2;
  5322. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5323. return QDF_STATUS_SUCCESS;
  5324. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5325. goto fail3;
  5326. return QDF_STATUS_SUCCESS;
  5327. fail3:
  5328. dp_tx_ext_desc_pool_free(soc, num_pool);
  5329. fail2:
  5330. dp_tx_delete_static_pools(soc, num_pool);
  5331. fail1:
  5332. return QDF_STATUS_E_RESOURCES;
  5333. }
  5334. /**
  5335. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5336. * @soc: core txrx main context
  5337. *
  5338. * This function initializes the following TX descriptor pools
  5339. * 1. regular sw tx descriptor pools (static pools)
  5340. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5341. * 3. TSO descriptor pools
  5342. *
  5343. * Return: QDF_STATUS_SUCCESS: success
  5344. * QDF_STATUS_E_RESOURCES: Error return
  5345. */
  5346. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5347. {
  5348. uint8_t num_pool;
  5349. uint32_t num_desc;
  5350. uint32_t num_ext_desc;
  5351. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5352. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5353. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5354. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5355. goto fail1;
  5356. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5357. goto fail2;
  5358. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5359. return QDF_STATUS_SUCCESS;
  5360. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5361. goto fail3;
  5362. dp_tx_flow_control_init(soc);
  5363. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5364. return QDF_STATUS_SUCCESS;
  5365. fail3:
  5366. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5367. fail2:
  5368. dp_tx_deinit_static_pools(soc, num_pool);
  5369. fail1:
  5370. return QDF_STATUS_E_RESOURCES;
  5371. }
  5372. /**
  5373. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5374. * @txrx_soc: dp soc handle
  5375. *
  5376. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5377. * QDF_STATUS_E_FAILURE
  5378. */
  5379. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5380. {
  5381. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5382. uint8_t num_pool;
  5383. uint32_t num_desc;
  5384. uint32_t num_ext_desc;
  5385. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5386. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5387. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5388. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5389. return QDF_STATUS_E_FAILURE;
  5390. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5391. return QDF_STATUS_E_FAILURE;
  5392. return QDF_STATUS_SUCCESS;
  5393. }
  5394. /**
  5395. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5396. * @txrx_soc: dp soc handle
  5397. *
  5398. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5399. */
  5400. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5401. {
  5402. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5403. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5404. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5405. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5406. return QDF_STATUS_SUCCESS;
  5407. }
  5408. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5409. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5410. enum qdf_pkt_timestamp_index index, uint64_t time,
  5411. qdf_nbuf_t nbuf)
  5412. {
  5413. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5414. uint64_t tsf_time;
  5415. if (vdev->get_tsf_time) {
  5416. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5417. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5418. }
  5419. }
  5420. }
  5421. void dp_pkt_get_timestamp(uint64_t *time)
  5422. {
  5423. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5424. *time = qdf_get_log_timestamp();
  5425. }
  5426. #endif