sde_kms.c 109 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <drm/drm_atomic_uapi.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "dp_mst_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_color_processing.h"
  45. #include "sde_reg_dma.h"
  46. #include "sde_connector.h"
  47. #include "sde_vm.h"
  48. #include <linux/qcom_scm.h>
  49. #include "soc/qcom/secure_buffer.h"
  50. #include <linux/qtee_shmbridge.h>
  51. #include <linux/haven/hh_irq_lend.h>
  52. #define CREATE_TRACE_POINTS
  53. #include "sde_trace.h"
  54. /* defines for secure channel call */
  55. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  56. #define MDP_DEVICE_ID 0x1A
  57. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  58. static const char * const iommu_ports[] = {
  59. "mdp_0",
  60. };
  61. /**
  62. * Controls size of event log buffer. Specified as a power of 2.
  63. */
  64. #define SDE_EVTLOG_SIZE 1024
  65. /*
  66. * To enable overall DRM driver logging
  67. * # echo 0x2 > /sys/module/drm/parameters/debug
  68. *
  69. * To enable DRM driver h/w logging
  70. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  71. *
  72. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  73. */
  74. #define SDE_DEBUGFS_DIR "msm_sde"
  75. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  76. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  77. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  78. /**
  79. * sdecustom - enable certain driver customizations for sde clients
  80. * Enabling this modifies the standard DRM behavior slightly and assumes
  81. * that the clients have specific knowledge about the modifications that
  82. * are involved, so don't enable this unless you know what you're doing.
  83. *
  84. * Parts of the driver that are affected by this setting may be located by
  85. * searching for invocations of the 'sde_is_custom_client()' function.
  86. *
  87. * This is disabled by default.
  88. */
  89. static bool sdecustom = true;
  90. module_param(sdecustom, bool, 0400);
  91. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  92. static int sde_kms_hw_init(struct msm_kms *kms);
  93. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  94. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  95. static int _sde_kms_register_events(struct msm_kms *kms,
  96. struct drm_mode_object *obj, u32 event, bool en);
  97. bool sde_is_custom_client(void)
  98. {
  99. return sdecustom;
  100. }
  101. #ifdef CONFIG_DEBUG_FS
  102. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  103. {
  104. struct msm_drm_private *priv;
  105. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  106. return NULL;
  107. priv = sde_kms->dev->dev_private;
  108. return priv->debug_root;
  109. }
  110. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  111. {
  112. void *p;
  113. int rc;
  114. void *debugfs_root;
  115. p = sde_hw_util_get_log_mask_ptr();
  116. if (!sde_kms || !p)
  117. return -EINVAL;
  118. debugfs_root = sde_debugfs_get_root(sde_kms);
  119. if (!debugfs_root)
  120. return -EINVAL;
  121. /* allow debugfs_root to be NULL */
  122. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  123. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  124. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  125. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  126. if (rc) {
  127. SDE_ERROR("failed to init perf %d\n", rc);
  128. return rc;
  129. }
  130. if (sde_kms->catalog->qdss_count)
  131. debugfs_create_u32("qdss", 0600, debugfs_root,
  132. (u32 *)&sde_kms->qdss_enabled);
  133. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  134. (u32 *)&sde_kms->pm_suspend_clk_dump);
  135. return 0;
  136. }
  137. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  138. {
  139. struct sde_kms *sde_kms = to_sde_kms(kms);
  140. /* don't need to NULL check debugfs_root */
  141. if (sde_kms) {
  142. sde_debugfs_vbif_destroy(sde_kms);
  143. sde_debugfs_core_irq_destroy(sde_kms);
  144. }
  145. }
  146. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  147. {
  148. int i;
  149. struct device *dev = sde_kms->dev->dev;
  150. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  151. for (i = 0; i < sde_kms->dsi_display_count; i++)
  152. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  153. return 0;
  154. }
  155. #else
  156. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  157. {
  158. return 0;
  159. }
  160. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  161. {
  162. }
  163. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  164. {
  165. return 0;
  166. }
  167. #endif
  168. static bool _sde_kms_skip_vblank_op(struct sde_kms *sde_kms)
  169. {
  170. struct sde_vm_ops *vm_ops = sde_vm_get_ops(sde_kms);
  171. if (vm_ops && vm_ops->vm_owns_hw
  172. && !vm_ops->vm_owns_hw(sde_kms))
  173. return true;
  174. return false;
  175. }
  176. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  177. {
  178. int ret = 0;
  179. struct sde_kms *sde_kms;
  180. if (!kms)
  181. return -EINVAL;
  182. sde_kms = to_sde_kms(kms);
  183. sde_vm_lock(sde_kms);
  184. if (_sde_kms_skip_vblank_op(sde_kms)) {
  185. SDE_DEBUG("skipping vblank enable due to HW unavailablity\n");
  186. goto done;
  187. }
  188. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  189. ret = sde_crtc_vblank(crtc, true);
  190. SDE_ATRACE_END("sde_kms_enable_vblank");
  191. done:
  192. sde_vm_unlock(sde_kms);
  193. return ret;
  194. }
  195. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  196. {
  197. struct sde_kms *sde_kms;
  198. if (!kms)
  199. return;
  200. sde_kms = to_sde_kms(kms);
  201. sde_vm_lock(sde_kms);
  202. if (_sde_kms_skip_vblank_op(sde_kms)) {
  203. SDE_DEBUG("skipping vblank disable due to HW unavailablity\n");
  204. goto done;
  205. }
  206. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  207. sde_crtc_vblank(crtc, false);
  208. SDE_ATRACE_END("sde_kms_disable_vblank");
  209. done:
  210. sde_vm_unlock(sde_kms);
  211. }
  212. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  213. struct drm_crtc *crtc)
  214. {
  215. struct drm_encoder *encoder;
  216. struct drm_device *dev;
  217. int ret;
  218. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  219. SDE_ERROR("invalid params\n");
  220. return;
  221. }
  222. if (!crtc->state->enable) {
  223. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  224. return;
  225. }
  226. if (!crtc->state->active) {
  227. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  228. return;
  229. }
  230. dev = crtc->dev;
  231. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  232. if (encoder->crtc != crtc)
  233. continue;
  234. /*
  235. * Video Mode - Wait for VSYNC
  236. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  237. * complete
  238. */
  239. SDE_EVT32_VERBOSE(DRMID(crtc));
  240. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  241. if (ret && ret != -EWOULDBLOCK) {
  242. SDE_ERROR(
  243. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  244. crtc->base.id, encoder->base.id, ret);
  245. break;
  246. }
  247. }
  248. }
  249. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  250. struct drm_crtc *crtc, bool enable)
  251. {
  252. struct drm_device *dev;
  253. struct msm_drm_private *priv;
  254. struct sde_mdss_cfg *sde_cfg;
  255. struct drm_plane *plane;
  256. int i, ret;
  257. dev = sde_kms->dev;
  258. priv = dev->dev_private;
  259. sde_cfg = sde_kms->catalog;
  260. ret = sde_vbif_halt_xin_mask(sde_kms,
  261. sde_cfg->sui_block_xin_mask, enable);
  262. if (ret) {
  263. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  264. return ret;
  265. }
  266. if (enable) {
  267. for (i = 0; i < priv->num_planes; i++) {
  268. plane = priv->planes[i];
  269. sde_plane_secure_ctrl_xin_client(plane, crtc);
  270. }
  271. }
  272. return 0;
  273. }
  274. /**
  275. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  276. * @sde_kms: Pointer to sde_kms struct
  277. * @vimd: switch the stage 2 translation to this VMID
  278. */
  279. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  280. {
  281. struct device dummy = {};
  282. dma_addr_t dma_handle;
  283. uint32_t num_sids;
  284. uint32_t *sec_sid;
  285. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  286. int ret = 0, i;
  287. struct qtee_shm shm;
  288. bool qtee_en = qtee_shmbridge_is_enabled();
  289. phys_addr_t mem_addr;
  290. u64 mem_size;
  291. num_sids = sde_cfg->sec_sid_mask_count;
  292. if (!num_sids) {
  293. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  294. return -EINVAL;
  295. }
  296. if (qtee_en) {
  297. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  298. &shm);
  299. if (ret)
  300. return -ENOMEM;
  301. sec_sid = (uint32_t *) shm.vaddr;
  302. mem_addr = shm.paddr;
  303. /**
  304. * SMMUSecureModeSwitch requires the size to be number of SID's
  305. * but shm allocates size in pages. Modify the args as per
  306. * client requirement.
  307. */
  308. mem_size = sizeof(uint32_t) * num_sids;
  309. } else {
  310. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  311. if (!sec_sid)
  312. return -ENOMEM;
  313. mem_addr = virt_to_phys(sec_sid);
  314. mem_size = sizeof(uint32_t) * num_sids;
  315. }
  316. for (i = 0; i < num_sids; i++) {
  317. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  318. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  319. }
  320. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  321. if (ret) {
  322. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  323. goto map_error;
  324. }
  325. set_dma_ops(&dummy, NULL);
  326. dma_handle = dma_map_single(&dummy, sec_sid,
  327. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  328. if (dma_mapping_error(&dummy, dma_handle)) {
  329. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  330. vmid);
  331. goto map_error;
  332. }
  333. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  334. vmid, num_sids, qtee_en);
  335. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  336. mem_size, vmid);
  337. if (ret)
  338. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  339. vmid, ret);
  340. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  341. vmid, qtee_en, num_sids, ret);
  342. dma_unmap_single(&dummy, dma_handle,
  343. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  344. map_error:
  345. if (qtee_en)
  346. qtee_shmbridge_free_shm(&shm);
  347. else
  348. kfree(sec_sid);
  349. return ret;
  350. }
  351. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  352. {
  353. u32 ret;
  354. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  355. return 0;
  356. /* detach_all_contexts */
  357. ret = sde_kms_mmu_detach(sde_kms, false);
  358. if (ret) {
  359. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  360. goto mmu_error;
  361. }
  362. ret = _sde_kms_scm_call(sde_kms, vmid);
  363. if (ret) {
  364. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  365. goto scm_error;
  366. }
  367. return 0;
  368. scm_error:
  369. sde_kms_mmu_attach(sde_kms, false);
  370. mmu_error:
  371. atomic_dec(&sde_kms->detach_all_cb);
  372. return ret;
  373. }
  374. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  375. u32 old_vmid)
  376. {
  377. u32 ret;
  378. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  379. return 0;
  380. ret = _sde_kms_scm_call(sde_kms, vmid);
  381. if (ret) {
  382. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  383. goto scm_error;
  384. }
  385. /* attach_all_contexts */
  386. ret = sde_kms_mmu_attach(sde_kms, false);
  387. if (ret) {
  388. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  389. goto mmu_error;
  390. }
  391. return 0;
  392. mmu_error:
  393. _sde_kms_scm_call(sde_kms, old_vmid);
  394. scm_error:
  395. atomic_inc(&sde_kms->detach_all_cb);
  396. return ret;
  397. }
  398. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  399. {
  400. u32 ret;
  401. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  402. return 0;
  403. /* detach secure_context */
  404. ret = sde_kms_mmu_detach(sde_kms, true);
  405. if (ret) {
  406. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  407. goto mmu_error;
  408. }
  409. ret = _sde_kms_scm_call(sde_kms, vmid);
  410. if (ret) {
  411. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  412. goto scm_error;
  413. }
  414. return 0;
  415. scm_error:
  416. sde_kms_mmu_attach(sde_kms, true);
  417. mmu_error:
  418. atomic_dec(&sde_kms->detach_sec_cb);
  419. return ret;
  420. }
  421. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  422. u32 old_vmid)
  423. {
  424. u32 ret;
  425. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  426. return 0;
  427. ret = _sde_kms_scm_call(sde_kms, vmid);
  428. if (ret) {
  429. goto scm_error;
  430. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  431. }
  432. ret = sde_kms_mmu_attach(sde_kms, true);
  433. if (ret) {
  434. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  435. goto mmu_error;
  436. }
  437. return 0;
  438. mmu_error:
  439. _sde_kms_scm_call(sde_kms, old_vmid);
  440. scm_error:
  441. atomic_inc(&sde_kms->detach_sec_cb);
  442. return ret;
  443. }
  444. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  445. struct drm_crtc *crtc, bool enable)
  446. {
  447. int ret;
  448. if (enable) {
  449. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  450. if (ret < 0) {
  451. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  452. return ret;
  453. }
  454. sde_crtc_misr_setup(crtc, true, 1);
  455. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  456. if (ret) {
  457. sde_crtc_misr_setup(crtc, false, 0);
  458. pm_runtime_put_sync(sde_kms->dev->dev);
  459. return ret;
  460. }
  461. } else {
  462. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  463. sde_crtc_misr_setup(crtc, false, 0);
  464. pm_runtime_put_sync(sde_kms->dev->dev);
  465. }
  466. return 0;
  467. }
  468. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  469. bool post_commit)
  470. {
  471. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  472. int old_smmu_state = smmu_state->state;
  473. int ret = 0;
  474. u32 vmid;
  475. if (!sde_kms || !crtc) {
  476. SDE_ERROR("invalid argument(s)\n");
  477. return -EINVAL;
  478. }
  479. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  480. post_commit, smmu_state->sui_misr_state,
  481. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  482. if ((!smmu_state->transition_type) ||
  483. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  484. /* Bail out */
  485. return 0;
  486. /* enable sui misr if requested, before the transition */
  487. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  488. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  489. if (ret) {
  490. smmu_state->sui_misr_state = NONE;
  491. goto end;
  492. }
  493. }
  494. mutex_lock(&sde_kms->secure_transition_lock);
  495. switch (smmu_state->state) {
  496. case DETACH_ALL_REQ:
  497. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  498. if (!ret)
  499. smmu_state->state = DETACHED;
  500. break;
  501. case ATTACH_ALL_REQ:
  502. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  503. VMID_CP_SEC_DISPLAY);
  504. if (!ret) {
  505. smmu_state->state = ATTACHED;
  506. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  507. }
  508. break;
  509. case DETACH_SEC_REQ:
  510. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  511. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  512. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  513. if (!ret)
  514. smmu_state->state = DETACHED_SEC;
  515. break;
  516. case ATTACH_SEC_REQ:
  517. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  518. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  519. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  520. if (!ret) {
  521. smmu_state->state = ATTACHED;
  522. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  523. }
  524. break;
  525. default:
  526. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  527. DRMID(crtc), smmu_state->state,
  528. smmu_state->transition_type);
  529. ret = -EINVAL;
  530. break;
  531. }
  532. mutex_unlock(&sde_kms->secure_transition_lock);
  533. /* disable sui misr if requested, after the transition */
  534. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  535. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  536. if (ret)
  537. goto end;
  538. }
  539. end:
  540. smmu_state->transition_error = false;
  541. if (ret) {
  542. smmu_state->transition_error = true;
  543. SDE_ERROR(
  544. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  545. DRMID(crtc), old_smmu_state, smmu_state->state,
  546. smmu_state->secure_level, ret);
  547. smmu_state->state = smmu_state->prev_state;
  548. smmu_state->secure_level = smmu_state->prev_secure_level;
  549. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  550. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  551. }
  552. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  553. DRMID(crtc), old_smmu_state, smmu_state->state,
  554. smmu_state->secure_level, ret);
  555. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  556. smmu_state->transition_type,
  557. smmu_state->transition_error,
  558. smmu_state->secure_level, smmu_state->prev_secure_level,
  559. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  560. smmu_state->sui_misr_state = NONE;
  561. smmu_state->transition_type = NONE;
  562. return ret;
  563. }
  564. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  565. struct drm_atomic_state *state)
  566. {
  567. struct drm_crtc *crtc;
  568. struct drm_crtc_state *old_crtc_state;
  569. struct drm_plane_state *old_plane_state, *new_plane_state;
  570. struct drm_plane *plane;
  571. struct drm_plane_state *plane_state;
  572. struct sde_kms *sde_kms = to_sde_kms(kms);
  573. struct drm_device *dev = sde_kms->dev;
  574. int i, ops = 0, ret = 0;
  575. bool old_valid_fb = false;
  576. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  577. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  578. if (!crtc->state || !crtc->state->active)
  579. continue;
  580. /*
  581. * It is safe to assume only one active crtc,
  582. * and compatible translation modes on the
  583. * planes staged on this crtc.
  584. * otherwise validation would have failed.
  585. * For this CRTC,
  586. */
  587. /*
  588. * 1. Check if old state on the CRTC has planes
  589. * staged with valid fbs
  590. */
  591. for_each_old_plane_in_state(state, plane, plane_state, i) {
  592. if (!plane_state->crtc)
  593. continue;
  594. if (plane_state->fb) {
  595. old_valid_fb = true;
  596. break;
  597. }
  598. }
  599. /*
  600. * 2.Get the operations needed to be performed before
  601. * secure transition can be initiated.
  602. */
  603. ops = sde_crtc_get_secure_transition_ops(crtc,
  604. old_crtc_state, old_valid_fb);
  605. if (ops < 0) {
  606. SDE_ERROR("invalid secure operations %x\n", ops);
  607. return ops;
  608. }
  609. if (!ops) {
  610. smmu_state->transition_error = false;
  611. goto no_ops;
  612. }
  613. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  614. crtc->base.id, ops, crtc->state);
  615. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  616. /* 3. Perform operations needed for secure transition */
  617. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  618. SDE_DEBUG("wait_for_transfer_done\n");
  619. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  620. }
  621. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  622. SDE_DEBUG("cleanup planes\n");
  623. drm_atomic_helper_cleanup_planes(dev, state);
  624. for_each_oldnew_plane_in_state(state, plane,
  625. old_plane_state, new_plane_state, i)
  626. sde_plane_destroy_fb(old_plane_state);
  627. }
  628. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  629. SDE_DEBUG("secure ctrl\n");
  630. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  631. }
  632. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  633. SDE_DEBUG("prepare planes %d",
  634. crtc->state->plane_mask);
  635. drm_atomic_crtc_for_each_plane(plane,
  636. crtc) {
  637. const struct drm_plane_helper_funcs *funcs;
  638. plane_state = plane->state;
  639. funcs = plane->helper_private;
  640. SDE_DEBUG("psde:%d FB[%u]\n",
  641. plane->base.id,
  642. plane->fb->base.id);
  643. if (!funcs)
  644. continue;
  645. if (funcs->prepare_fb(plane, plane_state)) {
  646. ret = funcs->prepare_fb(plane,
  647. plane_state);
  648. if (ret)
  649. return ret;
  650. }
  651. }
  652. }
  653. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  654. SDE_DEBUG("secure operations completed\n");
  655. }
  656. no_ops:
  657. return 0;
  658. }
  659. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  660. unsigned int splash_buffer_size,
  661. unsigned int ramdump_base,
  662. unsigned int ramdump_buffer_size)
  663. {
  664. unsigned long pfn_start, pfn_end, pfn_idx;
  665. int ret = 0;
  666. if (!mem_addr || !splash_buffer_size) {
  667. SDE_ERROR("invalid params\n");
  668. return -EINVAL;
  669. }
  670. /* leave ramdump memory only if base address matches */
  671. if (ramdump_base == mem_addr &&
  672. ramdump_buffer_size <= splash_buffer_size) {
  673. mem_addr += ramdump_buffer_size;
  674. splash_buffer_size -= ramdump_buffer_size;
  675. }
  676. pfn_start = mem_addr >> PAGE_SHIFT;
  677. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  678. if (ret) {
  679. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  680. return ret;
  681. }
  682. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  683. free_reserved_page(pfn_to_page(pfn_idx));
  684. return ret;
  685. }
  686. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  687. struct sde_splash_mem *splash)
  688. {
  689. struct msm_mmu *mmu = NULL;
  690. int ret = 0;
  691. if (!sde_kms->aspace[0]) {
  692. SDE_ERROR("aspace not found for sde kms node\n");
  693. return -EINVAL;
  694. }
  695. mmu = sde_kms->aspace[0]->mmu;
  696. if (!mmu) {
  697. SDE_ERROR("mmu not found for aspace\n");
  698. return -EINVAL;
  699. }
  700. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  701. SDE_ERROR("invalid input params for map\n");
  702. return -EINVAL;
  703. }
  704. if (!splash->ref_cnt) {
  705. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  706. splash->splash_buf_base,
  707. splash->splash_buf_size,
  708. IOMMU_READ | IOMMU_NOEXEC);
  709. if (ret)
  710. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  711. }
  712. splash->ref_cnt++;
  713. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  714. splash->splash_buf_base,
  715. splash->splash_buf_size,
  716. splash->ref_cnt);
  717. return ret;
  718. }
  719. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  720. {
  721. int i = 0;
  722. int ret = 0;
  723. if (!sde_kms)
  724. return -EINVAL;
  725. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  726. ret = _sde_kms_splash_mem_get(sde_kms,
  727. sde_kms->splash_data.splash_display[i].splash);
  728. if (ret)
  729. return ret;
  730. }
  731. return ret;
  732. }
  733. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  734. struct sde_splash_mem *splash)
  735. {
  736. struct msm_mmu *mmu = NULL;
  737. int rc = 0;
  738. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  739. SDE_ERROR("invalid params\n");
  740. return -EINVAL;
  741. }
  742. mmu = sde_kms->aspace[0]->mmu;
  743. if (!splash || !splash->ref_cnt ||
  744. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  745. return -EINVAL;
  746. splash->ref_cnt--;
  747. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  748. splash->splash_buf_base, splash->ref_cnt);
  749. if (!splash->ref_cnt) {
  750. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  751. splash->splash_buf_size);
  752. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  753. splash->splash_buf_size, splash->ramdump_base,
  754. splash->ramdump_size);
  755. splash->splash_buf_base = 0;
  756. splash->splash_buf_size = 0;
  757. }
  758. return rc;
  759. }
  760. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  761. {
  762. int i = 0;
  763. int ret = 0;
  764. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  765. return -EINVAL;
  766. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  767. ret = _sde_kms_splash_mem_put(sde_kms,
  768. sde_kms->splash_data.splash_display[i].splash);
  769. if (ret)
  770. return ret;
  771. }
  772. return ret;
  773. }
  774. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  775. struct drm_atomic_state *state)
  776. {
  777. struct drm_device *ddev;
  778. struct drm_crtc *crtc;
  779. struct drm_encoder *encoder;
  780. struct drm_connector *connector;
  781. struct sde_vm_ops *vm_ops;
  782. struct sde_crtc_state *cstate;
  783. enum sde_crtc_vm_req vm_req;
  784. int rc = 0;
  785. ddev = sde_kms->dev;
  786. vm_ops = sde_vm_get_ops(sde_kms);
  787. if (!vm_ops)
  788. return -EINVAL;
  789. crtc = state->crtcs[0].ptr;
  790. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  791. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  792. if (vm_req != VM_REQ_ACQUIRE)
  793. return 0;
  794. /* enable MDSS irq line */
  795. sde_irq_update(&sde_kms->base, true);
  796. /* clear the stale IRQ status bits */
  797. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  798. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  799. /* enable the display path IRQ's */
  800. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  801. sde_encoder_irq_control(encoder, true);
  802. /* Schedule ESD work */
  803. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  804. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  805. sde_connector_schedule_status_work(connector, true);
  806. /* handle non-SDE pre_acquire */
  807. if (vm_ops->vm_client_post_acquire)
  808. rc = vm_ops->vm_client_post_acquire(sde_kms);
  809. return rc;
  810. }
  811. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  812. struct drm_atomic_state *state)
  813. {
  814. struct drm_device *ddev;
  815. struct drm_plane *plane;
  816. struct sde_crtc_state *cstate;
  817. enum sde_crtc_vm_req vm_req;
  818. ddev = sde_kms->dev;
  819. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  820. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  821. if (vm_req != VM_REQ_ACQUIRE)
  822. return 0;
  823. /* Clear the stale IRQ status bits */
  824. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  825. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  826. /* Program the SID's for the trusted VM */
  827. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  828. sde_plane_set_sid(plane, 1);
  829. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  830. return 0;
  831. }
  832. static void sde_kms_prepare_commit(struct msm_kms *kms,
  833. struct drm_atomic_state *state)
  834. {
  835. struct sde_kms *sde_kms;
  836. struct msm_drm_private *priv;
  837. struct drm_device *dev;
  838. struct drm_encoder *encoder;
  839. struct drm_crtc *crtc;
  840. struct drm_crtc_state *crtc_state;
  841. struct sde_vm_ops *vm_ops;
  842. int i, rc;
  843. if (!kms)
  844. return;
  845. sde_kms = to_sde_kms(kms);
  846. dev = sde_kms->dev;
  847. if (!dev || !dev->dev_private)
  848. return;
  849. priv = dev->dev_private;
  850. SDE_ATRACE_BEGIN("prepare_commit");
  851. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  852. if (rc < 0) {
  853. SDE_ERROR("failed to enable power resources %d\n", rc);
  854. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  855. goto end;
  856. }
  857. if (sde_kms->first_kickoff) {
  858. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  859. sde_kms->first_kickoff = false;
  860. }
  861. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  862. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  863. head) {
  864. if (encoder->crtc != crtc)
  865. continue;
  866. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  867. SDE_ERROR("crtc:%d, initiating hw reset\n",
  868. DRMID(crtc));
  869. sde_encoder_needs_hw_reset(encoder);
  870. sde_crtc_set_needs_hw_reset(crtc);
  871. }
  872. }
  873. }
  874. /*
  875. * NOTE: for secure use cases we want to apply the new HW
  876. * configuration only after completing preparation for secure
  877. * transitions prepare below if any transtions is required.
  878. */
  879. sde_kms_prepare_secure_transition(kms, state);
  880. vm_ops = sde_vm_get_ops(sde_kms);
  881. if (!vm_ops)
  882. goto end;
  883. if (vm_ops->vm_prepare_commit)
  884. vm_ops->vm_prepare_commit(sde_kms, state);
  885. end:
  886. SDE_ATRACE_END("prepare_commit");
  887. }
  888. static void sde_kms_commit(struct msm_kms *kms,
  889. struct drm_atomic_state *old_state)
  890. {
  891. struct sde_kms *sde_kms;
  892. struct drm_crtc *crtc;
  893. struct drm_crtc_state *old_crtc_state;
  894. int i;
  895. if (!kms || !old_state)
  896. return;
  897. sde_kms = to_sde_kms(kms);
  898. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  899. SDE_ERROR("power resource is not enabled\n");
  900. return;
  901. }
  902. SDE_ATRACE_BEGIN("sde_kms_commit");
  903. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  904. if (crtc->state->active) {
  905. SDE_EVT32(DRMID(crtc));
  906. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  907. }
  908. }
  909. SDE_ATRACE_END("sde_kms_commit");
  910. }
  911. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  912. struct sde_splash_display *splash_display)
  913. {
  914. if (!sde_kms || !splash_display ||
  915. !sde_kms->splash_data.num_splash_displays)
  916. return;
  917. if (sde_kms->splash_data.num_splash_regions)
  918. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  919. sde_kms->splash_data.num_splash_displays--;
  920. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  921. sde_kms->splash_data.num_splash_displays);
  922. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  923. }
  924. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  925. struct drm_crtc *crtc)
  926. {
  927. struct msm_drm_private *priv;
  928. struct sde_splash_display *splash_display;
  929. int i;
  930. if (!sde_kms || !crtc)
  931. return;
  932. priv = sde_kms->dev->dev_private;
  933. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  934. return;
  935. SDE_EVT32(DRMID(crtc), crtc->state->active,
  936. sde_kms->splash_data.num_splash_displays);
  937. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  938. splash_display = &sde_kms->splash_data.splash_display[i];
  939. if (splash_display->encoder &&
  940. crtc == splash_display->encoder->crtc)
  941. break;
  942. }
  943. if (i >= MAX_DSI_DISPLAYS)
  944. return;
  945. if (splash_display->cont_splash_enabled) {
  946. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  947. splash_display, false);
  948. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  949. }
  950. /* remove the votes if all displays are done with splash */
  951. if (!sde_kms->splash_data.num_splash_displays) {
  952. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  953. sde_power_data_bus_set_quota(&priv->phandle, i,
  954. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  955. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  956. pm_runtime_put_sync(sde_kms->dev->dev);
  957. }
  958. }
  959. void _sde_kms_program_mode_info(struct sde_kms *sde_kms)
  960. {
  961. struct drm_encoder *encoder;
  962. struct drm_crtc *crtc;
  963. struct drm_connector *connector;
  964. struct drm_connector_list_iter conn_iter;
  965. struct dsi_display *dsi_display;
  966. struct drm_display_mode *drm_mode;
  967. int i;
  968. struct drm_device *dev;
  969. u32 mode_index = 0;
  970. if (!sde_kms->dev || !sde_kms->hw_mdp)
  971. return;
  972. dev = sde_kms->dev;
  973. sde_kms->hw_mdp->ops.clear_mode_index(sde_kms->hw_mdp);
  974. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  975. dsi_display = (struct dsi_display *)sde_kms->dsi_displays[i];
  976. if (dsi_display->bridge->base.encoder) {
  977. encoder = dsi_display->bridge->base.encoder;
  978. crtc = encoder->crtc;
  979. if (!crtc->state->active)
  980. continue;
  981. mutex_lock(&dev->mode_config.mutex);
  982. drm_connector_list_iter_begin(dev, &conn_iter);
  983. drm_for_each_connector_iter(connector, &conn_iter) {
  984. if (connector->encoder_ids[0]
  985. == encoder->base.id)
  986. break;
  987. }
  988. drm_connector_list_iter_end(&conn_iter);
  989. mutex_unlock(&dev->mode_config.mutex);
  990. list_for_each_entry(drm_mode, &connector->modes, head) {
  991. if (drm_mode_equal(
  992. &crtc->state->mode, drm_mode))
  993. break;
  994. mode_index++;
  995. }
  996. sde_kms->hw_mdp->ops.set_mode_index(
  997. sde_kms->hw_mdp, i, mode_index);
  998. SDE_DEBUG("crtc:%d, display_idx:%d, mode_index:%d\n",
  999. DRMID(crtc), i, mode_index);
  1000. }
  1001. }
  1002. }
  1003. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1004. struct drm_atomic_state *state)
  1005. {
  1006. struct sde_vm_ops *vm_ops;
  1007. struct drm_device *ddev;
  1008. struct drm_crtc *crtc;
  1009. struct drm_plane *plane;
  1010. struct drm_encoder *encoder;
  1011. struct sde_crtc_state *cstate;
  1012. struct drm_crtc_state *new_cstate;
  1013. enum sde_crtc_vm_req vm_req;
  1014. int rc = 0;
  1015. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1016. return -EINVAL;
  1017. vm_ops = sde_vm_get_ops(sde_kms);
  1018. ddev = sde_kms->dev;
  1019. crtc = state->crtcs[0].ptr;
  1020. new_cstate = state->crtcs[0].new_state;
  1021. cstate = to_sde_crtc_state(new_cstate);
  1022. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1023. if (vm_req != VM_REQ_RELEASE)
  1024. return rc;
  1025. if (!new_cstate->active && !new_cstate->active_changed)
  1026. return rc;
  1027. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1028. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1029. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1030. sde_encoder_irq_control(encoder, false);
  1031. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1032. sde_plane_set_sid(plane, 0);
  1033. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1034. sde_kms_vm_trusted_resource_deinit(sde_kms);
  1035. if (vm_ops->vm_release)
  1036. rc = vm_ops->vm_release(sde_kms);
  1037. return rc;
  1038. }
  1039. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1040. struct drm_atomic_state *state)
  1041. {
  1042. struct drm_device *ddev;
  1043. struct drm_crtc *crtc;
  1044. struct drm_encoder *encoder;
  1045. struct drm_connector *connector;
  1046. int rc = 0;
  1047. ddev = sde_kms->dev;
  1048. crtc = state->crtcs[0].ptr;
  1049. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1050. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1051. /* disable ESD work */
  1052. list_for_each_entry(connector,
  1053. &ddev->mode_config.connector_list, head) {
  1054. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1055. sde_connector_schedule_status_work(connector, false);
  1056. }
  1057. /* disable SDE irq's */
  1058. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1059. sde_encoder_irq_control(encoder, false);
  1060. /* disable IRQ line */
  1061. sde_irq_update(&sde_kms->base, false);
  1062. return rc;
  1063. }
  1064. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1065. struct drm_atomic_state *state)
  1066. {
  1067. struct sde_vm_ops *vm_ops;
  1068. struct sde_crtc_state *cstate;
  1069. struct drm_crtc *crtc;
  1070. enum sde_crtc_vm_req vm_req;
  1071. int rc = 0;
  1072. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1073. return -EINVAL;
  1074. vm_ops = sde_vm_get_ops(sde_kms);
  1075. crtc = state->crtcs[0].ptr;
  1076. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1077. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1078. if (vm_req != VM_REQ_RELEASE)
  1079. goto exit;
  1080. /* handle SDE pre-release */
  1081. sde_kms_vm_pre_release(sde_kms, state);
  1082. /* properly handoff color processing features */
  1083. sde_cp_crtc_vm_primary_handoff(crtc);
  1084. /* program the current drm mode info to scratch reg */
  1085. _sde_kms_program_mode_info(sde_kms);
  1086. /* handle non-SDE clients pre-release */
  1087. if (vm_ops->vm_client_pre_release) {
  1088. rc = vm_ops->vm_client_pre_release(sde_kms);
  1089. if (rc) {
  1090. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1091. goto exit;
  1092. }
  1093. }
  1094. /* release HW */
  1095. if (vm_ops->vm_release) {
  1096. rc = vm_ops->vm_release(sde_kms);
  1097. if (rc)
  1098. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1099. }
  1100. exit:
  1101. return rc;
  1102. }
  1103. static void sde_kms_complete_commit(struct msm_kms *kms,
  1104. struct drm_atomic_state *old_state)
  1105. {
  1106. struct sde_kms *sde_kms;
  1107. struct msm_drm_private *priv;
  1108. struct drm_crtc *crtc;
  1109. struct drm_crtc_state *old_crtc_state;
  1110. struct drm_connector *connector;
  1111. struct drm_connector_state *old_conn_state;
  1112. struct msm_display_conn_params params;
  1113. struct sde_vm_ops *vm_ops;
  1114. int i, rc = 0;
  1115. if (!kms || !old_state)
  1116. return;
  1117. sde_kms = to_sde_kms(kms);
  1118. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1119. return;
  1120. priv = sde_kms->dev->dev_private;
  1121. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1122. SDE_ERROR("power resource is not enabled\n");
  1123. return;
  1124. }
  1125. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1126. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1127. sde_crtc_complete_commit(crtc, old_crtc_state);
  1128. /* complete secure transitions if any */
  1129. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1130. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1131. }
  1132. for_each_old_connector_in_state(old_state, connector,
  1133. old_conn_state, i) {
  1134. struct sde_connector *c_conn;
  1135. c_conn = to_sde_connector(connector);
  1136. if (!c_conn->ops.post_kickoff)
  1137. continue;
  1138. memset(&params, 0, sizeof(params));
  1139. sde_connector_complete_qsync_commit(connector, &params);
  1140. rc = c_conn->ops.post_kickoff(connector, &params);
  1141. if (rc) {
  1142. pr_err("Connector Post kickoff failed rc=%d\n",
  1143. rc);
  1144. }
  1145. }
  1146. vm_ops = sde_vm_get_ops(sde_kms);
  1147. if (vm_ops && vm_ops->vm_post_commit) {
  1148. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1149. if (rc)
  1150. SDE_ERROR("vm post commit failed, rc = %d\n",
  1151. rc);
  1152. }
  1153. pm_runtime_put_sync(sde_kms->dev->dev);
  1154. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1155. _sde_kms_release_splash_resource(sde_kms, crtc);
  1156. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1157. SDE_ATRACE_END("sde_kms_complete_commit");
  1158. }
  1159. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1160. struct drm_crtc *crtc)
  1161. {
  1162. struct drm_encoder *encoder;
  1163. struct drm_device *dev;
  1164. int ret;
  1165. if (!kms || !crtc || !crtc->state) {
  1166. SDE_ERROR("invalid params\n");
  1167. return;
  1168. }
  1169. dev = crtc->dev;
  1170. if (!crtc->state->enable) {
  1171. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1172. return;
  1173. }
  1174. if (!crtc->state->active) {
  1175. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1176. return;
  1177. }
  1178. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1179. SDE_ERROR("power resource is not enabled\n");
  1180. return;
  1181. }
  1182. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1183. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1184. if (encoder->crtc != crtc)
  1185. continue;
  1186. /*
  1187. * Wait for post-flush if necessary to delay before
  1188. * plane_cleanup. For example, wait for vsync in case of video
  1189. * mode panels. This may be a no-op for command mode panels.
  1190. */
  1191. SDE_EVT32_VERBOSE(DRMID(crtc));
  1192. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1193. if (ret && ret != -EWOULDBLOCK) {
  1194. SDE_ERROR("wait for commit done returned %d\n", ret);
  1195. sde_crtc_request_frame_reset(crtc);
  1196. break;
  1197. }
  1198. sde_crtc_complete_flip(crtc, NULL);
  1199. }
  1200. sde_crtc_static_cache_read_kickoff(crtc);
  1201. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1202. }
  1203. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1204. struct drm_atomic_state *old_state)
  1205. {
  1206. struct drm_crtc *crtc;
  1207. struct drm_crtc_state *old_crtc_state;
  1208. int i, rc;
  1209. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1210. SDE_ERROR("invalid argument(s)\n");
  1211. return;
  1212. }
  1213. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1214. retry:
  1215. /* attempt to acquire ww mutex for connection */
  1216. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1217. old_state->acquire_ctx);
  1218. if (rc == -EDEADLK) {
  1219. drm_modeset_backoff(old_state->acquire_ctx);
  1220. goto retry;
  1221. }
  1222. /* old_state actually contains updated crtc pointers */
  1223. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1224. if (crtc->state->active || crtc->state->active_changed)
  1225. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1226. }
  1227. SDE_ATRACE_END("sde_kms_prepare_fence");
  1228. }
  1229. /**
  1230. * _sde_kms_get_displays - query for underlying display handles and cache them
  1231. * @sde_kms: Pointer to sde kms structure
  1232. * Returns: Zero on success
  1233. */
  1234. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1235. {
  1236. int rc = -ENOMEM;
  1237. if (!sde_kms) {
  1238. SDE_ERROR("invalid sde kms\n");
  1239. return -EINVAL;
  1240. }
  1241. /* dsi */
  1242. sde_kms->dsi_displays = NULL;
  1243. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1244. if (sde_kms->dsi_display_count) {
  1245. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1246. sizeof(void *),
  1247. GFP_KERNEL);
  1248. if (!sde_kms->dsi_displays) {
  1249. SDE_ERROR("failed to allocate dsi displays\n");
  1250. goto exit_deinit_dsi;
  1251. }
  1252. sde_kms->dsi_display_count =
  1253. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1254. sde_kms->dsi_display_count);
  1255. }
  1256. /* wb */
  1257. sde_kms->wb_displays = NULL;
  1258. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1259. if (sde_kms->wb_display_count) {
  1260. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1261. sizeof(void *),
  1262. GFP_KERNEL);
  1263. if (!sde_kms->wb_displays) {
  1264. SDE_ERROR("failed to allocate wb displays\n");
  1265. goto exit_deinit_wb;
  1266. }
  1267. sde_kms->wb_display_count =
  1268. wb_display_get_displays(sde_kms->wb_displays,
  1269. sde_kms->wb_display_count);
  1270. }
  1271. /* dp */
  1272. sde_kms->dp_displays = NULL;
  1273. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1274. if (sde_kms->dp_display_count) {
  1275. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1276. sizeof(void *), GFP_KERNEL);
  1277. if (!sde_kms->dp_displays) {
  1278. SDE_ERROR("failed to allocate dp displays\n");
  1279. goto exit_deinit_dp;
  1280. }
  1281. sde_kms->dp_display_count =
  1282. dp_display_get_displays(sde_kms->dp_displays,
  1283. sde_kms->dp_display_count);
  1284. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1285. }
  1286. return 0;
  1287. exit_deinit_dp:
  1288. kfree(sde_kms->dp_displays);
  1289. sde_kms->dp_stream_count = 0;
  1290. sde_kms->dp_display_count = 0;
  1291. sde_kms->dp_displays = NULL;
  1292. exit_deinit_wb:
  1293. kfree(sde_kms->wb_displays);
  1294. sde_kms->wb_display_count = 0;
  1295. sde_kms->wb_displays = NULL;
  1296. exit_deinit_dsi:
  1297. kfree(sde_kms->dsi_displays);
  1298. sde_kms->dsi_display_count = 0;
  1299. sde_kms->dsi_displays = NULL;
  1300. return rc;
  1301. }
  1302. /**
  1303. * _sde_kms_release_displays - release cache of underlying display handles
  1304. * @sde_kms: Pointer to sde kms structure
  1305. */
  1306. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1307. {
  1308. if (!sde_kms) {
  1309. SDE_ERROR("invalid sde kms\n");
  1310. return;
  1311. }
  1312. kfree(sde_kms->wb_displays);
  1313. sde_kms->wb_displays = NULL;
  1314. sde_kms->wb_display_count = 0;
  1315. kfree(sde_kms->dsi_displays);
  1316. sde_kms->dsi_displays = NULL;
  1317. sde_kms->dsi_display_count = 0;
  1318. }
  1319. /**
  1320. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1321. * for underlying displays
  1322. * @dev: Pointer to drm device structure
  1323. * @priv: Pointer to private drm device data
  1324. * @sde_kms: Pointer to sde kms structure
  1325. * Returns: Zero on success
  1326. */
  1327. static int _sde_kms_setup_displays(struct drm_device *dev,
  1328. struct msm_drm_private *priv,
  1329. struct sde_kms *sde_kms)
  1330. {
  1331. static const struct sde_connector_ops dsi_ops = {
  1332. .set_info_blob = dsi_conn_set_info_blob,
  1333. .detect = dsi_conn_detect,
  1334. .get_modes = dsi_connector_get_modes,
  1335. .pre_destroy = dsi_connector_put_modes,
  1336. .mode_valid = dsi_conn_mode_valid,
  1337. .get_info = dsi_display_get_info,
  1338. .set_backlight = dsi_display_set_backlight,
  1339. .soft_reset = dsi_display_soft_reset,
  1340. .pre_kickoff = dsi_conn_pre_kickoff,
  1341. .clk_ctrl = dsi_display_clk_ctrl,
  1342. .set_power = dsi_display_set_power,
  1343. .get_mode_info = dsi_conn_get_mode_info,
  1344. .get_dst_format = dsi_display_get_dst_format,
  1345. .post_kickoff = dsi_conn_post_kickoff,
  1346. .check_status = dsi_display_check_status,
  1347. .enable_event = dsi_conn_enable_event,
  1348. .cmd_transfer = dsi_display_cmd_transfer,
  1349. .cont_splash_config = dsi_display_cont_splash_config,
  1350. .get_panel_vfp = dsi_display_get_panel_vfp,
  1351. .get_default_lms = dsi_display_get_default_lms,
  1352. .cmd_receive = dsi_display_cmd_receive,
  1353. .install_properties = NULL,
  1354. };
  1355. static const struct sde_connector_ops wb_ops = {
  1356. .post_init = sde_wb_connector_post_init,
  1357. .set_info_blob = sde_wb_connector_set_info_blob,
  1358. .detect = sde_wb_connector_detect,
  1359. .get_modes = sde_wb_connector_get_modes,
  1360. .set_property = sde_wb_connector_set_property,
  1361. .get_info = sde_wb_get_info,
  1362. .soft_reset = NULL,
  1363. .get_mode_info = sde_wb_get_mode_info,
  1364. .get_dst_format = NULL,
  1365. .check_status = NULL,
  1366. .cmd_transfer = NULL,
  1367. .cont_splash_config = NULL,
  1368. .get_panel_vfp = NULL,
  1369. .cmd_receive = NULL,
  1370. .install_properties = NULL,
  1371. };
  1372. static const struct sde_connector_ops dp_ops = {
  1373. .post_init = dp_connector_post_init,
  1374. .detect = dp_connector_detect,
  1375. .get_modes = dp_connector_get_modes,
  1376. .atomic_check = dp_connector_atomic_check,
  1377. .mode_valid = dp_connector_mode_valid,
  1378. .get_info = dp_connector_get_info,
  1379. .get_mode_info = dp_connector_get_mode_info,
  1380. .post_open = dp_connector_post_open,
  1381. .check_status = NULL,
  1382. .set_colorspace = dp_connector_set_colorspace,
  1383. .config_hdr = dp_connector_config_hdr,
  1384. .cmd_transfer = NULL,
  1385. .cont_splash_config = NULL,
  1386. .get_panel_vfp = NULL,
  1387. .update_pps = dp_connector_update_pps,
  1388. .cmd_receive = NULL,
  1389. .install_properties = dp_connector_install_properties,
  1390. };
  1391. struct msm_display_info info;
  1392. struct drm_encoder *encoder;
  1393. void *display, *connector;
  1394. int i, max_encoders;
  1395. int rc = 0;
  1396. u32 dsc_count = 0, mixer_count = 0;
  1397. u32 max_dp_dsc_count, max_dp_mixer_count;
  1398. if (!dev || !priv || !sde_kms) {
  1399. SDE_ERROR("invalid argument(s)\n");
  1400. return -EINVAL;
  1401. }
  1402. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1403. sde_kms->dp_display_count +
  1404. sde_kms->dp_stream_count;
  1405. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1406. max_encoders = ARRAY_SIZE(priv->encoders);
  1407. SDE_ERROR("capping number of displays to %d", max_encoders);
  1408. }
  1409. /* wb */
  1410. for (i = 0; i < sde_kms->wb_display_count &&
  1411. priv->num_encoders < max_encoders; ++i) {
  1412. display = sde_kms->wb_displays[i];
  1413. encoder = NULL;
  1414. memset(&info, 0x0, sizeof(info));
  1415. rc = sde_wb_get_info(NULL, &info, display);
  1416. if (rc) {
  1417. SDE_ERROR("wb get_info %d failed\n", i);
  1418. continue;
  1419. }
  1420. encoder = sde_encoder_init(dev, &info);
  1421. if (IS_ERR_OR_NULL(encoder)) {
  1422. SDE_ERROR("encoder init failed for wb %d\n", i);
  1423. continue;
  1424. }
  1425. rc = sde_wb_drm_init(display, encoder);
  1426. if (rc) {
  1427. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1428. sde_encoder_destroy(encoder);
  1429. continue;
  1430. }
  1431. connector = sde_connector_init(dev,
  1432. encoder,
  1433. 0,
  1434. display,
  1435. &wb_ops,
  1436. DRM_CONNECTOR_POLL_HPD,
  1437. DRM_MODE_CONNECTOR_VIRTUAL);
  1438. if (connector) {
  1439. priv->encoders[priv->num_encoders++] = encoder;
  1440. priv->connectors[priv->num_connectors++] = connector;
  1441. } else {
  1442. SDE_ERROR("wb %d connector init failed\n", i);
  1443. sde_wb_drm_deinit(display);
  1444. sde_encoder_destroy(encoder);
  1445. }
  1446. }
  1447. /* dsi */
  1448. for (i = 0; i < sde_kms->dsi_display_count &&
  1449. priv->num_encoders < max_encoders; ++i) {
  1450. display = sde_kms->dsi_displays[i];
  1451. encoder = NULL;
  1452. memset(&info, 0x0, sizeof(info));
  1453. rc = dsi_display_get_info(NULL, &info, display);
  1454. if (rc) {
  1455. SDE_ERROR("dsi get_info %d failed\n", i);
  1456. continue;
  1457. }
  1458. encoder = sde_encoder_init(dev, &info);
  1459. if (IS_ERR_OR_NULL(encoder)) {
  1460. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1461. continue;
  1462. }
  1463. rc = dsi_display_drm_bridge_init(display, encoder);
  1464. if (rc) {
  1465. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1466. sde_encoder_destroy(encoder);
  1467. continue;
  1468. }
  1469. connector = sde_connector_init(dev,
  1470. encoder,
  1471. dsi_display_get_drm_panel(display),
  1472. display,
  1473. &dsi_ops,
  1474. DRM_CONNECTOR_POLL_HPD,
  1475. DRM_MODE_CONNECTOR_DSI);
  1476. if (connector) {
  1477. priv->encoders[priv->num_encoders++] = encoder;
  1478. priv->connectors[priv->num_connectors++] = connector;
  1479. } else {
  1480. SDE_ERROR("dsi %d connector init failed\n", i);
  1481. dsi_display_drm_bridge_deinit(display);
  1482. sde_encoder_destroy(encoder);
  1483. continue;
  1484. }
  1485. rc = dsi_display_drm_ext_bridge_init(display,
  1486. encoder, connector);
  1487. if (rc) {
  1488. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1489. dsi_display_drm_bridge_deinit(display);
  1490. sde_connector_destroy(connector);
  1491. sde_encoder_destroy(encoder);
  1492. }
  1493. dsc_count += info.dsc_count;
  1494. mixer_count += info.lm_count;
  1495. }
  1496. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1497. sde_kms->catalog->mixer_count - mixer_count : 0;
  1498. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1499. sde_kms->catalog->dsc_count - dsc_count : 0;
  1500. /* dp */
  1501. for (i = 0; i < sde_kms->dp_display_count &&
  1502. priv->num_encoders < max_encoders; ++i) {
  1503. int idx;
  1504. display = sde_kms->dp_displays[i];
  1505. encoder = NULL;
  1506. memset(&info, 0x0, sizeof(info));
  1507. rc = dp_connector_get_info(NULL, &info, display);
  1508. if (rc) {
  1509. SDE_ERROR("dp get_info %d failed\n", i);
  1510. continue;
  1511. }
  1512. encoder = sde_encoder_init(dev, &info);
  1513. if (IS_ERR_OR_NULL(encoder)) {
  1514. SDE_ERROR("dp encoder init failed %d\n", i);
  1515. continue;
  1516. }
  1517. rc = dp_drm_bridge_init(display, encoder,
  1518. max_dp_mixer_count, max_dp_dsc_count);
  1519. if (rc) {
  1520. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1521. sde_encoder_destroy(encoder);
  1522. continue;
  1523. }
  1524. connector = sde_connector_init(dev,
  1525. encoder,
  1526. NULL,
  1527. display,
  1528. &dp_ops,
  1529. DRM_CONNECTOR_POLL_HPD,
  1530. DRM_MODE_CONNECTOR_DisplayPort);
  1531. if (connector) {
  1532. priv->encoders[priv->num_encoders++] = encoder;
  1533. priv->connectors[priv->num_connectors++] = connector;
  1534. } else {
  1535. SDE_ERROR("dp %d connector init failed\n", i);
  1536. dp_drm_bridge_deinit(display);
  1537. sde_encoder_destroy(encoder);
  1538. }
  1539. /* update display cap to MST_MODE for DP MST encoders */
  1540. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1541. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1542. priv->num_encoders < max_encoders; idx++) {
  1543. info.h_tile_instance[0] = idx;
  1544. encoder = sde_encoder_init(dev, &info);
  1545. if (IS_ERR_OR_NULL(encoder)) {
  1546. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1547. continue;
  1548. }
  1549. rc = dp_mst_drm_bridge_init(display, encoder);
  1550. if (rc) {
  1551. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1552. i, rc);
  1553. sde_encoder_destroy(encoder);
  1554. continue;
  1555. }
  1556. priv->encoders[priv->num_encoders++] = encoder;
  1557. }
  1558. }
  1559. return 0;
  1560. }
  1561. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1562. {
  1563. struct msm_drm_private *priv;
  1564. int i;
  1565. if (!sde_kms) {
  1566. SDE_ERROR("invalid sde_kms\n");
  1567. return;
  1568. } else if (!sde_kms->dev) {
  1569. SDE_ERROR("invalid dev\n");
  1570. return;
  1571. } else if (!sde_kms->dev->dev_private) {
  1572. SDE_ERROR("invalid dev_private\n");
  1573. return;
  1574. }
  1575. priv = sde_kms->dev->dev_private;
  1576. for (i = 0; i < priv->num_crtcs; i++)
  1577. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1578. priv->num_crtcs = 0;
  1579. for (i = 0; i < priv->num_planes; i++)
  1580. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1581. priv->num_planes = 0;
  1582. for (i = 0; i < priv->num_connectors; i++)
  1583. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1584. priv->num_connectors = 0;
  1585. for (i = 0; i < priv->num_encoders; i++)
  1586. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1587. priv->num_encoders = 0;
  1588. _sde_kms_release_displays(sde_kms);
  1589. }
  1590. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1591. {
  1592. struct drm_device *dev;
  1593. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1594. struct drm_crtc *crtc;
  1595. struct msm_drm_private *priv;
  1596. struct sde_mdss_cfg *catalog;
  1597. int primary_planes_idx = 0, i, ret;
  1598. int max_crtc_count;
  1599. u32 sspp_id[MAX_PLANES];
  1600. u32 master_plane_id[MAX_PLANES];
  1601. u32 num_virt_planes = 0;
  1602. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1603. SDE_ERROR("invalid sde_kms\n");
  1604. return -EINVAL;
  1605. }
  1606. dev = sde_kms->dev;
  1607. priv = dev->dev_private;
  1608. catalog = sde_kms->catalog;
  1609. ret = sde_core_irq_domain_add(sde_kms);
  1610. if (ret)
  1611. goto fail_irq;
  1612. /*
  1613. * Query for underlying display drivers, and create connectors,
  1614. * bridges and encoders for them.
  1615. */
  1616. if (!_sde_kms_get_displays(sde_kms))
  1617. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1618. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1619. /* Create the planes */
  1620. for (i = 0; i < catalog->sspp_count; i++) {
  1621. bool primary = true;
  1622. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1623. || primary_planes_idx >= max_crtc_count)
  1624. primary = false;
  1625. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1626. (1UL << max_crtc_count) - 1, 0);
  1627. if (IS_ERR(plane)) {
  1628. SDE_ERROR("sde_plane_init failed\n");
  1629. ret = PTR_ERR(plane);
  1630. goto fail;
  1631. }
  1632. priv->planes[priv->num_planes++] = plane;
  1633. if (primary)
  1634. primary_planes[primary_planes_idx++] = plane;
  1635. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1636. sde_is_custom_client()) {
  1637. int priority =
  1638. catalog->sspp[i].sblk->smart_dma_priority;
  1639. sspp_id[priority - 1] = catalog->sspp[i].id;
  1640. master_plane_id[priority - 1] = plane->base.id;
  1641. num_virt_planes++;
  1642. }
  1643. }
  1644. /* Initialize smart DMA virtual planes */
  1645. for (i = 0; i < num_virt_planes; i++) {
  1646. plane = sde_plane_init(dev, sspp_id[i], false,
  1647. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1648. if (IS_ERR(plane)) {
  1649. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1650. ret = PTR_ERR(plane);
  1651. goto fail;
  1652. }
  1653. priv->planes[priv->num_planes++] = plane;
  1654. }
  1655. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1656. /* Create one CRTC per encoder */
  1657. for (i = 0; i < max_crtc_count; i++) {
  1658. crtc = sde_crtc_init(dev, primary_planes[i]);
  1659. if (IS_ERR(crtc)) {
  1660. ret = PTR_ERR(crtc);
  1661. goto fail;
  1662. }
  1663. priv->crtcs[priv->num_crtcs++] = crtc;
  1664. }
  1665. if (sde_is_custom_client()) {
  1666. /* All CRTCs are compatible with all planes */
  1667. for (i = 0; i < priv->num_planes; i++)
  1668. priv->planes[i]->possible_crtcs =
  1669. (1 << priv->num_crtcs) - 1;
  1670. }
  1671. /* All CRTCs are compatible with all encoders */
  1672. for (i = 0; i < priv->num_encoders; i++)
  1673. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1674. return 0;
  1675. fail:
  1676. _sde_kms_drm_obj_destroy(sde_kms);
  1677. fail_irq:
  1678. sde_core_irq_domain_fini(sde_kms);
  1679. return ret;
  1680. }
  1681. /**
  1682. * sde_kms_timeline_status - provides current timeline status
  1683. * This API should be called without mode config lock.
  1684. * @dev: Pointer to drm device
  1685. */
  1686. void sde_kms_timeline_status(struct drm_device *dev)
  1687. {
  1688. struct drm_crtc *crtc;
  1689. struct drm_connector *conn;
  1690. struct drm_connector_list_iter conn_iter;
  1691. if (!dev) {
  1692. SDE_ERROR("invalid drm device node\n");
  1693. return;
  1694. }
  1695. drm_for_each_crtc(crtc, dev)
  1696. sde_crtc_timeline_status(crtc);
  1697. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1698. /*
  1699. *Probably locked from last close dumping status anyway
  1700. */
  1701. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1702. drm_connector_list_iter_begin(dev, &conn_iter);
  1703. drm_for_each_connector_iter(conn, &conn_iter)
  1704. sde_conn_timeline_status(conn);
  1705. drm_connector_list_iter_end(&conn_iter);
  1706. return;
  1707. }
  1708. mutex_lock(&dev->mode_config.mutex);
  1709. drm_connector_list_iter_begin(dev, &conn_iter);
  1710. drm_for_each_connector_iter(conn, &conn_iter)
  1711. sde_conn_timeline_status(conn);
  1712. drm_connector_list_iter_end(&conn_iter);
  1713. mutex_unlock(&dev->mode_config.mutex);
  1714. }
  1715. static int sde_kms_postinit(struct msm_kms *kms)
  1716. {
  1717. struct sde_kms *sde_kms = to_sde_kms(kms);
  1718. struct drm_device *dev;
  1719. struct drm_crtc *crtc;
  1720. int rc;
  1721. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1722. SDE_ERROR("invalid sde_kms\n");
  1723. return -EINVAL;
  1724. }
  1725. dev = sde_kms->dev;
  1726. rc = _sde_debugfs_init(sde_kms);
  1727. if (rc)
  1728. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1729. drm_for_each_crtc(crtc, dev)
  1730. sde_crtc_post_init(dev, crtc);
  1731. return rc;
  1732. }
  1733. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1734. struct drm_encoder *encoder)
  1735. {
  1736. return rate;
  1737. }
  1738. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1739. struct platform_device *pdev)
  1740. {
  1741. struct drm_device *dev;
  1742. struct msm_drm_private *priv;
  1743. struct sde_vm_ops *vm_ops;
  1744. int i;
  1745. if (!sde_kms || !pdev)
  1746. return;
  1747. dev = sde_kms->dev;
  1748. if (!dev)
  1749. return;
  1750. priv = dev->dev_private;
  1751. if (!priv)
  1752. return;
  1753. if (sde_kms->genpd_init) {
  1754. sde_kms->genpd_init = false;
  1755. pm_genpd_remove(&sde_kms->genpd);
  1756. of_genpd_del_provider(pdev->dev.of_node);
  1757. }
  1758. vm_ops = sde_vm_get_ops(sde_kms);
  1759. if (vm_ops && vm_ops->vm_deinit)
  1760. vm_ops->vm_deinit(sde_kms, vm_ops);
  1761. if (sde_kms->hw_intr)
  1762. sde_hw_intr_destroy(sde_kms->hw_intr);
  1763. sde_kms->hw_intr = NULL;
  1764. if (sde_kms->power_event)
  1765. sde_power_handle_unregister_event(
  1766. &priv->phandle, sde_kms->power_event);
  1767. _sde_kms_release_displays(sde_kms);
  1768. _sde_kms_unmap_all_splash_regions(sde_kms);
  1769. if (sde_kms->catalog) {
  1770. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1771. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1772. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1773. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1774. }
  1775. }
  1776. if (sde_kms->rm_init)
  1777. sde_rm_destroy(&sde_kms->rm);
  1778. sde_kms->rm_init = false;
  1779. if (sde_kms->catalog)
  1780. sde_hw_catalog_deinit(sde_kms->catalog);
  1781. sde_kms->catalog = NULL;
  1782. if (sde_kms->sid)
  1783. msm_iounmap(pdev, sde_kms->sid);
  1784. sde_kms->sid = NULL;
  1785. if (sde_kms->reg_dma)
  1786. msm_iounmap(pdev, sde_kms->reg_dma);
  1787. sde_kms->reg_dma = NULL;
  1788. if (sde_kms->vbif[VBIF_NRT])
  1789. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1790. sde_kms->vbif[VBIF_NRT] = NULL;
  1791. if (sde_kms->vbif[VBIF_RT])
  1792. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1793. sde_kms->vbif[VBIF_RT] = NULL;
  1794. if (sde_kms->mmio)
  1795. msm_iounmap(pdev, sde_kms->mmio);
  1796. sde_kms->mmio = NULL;
  1797. sde_reg_dma_deinit();
  1798. _sde_kms_mmu_destroy(sde_kms);
  1799. }
  1800. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1801. {
  1802. int i;
  1803. if (!sde_kms)
  1804. return -EINVAL;
  1805. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1806. struct msm_mmu *mmu;
  1807. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1808. if (!aspace)
  1809. continue;
  1810. mmu = sde_kms->aspace[i]->mmu;
  1811. if (secure_only &&
  1812. !aspace->mmu->funcs->is_domain_secure(mmu))
  1813. continue;
  1814. /* cleanup aspace before detaching */
  1815. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1816. SDE_DEBUG("Detaching domain:%d\n", i);
  1817. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1818. ARRAY_SIZE(iommu_ports));
  1819. aspace->domain_attached = false;
  1820. }
  1821. return 0;
  1822. }
  1823. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1824. {
  1825. int i;
  1826. if (!sde_kms)
  1827. return -EINVAL;
  1828. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1829. struct msm_mmu *mmu;
  1830. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1831. if (!aspace)
  1832. continue;
  1833. mmu = sde_kms->aspace[i]->mmu;
  1834. if (secure_only &&
  1835. !aspace->mmu->funcs->is_domain_secure(mmu))
  1836. continue;
  1837. SDE_DEBUG("Attaching domain:%d\n", i);
  1838. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1839. ARRAY_SIZE(iommu_ports));
  1840. aspace->domain_attached = true;
  1841. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1842. }
  1843. return 0;
  1844. }
  1845. static void sde_kms_destroy(struct msm_kms *kms)
  1846. {
  1847. struct sde_kms *sde_kms;
  1848. struct drm_device *dev;
  1849. if (!kms) {
  1850. SDE_ERROR("invalid kms\n");
  1851. return;
  1852. }
  1853. sde_kms = to_sde_kms(kms);
  1854. dev = sde_kms->dev;
  1855. if (!dev || !dev->dev) {
  1856. SDE_ERROR("invalid device\n");
  1857. return;
  1858. }
  1859. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1860. kfree(sde_kms);
  1861. }
  1862. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1863. struct drm_atomic_state *state)
  1864. {
  1865. struct drm_device *dev = sde_kms->dev;
  1866. struct drm_plane *plane;
  1867. struct drm_plane_state *plane_state;
  1868. struct drm_crtc *crtc;
  1869. struct drm_crtc_state *crtc_state;
  1870. struct drm_connector *conn;
  1871. struct drm_connector_state *conn_state;
  1872. struct drm_connector_list_iter conn_iter;
  1873. int ret = 0;
  1874. drm_for_each_plane(plane, dev) {
  1875. plane_state = drm_atomic_get_plane_state(state, plane);
  1876. if (IS_ERR(plane_state)) {
  1877. ret = PTR_ERR(plane_state);
  1878. SDE_ERROR("error %d getting plane %d state\n",
  1879. ret, DRMID(plane));
  1880. return ret;
  1881. }
  1882. ret = sde_plane_helper_reset_custom_properties(plane,
  1883. plane_state);
  1884. if (ret) {
  1885. SDE_ERROR("error %d resetting plane props %d\n",
  1886. ret, DRMID(plane));
  1887. return ret;
  1888. }
  1889. }
  1890. drm_for_each_crtc(crtc, dev) {
  1891. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1892. if (IS_ERR(crtc_state)) {
  1893. ret = PTR_ERR(crtc_state);
  1894. SDE_ERROR("error %d getting crtc %d state\n",
  1895. ret, DRMID(crtc));
  1896. return ret;
  1897. }
  1898. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1899. if (ret) {
  1900. SDE_ERROR("error %d resetting crtc props %d\n",
  1901. ret, DRMID(crtc));
  1902. return ret;
  1903. }
  1904. }
  1905. drm_connector_list_iter_begin(dev, &conn_iter);
  1906. drm_for_each_connector_iter(conn, &conn_iter) {
  1907. conn_state = drm_atomic_get_connector_state(state, conn);
  1908. if (IS_ERR(conn_state)) {
  1909. ret = PTR_ERR(conn_state);
  1910. SDE_ERROR("error %d getting connector %d state\n",
  1911. ret, DRMID(conn));
  1912. return ret;
  1913. }
  1914. ret = sde_connector_helper_reset_custom_properties(conn,
  1915. conn_state);
  1916. if (ret) {
  1917. SDE_ERROR("error %d resetting connector props %d\n",
  1918. ret, DRMID(conn));
  1919. return ret;
  1920. }
  1921. }
  1922. drm_connector_list_iter_end(&conn_iter);
  1923. return ret;
  1924. }
  1925. static void sde_kms_lastclose(struct msm_kms *kms)
  1926. {
  1927. struct sde_kms *sde_kms;
  1928. struct drm_device *dev;
  1929. struct drm_atomic_state *state;
  1930. struct drm_modeset_acquire_ctx ctx;
  1931. int ret;
  1932. if (!kms) {
  1933. SDE_ERROR("invalid argument\n");
  1934. return;
  1935. }
  1936. sde_kms = to_sde_kms(kms);
  1937. dev = sde_kms->dev;
  1938. drm_modeset_acquire_init(&ctx, 0);
  1939. state = drm_atomic_state_alloc(dev);
  1940. if (!state) {
  1941. ret = -ENOMEM;
  1942. goto out_ctx;
  1943. }
  1944. state->acquire_ctx = &ctx;
  1945. retry:
  1946. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1947. if (ret)
  1948. goto out_state;
  1949. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1950. if (ret)
  1951. goto out_state;
  1952. ret = drm_atomic_commit(state);
  1953. out_state:
  1954. if (ret == -EDEADLK)
  1955. goto backoff;
  1956. drm_atomic_state_put(state);
  1957. out_ctx:
  1958. drm_modeset_drop_locks(&ctx);
  1959. drm_modeset_acquire_fini(&ctx);
  1960. if (ret)
  1961. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1962. return;
  1963. backoff:
  1964. drm_atomic_state_clear(state);
  1965. drm_modeset_backoff(&ctx);
  1966. goto retry;
  1967. }
  1968. static int sde_kms_check_vm_request(struct msm_kms *kms,
  1969. struct drm_atomic_state *state)
  1970. {
  1971. struct sde_kms *sde_kms;
  1972. struct drm_device *dev;
  1973. struct drm_crtc *crtc;
  1974. struct drm_crtc_state *new_cstate, *old_cstate;
  1975. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  1976. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  1977. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  1978. struct sde_vm_ops *vm_ops;
  1979. bool vm_req_active = false;
  1980. enum sde_crtc_idle_pc_state idle_pc_state;
  1981. int rc = 0;
  1982. if (!kms || !state)
  1983. return -EINVAL;
  1984. sde_kms = to_sde_kms(kms);
  1985. dev = sde_kms->dev;
  1986. vm_ops = sde_vm_get_ops(sde_kms);
  1987. if (!vm_ops)
  1988. return 0;
  1989. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  1990. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  1991. new_state = to_sde_crtc_state(new_cstate);
  1992. if (!new_cstate->active && !new_cstate->active_changed)
  1993. continue;
  1994. new_vm_req = sde_crtc_get_property(new_state,
  1995. CRTC_PROP_VM_REQ_STATE);
  1996. commit_crtc_cnt++;
  1997. if (old_cstate) {
  1998. old_state = to_sde_crtc_state(old_cstate);
  1999. old_vm_req = sde_crtc_get_property(old_state,
  2000. CRTC_PROP_VM_REQ_STATE);
  2001. }
  2002. /**
  2003. * No active request if the transition is from
  2004. * VM_REQ_NONE to VM_REQ_NONE
  2005. */
  2006. if (new_vm_req || (old_state && old_vm_req))
  2007. vm_req_active = true;
  2008. idle_pc_state = sde_crtc_get_property(new_state,
  2009. CRTC_PROP_IDLE_PC_STATE);
  2010. active_crtc = crtc;
  2011. }
  2012. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2013. if (!crtc->state->active)
  2014. continue;
  2015. global_crtc_cnt++;
  2016. global_active_crtc = crtc;
  2017. }
  2018. /* Check for single crtc commits only on valid VM requests */
  2019. if (vm_req_active && active_crtc && global_active_crtc &&
  2020. (commit_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2021. global_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2022. active_crtc != global_active_crtc)) {
  2023. SDE_ERROR(
  2024. "failed to switch VM due to CRTC concurrencies: MAX_CNT: %d active_cnt: %d global_cnt: %d active_crtc: %d global_crtc: %d\n",
  2025. sde_kms->catalog->max_trusted_vm_displays,
  2026. commit_crtc_cnt, global_crtc_cnt, active_crtc,
  2027. global_active_crtc);
  2028. return -E2BIG;
  2029. }
  2030. if (!vm_req_active)
  2031. return 0;
  2032. /* disable idle-pc before releasing the HW */
  2033. if ((new_vm_req == VM_REQ_RELEASE) &&
  2034. (idle_pc_state == IDLE_PC_ENABLE)) {
  2035. SDE_ERROR("failed to switch VM since idle-pc is enabled\n");
  2036. return -EINVAL;
  2037. }
  2038. sde_vm_lock(sde_kms);
  2039. if (vm_ops->vm_request_valid)
  2040. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2041. if (rc)
  2042. SDE_ERROR(
  2043. "failed to complete vm transition request. old_state = %d, new_state = %d, hw_ownership: %d\n",
  2044. old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2045. sde_vm_unlock(sde_kms);
  2046. return rc;
  2047. }
  2048. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2049. struct drm_atomic_state *state)
  2050. {
  2051. struct sde_kms *sde_kms;
  2052. struct drm_device *dev;
  2053. struct drm_crtc *crtc;
  2054. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2055. struct drm_crtc_state *crtc_state;
  2056. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2057. bool sec_session = false, global_sec_session = false;
  2058. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2059. int i;
  2060. if (!kms || !state) {
  2061. return -EINVAL;
  2062. SDE_ERROR("invalid arguments\n");
  2063. }
  2064. sde_kms = to_sde_kms(kms);
  2065. dev = sde_kms->dev;
  2066. /* iterate state object for active secure/non-secure crtc */
  2067. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2068. if (!crtc_state->active)
  2069. continue;
  2070. active_crtc_cnt++;
  2071. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2072. &fb_sec, &fb_sec_dir);
  2073. if (fb_sec_dir)
  2074. sec_session = true;
  2075. cur_crtc = crtc;
  2076. }
  2077. /* iterate global list for active and secure/non-secure crtc */
  2078. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2079. if (!crtc->state->active)
  2080. continue;
  2081. global_active_crtc_cnt++;
  2082. /* update only when crtc is not the same as current crtc */
  2083. if (crtc != cur_crtc) {
  2084. fb_ns = fb_sec = fb_sec_dir = 0;
  2085. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2086. &fb_sec, &fb_sec_dir);
  2087. if (fb_sec_dir)
  2088. global_sec_session = true;
  2089. global_crtc = crtc;
  2090. }
  2091. }
  2092. if (!global_sec_session && !sec_session)
  2093. return 0;
  2094. /*
  2095. * - fail crtc commit, if secure-camera/secure-ui session is
  2096. * in-progress in any other display
  2097. * - fail secure-camera/secure-ui crtc commit, if any other display
  2098. * session is in-progress
  2099. */
  2100. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2101. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2102. SDE_ERROR(
  2103. "crtc%d secure check failed global_active:%d active:%d\n",
  2104. cur_crtc ? cur_crtc->base.id : -1,
  2105. global_active_crtc_cnt, active_crtc_cnt);
  2106. return -EPERM;
  2107. /*
  2108. * As only one crtc is allowed during secure session, the crtc
  2109. * in this commit should match with the global crtc
  2110. */
  2111. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2112. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2113. cur_crtc->base.id, sec_session,
  2114. global_crtc->base.id, global_sec_session);
  2115. return -EPERM;
  2116. }
  2117. return 0;
  2118. }
  2119. static int sde_kms_atomic_check(struct msm_kms *kms,
  2120. struct drm_atomic_state *state)
  2121. {
  2122. struct sde_kms *sde_kms;
  2123. struct drm_device *dev;
  2124. int ret;
  2125. if (!kms || !state)
  2126. return -EINVAL;
  2127. sde_kms = to_sde_kms(kms);
  2128. dev = sde_kms->dev;
  2129. SDE_ATRACE_BEGIN("atomic_check");
  2130. if (sde_kms_is_suspend_blocked(dev)) {
  2131. SDE_DEBUG("suspended, skip atomic_check\n");
  2132. ret = -EBUSY;
  2133. goto end;
  2134. }
  2135. ret = drm_atomic_helper_check(dev, state);
  2136. if (ret)
  2137. goto end;
  2138. /*
  2139. * Check if any secure transition(moving CRTC between secure and
  2140. * non-secure state and vice-versa) is allowed or not. when moving
  2141. * to secure state, planes with fb_mode set to dir_translated only can
  2142. * be staged on the CRTC, and only one CRTC can be active during
  2143. * Secure state
  2144. */
  2145. ret = sde_kms_check_secure_transition(kms, state);
  2146. if (ret)
  2147. goto end;
  2148. ret = sde_kms_check_vm_request(kms, state);
  2149. if (ret)
  2150. SDE_ERROR("vm switch request checks failed\n");
  2151. end:
  2152. SDE_ATRACE_END("atomic_check");
  2153. return ret;
  2154. }
  2155. static struct msm_gem_address_space*
  2156. _sde_kms_get_address_space(struct msm_kms *kms,
  2157. unsigned int domain)
  2158. {
  2159. struct sde_kms *sde_kms;
  2160. if (!kms) {
  2161. SDE_ERROR("invalid kms\n");
  2162. return NULL;
  2163. }
  2164. sde_kms = to_sde_kms(kms);
  2165. if (!sde_kms) {
  2166. SDE_ERROR("invalid sde_kms\n");
  2167. return NULL;
  2168. }
  2169. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2170. return NULL;
  2171. return (sde_kms->aspace[domain] &&
  2172. sde_kms->aspace[domain]->domain_attached) ?
  2173. sde_kms->aspace[domain] : NULL;
  2174. }
  2175. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2176. unsigned int domain)
  2177. {
  2178. struct sde_kms *sde_kms;
  2179. struct msm_gem_address_space *aspace;
  2180. if (!kms) {
  2181. SDE_ERROR("invalid kms\n");
  2182. return NULL;
  2183. }
  2184. sde_kms = to_sde_kms(kms);
  2185. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2186. SDE_ERROR("invalid params\n");
  2187. return NULL;
  2188. }
  2189. aspace = _sde_kms_get_address_space(kms, domain);
  2190. return (aspace && aspace->domain_attached) ?
  2191. msm_gem_get_aspace_device(aspace) : NULL;
  2192. }
  2193. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2194. {
  2195. struct drm_device *dev = NULL;
  2196. struct sde_kms *sde_kms = NULL;
  2197. struct drm_connector *connector = NULL;
  2198. struct drm_connector_list_iter conn_iter;
  2199. struct sde_connector *sde_conn = NULL;
  2200. if (!kms) {
  2201. SDE_ERROR("invalid kms\n");
  2202. return;
  2203. }
  2204. sde_kms = to_sde_kms(kms);
  2205. dev = sde_kms->dev;
  2206. if (!dev) {
  2207. SDE_ERROR("invalid device\n");
  2208. return;
  2209. }
  2210. if (!dev->mode_config.poll_enabled)
  2211. return;
  2212. mutex_lock(&dev->mode_config.mutex);
  2213. drm_connector_list_iter_begin(dev, &conn_iter);
  2214. drm_for_each_connector_iter(connector, &conn_iter) {
  2215. /* Only handle HPD capable connectors. */
  2216. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2217. continue;
  2218. sde_conn = to_sde_connector(connector);
  2219. if (sde_conn->ops.post_open)
  2220. sde_conn->ops.post_open(&sde_conn->base,
  2221. sde_conn->display);
  2222. }
  2223. drm_connector_list_iter_end(&conn_iter);
  2224. mutex_unlock(&dev->mode_config.mutex);
  2225. }
  2226. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2227. struct sde_splash_display *splash_display,
  2228. struct drm_crtc *crtc)
  2229. {
  2230. struct msm_drm_private *priv;
  2231. struct drm_plane *plane;
  2232. struct sde_splash_mem *splash;
  2233. enum sde_sspp plane_id;
  2234. bool is_virtual;
  2235. int i, j;
  2236. if (!sde_kms || !splash_display || !crtc) {
  2237. SDE_ERROR("invalid input args\n");
  2238. return -EINVAL;
  2239. }
  2240. priv = sde_kms->dev->dev_private;
  2241. for (i = 0; i < priv->num_planes; i++) {
  2242. plane = priv->planes[i];
  2243. plane_id = sde_plane_pipe(plane);
  2244. is_virtual = is_sde_plane_virtual(plane);
  2245. splash = splash_display->splash;
  2246. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2247. if ((plane_id != splash_display->pipes[j].sspp) ||
  2248. (splash_display->pipes[j].is_virtual
  2249. != is_virtual))
  2250. continue;
  2251. if (splash && sde_plane_validate_src_addr(plane,
  2252. splash->splash_buf_base,
  2253. splash->splash_buf_size)) {
  2254. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2255. plane_id, crtc->base.id);
  2256. }
  2257. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2258. crtc->base.id, plane_id, is_virtual);
  2259. }
  2260. }
  2261. return 0;
  2262. }
  2263. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2264. struct sde_kms *sde_kms, struct drm_connector *connector,
  2265. u32 display_idx)
  2266. {
  2267. struct drm_display_mode *drm_mode = NULL, *curr_mode = NULL;
  2268. u32 i = 0, mode_index;
  2269. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2270. /* currently consider modes[0] as the preferred mode */
  2271. curr_mode = list_first_entry(&connector->modes,
  2272. struct drm_display_mode, head);
  2273. } else if (sde_kms->hw_mdp && sde_kms->hw_mdp->ops.get_mode_index) {
  2274. mode_index = sde_kms->hw_mdp->ops.get_mode_index(
  2275. sde_kms->hw_mdp, display_idx);
  2276. list_for_each_entry(drm_mode, &connector->modes, head) {
  2277. if (mode_index == i) {
  2278. curr_mode = drm_mode;
  2279. break;
  2280. }
  2281. i++;
  2282. }
  2283. }
  2284. return curr_mode;
  2285. }
  2286. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2287. {
  2288. void *display;
  2289. struct dsi_display *dsi_display;
  2290. struct msm_display_info info;
  2291. struct drm_encoder *encoder = NULL;
  2292. struct drm_crtc *crtc = NULL;
  2293. int i, rc = 0;
  2294. struct drm_display_mode *drm_mode = NULL;
  2295. struct drm_device *dev;
  2296. struct msm_drm_private *priv;
  2297. struct sde_kms *sde_kms;
  2298. struct drm_connector_list_iter conn_iter;
  2299. struct drm_connector *connector = NULL;
  2300. struct sde_connector *sde_conn = NULL;
  2301. struct sde_splash_display *splash_display;
  2302. if (!kms) {
  2303. SDE_ERROR("invalid kms\n");
  2304. return -EINVAL;
  2305. }
  2306. sde_kms = to_sde_kms(kms);
  2307. dev = sde_kms->dev;
  2308. if (!dev) {
  2309. SDE_ERROR("invalid device\n");
  2310. return -EINVAL;
  2311. }
  2312. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2313. && (!sde_kms->splash_data.num_splash_regions)) ||
  2314. !sde_kms->splash_data.num_splash_displays) {
  2315. DRM_INFO("cont_splash feature not enabled\n");
  2316. return rc;
  2317. }
  2318. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2319. sde_kms->splash_data.num_splash_displays,
  2320. sde_kms->dsi_display_count);
  2321. /* dsi */
  2322. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2323. display = sde_kms->dsi_displays[i];
  2324. dsi_display = (struct dsi_display *)display;
  2325. splash_display = &sde_kms->splash_data.splash_display[i];
  2326. if (!splash_display->cont_splash_enabled) {
  2327. SDE_DEBUG("display->name = %s splash not enabled\n",
  2328. dsi_display->name);
  2329. continue;
  2330. }
  2331. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2332. if (dsi_display->bridge->base.encoder) {
  2333. encoder = dsi_display->bridge->base.encoder;
  2334. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2335. }
  2336. memset(&info, 0x0, sizeof(info));
  2337. rc = dsi_display_get_info(NULL, &info, display);
  2338. if (rc) {
  2339. SDE_ERROR("dsi get_info %d failed\n", i);
  2340. encoder = NULL;
  2341. continue;
  2342. }
  2343. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2344. ((info.is_connected) ? "true" : "false"),
  2345. info.display_type);
  2346. if (!encoder) {
  2347. SDE_ERROR("encoder not initialized\n");
  2348. return -EINVAL;
  2349. }
  2350. priv = sde_kms->dev->dev_private;
  2351. encoder->crtc = priv->crtcs[i];
  2352. crtc = encoder->crtc;
  2353. splash_display->encoder = encoder;
  2354. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2355. i, crtc->base.id, encoder->base.id);
  2356. mutex_lock(&dev->mode_config.mutex);
  2357. drm_connector_list_iter_begin(dev, &conn_iter);
  2358. drm_for_each_connector_iter(connector, &conn_iter) {
  2359. /**
  2360. * SDE_KMS doesn't attach more than one encoder to
  2361. * a DSI connector. So it is safe to check only with
  2362. * the first encoder entry. Revisit this logic if we
  2363. * ever have to support continuous splash for
  2364. * external displays in MST configuration.
  2365. */
  2366. if (connector->encoder_ids[0] == encoder->base.id)
  2367. break;
  2368. }
  2369. drm_connector_list_iter_end(&conn_iter);
  2370. if (!connector) {
  2371. SDE_ERROR("connector not initialized\n");
  2372. mutex_unlock(&dev->mode_config.mutex);
  2373. return -EINVAL;
  2374. }
  2375. if (connector->funcs->fill_modes) {
  2376. connector->funcs->fill_modes(connector,
  2377. dev->mode_config.max_width,
  2378. dev->mode_config.max_height);
  2379. } else {
  2380. SDE_ERROR("fill_modes api not defined\n");
  2381. mutex_unlock(&dev->mode_config.mutex);
  2382. return -EINVAL;
  2383. }
  2384. mutex_unlock(&dev->mode_config.mutex);
  2385. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2386. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, i);
  2387. if (!drm_mode) {
  2388. SDE_ERROR("invalid drm-mode type:%d, index:%d\n",
  2389. sde_kms->splash_data.type, i);
  2390. return -EINVAL;
  2391. }
  2392. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2393. drm_mode->name, drm_mode->type,
  2394. drm_mode->flags);
  2395. /* Update CRTC drm structure */
  2396. crtc->state->active = true;
  2397. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2398. if (rc) {
  2399. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2400. return rc;
  2401. }
  2402. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2403. drm_mode_copy(&crtc->mode, drm_mode);
  2404. /* Update encoder structure */
  2405. sde_encoder_update_caps_for_cont_splash(encoder,
  2406. splash_display, true);
  2407. sde_crtc_update_cont_splash_settings(crtc);
  2408. sde_conn = to_sde_connector(connector);
  2409. if (sde_conn && sde_conn->ops.cont_splash_config)
  2410. sde_conn->ops.cont_splash_config(sde_conn->display);
  2411. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2412. splash_display, crtc);
  2413. if (rc) {
  2414. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2415. return rc;
  2416. }
  2417. }
  2418. return rc;
  2419. }
  2420. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2421. {
  2422. struct sde_kms *sde_kms;
  2423. if (!kms) {
  2424. SDE_ERROR("invalid kms\n");
  2425. return false;
  2426. }
  2427. sde_kms = to_sde_kms(kms);
  2428. return sde_kms->splash_data.num_splash_displays;
  2429. }
  2430. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2431. const struct drm_display_mode *mode,
  2432. const struct msm_resource_caps_info *res, u32 *num_lm)
  2433. {
  2434. struct sde_kms *sde_kms;
  2435. s64 mode_clock_hz = 0;
  2436. s64 max_mdp_clock_hz = 0;
  2437. s64 max_lm_width = 0;
  2438. s64 hdisplay_fp = 0;
  2439. s64 htotal_fp = 0;
  2440. s64 vtotal_fp = 0;
  2441. s64 vrefresh_fp = 0;
  2442. s64 mdp_fudge_factor = 0;
  2443. s64 num_lm_fp = 0;
  2444. s64 lm_clk_fp = 0;
  2445. s64 lm_width_fp = 0;
  2446. int rc = 0;
  2447. if (!num_lm) {
  2448. SDE_ERROR("invalid num_lm pointer\n");
  2449. return -EINVAL;
  2450. }
  2451. /* default to 1 layer mixer */
  2452. *num_lm = 1;
  2453. if (!kms || !mode || !res) {
  2454. SDE_ERROR("invalid input args\n");
  2455. return -EINVAL;
  2456. }
  2457. sde_kms = to_sde_kms(kms);
  2458. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2459. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2460. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2461. htotal_fp = drm_int2fixp(mode->htotal);
  2462. vtotal_fp = drm_int2fixp(mode->vtotal);
  2463. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2464. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2465. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2466. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2467. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2468. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2469. if (mode_clock_hz > max_mdp_clock_hz ||
  2470. hdisplay_fp > max_lm_width) {
  2471. *num_lm = 0;
  2472. do {
  2473. *num_lm += 2;
  2474. num_lm_fp = drm_int2fixp(*num_lm);
  2475. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2476. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2477. if (*num_lm > 4) {
  2478. rc = -EINVAL;
  2479. goto error;
  2480. }
  2481. } while (lm_clk_fp > max_mdp_clock_hz ||
  2482. lm_width_fp > max_lm_width);
  2483. mode_clock_hz = lm_clk_fp;
  2484. }
  2485. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2486. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2487. *num_lm, drm_fixp2int(mode_clock_hz),
  2488. sde_kms->perf.max_core_clk_rate);
  2489. return 0;
  2490. error:
  2491. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2492. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2493. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2494. *num_lm, drm_fixp2int(mode_clock_hz),
  2495. sde_kms->perf.max_core_clk_rate);
  2496. return rc;
  2497. }
  2498. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2499. u32 hdisplay, u32 *num_dsc)
  2500. {
  2501. struct sde_kms *sde_kms;
  2502. uint32_t max_dsc_width;
  2503. if (!num_dsc) {
  2504. SDE_ERROR("invalid num_dsc pointer\n");
  2505. return -EINVAL;
  2506. }
  2507. *num_dsc = 0;
  2508. if (!kms || !hdisplay) {
  2509. SDE_ERROR("invalid input args\n");
  2510. return -EINVAL;
  2511. }
  2512. sde_kms = to_sde_kms(kms);
  2513. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2514. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2515. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2516. hdisplay, max_dsc_width,
  2517. *num_dsc);
  2518. return 0;
  2519. }
  2520. static void _sde_kms_null_commit(struct drm_device *dev,
  2521. struct drm_encoder *enc)
  2522. {
  2523. struct drm_modeset_acquire_ctx ctx;
  2524. struct drm_connector *conn = NULL;
  2525. struct drm_connector *tmp_conn = NULL;
  2526. struct drm_connector_list_iter conn_iter;
  2527. struct drm_atomic_state *state = NULL;
  2528. struct drm_crtc_state *crtc_state = NULL;
  2529. struct drm_connector_state *conn_state = NULL;
  2530. int retry_cnt = 0;
  2531. int ret = 0;
  2532. drm_modeset_acquire_init(&ctx, 0);
  2533. retry:
  2534. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2535. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2536. drm_modeset_backoff(&ctx);
  2537. retry_cnt++;
  2538. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2539. goto retry;
  2540. } else if (WARN_ON(ret)) {
  2541. goto end;
  2542. }
  2543. state = drm_atomic_state_alloc(dev);
  2544. if (!state) {
  2545. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2546. goto end;
  2547. }
  2548. state->acquire_ctx = &ctx;
  2549. drm_connector_list_iter_begin(dev, &conn_iter);
  2550. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2551. if (enc == tmp_conn->state->best_encoder) {
  2552. conn = tmp_conn;
  2553. break;
  2554. }
  2555. }
  2556. drm_connector_list_iter_end(&conn_iter);
  2557. if (!conn) {
  2558. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2559. goto end;
  2560. }
  2561. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2562. conn_state = drm_atomic_get_connector_state(state, conn);
  2563. if (IS_ERR(conn_state)) {
  2564. SDE_ERROR("error %d getting connector %d state\n",
  2565. ret, DRMID(conn));
  2566. goto end;
  2567. }
  2568. crtc_state->active = true;
  2569. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2570. if (ret)
  2571. SDE_ERROR("error %d setting the crtc\n", ret);
  2572. ret = drm_atomic_commit(state);
  2573. if (ret)
  2574. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2575. end:
  2576. if (state)
  2577. drm_atomic_state_put(state);
  2578. drm_modeset_drop_locks(&ctx);
  2579. drm_modeset_acquire_fini(&ctx);
  2580. }
  2581. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2582. const int32_t connector_id)
  2583. {
  2584. struct drm_connector_list_iter conn_iter;
  2585. struct drm_connector *conn;
  2586. struct drm_encoder *drm_enc;
  2587. drm_connector_list_iter_begin(dev, &conn_iter);
  2588. drm_for_each_connector_iter(conn, &conn_iter) {
  2589. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2590. connector_id != conn->base.id)
  2591. continue;
  2592. if (conn->state && conn->state->best_encoder)
  2593. drm_enc = conn->state->best_encoder;
  2594. else
  2595. drm_enc = conn->encoder;
  2596. sde_encoder_early_wakeup(drm_enc);
  2597. }
  2598. drm_connector_list_iter_end(&conn_iter);
  2599. }
  2600. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2601. struct device *dev)
  2602. {
  2603. int i, ret, crtc_id = 0;
  2604. struct drm_device *ddev = dev_get_drvdata(dev);
  2605. struct drm_connector *conn;
  2606. struct drm_connector_list_iter conn_iter;
  2607. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2608. drm_connector_list_iter_begin(ddev, &conn_iter);
  2609. drm_for_each_connector_iter(conn, &conn_iter) {
  2610. uint64_t lp;
  2611. lp = sde_connector_get_lp(conn);
  2612. if (lp != SDE_MODE_DPMS_LP2)
  2613. continue;
  2614. if (sde_encoder_in_clone_mode(conn->encoder))
  2615. continue;
  2616. ret = sde_encoder_wait_for_event(conn->encoder,
  2617. MSM_ENC_TX_COMPLETE);
  2618. if (ret && ret != -EWOULDBLOCK) {
  2619. SDE_ERROR(
  2620. "[conn: %d] wait for commit done returned %d\n",
  2621. conn->base.id, ret);
  2622. } else if (!ret) {
  2623. crtc_id = drm_crtc_index(conn->state->crtc);
  2624. if (priv->event_thread[crtc_id].thread)
  2625. kthread_flush_worker(
  2626. &priv->event_thread[crtc_id].worker);
  2627. sde_encoder_idle_request(conn->encoder);
  2628. }
  2629. }
  2630. drm_connector_list_iter_end(&conn_iter);
  2631. for (i = 0; i < priv->num_crtcs; i++) {
  2632. if (priv->disp_thread[i].thread)
  2633. kthread_flush_worker(
  2634. &priv->disp_thread[i].worker);
  2635. if (priv->event_thread[i].thread)
  2636. kthread_flush_worker(
  2637. &priv->event_thread[i].worker);
  2638. }
  2639. kthread_flush_worker(&priv->pp_event_worker);
  2640. }
  2641. static int sde_kms_pm_suspend(struct device *dev)
  2642. {
  2643. struct drm_device *ddev;
  2644. struct drm_modeset_acquire_ctx ctx;
  2645. struct drm_connector *conn;
  2646. struct drm_encoder *enc;
  2647. struct drm_connector_list_iter conn_iter;
  2648. struct drm_atomic_state *state = NULL;
  2649. struct sde_kms *sde_kms;
  2650. int ret = 0, num_crtcs = 0;
  2651. if (!dev)
  2652. return -EINVAL;
  2653. ddev = dev_get_drvdata(dev);
  2654. if (!ddev || !ddev_to_msm_kms(ddev))
  2655. return -EINVAL;
  2656. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2657. SDE_EVT32(0);
  2658. /* disable hot-plug polling */
  2659. drm_kms_helper_poll_disable(ddev);
  2660. /* if a display stuck in CS trigger a null commit to complete handoff */
  2661. drm_for_each_encoder(enc, ddev) {
  2662. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2663. _sde_kms_null_commit(ddev, enc);
  2664. }
  2665. /* acquire modeset lock(s) */
  2666. drm_modeset_acquire_init(&ctx, 0);
  2667. retry:
  2668. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2669. if (ret)
  2670. goto unlock;
  2671. /* save current state for resume */
  2672. if (sde_kms->suspend_state)
  2673. drm_atomic_state_put(sde_kms->suspend_state);
  2674. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2675. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2676. ret = PTR_ERR(sde_kms->suspend_state);
  2677. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2678. sde_kms->suspend_state = NULL;
  2679. goto unlock;
  2680. }
  2681. /* create atomic state to disable all CRTCs */
  2682. state = drm_atomic_state_alloc(ddev);
  2683. if (!state) {
  2684. ret = -ENOMEM;
  2685. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2686. goto unlock;
  2687. }
  2688. state->acquire_ctx = &ctx;
  2689. drm_connector_list_iter_begin(ddev, &conn_iter);
  2690. drm_for_each_connector_iter(conn, &conn_iter) {
  2691. struct drm_crtc_state *crtc_state;
  2692. uint64_t lp;
  2693. if (!conn->state || !conn->state->crtc ||
  2694. conn->dpms != DRM_MODE_DPMS_ON ||
  2695. sde_encoder_in_clone_mode(conn->encoder))
  2696. continue;
  2697. lp = sde_connector_get_lp(conn);
  2698. if (lp == SDE_MODE_DPMS_LP1) {
  2699. /* transition LP1->LP2 on pm suspend */
  2700. ret = sde_connector_set_property_for_commit(conn, state,
  2701. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2702. if (ret) {
  2703. DRM_ERROR("failed to set lp2 for conn %d\n",
  2704. conn->base.id);
  2705. drm_connector_list_iter_end(&conn_iter);
  2706. goto unlock;
  2707. }
  2708. }
  2709. if (lp != SDE_MODE_DPMS_LP2) {
  2710. /* force CRTC to be inactive */
  2711. crtc_state = drm_atomic_get_crtc_state(state,
  2712. conn->state->crtc);
  2713. if (IS_ERR_OR_NULL(crtc_state)) {
  2714. DRM_ERROR("failed to get crtc %d state\n",
  2715. conn->state->crtc->base.id);
  2716. drm_connector_list_iter_end(&conn_iter);
  2717. goto unlock;
  2718. }
  2719. if (lp != SDE_MODE_DPMS_LP1)
  2720. crtc_state->active = false;
  2721. ++num_crtcs;
  2722. }
  2723. }
  2724. drm_connector_list_iter_end(&conn_iter);
  2725. /* check for nothing to do */
  2726. if (num_crtcs == 0) {
  2727. DRM_DEBUG("all crtcs are already in the off state\n");
  2728. sde_kms->suspend_block = true;
  2729. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2730. goto unlock;
  2731. }
  2732. /* commit the "disable all" state */
  2733. ret = drm_atomic_commit(state);
  2734. if (ret < 0) {
  2735. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2736. goto unlock;
  2737. }
  2738. sde_kms->suspend_block = true;
  2739. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2740. unlock:
  2741. if (state) {
  2742. drm_atomic_state_put(state);
  2743. state = NULL;
  2744. }
  2745. if (ret == -EDEADLK) {
  2746. drm_modeset_backoff(&ctx);
  2747. goto retry;
  2748. }
  2749. drm_modeset_drop_locks(&ctx);
  2750. drm_modeset_acquire_fini(&ctx);
  2751. /*
  2752. * pm runtime driver avoids multiple runtime_suspend API call by
  2753. * checking runtime_status. However, this call helps when there is a
  2754. * race condition between pm_suspend call and doze_suspend/power_off
  2755. * commit. It removes the extra vote from suspend and adds it back
  2756. * later to allow power collapse during pm_suspend call
  2757. */
  2758. pm_runtime_put_sync(dev);
  2759. pm_runtime_get_noresume(dev);
  2760. /* dump clock state before entering suspend */
  2761. if (sde_kms->pm_suspend_clk_dump)
  2762. _sde_kms_dump_clks_state(sde_kms);
  2763. return ret;
  2764. }
  2765. static int sde_kms_pm_resume(struct device *dev)
  2766. {
  2767. struct drm_device *ddev;
  2768. struct sde_kms *sde_kms;
  2769. struct drm_modeset_acquire_ctx ctx;
  2770. int ret, i;
  2771. if (!dev)
  2772. return -EINVAL;
  2773. ddev = dev_get_drvdata(dev);
  2774. if (!ddev || !ddev_to_msm_kms(ddev))
  2775. return -EINVAL;
  2776. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2777. SDE_EVT32(sde_kms->suspend_state != NULL);
  2778. drm_mode_config_reset(ddev);
  2779. drm_modeset_acquire_init(&ctx, 0);
  2780. retry:
  2781. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2782. if (ret == -EDEADLK) {
  2783. drm_modeset_backoff(&ctx);
  2784. goto retry;
  2785. } else if (WARN_ON(ret)) {
  2786. goto end;
  2787. }
  2788. sde_kms->suspend_block = false;
  2789. if (sde_kms->suspend_state) {
  2790. sde_kms->suspend_state->acquire_ctx = &ctx;
  2791. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2792. ret = drm_atomic_helper_commit_duplicated_state(
  2793. sde_kms->suspend_state, &ctx);
  2794. if (ret != -EDEADLK)
  2795. break;
  2796. drm_modeset_backoff(&ctx);
  2797. }
  2798. if (ret < 0)
  2799. DRM_ERROR("failed to restore state, %d\n", ret);
  2800. drm_atomic_state_put(sde_kms->suspend_state);
  2801. sde_kms->suspend_state = NULL;
  2802. }
  2803. end:
  2804. drm_modeset_drop_locks(&ctx);
  2805. drm_modeset_acquire_fini(&ctx);
  2806. /* enable hot-plug polling */
  2807. drm_kms_helper_poll_enable(ddev);
  2808. return 0;
  2809. }
  2810. static const struct msm_kms_funcs kms_funcs = {
  2811. .hw_init = sde_kms_hw_init,
  2812. .postinit = sde_kms_postinit,
  2813. .irq_preinstall = sde_irq_preinstall,
  2814. .irq_postinstall = sde_irq_postinstall,
  2815. .irq_uninstall = sde_irq_uninstall,
  2816. .irq = sde_irq,
  2817. .lastclose = sde_kms_lastclose,
  2818. .prepare_fence = sde_kms_prepare_fence,
  2819. .prepare_commit = sde_kms_prepare_commit,
  2820. .commit = sde_kms_commit,
  2821. .complete_commit = sde_kms_complete_commit,
  2822. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2823. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2824. .enable_vblank = sde_kms_enable_vblank,
  2825. .disable_vblank = sde_kms_disable_vblank,
  2826. .check_modified_format = sde_format_check_modified_format,
  2827. .atomic_check = sde_kms_atomic_check,
  2828. .get_format = sde_get_msm_format,
  2829. .round_pixclk = sde_kms_round_pixclk,
  2830. .display_early_wakeup = sde_kms_display_early_wakeup,
  2831. .pm_suspend = sde_kms_pm_suspend,
  2832. .pm_resume = sde_kms_pm_resume,
  2833. .destroy = sde_kms_destroy,
  2834. .debugfs_destroy = sde_kms_debugfs_destroy,
  2835. .cont_splash_config = sde_kms_cont_splash_config,
  2836. .register_events = _sde_kms_register_events,
  2837. .get_address_space = _sde_kms_get_address_space,
  2838. .get_address_space_device = _sde_kms_get_address_space_device,
  2839. .postopen = _sde_kms_post_open,
  2840. .check_for_splash = sde_kms_check_for_splash,
  2841. .get_mixer_count = sde_kms_get_mixer_count,
  2842. .get_dsc_count = sde_kms_get_dsc_count,
  2843. };
  2844. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2845. {
  2846. int i;
  2847. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2848. if (!sde_kms->aspace[i])
  2849. continue;
  2850. msm_gem_address_space_put(sde_kms->aspace[i]);
  2851. sde_kms->aspace[i] = NULL;
  2852. }
  2853. return 0;
  2854. }
  2855. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2856. {
  2857. struct msm_mmu *mmu;
  2858. int i, ret;
  2859. int early_map = 0;
  2860. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2861. return -EINVAL;
  2862. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2863. struct msm_gem_address_space *aspace;
  2864. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2865. if (IS_ERR(mmu)) {
  2866. ret = PTR_ERR(mmu);
  2867. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2868. i, ret);
  2869. continue;
  2870. }
  2871. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2872. mmu, "sde");
  2873. if (IS_ERR(aspace)) {
  2874. ret = PTR_ERR(aspace);
  2875. goto fail;
  2876. }
  2877. sde_kms->aspace[i] = aspace;
  2878. aspace->domain_attached = true;
  2879. /* Mapping splash memory block */
  2880. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2881. sde_kms->splash_data.num_splash_regions) {
  2882. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2883. if (ret) {
  2884. SDE_ERROR("failed to map ret:%d\n", ret);
  2885. goto fail;
  2886. }
  2887. }
  2888. /*
  2889. * disable early-map which would have been enabled during
  2890. * bootup by smmu through the device-tree hint for cont-spash
  2891. */
  2892. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2893. &early_map);
  2894. if (ret) {
  2895. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2896. ret, early_map);
  2897. goto early_map_fail;
  2898. }
  2899. }
  2900. sde_kms->base.aspace = sde_kms->aspace[0];
  2901. return 0;
  2902. early_map_fail:
  2903. _sde_kms_unmap_all_splash_regions(sde_kms);
  2904. fail:
  2905. mmu->funcs->destroy(mmu);
  2906. _sde_kms_mmu_destroy(sde_kms);
  2907. return ret;
  2908. }
  2909. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  2910. {
  2911. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  2912. return;
  2913. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  2914. }
  2915. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2916. {
  2917. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2918. return;
  2919. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2920. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2921. sde_kms->catalog);
  2922. }
  2923. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2924. {
  2925. struct sde_vbif_set_qos_params qos_params;
  2926. struct sde_mdss_cfg *catalog;
  2927. if (!sde_kms->catalog)
  2928. return;
  2929. catalog = sde_kms->catalog;
  2930. memset(&qos_params, 0, sizeof(qos_params));
  2931. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2932. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2933. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2934. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2935. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2936. }
  2937. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2938. {
  2939. struct sde_hw_uidle *uidle;
  2940. if (!sde_kms) {
  2941. SDE_ERROR("invalid kms\n");
  2942. return -EINVAL;
  2943. }
  2944. uidle = sde_kms->hw_uidle;
  2945. if (uidle && uidle->ops.active_override_enable)
  2946. uidle->ops.active_override_enable(uidle, enable);
  2947. return 0;
  2948. }
  2949. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2950. {
  2951. struct device *cpu_dev;
  2952. int cpu = 0;
  2953. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  2954. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2955. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2956. return;
  2957. }
  2958. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2959. cpu_dev = get_cpu_device(cpu);
  2960. if (!cpu_dev) {
  2961. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2962. cpu);
  2963. continue;
  2964. }
  2965. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2966. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2967. cpu_irq_latency);
  2968. else
  2969. dev_pm_qos_add_request(cpu_dev,
  2970. &sde_kms->pm_qos_irq_req[cpu],
  2971. DEV_PM_QOS_RESUME_LATENCY,
  2972. cpu_irq_latency);
  2973. }
  2974. }
  2975. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2976. {
  2977. struct device *cpu_dev;
  2978. int cpu = 0;
  2979. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2980. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2981. return;
  2982. }
  2983. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2984. cpu_dev = get_cpu_device(cpu);
  2985. if (!cpu_dev) {
  2986. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2987. cpu);
  2988. continue;
  2989. }
  2990. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2991. dev_pm_qos_remove_request(
  2992. &sde_kms->pm_qos_irq_req[cpu]);
  2993. }
  2994. }
  2995. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  2996. {
  2997. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2998. mutex_lock(&priv->phandle.phandle_lock);
  2999. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3000. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3001. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3002. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3003. mutex_unlock(&priv->phandle.phandle_lock);
  3004. }
  3005. static void sde_kms_irq_affinity_notify(
  3006. struct irq_affinity_notify *affinity_notify,
  3007. const cpumask_t *mask)
  3008. {
  3009. struct msm_drm_private *priv;
  3010. struct sde_kms *sde_kms = container_of(affinity_notify,
  3011. struct sde_kms, affinity_notify);
  3012. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3013. return;
  3014. priv = sde_kms->dev->dev_private;
  3015. mutex_lock(&priv->phandle.phandle_lock);
  3016. // save irq cpu mask
  3017. sde_kms->irq_cpu_mask = *mask;
  3018. // request vote with updated irq cpu mask
  3019. if (sde_kms->irq_enabled)
  3020. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3021. mutex_unlock(&priv->phandle.phandle_lock);
  3022. }
  3023. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3024. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3025. {
  3026. struct sde_kms *sde_kms = usr;
  3027. struct msm_kms *msm_kms;
  3028. msm_kms = &sde_kms->base;
  3029. if (!sde_kms)
  3030. return;
  3031. SDE_DEBUG("event_type:%d\n", event_type);
  3032. SDE_EVT32_VERBOSE(event_type);
  3033. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3034. sde_irq_update(msm_kms, true);
  3035. sde_kms->first_kickoff = true;
  3036. /**
  3037. * Rotator sid needs to be programmed since uefi doesn't
  3038. * configure it during continuous splash
  3039. */
  3040. sde_kms_init_rot_sid_hw(sde_kms);
  3041. if (sde_kms->splash_data.num_splash_displays ||
  3042. sde_in_trusted_vm(sde_kms))
  3043. return;
  3044. sde_vbif_init_memtypes(sde_kms);
  3045. sde_kms_init_shared_hw(sde_kms);
  3046. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3047. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3048. sde_irq_update(msm_kms, false);
  3049. sde_kms->first_kickoff = false;
  3050. if (sde_in_trusted_vm(sde_kms))
  3051. return;
  3052. _sde_kms_active_override(sde_kms, true);
  3053. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3054. sde_vbif_axi_halt_request(sde_kms);
  3055. }
  3056. }
  3057. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3058. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3059. {
  3060. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3061. int rc = -EINVAL;
  3062. SDE_DEBUG("\n");
  3063. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3064. if (rc > 0)
  3065. rc = 0;
  3066. SDE_EVT32(rc, genpd->device_count);
  3067. return rc;
  3068. }
  3069. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3070. {
  3071. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3072. SDE_DEBUG("\n");
  3073. pm_runtime_put_sync(sde_kms->dev->dev);
  3074. SDE_EVT32(genpd->device_count);
  3075. return 0;
  3076. }
  3077. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3078. struct sde_splash_data *data)
  3079. {
  3080. int i = 0;
  3081. int ret = 0;
  3082. struct device_node *parent, *node, *node1;
  3083. struct resource r, r1;
  3084. const char *node_name = "splash_region";
  3085. struct sde_splash_mem *mem;
  3086. bool share_splash_mem = false;
  3087. int num_displays, num_regions;
  3088. struct sde_splash_display *splash_display;
  3089. if (!data)
  3090. return -EINVAL;
  3091. memset(data, 0, sizeof(*data));
  3092. parent = of_find_node_by_path("/reserved-memory");
  3093. if (!parent) {
  3094. SDE_ERROR("failed to find reserved-memory node\n");
  3095. return -EINVAL;
  3096. }
  3097. node = of_find_node_by_name(parent, node_name);
  3098. if (!node) {
  3099. SDE_DEBUG("failed to find node %s\n", node_name);
  3100. return -EINVAL;
  3101. }
  3102. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3103. if (!node1)
  3104. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3105. /**
  3106. * Support sharing a single splash memory for all the built in displays
  3107. * and also independent splash region per displays. Incase of
  3108. * independent splash region for each connected display, dtsi node of
  3109. * cont_splash_region should be collection of all memory regions
  3110. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3111. */
  3112. num_displays = dsi_display_get_num_of_displays();
  3113. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3114. data->num_splash_displays = num_displays;
  3115. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3116. if (num_displays > num_regions) {
  3117. share_splash_mem = true;
  3118. pr_info(":%d displays share same splash buf\n", num_displays);
  3119. }
  3120. for (i = 0; i < num_displays; i++) {
  3121. splash_display = &data->splash_display[i];
  3122. if (!i || !share_splash_mem) {
  3123. if (of_address_to_resource(node, i, &r)) {
  3124. SDE_ERROR("invalid data for:%s\n", node_name);
  3125. return -EINVAL;
  3126. }
  3127. mem = &data->splash_mem[i];
  3128. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3129. SDE_DEBUG("failed to find ramdump memory\n");
  3130. mem->ramdump_base = 0;
  3131. mem->ramdump_size = 0;
  3132. } else {
  3133. mem->ramdump_base = (unsigned long)r1.start;
  3134. mem->ramdump_size = (r1.end - r1.start) + 1;
  3135. }
  3136. mem->splash_buf_base = (unsigned long)r.start;
  3137. mem->splash_buf_size = (r.end - r.start) + 1;
  3138. mem->ref_cnt = 0;
  3139. splash_display->splash = mem;
  3140. data->num_splash_regions++;
  3141. } else {
  3142. data->splash_display[i].splash = &data->splash_mem[0];
  3143. }
  3144. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3145. splash_display->splash->splash_buf_base,
  3146. splash_display->splash->splash_buf_size);
  3147. }
  3148. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3149. return ret;
  3150. }
  3151. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3152. struct platform_device *platformdev)
  3153. {
  3154. int rc = -EINVAL;
  3155. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3156. if (IS_ERR(sde_kms->mmio)) {
  3157. rc = PTR_ERR(sde_kms->mmio);
  3158. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3159. sde_kms->mmio = NULL;
  3160. goto error;
  3161. }
  3162. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3163. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3164. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3165. sde_kms->mmio_len);
  3166. if (rc)
  3167. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3168. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3169. "vbif_phys");
  3170. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3171. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3172. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3173. sde_kms->vbif[VBIF_RT] = NULL;
  3174. goto error;
  3175. }
  3176. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3177. "vbif_phys");
  3178. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3179. sde_kms->vbif_len[VBIF_RT]);
  3180. if (rc)
  3181. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3182. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3183. "vbif_nrt_phys");
  3184. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3185. sde_kms->vbif[VBIF_NRT] = NULL;
  3186. SDE_DEBUG("VBIF NRT is not defined");
  3187. } else {
  3188. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3189. "vbif_nrt_phys");
  3190. rc = sde_dbg_reg_register_base("vbif_nrt",
  3191. sde_kms->vbif[VBIF_NRT],
  3192. sde_kms->vbif_len[VBIF_NRT]);
  3193. if (rc)
  3194. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3195. rc);
  3196. }
  3197. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3198. "regdma_phys");
  3199. if (IS_ERR(sde_kms->reg_dma)) {
  3200. sde_kms->reg_dma = NULL;
  3201. SDE_DEBUG("REG_DMA is not defined");
  3202. } else {
  3203. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3204. "regdma_phys");
  3205. rc = sde_dbg_reg_register_base("reg_dma",
  3206. sde_kms->reg_dma,
  3207. sde_kms->reg_dma_len);
  3208. if (rc)
  3209. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3210. rc);
  3211. }
  3212. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3213. "sid_phys");
  3214. if (IS_ERR(sde_kms->sid)) {
  3215. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3216. sde_kms->sid = NULL;
  3217. } else {
  3218. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3219. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3220. sde_kms->sid_len);
  3221. if (rc)
  3222. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3223. }
  3224. error:
  3225. return rc;
  3226. }
  3227. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3228. struct sde_kms *sde_kms)
  3229. {
  3230. int rc = 0;
  3231. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3232. sde_kms->genpd.name = dev->unique;
  3233. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3234. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3235. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3236. if (rc < 0) {
  3237. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3238. sde_kms->genpd.name, rc);
  3239. return rc;
  3240. }
  3241. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3242. &sde_kms->genpd);
  3243. if (rc < 0) {
  3244. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3245. sde_kms->genpd.name, rc);
  3246. pm_genpd_remove(&sde_kms->genpd);
  3247. return rc;
  3248. }
  3249. sde_kms->genpd_init = true;
  3250. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3251. }
  3252. return rc;
  3253. }
  3254. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3255. struct drm_device *dev,
  3256. struct msm_drm_private *priv)
  3257. {
  3258. struct sde_rm *rm = NULL;
  3259. int i, rc = -EINVAL;
  3260. sde_kms->catalog = sde_hw_catalog_init(dev);
  3261. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3262. rc = PTR_ERR(sde_kms->catalog);
  3263. if (!sde_kms->catalog)
  3264. rc = -EINVAL;
  3265. SDE_ERROR("catalog init failed: %d\n", rc);
  3266. sde_kms->catalog = NULL;
  3267. goto power_error;
  3268. }
  3269. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3270. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3271. /* initialize power domain if defined */
  3272. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3273. if (rc) {
  3274. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3275. goto genpd_err;
  3276. }
  3277. rc = _sde_kms_mmu_init(sde_kms);
  3278. if (rc) {
  3279. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3280. goto power_error;
  3281. }
  3282. /* Initialize reg dma block which is a singleton */
  3283. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3284. sde_kms->dev);
  3285. if (rc) {
  3286. SDE_ERROR("failed: reg dma init failed\n");
  3287. goto power_error;
  3288. }
  3289. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3290. rm = &sde_kms->rm;
  3291. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3292. sde_kms->dev);
  3293. if (rc) {
  3294. SDE_ERROR("rm init failed: %d\n", rc);
  3295. goto power_error;
  3296. }
  3297. sde_kms->rm_init = true;
  3298. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3299. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3300. rc = PTR_ERR(sde_kms->hw_intr);
  3301. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3302. sde_kms->hw_intr = NULL;
  3303. goto hw_intr_init_err;
  3304. }
  3305. /*
  3306. * Attempt continuous splash handoff only if reserved
  3307. * splash memory is found & release resources on any error
  3308. * in finding display hw config in splash
  3309. */
  3310. if (sde_kms->splash_data.num_splash_regions) {
  3311. struct sde_splash_display *display;
  3312. int ret, display_count =
  3313. sde_kms->splash_data.num_splash_displays;
  3314. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3315. &sde_kms->splash_data, sde_kms->catalog);
  3316. for (i = 0; i < display_count; i++) {
  3317. display = &sde_kms->splash_data.splash_display[i];
  3318. /*
  3319. * free splash region on resource init failure and
  3320. * cont-splash disabled case
  3321. */
  3322. if (!display->cont_splash_enabled || ret)
  3323. _sde_kms_free_splash_display_data(
  3324. sde_kms, display);
  3325. }
  3326. }
  3327. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3328. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3329. rc = PTR_ERR(sde_kms->hw_mdp);
  3330. if (!sde_kms->hw_mdp)
  3331. rc = -EINVAL;
  3332. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3333. sde_kms->hw_mdp = NULL;
  3334. goto power_error;
  3335. }
  3336. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3337. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3338. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3339. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3340. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3341. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3342. if (!sde_kms->hw_vbif[vbif_idx])
  3343. rc = -EINVAL;
  3344. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3345. sde_kms->hw_vbif[vbif_idx] = NULL;
  3346. goto power_error;
  3347. }
  3348. }
  3349. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3350. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3351. sde_kms->mmio_len, sde_kms->catalog);
  3352. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3353. rc = PTR_ERR(sde_kms->hw_uidle);
  3354. if (!sde_kms->hw_uidle)
  3355. rc = -EINVAL;
  3356. /* uidle is optional, so do not make it a fatal error */
  3357. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3358. sde_kms->hw_uidle = NULL;
  3359. rc = 0;
  3360. }
  3361. } else {
  3362. sde_kms->hw_uidle = NULL;
  3363. }
  3364. if (sde_kms->sid) {
  3365. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3366. sde_kms->sid_len, sde_kms->catalog);
  3367. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3368. rc = PTR_ERR(sde_kms->hw_sid);
  3369. SDE_ERROR("failed to init sid %ld\n", rc);
  3370. sde_kms->hw_sid = NULL;
  3371. goto power_error;
  3372. }
  3373. }
  3374. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3375. &priv->phandle, "core_clk");
  3376. if (rc) {
  3377. SDE_ERROR("failed to init perf %d\n", rc);
  3378. goto perf_err;
  3379. }
  3380. /*
  3381. * _sde_kms_drm_obj_init should create the DRM related objects
  3382. * i.e. CRTCs, planes, encoders, connectors and so forth
  3383. */
  3384. rc = _sde_kms_drm_obj_init(sde_kms);
  3385. if (rc) {
  3386. SDE_ERROR("modeset init failed: %d\n", rc);
  3387. goto drm_obj_init_err;
  3388. }
  3389. return 0;
  3390. genpd_err:
  3391. drm_obj_init_err:
  3392. sde_core_perf_destroy(&sde_kms->perf);
  3393. hw_intr_init_err:
  3394. perf_err:
  3395. power_error:
  3396. return rc;
  3397. }
  3398. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3399. {
  3400. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3401. int rc = 0;
  3402. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3403. if (rc) {
  3404. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3405. return rc;
  3406. }
  3407. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3408. if (rc) {
  3409. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3410. return rc;
  3411. }
  3412. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3413. if (rc) {
  3414. SDE_ERROR("failed to get io irq for KMS");
  3415. return rc;
  3416. }
  3417. return rc;
  3418. }
  3419. static int sde_kms_hw_init(struct msm_kms *kms)
  3420. {
  3421. struct sde_kms *sde_kms;
  3422. struct drm_device *dev;
  3423. struct msm_drm_private *priv;
  3424. struct platform_device *platformdev;
  3425. int i, irq_num, rc = -EINVAL;
  3426. if (!kms) {
  3427. SDE_ERROR("invalid kms\n");
  3428. goto end;
  3429. }
  3430. sde_kms = to_sde_kms(kms);
  3431. dev = sde_kms->dev;
  3432. if (!dev || !dev->dev) {
  3433. SDE_ERROR("invalid device\n");
  3434. goto end;
  3435. }
  3436. platformdev = to_platform_device(dev->dev);
  3437. priv = dev->dev_private;
  3438. if (!priv) {
  3439. SDE_ERROR("invalid private data\n");
  3440. goto end;
  3441. }
  3442. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3443. if (rc)
  3444. goto error;
  3445. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3446. if (rc)
  3447. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3448. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3449. if (rc)
  3450. goto error;
  3451. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3452. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3453. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3454. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3455. mutex_init(&sde_kms->secure_transition_lock);
  3456. atomic_set(&sde_kms->detach_sec_cb, 0);
  3457. atomic_set(&sde_kms->detach_all_cb, 0);
  3458. atomic_set(&sde_kms->irq_vote_count, 0);
  3459. /*
  3460. * Support format modifiers for compression etc.
  3461. */
  3462. dev->mode_config.allow_fb_modifiers = true;
  3463. /*
  3464. * Handle (re)initializations during power enable
  3465. */
  3466. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3467. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3468. SDE_POWER_EVENT_POST_ENABLE |
  3469. SDE_POWER_EVENT_PRE_DISABLE,
  3470. sde_kms_handle_power_event, sde_kms, "kms");
  3471. if (sde_kms->splash_data.num_splash_displays) {
  3472. SDE_DEBUG("Skipping MDP Resources disable\n");
  3473. } else {
  3474. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3475. sde_power_data_bus_set_quota(&priv->phandle, i,
  3476. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3477. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3478. pm_runtime_put_sync(sde_kms->dev->dev);
  3479. }
  3480. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3481. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3482. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3483. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3484. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3485. if (sde_in_trusted_vm(sde_kms))
  3486. rc = sde_vm_trusted_init(sde_kms);
  3487. else
  3488. rc = sde_vm_primary_init(sde_kms);
  3489. if (rc) {
  3490. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3491. goto error;
  3492. }
  3493. return 0;
  3494. error:
  3495. _sde_kms_hw_destroy(sde_kms, platformdev);
  3496. end:
  3497. return rc;
  3498. }
  3499. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3500. {
  3501. struct msm_drm_private *priv;
  3502. struct sde_kms *sde_kms;
  3503. if (!dev || !dev->dev_private) {
  3504. SDE_ERROR("drm device node invalid\n");
  3505. return ERR_PTR(-EINVAL);
  3506. }
  3507. priv = dev->dev_private;
  3508. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3509. if (!sde_kms) {
  3510. SDE_ERROR("failed to allocate sde kms\n");
  3511. return ERR_PTR(-ENOMEM);
  3512. }
  3513. msm_kms_init(&sde_kms->base, &kms_funcs);
  3514. sde_kms->dev = dev;
  3515. return &sde_kms->base;
  3516. }
  3517. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3518. {
  3519. struct dsi_display *display;
  3520. struct sde_splash_display *handoff_display;
  3521. int i;
  3522. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3523. handoff_display = &sde_kms->splash_data.splash_display[i];
  3524. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3525. if (handoff_display->cont_splash_enabled)
  3526. _sde_kms_free_splash_display_data(sde_kms,
  3527. handoff_display);
  3528. dsi_display_set_active_state(display, false);
  3529. }
  3530. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3531. }
  3532. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms)
  3533. {
  3534. struct drm_device *dev;
  3535. struct msm_drm_private *priv;
  3536. struct sde_splash_display *handoff_display;
  3537. struct dsi_display *display;
  3538. struct sde_vm_ops *vm_ops;
  3539. int ret, i;
  3540. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3541. SDE_ERROR("invalid params\n");
  3542. return -EINVAL;
  3543. }
  3544. vm_ops = sde_vm_get_ops(sde_kms);
  3545. if (vm_ops && !vm_ops->vm_owns_hw(sde_kms)) {
  3546. SDE_DEBUG(
  3547. "skipping sde res init as device assign is not completed\n");
  3548. return 0;
  3549. }
  3550. if (sde_kms->dsi_display_count != 1) {
  3551. SDE_ERROR("no. of displays not supported:%d\n",
  3552. sde_kms->dsi_display_count);
  3553. return -EINVAL;
  3554. }
  3555. dev = sde_kms->dev;
  3556. priv = dev->dev_private;
  3557. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3558. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3559. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3560. &sde_kms->splash_data, sde_kms->catalog);
  3561. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3562. handoff_display = &sde_kms->splash_data.splash_display[i];
  3563. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3564. if (!handoff_display->cont_splash_enabled || ret)
  3565. _sde_kms_free_splash_display_data(sde_kms,
  3566. handoff_display);
  3567. else
  3568. dsi_display_set_active_state(display, true);
  3569. }
  3570. ret = sde_kms_cont_splash_config(&sde_kms->base);
  3571. if (ret) {
  3572. SDE_ERROR("error in setting handoff configs\n");
  3573. goto error;
  3574. }
  3575. /**
  3576. * fill-in vote for the continuous splash hanodff path, which will be
  3577. * removed on the successful first commit.
  3578. */
  3579. pm_runtime_get_sync(sde_kms->dev->dev);
  3580. return 0;
  3581. error:
  3582. sde_kms_vm_trusted_resource_deinit(sde_kms);
  3583. return ret;
  3584. }
  3585. static int _sde_kms_register_events(struct msm_kms *kms,
  3586. struct drm_mode_object *obj, u32 event, bool en)
  3587. {
  3588. int ret = 0;
  3589. struct drm_crtc *crtc = NULL;
  3590. struct drm_connector *conn = NULL;
  3591. struct sde_kms *sde_kms = NULL;
  3592. if (!kms || !obj) {
  3593. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3594. return -EINVAL;
  3595. }
  3596. sde_kms = to_sde_kms(kms);
  3597. switch (obj->type) {
  3598. case DRM_MODE_OBJECT_CRTC:
  3599. crtc = obj_to_crtc(obj);
  3600. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3601. break;
  3602. case DRM_MODE_OBJECT_CONNECTOR:
  3603. conn = obj_to_connector(obj);
  3604. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3605. en);
  3606. break;
  3607. }
  3608. return ret;
  3609. }
  3610. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3611. {
  3612. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3613. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3614. }