dp_tx.c 113 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #include "dp_internal.h"
  34. #ifdef FEATURE_WDS
  35. #include "dp_txrx_wds.h"
  36. #endif
  37. #define DP_TX_QUEUE_MASK 0x3
  38. /* TODO Add support in TSO */
  39. #define DP_DESC_NUM_FRAG(x) 0
  40. /* disable TQM_BYPASS */
  41. #define TQM_BYPASS_WAR 0
  42. /* invalid peer id for reinject*/
  43. #define DP_INVALID_PEER 0XFFFE
  44. /*mapping between hal encrypt type and cdp_sec_type*/
  45. #define MAX_CDP_SEC_TYPE 12
  46. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  47. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  48. HAL_TX_ENCRYPT_TYPE_WEP_128,
  49. HAL_TX_ENCRYPT_TYPE_WEP_104,
  50. HAL_TX_ENCRYPT_TYPE_WEP_40,
  51. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  52. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  53. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  54. HAL_TX_ENCRYPT_TYPE_WAPI,
  55. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  56. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  58. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  59. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  60. #include "dp_tx_capture.h"
  61. #endif
  62. /**
  63. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  64. * @vdev: DP Virtual device handle
  65. * @nbuf: Buffer pointer
  66. * @queue: queue ids container for nbuf
  67. *
  68. * TX packet queue has 2 instances, software descriptors id and dma ring id
  69. * Based on tx feature and hardware configuration queue id combination could be
  70. * different.
  71. * For example -
  72. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  73. * With no XPS,lock based resource protection, Descriptor pool ids are different
  74. * for each vdev, dma ring id will be same as single pdev id
  75. *
  76. * Return: None
  77. */
  78. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  79. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  80. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  81. {
  82. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  83. queue->desc_pool_id = queue_offset;
  84. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  85. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  86. "%s, pool_id:%d ring_id: %d",
  87. __func__, queue->desc_pool_id, queue->ring_id);
  88. return;
  89. }
  90. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  91. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  92. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  93. {
  94. /* get flow id */
  95. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  96. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  97. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  98. "%s, pool_id:%d ring_id: %d",
  99. __func__, queue->desc_pool_id, queue->ring_id);
  100. return;
  101. }
  102. #endif
  103. #if defined(FEATURE_TSO)
  104. /**
  105. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  106. *
  107. * @soc - core txrx main context
  108. * @seg_desc - tso segment descriptor
  109. * @num_seg_desc - tso number segment descriptor
  110. */
  111. static void dp_tx_tso_unmap_segment(
  112. struct dp_soc *soc,
  113. struct qdf_tso_seg_elem_t *seg_desc,
  114. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  115. {
  116. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  117. if (qdf_unlikely(!seg_desc)) {
  118. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  119. __func__, __LINE__);
  120. qdf_assert(0);
  121. } else if (qdf_unlikely(!num_seg_desc)) {
  122. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  123. __func__, __LINE__);
  124. qdf_assert(0);
  125. } else {
  126. bool is_last_seg;
  127. /* no tso segment left to do dma unmap */
  128. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  129. return;
  130. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  131. true : false;
  132. qdf_nbuf_unmap_tso_segment(soc->osdev,
  133. seg_desc, is_last_seg);
  134. num_seg_desc->num_seg.tso_cmn_num_seg--;
  135. }
  136. }
  137. /**
  138. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  139. * back to the freelist
  140. *
  141. * @soc - soc device handle
  142. * @tx_desc - Tx software descriptor
  143. */
  144. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  145. struct dp_tx_desc_s *tx_desc)
  146. {
  147. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  148. if (qdf_unlikely(!tx_desc->tso_desc)) {
  149. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  150. "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  154. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  155. "%s %d TSO num desc is NULL!",
  156. __func__, __LINE__);
  157. qdf_assert(0);
  158. } else {
  159. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  160. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  161. /* Add the tso num segment into the free list */
  162. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  163. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  164. tx_desc->tso_num_desc);
  165. tx_desc->tso_num_desc = NULL;
  166. }
  167. /* Add the tso segment into the free list*/
  168. dp_tx_tso_desc_free(soc,
  169. tx_desc->pool_id, tx_desc->tso_desc);
  170. tx_desc->tso_desc = NULL;
  171. }
  172. }
  173. #else
  174. static void dp_tx_tso_unmap_segment(
  175. struct dp_soc *soc,
  176. struct qdf_tso_seg_elem_t *seg_desc,
  177. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  178. {
  179. }
  180. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  181. struct dp_tx_desc_s *tx_desc)
  182. {
  183. }
  184. #endif
  185. /**
  186. * dp_tx_desc_release() - Release Tx Descriptor
  187. * @tx_desc : Tx Descriptor
  188. * @desc_pool_id: Descriptor Pool ID
  189. *
  190. * Deallocate all resources attached to Tx descriptor and free the Tx
  191. * descriptor.
  192. *
  193. * Return:
  194. */
  195. static void
  196. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  197. {
  198. struct dp_pdev *pdev = tx_desc->pdev;
  199. struct dp_soc *soc;
  200. uint8_t comp_status = 0;
  201. qdf_assert(pdev);
  202. soc = pdev->soc;
  203. if (tx_desc->frm_type == dp_tx_frm_tso)
  204. dp_tx_tso_desc_release(soc, tx_desc);
  205. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  206. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  207. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  208. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  209. qdf_atomic_dec(&pdev->num_tx_outstanding);
  210. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  211. qdf_atomic_dec(&pdev->num_tx_exception);
  212. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  213. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  214. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  215. soc->hal_soc);
  216. else
  217. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  218. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  219. "Tx Completion Release desc %d status %d outstanding %d",
  220. tx_desc->id, comp_status,
  221. qdf_atomic_read(&pdev->num_tx_outstanding));
  222. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  223. return;
  224. }
  225. /**
  226. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  227. * @vdev: DP vdev Handle
  228. * @nbuf: skb
  229. *
  230. * Prepares and fills HTT metadata in the frame pre-header for special frames
  231. * that should be transmitted using varying transmit parameters.
  232. * There are 2 VDEV modes that currently needs this special metadata -
  233. * 1) Mesh Mode
  234. * 2) DSRC Mode
  235. *
  236. * Return: HTT metadata size
  237. *
  238. */
  239. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  240. uint32_t *meta_data)
  241. {
  242. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  243. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  244. uint8_t htt_desc_size;
  245. /* Size rounded of multiple of 8 bytes */
  246. uint8_t htt_desc_size_aligned;
  247. uint8_t *hdr = NULL;
  248. /*
  249. * Metadata - HTT MSDU Extension header
  250. */
  251. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  252. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  253. if (vdev->mesh_vdev) {
  254. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  255. htt_desc_size_aligned)) {
  256. DP_STATS_INC(vdev,
  257. tx_i.dropped.headroom_insufficient, 1);
  258. return 0;
  259. }
  260. /* Fill and add HTT metaheader */
  261. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  262. if (!hdr) {
  263. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  264. "Error in filling HTT metadata");
  265. return 0;
  266. }
  267. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  268. } else if (vdev->opmode == wlan_op_mode_ocb) {
  269. /* Todo - Add support for DSRC */
  270. }
  271. return htt_desc_size_aligned;
  272. }
  273. /**
  274. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  275. * @tso_seg: TSO segment to process
  276. * @ext_desc: Pointer to MSDU extension descriptor
  277. *
  278. * Return: void
  279. */
  280. #if defined(FEATURE_TSO)
  281. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  282. void *ext_desc)
  283. {
  284. uint8_t num_frag;
  285. uint32_t tso_flags;
  286. /*
  287. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  288. * tcp_flag_mask
  289. *
  290. * Checksum enable flags are set in TCL descriptor and not in Extension
  291. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  292. */
  293. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  294. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  295. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  296. tso_seg->tso_flags.ip_len);
  297. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  298. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  299. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  300. uint32_t lo = 0;
  301. uint32_t hi = 0;
  302. qdf_dmaaddr_to_32s(
  303. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  304. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  305. tso_seg->tso_frags[num_frag].length);
  306. }
  307. return;
  308. }
  309. #else
  310. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  311. void *ext_desc)
  312. {
  313. return;
  314. }
  315. #endif
  316. #if defined(FEATURE_TSO)
  317. /**
  318. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  319. * allocated and free them
  320. *
  321. * @soc: soc handle
  322. * @free_seg: list of tso segments
  323. * @msdu_info: msdu descriptor
  324. *
  325. * Return - void
  326. */
  327. static void dp_tx_free_tso_seg_list(
  328. struct dp_soc *soc,
  329. struct qdf_tso_seg_elem_t *free_seg,
  330. struct dp_tx_msdu_info_s *msdu_info)
  331. {
  332. struct qdf_tso_seg_elem_t *next_seg;
  333. while (free_seg) {
  334. next_seg = free_seg->next;
  335. dp_tx_tso_desc_free(soc,
  336. msdu_info->tx_queue.desc_pool_id,
  337. free_seg);
  338. free_seg = next_seg;
  339. }
  340. }
  341. /**
  342. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  343. * allocated and free them
  344. *
  345. * @soc: soc handle
  346. * @free_num_seg: list of tso number segments
  347. * @msdu_info: msdu descriptor
  348. * Return - void
  349. */
  350. static void dp_tx_free_tso_num_seg_list(
  351. struct dp_soc *soc,
  352. struct qdf_tso_num_seg_elem_t *free_num_seg,
  353. struct dp_tx_msdu_info_s *msdu_info)
  354. {
  355. struct qdf_tso_num_seg_elem_t *next_num_seg;
  356. while (free_num_seg) {
  357. next_num_seg = free_num_seg->next;
  358. dp_tso_num_seg_free(soc,
  359. msdu_info->tx_queue.desc_pool_id,
  360. free_num_seg);
  361. free_num_seg = next_num_seg;
  362. }
  363. }
  364. /**
  365. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  366. * do dma unmap for each segment
  367. *
  368. * @soc: soc handle
  369. * @free_seg: list of tso segments
  370. * @num_seg_desc: tso number segment descriptor
  371. *
  372. * Return - void
  373. */
  374. static void dp_tx_unmap_tso_seg_list(
  375. struct dp_soc *soc,
  376. struct qdf_tso_seg_elem_t *free_seg,
  377. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  378. {
  379. struct qdf_tso_seg_elem_t *next_seg;
  380. if (qdf_unlikely(!num_seg_desc)) {
  381. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  382. return;
  383. }
  384. while (free_seg) {
  385. next_seg = free_seg->next;
  386. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  387. free_seg = next_seg;
  388. }
  389. }
  390. /**
  391. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  392. * free the tso segments descriptor and
  393. * tso num segments descriptor
  394. *
  395. * @soc: soc handle
  396. * @msdu_info: msdu descriptor
  397. * @tso_seg_unmap: flag to show if dma unmap is necessary
  398. *
  399. * Return - void
  400. */
  401. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  402. struct dp_tx_msdu_info_s *msdu_info,
  403. bool tso_seg_unmap)
  404. {
  405. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  406. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  407. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  408. tso_info->tso_num_seg_list;
  409. /* do dma unmap for each segment */
  410. if (tso_seg_unmap)
  411. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  412. /* free all tso number segment descriptor though looks only have 1 */
  413. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  414. /* free all tso segment descriptor */
  415. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  416. }
  417. /**
  418. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  419. * @vdev: virtual device handle
  420. * @msdu: network buffer
  421. * @msdu_info: meta data associated with the msdu
  422. *
  423. * Return: QDF_STATUS_SUCCESS success
  424. */
  425. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  426. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  427. {
  428. struct qdf_tso_seg_elem_t *tso_seg;
  429. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  430. struct dp_soc *soc = vdev->pdev->soc;
  431. struct qdf_tso_info_t *tso_info;
  432. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  433. tso_info = &msdu_info->u.tso_info;
  434. tso_info->curr_seg = NULL;
  435. tso_info->tso_seg_list = NULL;
  436. tso_info->num_segs = num_seg;
  437. msdu_info->frm_type = dp_tx_frm_tso;
  438. tso_info->tso_num_seg_list = NULL;
  439. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  440. while (num_seg) {
  441. tso_seg = dp_tx_tso_desc_alloc(
  442. soc, msdu_info->tx_queue.desc_pool_id);
  443. if (tso_seg) {
  444. tso_seg->next = tso_info->tso_seg_list;
  445. tso_info->tso_seg_list = tso_seg;
  446. num_seg--;
  447. } else {
  448. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  449. __func__);
  450. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  451. return QDF_STATUS_E_NOMEM;
  452. }
  453. }
  454. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  455. tso_num_seg = dp_tso_num_seg_alloc(soc,
  456. msdu_info->tx_queue.desc_pool_id);
  457. if (tso_num_seg) {
  458. tso_num_seg->next = tso_info->tso_num_seg_list;
  459. tso_info->tso_num_seg_list = tso_num_seg;
  460. } else {
  461. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  462. __func__);
  463. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  464. return QDF_STATUS_E_NOMEM;
  465. }
  466. msdu_info->num_seg =
  467. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  468. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  469. msdu_info->num_seg);
  470. if (!(msdu_info->num_seg)) {
  471. /*
  472. * Free allocated TSO seg desc and number seg desc,
  473. * do unmap for segments if dma map has done.
  474. */
  475. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  476. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  477. return QDF_STATUS_E_INVAL;
  478. }
  479. tso_info->curr_seg = tso_info->tso_seg_list;
  480. return QDF_STATUS_SUCCESS;
  481. }
  482. #else
  483. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  484. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  485. {
  486. return QDF_STATUS_E_NOMEM;
  487. }
  488. #endif
  489. /**
  490. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  491. * @vdev: DP Vdev handle
  492. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  493. * @desc_pool_id: Descriptor Pool ID
  494. *
  495. * Return:
  496. */
  497. static
  498. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  499. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  500. {
  501. uint8_t i;
  502. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  503. struct dp_tx_seg_info_s *seg_info;
  504. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  505. struct dp_soc *soc = vdev->pdev->soc;
  506. /* Allocate an extension descriptor */
  507. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  508. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  509. if (!msdu_ext_desc) {
  510. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  511. return NULL;
  512. }
  513. if (msdu_info->exception_fw &&
  514. qdf_unlikely(vdev->mesh_vdev)) {
  515. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  516. &msdu_info->meta_data[0],
  517. sizeof(struct htt_tx_msdu_desc_ext2_t));
  518. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  519. }
  520. switch (msdu_info->frm_type) {
  521. case dp_tx_frm_sg:
  522. case dp_tx_frm_me:
  523. case dp_tx_frm_raw:
  524. seg_info = msdu_info->u.sg_info.curr_seg;
  525. /* Update the buffer pointers in MSDU Extension Descriptor */
  526. for (i = 0; i < seg_info->frag_cnt; i++) {
  527. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  528. seg_info->frags[i].paddr_lo,
  529. seg_info->frags[i].paddr_hi,
  530. seg_info->frags[i].len);
  531. }
  532. break;
  533. case dp_tx_frm_tso:
  534. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  535. &cached_ext_desc[0]);
  536. break;
  537. default:
  538. break;
  539. }
  540. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  541. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  542. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  543. msdu_ext_desc->vaddr);
  544. return msdu_ext_desc;
  545. }
  546. /**
  547. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  548. *
  549. * @skb: skb to be traced
  550. * @msdu_id: msdu_id of the packet
  551. * @vdev_id: vdev_id of the packet
  552. *
  553. * Return: None
  554. */
  555. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  556. uint8_t vdev_id)
  557. {
  558. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  559. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  560. DPTRACE(qdf_dp_trace_ptr(skb,
  561. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  562. QDF_TRACE_DEFAULT_PDEV_ID,
  563. qdf_nbuf_data_addr(skb),
  564. sizeof(qdf_nbuf_data(skb)),
  565. msdu_id, vdev_id));
  566. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  567. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  568. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  569. msdu_id, QDF_TX));
  570. }
  571. #ifdef QCA_512M_CONFIG
  572. /**
  573. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  574. * tx descriptor configured value
  575. * @vdev: DP vdev handle
  576. *
  577. * Return: true if allocated tx descriptors reached max configured value, else
  578. * false.
  579. */
  580. static inline bool
  581. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  582. {
  583. struct dp_pdev *pdev = vdev->pdev;
  584. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  585. pdev->num_tx_allowed) {
  586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  587. "%s: queued packets are more than max tx, drop the frame",
  588. __func__);
  589. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  590. return true;
  591. }
  592. return false;
  593. }
  594. #else
  595. static inline bool
  596. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  597. {
  598. return false;
  599. }
  600. #endif
  601. /**
  602. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  603. * @vdev: DP vdev handle
  604. * @nbuf: skb
  605. * @desc_pool_id: Descriptor pool ID
  606. * @meta_data: Metadata to the fw
  607. * @tx_exc_metadata: Handle that holds exception path metadata
  608. * Allocate and prepare Tx descriptor with msdu information.
  609. *
  610. * Return: Pointer to Tx Descriptor on success,
  611. * NULL on failure
  612. */
  613. static
  614. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  615. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  616. struct dp_tx_msdu_info_s *msdu_info,
  617. struct cdp_tx_exception_metadata *tx_exc_metadata)
  618. {
  619. uint8_t align_pad;
  620. uint8_t is_exception = 0;
  621. uint8_t htt_hdr_size;
  622. qdf_ether_header_t *eh;
  623. struct dp_tx_desc_s *tx_desc;
  624. struct dp_pdev *pdev = vdev->pdev;
  625. struct dp_soc *soc = pdev->soc;
  626. if (dp_tx_pdev_pflow_control(vdev))
  627. return NULL;
  628. /* Allocate software Tx descriptor */
  629. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  630. if (qdf_unlikely(!tx_desc)) {
  631. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  632. return NULL;
  633. }
  634. /* Flow control/Congestion Control counters */
  635. qdf_atomic_inc(&pdev->num_tx_outstanding);
  636. /* Initialize the SW tx descriptor */
  637. tx_desc->nbuf = nbuf;
  638. tx_desc->frm_type = dp_tx_frm_std;
  639. tx_desc->tx_encap_type = (tx_exc_metadata ?
  640. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  641. tx_desc->vdev = vdev;
  642. tx_desc->pdev = pdev;
  643. tx_desc->msdu_ext_desc = NULL;
  644. tx_desc->pkt_offset = 0;
  645. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  646. /*
  647. * For special modes (vdev_type == ocb or mesh), data frames should be
  648. * transmitted using varying transmit parameters (tx spec) which include
  649. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  650. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  651. * These frames are sent as exception packets to firmware.
  652. *
  653. * HW requirement is that metadata should always point to a
  654. * 8-byte aligned address. So we add alignment pad to start of buffer.
  655. * HTT Metadata should be ensured to be multiple of 8-bytes,
  656. * to get 8-byte aligned start address along with align_pad added
  657. *
  658. * |-----------------------------|
  659. * | |
  660. * |-----------------------------| <-----Buffer Pointer Address given
  661. * | | ^ in HW descriptor (aligned)
  662. * | HTT Metadata | |
  663. * | | |
  664. * | | | Packet Offset given in descriptor
  665. * | | |
  666. * |-----------------------------| |
  667. * | Alignment Pad | v
  668. * |-----------------------------| <----- Actual buffer start address
  669. * | SKB Data | (Unaligned)
  670. * | |
  671. * | |
  672. * | |
  673. * | |
  674. * | |
  675. * |-----------------------------|
  676. */
  677. if (qdf_unlikely((msdu_info->exception_fw)) ||
  678. (vdev->opmode == wlan_op_mode_ocb)) {
  679. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  680. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  681. DP_STATS_INC(vdev,
  682. tx_i.dropped.headroom_insufficient, 1);
  683. goto failure;
  684. }
  685. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  686. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  687. "qdf_nbuf_push_head failed");
  688. goto failure;
  689. }
  690. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  691. msdu_info->meta_data);
  692. if (htt_hdr_size == 0)
  693. goto failure;
  694. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  695. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  696. is_exception = 1;
  697. }
  698. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  699. qdf_nbuf_map(soc->osdev, nbuf,
  700. QDF_DMA_TO_DEVICE))) {
  701. /* Handle failure */
  702. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  703. "qdf_nbuf_map failed");
  704. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  705. goto failure;
  706. }
  707. if (qdf_unlikely(vdev->nawds_enabled)) {
  708. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  709. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  710. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  711. is_exception = 1;
  712. }
  713. }
  714. #if !TQM_BYPASS_WAR
  715. if (is_exception || tx_exc_metadata)
  716. #endif
  717. {
  718. /* Temporary WAR due to TQM VP issues */
  719. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  720. qdf_atomic_inc(&pdev->num_tx_exception);
  721. }
  722. return tx_desc;
  723. failure:
  724. dp_tx_desc_release(tx_desc, desc_pool_id);
  725. return NULL;
  726. }
  727. /**
  728. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  729. * @vdev: DP vdev handle
  730. * @nbuf: skb
  731. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  732. * @desc_pool_id : Descriptor Pool ID
  733. *
  734. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  735. * information. For frames wth fragments, allocate and prepare
  736. * an MSDU extension descriptor
  737. *
  738. * Return: Pointer to Tx Descriptor on success,
  739. * NULL on failure
  740. */
  741. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  742. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  743. uint8_t desc_pool_id)
  744. {
  745. struct dp_tx_desc_s *tx_desc;
  746. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  747. struct dp_pdev *pdev = vdev->pdev;
  748. struct dp_soc *soc = pdev->soc;
  749. if (dp_tx_pdev_pflow_control(vdev))
  750. return NULL;
  751. /* Allocate software Tx descriptor */
  752. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  753. if (!tx_desc) {
  754. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  755. return NULL;
  756. }
  757. /* Flow control/Congestion Control counters */
  758. qdf_atomic_inc(&pdev->num_tx_outstanding);
  759. /* Initialize the SW tx descriptor */
  760. tx_desc->nbuf = nbuf;
  761. tx_desc->frm_type = msdu_info->frm_type;
  762. tx_desc->tx_encap_type = vdev->tx_encap_type;
  763. tx_desc->vdev = vdev;
  764. tx_desc->pdev = pdev;
  765. tx_desc->pkt_offset = 0;
  766. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  767. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  768. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  769. /* Handle scattered frames - TSO/SG/ME */
  770. /* Allocate and prepare an extension descriptor for scattered frames */
  771. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  772. if (!msdu_ext_desc) {
  773. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  774. "%s Tx Extension Descriptor Alloc Fail",
  775. __func__);
  776. goto failure;
  777. }
  778. #if TQM_BYPASS_WAR
  779. /* Temporary WAR due to TQM VP issues */
  780. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  781. qdf_atomic_inc(&pdev->num_tx_exception);
  782. #endif
  783. if (qdf_unlikely(msdu_info->exception_fw))
  784. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  785. tx_desc->msdu_ext_desc = msdu_ext_desc;
  786. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  787. return tx_desc;
  788. failure:
  789. dp_tx_desc_release(tx_desc, desc_pool_id);
  790. return NULL;
  791. }
  792. /**
  793. * dp_tx_prepare_raw() - Prepare RAW packet TX
  794. * @vdev: DP vdev handle
  795. * @nbuf: buffer pointer
  796. * @seg_info: Pointer to Segment info Descriptor to be prepared
  797. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  798. * descriptor
  799. *
  800. * Return:
  801. */
  802. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  803. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  804. {
  805. qdf_nbuf_t curr_nbuf = NULL;
  806. uint16_t total_len = 0;
  807. qdf_dma_addr_t paddr;
  808. int32_t i;
  809. int32_t mapped_buf_num = 0;
  810. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  811. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  812. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  813. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  814. if (vdev->raw_mode_war &&
  815. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  816. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  817. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  818. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  819. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  820. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  821. QDF_DMA_TO_DEVICE)) {
  822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  823. "%s dma map error ", __func__);
  824. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  825. mapped_buf_num = i;
  826. goto error;
  827. }
  828. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  829. seg_info->frags[i].paddr_lo = paddr;
  830. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  831. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  832. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  833. total_len += qdf_nbuf_len(curr_nbuf);
  834. }
  835. seg_info->frag_cnt = i;
  836. seg_info->total_len = total_len;
  837. seg_info->next = NULL;
  838. sg_info->curr_seg = seg_info;
  839. msdu_info->frm_type = dp_tx_frm_raw;
  840. msdu_info->num_seg = 1;
  841. return nbuf;
  842. error:
  843. i = 0;
  844. while (nbuf) {
  845. curr_nbuf = nbuf;
  846. if (i < mapped_buf_num) {
  847. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  848. i++;
  849. }
  850. nbuf = qdf_nbuf_next(nbuf);
  851. qdf_nbuf_free(curr_nbuf);
  852. }
  853. return NULL;
  854. }
  855. /**
  856. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  857. * @soc: DP Soc Handle
  858. * @vdev: DP vdev handle
  859. * @tx_desc: Tx Descriptor Handle
  860. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  861. * @fw_metadata: Metadata to send to Target Firmware along with frame
  862. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  863. * @tx_exc_metadata: Handle that holds exception path meta data
  864. *
  865. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  866. * from software Tx descriptor
  867. *
  868. * Return:
  869. */
  870. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  871. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  872. uint16_t fw_metadata, uint8_t ring_id,
  873. struct cdp_tx_exception_metadata
  874. *tx_exc_metadata)
  875. {
  876. uint8_t type;
  877. uint16_t length;
  878. void *hal_tx_desc, *hal_tx_desc_cached;
  879. qdf_dma_addr_t dma_addr;
  880. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  881. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  882. tx_exc_metadata->sec_type : vdev->sec_type);
  883. /* Return Buffer Manager ID */
  884. uint8_t bm_id = ring_id;
  885. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  886. hal_tx_desc_cached = (void *) cached_desc;
  887. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  888. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  889. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  890. type = HAL_TX_BUF_TYPE_EXT_DESC;
  891. dma_addr = tx_desc->msdu_ext_desc->paddr;
  892. } else {
  893. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  894. type = HAL_TX_BUF_TYPE_BUFFER;
  895. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  896. }
  897. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  898. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  899. dma_addr, bm_id, tx_desc->id,
  900. type, soc->hal_soc);
  901. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  902. return QDF_STATUS_E_RESOURCES;
  903. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  904. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  905. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  906. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  907. vdev->pdev->lmac_id);
  908. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  909. vdev->search_type);
  910. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  911. vdev->bss_ast_hash);
  912. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  913. vdev->dscp_tid_map_id);
  914. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  915. sec_type_map[sec_type]);
  916. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  917. length, type, (uint64_t)dma_addr,
  918. tx_desc->pkt_offset, tx_desc->id);
  919. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  920. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  921. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  922. vdev->hal_desc_addr_search_flags);
  923. /* verify checksum offload configuration*/
  924. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  925. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  926. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  927. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  928. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  929. }
  930. if (tid != HTT_TX_EXT_TID_INVALID)
  931. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  932. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  933. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  934. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  935. /* Sync cached descriptor with HW */
  936. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  937. if (!hal_tx_desc) {
  938. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  939. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  940. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  941. return QDF_STATUS_E_RESOURCES;
  942. }
  943. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  944. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  945. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  946. return QDF_STATUS_SUCCESS;
  947. }
  948. /**
  949. * dp_cce_classify() - Classify the frame based on CCE rules
  950. * @vdev: DP vdev handle
  951. * @nbuf: skb
  952. *
  953. * Classify frames based on CCE rules
  954. * Return: bool( true if classified,
  955. * else false)
  956. */
  957. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  958. {
  959. qdf_ether_header_t *eh = NULL;
  960. uint16_t ether_type;
  961. qdf_llc_t *llcHdr;
  962. qdf_nbuf_t nbuf_clone = NULL;
  963. qdf_dot3_qosframe_t *qos_wh = NULL;
  964. /* for mesh packets don't do any classification */
  965. if (qdf_unlikely(vdev->mesh_vdev))
  966. return false;
  967. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  968. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  969. ether_type = eh->ether_type;
  970. llcHdr = (qdf_llc_t *)(nbuf->data +
  971. sizeof(qdf_ether_header_t));
  972. } else {
  973. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  974. /* For encrypted packets don't do any classification */
  975. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  976. return false;
  977. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  978. if (qdf_unlikely(
  979. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  980. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  981. ether_type = *(uint16_t *)(nbuf->data
  982. + QDF_IEEE80211_4ADDR_HDR_LEN
  983. + sizeof(qdf_llc_t)
  984. - sizeof(ether_type));
  985. llcHdr = (qdf_llc_t *)(nbuf->data +
  986. QDF_IEEE80211_4ADDR_HDR_LEN);
  987. } else {
  988. ether_type = *(uint16_t *)(nbuf->data
  989. + QDF_IEEE80211_3ADDR_HDR_LEN
  990. + sizeof(qdf_llc_t)
  991. - sizeof(ether_type));
  992. llcHdr = (qdf_llc_t *)(nbuf->data +
  993. QDF_IEEE80211_3ADDR_HDR_LEN);
  994. }
  995. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  996. && (ether_type ==
  997. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  998. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  999. return true;
  1000. }
  1001. }
  1002. return false;
  1003. }
  1004. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1005. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1006. sizeof(*llcHdr));
  1007. nbuf_clone = qdf_nbuf_clone(nbuf);
  1008. if (qdf_unlikely(nbuf_clone)) {
  1009. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1010. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1011. qdf_nbuf_pull_head(nbuf_clone,
  1012. sizeof(qdf_net_vlanhdr_t));
  1013. }
  1014. }
  1015. } else {
  1016. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1017. nbuf_clone = qdf_nbuf_clone(nbuf);
  1018. if (qdf_unlikely(nbuf_clone)) {
  1019. qdf_nbuf_pull_head(nbuf_clone,
  1020. sizeof(qdf_net_vlanhdr_t));
  1021. }
  1022. }
  1023. }
  1024. if (qdf_unlikely(nbuf_clone))
  1025. nbuf = nbuf_clone;
  1026. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1027. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1028. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1029. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1030. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1031. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1032. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1033. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1034. if (qdf_unlikely(nbuf_clone))
  1035. qdf_nbuf_free(nbuf_clone);
  1036. return true;
  1037. }
  1038. if (qdf_unlikely(nbuf_clone))
  1039. qdf_nbuf_free(nbuf_clone);
  1040. return false;
  1041. }
  1042. /**
  1043. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1044. * @vdev: DP vdev handle
  1045. * @nbuf: skb
  1046. *
  1047. * Extract the DSCP or PCP information from frame and map into TID value.
  1048. *
  1049. * Return: void
  1050. */
  1051. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1052. struct dp_tx_msdu_info_s *msdu_info)
  1053. {
  1054. uint8_t tos = 0, dscp_tid_override = 0;
  1055. uint8_t *hdr_ptr, *L3datap;
  1056. uint8_t is_mcast = 0;
  1057. qdf_ether_header_t *eh = NULL;
  1058. qdf_ethervlan_header_t *evh = NULL;
  1059. uint16_t ether_type;
  1060. qdf_llc_t *llcHdr;
  1061. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1062. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1063. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1064. eh = (qdf_ether_header_t *)nbuf->data;
  1065. hdr_ptr = eh->ether_dhost;
  1066. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1067. } else {
  1068. qdf_dot3_qosframe_t *qos_wh =
  1069. (qdf_dot3_qosframe_t *) nbuf->data;
  1070. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1071. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1072. return;
  1073. }
  1074. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1075. ether_type = eh->ether_type;
  1076. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1077. /*
  1078. * Check if packet is dot3 or eth2 type.
  1079. */
  1080. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1081. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1082. sizeof(*llcHdr));
  1083. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1084. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1085. sizeof(*llcHdr);
  1086. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1087. + sizeof(*llcHdr) +
  1088. sizeof(qdf_net_vlanhdr_t));
  1089. } else {
  1090. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1091. sizeof(*llcHdr);
  1092. }
  1093. } else {
  1094. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1095. evh = (qdf_ethervlan_header_t *) eh;
  1096. ether_type = evh->ether_type;
  1097. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1098. }
  1099. }
  1100. /*
  1101. * Find priority from IP TOS DSCP field
  1102. */
  1103. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1104. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1105. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1106. /* Only for unicast frames */
  1107. if (!is_mcast) {
  1108. /* send it on VO queue */
  1109. msdu_info->tid = DP_VO_TID;
  1110. }
  1111. } else {
  1112. /*
  1113. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1114. * from TOS byte.
  1115. */
  1116. tos = ip->ip_tos;
  1117. dscp_tid_override = 1;
  1118. }
  1119. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1120. /* TODO
  1121. * use flowlabel
  1122. *igmpmld cases to be handled in phase 2
  1123. */
  1124. unsigned long ver_pri_flowlabel;
  1125. unsigned long pri;
  1126. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1127. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1128. DP_IPV6_PRIORITY_SHIFT;
  1129. tos = pri;
  1130. dscp_tid_override = 1;
  1131. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1132. msdu_info->tid = DP_VO_TID;
  1133. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1134. /* Only for unicast frames */
  1135. if (!is_mcast) {
  1136. /* send ucast arp on VO queue */
  1137. msdu_info->tid = DP_VO_TID;
  1138. }
  1139. }
  1140. /*
  1141. * Assign all MCAST packets to BE
  1142. */
  1143. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1144. if (is_mcast) {
  1145. tos = 0;
  1146. dscp_tid_override = 1;
  1147. }
  1148. }
  1149. if (dscp_tid_override == 1) {
  1150. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1151. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1152. }
  1153. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1154. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1155. return;
  1156. }
  1157. /**
  1158. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1159. * @vdev: DP vdev handle
  1160. * @nbuf: skb
  1161. *
  1162. * Software based TID classification is required when more than 2 DSCP-TID
  1163. * mapping tables are needed.
  1164. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1165. *
  1166. * Return: void
  1167. */
  1168. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1169. struct dp_tx_msdu_info_s *msdu_info)
  1170. {
  1171. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1172. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1173. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1174. return;
  1175. /* for mesh packets don't do any classification */
  1176. if (qdf_unlikely(vdev->mesh_vdev))
  1177. return;
  1178. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1179. }
  1180. #ifdef FEATURE_WLAN_TDLS
  1181. /**
  1182. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1183. * @tx_desc: TX descriptor
  1184. *
  1185. * Return: None
  1186. */
  1187. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1188. {
  1189. if (tx_desc->vdev) {
  1190. if (tx_desc->vdev->is_tdls_frame) {
  1191. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1192. tx_desc->vdev->is_tdls_frame = false;
  1193. }
  1194. }
  1195. }
  1196. /**
  1197. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1198. * @tx_desc: TX descriptor
  1199. * @vdev: datapath vdev handle
  1200. *
  1201. * Return: None
  1202. */
  1203. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1204. struct dp_vdev *vdev)
  1205. {
  1206. struct hal_tx_completion_status ts = {0};
  1207. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1208. if (qdf_unlikely(!vdev)) {
  1209. dp_err("vdev is null!");
  1210. return;
  1211. }
  1212. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1213. if (vdev->tx_non_std_data_callback.func) {
  1214. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1215. vdev->tx_non_std_data_callback.func(
  1216. vdev->tx_non_std_data_callback.ctxt,
  1217. nbuf, ts.status);
  1218. return;
  1219. }
  1220. }
  1221. #else
  1222. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1223. {
  1224. }
  1225. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1226. struct dp_vdev *vdev)
  1227. {
  1228. }
  1229. #endif
  1230. /**
  1231. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1232. * @vdev: DP vdev handle
  1233. * @nbuf: skb
  1234. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1235. * @meta_data: Metadata to the fw
  1236. * @tx_q: Tx queue to be used for this Tx frame
  1237. * @peer_id: peer_id of the peer in case of NAWDS frames
  1238. * @tx_exc_metadata: Handle that holds exception path metadata
  1239. *
  1240. * Return: NULL on success,
  1241. * nbuf when it fails to send
  1242. */
  1243. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1244. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1245. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1246. {
  1247. struct dp_pdev *pdev = vdev->pdev;
  1248. struct dp_soc *soc = pdev->soc;
  1249. struct dp_tx_desc_s *tx_desc;
  1250. QDF_STATUS status;
  1251. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1252. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1253. uint16_t htt_tcl_metadata = 0;
  1254. uint8_t tid = msdu_info->tid;
  1255. struct cdp_tid_tx_stats *tid_stats = NULL;
  1256. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1257. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1258. msdu_info, tx_exc_metadata);
  1259. if (!tx_desc) {
  1260. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1261. vdev, tx_q->desc_pool_id);
  1262. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1263. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1264. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1265. return nbuf;
  1266. }
  1267. if (qdf_unlikely(soc->cce_disable)) {
  1268. if (dp_cce_classify(vdev, nbuf) == true) {
  1269. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1270. tid = DP_VO_TID;
  1271. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1272. }
  1273. }
  1274. dp_tx_update_tdls_flags(tx_desc);
  1275. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1276. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1277. "%s %d : HAL RING Access Failed -- %pK",
  1278. __func__, __LINE__, hal_srng);
  1279. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1280. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1281. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1282. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1283. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1284. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1285. goto fail_return;
  1286. }
  1287. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1288. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1289. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1290. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1291. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1292. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1293. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1294. peer_id);
  1295. } else
  1296. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1297. if (msdu_info->exception_fw) {
  1298. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1299. }
  1300. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1301. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1302. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1303. if (status != QDF_STATUS_SUCCESS) {
  1304. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1305. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1306. __func__, tx_desc, tx_q->ring_id);
  1307. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1308. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1309. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1310. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1311. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1312. goto fail_return;
  1313. }
  1314. nbuf = NULL;
  1315. fail_return:
  1316. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1317. hal_srng_access_end(soc->hal_soc, hal_srng);
  1318. hif_pm_runtime_put(soc->hif_handle);
  1319. } else {
  1320. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1321. }
  1322. return nbuf;
  1323. }
  1324. /**
  1325. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1326. * @vdev: DP vdev handle
  1327. * @nbuf: skb
  1328. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1329. *
  1330. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1331. *
  1332. * Return: NULL on success,
  1333. * nbuf when it fails to send
  1334. */
  1335. #if QDF_LOCK_STATS
  1336. static noinline
  1337. #else
  1338. static
  1339. #endif
  1340. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1341. struct dp_tx_msdu_info_s *msdu_info)
  1342. {
  1343. uint8_t i;
  1344. struct dp_pdev *pdev = vdev->pdev;
  1345. struct dp_soc *soc = pdev->soc;
  1346. struct dp_tx_desc_s *tx_desc;
  1347. bool is_cce_classified = false;
  1348. QDF_STATUS status;
  1349. uint16_t htt_tcl_metadata = 0;
  1350. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1351. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1352. struct cdp_tid_tx_stats *tid_stats = NULL;
  1353. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1354. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1355. "%s %d : HAL RING Access Failed -- %pK",
  1356. __func__, __LINE__, hal_srng);
  1357. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1358. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1359. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1360. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1361. return nbuf;
  1362. }
  1363. if (qdf_unlikely(soc->cce_disable)) {
  1364. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1365. if (is_cce_classified) {
  1366. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1367. msdu_info->tid = DP_VO_TID;
  1368. }
  1369. }
  1370. if (msdu_info->frm_type == dp_tx_frm_me)
  1371. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1372. i = 0;
  1373. /* Print statement to track i and num_seg */
  1374. /*
  1375. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1376. * descriptors using information in msdu_info
  1377. */
  1378. while (i < msdu_info->num_seg) {
  1379. /*
  1380. * Setup Tx descriptor for an MSDU, and MSDU extension
  1381. * descriptor
  1382. */
  1383. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1384. tx_q->desc_pool_id);
  1385. if (!tx_desc) {
  1386. if (msdu_info->frm_type == dp_tx_frm_me) {
  1387. dp_tx_me_free_buf(pdev,
  1388. (void *)(msdu_info->u.sg_info
  1389. .curr_seg->frags[0].vaddr));
  1390. }
  1391. goto done;
  1392. }
  1393. if (msdu_info->frm_type == dp_tx_frm_me) {
  1394. tx_desc->me_buffer =
  1395. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1396. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1397. }
  1398. if (is_cce_classified)
  1399. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1400. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1401. if (msdu_info->exception_fw) {
  1402. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1403. }
  1404. /*
  1405. * Enqueue the Tx MSDU descriptor to HW for transmit
  1406. */
  1407. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1408. htt_tcl_metadata, tx_q->ring_id, NULL);
  1409. if (status != QDF_STATUS_SUCCESS) {
  1410. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1411. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1412. __func__, tx_desc, tx_q->ring_id);
  1413. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1414. tid_stats = &pdev->stats.tid_stats.
  1415. tid_tx_stats[msdu_info->tid];
  1416. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1417. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1418. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1419. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1420. goto done;
  1421. }
  1422. /*
  1423. * TODO
  1424. * if tso_info structure can be modified to have curr_seg
  1425. * as first element, following 2 blocks of code (for TSO and SG)
  1426. * can be combined into 1
  1427. */
  1428. /*
  1429. * For frames with multiple segments (TSO, ME), jump to next
  1430. * segment.
  1431. */
  1432. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1433. if (msdu_info->u.tso_info.curr_seg->next) {
  1434. msdu_info->u.tso_info.curr_seg =
  1435. msdu_info->u.tso_info.curr_seg->next;
  1436. /*
  1437. * If this is a jumbo nbuf, then increment the number of
  1438. * nbuf users for each additional segment of the msdu.
  1439. * This will ensure that the skb is freed only after
  1440. * receiving tx completion for all segments of an nbuf
  1441. */
  1442. qdf_nbuf_inc_users(nbuf);
  1443. /* Check with MCL if this is needed */
  1444. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1445. }
  1446. }
  1447. /*
  1448. * For Multicast-Unicast converted packets,
  1449. * each converted frame (for a client) is represented as
  1450. * 1 segment
  1451. */
  1452. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1453. (msdu_info->frm_type == dp_tx_frm_me)) {
  1454. if (msdu_info->u.sg_info.curr_seg->next) {
  1455. msdu_info->u.sg_info.curr_seg =
  1456. msdu_info->u.sg_info.curr_seg->next;
  1457. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1458. }
  1459. }
  1460. i++;
  1461. }
  1462. nbuf = NULL;
  1463. done:
  1464. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1465. hal_srng_access_end(soc->hal_soc, hal_srng);
  1466. hif_pm_runtime_put(soc->hif_handle);
  1467. } else {
  1468. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1469. }
  1470. return nbuf;
  1471. }
  1472. /**
  1473. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1474. * for SG frames
  1475. * @vdev: DP vdev handle
  1476. * @nbuf: skb
  1477. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1478. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1479. *
  1480. * Return: NULL on success,
  1481. * nbuf when it fails to send
  1482. */
  1483. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1484. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1485. {
  1486. uint32_t cur_frag, nr_frags;
  1487. qdf_dma_addr_t paddr;
  1488. struct dp_tx_sg_info_s *sg_info;
  1489. sg_info = &msdu_info->u.sg_info;
  1490. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1491. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1492. QDF_DMA_TO_DEVICE)) {
  1493. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1494. "dma map error");
  1495. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1496. qdf_nbuf_free(nbuf);
  1497. return NULL;
  1498. }
  1499. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1500. seg_info->frags[0].paddr_lo = paddr;
  1501. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1502. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1503. seg_info->frags[0].vaddr = (void *) nbuf;
  1504. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1505. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1506. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1507. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1508. "frag dma map error");
  1509. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1510. qdf_nbuf_free(nbuf);
  1511. return NULL;
  1512. }
  1513. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1514. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1515. seg_info->frags[cur_frag + 1].paddr_hi =
  1516. ((uint64_t) paddr) >> 32;
  1517. seg_info->frags[cur_frag + 1].len =
  1518. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1519. }
  1520. seg_info->frag_cnt = (cur_frag + 1);
  1521. seg_info->total_len = qdf_nbuf_len(nbuf);
  1522. seg_info->next = NULL;
  1523. sg_info->curr_seg = seg_info;
  1524. msdu_info->frm_type = dp_tx_frm_sg;
  1525. msdu_info->num_seg = 1;
  1526. return nbuf;
  1527. }
  1528. #ifdef MESH_MODE_SUPPORT
  1529. /**
  1530. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1531. and prepare msdu_info for mesh frames.
  1532. * @vdev: DP vdev handle
  1533. * @nbuf: skb
  1534. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1535. *
  1536. * Return: NULL on failure,
  1537. * nbuf when extracted successfully
  1538. */
  1539. static
  1540. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1541. struct dp_tx_msdu_info_s *msdu_info)
  1542. {
  1543. struct meta_hdr_s *mhdr;
  1544. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1545. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1546. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1547. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1548. msdu_info->exception_fw = 0;
  1549. goto remove_meta_hdr;
  1550. }
  1551. msdu_info->exception_fw = 1;
  1552. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1553. meta_data->host_tx_desc_pool = 1;
  1554. meta_data->update_peer_cache = 1;
  1555. meta_data->learning_frame = 1;
  1556. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1557. meta_data->power = mhdr->power;
  1558. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1559. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1560. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1561. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1562. meta_data->dyn_bw = 1;
  1563. meta_data->valid_pwr = 1;
  1564. meta_data->valid_mcs_mask = 1;
  1565. meta_data->valid_nss_mask = 1;
  1566. meta_data->valid_preamble_type = 1;
  1567. meta_data->valid_retries = 1;
  1568. meta_data->valid_bw_info = 1;
  1569. }
  1570. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1571. meta_data->encrypt_type = 0;
  1572. meta_data->valid_encrypt_type = 1;
  1573. meta_data->learning_frame = 0;
  1574. }
  1575. meta_data->valid_key_flags = 1;
  1576. meta_data->key_flags = (mhdr->keyix & 0x3);
  1577. remove_meta_hdr:
  1578. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1579. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1580. "qdf_nbuf_pull_head failed");
  1581. qdf_nbuf_free(nbuf);
  1582. return NULL;
  1583. }
  1584. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1586. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1587. " tid %d to_fw %d",
  1588. __func__, msdu_info->meta_data[0],
  1589. msdu_info->meta_data[1],
  1590. msdu_info->meta_data[2],
  1591. msdu_info->meta_data[3],
  1592. msdu_info->meta_data[4],
  1593. msdu_info->meta_data[5],
  1594. msdu_info->tid, msdu_info->exception_fw);
  1595. return nbuf;
  1596. }
  1597. #else
  1598. static
  1599. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1600. struct dp_tx_msdu_info_s *msdu_info)
  1601. {
  1602. return nbuf;
  1603. }
  1604. #endif
  1605. /**
  1606. * dp_check_exc_metadata() - Checks if parameters are valid
  1607. * @tx_exc - holds all exception path parameters
  1608. *
  1609. * Returns true when all the parameters are valid else false
  1610. *
  1611. */
  1612. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1613. {
  1614. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1615. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1616. tx_exc->sec_type > cdp_num_sec_types) {
  1617. return false;
  1618. }
  1619. return true;
  1620. }
  1621. /**
  1622. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1623. * @vap_dev: DP vdev handle
  1624. * @nbuf: skb
  1625. * @tx_exc_metadata: Handle that holds exception path meta data
  1626. *
  1627. * Entry point for Core Tx layer (DP_TX) invoked from
  1628. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1629. *
  1630. * Return: NULL on success,
  1631. * nbuf when it fails to send
  1632. */
  1633. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1634. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1635. {
  1636. qdf_ether_header_t *eh = NULL;
  1637. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1638. struct dp_tx_msdu_info_s msdu_info;
  1639. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1640. msdu_info.tid = tx_exc_metadata->tid;
  1641. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1642. dp_verbose_debug("skb %pM", nbuf->data);
  1643. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1644. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1645. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1646. "Invalid parameters in exception path");
  1647. goto fail;
  1648. }
  1649. /* Basic sanity checks for unsupported packets */
  1650. /* MESH mode */
  1651. if (qdf_unlikely(vdev->mesh_vdev)) {
  1652. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1653. "Mesh mode is not supported in exception path");
  1654. goto fail;
  1655. }
  1656. /* TSO or SG */
  1657. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1658. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1659. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1660. "TSO and SG are not supported in exception path");
  1661. goto fail;
  1662. }
  1663. /* RAW */
  1664. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1666. "Raw frame is not supported in exception path");
  1667. goto fail;
  1668. }
  1669. /* Mcast enhancement*/
  1670. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1671. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1672. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1673. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1674. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1675. }
  1676. }
  1677. /*
  1678. * Get HW Queue to use for this frame.
  1679. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1680. * dedicated for data and 1 for command.
  1681. * "queue_id" maps to one hardware ring.
  1682. * With each ring, we also associate a unique Tx descriptor pool
  1683. * to minimize lock contention for these resources.
  1684. */
  1685. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1686. /* Single linear frame */
  1687. /*
  1688. * If nbuf is a simple linear frame, use send_single function to
  1689. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1690. * SRNG. There is no need to setup a MSDU extension descriptor.
  1691. */
  1692. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1693. tx_exc_metadata->peer_id, tx_exc_metadata);
  1694. return nbuf;
  1695. fail:
  1696. dp_verbose_debug("pkt send failed");
  1697. return nbuf;
  1698. }
  1699. /**
  1700. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1701. * @vap_dev: DP vdev handle
  1702. * @nbuf: skb
  1703. *
  1704. * Entry point for Core Tx layer (DP_TX) invoked from
  1705. * hard_start_xmit in OSIF/HDD
  1706. *
  1707. * Return: NULL on success,
  1708. * nbuf when it fails to send
  1709. */
  1710. #ifdef MESH_MODE_SUPPORT
  1711. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1712. {
  1713. struct meta_hdr_s *mhdr;
  1714. qdf_nbuf_t nbuf_mesh = NULL;
  1715. qdf_nbuf_t nbuf_clone = NULL;
  1716. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1717. uint8_t no_enc_frame = 0;
  1718. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1719. if (!nbuf_mesh) {
  1720. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1721. "qdf_nbuf_unshare failed");
  1722. return nbuf;
  1723. }
  1724. nbuf = nbuf_mesh;
  1725. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1726. if ((vdev->sec_type != cdp_sec_type_none) &&
  1727. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1728. no_enc_frame = 1;
  1729. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1730. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1731. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1732. !no_enc_frame) {
  1733. nbuf_clone = qdf_nbuf_clone(nbuf);
  1734. if (!nbuf_clone) {
  1735. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1736. "qdf_nbuf_clone failed");
  1737. return nbuf;
  1738. }
  1739. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1740. }
  1741. if (nbuf_clone) {
  1742. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1743. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1744. } else {
  1745. qdf_nbuf_free(nbuf_clone);
  1746. }
  1747. }
  1748. if (no_enc_frame)
  1749. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1750. else
  1751. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1752. nbuf = dp_tx_send(vap_dev, nbuf);
  1753. if ((!nbuf) && no_enc_frame) {
  1754. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1755. }
  1756. return nbuf;
  1757. }
  1758. #else
  1759. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1760. {
  1761. return dp_tx_send(vap_dev, nbuf);
  1762. }
  1763. #endif
  1764. /**
  1765. * dp_tx_send() - Transmit a frame on a given VAP
  1766. * @vap_dev: DP vdev handle
  1767. * @nbuf: skb
  1768. *
  1769. * Entry point for Core Tx layer (DP_TX) invoked from
  1770. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1771. * cases
  1772. *
  1773. * Return: NULL on success,
  1774. * nbuf when it fails to send
  1775. */
  1776. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1777. {
  1778. qdf_ether_header_t *eh = NULL;
  1779. struct dp_tx_msdu_info_s msdu_info;
  1780. struct dp_tx_seg_info_s seg_info;
  1781. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1782. uint16_t peer_id = HTT_INVALID_PEER;
  1783. qdf_nbuf_t nbuf_mesh = NULL;
  1784. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1785. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1786. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1787. dp_verbose_debug("skb %pM", nbuf->data);
  1788. /*
  1789. * Set Default Host TID value to invalid TID
  1790. * (TID override disabled)
  1791. */
  1792. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1793. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1794. if (qdf_unlikely(vdev->mesh_vdev)) {
  1795. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1796. &msdu_info);
  1797. if (!nbuf_mesh) {
  1798. dp_verbose_debug("Extracting mesh metadata failed");
  1799. return nbuf;
  1800. }
  1801. nbuf = nbuf_mesh;
  1802. }
  1803. /*
  1804. * Get HW Queue to use for this frame.
  1805. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1806. * dedicated for data and 1 for command.
  1807. * "queue_id" maps to one hardware ring.
  1808. * With each ring, we also associate a unique Tx descriptor pool
  1809. * to minimize lock contention for these resources.
  1810. */
  1811. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1812. /*
  1813. * TCL H/W supports 2 DSCP-TID mapping tables.
  1814. * Table 1 - Default DSCP-TID mapping table
  1815. * Table 2 - 1 DSCP-TID override table
  1816. *
  1817. * If we need a different DSCP-TID mapping for this vap,
  1818. * call tid_classify to extract DSCP/ToS from frame and
  1819. * map to a TID and store in msdu_info. This is later used
  1820. * to fill in TCL Input descriptor (per-packet TID override).
  1821. */
  1822. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1823. /*
  1824. * Classify the frame and call corresponding
  1825. * "prepare" function which extracts the segment (TSO)
  1826. * and fragmentation information (for TSO , SG, ME, or Raw)
  1827. * into MSDU_INFO structure which is later used to fill
  1828. * SW and HW descriptors.
  1829. */
  1830. if (qdf_nbuf_is_tso(nbuf)) {
  1831. dp_verbose_debug("TSO frame %pK", vdev);
  1832. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1833. qdf_nbuf_len(nbuf));
  1834. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1835. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1836. qdf_nbuf_len(nbuf));
  1837. return nbuf;
  1838. }
  1839. goto send_multiple;
  1840. }
  1841. /* SG */
  1842. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1843. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1844. if (!nbuf)
  1845. return NULL;
  1846. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1847. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1848. qdf_nbuf_len(nbuf));
  1849. goto send_multiple;
  1850. }
  1851. #ifdef ATH_SUPPORT_IQUE
  1852. /* Mcast to Ucast Conversion*/
  1853. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1854. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1855. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1856. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1857. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1858. DP_STATS_INC_PKT(vdev,
  1859. tx_i.mcast_en.mcast_pkt, 1,
  1860. qdf_nbuf_len(nbuf));
  1861. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1862. QDF_STATUS_SUCCESS) {
  1863. return NULL;
  1864. }
  1865. }
  1866. }
  1867. #endif
  1868. /* RAW */
  1869. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1870. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1871. if (!nbuf)
  1872. return NULL;
  1873. dp_verbose_debug("Raw frame %pK", vdev);
  1874. goto send_multiple;
  1875. }
  1876. /* Single linear frame */
  1877. /*
  1878. * If nbuf is a simple linear frame, use send_single function to
  1879. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1880. * SRNG. There is no need to setup a MSDU extension descriptor.
  1881. */
  1882. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1883. return nbuf;
  1884. send_multiple:
  1885. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1886. return nbuf;
  1887. }
  1888. /**
  1889. * dp_tx_reinject_handler() - Tx Reinject Handler
  1890. * @tx_desc: software descriptor head pointer
  1891. * @status : Tx completion status from HTT descriptor
  1892. *
  1893. * This function reinjects frames back to Target.
  1894. * Todo - Host queue needs to be added
  1895. *
  1896. * Return: none
  1897. */
  1898. static
  1899. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1900. {
  1901. struct dp_vdev *vdev;
  1902. struct dp_peer *peer = NULL;
  1903. uint32_t peer_id = HTT_INVALID_PEER;
  1904. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1905. qdf_nbuf_t nbuf_copy = NULL;
  1906. struct dp_tx_msdu_info_s msdu_info;
  1907. struct dp_peer *sa_peer = NULL;
  1908. struct dp_ast_entry *ast_entry = NULL;
  1909. struct dp_soc *soc = NULL;
  1910. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1911. #ifdef WDS_VENDOR_EXTENSION
  1912. int is_mcast = 0, is_ucast = 0;
  1913. int num_peers_3addr = 0;
  1914. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1915. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1916. #endif
  1917. vdev = tx_desc->vdev;
  1918. soc = vdev->pdev->soc;
  1919. qdf_assert(vdev);
  1920. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1921. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1923. "%s Tx reinject path", __func__);
  1924. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1925. qdf_nbuf_len(tx_desc->nbuf));
  1926. qdf_spin_lock_bh(&(soc->ast_lock));
  1927. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1928. (soc,
  1929. (uint8_t *)(eh->ether_shost),
  1930. vdev->pdev->pdev_id);
  1931. if (ast_entry)
  1932. sa_peer = ast_entry->peer;
  1933. qdf_spin_unlock_bh(&(soc->ast_lock));
  1934. #ifdef WDS_VENDOR_EXTENSION
  1935. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1936. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1937. } else {
  1938. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1939. }
  1940. is_ucast = !is_mcast;
  1941. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1942. if (peer->bss_peer)
  1943. continue;
  1944. /* Detect wds peers that use 3-addr framing for mcast.
  1945. * if there are any, the bss_peer is used to send the
  1946. * the mcast frame using 3-addr format. all wds enabled
  1947. * peers that use 4-addr framing for mcast frames will
  1948. * be duplicated and sent as 4-addr frames below.
  1949. */
  1950. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1951. num_peers_3addr = 1;
  1952. break;
  1953. }
  1954. }
  1955. #endif
  1956. if (qdf_unlikely(vdev->mesh_vdev)) {
  1957. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1958. } else {
  1959. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1960. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1961. #ifdef WDS_VENDOR_EXTENSION
  1962. /*
  1963. * . if 3-addr STA, then send on BSS Peer
  1964. * . if Peer WDS enabled and accept 4-addr mcast,
  1965. * send mcast on that peer only
  1966. * . if Peer WDS enabled and accept 4-addr ucast,
  1967. * send ucast on that peer only
  1968. */
  1969. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1970. (peer->wds_enabled &&
  1971. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1972. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1973. #else
  1974. ((peer->bss_peer &&
  1975. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1976. peer->nawds_enabled)) {
  1977. #endif
  1978. peer_id = DP_INVALID_PEER;
  1979. if (peer->nawds_enabled) {
  1980. peer_id = peer->peer_ids[0];
  1981. if (sa_peer == peer) {
  1982. QDF_TRACE(
  1983. QDF_MODULE_ID_DP,
  1984. QDF_TRACE_LEVEL_DEBUG,
  1985. " %s: multicast packet",
  1986. __func__);
  1987. DP_STATS_INC(peer,
  1988. tx.nawds_mcast_drop, 1);
  1989. continue;
  1990. }
  1991. }
  1992. nbuf_copy = qdf_nbuf_copy(nbuf);
  1993. if (!nbuf_copy) {
  1994. QDF_TRACE(QDF_MODULE_ID_DP,
  1995. QDF_TRACE_LEVEL_DEBUG,
  1996. FL("nbuf copy failed"));
  1997. break;
  1998. }
  1999. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2000. nbuf_copy,
  2001. &msdu_info,
  2002. peer_id,
  2003. NULL);
  2004. if (nbuf_copy) {
  2005. QDF_TRACE(QDF_MODULE_ID_DP,
  2006. QDF_TRACE_LEVEL_DEBUG,
  2007. FL("pkt send failed"));
  2008. qdf_nbuf_free(nbuf_copy);
  2009. } else {
  2010. if (peer_id != DP_INVALID_PEER)
  2011. DP_STATS_INC_PKT(peer,
  2012. tx.nawds_mcast,
  2013. 1, qdf_nbuf_len(nbuf));
  2014. }
  2015. }
  2016. }
  2017. }
  2018. if (vdev->nawds_enabled) {
  2019. peer_id = DP_INVALID_PEER;
  2020. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2021. 1, qdf_nbuf_len(nbuf));
  2022. nbuf = dp_tx_send_msdu_single(vdev,
  2023. nbuf,
  2024. &msdu_info,
  2025. peer_id, NULL);
  2026. if (nbuf) {
  2027. QDF_TRACE(QDF_MODULE_ID_DP,
  2028. QDF_TRACE_LEVEL_DEBUG,
  2029. FL("pkt send failed"));
  2030. qdf_nbuf_free(nbuf);
  2031. }
  2032. } else
  2033. qdf_nbuf_free(nbuf);
  2034. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2035. }
  2036. /**
  2037. * dp_tx_inspect_handler() - Tx Inspect Handler
  2038. * @tx_desc: software descriptor head pointer
  2039. * @status : Tx completion status from HTT descriptor
  2040. *
  2041. * Handles Tx frames sent back to Host for inspection
  2042. * (ProxyARP)
  2043. *
  2044. * Return: none
  2045. */
  2046. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2047. {
  2048. struct dp_soc *soc;
  2049. struct dp_pdev *pdev = tx_desc->pdev;
  2050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2051. "%s Tx inspect path",
  2052. __func__);
  2053. qdf_assert(pdev);
  2054. soc = pdev->soc;
  2055. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2056. qdf_nbuf_len(tx_desc->nbuf));
  2057. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2058. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2059. }
  2060. #ifdef FEATURE_PERPKT_INFO
  2061. /**
  2062. * dp_get_completion_indication_for_stack() - send completion to stack
  2063. * @soc : dp_soc handle
  2064. * @pdev: dp_pdev handle
  2065. * @peer: dp peer handle
  2066. * @ts: transmit completion status structure
  2067. * @netbuf: Buffer pointer for free
  2068. *
  2069. * This function is used for indication whether buffer needs to be
  2070. * sent to stack for freeing or not
  2071. */
  2072. QDF_STATUS
  2073. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2074. struct dp_pdev *pdev,
  2075. struct dp_peer *peer,
  2076. struct hal_tx_completion_status *ts,
  2077. qdf_nbuf_t netbuf,
  2078. uint64_t time_latency)
  2079. {
  2080. struct tx_capture_hdr *ppdu_hdr;
  2081. uint16_t peer_id = ts->peer_id;
  2082. uint32_t ppdu_id = ts->ppdu_id;
  2083. uint8_t first_msdu = ts->first_msdu;
  2084. uint8_t last_msdu = ts->last_msdu;
  2085. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2086. !pdev->latency_capture_enable))
  2087. return QDF_STATUS_E_NOSUPPORT;
  2088. if (!peer) {
  2089. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2090. FL("Peer Invalid"));
  2091. return QDF_STATUS_E_INVAL;
  2092. }
  2093. if (pdev->mcopy_mode) {
  2094. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2095. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2096. return QDF_STATUS_E_INVAL;
  2097. }
  2098. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2099. pdev->m_copy_id.tx_peer_id = peer_id;
  2100. }
  2101. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2102. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2103. FL("No headroom"));
  2104. return QDF_STATUS_E_NOMEM;
  2105. }
  2106. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2107. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2108. QDF_MAC_ADDR_SIZE);
  2109. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2110. QDF_MAC_ADDR_SIZE);
  2111. ppdu_hdr->ppdu_id = ppdu_id;
  2112. ppdu_hdr->peer_id = peer_id;
  2113. ppdu_hdr->first_msdu = first_msdu;
  2114. ppdu_hdr->last_msdu = last_msdu;
  2115. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2116. ppdu_hdr->tsf = ts->tsf;
  2117. ppdu_hdr->time_latency = time_latency;
  2118. }
  2119. return QDF_STATUS_SUCCESS;
  2120. }
  2121. /**
  2122. * dp_send_completion_to_stack() - send completion to stack
  2123. * @soc : dp_soc handle
  2124. * @pdev: dp_pdev handle
  2125. * @peer_id: peer_id of the peer for which completion came
  2126. * @ppdu_id: ppdu_id
  2127. * @netbuf: Buffer pointer for free
  2128. *
  2129. * This function is used to send completion to stack
  2130. * to free buffer
  2131. */
  2132. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2133. uint16_t peer_id, uint32_t ppdu_id,
  2134. qdf_nbuf_t netbuf)
  2135. {
  2136. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2137. netbuf, peer_id,
  2138. WDI_NO_VAL, pdev->pdev_id);
  2139. }
  2140. #else
  2141. static QDF_STATUS
  2142. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2143. struct dp_pdev *pdev,
  2144. struct dp_peer *peer,
  2145. struct hal_tx_completion_status *ts,
  2146. qdf_nbuf_t netbuf,
  2147. uint64_t time_latency)
  2148. {
  2149. return QDF_STATUS_E_NOSUPPORT;
  2150. }
  2151. static void
  2152. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2153. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2154. {
  2155. }
  2156. #endif
  2157. /**
  2158. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2159. * @soc: Soc handle
  2160. * @desc: software Tx descriptor to be processed
  2161. *
  2162. * Return: none
  2163. */
  2164. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2165. struct dp_tx_desc_s *desc)
  2166. {
  2167. struct dp_vdev *vdev = desc->vdev;
  2168. qdf_nbuf_t nbuf = desc->nbuf;
  2169. /* nbuf already freed in vdev detach path */
  2170. if (!nbuf)
  2171. return;
  2172. /* If it is TDLS mgmt, don't unmap or free the frame */
  2173. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2174. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2175. /* 0 : MSDU buffer, 1 : MLE */
  2176. if (desc->msdu_ext_desc) {
  2177. /* TSO free */
  2178. if (hal_tx_ext_desc_get_tso_enable(
  2179. desc->msdu_ext_desc->vaddr)) {
  2180. /* unmap eash TSO seg before free the nbuf */
  2181. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2182. desc->tso_num_desc);
  2183. qdf_nbuf_free(nbuf);
  2184. return;
  2185. }
  2186. }
  2187. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2188. if (qdf_unlikely(!vdev)) {
  2189. qdf_nbuf_free(nbuf);
  2190. return;
  2191. }
  2192. if (qdf_likely(!vdev->mesh_vdev))
  2193. qdf_nbuf_free(nbuf);
  2194. else {
  2195. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2196. qdf_nbuf_free(nbuf);
  2197. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2198. } else
  2199. vdev->osif_tx_free_ext((nbuf));
  2200. }
  2201. }
  2202. #ifdef MESH_MODE_SUPPORT
  2203. /**
  2204. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2205. * in mesh meta header
  2206. * @tx_desc: software descriptor head pointer
  2207. * @ts: pointer to tx completion stats
  2208. * Return: none
  2209. */
  2210. static
  2211. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2212. struct hal_tx_completion_status *ts)
  2213. {
  2214. struct meta_hdr_s *mhdr;
  2215. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2216. if (!tx_desc->msdu_ext_desc) {
  2217. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2218. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2219. "netbuf %pK offset %d",
  2220. netbuf, tx_desc->pkt_offset);
  2221. return;
  2222. }
  2223. }
  2224. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2225. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2226. "netbuf %pK offset %lu", netbuf,
  2227. sizeof(struct meta_hdr_s));
  2228. return;
  2229. }
  2230. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2231. mhdr->rssi = ts->ack_frame_rssi;
  2232. mhdr->channel = tx_desc->pdev->operating_channel;
  2233. }
  2234. #else
  2235. static
  2236. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2237. struct hal_tx_completion_status *ts)
  2238. {
  2239. }
  2240. #endif
  2241. /**
  2242. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2243. * to pass in correct fields
  2244. *
  2245. * @vdev: pdev handle
  2246. * @tx_desc: tx descriptor
  2247. * @tid: tid value
  2248. * Return: none
  2249. */
  2250. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2251. struct dp_tx_desc_s *tx_desc, uint8_t tid)
  2252. {
  2253. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2254. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2255. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2256. return;
  2257. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2258. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2259. timestamp_hw_enqueue = tx_desc->timestamp;
  2260. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2261. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2262. timestamp_hw_enqueue);
  2263. interframe_delay = (uint32_t)(timestamp_ingress -
  2264. vdev->prev_tx_enq_tstamp);
  2265. /*
  2266. * Delay in software enqueue
  2267. */
  2268. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2269. CDP_DELAY_STATS_SW_ENQ);
  2270. /*
  2271. * Delay between packet enqueued to HW and Tx completion
  2272. */
  2273. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2274. CDP_DELAY_STATS_FW_HW_TRANSMIT);
  2275. /*
  2276. * Update interframe delay stats calculated at hardstart receive point.
  2277. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2278. * interframe delay will not be calculate correctly for 1st frame.
  2279. * On the other side, this will help in avoiding extra per packet check
  2280. * of !vdev->prev_tx_enq_tstamp.
  2281. */
  2282. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2283. CDP_DELAY_STATS_TX_INTERFRAME);
  2284. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2285. }
  2286. /**
  2287. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2288. * @tx_desc: software descriptor head pointer
  2289. * @ts: Tx completion status
  2290. * @peer: peer handle
  2291. *
  2292. * Return: None
  2293. */
  2294. static inline void
  2295. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2296. struct hal_tx_completion_status *ts,
  2297. struct dp_peer *peer)
  2298. {
  2299. struct dp_pdev *pdev = peer->vdev->pdev;
  2300. struct dp_soc *soc = NULL;
  2301. uint8_t mcs, pkt_type;
  2302. uint8_t tid = ts->tid;
  2303. uint32_t length;
  2304. struct cdp_tid_tx_stats *tid_stats;
  2305. if (!pdev)
  2306. return;
  2307. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2308. tid = CDP_MAX_DATA_TIDS - 1;
  2309. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2310. soc = pdev->soc;
  2311. mcs = ts->mcs;
  2312. pkt_type = ts->pkt_type;
  2313. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2314. dp_err("Release source is not from TQM");
  2315. return;
  2316. }
  2317. length = qdf_nbuf_len(tx_desc->nbuf);
  2318. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2319. if (qdf_unlikely(pdev->delay_stats_flag))
  2320. dp_tx_compute_delay(peer->vdev, tx_desc, tid);
  2321. tid_stats->complete_cnt++;
  2322. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2323. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2324. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2325. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2326. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2327. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2328. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2329. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2330. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2331. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2332. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2333. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2334. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2335. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2336. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2337. tid_stats->comp_fail_cnt++;
  2338. return;
  2339. }
  2340. tid_stats->success_cnt++;
  2341. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2342. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2343. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2344. /*
  2345. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2346. * Return from here if HTT PPDU events are enabled.
  2347. */
  2348. if (!(soc->process_tx_status))
  2349. return;
  2350. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2351. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2352. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2353. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2354. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2355. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2356. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2357. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2358. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2359. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2360. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2361. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2362. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2363. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2364. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2365. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2366. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2367. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2368. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2369. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2370. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2371. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2372. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2373. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2374. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2375. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2376. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2377. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2378. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2379. &peer->stats, ts->peer_id,
  2380. UPDATE_PEER_STATS, pdev->pdev_id);
  2381. #endif
  2382. }
  2383. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2384. /**
  2385. * dp_tx_flow_pool_lock() - take flow pool lock
  2386. * @soc: core txrx main context
  2387. * @tx_desc: tx desc
  2388. *
  2389. * Return: None
  2390. */
  2391. static inline
  2392. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2393. struct dp_tx_desc_s *tx_desc)
  2394. {
  2395. struct dp_tx_desc_pool_s *pool;
  2396. uint8_t desc_pool_id;
  2397. desc_pool_id = tx_desc->pool_id;
  2398. pool = &soc->tx_desc[desc_pool_id];
  2399. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2400. }
  2401. /**
  2402. * dp_tx_flow_pool_unlock() - release flow pool lock
  2403. * @soc: core txrx main context
  2404. * @tx_desc: tx desc
  2405. *
  2406. * Return: None
  2407. */
  2408. static inline
  2409. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2410. struct dp_tx_desc_s *tx_desc)
  2411. {
  2412. struct dp_tx_desc_pool_s *pool;
  2413. uint8_t desc_pool_id;
  2414. desc_pool_id = tx_desc->pool_id;
  2415. pool = &soc->tx_desc[desc_pool_id];
  2416. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2417. }
  2418. #else
  2419. static inline
  2420. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2421. {
  2422. }
  2423. static inline
  2424. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2425. {
  2426. }
  2427. #endif
  2428. /**
  2429. * dp_tx_notify_completion() - Notify tx completion for this desc
  2430. * @soc: core txrx main context
  2431. * @tx_desc: tx desc
  2432. * @netbuf: buffer
  2433. *
  2434. * Return: none
  2435. */
  2436. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2437. struct dp_tx_desc_s *tx_desc,
  2438. qdf_nbuf_t netbuf)
  2439. {
  2440. void *osif_dev;
  2441. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2442. qdf_assert(tx_desc);
  2443. dp_tx_flow_pool_lock(soc, tx_desc);
  2444. if (!tx_desc->vdev ||
  2445. !tx_desc->vdev->osif_vdev) {
  2446. dp_tx_flow_pool_unlock(soc, tx_desc);
  2447. return;
  2448. }
  2449. osif_dev = tx_desc->vdev->osif_vdev;
  2450. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2451. dp_tx_flow_pool_unlock(soc, tx_desc);
  2452. if (tx_compl_cbk)
  2453. tx_compl_cbk(netbuf, osif_dev);
  2454. }
  2455. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2456. * @pdev: pdev handle
  2457. * @tid: tid value
  2458. * @txdesc_ts: timestamp from txdesc
  2459. * @ppdu_id: ppdu id
  2460. *
  2461. * Return: none
  2462. */
  2463. #ifdef FEATURE_PERPKT_INFO
  2464. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2465. struct dp_peer *peer,
  2466. uint8_t tid,
  2467. uint64_t txdesc_ts,
  2468. uint32_t ppdu_id)
  2469. {
  2470. uint64_t delta_ms;
  2471. struct cdp_tx_sojourn_stats *sojourn_stats;
  2472. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2473. return;
  2474. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2475. tid >= CDP_DATA_TID_MAX))
  2476. return;
  2477. if (qdf_unlikely(!pdev->sojourn_buf))
  2478. return;
  2479. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2480. qdf_nbuf_data(pdev->sojourn_buf);
  2481. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2482. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2483. txdesc_ts;
  2484. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2485. delta_ms);
  2486. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2487. sojourn_stats->num_msdus[tid] = 1;
  2488. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2489. peer->avg_sojourn_msdu[tid].internal;
  2490. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2491. pdev->sojourn_buf, HTT_INVALID_PEER,
  2492. WDI_NO_VAL, pdev->pdev_id);
  2493. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2494. sojourn_stats->num_msdus[tid] = 0;
  2495. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2496. }
  2497. #else
  2498. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2499. uint8_t tid,
  2500. uint64_t txdesc_ts,
  2501. uint32_t ppdu_id)
  2502. {
  2503. }
  2504. #endif
  2505. /**
  2506. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2507. * @soc: DP Soc handle
  2508. * @tx_desc: software Tx descriptor
  2509. * @ts : Tx completion status from HAL/HTT descriptor
  2510. *
  2511. * Return: none
  2512. */
  2513. static inline void
  2514. dp_tx_comp_process_desc(struct dp_soc *soc,
  2515. struct dp_tx_desc_s *desc,
  2516. struct hal_tx_completion_status *ts,
  2517. struct dp_peer *peer)
  2518. {
  2519. uint64_t time_latency = 0;
  2520. /*
  2521. * m_copy/tx_capture modes are not supported for
  2522. * scatter gather packets
  2523. */
  2524. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2525. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2526. desc->timestamp);
  2527. }
  2528. if (!(desc->msdu_ext_desc)) {
  2529. if (QDF_STATUS_SUCCESS ==
  2530. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2531. return;
  2532. }
  2533. if (QDF_STATUS_SUCCESS ==
  2534. dp_get_completion_indication_for_stack(soc,
  2535. desc->pdev,
  2536. peer, ts,
  2537. desc->nbuf,
  2538. time_latency)) {
  2539. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2540. QDF_DMA_TO_DEVICE);
  2541. dp_send_completion_to_stack(soc,
  2542. desc->pdev,
  2543. ts->peer_id,
  2544. ts->ppdu_id,
  2545. desc->nbuf);
  2546. return;
  2547. }
  2548. }
  2549. dp_tx_comp_free_buf(soc, desc);
  2550. }
  2551. /**
  2552. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2553. * @tx_desc: software descriptor head pointer
  2554. * @ts: Tx completion status
  2555. * @peer: peer handle
  2556. *
  2557. * Return: none
  2558. */
  2559. static inline
  2560. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2561. struct hal_tx_completion_status *ts,
  2562. struct dp_peer *peer)
  2563. {
  2564. uint32_t length;
  2565. qdf_ether_header_t *eh;
  2566. struct dp_soc *soc = NULL;
  2567. struct dp_vdev *vdev = tx_desc->vdev;
  2568. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2569. if (!vdev || !nbuf) {
  2570. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2571. "invalid tx descriptor. vdev or nbuf NULL");
  2572. goto out;
  2573. }
  2574. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2575. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2576. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2577. QDF_TRACE_DEFAULT_PDEV_ID,
  2578. qdf_nbuf_data_addr(nbuf),
  2579. sizeof(qdf_nbuf_data(nbuf)),
  2580. tx_desc->id,
  2581. ts->status));
  2582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2583. "-------------------- \n"
  2584. "Tx Completion Stats: \n"
  2585. "-------------------- \n"
  2586. "ack_frame_rssi = %d \n"
  2587. "first_msdu = %d \n"
  2588. "last_msdu = %d \n"
  2589. "msdu_part_of_amsdu = %d \n"
  2590. "rate_stats valid = %d \n"
  2591. "bw = %d \n"
  2592. "pkt_type = %d \n"
  2593. "stbc = %d \n"
  2594. "ldpc = %d \n"
  2595. "sgi = %d \n"
  2596. "mcs = %d \n"
  2597. "ofdma = %d \n"
  2598. "tones_in_ru = %d \n"
  2599. "tsf = %d \n"
  2600. "ppdu_id = %d \n"
  2601. "transmit_cnt = %d \n"
  2602. "tid = %d \n"
  2603. "peer_id = %d\n",
  2604. ts->ack_frame_rssi, ts->first_msdu,
  2605. ts->last_msdu, ts->msdu_part_of_amsdu,
  2606. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2607. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2608. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2609. ts->transmit_cnt, ts->tid, ts->peer_id);
  2610. soc = vdev->pdev->soc;
  2611. /* Update SoC level stats */
  2612. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2613. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2614. /* Update per-packet stats for mesh mode */
  2615. if (qdf_unlikely(vdev->mesh_vdev) &&
  2616. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2617. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2618. length = qdf_nbuf_len(nbuf);
  2619. /* Update peer level stats */
  2620. if (!peer) {
  2621. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2622. "peer is null or deletion in progress");
  2623. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2624. goto out;
  2625. }
  2626. if (qdf_likely(!peer->bss_peer)) {
  2627. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2628. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2629. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2630. } else {
  2631. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2632. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2633. if ((peer->vdev->tx_encap_type ==
  2634. htt_cmn_pkt_type_ethernet) &&
  2635. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2636. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2637. }
  2638. }
  2639. }
  2640. dp_tx_update_peer_stats(tx_desc, ts, peer);
  2641. #ifdef QCA_SUPPORT_RDK_STATS
  2642. if (soc->wlanstats_enabled)
  2643. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2644. tx_desc->timestamp,
  2645. ts->ppdu_id);
  2646. #endif
  2647. out:
  2648. return;
  2649. }
  2650. /**
  2651. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2652. * @soc: core txrx main context
  2653. * @comp_head: software descriptor head pointer
  2654. *
  2655. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2656. * and release the software descriptors after processing is complete
  2657. *
  2658. * Return: none
  2659. */
  2660. static void
  2661. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2662. struct dp_tx_desc_s *comp_head)
  2663. {
  2664. struct dp_tx_desc_s *desc;
  2665. struct dp_tx_desc_s *next;
  2666. struct hal_tx_completion_status ts = {0};
  2667. struct dp_peer *peer;
  2668. qdf_nbuf_t netbuf;
  2669. desc = comp_head;
  2670. while (desc) {
  2671. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2672. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2673. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2674. netbuf = desc->nbuf;
  2675. /* check tx complete notification */
  2676. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2677. dp_tx_notify_completion(soc, desc, netbuf);
  2678. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2679. if (peer)
  2680. dp_peer_unref_del_find_by_id(peer);
  2681. next = desc->next;
  2682. dp_tx_desc_release(desc, desc->pool_id);
  2683. desc = next;
  2684. }
  2685. }
  2686. /**
  2687. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2688. * @tx_desc: software descriptor head pointer
  2689. * @status : Tx completion status from HTT descriptor
  2690. *
  2691. * This function will process HTT Tx indication messages from Target
  2692. *
  2693. * Return: none
  2694. */
  2695. static
  2696. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2697. {
  2698. uint8_t tx_status;
  2699. struct dp_pdev *pdev;
  2700. struct dp_vdev *vdev;
  2701. struct dp_soc *soc;
  2702. struct hal_tx_completion_status ts = {0};
  2703. uint32_t *htt_desc = (uint32_t *)status;
  2704. struct dp_peer *peer;
  2705. struct cdp_tid_tx_stats *tid_stats = NULL;
  2706. qdf_assert(tx_desc->pdev);
  2707. pdev = tx_desc->pdev;
  2708. vdev = tx_desc->vdev;
  2709. soc = pdev->soc;
  2710. if (!vdev)
  2711. return;
  2712. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2713. switch (tx_status) {
  2714. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2715. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2716. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2717. {
  2718. uint8_t tid;
  2719. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2720. ts.peer_id =
  2721. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2722. htt_desc[2]);
  2723. ts.tid =
  2724. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2725. htt_desc[2]);
  2726. } else {
  2727. ts.peer_id = HTT_INVALID_PEER;
  2728. ts.tid = HTT_INVALID_TID;
  2729. }
  2730. ts.ppdu_id =
  2731. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2732. htt_desc[1]);
  2733. ts.ack_frame_rssi =
  2734. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2735. htt_desc[1]);
  2736. ts.first_msdu = 1;
  2737. ts.last_msdu = 1;
  2738. tid = ts.tid;
  2739. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2740. tid = CDP_MAX_DATA_TIDS - 1;
  2741. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2742. if (qdf_unlikely(pdev->delay_stats_flag))
  2743. dp_tx_compute_delay(vdev, tx_desc, tid);
  2744. tid_stats->complete_cnt++;
  2745. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2746. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2747. tid_stats->comp_fail_cnt++;
  2748. } else {
  2749. tid_stats->success_cnt++;
  2750. }
  2751. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2752. if (qdf_likely(peer))
  2753. dp_peer_unref_del_find_by_id(peer);
  2754. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2755. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2756. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2757. break;
  2758. }
  2759. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2760. {
  2761. dp_tx_reinject_handler(tx_desc, status);
  2762. break;
  2763. }
  2764. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2765. {
  2766. dp_tx_inspect_handler(tx_desc, status);
  2767. break;
  2768. }
  2769. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2770. {
  2771. dp_tx_mec_handler(vdev, status);
  2772. break;
  2773. }
  2774. default:
  2775. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2776. "%s Invalid HTT tx_status %d\n",
  2777. __func__, tx_status);
  2778. break;
  2779. }
  2780. }
  2781. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2782. static inline
  2783. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2784. {
  2785. bool limit_hit = false;
  2786. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2787. limit_hit =
  2788. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2789. if (limit_hit)
  2790. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2791. return limit_hit;
  2792. }
  2793. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2794. {
  2795. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2796. }
  2797. #else
  2798. static inline
  2799. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2800. {
  2801. return false;
  2802. }
  2803. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2804. {
  2805. return false;
  2806. }
  2807. #endif
  2808. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2809. void *hal_srng, uint32_t quota)
  2810. {
  2811. void *tx_comp_hal_desc;
  2812. uint8_t buffer_src;
  2813. uint8_t pool_id;
  2814. uint32_t tx_desc_id;
  2815. struct dp_tx_desc_s *tx_desc = NULL;
  2816. struct dp_tx_desc_s *head_desc = NULL;
  2817. struct dp_tx_desc_s *tail_desc = NULL;
  2818. uint32_t num_processed = 0;
  2819. uint32_t count = 0;
  2820. bool force_break = false;
  2821. DP_HIST_INIT();
  2822. more_data:
  2823. /* Re-initialize local variables to be re-used */
  2824. head_desc = NULL;
  2825. tail_desc = NULL;
  2826. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2827. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2828. "%s %d : HAL RING Access Failed -- %pK",
  2829. __func__, __LINE__, hal_srng);
  2830. return 0;
  2831. }
  2832. /* Find head descriptor from completion ring */
  2833. while (qdf_likely(tx_comp_hal_desc =
  2834. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2835. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2836. /* If this buffer was not released by TQM or FW, then it is not
  2837. * Tx completion indication, assert */
  2838. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2839. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2840. QDF_TRACE(QDF_MODULE_ID_DP,
  2841. QDF_TRACE_LEVEL_FATAL,
  2842. "Tx comp release_src != TQM | FW but from %d",
  2843. buffer_src);
  2844. hal_dump_comp_desc(tx_comp_hal_desc);
  2845. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2846. qdf_assert_always(0);
  2847. }
  2848. /* Get descriptor id */
  2849. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2850. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2851. DP_TX_DESC_ID_POOL_OS;
  2852. /* Find Tx descriptor */
  2853. tx_desc = dp_tx_desc_find(soc, pool_id,
  2854. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2855. DP_TX_DESC_ID_PAGE_OS,
  2856. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2857. DP_TX_DESC_ID_OFFSET_OS);
  2858. /*
  2859. * If the descriptor is already freed in vdev_detach,
  2860. * continue to next descriptor
  2861. */
  2862. if (!tx_desc->vdev && !tx_desc->flags) {
  2863. QDF_TRACE(QDF_MODULE_ID_DP,
  2864. QDF_TRACE_LEVEL_INFO,
  2865. "Descriptor freed in vdev_detach %d",
  2866. tx_desc_id);
  2867. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2868. count++;
  2869. continue;
  2870. }
  2871. /*
  2872. * If the release source is FW, process the HTT status
  2873. */
  2874. if (qdf_unlikely(buffer_src ==
  2875. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2876. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2877. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2878. htt_tx_status);
  2879. dp_tx_process_htt_completion(tx_desc,
  2880. htt_tx_status);
  2881. } else {
  2882. /* Pool id is not matching. Error */
  2883. if (tx_desc->pool_id != pool_id) {
  2884. QDF_TRACE(QDF_MODULE_ID_DP,
  2885. QDF_TRACE_LEVEL_FATAL,
  2886. "Tx Comp pool id %d not matched %d",
  2887. pool_id, tx_desc->pool_id);
  2888. qdf_assert_always(0);
  2889. }
  2890. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2891. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2892. QDF_TRACE(QDF_MODULE_ID_DP,
  2893. QDF_TRACE_LEVEL_FATAL,
  2894. "Txdesc invalid, flgs = %x,id = %d",
  2895. tx_desc->flags, tx_desc_id);
  2896. qdf_assert_always(0);
  2897. }
  2898. /* First ring descriptor on the cycle */
  2899. if (!head_desc) {
  2900. head_desc = tx_desc;
  2901. tail_desc = tx_desc;
  2902. }
  2903. tail_desc->next = tx_desc;
  2904. tx_desc->next = NULL;
  2905. tail_desc = tx_desc;
  2906. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2907. /* Collect hw completion contents */
  2908. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2909. &tx_desc->comp, 1);
  2910. }
  2911. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2912. /*
  2913. * Processed packet count is more than given quota
  2914. * stop to processing
  2915. */
  2916. if (num_processed >= quota) {
  2917. force_break = true;
  2918. break;
  2919. }
  2920. count++;
  2921. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2922. break;
  2923. }
  2924. hal_srng_access_end(soc->hal_soc, hal_srng);
  2925. /* Process the reaped descriptors */
  2926. if (head_desc)
  2927. dp_tx_comp_process_desc_list(soc, head_desc);
  2928. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2929. if (!force_break &&
  2930. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2931. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2932. if (!hif_exec_should_yield(soc->hif_handle,
  2933. int_ctx->dp_intr_id))
  2934. goto more_data;
  2935. }
  2936. }
  2937. DP_TX_HIST_STATS_PER_PDEV();
  2938. return num_processed;
  2939. }
  2940. #ifdef FEATURE_WLAN_TDLS
  2941. /**
  2942. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2943. *
  2944. * @data_vdev - which vdev should transmit the tx data frames
  2945. * @tx_spec - what non-standard handling to apply to the tx data frames
  2946. * @msdu_list - NULL-terminated list of tx MSDUs
  2947. *
  2948. * Return: NULL on success,
  2949. * nbuf when it fails to send
  2950. */
  2951. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2952. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2953. {
  2954. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2955. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2956. vdev->is_tdls_frame = true;
  2957. return dp_tx_send(vdev_handle, msdu_list);
  2958. }
  2959. #endif
  2960. /**
  2961. * dp_tx_vdev_attach() - attach vdev to dp tx
  2962. * @vdev: virtual device instance
  2963. *
  2964. * Return: QDF_STATUS_SUCCESS: success
  2965. * QDF_STATUS_E_RESOURCES: Error return
  2966. */
  2967. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2968. {
  2969. /*
  2970. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2971. */
  2972. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2973. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2974. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2975. vdev->vdev_id);
  2976. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2977. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2978. /*
  2979. * Set HTT Extension Valid bit to 0 by default
  2980. */
  2981. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2982. dp_tx_vdev_update_search_flags(vdev);
  2983. return QDF_STATUS_SUCCESS;
  2984. }
  2985. #ifndef FEATURE_WDS
  2986. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2987. {
  2988. return false;
  2989. }
  2990. #endif
  2991. /**
  2992. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2993. * @vdev: virtual device instance
  2994. *
  2995. * Return: void
  2996. *
  2997. */
  2998. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2999. {
  3000. struct dp_soc *soc = vdev->pdev->soc;
  3001. /*
  3002. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3003. * for TDLS link
  3004. *
  3005. * Enable AddrY (SA based search) only for non-WDS STA and
  3006. * ProxySTA VAP (in HKv1) modes.
  3007. *
  3008. * In all other VAP modes, only DA based search should be
  3009. * enabled
  3010. */
  3011. if (vdev->opmode == wlan_op_mode_sta &&
  3012. vdev->tdls_link_connected)
  3013. vdev->hal_desc_addr_search_flags =
  3014. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3015. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3016. !dp_tx_da_search_override(vdev))
  3017. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3018. else
  3019. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3020. /* Set search type only when peer map v2 messaging is enabled
  3021. * as we will have the search index (AST hash) only when v2 is
  3022. * enabled
  3023. */
  3024. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3025. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3026. else
  3027. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3028. }
  3029. static inline bool
  3030. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3031. struct dp_vdev *vdev,
  3032. struct dp_tx_desc_s *tx_desc)
  3033. {
  3034. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3035. return false;
  3036. /*
  3037. * if vdev is given, then only check whether desc
  3038. * vdev match. if vdev is NULL, then check whether
  3039. * desc pdev match.
  3040. */
  3041. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3042. }
  3043. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3044. /**
  3045. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3046. *
  3047. * @soc: Handle to DP SoC structure
  3048. * @tx_desc: pointer of one TX desc
  3049. * @desc_pool_id: TX Desc pool id
  3050. */
  3051. static inline void
  3052. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3053. uint8_t desc_pool_id)
  3054. {
  3055. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3056. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3057. tx_desc->vdev = NULL;
  3058. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3059. }
  3060. /**
  3061. * dp_tx_desc_flush() - release resources associated
  3062. * to TX Desc
  3063. *
  3064. * @dp_pdev: Handle to DP pdev structure
  3065. * @vdev: virtual device instance
  3066. * NULL: no specific Vdev is required and check all allcated TX desc
  3067. * on this pdev.
  3068. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3069. *
  3070. * @force_free:
  3071. * true: flush the TX desc.
  3072. * false: only reset the Vdev in each allocated TX desc
  3073. * that associated to current Vdev.
  3074. *
  3075. * This function will go through the TX desc pool to flush
  3076. * the outstanding TX data or reset Vdev to NULL in associated TX
  3077. * Desc.
  3078. */
  3079. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3080. struct dp_vdev *vdev,
  3081. bool force_free)
  3082. {
  3083. uint8_t i;
  3084. uint32_t j;
  3085. uint32_t num_desc, page_id, offset;
  3086. uint16_t num_desc_per_page;
  3087. struct dp_soc *soc = pdev->soc;
  3088. struct dp_tx_desc_s *tx_desc = NULL;
  3089. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3090. if (!vdev && !force_free) {
  3091. dp_err("Reset TX desc vdev, Vdev param is required!");
  3092. return;
  3093. }
  3094. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3095. tx_desc_pool = &soc->tx_desc[i];
  3096. if (!(tx_desc_pool->pool_size) ||
  3097. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3098. !(tx_desc_pool->desc_pages.cacheable_pages))
  3099. continue;
  3100. num_desc = tx_desc_pool->pool_size;
  3101. num_desc_per_page =
  3102. tx_desc_pool->desc_pages.num_element_per_page;
  3103. for (j = 0; j < num_desc; j++) {
  3104. page_id = j / num_desc_per_page;
  3105. offset = j % num_desc_per_page;
  3106. if (qdf_unlikely(!(tx_desc_pool->
  3107. desc_pages.cacheable_pages)))
  3108. break;
  3109. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3110. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3111. /*
  3112. * Free TX desc if force free is
  3113. * required, otherwise only reset vdev
  3114. * in this TX desc.
  3115. */
  3116. if (force_free) {
  3117. dp_tx_comp_free_buf(soc, tx_desc);
  3118. dp_tx_desc_release(tx_desc, i);
  3119. } else {
  3120. dp_tx_desc_reset_vdev(soc, tx_desc,
  3121. i);
  3122. }
  3123. }
  3124. }
  3125. }
  3126. }
  3127. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3128. static inline void
  3129. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3130. uint8_t desc_pool_id)
  3131. {
  3132. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3133. tx_desc->vdev = NULL;
  3134. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3135. }
  3136. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3137. struct dp_vdev *vdev,
  3138. bool force_free)
  3139. {
  3140. uint8_t i, num_pool;
  3141. uint32_t j;
  3142. uint32_t num_desc, page_id, offset;
  3143. uint16_t num_desc_per_page;
  3144. struct dp_soc *soc = pdev->soc;
  3145. struct dp_tx_desc_s *tx_desc = NULL;
  3146. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3147. if (!vdev && !force_free) {
  3148. dp_err("Reset TX desc vdev, Vdev param is required!");
  3149. return;
  3150. }
  3151. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3152. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3153. for (i = 0; i < num_pool; i++) {
  3154. tx_desc_pool = &soc->tx_desc[i];
  3155. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3156. continue;
  3157. num_desc_per_page =
  3158. tx_desc_pool->desc_pages.num_element_per_page;
  3159. for (j = 0; j < num_desc; j++) {
  3160. page_id = j / num_desc_per_page;
  3161. offset = j % num_desc_per_page;
  3162. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3163. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3164. if (force_free) {
  3165. dp_tx_comp_free_buf(soc, tx_desc);
  3166. dp_tx_desc_release(tx_desc, i);
  3167. } else {
  3168. dp_tx_desc_reset_vdev(soc, tx_desc,
  3169. i);
  3170. }
  3171. }
  3172. }
  3173. }
  3174. }
  3175. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3176. /**
  3177. * dp_tx_vdev_detach() - detach vdev from dp tx
  3178. * @vdev: virtual device instance
  3179. *
  3180. * Return: QDF_STATUS_SUCCESS: success
  3181. * QDF_STATUS_E_RESOURCES: Error return
  3182. */
  3183. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3184. {
  3185. struct dp_pdev *pdev = vdev->pdev;
  3186. /* Reset TX desc associated to this Vdev as NULL */
  3187. dp_tx_desc_flush(pdev, vdev, false);
  3188. return QDF_STATUS_SUCCESS;
  3189. }
  3190. /**
  3191. * dp_tx_pdev_attach() - attach pdev to dp tx
  3192. * @pdev: physical device instance
  3193. *
  3194. * Return: QDF_STATUS_SUCCESS: success
  3195. * QDF_STATUS_E_RESOURCES: Error return
  3196. */
  3197. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3198. {
  3199. struct dp_soc *soc = pdev->soc;
  3200. /* Initialize Flow control counters */
  3201. qdf_atomic_init(&pdev->num_tx_exception);
  3202. qdf_atomic_init(&pdev->num_tx_outstanding);
  3203. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3204. /* Initialize descriptors in TCL Ring */
  3205. hal_tx_init_data_ring(soc->hal_soc,
  3206. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3207. }
  3208. return QDF_STATUS_SUCCESS;
  3209. }
  3210. /**
  3211. * dp_tx_pdev_detach() - detach pdev from dp tx
  3212. * @pdev: physical device instance
  3213. *
  3214. * Return: QDF_STATUS_SUCCESS: success
  3215. * QDF_STATUS_E_RESOURCES: Error return
  3216. */
  3217. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3218. {
  3219. /* flush TX outstanding data per pdev */
  3220. dp_tx_desc_flush(pdev, NULL, true);
  3221. dp_tx_me_exit(pdev);
  3222. return QDF_STATUS_SUCCESS;
  3223. }
  3224. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3225. /* Pools will be allocated dynamically */
  3226. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3227. int num_desc)
  3228. {
  3229. uint8_t i;
  3230. for (i = 0; i < num_pool; i++) {
  3231. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3232. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3233. }
  3234. return 0;
  3235. }
  3236. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3237. {
  3238. uint8_t i;
  3239. for (i = 0; i < num_pool; i++)
  3240. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3241. }
  3242. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3243. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3244. int num_desc)
  3245. {
  3246. uint8_t i;
  3247. /* Allocate software Tx descriptor pools */
  3248. for (i = 0; i < num_pool; i++) {
  3249. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3251. "%s Tx Desc Pool alloc %d failed %pK",
  3252. __func__, i, soc);
  3253. return ENOMEM;
  3254. }
  3255. }
  3256. return 0;
  3257. }
  3258. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3259. {
  3260. uint8_t i;
  3261. for (i = 0; i < num_pool; i++) {
  3262. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3263. if (dp_tx_desc_pool_free(soc, i)) {
  3264. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3265. "%s Tx Desc Pool Free failed", __func__);
  3266. }
  3267. }
  3268. }
  3269. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3270. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3271. /**
  3272. * dp_tso_attach_wifi3() - TSO attach handler
  3273. * @txrx_soc: Opaque Dp handle
  3274. *
  3275. * Reserve TSO descriptor buffers
  3276. *
  3277. * Return: QDF_STATUS_E_FAILURE on failure or
  3278. * QDF_STATUS_SUCCESS on success
  3279. */
  3280. static
  3281. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3282. {
  3283. return dp_tso_soc_attach(txrx_soc);
  3284. }
  3285. /**
  3286. * dp_tso_detach_wifi3() - TSO Detach handler
  3287. * @txrx_soc: Opaque Dp handle
  3288. *
  3289. * Deallocate TSO descriptor buffers
  3290. *
  3291. * Return: QDF_STATUS_E_FAILURE on failure or
  3292. * QDF_STATUS_SUCCESS on success
  3293. */
  3294. static
  3295. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3296. {
  3297. return dp_tso_soc_detach(txrx_soc);
  3298. }
  3299. #else
  3300. static
  3301. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3302. {
  3303. return QDF_STATUS_SUCCESS;
  3304. }
  3305. static
  3306. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3307. {
  3308. return QDF_STATUS_SUCCESS;
  3309. }
  3310. #endif
  3311. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3312. {
  3313. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3314. uint8_t i;
  3315. uint8_t num_pool;
  3316. uint32_t num_desc;
  3317. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3318. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3319. for (i = 0; i < num_pool; i++)
  3320. dp_tx_tso_desc_pool_free(soc, i);
  3321. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3322. __func__, num_pool, num_desc);
  3323. for (i = 0; i < num_pool; i++)
  3324. dp_tx_tso_num_seg_pool_free(soc, i);
  3325. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3326. __func__, num_pool, num_desc);
  3327. return QDF_STATUS_SUCCESS;
  3328. }
  3329. /**
  3330. * dp_tso_attach() - TSO attach handler
  3331. * @txrx_soc: Opaque Dp handle
  3332. *
  3333. * Reserve TSO descriptor buffers
  3334. *
  3335. * Return: QDF_STATUS_E_FAILURE on failure or
  3336. * QDF_STATUS_SUCCESS on success
  3337. */
  3338. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3339. {
  3340. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3341. uint8_t i;
  3342. uint8_t num_pool;
  3343. uint32_t num_desc;
  3344. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3345. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3346. for (i = 0; i < num_pool; i++) {
  3347. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3348. dp_err("TSO Desc Pool alloc %d failed %pK",
  3349. i, soc);
  3350. return QDF_STATUS_E_FAILURE;
  3351. }
  3352. }
  3353. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3354. __func__, num_pool, num_desc);
  3355. for (i = 0; i < num_pool; i++) {
  3356. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3357. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3358. i, soc);
  3359. return QDF_STATUS_E_FAILURE;
  3360. }
  3361. }
  3362. return QDF_STATUS_SUCCESS;
  3363. }
  3364. /**
  3365. * dp_tx_soc_detach() - detach soc from dp tx
  3366. * @soc: core txrx main context
  3367. *
  3368. * This function will detach dp tx into main device context
  3369. * will free dp tx resource and initialize resources
  3370. *
  3371. * Return: QDF_STATUS_SUCCESS: success
  3372. * QDF_STATUS_E_RESOURCES: Error return
  3373. */
  3374. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3375. {
  3376. uint8_t num_pool;
  3377. uint16_t num_desc;
  3378. uint16_t num_ext_desc;
  3379. uint8_t i;
  3380. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3381. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3382. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3383. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3384. dp_tx_flow_control_deinit(soc);
  3385. dp_tx_delete_static_pools(soc, num_pool);
  3386. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3387. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3388. __func__, num_pool, num_desc);
  3389. for (i = 0; i < num_pool; i++) {
  3390. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3391. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3392. "%s Tx Ext Desc Pool Free failed",
  3393. __func__);
  3394. return QDF_STATUS_E_RESOURCES;
  3395. }
  3396. }
  3397. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3398. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3399. __func__, num_pool, num_ext_desc);
  3400. status = dp_tso_detach_wifi3(soc);
  3401. if (status != QDF_STATUS_SUCCESS)
  3402. return status;
  3403. return QDF_STATUS_SUCCESS;
  3404. }
  3405. /**
  3406. * dp_tx_soc_attach() - attach soc to dp tx
  3407. * @soc: core txrx main context
  3408. *
  3409. * This function will attach dp tx into main device context
  3410. * will allocate dp tx resource and initialize resources
  3411. *
  3412. * Return: QDF_STATUS_SUCCESS: success
  3413. * QDF_STATUS_E_RESOURCES: Error return
  3414. */
  3415. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3416. {
  3417. uint8_t i;
  3418. uint8_t num_pool;
  3419. uint32_t num_desc;
  3420. uint32_t num_ext_desc;
  3421. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3422. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3423. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3424. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3425. if (num_pool > MAX_TXDESC_POOLS)
  3426. goto fail;
  3427. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3428. goto fail;
  3429. dp_tx_flow_control_init(soc);
  3430. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3431. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3432. __func__, num_pool, num_desc);
  3433. /* Allocate extension tx descriptor pools */
  3434. for (i = 0; i < num_pool; i++) {
  3435. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3436. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3437. "MSDU Ext Desc Pool alloc %d failed %pK",
  3438. i, soc);
  3439. goto fail;
  3440. }
  3441. }
  3442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3443. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3444. __func__, num_pool, num_ext_desc);
  3445. status = dp_tso_attach_wifi3((void *)soc);
  3446. if (status != QDF_STATUS_SUCCESS)
  3447. goto fail;
  3448. /* Initialize descriptors in TCL Rings */
  3449. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3450. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3451. hal_tx_init_data_ring(soc->hal_soc,
  3452. soc->tcl_data_ring[i].hal_srng);
  3453. }
  3454. }
  3455. /*
  3456. * todo - Add a runtime config option to enable this.
  3457. */
  3458. /*
  3459. * Due to multiple issues on NPR EMU, enable it selectively
  3460. * only for NPR EMU, should be removed, once NPR platforms
  3461. * are stable.
  3462. */
  3463. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3465. "%s HAL Tx init Success", __func__);
  3466. return QDF_STATUS_SUCCESS;
  3467. fail:
  3468. /* Detach will take care of freeing only allocated resources */
  3469. dp_tx_soc_detach(soc);
  3470. return QDF_STATUS_E_RESOURCES;
  3471. }
  3472. /*
  3473. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3474. * pdev: pointer to DP PDEV structure
  3475. * seg_info_head: Pointer to the head of list
  3476. *
  3477. * return: void
  3478. */
  3479. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3480. struct dp_tx_seg_info_s *seg_info_head)
  3481. {
  3482. struct dp_tx_me_buf_t *mc_uc_buf;
  3483. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3484. qdf_nbuf_t nbuf = NULL;
  3485. uint64_t phy_addr;
  3486. while (seg_info_head) {
  3487. nbuf = seg_info_head->nbuf;
  3488. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3489. seg_info_head->frags[0].vaddr;
  3490. phy_addr = seg_info_head->frags[0].paddr_hi;
  3491. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3492. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3493. phy_addr,
  3494. QDF_DMA_TO_DEVICE , QDF_MAC_ADDR_SIZE);
  3495. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3496. qdf_nbuf_free(nbuf);
  3497. seg_info_new = seg_info_head;
  3498. seg_info_head = seg_info_head->next;
  3499. qdf_mem_free(seg_info_new);
  3500. }
  3501. }
  3502. /**
  3503. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3504. * @vdev: DP VDEV handle
  3505. * @nbuf: Multicast nbuf
  3506. * @newmac: Table of the clients to which packets have to be sent
  3507. * @new_mac_cnt: No of clients
  3508. *
  3509. * return: no of converted packets
  3510. */
  3511. uint16_t
  3512. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3513. uint8_t newmac[][QDF_MAC_ADDR_SIZE], uint8_t new_mac_cnt)
  3514. {
  3515. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3516. struct dp_pdev *pdev = vdev->pdev;
  3517. qdf_ether_header_t *eh;
  3518. uint8_t *data;
  3519. uint16_t len;
  3520. /* reference to frame dst addr */
  3521. uint8_t *dstmac;
  3522. /* copy of original frame src addr */
  3523. uint8_t srcmac[QDF_MAC_ADDR_SIZE];
  3524. /* local index into newmac */
  3525. uint8_t new_mac_idx = 0;
  3526. struct dp_tx_me_buf_t *mc_uc_buf;
  3527. qdf_nbuf_t nbuf_clone;
  3528. struct dp_tx_msdu_info_s msdu_info;
  3529. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3530. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3531. struct dp_tx_seg_info_s *seg_info_new;
  3532. qdf_dma_addr_t paddr_data;
  3533. qdf_dma_addr_t paddr_mcbuf = 0;
  3534. uint8_t empty_entry_mac[QDF_MAC_ADDR_SIZE] = {0};
  3535. QDF_STATUS status;
  3536. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3537. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3538. eh = (qdf_ether_header_t *)nbuf;
  3539. qdf_mem_copy(srcmac, eh->ether_shost, QDF_MAC_ADDR_SIZE);
  3540. len = qdf_nbuf_len(nbuf);
  3541. data = qdf_nbuf_data(nbuf);
  3542. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3543. QDF_DMA_TO_DEVICE);
  3544. if (status) {
  3545. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3546. "Mapping failure Error:%d", status);
  3547. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3548. qdf_nbuf_free(nbuf);
  3549. return 1;
  3550. }
  3551. paddr_data = qdf_nbuf_mapped_paddr_get(nbuf) + QDF_MAC_ADDR_SIZE;
  3552. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3553. dstmac = newmac[new_mac_idx];
  3554. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3555. "added mac addr (%pM)", dstmac);
  3556. /* Check for NULL Mac Address */
  3557. if (!qdf_mem_cmp(dstmac, empty_entry_mac, QDF_MAC_ADDR_SIZE))
  3558. continue;
  3559. /* frame to self mac. skip */
  3560. if (!qdf_mem_cmp(dstmac, srcmac, QDF_MAC_ADDR_SIZE))
  3561. continue;
  3562. /*
  3563. * TODO: optimize to avoid malloc in per-packet path
  3564. * For eg. seg_pool can be made part of vdev structure
  3565. */
  3566. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3567. if (!seg_info_new) {
  3568. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3569. "alloc failed");
  3570. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3571. goto fail_seg_alloc;
  3572. }
  3573. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3574. if (!mc_uc_buf)
  3575. goto fail_buf_alloc;
  3576. /*
  3577. * TODO: Check if we need to clone the nbuf
  3578. * Or can we just use the reference for all cases
  3579. */
  3580. if (new_mac_idx < (new_mac_cnt - 1)) {
  3581. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3582. if (!nbuf_clone) {
  3583. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3584. goto fail_clone;
  3585. }
  3586. } else {
  3587. /*
  3588. * Update the ref
  3589. * to account for frame sent without cloning
  3590. */
  3591. qdf_nbuf_ref(nbuf);
  3592. nbuf_clone = nbuf;
  3593. }
  3594. qdf_mem_copy(mc_uc_buf->data, dstmac, QDF_MAC_ADDR_SIZE);
  3595. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3596. QDF_DMA_TO_DEVICE, QDF_MAC_ADDR_SIZE,
  3597. &paddr_mcbuf);
  3598. if (status) {
  3599. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3600. "Mapping failure Error:%d", status);
  3601. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3602. goto fail_map;
  3603. }
  3604. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3605. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3606. seg_info_new->frags[0].paddr_hi =
  3607. (uint16_t)((uint64_t)paddr_mcbuf >> 32);
  3608. seg_info_new->frags[0].len = QDF_MAC_ADDR_SIZE;
  3609. /*preparing data fragment*/
  3610. seg_info_new->frags[1].vaddr =
  3611. qdf_nbuf_data(nbuf) + QDF_MAC_ADDR_SIZE;
  3612. seg_info_new->frags[1].paddr_lo = (uint32_t)paddr_data;
  3613. seg_info_new->frags[1].paddr_hi =
  3614. (uint16_t)(((uint64_t)paddr_data) >> 32);
  3615. seg_info_new->frags[1].len = len - QDF_MAC_ADDR_SIZE;
  3616. seg_info_new->nbuf = nbuf_clone;
  3617. seg_info_new->frag_cnt = 2;
  3618. seg_info_new->total_len = len;
  3619. seg_info_new->next = NULL;
  3620. if (!seg_info_head)
  3621. seg_info_head = seg_info_new;
  3622. else
  3623. seg_info_tail->next = seg_info_new;
  3624. seg_info_tail = seg_info_new;
  3625. }
  3626. if (!seg_info_head) {
  3627. goto free_return;
  3628. }
  3629. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3630. msdu_info.num_seg = new_mac_cnt;
  3631. msdu_info.frm_type = dp_tx_frm_me;
  3632. msdu_info.tid = HTT_INVALID_TID;
  3633. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3634. qdf_unlikely(pdev->hmmc_tid_override_en))
  3635. msdu_info.tid = pdev->hmmc_tid;
  3636. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3637. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3638. while (seg_info_head->next) {
  3639. seg_info_new = seg_info_head;
  3640. seg_info_head = seg_info_head->next;
  3641. qdf_mem_free(seg_info_new);
  3642. }
  3643. qdf_mem_free(seg_info_head);
  3644. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3645. qdf_nbuf_free(nbuf);
  3646. return new_mac_cnt;
  3647. fail_map:
  3648. qdf_nbuf_free(nbuf_clone);
  3649. fail_clone:
  3650. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3651. fail_buf_alloc:
  3652. qdf_mem_free(seg_info_new);
  3653. fail_seg_alloc:
  3654. dp_tx_me_mem_free(pdev, seg_info_head);
  3655. free_return:
  3656. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3657. qdf_nbuf_free(nbuf);
  3658. return 1;
  3659. }