holi.c 190 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include <soc/soundwire.h>
  28. #include "device_event.h"
  29. #include "msm-pcm-routing-v2.h"
  30. #include "asoc/msm-cdc-pinctrl.h"
  31. #include "asoc/wcd-mbhc-v2.h"
  32. #include "codecs/wsa881x-analog.h"
  33. #include "codecs/wcd937x/wcd937x-mbhc.h"
  34. #include "codecs/wcd937x/wcd937x.h"
  35. #include "codecs/wcd938x/wcd938x-mbhc.h"
  36. #include "codecs/wcd938x/wcd938x.h"
  37. #include "codecs/bolero/bolero-cdc.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #include "holi-port-config.h"
  40. #include "msm_holi_dailink.h"
  41. #define DRV_NAME "holi-asoc-snd"
  42. #define __CHIPSET__ "HOLI "
  43. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  44. #define SAMPLING_RATE_8KHZ 8000
  45. #define SAMPLING_RATE_11P025KHZ 11025
  46. #define SAMPLING_RATE_16KHZ 16000
  47. #define SAMPLING_RATE_22P05KHZ 22050
  48. #define SAMPLING_RATE_32KHZ 32000
  49. #define SAMPLING_RATE_44P1KHZ 44100
  50. #define SAMPLING_RATE_48KHZ 48000
  51. #define SAMPLING_RATE_88P2KHZ 88200
  52. #define SAMPLING_RATE_96KHZ 96000
  53. #define SAMPLING_RATE_176P4KHZ 176400
  54. #define SAMPLING_RATE_192KHZ 192000
  55. #define SAMPLING_RATE_352P8KHZ 352800
  56. #define SAMPLING_RATE_384KHZ 384000
  57. #define IS_FRACTIONAL(x) \
  58. ((x == SAMPLING_RATE_11P025KHZ) || (x == SAMPLING_RATE_22P05KHZ) || \
  59. (x == SAMPLING_RATE_44P1KHZ) || (x == SAMPLING_RATE_88P2KHZ) || \
  60. (x == SAMPLING_RATE_176P4KHZ) || (x == SAMPLING_RATE_352P8KHZ))
  61. #define IS_MSM_INTERFACE_MI2S(x) \
  62. ((x == PRIM_MI2S) || (x == SEC_MI2S) || (x == TERT_MI2S))
  63. #define WCD9XXX_MBHC_DEF_RLOADS 5
  64. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  65. #define CODEC_EXT_CLK_RATE 9600000
  66. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  67. #define DEV_NAME_STR_LEN 32
  68. #define WCD_MBHC_HS_V_MAX 1600
  69. #define TDM_CHANNEL_MAX 8
  70. #define DEV_NAME_STR_LEN 32
  71. /* time in us to ensure LPM doesn't go in C3/C4 */
  72. #define MSM_LL_QOS_VALUE 300
  73. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  74. #define WCN_CDC_SLIM_RX_CH_MAX 2
  75. #define WCN_CDC_SLIM_TX_CH_MAX 2
  76. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  77. enum {
  78. RX_PATH = 0,
  79. TX_PATH,
  80. MAX_PATH,
  81. };
  82. enum {
  83. TDM_0 = 0,
  84. TDM_1,
  85. TDM_2,
  86. TDM_3,
  87. TDM_4,
  88. TDM_5,
  89. TDM_6,
  90. TDM_7,
  91. TDM_PORT_MAX,
  92. };
  93. #define TDM_MAX_SLOTS 8
  94. #define TDM_SLOT_WIDTH_BITS 32
  95. enum {
  96. TDM_PRI = 0,
  97. TDM_SEC,
  98. TDM_TERT,
  99. TDM_QUAT,
  100. TDM_INTERFACE_MAX,
  101. };
  102. enum {
  103. PRIM_AUX_PCM = 0,
  104. SEC_AUX_PCM,
  105. TERT_AUX_PCM,
  106. QUAT_AUX_PCM,
  107. AUX_PCM_MAX,
  108. };
  109. enum {
  110. PRIM_MI2S = 0,
  111. SEC_MI2S,
  112. TERT_MI2S,
  113. QUAT_MI2S,
  114. MI2S_MAX,
  115. };
  116. enum {
  117. RX_CDC_DMA_RX_0 = 0,
  118. RX_CDC_DMA_RX_1,
  119. RX_CDC_DMA_RX_2,
  120. RX_CDC_DMA_RX_3,
  121. RX_CDC_DMA_RX_5,
  122. RX_CDC_DMA_RX_6,
  123. CDC_DMA_RX_MAX,
  124. };
  125. enum {
  126. TX_CDC_DMA_TX_0 = 0,
  127. TX_CDC_DMA_TX_3,
  128. TX_CDC_DMA_TX_4,
  129. VA_CDC_DMA_TX_0,
  130. VA_CDC_DMA_TX_1,
  131. VA_CDC_DMA_TX_2,
  132. CDC_DMA_TX_MAX,
  133. };
  134. enum {
  135. SLIM_RX_7 = 0,
  136. SLIM_RX_MAX,
  137. };
  138. enum {
  139. SLIM_TX_7 = 0,
  140. SLIM_TX_8,
  141. SLIM_TX_MAX,
  142. };
  143. enum {
  144. AFE_LOOPBACK_TX_IDX = 0,
  145. AFE_LOOPBACK_TX_IDX_MAX,
  146. };
  147. struct msm_asoc_mach_data {
  148. struct snd_info_entry *codec_root;
  149. int usbc_en2_gpio; /* used by gpio driver API */
  150. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  151. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  152. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  153. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  154. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  155. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  156. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  157. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  158. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  159. bool is_afe_config_done;
  160. struct device_node *fsa_handle;
  161. struct clk *lpass_audio_hw_vote;
  162. int core_audio_vote_count;
  163. };
  164. struct tdm_port {
  165. u32 mode;
  166. u32 channel;
  167. };
  168. struct tdm_dev_config {
  169. unsigned int tdm_slot_offset[TDM_MAX_SLOTS];
  170. };
  171. struct dev_config {
  172. u32 sample_rate;
  173. u32 bit_format;
  174. u32 channels;
  175. };
  176. /* Default configuration of slimbus channels */
  177. static struct dev_config slim_rx_cfg[] = {
  178. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  179. };
  180. static struct dev_config slim_tx_cfg[] = {
  181. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  182. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  183. };
  184. static struct dev_config usb_rx_cfg = {
  185. .sample_rate = SAMPLING_RATE_48KHZ,
  186. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  187. .channels = 2,
  188. };
  189. static struct dev_config usb_tx_cfg = {
  190. .sample_rate = SAMPLING_RATE_48KHZ,
  191. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  192. .channels = 1,
  193. };
  194. static struct dev_config proxy_rx_cfg = {
  195. .sample_rate = SAMPLING_RATE_48KHZ,
  196. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  197. .channels = 2,
  198. };
  199. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  200. {
  201. AFE_API_VERSION_I2S_CONFIG,
  202. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  203. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  204. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  205. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  206. 0,
  207. },
  208. {
  209. AFE_API_VERSION_I2S_CONFIG,
  210. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  211. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  212. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  213. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  214. 0,
  215. },
  216. {
  217. AFE_API_VERSION_I2S_CONFIG,
  218. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  219. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  220. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  221. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  222. 0,
  223. },
  224. {
  225. AFE_API_VERSION_I2S_CONFIG,
  226. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  227. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  228. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  229. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  230. 0,
  231. },
  232. };
  233. struct mi2s_conf {
  234. struct mutex lock;
  235. u32 ref_cnt;
  236. u32 msm_is_mi2s_master;
  237. };
  238. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  239. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  240. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  241. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  242. };
  243. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  244. /* Default configuration of TDM channels */
  245. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  246. { /* PRI TDM */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  255. },
  256. { /* SEC TDM */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  265. },
  266. { /* TERT TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  275. },
  276. { /* QUAT TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  285. },
  286. };
  287. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  288. { /* PRI TDM */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  297. },
  298. { /* SEC TDM */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  307. },
  308. { /* TERT TDM */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  317. },
  318. { /* QUAT TDM */
  319. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  320. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  327. },
  328. };
  329. /* Default configuration of AUX PCM channels */
  330. static struct dev_config aux_pcm_rx_cfg[] = {
  331. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. };
  336. static struct dev_config aux_pcm_tx_cfg[] = {
  337. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  338. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  339. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  340. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  341. };
  342. /* Default configuration of MI2S channels */
  343. static struct dev_config mi2s_rx_cfg[] = {
  344. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  345. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  346. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. };
  349. static struct dev_config mi2s_tx_cfg[] = {
  350. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  351. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  352. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  353. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  354. };
  355. static struct tdm_dev_config pri_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  356. { /* PRI TDM */
  357. { {0, 4, 0xFFFF} }, /* RX_0 */
  358. { {8, 12, 0xFFFF} }, /* RX_1 */
  359. { {16, 20, 0xFFFF} }, /* RX_2 */
  360. { {24, 28, 0xFFFF} }, /* RX_3 */
  361. { {0xFFFF} }, /* RX_4 */
  362. { {0xFFFF} }, /* RX_5 */
  363. { {0xFFFF} }, /* RX_6 */
  364. { {0xFFFF} }, /* RX_7 */
  365. },
  366. {
  367. { {0, 4, 8, 12, 0xFFFF} }, /* TX_0 */
  368. { {8, 12, 0xFFFF} }, /* TX_1 */
  369. { {16, 20, 0xFFFF} }, /* TX_2 */
  370. { {24, 28, 0xFFFF} }, /* TX_3 */
  371. { {0xFFFF} }, /* TX_4 */
  372. { {0xFFFF} }, /* TX_5 */
  373. { {0xFFFF} }, /* TX_6 */
  374. { {0xFFFF} }, /* TX_7 */
  375. },
  376. };
  377. static struct tdm_dev_config sec_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  378. { /* SEC TDM */
  379. { {0, 4, 0xFFFF} }, /* RX_0 */
  380. { {8, 12, 0xFFFF} }, /* RX_1 */
  381. { {16, 20, 0xFFFF} }, /* RX_2 */
  382. { {24, 28, 0xFFFF} }, /* RX_3 */
  383. { {0xFFFF} }, /* RX_4 */
  384. { {0xFFFF} }, /* RX_5 */
  385. { {0xFFFF} }, /* RX_6 */
  386. { {0xFFFF} }, /* RX_7 */
  387. },
  388. {
  389. { {0, 4, 0xFFFF} }, /* TX_0 */
  390. { {8, 12, 0xFFFF} }, /* TX_1 */
  391. { {16, 20, 0xFFFF} }, /* TX_2 */
  392. { {24, 28, 0xFFFF} }, /* TX_3 */
  393. { {0xFFFF} }, /* TX_4 */
  394. { {0xFFFF} }, /* TX_5 */
  395. { {0xFFFF} }, /* TX_6 */
  396. { {0xFFFF} }, /* TX_7 */
  397. },
  398. };
  399. static struct tdm_dev_config tert_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  400. { /* TERT TDM */
  401. { {0, 4, 0xFFFF} }, /* RX_0 */
  402. { {8, 12, 0xFFFF} }, /* RX_1 */
  403. { {16, 20, 0xFFFF} }, /* RX_2 */
  404. { {24, 28, 0xFFFF} }, /* RX_3 */
  405. { {0xFFFF} }, /* RX_4 */
  406. { {0xFFFF} }, /* RX_5 */
  407. { {0xFFFF} }, /* RX_6 */
  408. { {0xFFFF} }, /* RX_7 */
  409. },
  410. {
  411. { {0, 4, 0xFFFF} }, /* TX_0 */
  412. { {8, 12, 0xFFFF} }, /* TX_1 */
  413. { {16, 20, 0xFFFF} }, /* TX_2 */
  414. { {24, 28, 0xFFFF} }, /* TX_3 */
  415. { {0xFFFF} }, /* TX_4 */
  416. { {0xFFFF} }, /* TX_5 */
  417. { {0xFFFF} }, /* TX_6 */
  418. { {0xFFFF} }, /* TX_7 */
  419. },
  420. };
  421. static struct tdm_dev_config quat_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  422. { /* QUAT TDM */
  423. { {0, 4, 0xFFFF} }, /* RX_0 */
  424. { {8, 12, 0xFFFF} }, /* RX_1 */
  425. { {16, 20, 0xFFFF} }, /* RX_2 */
  426. { {24, 28, 0xFFFF} }, /* RX_3 */
  427. { {0xFFFF} }, /* RX_4 */
  428. { {0xFFFF} }, /* RX_5 */
  429. { {0xFFFF} }, /* RX_6 */
  430. { {0xFFFF} }, /* RX_7 */
  431. },
  432. {
  433. { {0, 4, 0xFFFF} }, /* TX_0 */
  434. { {8, 12, 0xFFFF} }, /* TX_1 */
  435. { {16, 20, 0xFFFF} }, /* TX_2 */
  436. { {24, 28, 0xFFFF} }, /* TX_3 */
  437. { {0xFFFF} }, /* TX_4 */
  438. { {0xFFFF} }, /* TX_5 */
  439. { {0xFFFF} }, /* TX_6 */
  440. { {0xFFFF} }, /* TX_7 */
  441. },
  442. };
  443. static void *tdm_cfg[TDM_INTERFACE_MAX] = {
  444. pri_tdm_dev_config,
  445. sec_tdm_dev_config,
  446. tert_tdm_dev_config,
  447. quat_tdm_dev_config,
  448. };
  449. /* Default configuration of Codec DMA Interface RX */
  450. static struct dev_config cdc_dma_rx_cfg[] = {
  451. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  452. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  453. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  454. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  455. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  456. [RX_CDC_DMA_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  457. };
  458. /* Default configuration of Codec DMA Interface TX */
  459. static struct dev_config cdc_dma_tx_cfg[] = {
  460. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  461. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  462. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  463. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  464. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  465. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  466. };
  467. static struct dev_config afe_loopback_tx_cfg[] = {
  468. [AFE_LOOPBACK_TX_IDX] =
  469. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  470. };
  471. static int msm_vi_feed_tx_ch = 2;
  472. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  473. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  474. "S32_LE"};
  475. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  476. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  477. "Six", "Seven", "Eight"};
  478. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  479. "KHZ_16", "KHZ_22P05",
  480. "KHZ_32", "KHZ_44P1", "KHZ_48",
  481. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  482. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  483. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  484. "Five", "Six", "Seven",
  485. "Eight"};
  486. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  487. "KHZ_48", "KHZ_176P4",
  488. "KHZ_352P8"};
  489. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  490. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  491. "Five", "Six", "Seven", "Eight"};
  492. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  493. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  494. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  495. "KHZ_48", "KHZ_88P2", "KHZ_96",
  496. "KHZ_176P4", "KHZ_192", "KHZ_352P8",
  497. "KHZ_384"};
  498. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  499. "Five", "Six", "Seven",
  500. "Eight"};
  501. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  502. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  503. "Five", "Six", "Seven",
  504. "Eight"};
  505. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  506. "KHZ_16", "KHZ_22P05",
  507. "KHZ_32", "KHZ_44P1", "KHZ_48",
  508. "KHZ_88P2", "KHZ_96",
  509. "KHZ_176P4", "KHZ_192",
  510. "KHZ_352P8", "KHZ_384"};
  511. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  512. "KHZ_16", "KHZ_22P05",
  513. "KHZ_32", "KHZ_44P1", "KHZ_48",
  514. "KHZ_88P2", "KHZ_96",
  515. "KHZ_176P4", "KHZ_192"};
  516. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  517. "KHZ_44P1", "KHZ_48",
  518. "KHZ_88P2", "KHZ_96"};
  519. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  520. "KHZ_44P1", "KHZ_48",
  521. "KHZ_88P2", "KHZ_96"};
  522. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  523. "KHZ_44P1", "KHZ_48",
  524. "KHZ_88P2", "KHZ_96"};
  525. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  526. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  587. cdc_dma_sample_rate_text);
  588. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  589. cdc_dma_sample_rate_text);
  590. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  591. cdc_dma_sample_rate_text);
  592. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  593. cdc_dma_sample_rate_text);
  594. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  595. cdc_dma_sample_rate_text);
  596. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  597. cdc_dma_sample_rate_text);
  598. /* WCD9380 */
  599. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  600. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  601. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  602. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  604. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_format, cdc80_bit_format_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  606. cdc80_dma_sample_rate_text);
  607. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  608. cdc80_dma_sample_rate_text);
  609. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  610. cdc80_dma_sample_rate_text);
  611. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  612. cdc80_dma_sample_rate_text);
  613. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  614. cdc80_dma_sample_rate_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_sample_rate,
  616. cdc80_dma_sample_rate_text);
  617. /* WCD9385 */
  618. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  619. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  620. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  622. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_format, bit_format_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  625. cdc_dma_sample_rate_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  627. cdc_dma_sample_rate_text);
  628. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  629. cdc_dma_sample_rate_text);
  630. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  631. cdc_dma_sample_rate_text);
  632. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  633. cdc_dma_sample_rate_text);
  634. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_sample_rate,
  635. cdc_dma_sample_rate_text);
  636. /* WCD937x */
  637. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  638. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  639. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  640. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  641. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  642. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  643. cdc_dma_sample_rate_text);
  644. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  645. cdc_dma_sample_rate_text);
  646. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  647. cdc_dma_sample_rate_text);
  648. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  649. cdc_dma_sample_rate_text);
  650. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  651. cdc_dma_sample_rate_text);
  652. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  653. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  654. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  655. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  656. static bool is_initial_boot;
  657. static bool codec_reg_done;
  658. static struct snd_soc_card snd_soc_card_holi_msm;
  659. static int dmic_0_1_gpio_cnt;
  660. static int dmic_2_3_gpio_cnt;
  661. static int dmic_4_5_gpio_cnt;
  662. static void *def_wcd_mbhc_cal(void);
  663. static int msm_aux_codec_init(struct snd_soc_pcm_runtime *);
  664. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *);
  665. /*
  666. * Need to report LINEIN
  667. * if R/L channel impedance is larger than 5K ohm
  668. */
  669. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  670. .read_fw_bin = false,
  671. .calibration = NULL,
  672. .detect_extn_cable = true,
  673. .mono_stero_detection = false,
  674. .swap_gnd_mic = NULL,
  675. .hs_ext_micbias = true,
  676. .key_code[0] = KEY_MEDIA,
  677. .key_code[1] = KEY_VOICECOMMAND,
  678. .key_code[2] = KEY_VOLUMEUP,
  679. .key_code[3] = KEY_VOLUMEDOWN,
  680. .key_code[4] = 0,
  681. .key_code[5] = 0,
  682. .key_code[6] = 0,
  683. .key_code[7] = 0,
  684. .linein_th = 5000,
  685. .moisture_en = false,
  686. .mbhc_micbias = MIC_BIAS_2,
  687. .anc_micbias = MIC_BIAS_2,
  688. .enable_anc_mic_detect = false,
  689. .moisture_duty_cycle_en = true,
  690. };
  691. static inline int param_is_mask(int p)
  692. {
  693. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  694. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  695. }
  696. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  697. int n)
  698. {
  699. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  700. }
  701. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  702. unsigned int bit)
  703. {
  704. if (bit >= SNDRV_MASK_MAX)
  705. return;
  706. if (param_is_mask(n)) {
  707. struct snd_mask *m = param_to_mask(p, n);
  708. m->bits[0] = 0;
  709. m->bits[1] = 0;
  710. m->bits[bit >> 5] |= (1 << (bit & 31));
  711. }
  712. }
  713. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  714. struct snd_ctl_elem_value *ucontrol)
  715. {
  716. int sample_rate_val = 0;
  717. switch (usb_rx_cfg.sample_rate) {
  718. case SAMPLING_RATE_384KHZ:
  719. sample_rate_val = 12;
  720. break;
  721. case SAMPLING_RATE_352P8KHZ:
  722. sample_rate_val = 11;
  723. break;
  724. case SAMPLING_RATE_192KHZ:
  725. sample_rate_val = 10;
  726. break;
  727. case SAMPLING_RATE_176P4KHZ:
  728. sample_rate_val = 9;
  729. break;
  730. case SAMPLING_RATE_96KHZ:
  731. sample_rate_val = 8;
  732. break;
  733. case SAMPLING_RATE_88P2KHZ:
  734. sample_rate_val = 7;
  735. break;
  736. case SAMPLING_RATE_48KHZ:
  737. sample_rate_val = 6;
  738. break;
  739. case SAMPLING_RATE_44P1KHZ:
  740. sample_rate_val = 5;
  741. break;
  742. case SAMPLING_RATE_32KHZ:
  743. sample_rate_val = 4;
  744. break;
  745. case SAMPLING_RATE_22P05KHZ:
  746. sample_rate_val = 3;
  747. break;
  748. case SAMPLING_RATE_16KHZ:
  749. sample_rate_val = 2;
  750. break;
  751. case SAMPLING_RATE_11P025KHZ:
  752. sample_rate_val = 1;
  753. break;
  754. case SAMPLING_RATE_8KHZ:
  755. default:
  756. sample_rate_val = 0;
  757. break;
  758. }
  759. ucontrol->value.integer.value[0] = sample_rate_val;
  760. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  761. usb_rx_cfg.sample_rate);
  762. return 0;
  763. }
  764. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  765. struct snd_ctl_elem_value *ucontrol)
  766. {
  767. switch (ucontrol->value.integer.value[0]) {
  768. case 12:
  769. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  770. break;
  771. case 11:
  772. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  773. break;
  774. case 10:
  775. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  776. break;
  777. case 9:
  778. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  779. break;
  780. case 8:
  781. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  782. break;
  783. case 7:
  784. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  785. break;
  786. case 6:
  787. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  788. break;
  789. case 5:
  790. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  791. break;
  792. case 4:
  793. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  794. break;
  795. case 3:
  796. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  797. break;
  798. case 2:
  799. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  800. break;
  801. case 1:
  802. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  803. break;
  804. case 0:
  805. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  806. break;
  807. default:
  808. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  809. break;
  810. }
  811. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  812. __func__, ucontrol->value.integer.value[0],
  813. usb_rx_cfg.sample_rate);
  814. return 0;
  815. }
  816. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  817. struct snd_ctl_elem_value *ucontrol)
  818. {
  819. int sample_rate_val = 0;
  820. switch (usb_tx_cfg.sample_rate) {
  821. case SAMPLING_RATE_384KHZ:
  822. sample_rate_val = 12;
  823. break;
  824. case SAMPLING_RATE_352P8KHZ:
  825. sample_rate_val = 11;
  826. break;
  827. case SAMPLING_RATE_192KHZ:
  828. sample_rate_val = 10;
  829. break;
  830. case SAMPLING_RATE_176P4KHZ:
  831. sample_rate_val = 9;
  832. break;
  833. case SAMPLING_RATE_96KHZ:
  834. sample_rate_val = 8;
  835. break;
  836. case SAMPLING_RATE_88P2KHZ:
  837. sample_rate_val = 7;
  838. break;
  839. case SAMPLING_RATE_48KHZ:
  840. sample_rate_val = 6;
  841. break;
  842. case SAMPLING_RATE_44P1KHZ:
  843. sample_rate_val = 5;
  844. break;
  845. case SAMPLING_RATE_32KHZ:
  846. sample_rate_val = 4;
  847. break;
  848. case SAMPLING_RATE_22P05KHZ:
  849. sample_rate_val = 3;
  850. break;
  851. case SAMPLING_RATE_16KHZ:
  852. sample_rate_val = 2;
  853. break;
  854. case SAMPLING_RATE_11P025KHZ:
  855. sample_rate_val = 1;
  856. break;
  857. case SAMPLING_RATE_8KHZ:
  858. sample_rate_val = 0;
  859. break;
  860. default:
  861. sample_rate_val = 6;
  862. break;
  863. }
  864. ucontrol->value.integer.value[0] = sample_rate_val;
  865. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  866. usb_tx_cfg.sample_rate);
  867. return 0;
  868. }
  869. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  870. struct snd_ctl_elem_value *ucontrol)
  871. {
  872. switch (ucontrol->value.integer.value[0]) {
  873. case 12:
  874. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  875. break;
  876. case 11:
  877. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  878. break;
  879. case 10:
  880. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  881. break;
  882. case 9:
  883. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  884. break;
  885. case 8:
  886. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  887. break;
  888. case 7:
  889. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  890. break;
  891. case 6:
  892. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  893. break;
  894. case 5:
  895. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  896. break;
  897. case 4:
  898. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  899. break;
  900. case 3:
  901. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  902. break;
  903. case 2:
  904. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  905. break;
  906. case 1:
  907. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  908. break;
  909. case 0:
  910. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  911. break;
  912. default:
  913. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  914. break;
  915. }
  916. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  917. __func__, ucontrol->value.integer.value[0],
  918. usb_tx_cfg.sample_rate);
  919. return 0;
  920. }
  921. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  922. struct snd_ctl_elem_value *ucontrol)
  923. {
  924. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  925. afe_loopback_tx_cfg[0].channels);
  926. ucontrol->value.enumerated.item[0] =
  927. afe_loopback_tx_cfg[0].channels - 1;
  928. return 0;
  929. }
  930. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  931. struct snd_ctl_elem_value *ucontrol)
  932. {
  933. afe_loopback_tx_cfg[0].channels =
  934. ucontrol->value.enumerated.item[0] + 1;
  935. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  936. afe_loopback_tx_cfg[0].channels);
  937. return 1;
  938. }
  939. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  940. struct snd_ctl_elem_value *ucontrol)
  941. {
  942. switch (usb_rx_cfg.bit_format) {
  943. case SNDRV_PCM_FORMAT_S32_LE:
  944. ucontrol->value.integer.value[0] = 3;
  945. break;
  946. case SNDRV_PCM_FORMAT_S24_3LE:
  947. ucontrol->value.integer.value[0] = 2;
  948. break;
  949. case SNDRV_PCM_FORMAT_S24_LE:
  950. ucontrol->value.integer.value[0] = 1;
  951. break;
  952. case SNDRV_PCM_FORMAT_S16_LE:
  953. default:
  954. ucontrol->value.integer.value[0] = 0;
  955. break;
  956. }
  957. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  958. __func__, usb_rx_cfg.bit_format,
  959. ucontrol->value.integer.value[0]);
  960. return 0;
  961. }
  962. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  963. struct snd_ctl_elem_value *ucontrol)
  964. {
  965. int rc = 0;
  966. switch (ucontrol->value.integer.value[0]) {
  967. case 3:
  968. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  969. break;
  970. case 2:
  971. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  972. break;
  973. case 1:
  974. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  975. break;
  976. case 0:
  977. default:
  978. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  979. break;
  980. }
  981. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  982. __func__, usb_rx_cfg.bit_format,
  983. ucontrol->value.integer.value[0]);
  984. return rc;
  985. }
  986. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  987. struct snd_ctl_elem_value *ucontrol)
  988. {
  989. switch (usb_tx_cfg.bit_format) {
  990. case SNDRV_PCM_FORMAT_S32_LE:
  991. ucontrol->value.integer.value[0] = 3;
  992. break;
  993. case SNDRV_PCM_FORMAT_S24_3LE:
  994. ucontrol->value.integer.value[0] = 2;
  995. break;
  996. case SNDRV_PCM_FORMAT_S24_LE:
  997. ucontrol->value.integer.value[0] = 1;
  998. break;
  999. case SNDRV_PCM_FORMAT_S16_LE:
  1000. default:
  1001. ucontrol->value.integer.value[0] = 0;
  1002. break;
  1003. }
  1004. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1005. __func__, usb_tx_cfg.bit_format,
  1006. ucontrol->value.integer.value[0]);
  1007. return 0;
  1008. }
  1009. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1010. struct snd_ctl_elem_value *ucontrol)
  1011. {
  1012. int rc = 0;
  1013. switch (ucontrol->value.integer.value[0]) {
  1014. case 3:
  1015. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1016. break;
  1017. case 2:
  1018. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1019. break;
  1020. case 1:
  1021. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1022. break;
  1023. case 0:
  1024. default:
  1025. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1026. break;
  1027. }
  1028. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1029. __func__, usb_tx_cfg.bit_format,
  1030. ucontrol->value.integer.value[0]);
  1031. return rc;
  1032. }
  1033. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1034. struct snd_ctl_elem_value *ucontrol)
  1035. {
  1036. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1037. usb_rx_cfg.channels);
  1038. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1039. return 0;
  1040. }
  1041. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1042. struct snd_ctl_elem_value *ucontrol)
  1043. {
  1044. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1045. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1046. return 1;
  1047. }
  1048. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1049. struct snd_ctl_elem_value *ucontrol)
  1050. {
  1051. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1052. usb_tx_cfg.channels);
  1053. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1054. return 0;
  1055. }
  1056. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1057. struct snd_ctl_elem_value *ucontrol)
  1058. {
  1059. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1060. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1061. return 1;
  1062. }
  1063. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1064. struct snd_ctl_elem_value *ucontrol)
  1065. {
  1066. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1067. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1068. ucontrol->value.integer.value[0]);
  1069. return 0;
  1070. }
  1071. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1072. struct snd_ctl_elem_value *ucontrol)
  1073. {
  1074. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1075. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1076. return 1;
  1077. }
  1078. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1079. struct snd_ctl_elem_value *ucontrol)
  1080. {
  1081. pr_debug("%s: proxy_rx channels = %d\n",
  1082. __func__, proxy_rx_cfg.channels);
  1083. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1084. return 0;
  1085. }
  1086. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1087. struct snd_ctl_elem_value *ucontrol)
  1088. {
  1089. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1090. pr_debug("%s: proxy_rx channels = %d\n",
  1091. __func__, proxy_rx_cfg.channels);
  1092. return 1;
  1093. }
  1094. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1095. struct tdm_port *port)
  1096. {
  1097. if (port) {
  1098. if (strnstr(kcontrol->id.name, "PRI",
  1099. sizeof(kcontrol->id.name))) {
  1100. port->mode = TDM_PRI;
  1101. } else if (strnstr(kcontrol->id.name, "SEC",
  1102. sizeof(kcontrol->id.name))) {
  1103. port->mode = TDM_SEC;
  1104. } else if (strnstr(kcontrol->id.name, "TERT",
  1105. sizeof(kcontrol->id.name))) {
  1106. port->mode = TDM_TERT;
  1107. } else if (strnstr(kcontrol->id.name, "QUAT",
  1108. sizeof(kcontrol->id.name))) {
  1109. port->mode = TDM_QUAT;
  1110. } else {
  1111. pr_err("%s: unsupported mode in: %s\n",
  1112. __func__, kcontrol->id.name);
  1113. return -EINVAL;
  1114. }
  1115. if (strnstr(kcontrol->id.name, "RX_0",
  1116. sizeof(kcontrol->id.name)) ||
  1117. strnstr(kcontrol->id.name, "TX_0",
  1118. sizeof(kcontrol->id.name))) {
  1119. port->channel = TDM_0;
  1120. } else if (strnstr(kcontrol->id.name, "RX_1",
  1121. sizeof(kcontrol->id.name)) ||
  1122. strnstr(kcontrol->id.name, "TX_1",
  1123. sizeof(kcontrol->id.name))) {
  1124. port->channel = TDM_1;
  1125. } else if (strnstr(kcontrol->id.name, "RX_2",
  1126. sizeof(kcontrol->id.name)) ||
  1127. strnstr(kcontrol->id.name, "TX_2",
  1128. sizeof(kcontrol->id.name))) {
  1129. port->channel = TDM_2;
  1130. } else if (strnstr(kcontrol->id.name, "RX_3",
  1131. sizeof(kcontrol->id.name)) ||
  1132. strnstr(kcontrol->id.name, "TX_3",
  1133. sizeof(kcontrol->id.name))) {
  1134. port->channel = TDM_3;
  1135. } else if (strnstr(kcontrol->id.name, "RX_4",
  1136. sizeof(kcontrol->id.name)) ||
  1137. strnstr(kcontrol->id.name, "TX_4",
  1138. sizeof(kcontrol->id.name))) {
  1139. port->channel = TDM_4;
  1140. } else if (strnstr(kcontrol->id.name, "RX_5",
  1141. sizeof(kcontrol->id.name)) ||
  1142. strnstr(kcontrol->id.name, "TX_5",
  1143. sizeof(kcontrol->id.name))) {
  1144. port->channel = TDM_5;
  1145. } else if (strnstr(kcontrol->id.name, "RX_6",
  1146. sizeof(kcontrol->id.name)) ||
  1147. strnstr(kcontrol->id.name, "TX_6",
  1148. sizeof(kcontrol->id.name))) {
  1149. port->channel = TDM_6;
  1150. } else if (strnstr(kcontrol->id.name, "RX_7",
  1151. sizeof(kcontrol->id.name)) ||
  1152. strnstr(kcontrol->id.name, "TX_7",
  1153. sizeof(kcontrol->id.name))) {
  1154. port->channel = TDM_7;
  1155. } else {
  1156. pr_err("%s: unsupported channel in: %s\n",
  1157. __func__, kcontrol->id.name);
  1158. return -EINVAL;
  1159. }
  1160. } else {
  1161. return -EINVAL;
  1162. }
  1163. return 0;
  1164. }
  1165. static int tdm_get_sample_rate(int value)
  1166. {
  1167. int sample_rate = 0;
  1168. switch (value) {
  1169. case 0:
  1170. sample_rate = SAMPLING_RATE_8KHZ;
  1171. break;
  1172. case 1:
  1173. sample_rate = SAMPLING_RATE_16KHZ;
  1174. break;
  1175. case 2:
  1176. sample_rate = SAMPLING_RATE_32KHZ;
  1177. break;
  1178. case 3:
  1179. sample_rate = SAMPLING_RATE_48KHZ;
  1180. break;
  1181. case 4:
  1182. sample_rate = SAMPLING_RATE_176P4KHZ;
  1183. break;
  1184. case 5:
  1185. sample_rate = SAMPLING_RATE_352P8KHZ;
  1186. break;
  1187. default:
  1188. sample_rate = SAMPLING_RATE_48KHZ;
  1189. break;
  1190. }
  1191. return sample_rate;
  1192. }
  1193. static int tdm_get_sample_rate_val(int sample_rate)
  1194. {
  1195. int sample_rate_val = 0;
  1196. switch (sample_rate) {
  1197. case SAMPLING_RATE_8KHZ:
  1198. sample_rate_val = 0;
  1199. break;
  1200. case SAMPLING_RATE_16KHZ:
  1201. sample_rate_val = 1;
  1202. break;
  1203. case SAMPLING_RATE_32KHZ:
  1204. sample_rate_val = 2;
  1205. break;
  1206. case SAMPLING_RATE_48KHZ:
  1207. sample_rate_val = 3;
  1208. break;
  1209. case SAMPLING_RATE_176P4KHZ:
  1210. sample_rate_val = 4;
  1211. break;
  1212. case SAMPLING_RATE_352P8KHZ:
  1213. sample_rate_val = 5;
  1214. break;
  1215. default:
  1216. sample_rate_val = 3;
  1217. break;
  1218. }
  1219. return sample_rate_val;
  1220. }
  1221. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1222. struct snd_ctl_elem_value *ucontrol)
  1223. {
  1224. struct tdm_port port;
  1225. int ret = tdm_get_port_idx(kcontrol, &port);
  1226. if (ret) {
  1227. pr_err("%s: unsupported control: %s\n",
  1228. __func__, kcontrol->id.name);
  1229. } else {
  1230. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1231. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1232. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1233. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1234. ucontrol->value.enumerated.item[0]);
  1235. }
  1236. return ret;
  1237. }
  1238. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1239. struct snd_ctl_elem_value *ucontrol)
  1240. {
  1241. struct tdm_port port;
  1242. int ret = tdm_get_port_idx(kcontrol, &port);
  1243. if (ret) {
  1244. pr_err("%s: unsupported control: %s\n",
  1245. __func__, kcontrol->id.name);
  1246. } else {
  1247. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1248. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1249. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1250. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1251. ucontrol->value.enumerated.item[0]);
  1252. }
  1253. return ret;
  1254. }
  1255. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1256. struct snd_ctl_elem_value *ucontrol)
  1257. {
  1258. struct tdm_port port;
  1259. int ret = tdm_get_port_idx(kcontrol, &port);
  1260. if (ret) {
  1261. pr_err("%s: unsupported control: %s\n",
  1262. __func__, kcontrol->id.name);
  1263. } else {
  1264. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1265. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1266. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1267. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1268. ucontrol->value.enumerated.item[0]);
  1269. }
  1270. return ret;
  1271. }
  1272. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1273. struct snd_ctl_elem_value *ucontrol)
  1274. {
  1275. struct tdm_port port;
  1276. int ret = tdm_get_port_idx(kcontrol, &port);
  1277. if (ret) {
  1278. pr_err("%s: unsupported control: %s\n",
  1279. __func__, kcontrol->id.name);
  1280. } else {
  1281. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1282. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1283. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1284. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1285. ucontrol->value.enumerated.item[0]);
  1286. }
  1287. return ret;
  1288. }
  1289. static int tdm_get_format(int value)
  1290. {
  1291. int format = 0;
  1292. switch (value) {
  1293. case 0:
  1294. format = SNDRV_PCM_FORMAT_S16_LE;
  1295. break;
  1296. case 1:
  1297. format = SNDRV_PCM_FORMAT_S24_LE;
  1298. break;
  1299. case 2:
  1300. format = SNDRV_PCM_FORMAT_S32_LE;
  1301. break;
  1302. default:
  1303. format = SNDRV_PCM_FORMAT_S16_LE;
  1304. break;
  1305. }
  1306. return format;
  1307. }
  1308. static int tdm_get_format_val(int format)
  1309. {
  1310. int value = 0;
  1311. switch (format) {
  1312. case SNDRV_PCM_FORMAT_S16_LE:
  1313. value = 0;
  1314. break;
  1315. case SNDRV_PCM_FORMAT_S24_LE:
  1316. value = 1;
  1317. break;
  1318. case SNDRV_PCM_FORMAT_S32_LE:
  1319. value = 2;
  1320. break;
  1321. default:
  1322. value = 0;
  1323. break;
  1324. }
  1325. return value;
  1326. }
  1327. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1328. struct snd_ctl_elem_value *ucontrol)
  1329. {
  1330. struct tdm_port port;
  1331. int ret = tdm_get_port_idx(kcontrol, &port);
  1332. if (ret) {
  1333. pr_err("%s: unsupported control: %s\n",
  1334. __func__, kcontrol->id.name);
  1335. } else {
  1336. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1337. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1338. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1339. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1340. ucontrol->value.enumerated.item[0]);
  1341. }
  1342. return ret;
  1343. }
  1344. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1345. struct snd_ctl_elem_value *ucontrol)
  1346. {
  1347. struct tdm_port port;
  1348. int ret = tdm_get_port_idx(kcontrol, &port);
  1349. if (ret) {
  1350. pr_err("%s: unsupported control: %s\n",
  1351. __func__, kcontrol->id.name);
  1352. } else {
  1353. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1354. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1355. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1356. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1357. ucontrol->value.enumerated.item[0]);
  1358. }
  1359. return ret;
  1360. }
  1361. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1362. struct snd_ctl_elem_value *ucontrol)
  1363. {
  1364. struct tdm_port port;
  1365. int ret = tdm_get_port_idx(kcontrol, &port);
  1366. if (ret) {
  1367. pr_err("%s: unsupported control: %s\n",
  1368. __func__, kcontrol->id.name);
  1369. } else {
  1370. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1371. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1372. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1373. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1374. ucontrol->value.enumerated.item[0]);
  1375. }
  1376. return ret;
  1377. }
  1378. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1379. struct snd_ctl_elem_value *ucontrol)
  1380. {
  1381. struct tdm_port port;
  1382. int ret = tdm_get_port_idx(kcontrol, &port);
  1383. if (ret) {
  1384. pr_err("%s: unsupported control: %s\n",
  1385. __func__, kcontrol->id.name);
  1386. } else {
  1387. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1388. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1389. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1390. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1391. ucontrol->value.enumerated.item[0]);
  1392. }
  1393. return ret;
  1394. }
  1395. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1396. struct snd_ctl_elem_value *ucontrol)
  1397. {
  1398. struct tdm_port port;
  1399. int ret = tdm_get_port_idx(kcontrol, &port);
  1400. if (ret) {
  1401. pr_err("%s: unsupported control: %s\n",
  1402. __func__, kcontrol->id.name);
  1403. } else {
  1404. ucontrol->value.enumerated.item[0] =
  1405. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1406. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1407. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1408. ucontrol->value.enumerated.item[0]);
  1409. }
  1410. return ret;
  1411. }
  1412. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1413. struct snd_ctl_elem_value *ucontrol)
  1414. {
  1415. struct tdm_port port;
  1416. int ret = tdm_get_port_idx(kcontrol, &port);
  1417. if (ret) {
  1418. pr_err("%s: unsupported control: %s\n",
  1419. __func__, kcontrol->id.name);
  1420. } else {
  1421. tdm_rx_cfg[port.mode][port.channel].channels =
  1422. ucontrol->value.enumerated.item[0] + 1;
  1423. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1424. tdm_rx_cfg[port.mode][port.channel].channels,
  1425. ucontrol->value.enumerated.item[0] + 1);
  1426. }
  1427. return ret;
  1428. }
  1429. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1430. struct snd_ctl_elem_value *ucontrol)
  1431. {
  1432. struct tdm_port port;
  1433. int ret = tdm_get_port_idx(kcontrol, &port);
  1434. if (ret) {
  1435. pr_err("%s: unsupported control: %s\n",
  1436. __func__, kcontrol->id.name);
  1437. } else {
  1438. ucontrol->value.enumerated.item[0] =
  1439. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1440. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1441. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1442. ucontrol->value.enumerated.item[0]);
  1443. }
  1444. return ret;
  1445. }
  1446. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1447. struct snd_ctl_elem_value *ucontrol)
  1448. {
  1449. struct tdm_port port;
  1450. int ret = tdm_get_port_idx(kcontrol, &port);
  1451. if (ret) {
  1452. pr_err("%s: unsupported control: %s\n",
  1453. __func__, kcontrol->id.name);
  1454. } else {
  1455. tdm_tx_cfg[port.mode][port.channel].channels =
  1456. ucontrol->value.enumerated.item[0] + 1;
  1457. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1458. tdm_tx_cfg[port.mode][port.channel].channels,
  1459. ucontrol->value.enumerated.item[0] + 1);
  1460. }
  1461. return ret;
  1462. }
  1463. static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
  1464. struct snd_ctl_elem_value *ucontrol)
  1465. {
  1466. int slot_index = 0;
  1467. int interface = ucontrol->value.integer.value[0];
  1468. int channel = ucontrol->value.integer.value[1];
  1469. unsigned int offset_val = 0;
  1470. unsigned int *slot_offset = NULL;
  1471. struct tdm_dev_config *config = NULL;
  1472. if (interface < 0 || interface >= (TDM_INTERFACE_MAX * MAX_PATH)) {
  1473. pr_err("%s: incorrect interface = %d\n", __func__, interface);
  1474. return -EINVAL;
  1475. }
  1476. if (channel < 0 || channel >= TDM_PORT_MAX) {
  1477. pr_err("%s: incorrect channel = %d\n", __func__, channel);
  1478. return -EINVAL;
  1479. }
  1480. pr_debug("%s: interface = %d, channel = %d\n", __func__,
  1481. interface, channel);
  1482. config = ((struct tdm_dev_config *) tdm_cfg[interface / MAX_PATH]) +
  1483. ((interface % MAX_PATH) * TDM_PORT_MAX) + channel;
  1484. slot_offset = config->tdm_slot_offset;
  1485. for (slot_index = 0; slot_index < TDM_MAX_SLOTS; slot_index++) {
  1486. offset_val = ucontrol->value.integer.value[MAX_PATH +
  1487. slot_index];
  1488. /* Offset value can only be 0, 4, 8, ..28 */
  1489. if (offset_val % 4 == 0 && offset_val <= 28)
  1490. slot_offset[slot_index] = offset_val;
  1491. pr_debug("%s: slot offset[%d] = %d\n", __func__,
  1492. slot_index, slot_offset[slot_index]);
  1493. }
  1494. return 0;
  1495. }
  1496. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1497. {
  1498. int idx = 0;
  1499. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1500. sizeof("PRIM_AUX_PCM"))) {
  1501. idx = PRIM_AUX_PCM;
  1502. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1503. sizeof("SEC_AUX_PCM"))) {
  1504. idx = SEC_AUX_PCM;
  1505. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1506. sizeof("TERT_AUX_PCM"))) {
  1507. idx = TERT_AUX_PCM;
  1508. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1509. sizeof("QUAT_AUX_PCM"))) {
  1510. idx = QUAT_AUX_PCM;
  1511. } else {
  1512. pr_err("%s: unsupported port: %s\n",
  1513. __func__, kcontrol->id.name);
  1514. idx = -EINVAL;
  1515. }
  1516. return idx;
  1517. }
  1518. static int aux_pcm_get_sample_rate(int value)
  1519. {
  1520. int sample_rate = 0;
  1521. switch (value) {
  1522. case 1:
  1523. sample_rate = SAMPLING_RATE_16KHZ;
  1524. break;
  1525. case 0:
  1526. default:
  1527. sample_rate = SAMPLING_RATE_8KHZ;
  1528. break;
  1529. }
  1530. return sample_rate;
  1531. }
  1532. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1533. {
  1534. int sample_rate_val = 0;
  1535. switch (sample_rate) {
  1536. case SAMPLING_RATE_16KHZ:
  1537. sample_rate_val = 1;
  1538. break;
  1539. case SAMPLING_RATE_8KHZ:
  1540. default:
  1541. sample_rate_val = 0;
  1542. break;
  1543. }
  1544. return sample_rate_val;
  1545. }
  1546. static int mi2s_auxpcm_get_format(int value)
  1547. {
  1548. int format = 0;
  1549. switch (value) {
  1550. case 0:
  1551. format = SNDRV_PCM_FORMAT_S16_LE;
  1552. break;
  1553. case 1:
  1554. format = SNDRV_PCM_FORMAT_S24_LE;
  1555. break;
  1556. case 2:
  1557. format = SNDRV_PCM_FORMAT_S24_3LE;
  1558. break;
  1559. case 3:
  1560. format = SNDRV_PCM_FORMAT_S32_LE;
  1561. break;
  1562. default:
  1563. format = SNDRV_PCM_FORMAT_S16_LE;
  1564. break;
  1565. }
  1566. return format;
  1567. }
  1568. static int mi2s_auxpcm_get_format_value(int format)
  1569. {
  1570. int value = 0;
  1571. switch (format) {
  1572. case SNDRV_PCM_FORMAT_S16_LE:
  1573. value = 0;
  1574. break;
  1575. case SNDRV_PCM_FORMAT_S24_LE:
  1576. value = 1;
  1577. break;
  1578. case SNDRV_PCM_FORMAT_S24_3LE:
  1579. value = 2;
  1580. break;
  1581. case SNDRV_PCM_FORMAT_S32_LE:
  1582. value = 3;
  1583. break;
  1584. default:
  1585. value = 0;
  1586. break;
  1587. }
  1588. return value;
  1589. }
  1590. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1591. struct snd_ctl_elem_value *ucontrol)
  1592. {
  1593. int idx = aux_pcm_get_port_idx(kcontrol);
  1594. if (idx < 0)
  1595. return idx;
  1596. ucontrol->value.enumerated.item[0] =
  1597. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1598. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1599. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1600. ucontrol->value.enumerated.item[0]);
  1601. return 0;
  1602. }
  1603. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1604. struct snd_ctl_elem_value *ucontrol)
  1605. {
  1606. int idx = aux_pcm_get_port_idx(kcontrol);
  1607. if (idx < 0)
  1608. return idx;
  1609. aux_pcm_rx_cfg[idx].sample_rate =
  1610. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1611. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1612. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1613. ucontrol->value.enumerated.item[0]);
  1614. return 0;
  1615. }
  1616. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1617. struct snd_ctl_elem_value *ucontrol)
  1618. {
  1619. int idx = aux_pcm_get_port_idx(kcontrol);
  1620. if (idx < 0)
  1621. return idx;
  1622. ucontrol->value.enumerated.item[0] =
  1623. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1624. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1625. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1626. ucontrol->value.enumerated.item[0]);
  1627. return 0;
  1628. }
  1629. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1630. struct snd_ctl_elem_value *ucontrol)
  1631. {
  1632. int idx = aux_pcm_get_port_idx(kcontrol);
  1633. if (idx < 0)
  1634. return idx;
  1635. aux_pcm_tx_cfg[idx].sample_rate =
  1636. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1637. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1638. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1639. ucontrol->value.enumerated.item[0]);
  1640. return 0;
  1641. }
  1642. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1643. struct snd_ctl_elem_value *ucontrol)
  1644. {
  1645. int idx = aux_pcm_get_port_idx(kcontrol);
  1646. if (idx < 0)
  1647. return idx;
  1648. ucontrol->value.enumerated.item[0] =
  1649. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1650. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1651. idx, aux_pcm_rx_cfg[idx].bit_format,
  1652. ucontrol->value.enumerated.item[0]);
  1653. return 0;
  1654. }
  1655. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1656. struct snd_ctl_elem_value *ucontrol)
  1657. {
  1658. int idx = aux_pcm_get_port_idx(kcontrol);
  1659. if (idx < 0)
  1660. return idx;
  1661. aux_pcm_rx_cfg[idx].bit_format =
  1662. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1663. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1664. idx, aux_pcm_rx_cfg[idx].bit_format,
  1665. ucontrol->value.enumerated.item[0]);
  1666. return 0;
  1667. }
  1668. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1669. struct snd_ctl_elem_value *ucontrol)
  1670. {
  1671. int idx = aux_pcm_get_port_idx(kcontrol);
  1672. if (idx < 0)
  1673. return idx;
  1674. ucontrol->value.enumerated.item[0] =
  1675. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1676. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1677. idx, aux_pcm_tx_cfg[idx].bit_format,
  1678. ucontrol->value.enumerated.item[0]);
  1679. return 0;
  1680. }
  1681. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1682. struct snd_ctl_elem_value *ucontrol)
  1683. {
  1684. int idx = aux_pcm_get_port_idx(kcontrol);
  1685. if (idx < 0)
  1686. return idx;
  1687. aux_pcm_tx_cfg[idx].bit_format =
  1688. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1689. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1690. idx, aux_pcm_tx_cfg[idx].bit_format,
  1691. ucontrol->value.enumerated.item[0]);
  1692. return 0;
  1693. }
  1694. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1695. {
  1696. int idx = 0;
  1697. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1698. sizeof("PRIM_MI2S_RX"))) {
  1699. idx = PRIM_MI2S;
  1700. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1701. sizeof("SEC_MI2S_RX"))) {
  1702. idx = SEC_MI2S;
  1703. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1704. sizeof("TERT_MI2S_RX"))) {
  1705. idx = TERT_MI2S;
  1706. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1707. sizeof("QUAT_MI2S_RX"))) {
  1708. idx = QUAT_MI2S;
  1709. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1710. sizeof("PRIM_MI2S_TX"))) {
  1711. idx = PRIM_MI2S;
  1712. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1713. sizeof("SEC_MI2S_TX"))) {
  1714. idx = SEC_MI2S;
  1715. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1716. sizeof("TERT_MI2S_TX"))) {
  1717. idx = TERT_MI2S;
  1718. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1719. sizeof("QUAT_MI2S_TX"))) {
  1720. idx = QUAT_MI2S;
  1721. } else {
  1722. pr_err("%s: unsupported channel: %s\n",
  1723. __func__, kcontrol->id.name);
  1724. idx = -EINVAL;
  1725. }
  1726. return idx;
  1727. }
  1728. static int mi2s_get_sample_rate(int value)
  1729. {
  1730. int sample_rate = 0;
  1731. switch (value) {
  1732. case 0:
  1733. sample_rate = SAMPLING_RATE_8KHZ;
  1734. break;
  1735. case 1:
  1736. sample_rate = SAMPLING_RATE_11P025KHZ;
  1737. break;
  1738. case 2:
  1739. sample_rate = SAMPLING_RATE_16KHZ;
  1740. break;
  1741. case 3:
  1742. sample_rate = SAMPLING_RATE_22P05KHZ;
  1743. break;
  1744. case 4:
  1745. sample_rate = SAMPLING_RATE_32KHZ;
  1746. break;
  1747. case 5:
  1748. sample_rate = SAMPLING_RATE_44P1KHZ;
  1749. break;
  1750. case 6:
  1751. sample_rate = SAMPLING_RATE_48KHZ;
  1752. break;
  1753. case 7:
  1754. sample_rate = SAMPLING_RATE_88P2KHZ;
  1755. break;
  1756. case 8:
  1757. sample_rate = SAMPLING_RATE_96KHZ;
  1758. break;
  1759. case 9:
  1760. sample_rate = SAMPLING_RATE_176P4KHZ;
  1761. break;
  1762. case 10:
  1763. sample_rate = SAMPLING_RATE_192KHZ;
  1764. break;
  1765. case 11:
  1766. sample_rate = SAMPLING_RATE_352P8KHZ;
  1767. break;
  1768. case 12:
  1769. sample_rate = SAMPLING_RATE_384KHZ;
  1770. break;
  1771. default:
  1772. sample_rate = SAMPLING_RATE_48KHZ;
  1773. break;
  1774. }
  1775. return sample_rate;
  1776. }
  1777. static int mi2s_get_sample_rate_val(int sample_rate)
  1778. {
  1779. int sample_rate_val = 0;
  1780. switch (sample_rate) {
  1781. case SAMPLING_RATE_8KHZ:
  1782. sample_rate_val = 0;
  1783. break;
  1784. case SAMPLING_RATE_11P025KHZ:
  1785. sample_rate_val = 1;
  1786. break;
  1787. case SAMPLING_RATE_16KHZ:
  1788. sample_rate_val = 2;
  1789. break;
  1790. case SAMPLING_RATE_22P05KHZ:
  1791. sample_rate_val = 3;
  1792. break;
  1793. case SAMPLING_RATE_32KHZ:
  1794. sample_rate_val = 4;
  1795. break;
  1796. case SAMPLING_RATE_44P1KHZ:
  1797. sample_rate_val = 5;
  1798. break;
  1799. case SAMPLING_RATE_48KHZ:
  1800. sample_rate_val = 6;
  1801. break;
  1802. case SAMPLING_RATE_88P2KHZ:
  1803. sample_rate_val = 7;
  1804. break;
  1805. case SAMPLING_RATE_96KHZ:
  1806. sample_rate_val = 8;
  1807. break;
  1808. case SAMPLING_RATE_176P4KHZ:
  1809. sample_rate_val = 9;
  1810. break;
  1811. case SAMPLING_RATE_192KHZ:
  1812. sample_rate_val = 10;
  1813. break;
  1814. case SAMPLING_RATE_352P8KHZ:
  1815. sample_rate_val = 11;
  1816. break;
  1817. case SAMPLING_RATE_384KHZ:
  1818. sample_rate_val = 12;
  1819. break;
  1820. default:
  1821. sample_rate_val = 6;
  1822. break;
  1823. }
  1824. return sample_rate_val;
  1825. }
  1826. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1827. struct snd_ctl_elem_value *ucontrol)
  1828. {
  1829. int idx = mi2s_get_port_idx(kcontrol);
  1830. if (idx < 0)
  1831. return idx;
  1832. ucontrol->value.enumerated.item[0] =
  1833. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1834. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1835. idx, mi2s_rx_cfg[idx].sample_rate,
  1836. ucontrol->value.enumerated.item[0]);
  1837. return 0;
  1838. }
  1839. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1840. struct snd_ctl_elem_value *ucontrol)
  1841. {
  1842. int idx = mi2s_get_port_idx(kcontrol);
  1843. if (idx < 0)
  1844. return idx;
  1845. mi2s_rx_cfg[idx].sample_rate =
  1846. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1847. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1848. idx, mi2s_rx_cfg[idx].sample_rate,
  1849. ucontrol->value.enumerated.item[0]);
  1850. return 0;
  1851. }
  1852. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1853. struct snd_ctl_elem_value *ucontrol)
  1854. {
  1855. int idx = mi2s_get_port_idx(kcontrol);
  1856. if (idx < 0)
  1857. return idx;
  1858. ucontrol->value.enumerated.item[0] =
  1859. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1860. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1861. idx, mi2s_tx_cfg[idx].sample_rate,
  1862. ucontrol->value.enumerated.item[0]);
  1863. return 0;
  1864. }
  1865. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1866. struct snd_ctl_elem_value *ucontrol)
  1867. {
  1868. int idx = mi2s_get_port_idx(kcontrol);
  1869. if (idx < 0)
  1870. return idx;
  1871. mi2s_tx_cfg[idx].sample_rate =
  1872. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1873. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1874. idx, mi2s_tx_cfg[idx].sample_rate,
  1875. ucontrol->value.enumerated.item[0]);
  1876. return 0;
  1877. }
  1878. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1879. struct snd_ctl_elem_value *ucontrol)
  1880. {
  1881. int idx = mi2s_get_port_idx(kcontrol);
  1882. if (idx < 0)
  1883. return idx;
  1884. ucontrol->value.enumerated.item[0] =
  1885. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1886. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1887. idx, mi2s_rx_cfg[idx].bit_format,
  1888. ucontrol->value.enumerated.item[0]);
  1889. return 0;
  1890. }
  1891. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1892. struct snd_ctl_elem_value *ucontrol)
  1893. {
  1894. int idx = mi2s_get_port_idx(kcontrol);
  1895. if (idx < 0)
  1896. return idx;
  1897. mi2s_rx_cfg[idx].bit_format =
  1898. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1899. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1900. idx, mi2s_rx_cfg[idx].bit_format,
  1901. ucontrol->value.enumerated.item[0]);
  1902. return 0;
  1903. }
  1904. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1905. struct snd_ctl_elem_value *ucontrol)
  1906. {
  1907. int idx = mi2s_get_port_idx(kcontrol);
  1908. if (idx < 0)
  1909. return idx;
  1910. ucontrol->value.enumerated.item[0] =
  1911. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1912. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1913. idx, mi2s_tx_cfg[idx].bit_format,
  1914. ucontrol->value.enumerated.item[0]);
  1915. return 0;
  1916. }
  1917. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_value *ucontrol)
  1919. {
  1920. int idx = mi2s_get_port_idx(kcontrol);
  1921. if (idx < 0)
  1922. return idx;
  1923. mi2s_tx_cfg[idx].bit_format =
  1924. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1925. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1926. idx, mi2s_tx_cfg[idx].bit_format,
  1927. ucontrol->value.enumerated.item[0]);
  1928. return 0;
  1929. }
  1930. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1931. struct snd_ctl_elem_value *ucontrol)
  1932. {
  1933. int idx = mi2s_get_port_idx(kcontrol);
  1934. if (idx < 0)
  1935. return idx;
  1936. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1937. idx, mi2s_rx_cfg[idx].channels);
  1938. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1939. return 0;
  1940. }
  1941. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1942. struct snd_ctl_elem_value *ucontrol)
  1943. {
  1944. int idx = mi2s_get_port_idx(kcontrol);
  1945. if (idx < 0)
  1946. return idx;
  1947. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1948. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1949. idx, mi2s_rx_cfg[idx].channels);
  1950. return 1;
  1951. }
  1952. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1953. struct snd_ctl_elem_value *ucontrol)
  1954. {
  1955. int idx = mi2s_get_port_idx(kcontrol);
  1956. if (idx < 0)
  1957. return idx;
  1958. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1959. idx, mi2s_tx_cfg[idx].channels);
  1960. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1961. return 0;
  1962. }
  1963. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1964. struct snd_ctl_elem_value *ucontrol)
  1965. {
  1966. int idx = mi2s_get_port_idx(kcontrol);
  1967. if (idx < 0)
  1968. return idx;
  1969. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1970. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1971. idx, mi2s_tx_cfg[idx].channels);
  1972. return 1;
  1973. }
  1974. static int msm_get_port_id(int be_id)
  1975. {
  1976. int afe_port_id = 0;
  1977. switch (be_id) {
  1978. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  1979. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  1980. break;
  1981. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  1982. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  1983. break;
  1984. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  1985. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  1986. break;
  1987. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  1988. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  1989. break;
  1990. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  1991. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  1992. break;
  1993. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  1994. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  1995. break;
  1996. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  1997. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  1998. break;
  1999. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2000. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2001. break;
  2002. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2003. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2004. break;
  2005. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2006. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2007. break;
  2008. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2009. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2010. break;
  2011. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2012. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_0;
  2013. break;
  2014. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2015. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_0;
  2016. break;
  2017. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2018. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_1;
  2019. break;
  2020. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_1:
  2021. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_1;
  2022. break;
  2023. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2024. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_2;
  2025. break;
  2026. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_2:
  2027. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_2;
  2028. break;
  2029. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2030. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_3;
  2031. break;
  2032. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2033. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_3;
  2034. break;
  2035. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  2036. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_4;
  2037. break;
  2038. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2039. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_4;
  2040. break;
  2041. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2042. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_5;
  2043. break;
  2044. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_5:
  2045. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_5;
  2046. break;
  2047. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  2048. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_6;
  2049. break;
  2050. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_7:
  2051. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_7;
  2052. break;
  2053. default:
  2054. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2055. afe_port_id = -EINVAL;
  2056. }
  2057. return afe_port_id;
  2058. }
  2059. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2060. {
  2061. u32 bit_per_sample = 0;
  2062. switch (bit_format) {
  2063. case SNDRV_PCM_FORMAT_S32_LE:
  2064. case SNDRV_PCM_FORMAT_S24_3LE:
  2065. case SNDRV_PCM_FORMAT_S24_LE:
  2066. bit_per_sample = 32;
  2067. break;
  2068. case SNDRV_PCM_FORMAT_S16_LE:
  2069. default:
  2070. bit_per_sample = 16;
  2071. break;
  2072. }
  2073. return bit_per_sample;
  2074. }
  2075. static void update_mi2s_clk_val(int dai_id, int stream)
  2076. {
  2077. u32 bit_per_sample = 0;
  2078. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2079. bit_per_sample =
  2080. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2081. mi2s_clk[dai_id].clk_freq_in_hz =
  2082. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2083. } else {
  2084. bit_per_sample =
  2085. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2086. mi2s_clk[dai_id].clk_freq_in_hz =
  2087. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2088. }
  2089. }
  2090. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2091. {
  2092. int ret = 0;
  2093. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2094. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2095. int port_id = 0;
  2096. int index = cpu_dai->id;
  2097. port_id = msm_get_port_id(rtd->dai_link->id);
  2098. if (port_id < 0) {
  2099. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2100. ret = port_id;
  2101. goto err;
  2102. }
  2103. if (enable) {
  2104. update_mi2s_clk_val(index, substream->stream);
  2105. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2106. mi2s_clk[index].clk_freq_in_hz);
  2107. }
  2108. mi2s_clk[index].enable = enable;
  2109. ret = afe_set_lpass_clock_v2(port_id,
  2110. &mi2s_clk[index]);
  2111. if (ret < 0) {
  2112. dev_err(rtd->card->dev,
  2113. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2114. __func__, port_id, ret);
  2115. goto err;
  2116. }
  2117. err:
  2118. return ret;
  2119. }
  2120. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2121. {
  2122. int idx = 0;
  2123. if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2124. sizeof("RX_CDC_DMA_RX_0")))
  2125. idx = RX_CDC_DMA_RX_0;
  2126. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2127. sizeof("RX_CDC_DMA_RX_1")))
  2128. idx = RX_CDC_DMA_RX_1;
  2129. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2130. sizeof("RX_CDC_DMA_RX_2")))
  2131. idx = RX_CDC_DMA_RX_2;
  2132. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2133. sizeof("RX_CDC_DMA_RX_3")))
  2134. idx = RX_CDC_DMA_RX_3;
  2135. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2136. sizeof("RX_CDC_DMA_RX_5")))
  2137. idx = RX_CDC_DMA_RX_5;
  2138. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_6",
  2139. sizeof("RX_CDC_DMA_RX_6")))
  2140. idx = RX_CDC_DMA_RX_6;
  2141. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2142. sizeof("TX_CDC_DMA_TX_0")))
  2143. idx = TX_CDC_DMA_TX_0;
  2144. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2145. sizeof("TX_CDC_DMA_TX_3")))
  2146. idx = TX_CDC_DMA_TX_3;
  2147. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2148. sizeof("TX_CDC_DMA_TX_4")))
  2149. idx = TX_CDC_DMA_TX_4;
  2150. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2151. sizeof("VA_CDC_DMA_TX_0")))
  2152. idx = VA_CDC_DMA_TX_0;
  2153. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2154. sizeof("VA_CDC_DMA_TX_1")))
  2155. idx = VA_CDC_DMA_TX_1;
  2156. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2157. sizeof("VA_CDC_DMA_TX_2")))
  2158. idx = VA_CDC_DMA_TX_2;
  2159. else {
  2160. pr_err("%s: unsupported channel: %s\n",
  2161. __func__, kcontrol->id.name);
  2162. return -EINVAL;
  2163. }
  2164. return idx;
  2165. }
  2166. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2167. struct snd_ctl_elem_value *ucontrol)
  2168. {
  2169. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2170. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2171. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2172. return ch_num;
  2173. }
  2174. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2175. cdc_dma_rx_cfg[ch_num].channels - 1);
  2176. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2177. return 0;
  2178. }
  2179. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2180. struct snd_ctl_elem_value *ucontrol)
  2181. {
  2182. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2183. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2184. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2185. return ch_num;
  2186. }
  2187. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2188. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2189. cdc_dma_rx_cfg[ch_num].channels);
  2190. return 1;
  2191. }
  2192. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2193. struct snd_ctl_elem_value *ucontrol)
  2194. {
  2195. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2196. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2197. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2198. return ch_num;
  2199. }
  2200. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2201. case SNDRV_PCM_FORMAT_S32_LE:
  2202. ucontrol->value.integer.value[0] = 3;
  2203. break;
  2204. case SNDRV_PCM_FORMAT_S24_3LE:
  2205. ucontrol->value.integer.value[0] = 2;
  2206. break;
  2207. case SNDRV_PCM_FORMAT_S24_LE:
  2208. ucontrol->value.integer.value[0] = 1;
  2209. break;
  2210. case SNDRV_PCM_FORMAT_S16_LE:
  2211. default:
  2212. ucontrol->value.integer.value[0] = 0;
  2213. break;
  2214. }
  2215. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2216. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2217. ucontrol->value.integer.value[0]);
  2218. return 0;
  2219. }
  2220. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2221. struct snd_ctl_elem_value *ucontrol)
  2222. {
  2223. int rc = 0;
  2224. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2225. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2226. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2227. return ch_num;
  2228. }
  2229. switch (ucontrol->value.integer.value[0]) {
  2230. case 3:
  2231. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2232. break;
  2233. case 2:
  2234. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2235. break;
  2236. case 1:
  2237. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2238. break;
  2239. case 0:
  2240. default:
  2241. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2242. break;
  2243. }
  2244. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2245. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2246. ucontrol->value.integer.value[0]);
  2247. return rc;
  2248. }
  2249. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2250. {
  2251. int sample_rate_val = 0;
  2252. switch (sample_rate) {
  2253. case SAMPLING_RATE_8KHZ:
  2254. sample_rate_val = 0;
  2255. break;
  2256. case SAMPLING_RATE_11P025KHZ:
  2257. sample_rate_val = 1;
  2258. break;
  2259. case SAMPLING_RATE_16KHZ:
  2260. sample_rate_val = 2;
  2261. break;
  2262. case SAMPLING_RATE_22P05KHZ:
  2263. sample_rate_val = 3;
  2264. break;
  2265. case SAMPLING_RATE_32KHZ:
  2266. sample_rate_val = 4;
  2267. break;
  2268. case SAMPLING_RATE_44P1KHZ:
  2269. sample_rate_val = 5;
  2270. break;
  2271. case SAMPLING_RATE_48KHZ:
  2272. sample_rate_val = 6;
  2273. break;
  2274. case SAMPLING_RATE_88P2KHZ:
  2275. sample_rate_val = 7;
  2276. break;
  2277. case SAMPLING_RATE_96KHZ:
  2278. sample_rate_val = 8;
  2279. break;
  2280. case SAMPLING_RATE_176P4KHZ:
  2281. sample_rate_val = 9;
  2282. break;
  2283. case SAMPLING_RATE_192KHZ:
  2284. sample_rate_val = 10;
  2285. break;
  2286. case SAMPLING_RATE_352P8KHZ:
  2287. sample_rate_val = 11;
  2288. break;
  2289. case SAMPLING_RATE_384KHZ:
  2290. sample_rate_val = 12;
  2291. break;
  2292. default:
  2293. sample_rate_val = 6;
  2294. break;
  2295. }
  2296. return sample_rate_val;
  2297. }
  2298. static int cdc_dma_get_sample_rate(int value)
  2299. {
  2300. int sample_rate = 0;
  2301. switch (value) {
  2302. case 0:
  2303. sample_rate = SAMPLING_RATE_8KHZ;
  2304. break;
  2305. case 1:
  2306. sample_rate = SAMPLING_RATE_11P025KHZ;
  2307. break;
  2308. case 2:
  2309. sample_rate = SAMPLING_RATE_16KHZ;
  2310. break;
  2311. case 3:
  2312. sample_rate = SAMPLING_RATE_22P05KHZ;
  2313. break;
  2314. case 4:
  2315. sample_rate = SAMPLING_RATE_32KHZ;
  2316. break;
  2317. case 5:
  2318. sample_rate = SAMPLING_RATE_44P1KHZ;
  2319. break;
  2320. case 6:
  2321. sample_rate = SAMPLING_RATE_48KHZ;
  2322. break;
  2323. case 7:
  2324. sample_rate = SAMPLING_RATE_88P2KHZ;
  2325. break;
  2326. case 8:
  2327. sample_rate = SAMPLING_RATE_96KHZ;
  2328. break;
  2329. case 9:
  2330. sample_rate = SAMPLING_RATE_176P4KHZ;
  2331. break;
  2332. case 10:
  2333. sample_rate = SAMPLING_RATE_192KHZ;
  2334. break;
  2335. case 11:
  2336. sample_rate = SAMPLING_RATE_352P8KHZ;
  2337. break;
  2338. case 12:
  2339. sample_rate = SAMPLING_RATE_384KHZ;
  2340. break;
  2341. default:
  2342. sample_rate = SAMPLING_RATE_48KHZ;
  2343. break;
  2344. }
  2345. return sample_rate;
  2346. }
  2347. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2348. struct snd_ctl_elem_value *ucontrol)
  2349. {
  2350. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2351. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2352. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2353. return ch_num;
  2354. }
  2355. ucontrol->value.enumerated.item[0] =
  2356. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2357. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2358. cdc_dma_rx_cfg[ch_num].sample_rate);
  2359. return 0;
  2360. }
  2361. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2362. struct snd_ctl_elem_value *ucontrol)
  2363. {
  2364. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2365. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2366. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2367. return ch_num;
  2368. }
  2369. cdc_dma_rx_cfg[ch_num].sample_rate =
  2370. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2371. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2372. __func__, ucontrol->value.enumerated.item[0],
  2373. cdc_dma_rx_cfg[ch_num].sample_rate);
  2374. return 0;
  2375. }
  2376. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2377. struct snd_ctl_elem_value *ucontrol)
  2378. {
  2379. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2380. if (ch_num < 0) {
  2381. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2382. return ch_num;
  2383. }
  2384. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2385. cdc_dma_tx_cfg[ch_num].channels);
  2386. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2387. return 0;
  2388. }
  2389. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2390. struct snd_ctl_elem_value *ucontrol)
  2391. {
  2392. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2393. if (ch_num < 0) {
  2394. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2395. return ch_num;
  2396. }
  2397. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2398. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2399. cdc_dma_tx_cfg[ch_num].channels);
  2400. return 1;
  2401. }
  2402. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2403. struct snd_ctl_elem_value *ucontrol)
  2404. {
  2405. int sample_rate_val;
  2406. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2407. if (ch_num < 0) {
  2408. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2409. return ch_num;
  2410. }
  2411. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2412. case SAMPLING_RATE_384KHZ:
  2413. sample_rate_val = 12;
  2414. break;
  2415. case SAMPLING_RATE_352P8KHZ:
  2416. sample_rate_val = 11;
  2417. break;
  2418. case SAMPLING_RATE_192KHZ:
  2419. sample_rate_val = 10;
  2420. break;
  2421. case SAMPLING_RATE_176P4KHZ:
  2422. sample_rate_val = 9;
  2423. break;
  2424. case SAMPLING_RATE_96KHZ:
  2425. sample_rate_val = 8;
  2426. break;
  2427. case SAMPLING_RATE_88P2KHZ:
  2428. sample_rate_val = 7;
  2429. break;
  2430. case SAMPLING_RATE_48KHZ:
  2431. sample_rate_val = 6;
  2432. break;
  2433. case SAMPLING_RATE_44P1KHZ:
  2434. sample_rate_val = 5;
  2435. break;
  2436. case SAMPLING_RATE_32KHZ:
  2437. sample_rate_val = 4;
  2438. break;
  2439. case SAMPLING_RATE_22P05KHZ:
  2440. sample_rate_val = 3;
  2441. break;
  2442. case SAMPLING_RATE_16KHZ:
  2443. sample_rate_val = 2;
  2444. break;
  2445. case SAMPLING_RATE_11P025KHZ:
  2446. sample_rate_val = 1;
  2447. break;
  2448. case SAMPLING_RATE_8KHZ:
  2449. sample_rate_val = 0;
  2450. break;
  2451. default:
  2452. sample_rate_val = 6;
  2453. break;
  2454. }
  2455. ucontrol->value.integer.value[0] = sample_rate_val;
  2456. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2457. cdc_dma_tx_cfg[ch_num].sample_rate);
  2458. return 0;
  2459. }
  2460. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2461. struct snd_ctl_elem_value *ucontrol)
  2462. {
  2463. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2464. if (ch_num < 0) {
  2465. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2466. return ch_num;
  2467. }
  2468. switch (ucontrol->value.integer.value[0]) {
  2469. case 12:
  2470. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2471. break;
  2472. case 11:
  2473. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2474. break;
  2475. case 10:
  2476. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2477. break;
  2478. case 9:
  2479. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2480. break;
  2481. case 8:
  2482. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2483. break;
  2484. case 7:
  2485. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2486. break;
  2487. case 6:
  2488. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2489. break;
  2490. case 5:
  2491. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2492. break;
  2493. case 4:
  2494. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2495. break;
  2496. case 3:
  2497. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2498. break;
  2499. case 2:
  2500. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2501. break;
  2502. case 1:
  2503. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2504. break;
  2505. case 0:
  2506. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2507. break;
  2508. default:
  2509. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2510. break;
  2511. }
  2512. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2513. __func__, ucontrol->value.integer.value[0],
  2514. cdc_dma_tx_cfg[ch_num].sample_rate);
  2515. return 0;
  2516. }
  2517. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2518. struct snd_ctl_elem_value *ucontrol)
  2519. {
  2520. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2521. if (ch_num < 0) {
  2522. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2523. return ch_num;
  2524. }
  2525. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2526. case SNDRV_PCM_FORMAT_S32_LE:
  2527. ucontrol->value.integer.value[0] = 3;
  2528. break;
  2529. case SNDRV_PCM_FORMAT_S24_3LE:
  2530. ucontrol->value.integer.value[0] = 2;
  2531. break;
  2532. case SNDRV_PCM_FORMAT_S24_LE:
  2533. ucontrol->value.integer.value[0] = 1;
  2534. break;
  2535. case SNDRV_PCM_FORMAT_S16_LE:
  2536. default:
  2537. ucontrol->value.integer.value[0] = 0;
  2538. break;
  2539. }
  2540. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2541. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2542. ucontrol->value.integer.value[0]);
  2543. return 0;
  2544. }
  2545. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2546. struct snd_ctl_elem_value *ucontrol)
  2547. {
  2548. int rc = 0;
  2549. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2550. if (ch_num < 0) {
  2551. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2552. return ch_num;
  2553. }
  2554. switch (ucontrol->value.integer.value[0]) {
  2555. case 3:
  2556. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2557. break;
  2558. case 2:
  2559. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2560. break;
  2561. case 1:
  2562. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2563. break;
  2564. case 0:
  2565. default:
  2566. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2567. break;
  2568. }
  2569. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2570. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2571. ucontrol->value.integer.value[0]);
  2572. return rc;
  2573. }
  2574. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2575. {
  2576. int idx = 0;
  2577. switch (be_id) {
  2578. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2579. idx = RX_CDC_DMA_RX_0;
  2580. break;
  2581. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2582. idx = RX_CDC_DMA_RX_1;
  2583. break;
  2584. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2585. idx = RX_CDC_DMA_RX_2;
  2586. break;
  2587. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2588. idx = RX_CDC_DMA_RX_3;
  2589. break;
  2590. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2591. idx = RX_CDC_DMA_RX_5;
  2592. break;
  2593. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  2594. idx = RX_CDC_DMA_RX_6;
  2595. break;
  2596. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2597. idx = TX_CDC_DMA_TX_0;
  2598. break;
  2599. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2600. idx = TX_CDC_DMA_TX_3;
  2601. break;
  2602. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2603. idx = TX_CDC_DMA_TX_4;
  2604. break;
  2605. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2606. idx = VA_CDC_DMA_TX_0;
  2607. break;
  2608. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2609. idx = VA_CDC_DMA_TX_1;
  2610. break;
  2611. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2612. idx = VA_CDC_DMA_TX_2;
  2613. break;
  2614. default:
  2615. idx = RX_CDC_DMA_RX_0;
  2616. break;
  2617. }
  2618. return idx;
  2619. }
  2620. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2621. struct snd_ctl_elem_value *ucontrol)
  2622. {
  2623. /*
  2624. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2625. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2626. * value.
  2627. */
  2628. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2629. case SAMPLING_RATE_96KHZ:
  2630. ucontrol->value.integer.value[0] = 5;
  2631. break;
  2632. case SAMPLING_RATE_88P2KHZ:
  2633. ucontrol->value.integer.value[0] = 4;
  2634. break;
  2635. case SAMPLING_RATE_48KHZ:
  2636. ucontrol->value.integer.value[0] = 3;
  2637. break;
  2638. case SAMPLING_RATE_44P1KHZ:
  2639. ucontrol->value.integer.value[0] = 2;
  2640. break;
  2641. case SAMPLING_RATE_16KHZ:
  2642. ucontrol->value.integer.value[0] = 1;
  2643. break;
  2644. case SAMPLING_RATE_8KHZ:
  2645. default:
  2646. ucontrol->value.integer.value[0] = 0;
  2647. break;
  2648. }
  2649. pr_debug("%s: sample rate = %d\n", __func__,
  2650. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2651. return 0;
  2652. }
  2653. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2654. struct snd_ctl_elem_value *ucontrol)
  2655. {
  2656. switch (ucontrol->value.integer.value[0]) {
  2657. case 1:
  2658. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2659. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2660. break;
  2661. case 2:
  2662. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2663. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2664. break;
  2665. case 3:
  2666. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2667. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2668. break;
  2669. case 4:
  2670. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2671. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2672. break;
  2673. case 5:
  2674. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2675. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2676. break;
  2677. case 0:
  2678. default:
  2679. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2680. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2681. break;
  2682. }
  2683. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2684. __func__,
  2685. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2686. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2687. ucontrol->value.enumerated.item[0]);
  2688. return 0;
  2689. }
  2690. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2691. struct snd_ctl_elem_value *ucontrol)
  2692. {
  2693. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2694. case SAMPLING_RATE_96KHZ:
  2695. ucontrol->value.integer.value[0] = 5;
  2696. break;
  2697. case SAMPLING_RATE_88P2KHZ:
  2698. ucontrol->value.integer.value[0] = 4;
  2699. break;
  2700. case SAMPLING_RATE_48KHZ:
  2701. ucontrol->value.integer.value[0] = 3;
  2702. break;
  2703. case SAMPLING_RATE_44P1KHZ:
  2704. ucontrol->value.integer.value[0] = 2;
  2705. break;
  2706. case SAMPLING_RATE_16KHZ:
  2707. ucontrol->value.integer.value[0] = 1;
  2708. break;
  2709. case SAMPLING_RATE_8KHZ:
  2710. default:
  2711. ucontrol->value.integer.value[0] = 0;
  2712. break;
  2713. }
  2714. pr_debug("%s: sample rate rx = %d\n", __func__,
  2715. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2716. return 0;
  2717. }
  2718. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2719. struct snd_ctl_elem_value *ucontrol)
  2720. {
  2721. switch (ucontrol->value.integer.value[0]) {
  2722. case 1:
  2723. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2724. break;
  2725. case 2:
  2726. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2727. break;
  2728. case 3:
  2729. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2730. break;
  2731. case 4:
  2732. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2733. break;
  2734. case 5:
  2735. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2736. break;
  2737. case 0:
  2738. default:
  2739. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2740. break;
  2741. }
  2742. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2743. __func__,
  2744. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2745. ucontrol->value.enumerated.item[0]);
  2746. return 0;
  2747. }
  2748. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2749. struct snd_ctl_elem_value *ucontrol)
  2750. {
  2751. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2752. case SAMPLING_RATE_96KHZ:
  2753. ucontrol->value.integer.value[0] = 5;
  2754. break;
  2755. case SAMPLING_RATE_88P2KHZ:
  2756. ucontrol->value.integer.value[0] = 4;
  2757. break;
  2758. case SAMPLING_RATE_48KHZ:
  2759. ucontrol->value.integer.value[0] = 3;
  2760. break;
  2761. case SAMPLING_RATE_44P1KHZ:
  2762. ucontrol->value.integer.value[0] = 2;
  2763. break;
  2764. case SAMPLING_RATE_16KHZ:
  2765. ucontrol->value.integer.value[0] = 1;
  2766. break;
  2767. case SAMPLING_RATE_8KHZ:
  2768. default:
  2769. ucontrol->value.integer.value[0] = 0;
  2770. break;
  2771. }
  2772. pr_debug("%s: sample rate tx = %d\n", __func__,
  2773. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2774. return 0;
  2775. }
  2776. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2777. struct snd_ctl_elem_value *ucontrol)
  2778. {
  2779. switch (ucontrol->value.integer.value[0]) {
  2780. case 1:
  2781. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2782. break;
  2783. case 2:
  2784. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2785. break;
  2786. case 3:
  2787. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2788. break;
  2789. case 4:
  2790. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2791. break;
  2792. case 5:
  2793. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2794. break;
  2795. case 0:
  2796. default:
  2797. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2798. break;
  2799. }
  2800. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2801. __func__,
  2802. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2803. ucontrol->value.enumerated.item[0]);
  2804. return 0;
  2805. }
  2806. static const struct snd_kcontrol_new msm_int_wcd937x_snd_controls[] = {
  2807. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2808. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2809. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2810. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2811. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2812. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2813. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2814. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2815. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2816. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2817. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2818. rx_cdc_dma_rx_0_sample_rate,
  2819. cdc_dma_rx_sample_rate_get,
  2820. cdc_dma_rx_sample_rate_put),
  2821. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2822. rx_cdc_dma_rx_1_sample_rate,
  2823. cdc_dma_rx_sample_rate_get,
  2824. cdc_dma_rx_sample_rate_put),
  2825. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2826. rx_cdc_dma_rx_2_sample_rate,
  2827. cdc_dma_rx_sample_rate_get,
  2828. cdc_dma_rx_sample_rate_put),
  2829. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2830. rx_cdc_dma_rx_3_sample_rate,
  2831. cdc_dma_rx_sample_rate_get,
  2832. cdc_dma_rx_sample_rate_put),
  2833. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2834. rx_cdc_dma_rx_5_sample_rate,
  2835. cdc_dma_rx_sample_rate_get,
  2836. cdc_dma_rx_sample_rate_put),
  2837. };
  2838. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2839. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2840. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2841. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2842. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2843. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2844. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2845. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2846. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2847. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2848. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2849. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Channels", rx_cdc_dma_rx_6_chs,
  2850. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2851. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2852. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2853. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2854. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2855. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2856. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2857. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2858. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2859. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2860. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2861. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2862. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2863. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2864. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2865. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2866. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2867. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2868. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2869. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2870. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2871. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2872. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2873. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2874. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2875. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2876. tx_cdc_dma_tx_0_sample_rate,
  2877. cdc_dma_tx_sample_rate_get,
  2878. cdc_dma_tx_sample_rate_put),
  2879. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2880. tx_cdc_dma_tx_3_sample_rate,
  2881. cdc_dma_tx_sample_rate_get,
  2882. cdc_dma_tx_sample_rate_put),
  2883. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2884. tx_cdc_dma_tx_4_sample_rate,
  2885. cdc_dma_tx_sample_rate_get,
  2886. cdc_dma_tx_sample_rate_put),
  2887. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2888. va_cdc_dma_tx_0_sample_rate,
  2889. cdc_dma_tx_sample_rate_get,
  2890. cdc_dma_tx_sample_rate_put),
  2891. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2892. va_cdc_dma_tx_1_sample_rate,
  2893. cdc_dma_tx_sample_rate_get,
  2894. cdc_dma_tx_sample_rate_put),
  2895. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2896. va_cdc_dma_tx_2_sample_rate,
  2897. cdc_dma_tx_sample_rate_get,
  2898. cdc_dma_tx_sample_rate_put),
  2899. };
  2900. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  2901. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  2902. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2903. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  2904. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2905. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  2906. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2907. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  2908. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2909. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  2910. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2911. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc80_dma_rx_6_format,
  2912. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2913. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2914. rx_cdc80_dma_rx_0_sample_rate,
  2915. cdc_dma_rx_sample_rate_get,
  2916. cdc_dma_rx_sample_rate_put),
  2917. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2918. rx_cdc80_dma_rx_1_sample_rate,
  2919. cdc_dma_rx_sample_rate_get,
  2920. cdc_dma_rx_sample_rate_put),
  2921. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2922. rx_cdc80_dma_rx_2_sample_rate,
  2923. cdc_dma_rx_sample_rate_get,
  2924. cdc_dma_rx_sample_rate_put),
  2925. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2926. rx_cdc80_dma_rx_3_sample_rate,
  2927. cdc_dma_rx_sample_rate_get,
  2928. cdc_dma_rx_sample_rate_put),
  2929. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2930. rx_cdc80_dma_rx_5_sample_rate,
  2931. cdc_dma_rx_sample_rate_get,
  2932. cdc_dma_rx_sample_rate_put),
  2933. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate",
  2934. rx_cdc80_dma_rx_6_sample_rate,
  2935. cdc_dma_rx_sample_rate_get,
  2936. cdc_dma_rx_sample_rate_put),
  2937. };
  2938. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  2939. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  2940. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2941. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  2942. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2943. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  2944. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2945. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  2946. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2947. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  2948. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2949. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc85_dma_rx_6_format,
  2950. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2951. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2952. rx_cdc85_dma_rx_0_sample_rate,
  2953. cdc_dma_rx_sample_rate_get,
  2954. cdc_dma_rx_sample_rate_put),
  2955. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2956. rx_cdc85_dma_rx_1_sample_rate,
  2957. cdc_dma_rx_sample_rate_get,
  2958. cdc_dma_rx_sample_rate_put),
  2959. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2960. rx_cdc85_dma_rx_2_sample_rate,
  2961. cdc_dma_rx_sample_rate_get,
  2962. cdc_dma_rx_sample_rate_put),
  2963. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2964. rx_cdc85_dma_rx_3_sample_rate,
  2965. cdc_dma_rx_sample_rate_get,
  2966. cdc_dma_rx_sample_rate_put),
  2967. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2968. rx_cdc85_dma_rx_5_sample_rate,
  2969. cdc_dma_rx_sample_rate_get,
  2970. cdc_dma_rx_sample_rate_put),
  2971. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate",
  2972. rx_cdc85_dma_rx_6_sample_rate,
  2973. cdc_dma_rx_sample_rate_get,
  2974. cdc_dma_rx_sample_rate_put),
  2975. };
  2976. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  2977. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2978. usb_audio_rx_sample_rate_get,
  2979. usb_audio_rx_sample_rate_put),
  2980. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2981. usb_audio_tx_sample_rate_get,
  2982. usb_audio_tx_sample_rate_put),
  2983. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2984. tdm_rx_sample_rate_get,
  2985. tdm_rx_sample_rate_put),
  2986. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2987. tdm_rx_sample_rate_get,
  2988. tdm_rx_sample_rate_put),
  2989. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2990. tdm_rx_sample_rate_get,
  2991. tdm_rx_sample_rate_put),
  2992. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2993. tdm_rx_sample_rate_get,
  2994. tdm_rx_sample_rate_put),
  2995. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2996. tdm_tx_sample_rate_get,
  2997. tdm_tx_sample_rate_put),
  2998. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2999. tdm_tx_sample_rate_get,
  3000. tdm_tx_sample_rate_put),
  3001. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3002. tdm_tx_sample_rate_get,
  3003. tdm_tx_sample_rate_put),
  3004. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3005. tdm_tx_sample_rate_get,
  3006. tdm_tx_sample_rate_put),
  3007. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3008. aux_pcm_rx_sample_rate_get,
  3009. aux_pcm_rx_sample_rate_put),
  3010. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3011. aux_pcm_rx_sample_rate_get,
  3012. aux_pcm_rx_sample_rate_put),
  3013. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3014. aux_pcm_rx_sample_rate_get,
  3015. aux_pcm_rx_sample_rate_put),
  3016. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3017. aux_pcm_rx_sample_rate_get,
  3018. aux_pcm_rx_sample_rate_put),
  3019. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3020. aux_pcm_tx_sample_rate_get,
  3021. aux_pcm_tx_sample_rate_put),
  3022. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3023. aux_pcm_tx_sample_rate_get,
  3024. aux_pcm_tx_sample_rate_put),
  3025. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3026. aux_pcm_tx_sample_rate_get,
  3027. aux_pcm_tx_sample_rate_put),
  3028. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3029. aux_pcm_tx_sample_rate_get,
  3030. aux_pcm_tx_sample_rate_put),
  3031. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3032. mi2s_rx_sample_rate_get,
  3033. mi2s_rx_sample_rate_put),
  3034. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3035. mi2s_rx_sample_rate_get,
  3036. mi2s_rx_sample_rate_put),
  3037. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3038. mi2s_rx_sample_rate_get,
  3039. mi2s_rx_sample_rate_put),
  3040. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3041. mi2s_rx_sample_rate_get,
  3042. mi2s_rx_sample_rate_put),
  3043. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3044. mi2s_tx_sample_rate_get,
  3045. mi2s_tx_sample_rate_put),
  3046. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3047. mi2s_tx_sample_rate_get,
  3048. mi2s_tx_sample_rate_put),
  3049. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3050. mi2s_tx_sample_rate_get,
  3051. mi2s_tx_sample_rate_put),
  3052. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3053. mi2s_tx_sample_rate_get,
  3054. mi2s_tx_sample_rate_put),
  3055. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3056. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3057. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3058. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3059. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3060. tdm_rx_format_get,
  3061. tdm_rx_format_put),
  3062. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3063. tdm_rx_format_get,
  3064. tdm_rx_format_put),
  3065. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3066. tdm_rx_format_get,
  3067. tdm_rx_format_put),
  3068. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3069. tdm_rx_format_get,
  3070. tdm_rx_format_put),
  3071. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3072. tdm_tx_format_get,
  3073. tdm_tx_format_put),
  3074. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3075. tdm_tx_format_get,
  3076. tdm_tx_format_put),
  3077. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3078. tdm_tx_format_get,
  3079. tdm_tx_format_put),
  3080. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3081. tdm_tx_format_get,
  3082. tdm_tx_format_put),
  3083. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3084. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3085. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3086. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3087. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3088. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3089. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3090. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3091. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3092. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3093. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3094. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3095. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3096. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3097. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3098. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3099. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3100. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3101. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3102. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3103. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3104. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3105. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3106. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3107. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3108. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3109. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3110. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3111. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3112. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3113. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3114. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3115. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3116. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3117. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3118. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3119. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3120. proxy_rx_ch_get, proxy_rx_ch_put),
  3121. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3122. tdm_rx_ch_get,
  3123. tdm_rx_ch_put),
  3124. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3125. tdm_rx_ch_get,
  3126. tdm_rx_ch_put),
  3127. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3128. tdm_rx_ch_get,
  3129. tdm_rx_ch_put),
  3130. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3131. tdm_rx_ch_get,
  3132. tdm_rx_ch_put),
  3133. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3134. tdm_tx_ch_get,
  3135. tdm_tx_ch_put),
  3136. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3137. tdm_tx_ch_get,
  3138. tdm_tx_ch_put),
  3139. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3140. tdm_tx_ch_get,
  3141. tdm_tx_ch_put),
  3142. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3143. tdm_tx_ch_get,
  3144. tdm_tx_ch_put),
  3145. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3146. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3147. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3148. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3149. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3150. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3151. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3152. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3153. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3154. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3155. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3156. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3157. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3158. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3159. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3160. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3161. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3162. msm_bt_sample_rate_get,
  3163. msm_bt_sample_rate_put),
  3164. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3165. msm_bt_sample_rate_rx_get,
  3166. msm_bt_sample_rate_rx_put),
  3167. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3168. msm_bt_sample_rate_tx_get,
  3169. msm_bt_sample_rate_tx_put),
  3170. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3171. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3172. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3173. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3174. SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
  3175. TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
  3176. };
  3177. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3178. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3179. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3180. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3181. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3182. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3183. aux_pcm_rx_sample_rate_get,
  3184. aux_pcm_rx_sample_rate_put),
  3185. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3186. aux_pcm_tx_sample_rate_get,
  3187. aux_pcm_tx_sample_rate_put),
  3188. };
  3189. static int holi_send_island_va_config(int32_t be_id)
  3190. {
  3191. int rc = 0;
  3192. int port_id = 0xFFFF;
  3193. port_id = msm_get_port_id(be_id);
  3194. if (port_id < 0) {
  3195. pr_err("%s: Invalid island interface, be_id: %d\n",
  3196. __func__, be_id);
  3197. rc = -EINVAL;
  3198. } else {
  3199. /*
  3200. * send island mode config
  3201. * This should be the first configuration
  3202. */
  3203. rc = afe_send_port_island_mode(port_id);
  3204. if (rc)
  3205. pr_err("%s: afe send island mode failed %d\n",
  3206. __func__, rc);
  3207. }
  3208. return rc;
  3209. }
  3210. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3211. struct snd_pcm_hw_params *params)
  3212. {
  3213. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3214. struct snd_interval *rate = hw_param_interval(params,
  3215. SNDRV_PCM_HW_PARAM_RATE);
  3216. struct snd_interval *channels = hw_param_interval(params,
  3217. SNDRV_PCM_HW_PARAM_CHANNELS);
  3218. int idx = 0, rc = 0;
  3219. pr_debug("%s: dai_id= %d, format = %d, rate = %d\n",
  3220. __func__, dai_link->id, params_format(params),
  3221. params_rate(params));
  3222. switch (dai_link->id) {
  3223. case MSM_BACKEND_DAI_USB_RX:
  3224. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3225. usb_rx_cfg.bit_format);
  3226. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3227. channels->min = channels->max = usb_rx_cfg.channels;
  3228. break;
  3229. case MSM_BACKEND_DAI_USB_TX:
  3230. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3231. usb_tx_cfg.bit_format);
  3232. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3233. channels->min = channels->max = usb_tx_cfg.channels;
  3234. break;
  3235. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3236. channels->min = channels->max = proxy_rx_cfg.channels;
  3237. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3238. break;
  3239. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3240. channels->min = channels->max =
  3241. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3242. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3243. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3244. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3245. break;
  3246. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3247. channels->min = channels->max =
  3248. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3249. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3250. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3251. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3252. break;
  3253. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3254. channels->min = channels->max =
  3255. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3256. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3257. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3258. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3259. break;
  3260. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3261. channels->min = channels->max =
  3262. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3263. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3264. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3265. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3266. break;
  3267. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3268. channels->min = channels->max =
  3269. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3270. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3271. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3272. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3273. break;
  3274. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3275. channels->min = channels->max =
  3276. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3277. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3278. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3279. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3280. break;
  3281. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3282. channels->min = channels->max =
  3283. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3284. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3285. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3286. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3287. break;
  3288. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3289. channels->min = channels->max =
  3290. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3291. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3292. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3293. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3294. break;
  3295. case MSM_BACKEND_DAI_AUXPCM_RX:
  3296. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3297. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3298. rate->min = rate->max =
  3299. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3300. channels->min = channels->max =
  3301. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3302. break;
  3303. case MSM_BACKEND_DAI_AUXPCM_TX:
  3304. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3305. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3306. rate->min = rate->max =
  3307. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3308. channels->min = channels->max =
  3309. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3310. break;
  3311. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3312. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3313. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3314. rate->min = rate->max =
  3315. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3316. channels->min = channels->max =
  3317. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3318. break;
  3319. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3320. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3321. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3322. rate->min = rate->max =
  3323. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3324. channels->min = channels->max =
  3325. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3326. break;
  3327. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3328. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3329. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3330. rate->min = rate->max =
  3331. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3332. channels->min = channels->max =
  3333. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3334. break;
  3335. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3336. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3337. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3338. rate->min = rate->max =
  3339. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3340. channels->min = channels->max =
  3341. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3342. break;
  3343. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3344. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3345. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3346. rate->min = rate->max =
  3347. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3348. channels->min = channels->max =
  3349. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3350. break;
  3351. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3352. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3353. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3354. rate->min = rate->max =
  3355. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3356. channels->min = channels->max =
  3357. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3358. break;
  3359. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3360. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3361. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3362. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3363. channels->min = channels->max =
  3364. mi2s_rx_cfg[PRIM_MI2S].channels;
  3365. break;
  3366. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3367. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3368. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3369. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3370. channels->min = channels->max =
  3371. mi2s_tx_cfg[PRIM_MI2S].channels;
  3372. break;
  3373. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3374. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3375. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3376. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3377. channels->min = channels->max =
  3378. mi2s_rx_cfg[SEC_MI2S].channels;
  3379. break;
  3380. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3381. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3382. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3383. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3384. channels->min = channels->max =
  3385. mi2s_tx_cfg[SEC_MI2S].channels;
  3386. break;
  3387. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3388. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3389. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3390. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3391. channels->min = channels->max =
  3392. mi2s_rx_cfg[TERT_MI2S].channels;
  3393. break;
  3394. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3395. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3396. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3397. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3398. channels->min = channels->max =
  3399. mi2s_tx_cfg[TERT_MI2S].channels;
  3400. break;
  3401. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3402. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3403. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3404. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3405. channels->min = channels->max =
  3406. mi2s_rx_cfg[QUAT_MI2S].channels;
  3407. break;
  3408. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3409. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3410. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3411. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3412. channels->min = channels->max =
  3413. mi2s_tx_cfg[QUAT_MI2S].channels;
  3414. break;
  3415. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3416. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3417. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3418. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3419. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  3420. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3421. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3422. cdc_dma_rx_cfg[idx].bit_format);
  3423. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3424. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3425. break;
  3426. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3427. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3428. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3429. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3430. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3431. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3432. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3433. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3434. cdc_dma_tx_cfg[idx].bit_format);
  3435. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3436. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3437. break;
  3438. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3439. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3440. slim_rx_cfg[SLIM_RX_7].bit_format);
  3441. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3442. channels->min = channels->max =
  3443. slim_rx_cfg[SLIM_RX_7].channels;
  3444. break;
  3445. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3446. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3447. slim_tx_cfg[SLIM_TX_7].bit_format);
  3448. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3449. channels->min = channels->max =
  3450. slim_tx_cfg[SLIM_TX_7].channels;
  3451. break;
  3452. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3453. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3454. channels->min = channels->max =
  3455. slim_tx_cfg[SLIM_TX_8].channels;
  3456. break;
  3457. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3458. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3459. afe_loopback_tx_cfg[idx].bit_format);
  3460. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3461. channels->min = channels->max =
  3462. afe_loopback_tx_cfg[idx].channels;
  3463. break;
  3464. default:
  3465. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3466. break;
  3467. }
  3468. return rc;
  3469. }
  3470. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component,
  3471. bool active)
  3472. {
  3473. struct snd_soc_card *card = component->card;
  3474. struct msm_asoc_mach_data *pdata =
  3475. snd_soc_card_get_drvdata(card);
  3476. if (!pdata->fsa_handle)
  3477. return false;
  3478. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3479. }
  3480. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3481. {
  3482. int value = 0;
  3483. bool ret = false;
  3484. struct snd_soc_card *card;
  3485. struct msm_asoc_mach_data *pdata;
  3486. if (!component) {
  3487. pr_err("%s component is NULL\n", __func__);
  3488. return false;
  3489. }
  3490. card = component->card;
  3491. pdata = snd_soc_card_get_drvdata(card);
  3492. if (!pdata)
  3493. return false;
  3494. if (wcd_mbhc_cfg.enable_usbc_analog)
  3495. return msm_usbc_swap_gnd_mic(component, active);
  3496. /* if usbc is not defined, swap using us_euro_gpio_p */
  3497. if (pdata->us_euro_gpio_p) {
  3498. value = msm_cdc_pinctrl_get_state(
  3499. pdata->us_euro_gpio_p);
  3500. if (value)
  3501. msm_cdc_pinctrl_select_sleep_state(
  3502. pdata->us_euro_gpio_p);
  3503. else
  3504. msm_cdc_pinctrl_select_active_state(
  3505. pdata->us_euro_gpio_p);
  3506. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3507. __func__, value, !value);
  3508. ret = true;
  3509. }
  3510. return ret;
  3511. }
  3512. static int holi_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3513. struct snd_pcm_hw_params *params)
  3514. {
  3515. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3516. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3517. int ret = 0;
  3518. int slot_width = TDM_SLOT_WIDTH_BITS;
  3519. int channels, slots = TDM_MAX_SLOTS;
  3520. unsigned int slot_mask, rate, clk_freq;
  3521. unsigned int *slot_offset;
  3522. struct tdm_dev_config *config;
  3523. unsigned int path_dir = 0, interface = 0, channel_interface = 0;
  3524. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3525. if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
  3526. pr_err("%s: dai id 0x%x not supported\n",
  3527. __func__, cpu_dai->id);
  3528. return -EINVAL;
  3529. }
  3530. /* RX or TX */
  3531. path_dir = cpu_dai->id % MAX_PATH;
  3532. /* PRI, SEC, TERT, QUAT ... */
  3533. interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
  3534. / (MAX_PATH * TDM_PORT_MAX);
  3535. /* 0, 1, 2, .. 7 */
  3536. channel_interface =
  3537. ((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
  3538. % TDM_PORT_MAX;
  3539. pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
  3540. __func__, path_dir, interface, channel_interface);
  3541. config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
  3542. (path_dir * TDM_PORT_MAX) + channel_interface;
  3543. slot_offset = config->tdm_slot_offset;
  3544. if (path_dir)
  3545. channels = tdm_tx_cfg[interface][channel_interface].channels;
  3546. else
  3547. channels = tdm_rx_cfg[interface][channel_interface].channels;
  3548. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3549. /*2 slot config - bits 0 and 1 set for the first two slots */
  3550. slot_mask = 0x0000FFFF >> (16 - slots);
  3551. pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
  3552. __func__, slot_width, slots, slot_mask);
  3553. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3554. slots, slot_width);
  3555. if (ret < 0) {
  3556. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3557. __func__, ret);
  3558. goto end;
  3559. }
  3560. pr_debug("%s: tdm rx channels: %d\n", __func__, channels);
  3561. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3562. 0, NULL, channels, slot_offset);
  3563. if (ret < 0) {
  3564. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3565. __func__, ret);
  3566. goto end;
  3567. }
  3568. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3569. /*2 slot config - bits 0 and 1 set for the first two slots */
  3570. slot_mask = 0x0000FFFF >> (16 - slots);
  3571. pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
  3572. __func__, slot_width, slots, slot_mask);
  3573. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3574. slots, slot_width);
  3575. if (ret < 0) {
  3576. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3577. __func__, ret);
  3578. goto end;
  3579. }
  3580. pr_debug("%s: tdm tx channels: %d\n", __func__, channels);
  3581. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3582. channels, slot_offset, 0, NULL);
  3583. if (ret < 0) {
  3584. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3585. __func__, ret);
  3586. goto end;
  3587. }
  3588. } else {
  3589. ret = -EINVAL;
  3590. pr_err("%s: invalid use case, err:%d\n",
  3591. __func__, ret);
  3592. goto end;
  3593. }
  3594. rate = params_rate(params);
  3595. clk_freq = rate * slot_width * slots;
  3596. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3597. if (ret < 0)
  3598. pr_err("%s: failed to set tdm clk, err:%d\n",
  3599. __func__, ret);
  3600. end:
  3601. return ret;
  3602. }
  3603. static int msm_get_tdm_mode(u32 port_id)
  3604. {
  3605. int tdm_mode;
  3606. switch (port_id) {
  3607. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3608. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3609. tdm_mode = TDM_PRI;
  3610. break;
  3611. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3612. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3613. tdm_mode = TDM_SEC;
  3614. break;
  3615. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3616. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3617. tdm_mode = TDM_TERT;
  3618. break;
  3619. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3620. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3621. tdm_mode = TDM_QUAT;
  3622. break;
  3623. default:
  3624. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3625. tdm_mode = -EINVAL;
  3626. }
  3627. return tdm_mode;
  3628. }
  3629. static int holi_tdm_snd_startup(struct snd_pcm_substream *substream)
  3630. {
  3631. int ret = 0;
  3632. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3633. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3634. struct snd_soc_card *card = rtd->card;
  3635. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3636. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3637. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3638. ret = -EINVAL;
  3639. pr_err("%s: Invalid TDM interface %d\n",
  3640. __func__, ret);
  3641. return ret;
  3642. }
  3643. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3644. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3645. == 0) {
  3646. ret = msm_cdc_pinctrl_select_active_state(
  3647. pdata->mi2s_gpio_p[tdm_mode]);
  3648. if (ret) {
  3649. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3650. __func__, ret);
  3651. goto done;
  3652. }
  3653. }
  3654. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3655. }
  3656. done:
  3657. return ret;
  3658. }
  3659. static void holi_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3660. {
  3661. int ret = 0;
  3662. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3663. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3664. struct snd_soc_card *card = rtd->card;
  3665. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3666. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3667. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3668. ret = -EINVAL;
  3669. pr_err("%s: Invalid TDM interface %d\n",
  3670. __func__, ret);
  3671. return;
  3672. }
  3673. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3674. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3675. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3676. == 0) {
  3677. ret = msm_cdc_pinctrl_select_sleep_state(
  3678. pdata->mi2s_gpio_p[tdm_mode]);
  3679. if (ret)
  3680. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3681. __func__, ret);
  3682. }
  3683. }
  3684. }
  3685. static int holi_aux_snd_startup(struct snd_pcm_substream *substream)
  3686. {
  3687. int ret = 0;
  3688. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3689. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3690. struct snd_soc_card *card = rtd->card;
  3691. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3692. u32 aux_mode = cpu_dai->id - 1;
  3693. if (aux_mode >= AUX_PCM_MAX) {
  3694. ret = -EINVAL;
  3695. pr_err("%s: Invalid AUX interface %d\n",
  3696. __func__, ret);
  3697. return ret;
  3698. }
  3699. if (pdata->mi2s_gpio_p[aux_mode]) {
  3700. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3701. == 0) {
  3702. ret = msm_cdc_pinctrl_select_active_state(
  3703. pdata->mi2s_gpio_p[aux_mode]);
  3704. if (ret) {
  3705. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3706. __func__, ret);
  3707. goto done;
  3708. }
  3709. }
  3710. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3711. }
  3712. done:
  3713. return ret;
  3714. }
  3715. static void holi_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3716. {
  3717. int ret = 0;
  3718. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3719. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3720. struct snd_soc_card *card = rtd->card;
  3721. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3722. u32 aux_mode = cpu_dai->id - 1;
  3723. if (aux_mode >= AUX_PCM_MAX) {
  3724. pr_err("%s: Invalid AUX interface %d\n",
  3725. __func__, ret);
  3726. return;
  3727. }
  3728. if (pdata->mi2s_gpio_p[aux_mode]) {
  3729. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3730. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3731. == 0) {
  3732. ret = msm_cdc_pinctrl_select_sleep_state(
  3733. pdata->mi2s_gpio_p[aux_mode]);
  3734. if (ret)
  3735. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  3736. __func__, ret);
  3737. }
  3738. }
  3739. }
  3740. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  3741. {
  3742. int ret = 0;
  3743. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3744. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3745. switch (dai_link->id) {
  3746. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3747. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3748. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3749. ret = holi_send_island_va_config(dai_link->id);
  3750. if (ret)
  3751. pr_err("%s: send island va cfg failed, err: %d\n",
  3752. __func__, ret);
  3753. break;
  3754. }
  3755. return ret;
  3756. }
  3757. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3758. struct snd_pcm_hw_params *params)
  3759. {
  3760. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3761. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3762. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3763. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3764. int ret = 0;
  3765. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3766. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3767. u32 user_set_tx_ch = 0;
  3768. u32 user_set_rx_ch = 0;
  3769. u32 ch_id;
  3770. ret = snd_soc_dai_get_channel_map(codec_dai,
  3771. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3772. &rx_ch_cdc_dma);
  3773. if (ret < 0) {
  3774. pr_err("%s: failed to get codec chan map, err:%d\n",
  3775. __func__, ret);
  3776. goto err;
  3777. }
  3778. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3779. switch (dai_link->id) {
  3780. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3781. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3782. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3783. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3784. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3785. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3786. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  3787. {
  3788. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3789. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3790. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3791. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3792. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3793. user_set_rx_ch, &rx_ch_cdc_dma);
  3794. if (ret < 0) {
  3795. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3796. __func__, ret);
  3797. goto err;
  3798. }
  3799. }
  3800. break;
  3801. }
  3802. } else {
  3803. switch (dai_link->id) {
  3804. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3805. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3806. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3807. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3808. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3809. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3810. {
  3811. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3812. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3813. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3814. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3815. }
  3816. break;
  3817. }
  3818. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3819. &tx_ch_cdc_dma, 0, 0);
  3820. if (ret < 0) {
  3821. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3822. __func__, ret);
  3823. goto err;
  3824. }
  3825. }
  3826. err:
  3827. return ret;
  3828. }
  3829. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3830. {
  3831. pr_debug("%s: TODO: add new QOS implementation\n", __func__);
  3832. return 0;
  3833. }
  3834. void mi2s_disable_audio_vote(struct snd_pcm_substream *substream)
  3835. {
  3836. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3837. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3838. int index = cpu_dai->id;
  3839. struct snd_soc_card *card = rtd->card;
  3840. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3841. int sample_rate = 0;
  3842. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3843. sample_rate = mi2s_rx_cfg[index].sample_rate;
  3844. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3845. sample_rate = mi2s_tx_cfg[index].sample_rate;
  3846. } else {
  3847. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  3848. return;
  3849. }
  3850. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  3851. if (pdata->lpass_audio_hw_vote != NULL) {
  3852. if (--pdata->core_audio_vote_count == 0) {
  3853. clk_disable_unprepare(
  3854. pdata->lpass_audio_hw_vote);
  3855. } else if (pdata->core_audio_vote_count < 0) {
  3856. pr_err("%s: audio vote mismatch\n", __func__);
  3857. pdata->core_audio_vote_count = 0;
  3858. }
  3859. } else {
  3860. pr_err("%s: Invalid lpass audio hw node\n", __func__);
  3861. }
  3862. }
  3863. }
  3864. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3865. {
  3866. int ret = 0;
  3867. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3868. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3869. int index = cpu_dai->id;
  3870. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3871. struct snd_soc_card *card = rtd->card;
  3872. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3873. int sample_rate = 0;
  3874. dev_dbg(rtd->card->dev,
  3875. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3876. __func__, substream->name, substream->stream,
  3877. cpu_dai->name, cpu_dai->id);
  3878. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3879. ret = -EINVAL;
  3880. dev_err(rtd->card->dev,
  3881. "%s: CPU DAI id (%d) out of range\n",
  3882. __func__, cpu_dai->id);
  3883. goto err;
  3884. }
  3885. /*
  3886. * Mutex protection in case the same MI2S
  3887. * interface using for both TX and RX so
  3888. * that the same clock won't be enable twice.
  3889. */
  3890. mutex_lock(&mi2s_intf_conf[index].lock);
  3891. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3892. sample_rate = mi2s_rx_cfg[index].sample_rate;
  3893. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3894. sample_rate = mi2s_tx_cfg[index].sample_rate;
  3895. } else {
  3896. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  3897. ret = -EINVAL;
  3898. goto vote_err;
  3899. }
  3900. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  3901. if (pdata->lpass_audio_hw_vote == NULL) {
  3902. dev_err(rtd->card->dev, "%s: Invalid lpass audio hw node\n",
  3903. __func__);
  3904. ret = -EINVAL;
  3905. goto vote_err;
  3906. }
  3907. if (pdata->core_audio_vote_count == 0) {
  3908. ret = clk_prepare_enable(pdata->lpass_audio_hw_vote);
  3909. if (ret < 0) {
  3910. dev_err(rtd->card->dev, "%s: audio vote error\n",
  3911. __func__);
  3912. goto vote_err;
  3913. }
  3914. }
  3915. pdata->core_audio_vote_count++;
  3916. }
  3917. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3918. /* Check if msm needs to provide the clock to the interface */
  3919. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3920. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3921. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3922. }
  3923. ret = msm_mi2s_set_sclk(substream, true);
  3924. if (ret < 0) {
  3925. dev_err(rtd->card->dev,
  3926. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3927. __func__, ret);
  3928. goto clean_up;
  3929. }
  3930. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3931. if (ret < 0) {
  3932. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  3933. __func__, index, ret);
  3934. goto clk_off;
  3935. }
  3936. if (pdata->mi2s_gpio_p[index]) {
  3937. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  3938. == 0) {
  3939. ret = msm_cdc_pinctrl_select_active_state(
  3940. pdata->mi2s_gpio_p[index]);
  3941. if (ret) {
  3942. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  3943. __func__, ret);
  3944. goto clk_off;
  3945. }
  3946. }
  3947. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  3948. }
  3949. }
  3950. clk_off:
  3951. if (ret < 0)
  3952. msm_mi2s_set_sclk(substream, false);
  3953. clean_up:
  3954. if (ret < 0) {
  3955. mi2s_intf_conf[index].ref_cnt--;
  3956. mi2s_disable_audio_vote(substream);
  3957. }
  3958. vote_err:
  3959. mutex_unlock(&mi2s_intf_conf[index].lock);
  3960. err:
  3961. return ret;
  3962. }
  3963. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  3964. {
  3965. int ret = 0;
  3966. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3967. int index = rtd->cpu_dai->id;
  3968. struct snd_soc_card *card = rtd->card;
  3969. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3970. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  3971. substream->name, substream->stream);
  3972. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3973. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  3974. return;
  3975. }
  3976. mutex_lock(&mi2s_intf_conf[index].lock);
  3977. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  3978. if (pdata->mi2s_gpio_p[index]) {
  3979. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  3980. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  3981. == 0) {
  3982. ret = msm_cdc_pinctrl_select_sleep_state(
  3983. pdata->mi2s_gpio_p[index]);
  3984. if (ret)
  3985. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  3986. __func__, ret);
  3987. }
  3988. }
  3989. ret = msm_mi2s_set_sclk(substream, false);
  3990. if (ret < 0)
  3991. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  3992. __func__, index, ret);
  3993. }
  3994. mi2s_disable_audio_vote(substream);
  3995. mutex_unlock(&mi2s_intf_conf[index].lock);
  3996. }
  3997. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  3998. struct snd_pcm_hw_params *params)
  3999. {
  4000. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4001. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4002. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4003. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4004. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4005. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4006. int ret = 0;
  4007. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4008. codec_dai->name, codec_dai->id);
  4009. ret = snd_soc_dai_get_channel_map(codec_dai,
  4010. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4011. if (ret) {
  4012. dev_err(rtd->dev,
  4013. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4014. __func__, ret);
  4015. goto err;
  4016. }
  4017. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4018. __func__, tx_ch_cnt, dai_link->id);
  4019. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4020. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4021. if (ret)
  4022. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4023. __func__, ret);
  4024. err:
  4025. return ret;
  4026. }
  4027. static struct snd_soc_ops holi_aux_be_ops = {
  4028. .startup = holi_aux_snd_startup,
  4029. .shutdown = holi_aux_snd_shutdown
  4030. };
  4031. static struct snd_soc_ops holi_tdm_be_ops = {
  4032. .hw_params = holi_tdm_snd_hw_params,
  4033. .startup = holi_tdm_snd_startup,
  4034. .shutdown = holi_tdm_snd_shutdown
  4035. };
  4036. static struct snd_soc_ops msm_mi2s_be_ops = {
  4037. .startup = msm_mi2s_snd_startup,
  4038. .shutdown = msm_mi2s_snd_shutdown,
  4039. };
  4040. static struct snd_soc_ops msm_fe_qos_ops = {
  4041. .prepare = msm_fe_qos_prepare,
  4042. };
  4043. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4044. .startup = msm_snd_cdc_dma_startup,
  4045. .hw_params = msm_snd_cdc_dma_hw_params,
  4046. };
  4047. static struct snd_soc_ops msm_wcn_ops_lito = {
  4048. .hw_params = msm_wcn_hw_params_lito,
  4049. };
  4050. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4051. struct snd_kcontrol *kcontrol, int event)
  4052. {
  4053. struct msm_asoc_mach_data *pdata = NULL;
  4054. struct snd_soc_component *component =
  4055. snd_soc_dapm_to_component(w->dapm);
  4056. int ret = 0;
  4057. u32 dmic_idx;
  4058. int *dmic_gpio_cnt;
  4059. struct device_node *dmic_gpio;
  4060. char *wname;
  4061. wname = strpbrk(w->name, "012345");
  4062. if (!wname) {
  4063. dev_err(component->dev, "%s: widget not found\n", __func__);
  4064. return -EINVAL;
  4065. }
  4066. ret = kstrtouint(wname, 10, &dmic_idx);
  4067. if (ret < 0) {
  4068. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4069. __func__);
  4070. return -EINVAL;
  4071. }
  4072. pdata = snd_soc_card_get_drvdata(component->card);
  4073. switch (dmic_idx) {
  4074. case 0:
  4075. case 1:
  4076. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4077. dmic_gpio = pdata->dmic01_gpio_p;
  4078. break;
  4079. case 2:
  4080. case 3:
  4081. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4082. dmic_gpio = pdata->dmic23_gpio_p;
  4083. break;
  4084. case 4:
  4085. case 5:
  4086. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4087. dmic_gpio = pdata->dmic45_gpio_p;
  4088. break;
  4089. default:
  4090. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4091. __func__);
  4092. return -EINVAL;
  4093. }
  4094. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4095. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4096. switch (event) {
  4097. case SND_SOC_DAPM_PRE_PMU:
  4098. (*dmic_gpio_cnt)++;
  4099. if (*dmic_gpio_cnt == 1) {
  4100. ret = msm_cdc_pinctrl_select_active_state(
  4101. dmic_gpio);
  4102. if (ret < 0) {
  4103. pr_err("%s: gpio set cannot be activated %sd",
  4104. __func__, "dmic_gpio");
  4105. return ret;
  4106. }
  4107. }
  4108. break;
  4109. case SND_SOC_DAPM_POST_PMD:
  4110. (*dmic_gpio_cnt)--;
  4111. if (*dmic_gpio_cnt == 0) {
  4112. ret = msm_cdc_pinctrl_select_sleep_state(
  4113. dmic_gpio);
  4114. if (ret < 0) {
  4115. pr_err("%s: gpio set cannot be de-activated %sd",
  4116. __func__, "dmic_gpio");
  4117. return ret;
  4118. }
  4119. }
  4120. break;
  4121. default:
  4122. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4123. return -EINVAL;
  4124. }
  4125. return 0;
  4126. }
  4127. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4128. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4129. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4130. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4131. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4132. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4133. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4134. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4135. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4136. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4137. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4138. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4139. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4140. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4141. };
  4142. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4143. {
  4144. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4145. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4146. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4147. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4148. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4149. }
  4150. static struct snd_info_entry *msm_snd_info_create_subdir(struct module *mod,
  4151. const char *name,
  4152. struct snd_info_entry *parent)
  4153. {
  4154. struct snd_info_entry *entry;
  4155. entry = snd_info_create_module_entry(mod, name, parent);
  4156. if (!entry)
  4157. return NULL;
  4158. entry->mode = S_IFDIR | 0555;
  4159. if (snd_info_register(entry) < 0) {
  4160. snd_info_free_entry(entry);
  4161. return NULL;
  4162. }
  4163. return entry;
  4164. }
  4165. static void *def_wcd_mbhc_cal(void)
  4166. {
  4167. void *wcd_mbhc_cal;
  4168. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4169. u16 *btn_high;
  4170. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4171. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4172. if (!wcd_mbhc_cal)
  4173. return NULL;
  4174. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4175. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4176. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4177. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4178. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4179. btn_high[0] = 75;
  4180. btn_high[1] = 150;
  4181. btn_high[2] = 237;
  4182. btn_high[3] = 500;
  4183. btn_high[4] = 500;
  4184. btn_high[5] = 500;
  4185. btn_high[6] = 500;
  4186. btn_high[7] = 500;
  4187. return wcd_mbhc_cal;
  4188. }
  4189. /* Digital audio interface glue - connects codec <---> CPU */
  4190. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4191. /* FrontEnd DAI Links */
  4192. {/* hw:x,0 */
  4193. .name = MSM_DAILINK_NAME(Media1),
  4194. .stream_name = "MultiMedia1",
  4195. .dynamic = 1,
  4196. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4197. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4198. #endif /* CONFIG_AUDIO_QGKI */
  4199. .dpcm_playback = 1,
  4200. .dpcm_capture = 1,
  4201. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4202. SND_SOC_DPCM_TRIGGER_POST},
  4203. .ignore_suspend = 1,
  4204. /* this dainlink has playback support */
  4205. .ignore_pmdown_time = 1,
  4206. .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
  4207. SND_SOC_DAILINK_REG(multimedia1),
  4208. },
  4209. {/* hw:x,1 */
  4210. .name = MSM_DAILINK_NAME(Media2),
  4211. .stream_name = "MultiMedia2",
  4212. .dynamic = 1,
  4213. .dpcm_playback = 1,
  4214. .dpcm_capture = 1,
  4215. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4216. SND_SOC_DPCM_TRIGGER_POST},
  4217. .ignore_suspend = 1,
  4218. /* this dainlink has playback support */
  4219. .ignore_pmdown_time = 1,
  4220. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4221. SND_SOC_DAILINK_REG(multimedia2),
  4222. },
  4223. {/* hw:x,2 */
  4224. .name = "VoiceMMode1",
  4225. .stream_name = "VoiceMMode1",
  4226. .dynamic = 1,
  4227. .dpcm_playback = 1,
  4228. .dpcm_capture = 1,
  4229. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4230. SND_SOC_DPCM_TRIGGER_POST},
  4231. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4232. .ignore_suspend = 1,
  4233. .ignore_pmdown_time = 1,
  4234. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4235. SND_SOC_DAILINK_REG(voicemmode1),
  4236. },
  4237. {/* hw:x,3 */
  4238. .name = "MSM VoIP",
  4239. .stream_name = "VoIP",
  4240. .dynamic = 1,
  4241. .dpcm_playback = 1,
  4242. .dpcm_capture = 1,
  4243. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4244. SND_SOC_DPCM_TRIGGER_POST},
  4245. .ignore_suspend = 1,
  4246. /* this dainlink has playback support */
  4247. .ignore_pmdown_time = 1,
  4248. .id = MSM_FRONTEND_DAI_VOIP,
  4249. SND_SOC_DAILINK_REG(msmvoip),
  4250. },
  4251. {/* hw:x,4 */
  4252. .name = MSM_DAILINK_NAME(ULL),
  4253. .stream_name = "MultiMedia3",
  4254. .dynamic = 1,
  4255. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4256. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4257. #endif /* CONFIG_AUDIO_QGKI */
  4258. .dpcm_playback = 1,
  4259. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4260. SND_SOC_DPCM_TRIGGER_POST},
  4261. .ignore_suspend = 1,
  4262. /* this dainlink has playback support */
  4263. .ignore_pmdown_time = 1,
  4264. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4265. SND_SOC_DAILINK_REG(multimedia3),
  4266. },
  4267. {/* hw:x,5 */
  4268. .name = "MSM AFE-PCM RX",
  4269. .stream_name = "AFE-PROXY RX",
  4270. .dpcm_playback = 1,
  4271. .ignore_suspend = 1,
  4272. /* this dainlink has playback support */
  4273. .ignore_pmdown_time = 1,
  4274. SND_SOC_DAILINK_REG(afepcm_rx),
  4275. },
  4276. {/* hw:x,6 */
  4277. .name = "MSM AFE-PCM TX",
  4278. .stream_name = "AFE-PROXY TX",
  4279. .dpcm_capture = 1,
  4280. .ignore_suspend = 1,
  4281. SND_SOC_DAILINK_REG(afepcm_tx),
  4282. },
  4283. {/* hw:x,7 */
  4284. .name = MSM_DAILINK_NAME(Compress1),
  4285. .stream_name = "Compress1",
  4286. .dynamic = 1,
  4287. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4288. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4289. #endif /* CONFIG_AUDIO_QGKI */
  4290. .dpcm_playback = 1,
  4291. .dpcm_capture = 1,
  4292. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4293. SND_SOC_DPCM_TRIGGER_POST},
  4294. .ignore_suspend = 1,
  4295. .ignore_pmdown_time = 1,
  4296. /* this dainlink has playback support */
  4297. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4298. SND_SOC_DAILINK_REG(multimedia4),
  4299. },
  4300. /* Hostless PCM purpose */
  4301. {/* hw:x,8 */
  4302. .name = "AUXPCM Hostless",
  4303. .stream_name = "AUXPCM Hostless",
  4304. .dynamic = 1,
  4305. .dpcm_playback = 1,
  4306. .dpcm_capture = 1,
  4307. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4308. SND_SOC_DPCM_TRIGGER_POST},
  4309. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4310. .ignore_suspend = 1,
  4311. /* this dainlink has playback support */
  4312. .ignore_pmdown_time = 1,
  4313. SND_SOC_DAILINK_REG(auxpcm_hostless),
  4314. },
  4315. {/* hw:x,9 */
  4316. .name = MSM_DAILINK_NAME(LowLatency),
  4317. .stream_name = "MultiMedia5",
  4318. .dynamic = 1,
  4319. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4320. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4321. #endif /* CONFIG_AUDIO_QGKI */
  4322. .dpcm_playback = 1,
  4323. .dpcm_capture = 1,
  4324. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4325. SND_SOC_DPCM_TRIGGER_POST},
  4326. .ignore_suspend = 1,
  4327. /* this dainlink has playback support */
  4328. .ignore_pmdown_time = 1,
  4329. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4330. .ops = &msm_fe_qos_ops,
  4331. SND_SOC_DAILINK_REG(multimedia5),
  4332. },
  4333. {/* hw:x,10 */
  4334. .name = "Listen 1 Audio Service",
  4335. .stream_name = "Listen 1 Audio Service",
  4336. .dynamic = 1,
  4337. .dpcm_capture = 1,
  4338. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4339. SND_SOC_DPCM_TRIGGER_POST },
  4340. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4341. .ignore_suspend = 1,
  4342. .id = MSM_FRONTEND_DAI_LSM1,
  4343. SND_SOC_DAILINK_REG(listen1),
  4344. },
  4345. /* Multiple Tunnel instances */
  4346. {/* hw:x,11 */
  4347. .name = MSM_DAILINK_NAME(Compress2),
  4348. .stream_name = "Compress2",
  4349. .dynamic = 1,
  4350. .dpcm_playback = 1,
  4351. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4352. SND_SOC_DPCM_TRIGGER_POST},
  4353. .ignore_suspend = 1,
  4354. .ignore_pmdown_time = 1,
  4355. /* this dainlink has playback support */
  4356. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4357. SND_SOC_DAILINK_REG(multimedia7),
  4358. },
  4359. {/* hw:x,12 */
  4360. .name = MSM_DAILINK_NAME(MultiMedia10),
  4361. .stream_name = "MultiMedia10",
  4362. .dynamic = 1,
  4363. .dpcm_playback = 1,
  4364. .dpcm_capture = 1,
  4365. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4366. SND_SOC_DPCM_TRIGGER_POST},
  4367. .ignore_suspend = 1,
  4368. .ignore_pmdown_time = 1,
  4369. /* this dainlink has playback support */
  4370. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4371. SND_SOC_DAILINK_REG(multimedia10),
  4372. },
  4373. {/* hw:x,13 */
  4374. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4375. .stream_name = "MM_NOIRQ",
  4376. .dynamic = 1,
  4377. .dpcm_playback = 1,
  4378. .dpcm_capture = 1,
  4379. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4380. SND_SOC_DPCM_TRIGGER_POST},
  4381. .ignore_suspend = 1,
  4382. .ignore_pmdown_time = 1,
  4383. /* this dainlink has playback support */
  4384. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4385. .ops = &msm_fe_qos_ops,
  4386. SND_SOC_DAILINK_REG(multimedia8),
  4387. },
  4388. /* HDMI Hostless */
  4389. {/* hw:x,14 */
  4390. .name = "HDMI_RX_HOSTLESS",
  4391. .stream_name = "HDMI_RX_HOSTLESS",
  4392. .dynamic = 1,
  4393. .dpcm_playback = 1,
  4394. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4395. SND_SOC_DPCM_TRIGGER_POST},
  4396. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4397. .ignore_suspend = 1,
  4398. .ignore_pmdown_time = 1,
  4399. SND_SOC_DAILINK_REG(hdmi_rx_hostless),
  4400. },
  4401. {/* hw:x,15 */
  4402. .name = "VoiceMMode2",
  4403. .stream_name = "VoiceMMode2",
  4404. .dynamic = 1,
  4405. .dpcm_playback = 1,
  4406. .dpcm_capture = 1,
  4407. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4408. SND_SOC_DPCM_TRIGGER_POST},
  4409. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4410. .ignore_suspend = 1,
  4411. .ignore_pmdown_time = 1,
  4412. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4413. SND_SOC_DAILINK_REG(voicemmode2),
  4414. },
  4415. /* LSM FE */
  4416. {/* hw:x,16 */
  4417. .name = "Listen 2 Audio Service",
  4418. .stream_name = "Listen 2 Audio Service",
  4419. .dynamic = 1,
  4420. .dpcm_capture = 1,
  4421. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4422. SND_SOC_DPCM_TRIGGER_POST },
  4423. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4424. .ignore_suspend = 1,
  4425. .id = MSM_FRONTEND_DAI_LSM2,
  4426. SND_SOC_DAILINK_REG(listen2),
  4427. },
  4428. {/* hw:x,17 */
  4429. .name = "Listen 3 Audio Service",
  4430. .stream_name = "Listen 3 Audio Service",
  4431. .dynamic = 1,
  4432. .dpcm_capture = 1,
  4433. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4434. SND_SOC_DPCM_TRIGGER_POST },
  4435. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4436. .ignore_suspend = 1,
  4437. .id = MSM_FRONTEND_DAI_LSM3,
  4438. SND_SOC_DAILINK_REG(listen3),
  4439. },
  4440. {/* hw:x,18 */
  4441. .name = "Listen 4 Audio Service",
  4442. .stream_name = "Listen 4 Audio Service",
  4443. .dynamic = 1,
  4444. .dpcm_capture = 1,
  4445. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4446. SND_SOC_DPCM_TRIGGER_POST },
  4447. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4448. .ignore_suspend = 1,
  4449. .id = MSM_FRONTEND_DAI_LSM4,
  4450. SND_SOC_DAILINK_REG(listen4),
  4451. },
  4452. {/* hw:x,19 */
  4453. .name = "Listen 5 Audio Service",
  4454. .stream_name = "Listen 5 Audio Service",
  4455. .dynamic = 1,
  4456. .dpcm_capture = 1,
  4457. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4458. SND_SOC_DPCM_TRIGGER_POST },
  4459. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4460. .ignore_suspend = 1,
  4461. .id = MSM_FRONTEND_DAI_LSM5,
  4462. SND_SOC_DAILINK_REG(listen5),
  4463. },
  4464. {/* hw:x,20 */
  4465. .name = "Listen 6 Audio Service",
  4466. .stream_name = "Listen 6 Audio Service",
  4467. .dynamic = 1,
  4468. .dpcm_capture = 1,
  4469. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4470. SND_SOC_DPCM_TRIGGER_POST },
  4471. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4472. .ignore_suspend = 1,
  4473. .id = MSM_FRONTEND_DAI_LSM6,
  4474. SND_SOC_DAILINK_REG(listen6),
  4475. },
  4476. {/* hw:x,21 */
  4477. .name = "Listen 7 Audio Service",
  4478. .stream_name = "Listen 7 Audio Service",
  4479. .dynamic = 1,
  4480. .dpcm_capture = 1,
  4481. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4482. SND_SOC_DPCM_TRIGGER_POST },
  4483. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4484. .ignore_suspend = 1,
  4485. .id = MSM_FRONTEND_DAI_LSM7,
  4486. SND_SOC_DAILINK_REG(listen7),
  4487. },
  4488. {/* hw:x,22 */
  4489. .name = "Listen 8 Audio Service",
  4490. .stream_name = "Listen 8 Audio Service",
  4491. .dynamic = 1,
  4492. .dpcm_capture = 1,
  4493. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4494. SND_SOC_DPCM_TRIGGER_POST },
  4495. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4496. .ignore_suspend = 1,
  4497. .id = MSM_FRONTEND_DAI_LSM8,
  4498. SND_SOC_DAILINK_REG(listen8),
  4499. },
  4500. {/* hw:x,23 */
  4501. .name = MSM_DAILINK_NAME(Media9),
  4502. .stream_name = "MultiMedia9",
  4503. .dynamic = 1,
  4504. .dpcm_playback = 1,
  4505. .dpcm_capture = 1,
  4506. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4507. SND_SOC_DPCM_TRIGGER_POST},
  4508. .ignore_suspend = 1,
  4509. /* this dainlink has playback support */
  4510. .ignore_pmdown_time = 1,
  4511. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4512. SND_SOC_DAILINK_REG(multimedia9),
  4513. },
  4514. {/* hw:x,24 */
  4515. .name = MSM_DAILINK_NAME(Compress4),
  4516. .stream_name = "Compress4",
  4517. .dynamic = 1,
  4518. .dpcm_playback = 1,
  4519. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4520. SND_SOC_DPCM_TRIGGER_POST},
  4521. .ignore_suspend = 1,
  4522. .ignore_pmdown_time = 1,
  4523. /* this dainlink has playback support */
  4524. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4525. SND_SOC_DAILINK_REG(multimedia11),
  4526. },
  4527. {/* hw:x,25 */
  4528. .name = MSM_DAILINK_NAME(Compress5),
  4529. .stream_name = "Compress5",
  4530. .dynamic = 1,
  4531. .dpcm_playback = 1,
  4532. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4533. SND_SOC_DPCM_TRIGGER_POST},
  4534. .ignore_suspend = 1,
  4535. .ignore_pmdown_time = 1,
  4536. /* this dainlink has playback support */
  4537. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4538. SND_SOC_DAILINK_REG(multimedia12),
  4539. },
  4540. {/* hw:x,26 */
  4541. .name = MSM_DAILINK_NAME(Compress6),
  4542. .stream_name = "Compress6",
  4543. .dynamic = 1,
  4544. .dpcm_playback = 1,
  4545. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4546. SND_SOC_DPCM_TRIGGER_POST},
  4547. .ignore_suspend = 1,
  4548. .ignore_pmdown_time = 1,
  4549. /* this dainlink has playback support */
  4550. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4551. SND_SOC_DAILINK_REG(multimedia13),
  4552. },
  4553. {/* hw:x,27 */
  4554. .name = MSM_DAILINK_NAME(Compress7),
  4555. .stream_name = "Compress7",
  4556. .dynamic = 1,
  4557. .dpcm_playback = 1,
  4558. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4559. SND_SOC_DPCM_TRIGGER_POST},
  4560. .ignore_suspend = 1,
  4561. .ignore_pmdown_time = 1,
  4562. /* this dainlink has playback support */
  4563. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4564. SND_SOC_DAILINK_REG(multimedia14),
  4565. },
  4566. {/* hw:x,28 */
  4567. .name = MSM_DAILINK_NAME(Compress8),
  4568. .stream_name = "Compress8",
  4569. .dynamic = 1,
  4570. .dpcm_playback = 1,
  4571. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4572. SND_SOC_DPCM_TRIGGER_POST},
  4573. .ignore_suspend = 1,
  4574. .ignore_pmdown_time = 1,
  4575. /* this dainlink has playback support */
  4576. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4577. SND_SOC_DAILINK_REG(multimedia15),
  4578. },
  4579. {/* hw:x,29 */
  4580. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4581. .stream_name = "MM_NOIRQ_2",
  4582. .dynamic = 1,
  4583. .dpcm_playback = 1,
  4584. .dpcm_capture = 1,
  4585. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4586. SND_SOC_DPCM_TRIGGER_POST},
  4587. .ignore_suspend = 1,
  4588. .ignore_pmdown_time = 1,
  4589. /* this dainlink has playback support */
  4590. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4591. .ops = &msm_fe_qos_ops,
  4592. SND_SOC_DAILINK_REG(multimedia16),
  4593. },
  4594. {/* hw:x,30 */
  4595. .name = "CDC_DMA Hostless",
  4596. .stream_name = "CDC_DMA Hostless",
  4597. .dynamic = 1,
  4598. .dpcm_playback = 1,
  4599. .dpcm_capture = 1,
  4600. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4601. SND_SOC_DPCM_TRIGGER_POST},
  4602. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4603. .ignore_suspend = 1,
  4604. /* this dailink has playback support */
  4605. .ignore_pmdown_time = 1,
  4606. SND_SOC_DAILINK_REG(cdcdma_hostless),
  4607. },
  4608. {/* hw:x,31 */
  4609. .name = "TX3_CDC_DMA Hostless",
  4610. .stream_name = "TX3_CDC_DMA Hostless",
  4611. .dynamic = 1,
  4612. .dpcm_capture = 1,
  4613. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4614. SND_SOC_DPCM_TRIGGER_POST},
  4615. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4616. .ignore_suspend = 1,
  4617. SND_SOC_DAILINK_REG(tx3_cdcdma_hostless),
  4618. },
  4619. {/* hw:x,32 */
  4620. .name = "Tertiary MI2S TX_Hostless",
  4621. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4622. .dynamic = 1,
  4623. .dpcm_capture = 1,
  4624. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4625. SND_SOC_DPCM_TRIGGER_POST},
  4626. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4627. .ignore_suspend = 1,
  4628. .ignore_pmdown_time = 1,
  4629. SND_SOC_DAILINK_REG(tert_mi2s_tx_hostless),
  4630. },
  4631. };
  4632. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4633. {/* hw:x,33 */
  4634. .name = MSM_DAILINK_NAME(ASM Loopback),
  4635. .stream_name = "MultiMedia6",
  4636. .dynamic = 1,
  4637. .dpcm_playback = 1,
  4638. .dpcm_capture = 1,
  4639. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4640. SND_SOC_DPCM_TRIGGER_POST},
  4641. .ignore_suspend = 1,
  4642. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4643. .ignore_pmdown_time = 1,
  4644. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4645. SND_SOC_DAILINK_REG(multimedia6),
  4646. },
  4647. {/* hw:x,34 */
  4648. .name = "USB Audio Hostless",
  4649. .stream_name = "USB Audio Hostless",
  4650. .dynamic = 1,
  4651. .dpcm_playback = 1,
  4652. .dpcm_capture = 1,
  4653. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4654. SND_SOC_DPCM_TRIGGER_POST},
  4655. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4656. .ignore_suspend = 1,
  4657. .ignore_pmdown_time = 1,
  4658. SND_SOC_DAILINK_REG(usbaudio_hostless),
  4659. },
  4660. {/* hw:x,35 */
  4661. .name = "SLIMBUS_7 Hostless",
  4662. .stream_name = "SLIMBUS_7 Hostless",
  4663. .dynamic = 1,
  4664. .dpcm_capture = 1,
  4665. .dpcm_playback = 1,
  4666. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4667. SND_SOC_DPCM_TRIGGER_POST},
  4668. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4669. .ignore_suspend = 1,
  4670. .ignore_pmdown_time = 1,
  4671. SND_SOC_DAILINK_REG(slimbus7_hostless),
  4672. },
  4673. {/* hw:x,36 */
  4674. .name = "Compress Capture",
  4675. .stream_name = "Compress9",
  4676. .dynamic = 1,
  4677. .dpcm_capture = 1,
  4678. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4679. SND_SOC_DPCM_TRIGGER_POST},
  4680. .ignore_suspend = 1,
  4681. .ignore_pmdown_time = 1,
  4682. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4683. SND_SOC_DAILINK_REG(multimedia17),
  4684. },
  4685. {/* hw:x,37 */
  4686. .name = "SLIMBUS_8 Hostless",
  4687. .stream_name = "SLIMBUS_8 Hostless",
  4688. .dynamic = 1,
  4689. .dpcm_capture = 1,
  4690. .dpcm_playback = 1,
  4691. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4692. SND_SOC_DPCM_TRIGGER_POST},
  4693. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4694. .ignore_suspend = 1,
  4695. .ignore_pmdown_time = 1,
  4696. SND_SOC_DAILINK_REG(slimbus8_hostless),
  4697. },
  4698. {/* hw:x,38 */
  4699. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  4700. .stream_name = "TX CDC DMA5 Capture",
  4701. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  4702. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4703. .ignore_suspend = 1,
  4704. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4705. .ops = &msm_cdc_dma_be_ops,
  4706. SND_SOC_DAILINK_REG(tx_cdcdma5_tx),
  4707. },
  4708. {/* hw:x,39 */
  4709. .name = MSM_DAILINK_NAME(Media31),
  4710. .stream_name = "MultiMedia31",
  4711. .dynamic = 1,
  4712. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4713. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4714. #endif /* CONFIG_AUDIO_QGKI */
  4715. .dpcm_playback = 1,
  4716. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4717. SND_SOC_DPCM_TRIGGER_POST},
  4718. .ignore_suspend = 1,
  4719. /* this dainlink has playback support */
  4720. .ignore_pmdown_time = 1,
  4721. .id = MSM_FRONTEND_DAI_MULTIMEDIA31,
  4722. SND_SOC_DAILINK_REG(multimedia31),
  4723. },
  4724. {/* hw:x,40 */
  4725. .name = MSM_DAILINK_NAME(Media32),
  4726. .stream_name = "MultiMedia32",
  4727. .dynamic = 1,
  4728. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4729. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4730. #endif /* CONFIG_AUDIO_QGKI */
  4731. .dpcm_playback = 1,
  4732. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4733. SND_SOC_DPCM_TRIGGER_POST},
  4734. .ignore_suspend = 1,
  4735. /* this dainlink has playback support */
  4736. .ignore_pmdown_time = 1,
  4737. .id = MSM_FRONTEND_DAI_MULTIMEDIA32,
  4738. SND_SOC_DAILINK_REG(multimedia32),
  4739. },
  4740. {/* hw:x,41 */
  4741. .name = "MSM AFE-PCM TX1",
  4742. .stream_name = "AFE-PROXY TX1",
  4743. .dpcm_capture = 1,
  4744. .ignore_suspend = 1,
  4745. SND_SOC_DAILINK_REG(afepcm_tx1),
  4746. },
  4747. };
  4748. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4749. /* Backend AFE DAI Links */
  4750. {
  4751. .name = LPASS_BE_AFE_PCM_RX,
  4752. .stream_name = "AFE Playback",
  4753. .no_pcm = 1,
  4754. .dpcm_playback = 1,
  4755. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4756. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4757. /* this dainlink has playback support */
  4758. .ignore_pmdown_time = 1,
  4759. .ignore_suspend = 1,
  4760. SND_SOC_DAILINK_REG(afe_pcm_rx),
  4761. },
  4762. {
  4763. .name = LPASS_BE_AFE_PCM_TX,
  4764. .stream_name = "AFE Capture",
  4765. .no_pcm = 1,
  4766. .dpcm_capture = 1,
  4767. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4768. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4769. .ignore_suspend = 1,
  4770. SND_SOC_DAILINK_REG(afe_pcm_tx),
  4771. },
  4772. /* Incall Record Uplink BACK END DAI Link */
  4773. {
  4774. .name = LPASS_BE_INCALL_RECORD_TX,
  4775. .stream_name = "Voice Uplink Capture",
  4776. .no_pcm = 1,
  4777. .dpcm_capture = 1,
  4778. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4779. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4780. .ignore_suspend = 1,
  4781. SND_SOC_DAILINK_REG(incall_record_tx),
  4782. },
  4783. /* Incall Record Downlink BACK END DAI Link */
  4784. {
  4785. .name = LPASS_BE_INCALL_RECORD_RX,
  4786. .stream_name = "Voice Downlink Capture",
  4787. .no_pcm = 1,
  4788. .dpcm_capture = 1,
  4789. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4790. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4791. .ignore_suspend = 1,
  4792. SND_SOC_DAILINK_REG(incall_record_rx),
  4793. },
  4794. /* Incall Music BACK END DAI Link */
  4795. {
  4796. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4797. .stream_name = "Voice Farend Playback",
  4798. .no_pcm = 1,
  4799. .dpcm_playback = 1,
  4800. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4801. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4802. .ignore_suspend = 1,
  4803. .ignore_pmdown_time = 1,
  4804. SND_SOC_DAILINK_REG(voice_playback_tx),
  4805. },
  4806. /* Incall Music 2 BACK END DAI Link */
  4807. {
  4808. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4809. .stream_name = "Voice2 Farend Playback",
  4810. .no_pcm = 1,
  4811. .dpcm_playback = 1,
  4812. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4813. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4814. .ignore_suspend = 1,
  4815. .ignore_pmdown_time = 1,
  4816. SND_SOC_DAILINK_REG(voice2_playback_tx),
  4817. },
  4818. /* Proxy Tx BACK END DAI Link */
  4819. {
  4820. .name = LPASS_BE_PROXY_TX,
  4821. .stream_name = "Proxy Capture",
  4822. .no_pcm = 1,
  4823. .dpcm_capture = 1,
  4824. .id = MSM_BACKEND_DAI_PROXY_TX,
  4825. .ignore_suspend = 1,
  4826. SND_SOC_DAILINK_REG(proxy_tx),
  4827. },
  4828. /* Proxy Rx BACK END DAI Link */
  4829. {
  4830. .name = LPASS_BE_PROXY_RX,
  4831. .stream_name = "Proxy Playback",
  4832. .no_pcm = 1,
  4833. .dpcm_playback = 1,
  4834. .id = MSM_BACKEND_DAI_PROXY_RX,
  4835. .ignore_pmdown_time = 1,
  4836. .ignore_suspend = 1,
  4837. SND_SOC_DAILINK_REG(proxy_rx),
  4838. },
  4839. {
  4840. .name = LPASS_BE_USB_AUDIO_RX,
  4841. .stream_name = "USB Audio Playback",
  4842. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4843. .dynamic_be = 1,
  4844. #endif /* CONFIG_AUDIO_QGKI */
  4845. .no_pcm = 1,
  4846. .dpcm_playback = 1,
  4847. .id = MSM_BACKEND_DAI_USB_RX,
  4848. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4849. .ignore_pmdown_time = 1,
  4850. .ignore_suspend = 1,
  4851. SND_SOC_DAILINK_REG(usb_audio_rx),
  4852. },
  4853. {
  4854. .name = LPASS_BE_USB_AUDIO_TX,
  4855. .stream_name = "USB Audio Capture",
  4856. .no_pcm = 1,
  4857. .dpcm_capture = 1,
  4858. .id = MSM_BACKEND_DAI_USB_TX,
  4859. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4860. .ignore_suspend = 1,
  4861. SND_SOC_DAILINK_REG(usb_audio_tx),
  4862. },
  4863. {
  4864. .name = LPASS_BE_PRI_TDM_RX_0,
  4865. .stream_name = "Primary TDM0 Playback",
  4866. .no_pcm = 1,
  4867. .dpcm_playback = 1,
  4868. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4869. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4870. .ops = &holi_tdm_be_ops,
  4871. .ignore_suspend = 1,
  4872. .ignore_pmdown_time = 1,
  4873. SND_SOC_DAILINK_REG(pri_tdm_rx_0),
  4874. },
  4875. {
  4876. .name = LPASS_BE_PRI_TDM_TX_0,
  4877. .stream_name = "Primary TDM0 Capture",
  4878. .no_pcm = 1,
  4879. .dpcm_capture = 1,
  4880. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4881. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4882. .ops = &holi_tdm_be_ops,
  4883. .ignore_suspend = 1,
  4884. SND_SOC_DAILINK_REG(pri_tdm_tx_0),
  4885. },
  4886. {
  4887. .name = LPASS_BE_SEC_TDM_RX_0,
  4888. .stream_name = "Secondary TDM0 Playback",
  4889. .no_pcm = 1,
  4890. .dpcm_playback = 1,
  4891. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4892. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4893. .ops = &holi_tdm_be_ops,
  4894. .ignore_suspend = 1,
  4895. .ignore_pmdown_time = 1,
  4896. SND_SOC_DAILINK_REG(sec_tdm_rx_0),
  4897. },
  4898. {
  4899. .name = LPASS_BE_SEC_TDM_TX_0,
  4900. .stream_name = "Secondary TDM0 Capture",
  4901. .no_pcm = 1,
  4902. .dpcm_capture = 1,
  4903. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4904. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4905. .ops = &holi_tdm_be_ops,
  4906. .ignore_suspend = 1,
  4907. SND_SOC_DAILINK_REG(sec_tdm_tx_0),
  4908. },
  4909. {
  4910. .name = LPASS_BE_TERT_TDM_RX_0,
  4911. .stream_name = "Tertiary TDM0 Playback",
  4912. .no_pcm = 1,
  4913. .dpcm_playback = 1,
  4914. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4915. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4916. .ops = &holi_tdm_be_ops,
  4917. .ignore_suspend = 1,
  4918. .ignore_pmdown_time = 1,
  4919. SND_SOC_DAILINK_REG(tert_tdm_rx_0),
  4920. },
  4921. {
  4922. .name = LPASS_BE_TERT_TDM_TX_0,
  4923. .stream_name = "Tertiary TDM0 Capture",
  4924. .no_pcm = 1,
  4925. .dpcm_capture = 1,
  4926. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4927. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4928. .ops = &holi_tdm_be_ops,
  4929. .ignore_suspend = 1,
  4930. SND_SOC_DAILINK_REG(tert_tdm_tx_0),
  4931. },
  4932. {
  4933. .name = LPASS_BE_QUAT_TDM_RX_0,
  4934. .stream_name = "Quaternary TDM0 Playback",
  4935. .no_pcm = 1,
  4936. .dpcm_playback = 1,
  4937. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  4938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4939. .ops = &holi_tdm_be_ops,
  4940. .ignore_suspend = 1,
  4941. .ignore_pmdown_time = 1,
  4942. SND_SOC_DAILINK_REG(quat_tdm_rx_0),
  4943. },
  4944. {
  4945. .name = LPASS_BE_QUAT_TDM_TX_0,
  4946. .stream_name = "Quaternary TDM0 Capture",
  4947. .no_pcm = 1,
  4948. .dpcm_capture = 1,
  4949. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  4950. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4951. .ops = &holi_tdm_be_ops,
  4952. .ignore_suspend = 1,
  4953. SND_SOC_DAILINK_REG(quat_tdm_tx_0),
  4954. },
  4955. };
  4956. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  4957. {
  4958. .name = LPASS_BE_SLIMBUS_7_RX,
  4959. .stream_name = "Slimbus7 Playback",
  4960. .no_pcm = 1,
  4961. .dpcm_playback = 1,
  4962. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  4963. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4964. .init = &msm_wcn_init_lito,
  4965. .ops = &msm_wcn_ops_lito,
  4966. /* dai link has playback support */
  4967. .ignore_pmdown_time = 1,
  4968. .ignore_suspend = 1,
  4969. SND_SOC_DAILINK_REG(slimbus_7_rx),
  4970. },
  4971. {
  4972. .name = LPASS_BE_SLIMBUS_7_TX,
  4973. .stream_name = "Slimbus7 Capture",
  4974. .no_pcm = 1,
  4975. .dpcm_capture = 1,
  4976. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  4977. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4978. .ops = &msm_wcn_ops_lito,
  4979. .ignore_suspend = 1,
  4980. SND_SOC_DAILINK_REG(slimbus_7_tx),
  4981. },
  4982. {
  4983. .name = LPASS_BE_SLIMBUS_8_TX,
  4984. .stream_name = "Slimbus8 Capture",
  4985. .no_pcm = 1,
  4986. .dpcm_capture = 1,
  4987. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  4988. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4989. .ops = &msm_wcn_ops_lito,
  4990. .ignore_suspend = 1,
  4991. SND_SOC_DAILINK_REG(slimbus_8_tx),
  4992. },
  4993. };
  4994. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  4995. {
  4996. .name = LPASS_BE_PRI_MI2S_RX,
  4997. .stream_name = "Primary MI2S Playback",
  4998. .no_pcm = 1,
  4999. .dpcm_playback = 1,
  5000. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5001. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5002. .ops = &msm_mi2s_be_ops,
  5003. .ignore_suspend = 1,
  5004. .ignore_pmdown_time = 1,
  5005. SND_SOC_DAILINK_REG(pri_mi2s_rx),
  5006. },
  5007. {
  5008. .name = LPASS_BE_PRI_MI2S_TX,
  5009. .stream_name = "Primary MI2S Capture",
  5010. .no_pcm = 1,
  5011. .dpcm_capture = 1,
  5012. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5013. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5014. .ops = &msm_mi2s_be_ops,
  5015. .ignore_suspend = 1,
  5016. SND_SOC_DAILINK_REG(pri_mi2s_tx),
  5017. },
  5018. {
  5019. .name = LPASS_BE_SEC_MI2S_RX,
  5020. .stream_name = "Secondary MI2S Playback",
  5021. .no_pcm = 1,
  5022. .dpcm_playback = 1,
  5023. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5024. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5025. .ops = &msm_mi2s_be_ops,
  5026. .ignore_suspend = 1,
  5027. .ignore_pmdown_time = 1,
  5028. SND_SOC_DAILINK_REG(sec_mi2s_rx),
  5029. },
  5030. {
  5031. .name = LPASS_BE_SEC_MI2S_TX,
  5032. .stream_name = "Secondary MI2S Capture",
  5033. .no_pcm = 1,
  5034. .dpcm_capture = 1,
  5035. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5036. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5037. .ops = &msm_mi2s_be_ops,
  5038. .ignore_suspend = 1,
  5039. SND_SOC_DAILINK_REG(sec_mi2s_tx),
  5040. },
  5041. {
  5042. .name = LPASS_BE_TERT_MI2S_RX,
  5043. .stream_name = "Tertiary MI2S Playback",
  5044. .no_pcm = 1,
  5045. .dpcm_playback = 1,
  5046. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5047. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5048. .ops = &msm_mi2s_be_ops,
  5049. .ignore_suspend = 1,
  5050. .ignore_pmdown_time = 1,
  5051. SND_SOC_DAILINK_REG(tert_mi2s_rx),
  5052. },
  5053. {
  5054. .name = LPASS_BE_TERT_MI2S_TX,
  5055. .stream_name = "Tertiary MI2S Capture",
  5056. .no_pcm = 1,
  5057. .dpcm_capture = 1,
  5058. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5059. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5060. .ops = &msm_mi2s_be_ops,
  5061. .ignore_suspend = 1,
  5062. SND_SOC_DAILINK_REG(tert_mi2s_tx),
  5063. },
  5064. {
  5065. .name = LPASS_BE_QUAT_MI2S_RX,
  5066. .stream_name = "Quaternary MI2S Playback",
  5067. .no_pcm = 1,
  5068. .dpcm_playback = 1,
  5069. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5070. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5071. .ops = &msm_mi2s_be_ops,
  5072. .ignore_suspend = 1,
  5073. .ignore_pmdown_time = 1,
  5074. SND_SOC_DAILINK_REG(quat_mi2s_rx),
  5075. },
  5076. {
  5077. .name = LPASS_BE_QUAT_MI2S_TX,
  5078. .stream_name = "Quaternary MI2S Capture",
  5079. .no_pcm = 1,
  5080. .dpcm_capture = 1,
  5081. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5082. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5083. .ops = &msm_mi2s_be_ops,
  5084. .ignore_suspend = 1,
  5085. SND_SOC_DAILINK_REG(quat_mi2s_tx),
  5086. },
  5087. };
  5088. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5089. /* Primary AUX PCM Backend DAI Links */
  5090. {
  5091. .name = LPASS_BE_AUXPCM_RX,
  5092. .stream_name = "AUX PCM Playback",
  5093. .no_pcm = 1,
  5094. .dpcm_playback = 1,
  5095. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5096. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5097. .ops = &holi_aux_be_ops,
  5098. .ignore_pmdown_time = 1,
  5099. .ignore_suspend = 1,
  5100. SND_SOC_DAILINK_REG(auxpcm_rx),
  5101. },
  5102. {
  5103. .name = LPASS_BE_AUXPCM_TX,
  5104. .stream_name = "AUX PCM Capture",
  5105. .no_pcm = 1,
  5106. .dpcm_capture = 1,
  5107. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5108. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5109. .ops = &holi_aux_be_ops,
  5110. .ignore_suspend = 1,
  5111. SND_SOC_DAILINK_REG(auxpcm_tx),
  5112. },
  5113. /* Secondary AUX PCM Backend DAI Links */
  5114. {
  5115. .name = LPASS_BE_SEC_AUXPCM_RX,
  5116. .stream_name = "Sec AUX PCM Playback",
  5117. .no_pcm = 1,
  5118. .dpcm_playback = 1,
  5119. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5120. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5121. .ops = &holi_aux_be_ops,
  5122. .ignore_pmdown_time = 1,
  5123. .ignore_suspend = 1,
  5124. SND_SOC_DAILINK_REG(sec_auxpcm_rx),
  5125. },
  5126. {
  5127. .name = LPASS_BE_SEC_AUXPCM_TX,
  5128. .stream_name = "Sec AUX PCM Capture",
  5129. .no_pcm = 1,
  5130. .dpcm_capture = 1,
  5131. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5132. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5133. .ops = &holi_aux_be_ops,
  5134. .ignore_suspend = 1,
  5135. SND_SOC_DAILINK_REG(sec_auxpcm_tx),
  5136. },
  5137. /* Tertiary AUX PCM Backend DAI Links */
  5138. {
  5139. .name = LPASS_BE_TERT_AUXPCM_RX,
  5140. .stream_name = "Tert AUX PCM Playback",
  5141. .no_pcm = 1,
  5142. .dpcm_playback = 1,
  5143. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5144. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5145. .ops = &holi_aux_be_ops,
  5146. .ignore_suspend = 1,
  5147. SND_SOC_DAILINK_REG(tert_auxpcm_rx),
  5148. },
  5149. {
  5150. .name = LPASS_BE_TERT_AUXPCM_TX,
  5151. .stream_name = "Tert AUX PCM Capture",
  5152. .no_pcm = 1,
  5153. .dpcm_capture = 1,
  5154. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5155. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5156. .ops = &holi_aux_be_ops,
  5157. .ignore_suspend = 1,
  5158. SND_SOC_DAILINK_REG(tert_auxpcm_tx),
  5159. },
  5160. /* Quaternary AUX PCM Backend DAI Links */
  5161. {
  5162. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5163. .stream_name = "Quat AUX PCM Playback",
  5164. .no_pcm = 1,
  5165. .dpcm_playback = 1,
  5166. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5167. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5168. .ops = &holi_aux_be_ops,
  5169. .ignore_suspend = 1,
  5170. SND_SOC_DAILINK_REG(quat_auxpcm_rx),
  5171. },
  5172. {
  5173. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5174. .stream_name = "Quat AUX PCM Capture",
  5175. .no_pcm = 1,
  5176. .dpcm_capture = 1,
  5177. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5178. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5179. .ops = &holi_aux_be_ops,
  5180. .ignore_suspend = 1,
  5181. SND_SOC_DAILINK_REG(quat_auxpcm_tx),
  5182. },
  5183. };
  5184. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5185. /* RX CDC DMA Backend DAI Links */
  5186. {
  5187. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5188. .stream_name = "RX CDC DMA0 Playback",
  5189. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5190. .dynamic_be = 1,
  5191. #endif /* CONFIG_AUDIO_QGKI */
  5192. .no_pcm = 1,
  5193. .dpcm_playback = 1,
  5194. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5196. .ignore_pmdown_time = 1,
  5197. .ignore_suspend = 1,
  5198. .ops = &msm_cdc_dma_be_ops,
  5199. SND_SOC_DAILINK_REG(rx_dma_rx0),
  5200. .init = &msm_aux_codec_init,
  5201. },
  5202. {
  5203. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5204. .stream_name = "RX CDC DMA1 Playback",
  5205. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5206. .dynamic_be = 1,
  5207. #endif /* CONFIG_AUDIO_QGKI */
  5208. .no_pcm = 1,
  5209. .dpcm_playback = 1,
  5210. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5211. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5212. .ignore_pmdown_time = 1,
  5213. .ignore_suspend = 1,
  5214. .ops = &msm_cdc_dma_be_ops,
  5215. SND_SOC_DAILINK_REG(rx_dma_rx1),
  5216. },
  5217. {
  5218. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5219. .stream_name = "RX CDC DMA2 Playback",
  5220. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5221. .dynamic_be = 1,
  5222. #endif /* CONFIG_AUDIO_QGKI */
  5223. .no_pcm = 1,
  5224. .dpcm_playback = 1,
  5225. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5226. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5227. .ignore_pmdown_time = 1,
  5228. .ignore_suspend = 1,
  5229. .ops = &msm_cdc_dma_be_ops,
  5230. SND_SOC_DAILINK_REG(rx_dma_rx2),
  5231. },
  5232. {
  5233. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5234. .stream_name = "RX CDC DMA3 Playback",
  5235. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5236. .dynamic_be = 1,
  5237. #endif /* CONFIG_AUDIO_QGKI */
  5238. .no_pcm = 1,
  5239. .dpcm_playback = 1,
  5240. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5241. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5242. .ignore_pmdown_time = 1,
  5243. .ignore_suspend = 1,
  5244. .ops = &msm_cdc_dma_be_ops,
  5245. SND_SOC_DAILINK_REG(rx_dma_rx3),
  5246. },
  5247. /* TX CDC DMA Backend DAI Links */
  5248. {
  5249. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5250. .stream_name = "TX CDC DMA3 Capture",
  5251. .no_pcm = 1,
  5252. .dpcm_capture = 1,
  5253. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5254. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5255. .ignore_suspend = 1,
  5256. .ops = &msm_cdc_dma_be_ops,
  5257. SND_SOC_DAILINK_REG(tx_dma_tx3),
  5258. },
  5259. {
  5260. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5261. .stream_name = "TX CDC DMA4 Capture",
  5262. .no_pcm = 1,
  5263. .dpcm_capture = 1,
  5264. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5265. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5266. .ignore_suspend = 1,
  5267. .ops = &msm_cdc_dma_be_ops,
  5268. SND_SOC_DAILINK_REG(tx_dma_tx4),
  5269. },
  5270. };
  5271. static struct snd_soc_dai_link msm_rx_tx_cdc937x_dma_be_dai_links[] = {
  5272. /* RX CDC DMA Backend DAI Links */
  5273. {
  5274. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5275. .stream_name = "RX CDC DMA0 Playback",
  5276. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5277. .dynamic_be = 1,
  5278. #endif /* CONFIG_AUDIO_QGKI */
  5279. .no_pcm = 1,
  5280. .dpcm_playback = 1,
  5281. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5282. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5283. .ignore_pmdown_time = 1,
  5284. .ignore_suspend = 1,
  5285. .ops = &msm_cdc_dma_be_ops,
  5286. SND_SOC_DAILINK_REG(rx_dma_rx0_937x),
  5287. .init = &msm_aux_codec_init,
  5288. },
  5289. {
  5290. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5291. .stream_name = "RX CDC DMA1 Playback",
  5292. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5293. .dynamic_be = 1,
  5294. #endif /* CONFIG_AUDIO_QGKI */
  5295. .no_pcm = 1,
  5296. .dpcm_playback = 1,
  5297. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5298. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5299. .ignore_pmdown_time = 1,
  5300. .ignore_suspend = 1,
  5301. .ops = &msm_cdc_dma_be_ops,
  5302. SND_SOC_DAILINK_REG(rx_dma_rx1_937x),
  5303. },
  5304. {
  5305. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5306. .stream_name = "RX CDC DMA2 Playback",
  5307. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5308. .dynamic_be = 1,
  5309. #endif /* CONFIG_AUDIO_QGKI */
  5310. .no_pcm = 1,
  5311. .dpcm_playback = 1,
  5312. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5313. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5314. .ignore_pmdown_time = 1,
  5315. .ignore_suspend = 1,
  5316. .ops = &msm_cdc_dma_be_ops,
  5317. SND_SOC_DAILINK_REG(rx_dma_rx2_937x),
  5318. },
  5319. {
  5320. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5321. .stream_name = "RX CDC DMA3 Playback",
  5322. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5323. .dynamic_be = 1,
  5324. #endif /* CONFIG_AUDIO_QGKI */
  5325. .no_pcm = 1,
  5326. .dpcm_playback = 1,
  5327. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5328. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5329. .ignore_pmdown_time = 1,
  5330. .ignore_suspend = 1,
  5331. .ops = &msm_cdc_dma_be_ops,
  5332. SND_SOC_DAILINK_REG(rx_dma_rx3_937x),
  5333. },
  5334. /* TX CDC DMA Backend DAI Links */
  5335. {
  5336. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5337. .stream_name = "TX CDC DMA3 Capture",
  5338. .no_pcm = 1,
  5339. .dpcm_capture = 1,
  5340. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5341. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5342. .ignore_suspend = 1,
  5343. .ops = &msm_cdc_dma_be_ops,
  5344. SND_SOC_DAILINK_REG(tx_dma_tx3_937x),
  5345. },
  5346. {
  5347. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5348. .stream_name = "TX CDC DMA4 Capture",
  5349. .no_pcm = 1,
  5350. .dpcm_capture = 1,
  5351. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5352. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5353. .ignore_suspend = 1,
  5354. .ops = &msm_cdc_dma_be_ops,
  5355. SND_SOC_DAILINK_REG(tx_dma_tx4_937x),
  5356. },
  5357. };
  5358. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5359. {
  5360. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5361. .stream_name = "VA CDC DMA0 Capture",
  5362. .no_pcm = 1,
  5363. .dpcm_capture = 1,
  5364. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5365. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5366. .ignore_suspend = 1,
  5367. .ops = &msm_cdc_dma_be_ops,
  5368. SND_SOC_DAILINK_REG(va_dma_tx0),
  5369. .init = &msm_int_audrx_init,
  5370. },
  5371. {
  5372. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5373. .stream_name = "VA CDC DMA1 Capture",
  5374. .no_pcm = 1,
  5375. .dpcm_capture = 1,
  5376. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5377. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5378. .ignore_suspend = 1,
  5379. .ops = &msm_cdc_dma_be_ops,
  5380. SND_SOC_DAILINK_REG(va_dma_tx1),
  5381. },
  5382. {
  5383. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5384. .stream_name = "VA CDC DMA2 Capture",
  5385. .no_pcm = 1,
  5386. .dpcm_capture = 1,
  5387. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5388. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5389. .ignore_suspend = 1,
  5390. .ops = &msm_cdc_dma_be_ops,
  5391. SND_SOC_DAILINK_REG(va_dma_tx2),
  5392. },
  5393. };
  5394. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5395. {
  5396. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5397. .stream_name = "AFE Loopback Capture",
  5398. .no_pcm = 1,
  5399. .dpcm_capture = 1,
  5400. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5401. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5402. .ignore_pmdown_time = 1,
  5403. .ignore_suspend = 1,
  5404. SND_SOC_DAILINK_REG(afe_loopback_tx),
  5405. },
  5406. };
  5407. static struct snd_soc_dai_link msm_holi_dai_links[
  5408. ARRAY_SIZE(msm_common_dai_links) +
  5409. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5410. ARRAY_SIZE(msm_common_be_dai_links) +
  5411. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5412. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5413. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5414. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5415. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  5416. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  5417. static int msm_populate_dai_link_component_of_node(
  5418. struct snd_soc_card *card)
  5419. {
  5420. int i, j, index, ret = 0;
  5421. struct device *cdev = card->dev;
  5422. struct snd_soc_dai_link *dai_link = card->dai_link;
  5423. struct device_node *np = NULL;
  5424. int codecs_enabled = 0;
  5425. struct snd_soc_dai_link_component *codecs_comp = NULL;
  5426. if (!cdev) {
  5427. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5428. return -ENODEV;
  5429. }
  5430. for (i = 0; i < card->num_links; i++) {
  5431. if (dai_link[i].platforms->of_node && dai_link[i].cpus->of_node)
  5432. continue;
  5433. /* populate platform_of_node for snd card dai links */
  5434. if (dai_link[i].platforms->name &&
  5435. !dai_link[i].platforms->of_node) {
  5436. index = of_property_match_string(cdev->of_node,
  5437. "asoc-platform-names",
  5438. dai_link[i].platforms->name);
  5439. if (index < 0) {
  5440. dev_err(cdev, "%s: No match found for platform name: %s\n",
  5441. __func__, dai_link[i].platforms->name);
  5442. ret = index;
  5443. goto err;
  5444. }
  5445. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5446. index);
  5447. if (!np) {
  5448. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  5449. __func__, dai_link[i].platforms->name,
  5450. index);
  5451. ret = -ENODEV;
  5452. goto err;
  5453. }
  5454. dai_link[i].platforms->of_node = np;
  5455. dai_link[i].platforms->name = NULL;
  5456. }
  5457. /* populate cpu_of_node for snd card dai links */
  5458. if (dai_link[i].cpus->dai_name && !dai_link[i].cpus->of_node) {
  5459. index = of_property_match_string(cdev->of_node,
  5460. "asoc-cpu-names",
  5461. dai_link[i].cpus->dai_name);
  5462. if (index >= 0) {
  5463. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5464. index);
  5465. if (!np) {
  5466. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  5467. __func__,
  5468. dai_link[i].cpus->dai_name);
  5469. ret = -ENODEV;
  5470. goto err;
  5471. }
  5472. dai_link[i].cpus->of_node = np;
  5473. dai_link[i].cpus->dai_name = NULL;
  5474. }
  5475. }
  5476. /* populate codec_of_node for snd card dai links */
  5477. if (dai_link[i].num_codecs > 0) {
  5478. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5479. if (dai_link[i].codecs[j].of_node ||
  5480. !dai_link[i].codecs[j].name)
  5481. continue;
  5482. index = of_property_match_string(cdev->of_node,
  5483. "asoc-codec-names",
  5484. dai_link[i].codecs[j].name);
  5485. if (index < 0)
  5486. continue;
  5487. np = of_parse_phandle(cdev->of_node,
  5488. "asoc-codec",
  5489. index);
  5490. if (!np) {
  5491. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  5492. __func__,
  5493. dai_link[i].codecs[j].name);
  5494. ret = -ENODEV;
  5495. goto err;
  5496. }
  5497. dai_link[i].codecs[j].of_node = np;
  5498. dai_link[i].codecs[j].name = NULL;
  5499. }
  5500. }
  5501. }
  5502. /* In multi-codec scenario, check if codecs are enabled for this platform */
  5503. for (i = 0; i < card->num_links; i++) {
  5504. codecs_enabled = 0;
  5505. if (dai_link[i].num_codecs > 1) {
  5506. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5507. if (!dai_link[i].codecs[j].of_node)
  5508. continue;
  5509. np = dai_link[i].codecs[j].of_node;
  5510. if (!of_device_is_available(np)) {
  5511. dev_err(cdev, "%s: codec is disabled: %s\n",
  5512. __func__,
  5513. np->full_name);
  5514. dai_link[i].codecs[j].of_node = NULL;
  5515. continue;
  5516. }
  5517. codecs_enabled++;
  5518. }
  5519. if (codecs_enabled > 0 &&
  5520. codecs_enabled < dai_link[i].num_codecs) {
  5521. codecs_comp = devm_kzalloc(cdev,
  5522. sizeof(struct snd_soc_dai_link_component)
  5523. * codecs_enabled, GFP_KERNEL);
  5524. if (!codecs_comp) {
  5525. dev_err(cdev, "%s: %s dailink codec component alloc failed\n",
  5526. __func__, dai_link[i].name);
  5527. ret = -ENOMEM;
  5528. goto err;
  5529. }
  5530. index = 0;
  5531. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5532. if (dai_link[i].codecs[j].of_node) {
  5533. codecs_comp[index].of_node =
  5534. dai_link[i].codecs[j].of_node;
  5535. codecs_comp[index].dai_name =
  5536. dai_link[i].codecs[j].dai_name;
  5537. codecs_comp[index].name = NULL;
  5538. index++;
  5539. }
  5540. }
  5541. dai_link[i].codecs = codecs_comp;
  5542. dai_link[i].num_codecs = codecs_enabled;
  5543. }
  5544. }
  5545. }
  5546. err:
  5547. return ret;
  5548. }
  5549. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5550. {
  5551. int ret = -EINVAL;
  5552. struct snd_soc_component *component =
  5553. snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5554. if (!component) {
  5555. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  5556. return ret;
  5557. }
  5558. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5559. ARRAY_SIZE(msm_snd_controls));
  5560. if (ret < 0) {
  5561. dev_err(component->dev,
  5562. "%s: add_codec_controls failed, err = %d\n",
  5563. __func__, ret);
  5564. return ret;
  5565. }
  5566. return ret;
  5567. }
  5568. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5569. struct snd_pcm_hw_params *params)
  5570. {
  5571. return 0;
  5572. }
  5573. static struct snd_soc_ops msm_stub_be_ops = {
  5574. .hw_params = msm_snd_stub_hw_params,
  5575. };
  5576. struct snd_soc_card snd_soc_card_stub_msm = {
  5577. .name = "holi-stub-snd-card",
  5578. };
  5579. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5580. /* FrontEnd DAI Links */
  5581. {
  5582. .name = "MSMSTUB Media1",
  5583. .stream_name = "MultiMedia1",
  5584. .dynamic = 1,
  5585. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5586. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5587. #endif /* CONFIG_AUDIO_QGKI */
  5588. .dpcm_playback = 1,
  5589. .dpcm_capture = 1,
  5590. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5591. SND_SOC_DPCM_TRIGGER_POST},
  5592. .ignore_suspend = 1,
  5593. /* this dainlink has playback support */
  5594. .ignore_pmdown_time = 1,
  5595. .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
  5596. SND_SOC_DAILINK_REG(multimedia1),
  5597. },
  5598. };
  5599. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5600. /* Backend DAI Links */
  5601. {
  5602. .name = LPASS_BE_AUXPCM_RX,
  5603. .stream_name = "AUX PCM Playback",
  5604. .no_pcm = 1,
  5605. .dpcm_playback = 1,
  5606. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5607. .init = &msm_audrx_stub_init,
  5608. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5609. .ignore_pmdown_time = 1,
  5610. .ignore_suspend = 1,
  5611. .ops = &msm_stub_be_ops,
  5612. SND_SOC_DAILINK_REG(auxpcm_rx),
  5613. },
  5614. {
  5615. .name = LPASS_BE_AUXPCM_TX,
  5616. .stream_name = "AUX PCM Capture",
  5617. .no_pcm = 1,
  5618. .dpcm_capture = 1,
  5619. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5620. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5621. .ignore_suspend = 1,
  5622. .ops = &msm_stub_be_ops,
  5623. SND_SOC_DAILINK_REG(auxpcm_tx),
  5624. },
  5625. };
  5626. static struct snd_soc_dai_link msm_stub_dai_links[
  5627. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5628. ARRAY_SIZE(msm_stub_be_dai_links)];
  5629. static const struct of_device_id holi_asoc_machine_of_match[] = {
  5630. { .compatible = "qcom,holi-asoc-snd",
  5631. .data = "codec"},
  5632. { .compatible = "qcom,holi-asoc-snd-stub",
  5633. .data = "stub_codec"},
  5634. {},
  5635. };
  5636. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5637. {
  5638. struct snd_soc_card *card = NULL;
  5639. struct snd_soc_dai_link *dailink = NULL;
  5640. int len_1 = 0;
  5641. int len_2 = 0;
  5642. int total_links = 0;
  5643. int rc = 0;
  5644. u32 mi2s_audio_intf = 0;
  5645. u32 auxpcm_audio_intf = 0;
  5646. u32 val = 0;
  5647. u32 wcn_btfm_intf = 0;
  5648. const struct of_device_id *match;
  5649. int is_wcd937x_codec = 1;
  5650. match = of_match_node(holi_asoc_machine_of_match, dev->of_node);
  5651. if (!match) {
  5652. dev_err(dev, "%s: No DT match found for sound card\n",
  5653. __func__);
  5654. return NULL;
  5655. }
  5656. rc = of_property_read_u32(dev->of_node,
  5657. "qcom,is-wcd937x-codec",
  5658. &is_wcd937x_codec);
  5659. if (rc) {
  5660. dev_dbg(dev, "%s: No DT match is-primary-codec\n",
  5661. __func__);
  5662. }
  5663. if (!strcmp(match->data, "codec")) {
  5664. card = &snd_soc_card_holi_msm;
  5665. memcpy(msm_holi_dai_links + total_links,
  5666. msm_common_dai_links,
  5667. sizeof(msm_common_dai_links));
  5668. total_links += ARRAY_SIZE(msm_common_dai_links);
  5669. memcpy(msm_holi_dai_links + total_links,
  5670. msm_common_misc_fe_dai_links,
  5671. sizeof(msm_common_misc_fe_dai_links));
  5672. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5673. memcpy(msm_holi_dai_links + total_links,
  5674. msm_common_be_dai_links,
  5675. sizeof(msm_common_be_dai_links));
  5676. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5677. if (is_wcd937x_codec) {
  5678. memcpy(msm_holi_dai_links + total_links,
  5679. msm_rx_tx_cdc937x_dma_be_dai_links,
  5680. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5681. } else {
  5682. memcpy(msm_holi_dai_links + total_links,
  5683. msm_rx_tx_cdc_dma_be_dai_links,
  5684. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5685. }
  5686. total_links +=
  5687. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  5688. memcpy(msm_holi_dai_links + total_links,
  5689. msm_va_cdc_dma_be_dai_links,
  5690. sizeof(msm_va_cdc_dma_be_dai_links));
  5691. total_links +=
  5692. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5693. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5694. &mi2s_audio_intf);
  5695. if (rc) {
  5696. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5697. __func__);
  5698. } else {
  5699. if (mi2s_audio_intf) {
  5700. memcpy(msm_holi_dai_links + total_links,
  5701. msm_mi2s_be_dai_links,
  5702. sizeof(msm_mi2s_be_dai_links));
  5703. total_links +=
  5704. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5705. }
  5706. }
  5707. rc = of_property_read_u32(dev->of_node,
  5708. "qcom,auxpcm-audio-intf",
  5709. &auxpcm_audio_intf);
  5710. if (rc) {
  5711. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5712. __func__);
  5713. } else {
  5714. if (auxpcm_audio_intf) {
  5715. memcpy(msm_holi_dai_links + total_links,
  5716. msm_auxpcm_be_dai_links,
  5717. sizeof(msm_auxpcm_be_dai_links));
  5718. total_links +=
  5719. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5720. }
  5721. }
  5722. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5723. &val);
  5724. if (!rc && val) {
  5725. memcpy(msm_holi_dai_links + total_links,
  5726. msm_afe_rxtx_lb_be_dai_link,
  5727. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5728. total_links +=
  5729. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5730. }
  5731. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  5732. &wcn_btfm_intf);
  5733. if (rc) {
  5734. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  5735. __func__);
  5736. } else {
  5737. if (wcn_btfm_intf) {
  5738. memcpy(msm_holi_dai_links + total_links,
  5739. msm_wcn_btfm_be_dai_links,
  5740. sizeof(msm_wcn_btfm_be_dai_links));
  5741. total_links +=
  5742. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  5743. }
  5744. }
  5745. dailink = msm_holi_dai_links;
  5746. } else if (!strcmp(match->data, "stub_codec")) {
  5747. card = &snd_soc_card_stub_msm;
  5748. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5749. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5750. memcpy(msm_stub_dai_links,
  5751. msm_stub_fe_dai_links,
  5752. sizeof(msm_stub_fe_dai_links));
  5753. memcpy(msm_stub_dai_links + len_1,
  5754. msm_stub_be_dai_links,
  5755. sizeof(msm_stub_be_dai_links));
  5756. dailink = msm_stub_dai_links;
  5757. total_links = len_2;
  5758. }
  5759. if (card) {
  5760. card->dai_link = dailink;
  5761. card->num_links = total_links;
  5762. }
  5763. return card;
  5764. }
  5765. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  5766. {
  5767. struct snd_soc_component *component = NULL;
  5768. struct snd_soc_dapm_context *dapm = NULL;
  5769. struct snd_card *card = NULL;
  5770. struct snd_info_entry *entry = NULL;
  5771. struct msm_asoc_mach_data *pdata =
  5772. snd_soc_card_get_drvdata(rtd->card);
  5773. int ret = 0;
  5774. component = snd_soc_rtdcom_lookup(rtd, "wsa-codec.1");
  5775. if (!component) {
  5776. pr_err("%s: wsa-codec.1 component is NULL\n", __func__);
  5777. return -EINVAL;
  5778. }
  5779. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5780. if (!component) {
  5781. pr_err("%s: could not find component for bolero_codec\n",
  5782. __func__);
  5783. return ret;
  5784. }
  5785. dapm = snd_soc_component_get_dapm(component);
  5786. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  5787. ARRAY_SIZE(msm_int_snd_controls));
  5788. if (ret < 0) {
  5789. pr_err("%s: add_component_controls failed: %d\n",
  5790. __func__, ret);
  5791. return ret;
  5792. }
  5793. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  5794. ARRAY_SIZE(msm_common_snd_controls));
  5795. if (ret < 0) {
  5796. pr_err("%s: add common snd controls failed: %d\n",
  5797. __func__, ret);
  5798. return ret;
  5799. }
  5800. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  5801. ARRAY_SIZE(msm_int_dapm_widgets));
  5802. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  5803. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  5804. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  5805. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  5806. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  5807. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  5808. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  5809. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  5810. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  5811. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  5812. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  5813. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  5814. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  5815. snd_soc_dapm_sync(dapm);
  5816. card = rtd->card->snd_card;
  5817. if (!pdata->codec_root) {
  5818. entry = msm_snd_info_create_subdir(card->module, "codecs",
  5819. card->proc_root);
  5820. if (!entry) {
  5821. pr_debug("%s: Cannot create codecs module entry\n",
  5822. __func__);
  5823. ret = 0;
  5824. goto err;
  5825. }
  5826. pdata->codec_root = entry;
  5827. }
  5828. bolero_info_create_codec_entry(pdata->codec_root, component);
  5829. bolero_register_wake_irq(component, false);
  5830. codec_reg_done = true;
  5831. err:
  5832. return ret;
  5833. }
  5834. static int msm_aux_codec_init(struct snd_soc_pcm_runtime *rtd)
  5835. {
  5836. struct snd_soc_component *bolero_component = NULL;
  5837. struct snd_soc_component *component = NULL;
  5838. struct snd_soc_dapm_context *dapm = NULL;
  5839. int ret = 0;
  5840. int codec_variant = -1;
  5841. void *mbhc_calibration;
  5842. struct snd_info_entry *entry;
  5843. struct snd_card *card = NULL;
  5844. struct msm_asoc_mach_data *pdata;
  5845. bolero_component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5846. if (!bolero_component) {
  5847. pr_err("%s: could not find component for bolero_codec\n",
  5848. __func__);
  5849. return -EINVAL;
  5850. }
  5851. component = snd_soc_rtdcom_lookup(rtd, WCD938X_DRV_NAME);
  5852. if (!component) {
  5853. component = snd_soc_rtdcom_lookup(rtd, WCD937X_DRV_NAME);
  5854. }
  5855. if (!component) {
  5856. pr_err("%s component is NULL\n", __func__);
  5857. return -EINVAL;
  5858. }
  5859. dapm = snd_soc_component_get_dapm(component);
  5860. card = component->card->snd_card;
  5861. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5862. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5863. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5864. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5865. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5866. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5867. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5868. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5869. snd_soc_dapm_sync(dapm);
  5870. pdata = snd_soc_card_get_drvdata(component->card);
  5871. if (!pdata->codec_root) {
  5872. entry = msm_snd_info_create_subdir(card->module, "codecs",
  5873. card->proc_root);
  5874. if (!entry) {
  5875. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5876. __func__);
  5877. ret = 0;
  5878. goto mbhc_cfg_cal;
  5879. }
  5880. pdata->codec_root = entry;
  5881. }
  5882. if (!strncmp(component->driver->name, WCD937X_DRV_NAME, 13)) {
  5883. wcd937x_info_create_codec_entry(pdata->codec_root, component);
  5884. ret = snd_soc_add_component_controls(component,
  5885. msm_int_wcd937x_snd_controls,
  5886. ARRAY_SIZE(msm_int_wcd937x_snd_controls));
  5887. bolero_set_port_map(bolero_component,
  5888. ARRAY_SIZE(sm_port_map_wcd937x), sm_port_map_wcd937x);
  5889. } else if (!strncmp(component->driver->name, WCD938X_DRV_NAME, 13)) {
  5890. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  5891. codec_variant = wcd938x_get_codec_variant(component);
  5892. dev_dbg(component->dev, "%s: variant %d\n",
  5893. __func__, codec_variant);
  5894. if (codec_variant == WCD9380)
  5895. ret = snd_soc_add_component_controls(component,
  5896. msm_int_wcd9380_snd_controls,
  5897. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  5898. else if (codec_variant == WCD9385)
  5899. ret = snd_soc_add_component_controls(component,
  5900. msm_int_wcd9385_snd_controls,
  5901. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  5902. bolero_set_port_map(bolero_component, ARRAY_SIZE(sm_port_map),
  5903. sm_port_map);
  5904. } else {
  5905. bolero_set_port_map(bolero_component, ARRAY_SIZE(sm_port_map),
  5906. sm_port_map);
  5907. }
  5908. if (ret < 0) {
  5909. dev_err(component->dev,
  5910. "%s: add codec specific snd controls failed: %d\n",
  5911. __func__, ret);
  5912. return ret;
  5913. }
  5914. mbhc_cfg_cal:
  5915. mbhc_calibration = def_wcd_mbhc_cal();
  5916. if (!mbhc_calibration)
  5917. return -ENOMEM;
  5918. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5919. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5920. if (ret) {
  5921. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5922. __func__, ret);
  5923. goto err_hs_detect;
  5924. }
  5925. return 0;
  5926. err_hs_detect:
  5927. kfree(mbhc_calibration);
  5928. return ret;
  5929. }
  5930. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5931. {
  5932. int count = 0;
  5933. u32 mi2s_master_slave[MI2S_MAX];
  5934. int ret = 0;
  5935. for (count = 0; count < MI2S_MAX; count++) {
  5936. mutex_init(&mi2s_intf_conf[count].lock);
  5937. mi2s_intf_conf[count].ref_cnt = 0;
  5938. }
  5939. ret = of_property_read_u32_array(pdev->dev.of_node,
  5940. "qcom,msm-mi2s-master",
  5941. mi2s_master_slave, MI2S_MAX);
  5942. if (ret) {
  5943. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5944. __func__);
  5945. } else {
  5946. for (count = 0; count < MI2S_MAX; count++) {
  5947. mi2s_intf_conf[count].msm_is_mi2s_master =
  5948. mi2s_master_slave[count];
  5949. }
  5950. }
  5951. }
  5952. static void msm_i2s_auxpcm_deinit(void)
  5953. {
  5954. int count = 0;
  5955. for (count = 0; count < MI2S_MAX; count++) {
  5956. mutex_destroy(&mi2s_intf_conf[count].lock);
  5957. mi2s_intf_conf[count].ref_cnt = 0;
  5958. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5959. }
  5960. }
  5961. static int holi_ssr_enable(struct device *dev, void *data)
  5962. {
  5963. struct platform_device *pdev = to_platform_device(dev);
  5964. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5965. int ret = 0;
  5966. if (!card) {
  5967. dev_err(dev, "%s: card is NULL\n", __func__);
  5968. ret = -EINVAL;
  5969. goto err;
  5970. }
  5971. if (!strcmp(card->name, "holi-stub-snd-card")) {
  5972. /* TODO */
  5973. dev_dbg(dev, "%s: TODO \n", __func__);
  5974. }
  5975. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5976. snd_soc_card_change_online_state(card, 1);
  5977. #endif /* CONFIG_AUDIO_QGKI */
  5978. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5979. err:
  5980. return ret;
  5981. }
  5982. static void holi_ssr_disable(struct device *dev, void *data)
  5983. {
  5984. struct platform_device *pdev = to_platform_device(dev);
  5985. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5986. if (!card) {
  5987. dev_err(dev, "%s: card is NULL\n", __func__);
  5988. return;
  5989. }
  5990. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5991. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5992. snd_soc_card_change_online_state(card, 0);
  5993. #endif /* CONFIG_AUDIO_QGKI */
  5994. if (!strcmp(card->name, "holi-stub-snd-card")) {
  5995. /* TODO */
  5996. dev_dbg(dev, "%s: TODO \n", __func__);
  5997. }
  5998. }
  5999. static const struct snd_event_ops holi_ssr_ops = {
  6000. .enable = holi_ssr_enable,
  6001. .disable = holi_ssr_disable,
  6002. };
  6003. static int msm_audio_ssr_compare(struct device *dev, void *data)
  6004. {
  6005. struct device_node *node = data;
  6006. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  6007. __func__, dev->of_node, node);
  6008. return (dev->of_node && dev->of_node == node);
  6009. }
  6010. static int msm_audio_ssr_register(struct device *dev)
  6011. {
  6012. struct device_node *np = dev->of_node;
  6013. struct snd_event_clients *ssr_clients = NULL;
  6014. struct device_node *node = NULL;
  6015. int ret = 0;
  6016. int i = 0;
  6017. for (i = 0; ; i++) {
  6018. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  6019. if (!node)
  6020. break;
  6021. snd_event_mstr_add_client(&ssr_clients,
  6022. msm_audio_ssr_compare, node);
  6023. }
  6024. ret = snd_event_master_register(dev, &holi_ssr_ops,
  6025. ssr_clients, NULL);
  6026. if (!ret)
  6027. snd_event_notify(dev, SND_EVENT_UP);
  6028. return ret;
  6029. }
  6030. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6031. {
  6032. struct snd_soc_card *card = NULL;
  6033. struct msm_asoc_mach_data *pdata = NULL;
  6034. const char *mbhc_audio_jack_type = NULL;
  6035. int ret = 0;
  6036. uint index = 0;
  6037. struct clk *lpass_audio_hw_vote = NULL;
  6038. if (!pdev->dev.of_node) {
  6039. dev_err(&pdev->dev,
  6040. "%s: No platform supplied from device tree\n", __func__);
  6041. return -EINVAL;
  6042. }
  6043. pdata = devm_kzalloc(&pdev->dev,
  6044. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6045. if (!pdata)
  6046. return -ENOMEM;
  6047. card = populate_snd_card_dailinks(&pdev->dev);
  6048. if (!card) {
  6049. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6050. ret = -EINVAL;
  6051. goto err;
  6052. }
  6053. card->dev = &pdev->dev;
  6054. platform_set_drvdata(pdev, card);
  6055. snd_soc_card_set_drvdata(card, pdata);
  6056. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6057. if (ret) {
  6058. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  6059. __func__, ret);
  6060. goto err;
  6061. }
  6062. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6063. if (ret) {
  6064. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  6065. __func__, ret);
  6066. goto err;
  6067. }
  6068. ret = msm_populate_dai_link_component_of_node(card);
  6069. if (ret) {
  6070. ret = -EPROBE_DEFER;
  6071. goto err;
  6072. }
  6073. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6074. if (ret == -EPROBE_DEFER) {
  6075. if (codec_reg_done)
  6076. ret = -EINVAL;
  6077. goto err;
  6078. } else if (ret) {
  6079. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  6080. __func__, ret);
  6081. goto err;
  6082. }
  6083. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  6084. __func__, card->name);
  6085. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6086. "qcom,hph-en1-gpio", 0);
  6087. if (!pdata->hph_en1_gpio_p) {
  6088. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6089. __func__, "qcom,hph-en1-gpio",
  6090. pdev->dev.of_node->full_name);
  6091. }
  6092. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6093. "qcom,hph-en0-gpio", 0);
  6094. if (!pdata->hph_en0_gpio_p) {
  6095. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6096. __func__, "qcom,hph-en0-gpio",
  6097. pdev->dev.of_node->full_name);
  6098. }
  6099. ret = of_property_read_string(pdev->dev.of_node,
  6100. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6101. if (ret) {
  6102. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6103. __func__, "qcom,mbhc-audio-jack-type",
  6104. pdev->dev.of_node->full_name);
  6105. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6106. } else {
  6107. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6108. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6109. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6110. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6111. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6112. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6113. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6114. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6115. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6116. } else {
  6117. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6118. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6119. }
  6120. }
  6121. /*
  6122. * Parse US-Euro gpio info from DT. Report no error if us-euro
  6123. * entry is not found in DT file as some targets do not support
  6124. * US-Euro detection
  6125. */
  6126. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6127. "qcom,us-euro-gpios", 0);
  6128. if (!pdata->us_euro_gpio_p) {
  6129. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  6130. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  6131. } else {
  6132. dev_dbg(&pdev->dev, "%s detected\n",
  6133. "qcom,us-euro-gpios");
  6134. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  6135. }
  6136. if (wcd_mbhc_cfg.enable_usbc_analog)
  6137. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  6138. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  6139. "fsa4480-i2c-handle", 0);
  6140. if (!pdata->fsa_handle)
  6141. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  6142. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  6143. msm_i2s_auxpcm_init(pdev);
  6144. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6145. "qcom,cdc-dmic01-gpios",
  6146. 0);
  6147. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6148. "qcom,cdc-dmic23-gpios",
  6149. 0);
  6150. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6151. "qcom,cdc-dmic45-gpios",
  6152. 0);
  6153. if (pdata->dmic01_gpio_p)
  6154. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  6155. if (pdata->dmic23_gpio_p)
  6156. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  6157. if (pdata->dmic45_gpio_p)
  6158. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  6159. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6160. "qcom,pri-mi2s-gpios", 0);
  6161. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6162. "qcom,sec-mi2s-gpios", 0);
  6163. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6164. "qcom,tert-mi2s-gpios", 0);
  6165. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6166. "qcom,quat-mi2s-gpios", 0);
  6167. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  6168. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  6169. /* Register LPASS audio hw vote */
  6170. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  6171. if (IS_ERR(lpass_audio_hw_vote)) {
  6172. ret = PTR_ERR(lpass_audio_hw_vote);
  6173. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  6174. __func__, "lpass_audio_hw_vote", ret);
  6175. lpass_audio_hw_vote = NULL;
  6176. ret = 0;
  6177. }
  6178. pdata->lpass_audio_hw_vote = lpass_audio_hw_vote;
  6179. pdata->core_audio_vote_count = 0;
  6180. ret = msm_audio_ssr_register(&pdev->dev);
  6181. if (ret)
  6182. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  6183. __func__, ret);
  6184. is_initial_boot = true;
  6185. return 0;
  6186. err:
  6187. devm_kfree(&pdev->dev, pdata);
  6188. return ret;
  6189. }
  6190. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6191. {
  6192. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6193. snd_event_master_deregister(&pdev->dev);
  6194. snd_soc_unregister_card(card);
  6195. msm_i2s_auxpcm_deinit();
  6196. return 0;
  6197. }
  6198. static struct platform_driver holi_asoc_machine_driver = {
  6199. .driver = {
  6200. .name = DRV_NAME,
  6201. .owner = THIS_MODULE,
  6202. .pm = &snd_soc_pm_ops,
  6203. .of_match_table = holi_asoc_machine_of_match,
  6204. .suppress_bind_attrs = true,
  6205. },
  6206. .probe = msm_asoc_machine_probe,
  6207. .remove = msm_asoc_machine_remove,
  6208. };
  6209. module_platform_driver(holi_asoc_machine_driver);
  6210. MODULE_DESCRIPTION("ALSA SoC msm");
  6211. MODULE_LICENSE("GPL v2");
  6212. MODULE_ALIAS("platform:" DRV_NAME);
  6213. MODULE_DEVICE_TABLE(of, holi_asoc_machine_of_match);