wcd937x.c 95 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #define WCD9370_VARIANT 0
  27. #define WCD9375_VARIANT 5
  28. #define WCD937X_VARIANT_ENTRY_SIZE 32
  29. #define NUM_SWRS_DT_PARAMS 5
  30. #define WCD937X_VERSION_1_0 1
  31. #define WCD937X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. #define NUM_ATTEMPTS 5
  34. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  35. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  36. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  37. SNDRV_PCM_RATE_384000)
  38. /* Fractional Rates */
  39. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  40. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  41. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  42. SNDRV_PCM_FMTBIT_S24_LE |\
  43. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  44. enum {
  45. CODEC_TX = 0,
  46. CODEC_RX,
  47. };
  48. enum {
  49. ALLOW_BUCK_DISABLE,
  50. HPH_COMP_DELAY,
  51. HPH_PA_DELAY,
  52. AMIC2_BCS_ENABLE,
  53. };
  54. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  55. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  56. static int wcd937x_handle_post_irq(void *data);
  57. static int wcd937x_reset(struct device *dev);
  58. static int wcd937x_reset_low(struct device *dev);
  59. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  60. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  80. };
  81. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  82. .name = "wcd937x",
  83. .irqs = wcd937x_irqs,
  84. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  85. .num_regs = 3,
  86. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  87. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  88. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  89. .use_ack = 1,
  90. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  91. .runtime_pm = false,
  92. .handle_post_irq = wcd937x_handle_post_irq,
  93. .irq_drv_data = NULL,
  94. };
  95. static struct snd_soc_dai_driver wcd937x_dai[] = {
  96. {
  97. .name = "wcd937x_cdc",
  98. .playback = {
  99. .stream_name = "WCD937X_AIF Playback",
  100. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  101. .formats = WCD937X_FORMATS,
  102. .rate_max = 384000,
  103. .rate_min = 8000,
  104. .channels_min = 1,
  105. .channels_max = 4,
  106. },
  107. .capture = {
  108. .stream_name = "WCD937X_AIF Capture",
  109. .rates = WCD937X_RATES,
  110. .formats = WCD937X_FORMATS,
  111. .rate_max = 192000,
  112. .rate_min = 8000,
  113. .channels_min = 1,
  114. .channels_max = 4,
  115. },
  116. },
  117. };
  118. static int wcd937x_handle_post_irq(void *data)
  119. {
  120. struct wcd937x_priv *wcd937x = data;
  121. u32 status1 = 0, status2 = 0, status3 = 0;
  122. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  123. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  124. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  125. wcd937x->tx_swr_dev->slave_irq_pending =
  126. ((status1 || status2 || status3) ? true : false);
  127. return IRQ_HANDLED;
  128. }
  129. static int wcd937x_init_reg(struct snd_soc_component *component)
  130. {
  131. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  132. 0x0E, 0x0E);
  133. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  134. 0x80, 0x80);
  135. usleep_range(1000, 1010);
  136. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  137. 0x40, 0x40);
  138. usleep_range(1000, 1010);
  139. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  140. 0x10, 0x00);
  141. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  142. 0xF0, 0x80);
  143. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  144. 0x80, 0x80);
  145. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  146. 0x40, 0x40);
  147. usleep_range(10000, 10010);
  148. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  149. 0x40, 0x00);
  150. snd_soc_component_update_bits(component,
  151. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  152. 0xFF, 0xD9);
  153. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  154. 0xFF, 0xFA);
  155. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  156. 0xFF, 0xFA);
  157. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  158. 0xFF, 0xFA);
  159. return 0;
  160. }
  161. static int wcd937x_set_port_params(struct snd_soc_component *component,
  162. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  163. u8 *ch_mask, u32 *ch_rate,
  164. u8 *port_type, u8 path)
  165. {
  166. int i, j;
  167. u8 num_ports = 0;
  168. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  169. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  170. switch (path) {
  171. case CODEC_RX:
  172. map = &wcd937x->rx_port_mapping;
  173. num_ports = wcd937x->num_rx_ports;
  174. break;
  175. case CODEC_TX:
  176. map = &wcd937x->tx_port_mapping;
  177. num_ports = wcd937x->num_tx_ports;
  178. break;
  179. default:
  180. dev_err(component->dev, "%s Invalid path selected %u\n",
  181. __func__, path);
  182. return -EINVAL;
  183. }
  184. for (i = 0; i <= num_ports; i++) {
  185. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  186. if ((*map)[i][j].slave_port_type == slv_prt_type)
  187. goto found;
  188. }
  189. }
  190. found:
  191. if (i > num_ports || j == MAX_CH_PER_PORT) {
  192. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  193. __func__, slv_prt_type);
  194. return -EINVAL;
  195. }
  196. *port_id = i;
  197. *num_ch = (*map)[i][j].num_ch;
  198. *ch_mask = (*map)[i][j].ch_mask;
  199. *ch_rate = (*map)[i][j].ch_rate;
  200. *port_type = (*map)[i][j].master_port_type;
  201. return 0;
  202. }
  203. static int wcd937x_parse_port_mapping(struct device *dev,
  204. char *prop, u8 path)
  205. {
  206. u32 *dt_array, map_size, map_length;
  207. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  208. u32 slave_port_type, master_port_type;
  209. u32 i, ch_iter = 0;
  210. int ret = 0;
  211. u8 *num_ports = NULL;
  212. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  213. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  214. switch (path) {
  215. case CODEC_RX:
  216. map = &wcd937x->rx_port_mapping;
  217. num_ports = &wcd937x->num_rx_ports;
  218. break;
  219. case CODEC_TX:
  220. map = &wcd937x->tx_port_mapping;
  221. num_ports = &wcd937x->num_tx_ports;
  222. break;
  223. default:
  224. dev_err(dev, "%s Invalid path selected %u\n",
  225. __func__, path);
  226. return -EINVAL;
  227. }
  228. if (!of_find_property(dev->of_node, prop,
  229. &map_size)) {
  230. dev_err(dev, "missing port mapping prop %s\n", prop);
  231. ret = -EINVAL;
  232. goto err;
  233. }
  234. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  235. dt_array = kzalloc(map_size, GFP_KERNEL);
  236. if (!dt_array) {
  237. ret = -ENOMEM;
  238. goto err;
  239. }
  240. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  241. NUM_SWRS_DT_PARAMS * map_length);
  242. if (ret) {
  243. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  244. __func__, prop);
  245. ret = -EINVAL;
  246. goto err_pdata_fail;
  247. }
  248. for (i = 0; i < map_length; i++) {
  249. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  250. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  251. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  252. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  253. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  254. if (port_num != old_port_num)
  255. ch_iter = 0;
  256. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  257. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  258. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  259. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  260. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  261. old_port_num = port_num;
  262. }
  263. *num_ports = port_num;
  264. kfree(dt_array);
  265. return 0;
  266. err_pdata_fail:
  267. kfree(dt_array);
  268. err:
  269. return ret;
  270. }
  271. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  272. u8 slv_port_type, u8 enable)
  273. {
  274. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  275. u8 port_id;
  276. u8 num_ch;
  277. u8 ch_mask;
  278. u32 ch_rate;
  279. u8 ch_type = 0;
  280. int slave_ch_idx;
  281. u8 num_port = 1;
  282. int ret = 0;
  283. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  284. &num_ch, &ch_mask, &ch_rate,
  285. &ch_type, CODEC_TX);
  286. if (ret)
  287. return ret;
  288. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  289. if (slave_ch_idx != -EINVAL)
  290. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  291. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  292. __func__, slave_ch_idx, ch_type);
  293. if (enable)
  294. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  295. num_port, &ch_mask, &ch_rate,
  296. &num_ch, &ch_type);
  297. else
  298. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  299. num_port, &ch_mask, &ch_type);
  300. return ret;
  301. }
  302. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  303. u8 slv_port_type, u8 enable)
  304. {
  305. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  306. u8 port_id;
  307. u8 num_ch;
  308. u8 ch_mask;
  309. u32 ch_rate;
  310. u8 port_type;
  311. u8 num_port = 1;
  312. int ret = 0;
  313. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  314. &num_ch, &ch_mask, &ch_rate,
  315. &port_type, CODEC_RX);
  316. if (ret)
  317. return ret;
  318. if (enable)
  319. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  320. num_port, &ch_mask, &ch_rate,
  321. &num_ch, &port_type);
  322. else
  323. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  324. num_port, &ch_mask, &port_type);
  325. return ret;
  326. }
  327. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  328. {
  329. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  330. if (wcd937x->rx_clk_cnt == 0) {
  331. snd_soc_component_update_bits(component,
  332. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  333. snd_soc_component_update_bits(component,
  334. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  335. snd_soc_component_update_bits(component,
  336. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  337. snd_soc_component_update_bits(component,
  338. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  339. snd_soc_component_update_bits(component,
  340. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  341. snd_soc_component_update_bits(component,
  342. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  343. snd_soc_component_update_bits(component,
  344. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  345. }
  346. wcd937x->rx_clk_cnt++;
  347. return 0;
  348. }
  349. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  350. {
  351. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  352. if (wcd937x->rx_clk_cnt == 0) {
  353. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  354. return 0;
  355. }
  356. wcd937x->rx_clk_cnt--;
  357. if (wcd937x->rx_clk_cnt == 0) {
  358. snd_soc_component_update_bits(component,
  359. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  360. snd_soc_component_update_bits(component,
  361. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  362. 0x02, 0x00);
  363. snd_soc_component_update_bits(component,
  364. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  365. 0x01, 0x00);
  366. }
  367. return 0;
  368. }
  369. /*
  370. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  371. * @component: handle to snd_soc_component *
  372. *
  373. * return wcd937x_mbhc handle or error code in case of failure
  374. */
  375. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  376. {
  377. struct wcd937x_priv *wcd937x;
  378. if (!component) {
  379. pr_err("%s: Invalid params, NULL component\n", __func__);
  380. return NULL;
  381. }
  382. wcd937x = snd_soc_component_get_drvdata(component);
  383. if (!wcd937x) {
  384. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  385. return NULL;
  386. }
  387. return wcd937x->mbhc;
  388. }
  389. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  390. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  391. struct snd_kcontrol *kcontrol,
  392. int event)
  393. {
  394. struct snd_soc_component *component =
  395. snd_soc_dapm_to_component(w->dapm);
  396. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  397. int hph_mode = wcd937x->hph_mode;
  398. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  399. w->name, event);
  400. switch (event) {
  401. case SND_SOC_DAPM_PRE_PMU:
  402. wcd937x_rx_clk_enable(component);
  403. snd_soc_component_update_bits(component,
  404. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  405. 0x01, 0x01);
  406. snd_soc_component_update_bits(component,
  407. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  408. 0x04, 0x04);
  409. snd_soc_component_update_bits(component,
  410. WCD937X_HPH_RDAC_CLK_CTL1,
  411. 0x80, 0x00);
  412. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  413. break;
  414. case SND_SOC_DAPM_POST_PMU:
  415. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  416. snd_soc_component_update_bits(component,
  417. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  418. 0x0F, 0x02);
  419. else if (hph_mode == CLS_H_LOHIFI)
  420. snd_soc_component_update_bits(component,
  421. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  422. 0x0F, 0x06);
  423. if (wcd937x->comp1_enable) {
  424. snd_soc_component_update_bits(component,
  425. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  426. 0x02, 0x02);
  427. snd_soc_component_update_bits(component,
  428. WCD937X_HPH_L_EN, 0x20, 0x00);
  429. if (wcd937x->comp2_enable) {
  430. snd_soc_component_update_bits(component,
  431. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  432. 0x01, 0x01);
  433. snd_soc_component_update_bits(component,
  434. WCD937X_HPH_R_EN, 0x20, 0x00);
  435. }
  436. /*
  437. * 5ms sleep is required after COMP is enabled as per
  438. * HW requirement
  439. */
  440. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  441. usleep_range(5000, 5100);
  442. clear_bit(HPH_COMP_DELAY,
  443. &wcd937x->status_mask);
  444. }
  445. } else {
  446. snd_soc_component_update_bits(component,
  447. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  448. 0x02, 0x00);
  449. snd_soc_component_update_bits(component,
  450. WCD937X_HPH_L_EN, 0x20, 0x20);
  451. }
  452. snd_soc_component_update_bits(component,
  453. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  454. break;
  455. case SND_SOC_DAPM_POST_PMD:
  456. snd_soc_component_update_bits(component,
  457. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  458. 0x0F, 0x01);
  459. break;
  460. }
  461. return 0;
  462. }
  463. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  464. struct snd_kcontrol *kcontrol,
  465. int event)
  466. {
  467. struct snd_soc_component *component =
  468. snd_soc_dapm_to_component(w->dapm);
  469. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  470. int hph_mode = wcd937x->hph_mode;
  471. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  472. w->name, event);
  473. switch (event) {
  474. case SND_SOC_DAPM_PRE_PMU:
  475. wcd937x_rx_clk_enable(component);
  476. snd_soc_component_update_bits(component,
  477. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  478. snd_soc_component_update_bits(component,
  479. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  480. snd_soc_component_update_bits(component,
  481. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  482. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  483. break;
  484. case SND_SOC_DAPM_POST_PMU:
  485. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  486. snd_soc_component_update_bits(component,
  487. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  488. 0x0F, 0x02);
  489. else if (hph_mode == CLS_H_LOHIFI)
  490. snd_soc_component_update_bits(component,
  491. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  492. 0x0F, 0x06);
  493. if (wcd937x->comp2_enable) {
  494. snd_soc_component_update_bits(component,
  495. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  496. 0x01, 0x01);
  497. snd_soc_component_update_bits(component,
  498. WCD937X_HPH_R_EN, 0x20, 0x00);
  499. if (wcd937x->comp1_enable) {
  500. snd_soc_component_update_bits(component,
  501. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  502. 0x02, 0x02);
  503. snd_soc_component_update_bits(component,
  504. WCD937X_HPH_L_EN, 0x20, 0x00);
  505. }
  506. /*
  507. * 5ms sleep is required after COMP is enabled as per
  508. * HW requirement
  509. */
  510. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  511. usleep_range(5000, 5100);
  512. clear_bit(HPH_COMP_DELAY,
  513. &wcd937x->status_mask);
  514. }
  515. } else {
  516. snd_soc_component_update_bits(component,
  517. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  518. 0x01, 0x00);
  519. snd_soc_component_update_bits(component,
  520. WCD937X_HPH_R_EN, 0x20, 0x20);
  521. }
  522. snd_soc_component_update_bits(component,
  523. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  524. break;
  525. case SND_SOC_DAPM_POST_PMD:
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  528. 0x0F, 0x01);
  529. break;
  530. }
  531. return 0;
  532. }
  533. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  534. struct snd_kcontrol *kcontrol,
  535. int event)
  536. {
  537. struct snd_soc_component *component =
  538. snd_soc_dapm_to_component(w->dapm);
  539. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  540. int hph_mode = wcd937x->hph_mode;
  541. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  542. w->name, event);
  543. switch (event) {
  544. case SND_SOC_DAPM_PRE_PMU:
  545. wcd937x_rx_clk_enable(component);
  546. snd_soc_component_update_bits(component,
  547. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  548. 0x04, 0x04);
  549. snd_soc_component_update_bits(component,
  550. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  551. 0x01, 0x01);
  552. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  553. snd_soc_component_update_bits(component,
  554. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  555. 0x0F, 0x02);
  556. else if (hph_mode == CLS_H_LOHIFI)
  557. snd_soc_component_update_bits(component,
  558. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  559. 0x0F, 0x06);
  560. if (wcd937x->comp1_enable)
  561. snd_soc_component_update_bits(component,
  562. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  563. 0x02, 0x02);
  564. usleep_range(5000, 5010);
  565. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  566. 0x04, 0x00);
  567. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  568. WCD_CLSH_EVENT_PRE_DAC,
  569. WCD_CLSH_STATE_EAR,
  570. hph_mode);
  571. break;
  572. case SND_SOC_DAPM_POST_PMD:
  573. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  574. hph_mode == CLS_H_HIFI)
  575. snd_soc_component_update_bits(component,
  576. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  577. 0x0F, 0x01);
  578. if (wcd937x->comp1_enable)
  579. snd_soc_component_update_bits(component,
  580. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  581. 0x02, 0x00);
  582. break;
  583. };
  584. return 0;
  585. }
  586. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  587. struct snd_kcontrol *kcontrol,
  588. int event)
  589. {
  590. struct snd_soc_component *component =
  591. snd_soc_dapm_to_component(w->dapm);
  592. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  593. int hph_mode = wcd937x->hph_mode;
  594. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  595. w->name, event);
  596. switch (event) {
  597. case SND_SOC_DAPM_PRE_PMU:
  598. wcd937x_rx_clk_enable(component);
  599. snd_soc_component_update_bits(component,
  600. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  601. 0x04, 0x04);
  602. snd_soc_component_update_bits(component,
  603. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  604. 0x04, 0x04);
  605. snd_soc_component_update_bits(component,
  606. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  607. 0x01, 0x01);
  608. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  609. WCD_CLSH_EVENT_PRE_DAC,
  610. WCD_CLSH_STATE_AUX,
  611. hph_mode);
  612. break;
  613. case SND_SOC_DAPM_POST_PMD:
  614. snd_soc_component_update_bits(component,
  615. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  616. 0x04, 0x00);
  617. break;
  618. };
  619. return 0;
  620. }
  621. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  622. struct snd_kcontrol *kcontrol,
  623. int event)
  624. {
  625. struct snd_soc_component *component =
  626. snd_soc_dapm_to_component(w->dapm);
  627. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  628. int ret = 0;
  629. int hph_mode = wcd937x->hph_mode;
  630. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  631. w->name, event);
  632. switch (event) {
  633. case SND_SOC_DAPM_PRE_PMU:
  634. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  635. wcd937x->rx_swr_dev->dev_num,
  636. true);
  637. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  638. WCD_CLSH_EVENT_PRE_DAC,
  639. WCD_CLSH_STATE_HPHR,
  640. hph_mode);
  641. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  642. 0x10, 0x10);
  643. usleep_range(100, 110);
  644. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  645. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  646. wcd937x->rx_swr_dev->dev_num,
  647. true);
  648. snd_soc_component_update_bits(component,
  649. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  650. break;
  651. case SND_SOC_DAPM_POST_PMU:
  652. /*
  653. * 7ms sleep is required after PA is enabled as per
  654. * HW requirement. If compander is disabled, then
  655. * 20ms delay is required.
  656. */
  657. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  658. if (!wcd937x->comp2_enable)
  659. usleep_range(20000, 20100);
  660. else
  661. usleep_range(7000, 7100);
  662. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  663. }
  664. snd_soc_component_update_bits(component,
  665. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  666. 0x02, 0x02);
  667. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  668. snd_soc_component_update_bits(component,
  669. WCD937X_ANA_RX_SUPPLIES,
  670. 0x02, 0x02);
  671. if (wcd937x->update_wcd_event)
  672. wcd937x->update_wcd_event(wcd937x->handle,
  673. WCD_BOLERO_EVT_RX_MUTE,
  674. (WCD_RX2 << 0x10));
  675. wcd_enable_irq(&wcd937x->irq_info,
  676. WCD937X_IRQ_HPHR_PDM_WD_INT);
  677. break;
  678. case SND_SOC_DAPM_PRE_PMD:
  679. wcd_disable_irq(&wcd937x->irq_info,
  680. WCD937X_IRQ_HPHR_PDM_WD_INT);
  681. if (wcd937x->update_wcd_event)
  682. wcd937x->update_wcd_event(wcd937x->handle,
  683. WCD_BOLERO_EVT_RX_MUTE,
  684. (WCD_RX2 << 0x10 | 0x1));
  685. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  686. WCD_EVENT_PRE_HPHR_PA_OFF,
  687. &wcd937x->mbhc->wcd_mbhc);
  688. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  689. break;
  690. case SND_SOC_DAPM_POST_PMD:
  691. /*
  692. * 7ms sleep is required after PA is disabled as per
  693. * HW requirement. If compander is disabled, then
  694. * 20ms delay is required.
  695. */
  696. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  697. if (!wcd937x->comp2_enable)
  698. usleep_range(20000, 20100);
  699. else
  700. usleep_range(7000, 7100);
  701. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  702. }
  703. snd_soc_component_update_bits(component,
  704. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  705. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  706. WCD_EVENT_POST_HPHR_PA_OFF,
  707. &wcd937x->mbhc->wcd_mbhc);
  708. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  709. 0x10, 0x00);
  710. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  711. WCD_CLSH_EVENT_POST_PA,
  712. WCD_CLSH_STATE_HPHR,
  713. hph_mode);
  714. break;
  715. };
  716. return ret;
  717. }
  718. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  719. struct snd_kcontrol *kcontrol,
  720. int event)
  721. {
  722. struct snd_soc_component *component =
  723. snd_soc_dapm_to_component(w->dapm);
  724. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  725. int ret = 0;
  726. int hph_mode = wcd937x->hph_mode;
  727. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  728. w->name, event);
  729. switch (event) {
  730. case SND_SOC_DAPM_PRE_PMU:
  731. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  732. wcd937x->rx_swr_dev->dev_num,
  733. true);
  734. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  735. WCD_CLSH_EVENT_PRE_DAC,
  736. WCD_CLSH_STATE_HPHL,
  737. hph_mode);
  738. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  739. 0x20, 0x20);
  740. usleep_range(100, 110);
  741. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  742. snd_soc_component_update_bits(component,
  743. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  744. break;
  745. case SND_SOC_DAPM_POST_PMU:
  746. /*
  747. * 7ms sleep is required after PA is enabled as per
  748. * HW requirement. If compander is disabled, then
  749. * 20ms delay is required.
  750. */
  751. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  752. if (!wcd937x->comp1_enable)
  753. usleep_range(20000, 20100);
  754. else
  755. usleep_range(7000, 7100);
  756. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  757. }
  758. snd_soc_component_update_bits(component,
  759. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  760. 0x02, 0x02);
  761. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  762. snd_soc_component_update_bits(component,
  763. WCD937X_ANA_RX_SUPPLIES,
  764. 0x02, 0x02);
  765. if (wcd937x->update_wcd_event)
  766. wcd937x->update_wcd_event(wcd937x->handle,
  767. WCD_BOLERO_EVT_RX_MUTE,
  768. (WCD_RX1 << 0x10));
  769. wcd_enable_irq(&wcd937x->irq_info,
  770. WCD937X_IRQ_HPHL_PDM_WD_INT);
  771. break;
  772. case SND_SOC_DAPM_PRE_PMD:
  773. wcd_disable_irq(&wcd937x->irq_info,
  774. WCD937X_IRQ_HPHL_PDM_WD_INT);
  775. if (wcd937x->update_wcd_event)
  776. wcd937x->update_wcd_event(wcd937x->handle,
  777. WCD_BOLERO_EVT_RX_MUTE,
  778. (WCD_RX1 << 0x10 | 0x1));
  779. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  780. WCD_EVENT_PRE_HPHL_PA_OFF,
  781. &wcd937x->mbhc->wcd_mbhc);
  782. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  783. break;
  784. case SND_SOC_DAPM_POST_PMD:
  785. /*
  786. * 7ms sleep is required after PA is disabled as per
  787. * HW requirement. If compander is disabled, then
  788. * 20ms delay is required.
  789. */
  790. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  791. if (!wcd937x->comp1_enable)
  792. usleep_range(20000, 20100);
  793. else
  794. usleep_range(7000, 7100);
  795. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  796. }
  797. snd_soc_component_update_bits(component,
  798. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  799. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  800. WCD_EVENT_POST_HPHL_PA_OFF,
  801. &wcd937x->mbhc->wcd_mbhc);
  802. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  803. 0x20, 0x00);
  804. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  805. WCD_CLSH_EVENT_POST_PA,
  806. WCD_CLSH_STATE_HPHL,
  807. hph_mode);
  808. break;
  809. };
  810. return ret;
  811. }
  812. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  813. struct snd_kcontrol *kcontrol,
  814. int event)
  815. {
  816. struct snd_soc_component *component =
  817. snd_soc_dapm_to_component(w->dapm);
  818. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  819. int hph_mode = wcd937x->hph_mode;
  820. int ret = 0;
  821. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  822. w->name, event);
  823. switch (event) {
  824. case SND_SOC_DAPM_PRE_PMU:
  825. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  826. wcd937x->rx_swr_dev->dev_num,
  827. true);
  828. snd_soc_component_update_bits(component,
  829. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  830. break;
  831. case SND_SOC_DAPM_POST_PMU:
  832. usleep_range(1000, 1010);
  833. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  834. snd_soc_component_update_bits(component,
  835. WCD937X_ANA_RX_SUPPLIES,
  836. 0x02, 0x02);
  837. if (wcd937x->update_wcd_event)
  838. wcd937x->update_wcd_event(wcd937x->handle,
  839. WCD_BOLERO_EVT_RX_MUTE,
  840. (WCD_RX3 << 0x10));
  841. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  842. break;
  843. case SND_SOC_DAPM_PRE_PMD:
  844. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  845. if (wcd937x->update_wcd_event)
  846. wcd937x->update_wcd_event(wcd937x->handle,
  847. WCD_BOLERO_EVT_RX_MUTE,
  848. (WCD_RX3 << 0x10 | 0x1));
  849. break;
  850. case SND_SOC_DAPM_POST_PMD:
  851. /* Add delay as per hw requirement */
  852. usleep_range(2000, 2010);
  853. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  854. WCD_CLSH_EVENT_POST_PA,
  855. WCD_CLSH_STATE_AUX,
  856. hph_mode);
  857. snd_soc_component_update_bits(component,
  858. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  859. break;
  860. };
  861. return ret;
  862. }
  863. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  864. struct snd_kcontrol *kcontrol,
  865. int event)
  866. {
  867. struct snd_soc_component *component =
  868. snd_soc_dapm_to_component(w->dapm);
  869. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  870. int hph_mode = wcd937x->hph_mode;
  871. int ret = 0;
  872. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  873. w->name, event);
  874. switch (event) {
  875. case SND_SOC_DAPM_PRE_PMU:
  876. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  877. wcd937x->rx_swr_dev->dev_num,
  878. true);
  879. /*
  880. * Enable watchdog interrupt for HPHL or AUX
  881. * depending on mux value
  882. */
  883. wcd937x->ear_rx_path =
  884. snd_soc_component_read32(
  885. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  886. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  887. snd_soc_component_update_bits(component,
  888. WCD937X_DIGITAL_PDM_WD_CTL2,
  889. 0x05, 0x05);
  890. else
  891. snd_soc_component_update_bits(component,
  892. WCD937X_DIGITAL_PDM_WD_CTL0,
  893. 0x17, 0x13);
  894. if (!wcd937x->comp1_enable)
  895. snd_soc_component_update_bits(component,
  896. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  897. break;
  898. case SND_SOC_DAPM_POST_PMU:
  899. usleep_range(6000, 6010);
  900. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  901. snd_soc_component_update_bits(component,
  902. WCD937X_ANA_RX_SUPPLIES,
  903. 0x02, 0x02);
  904. if (wcd937x->update_wcd_event)
  905. wcd937x->update_wcd_event(wcd937x->handle,
  906. WCD_BOLERO_EVT_RX_MUTE,
  907. (WCD_RX1 << 0x10));
  908. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  909. wcd_enable_irq(&wcd937x->irq_info,
  910. WCD937X_IRQ_AUX_PDM_WD_INT);
  911. else
  912. wcd_enable_irq(&wcd937x->irq_info,
  913. WCD937X_IRQ_HPHL_PDM_WD_INT);
  914. break;
  915. case SND_SOC_DAPM_PRE_PMD:
  916. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  917. wcd_disable_irq(&wcd937x->irq_info,
  918. WCD937X_IRQ_AUX_PDM_WD_INT);
  919. else
  920. wcd_disable_irq(&wcd937x->irq_info,
  921. WCD937X_IRQ_HPHL_PDM_WD_INT);
  922. if (wcd937x->update_wcd_event)
  923. wcd937x->update_wcd_event(wcd937x->handle,
  924. WCD_BOLERO_EVT_RX_MUTE,
  925. (WCD_RX1 << 0x10 | 0x1));
  926. break;
  927. case SND_SOC_DAPM_POST_PMD:
  928. if (!wcd937x->comp1_enable)
  929. snd_soc_component_update_bits(component,
  930. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  931. usleep_range(7000, 7010);
  932. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  933. WCD_CLSH_EVENT_POST_PA,
  934. WCD_CLSH_STATE_EAR,
  935. hph_mode);
  936. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  937. 0x04, 0x04);
  938. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  939. snd_soc_component_update_bits(component,
  940. WCD937X_DIGITAL_PDM_WD_CTL2,
  941. 0x05, 0x00);
  942. else
  943. snd_soc_component_update_bits(component,
  944. WCD937X_DIGITAL_PDM_WD_CTL0,
  945. 0x17, 0x00);
  946. break;
  947. };
  948. return ret;
  949. }
  950. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  951. struct snd_kcontrol *kcontrol,
  952. int event)
  953. {
  954. struct snd_soc_component *component =
  955. snd_soc_dapm_to_component(w->dapm);
  956. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  957. int mode = wcd937x->hph_mode;
  958. int ret = 0;
  959. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  960. w->name, event);
  961. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  962. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  963. wcd937x_rx_connect_port(component, CLSH,
  964. SND_SOC_DAPM_EVENT_ON(event));
  965. }
  966. if (SND_SOC_DAPM_EVENT_OFF(event))
  967. ret = swr_slvdev_datapath_control(
  968. wcd937x->rx_swr_dev,
  969. wcd937x->rx_swr_dev->dev_num,
  970. false);
  971. return ret;
  972. }
  973. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  974. struct snd_kcontrol *kcontrol,
  975. int event)
  976. {
  977. struct snd_soc_component *component =
  978. snd_soc_dapm_to_component(w->dapm);
  979. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  980. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  981. w->name, event);
  982. switch (event) {
  983. case SND_SOC_DAPM_PRE_PMU:
  984. wcd937x_rx_connect_port(component, HPH_L, true);
  985. if (wcd937x->comp1_enable)
  986. wcd937x_rx_connect_port(component, COMP_L, true);
  987. break;
  988. case SND_SOC_DAPM_POST_PMD:
  989. wcd937x_rx_connect_port(component, HPH_L, false);
  990. if (wcd937x->comp1_enable)
  991. wcd937x_rx_connect_port(component, COMP_L, false);
  992. wcd937x_rx_clk_disable(component);
  993. snd_soc_component_update_bits(component,
  994. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  995. 0x01, 0x00);
  996. break;
  997. };
  998. return 0;
  999. }
  1000. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1001. struct snd_kcontrol *kcontrol, int event)
  1002. {
  1003. struct snd_soc_component *component =
  1004. snd_soc_dapm_to_component(w->dapm);
  1005. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1006. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1007. w->name, event);
  1008. switch (event) {
  1009. case SND_SOC_DAPM_PRE_PMU:
  1010. wcd937x_rx_connect_port(component, HPH_R, true);
  1011. if (wcd937x->comp2_enable)
  1012. wcd937x_rx_connect_port(component, COMP_R, true);
  1013. break;
  1014. case SND_SOC_DAPM_POST_PMD:
  1015. wcd937x_rx_connect_port(component, HPH_R, false);
  1016. if (wcd937x->comp2_enable)
  1017. wcd937x_rx_connect_port(component, COMP_R, false);
  1018. wcd937x_rx_clk_disable(component);
  1019. snd_soc_component_update_bits(component,
  1020. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1021. 0x02, 0x00);
  1022. break;
  1023. };
  1024. return 0;
  1025. }
  1026. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1027. struct snd_kcontrol *kcontrol,
  1028. int event)
  1029. {
  1030. struct snd_soc_component *component =
  1031. snd_soc_dapm_to_component(w->dapm);
  1032. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1033. w->name, event);
  1034. switch (event) {
  1035. case SND_SOC_DAPM_PRE_PMU:
  1036. wcd937x_rx_connect_port(component, LO, true);
  1037. break;
  1038. case SND_SOC_DAPM_POST_PMD:
  1039. wcd937x_rx_connect_port(component, LO, false);
  1040. usleep_range(6000, 6010);
  1041. wcd937x_rx_clk_disable(component);
  1042. snd_soc_component_update_bits(component,
  1043. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1044. break;
  1045. }
  1046. return 0;
  1047. }
  1048. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1049. struct snd_kcontrol *kcontrol,
  1050. int event)
  1051. {
  1052. struct snd_soc_component *component =
  1053. snd_soc_dapm_to_component(w->dapm);
  1054. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1055. u16 dmic_clk_reg;
  1056. s32 *dmic_clk_cnt;
  1057. unsigned int dmic;
  1058. char *wname;
  1059. int ret = 0;
  1060. wname = strpbrk(w->name, "012345");
  1061. if (!wname) {
  1062. dev_err(component->dev, "%s: widget not found\n", __func__);
  1063. return -EINVAL;
  1064. }
  1065. ret = kstrtouint(wname, 10, &dmic);
  1066. if (ret < 0) {
  1067. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1068. __func__);
  1069. return -EINVAL;
  1070. }
  1071. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1072. w->name, event);
  1073. switch (dmic) {
  1074. case 0:
  1075. case 1:
  1076. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1077. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1078. break;
  1079. case 2:
  1080. case 3:
  1081. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1082. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1083. break;
  1084. case 4:
  1085. case 5:
  1086. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1087. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1088. break;
  1089. default:
  1090. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1091. __func__);
  1092. return -EINVAL;
  1093. };
  1094. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1095. __func__, event, dmic, *dmic_clk_cnt);
  1096. switch (event) {
  1097. case SND_SOC_DAPM_PRE_PMU:
  1098. snd_soc_component_update_bits(component,
  1099. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1100. snd_soc_component_update_bits(component,
  1101. dmic_clk_reg, 0x07, 0x02);
  1102. snd_soc_component_update_bits(component,
  1103. dmic_clk_reg, 0x08, 0x08);
  1104. snd_soc_component_update_bits(component,
  1105. dmic_clk_reg, 0x70, 0x20);
  1106. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1107. break;
  1108. case SND_SOC_DAPM_POST_PMD:
  1109. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1110. break;
  1111. };
  1112. return 0;
  1113. }
  1114. /*
  1115. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1116. * @micb_mv: micbias in mv
  1117. *
  1118. * return register value converted
  1119. */
  1120. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1121. {
  1122. /* min micbias voltage is 1V and maximum is 2.85V */
  1123. if (micb_mv < 1000 || micb_mv > 2850) {
  1124. pr_err("%s: unsupported micbias voltage\n", __func__);
  1125. return -EINVAL;
  1126. }
  1127. return (micb_mv - 1000) / 50;
  1128. }
  1129. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1130. /*
  1131. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1132. * @component: handle to snd_soc_component *
  1133. * @req_volt: micbias voltage to be set
  1134. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1135. *
  1136. * return 0 if adjustment is success or error code in case of failure
  1137. */
  1138. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1139. int req_volt, int micb_num)
  1140. {
  1141. struct wcd937x_priv *wcd937x =
  1142. snd_soc_component_get_drvdata(component);
  1143. int cur_vout_ctl, req_vout_ctl;
  1144. int micb_reg, micb_val, micb_en;
  1145. int ret = 0;
  1146. switch (micb_num) {
  1147. case MIC_BIAS_1:
  1148. micb_reg = WCD937X_ANA_MICB1;
  1149. break;
  1150. case MIC_BIAS_2:
  1151. micb_reg = WCD937X_ANA_MICB2;
  1152. break;
  1153. case MIC_BIAS_3:
  1154. micb_reg = WCD937X_ANA_MICB3;
  1155. break;
  1156. default:
  1157. return -EINVAL;
  1158. }
  1159. mutex_lock(&wcd937x->micb_lock);
  1160. /*
  1161. * If requested micbias voltage is same as current micbias
  1162. * voltage, then just return. Otherwise, adjust voltage as
  1163. * per requested value. If micbias is already enabled, then
  1164. * to avoid slow micbias ramp-up or down enable pull-up
  1165. * momentarily, change the micbias value and then re-enable
  1166. * micbias.
  1167. */
  1168. micb_val = snd_soc_component_read32(component, micb_reg);
  1169. micb_en = (micb_val & 0xC0) >> 6;
  1170. cur_vout_ctl = micb_val & 0x3F;
  1171. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1172. if (req_vout_ctl < 0) {
  1173. ret = -EINVAL;
  1174. goto exit;
  1175. }
  1176. if (cur_vout_ctl == req_vout_ctl) {
  1177. ret = 0;
  1178. goto exit;
  1179. }
  1180. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1181. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1182. req_volt, micb_en);
  1183. if (micb_en == 0x1)
  1184. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1185. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1186. if (micb_en == 0x1) {
  1187. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1188. /*
  1189. * Add 2ms delay as per HW requirement after enabling
  1190. * micbias
  1191. */
  1192. usleep_range(2000, 2100);
  1193. }
  1194. exit:
  1195. mutex_unlock(&wcd937x->micb_lock);
  1196. return ret;
  1197. }
  1198. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1199. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1200. struct snd_kcontrol *kcontrol,
  1201. int event)
  1202. {
  1203. struct snd_soc_component *component =
  1204. snd_soc_dapm_to_component(w->dapm);
  1205. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1206. int ret = 0;
  1207. switch (event) {
  1208. case SND_SOC_DAPM_PRE_PMU:
  1209. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1210. wcd937x->tx_swr_dev->dev_num,
  1211. true);
  1212. break;
  1213. case SND_SOC_DAPM_POST_PMD:
  1214. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1215. wcd937x->tx_swr_dev->dev_num,
  1216. false);
  1217. break;
  1218. };
  1219. return ret;
  1220. }
  1221. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1222. struct snd_kcontrol *kcontrol,
  1223. int event){
  1224. struct snd_soc_component *component =
  1225. snd_soc_dapm_to_component(w->dapm);
  1226. struct wcd937x_priv *wcd937x =
  1227. snd_soc_component_get_drvdata(component);
  1228. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1229. w->name, event);
  1230. switch (event) {
  1231. case SND_SOC_DAPM_PRE_PMU:
  1232. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1233. wcd937x->ana_clk_count++;
  1234. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1235. snd_soc_component_update_bits(component,
  1236. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1237. snd_soc_component_update_bits(component,
  1238. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1239. snd_soc_component_update_bits(component,
  1240. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1241. /* Enable BCS for Headset mic */
  1242. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1243. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1244. wcd937x_tx_connect_port(component, MBHC, true);
  1245. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1246. }
  1247. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1248. break;
  1249. case SND_SOC_DAPM_POST_PMD:
  1250. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1251. if (w->shift == 1 &&
  1252. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1253. wcd937x_tx_connect_port(component, MBHC, false);
  1254. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1255. }
  1256. snd_soc_component_update_bits(component,
  1257. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1258. break;
  1259. };
  1260. return 0;
  1261. }
  1262. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1263. struct snd_kcontrol *kcontrol, int event)
  1264. {
  1265. struct snd_soc_component *component =
  1266. snd_soc_dapm_to_component(w->dapm);
  1267. struct wcd937x_priv *wcd937x =
  1268. snd_soc_component_get_drvdata(component);
  1269. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1270. w->name, event);
  1271. switch (event) {
  1272. case SND_SOC_DAPM_PRE_PMU:
  1273. snd_soc_component_update_bits(component,
  1274. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1275. snd_soc_component_update_bits(component,
  1276. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1277. snd_soc_component_update_bits(component,
  1278. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1279. snd_soc_component_update_bits(component,
  1280. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1281. snd_soc_component_update_bits(component,
  1282. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1283. snd_soc_component_update_bits(component,
  1284. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1285. snd_soc_component_update_bits(component,
  1286. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1287. snd_soc_component_update_bits(component,
  1288. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1289. snd_soc_component_update_bits(component,
  1290. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1291. break;
  1292. case SND_SOC_DAPM_POST_PMD:
  1293. snd_soc_component_update_bits(component,
  1294. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1295. snd_soc_component_update_bits(component,
  1296. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1297. snd_soc_component_update_bits(component,
  1298. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1299. snd_soc_component_update_bits(component,
  1300. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1301. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1302. wcd937x->ana_clk_count--;
  1303. if (wcd937x->ana_clk_count <= 0) {
  1304. snd_soc_component_update_bits(component,
  1305. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1306. wcd937x->ana_clk_count = 0;
  1307. }
  1308. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1309. snd_soc_component_update_bits(component,
  1310. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1311. break;
  1312. };
  1313. return 0;
  1314. }
  1315. int wcd937x_micbias_control(struct snd_soc_component *component,
  1316. int micb_num, int req, bool is_dapm)
  1317. {
  1318. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1319. int micb_index = micb_num - 1;
  1320. u16 micb_reg;
  1321. int pre_off_event = 0, post_off_event = 0;
  1322. int post_on_event = 0, post_dapm_off = 0;
  1323. int post_dapm_on = 0;
  1324. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1325. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1326. __func__, micb_index);
  1327. return -EINVAL;
  1328. }
  1329. switch (micb_num) {
  1330. case MIC_BIAS_1:
  1331. micb_reg = WCD937X_ANA_MICB1;
  1332. break;
  1333. case MIC_BIAS_2:
  1334. micb_reg = WCD937X_ANA_MICB2;
  1335. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1336. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1337. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1338. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1339. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1340. break;
  1341. case MIC_BIAS_3:
  1342. micb_reg = WCD937X_ANA_MICB3;
  1343. break;
  1344. default:
  1345. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1346. __func__, micb_num);
  1347. return -EINVAL;
  1348. };
  1349. mutex_lock(&wcd937x->micb_lock);
  1350. switch (req) {
  1351. case MICB_PULLUP_ENABLE:
  1352. wcd937x->pullup_ref[micb_index]++;
  1353. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1354. (wcd937x->micb_ref[micb_index] == 0))
  1355. snd_soc_component_update_bits(component, micb_reg,
  1356. 0xC0, 0x80);
  1357. break;
  1358. case MICB_PULLUP_DISABLE:
  1359. if (wcd937x->pullup_ref[micb_index] > 0)
  1360. wcd937x->pullup_ref[micb_index]--;
  1361. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1362. (wcd937x->micb_ref[micb_index] == 0))
  1363. snd_soc_component_update_bits(component, micb_reg,
  1364. 0xC0, 0x00);
  1365. break;
  1366. case MICB_ENABLE:
  1367. wcd937x->micb_ref[micb_index]++;
  1368. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1369. wcd937x->ana_clk_count++;
  1370. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1371. if (wcd937x->micb_ref[micb_index] == 1) {
  1372. snd_soc_component_update_bits(component,
  1373. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1374. snd_soc_component_update_bits(component,
  1375. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1376. snd_soc_component_update_bits(component,
  1377. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1378. snd_soc_component_update_bits(component,
  1379. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1380. snd_soc_component_update_bits(component,
  1381. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1382. snd_soc_component_update_bits(component,
  1383. micb_reg, 0xC0, 0x40);
  1384. if (post_on_event)
  1385. blocking_notifier_call_chain(
  1386. &wcd937x->mbhc->notifier, post_on_event,
  1387. &wcd937x->mbhc->wcd_mbhc);
  1388. }
  1389. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1390. blocking_notifier_call_chain(
  1391. &wcd937x->mbhc->notifier, post_dapm_on,
  1392. &wcd937x->mbhc->wcd_mbhc);
  1393. break;
  1394. case MICB_DISABLE:
  1395. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1396. wcd937x->ana_clk_count--;
  1397. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1398. if (wcd937x->micb_ref[micb_index] > 0)
  1399. wcd937x->micb_ref[micb_index]--;
  1400. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1401. (wcd937x->pullup_ref[micb_index] > 0))
  1402. snd_soc_component_update_bits(component, micb_reg,
  1403. 0xC0, 0x80);
  1404. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1405. (wcd937x->pullup_ref[micb_index] == 0)) {
  1406. if (pre_off_event && wcd937x->mbhc)
  1407. blocking_notifier_call_chain(
  1408. &wcd937x->mbhc->notifier, pre_off_event,
  1409. &wcd937x->mbhc->wcd_mbhc);
  1410. snd_soc_component_update_bits(component, micb_reg,
  1411. 0xC0, 0x00);
  1412. if (post_off_event && wcd937x->mbhc)
  1413. blocking_notifier_call_chain(
  1414. &wcd937x->mbhc->notifier,
  1415. post_off_event,
  1416. &wcd937x->mbhc->wcd_mbhc);
  1417. }
  1418. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1419. if (wcd937x->ana_clk_count <= 0) {
  1420. snd_soc_component_update_bits(component,
  1421. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1422. 0x10, 0x00);
  1423. wcd937x->ana_clk_count = 0;
  1424. }
  1425. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1426. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1427. blocking_notifier_call_chain(
  1428. &wcd937x->mbhc->notifier, post_dapm_off,
  1429. &wcd937x->mbhc->wcd_mbhc);
  1430. break;
  1431. };
  1432. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1433. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1434. wcd937x->pullup_ref[micb_index]);
  1435. mutex_unlock(&wcd937x->micb_lock);
  1436. return 0;
  1437. }
  1438. EXPORT_SYMBOL(wcd937x_micbias_control);
  1439. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1440. bool bcs_disable)
  1441. {
  1442. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1443. if (wcd937x->update_wcd_event) {
  1444. if (bcs_disable)
  1445. wcd937x->update_wcd_event(wcd937x->handle,
  1446. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1447. else
  1448. wcd937x->update_wcd_event(wcd937x->handle,
  1449. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1450. }
  1451. }
  1452. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1453. {
  1454. int ret = 0;
  1455. uint8_t devnum = 0;
  1456. int num_retry = NUM_ATTEMPTS;
  1457. do {
  1458. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1459. if (ret) {
  1460. dev_err(&swr_dev->dev,
  1461. "%s get devnum %d for dev addr %lx failed\n",
  1462. __func__, devnum, swr_dev->addr);
  1463. /* retry after 1ms */
  1464. usleep_range(1000, 1010);
  1465. }
  1466. } while (ret && --num_retry);
  1467. swr_dev->dev_num = devnum;
  1468. return 0;
  1469. }
  1470. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1471. struct wcd_mbhc_config *mbhc_cfg)
  1472. {
  1473. if (mbhc_cfg->enable_usbc_analog) {
  1474. if (!(snd_soc_component_read32(component, WCD937X_ANA_MBHC_MECH)
  1475. & 0x20))
  1476. return true;
  1477. }
  1478. return false;
  1479. }
  1480. static int wcd937x_event_notify(struct notifier_block *block,
  1481. unsigned long val,
  1482. void *data)
  1483. {
  1484. u16 event = (val & 0xffff);
  1485. u16 amic = (val >> 0x10);
  1486. u16 mask = 0x40, reg = 0x0;
  1487. int ret = 0;
  1488. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1489. struct snd_soc_component *component = wcd937x->component;
  1490. struct wcd_mbhc *mbhc;
  1491. switch (event) {
  1492. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1493. if (amic == 0x1 || amic == 0x2)
  1494. reg = WCD937X_ANA_TX_CH2;
  1495. else if (amic == 0x3)
  1496. reg = WCD937X_ANA_TX_CH3_HPF;
  1497. else
  1498. return 0;
  1499. if (amic == 0x2)
  1500. mask = 0x20;
  1501. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1502. break;
  1503. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1504. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1505. 0xC0, 0x00);
  1506. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1507. 0x80, 0x00);
  1508. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1509. 0x80, 0x00);
  1510. break;
  1511. case BOLERO_WCD_EVT_SSR_DOWN:
  1512. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1513. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1514. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1515. mbhc->mbhc_cfg);
  1516. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1517. wcd937x_reset_low(wcd937x->dev);
  1518. break;
  1519. case BOLERO_WCD_EVT_SSR_UP:
  1520. wcd937x_reset(wcd937x->dev);
  1521. /* allow reset to take effect */
  1522. usleep_range(10000, 10010);
  1523. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1524. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1525. wcd937x_init_reg(component);
  1526. regcache_mark_dirty(wcd937x->regmap);
  1527. regcache_sync(wcd937x->regmap);
  1528. /* Initialize MBHC module */
  1529. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1530. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1531. if (ret) {
  1532. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1533. __func__);
  1534. } else {
  1535. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1536. if (wcd937x->usbc_hs_status)
  1537. mdelay(500);
  1538. }
  1539. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1540. break;
  1541. default:
  1542. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1543. event);
  1544. break;
  1545. }
  1546. return 0;
  1547. }
  1548. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1549. int event)
  1550. {
  1551. struct snd_soc_component *component =
  1552. snd_soc_dapm_to_component(w->dapm);
  1553. int micb_num;
  1554. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1555. __func__, w->name, event);
  1556. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1557. micb_num = MIC_BIAS_1;
  1558. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1559. micb_num = MIC_BIAS_2;
  1560. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1561. micb_num = MIC_BIAS_3;
  1562. else
  1563. return -EINVAL;
  1564. switch (event) {
  1565. case SND_SOC_DAPM_PRE_PMU:
  1566. wcd937x_micbias_control(component, micb_num,
  1567. MICB_ENABLE, true);
  1568. break;
  1569. case SND_SOC_DAPM_POST_PMU:
  1570. usleep_range(1000, 1100);
  1571. break;
  1572. case SND_SOC_DAPM_POST_PMD:
  1573. wcd937x_micbias_control(component, micb_num,
  1574. MICB_DISABLE, true);
  1575. break;
  1576. };
  1577. return 0;
  1578. }
  1579. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1580. struct snd_kcontrol *kcontrol,
  1581. int event)
  1582. {
  1583. return __wcd937x_codec_enable_micbias(w, event);
  1584. }
  1585. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1586. int event)
  1587. {
  1588. struct snd_soc_component *component =
  1589. snd_soc_dapm_to_component(w->dapm);
  1590. int micb_num;
  1591. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1592. __func__, w->name, event);
  1593. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1594. micb_num = MIC_BIAS_1;
  1595. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1596. micb_num = MIC_BIAS_2;
  1597. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1598. micb_num = MIC_BIAS_3;
  1599. else
  1600. return -EINVAL;
  1601. switch (event) {
  1602. case SND_SOC_DAPM_PRE_PMU:
  1603. wcd937x_micbias_control(component, micb_num,
  1604. MICB_PULLUP_ENABLE, true);
  1605. break;
  1606. case SND_SOC_DAPM_POST_PMU:
  1607. /* 1 msec delay as per HW requirement */
  1608. usleep_range(1000, 1100);
  1609. break;
  1610. case SND_SOC_DAPM_POST_PMD:
  1611. wcd937x_micbias_control(component, micb_num,
  1612. MICB_PULLUP_DISABLE, true);
  1613. break;
  1614. };
  1615. return 0;
  1616. }
  1617. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1618. struct snd_kcontrol *kcontrol,
  1619. int event)
  1620. {
  1621. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1622. }
  1623. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1624. struct snd_ctl_elem_value *ucontrol)
  1625. {
  1626. struct snd_soc_component *component =
  1627. snd_soc_kcontrol_component(kcontrol);
  1628. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1629. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1630. return 0;
  1631. }
  1632. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1633. struct snd_ctl_elem_value *ucontrol)
  1634. {
  1635. struct snd_soc_component *component =
  1636. snd_soc_kcontrol_component(kcontrol);
  1637. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1638. u32 mode_val;
  1639. mode_val = ucontrol->value.enumerated.item[0];
  1640. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1641. if (mode_val == 0) {
  1642. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1643. __func__);
  1644. mode_val = 3; /* enum will be updated later */
  1645. }
  1646. wcd937x->hph_mode = mode_val;
  1647. return 0;
  1648. }
  1649. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1650. struct snd_ctl_elem_value *ucontrol)
  1651. {
  1652. struct snd_soc_component *component =
  1653. snd_soc_kcontrol_component(kcontrol);
  1654. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1655. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1656. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1657. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1658. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1659. return 0;
  1660. }
  1661. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1662. struct snd_ctl_elem_value *ucontrol)
  1663. {
  1664. struct snd_soc_component *component =
  1665. snd_soc_kcontrol_component(kcontrol);
  1666. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1667. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1668. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1669. __func__, pwr_level);
  1670. if (strnstr(kcontrol->id.name, "CH1",
  1671. sizeof(kcontrol->id.name))) {
  1672. snd_soc_component_update_bits(component,
  1673. WCD937X_ANA_TX_CH1, 0x60,
  1674. pwr_level << 0x5);
  1675. wcd937x->tx_ch_pwr[0] = pwr_level;
  1676. } else if (strnstr(kcontrol->id.name, "CH3",
  1677. sizeof(kcontrol->id.name))) {
  1678. snd_soc_component_update_bits(component,
  1679. WCD937X_ANA_TX_CH3, 0x60,
  1680. pwr_level << 0x5);
  1681. wcd937x->tx_ch_pwr[1] = pwr_level;
  1682. }
  1683. return 0;
  1684. }
  1685. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1686. struct snd_ctl_elem_value *ucontrol)
  1687. {
  1688. u8 ear_pa_gain = 0;
  1689. struct snd_soc_component *component =
  1690. snd_soc_kcontrol_component(kcontrol);
  1691. ear_pa_gain = snd_soc_component_read32(component,
  1692. WCD937X_ANA_EAR_COMPANDER_CTL);
  1693. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1694. ucontrol->value.integer.value[0] = ear_pa_gain;
  1695. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1696. ear_pa_gain);
  1697. return 0;
  1698. }
  1699. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. u8 ear_pa_gain = 0;
  1703. struct snd_soc_component *component =
  1704. snd_soc_kcontrol_component(kcontrol);
  1705. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1706. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1707. __func__, ucontrol->value.integer.value[0]);
  1708. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1709. if (!wcd937x->comp1_enable) {
  1710. snd_soc_component_update_bits(component,
  1711. WCD937X_ANA_EAR_COMPANDER_CTL,
  1712. 0x7C, ear_pa_gain);
  1713. }
  1714. return 0;
  1715. }
  1716. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1717. struct snd_ctl_elem_value *ucontrol)
  1718. {
  1719. struct snd_soc_component *component =
  1720. snd_soc_kcontrol_component(kcontrol);
  1721. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1722. bool hphr;
  1723. struct soc_multi_mixer_control *mc;
  1724. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1725. hphr = mc->shift;
  1726. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1727. wcd937x->comp1_enable;
  1728. return 0;
  1729. }
  1730. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1731. struct snd_ctl_elem_value *ucontrol)
  1732. {
  1733. struct snd_soc_component *component =
  1734. snd_soc_kcontrol_component(kcontrol);
  1735. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1736. int value = ucontrol->value.integer.value[0];
  1737. bool hphr;
  1738. struct soc_multi_mixer_control *mc;
  1739. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1740. hphr = mc->shift;
  1741. if (hphr)
  1742. wcd937x->comp2_enable = value;
  1743. else
  1744. wcd937x->comp1_enable = value;
  1745. return 0;
  1746. }
  1747. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1748. struct snd_kcontrol *kcontrol,
  1749. int event)
  1750. {
  1751. struct snd_soc_component *component =
  1752. snd_soc_dapm_to_component(w->dapm);
  1753. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1754. struct wcd937x_pdata *pdata = NULL;
  1755. int ret = 0;
  1756. pdata = dev_get_platdata(wcd937x->dev);
  1757. if (!pdata) {
  1758. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1759. return -EINVAL;
  1760. }
  1761. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1762. w->name, event);
  1763. switch (event) {
  1764. case SND_SOC_DAPM_PRE_PMU:
  1765. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1766. dev_dbg(component->dev,
  1767. "%s: buck already in enabled state\n",
  1768. __func__);
  1769. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1770. return 0;
  1771. }
  1772. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1773. wcd937x->supplies,
  1774. pdata->regulator,
  1775. pdata->num_supplies,
  1776. "cdc-vdd-buck");
  1777. if (ret == -EINVAL) {
  1778. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1779. __func__);
  1780. return ret;
  1781. }
  1782. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1783. /*
  1784. * 200us sleep is required after LDO15 is enabled as per
  1785. * HW requirement
  1786. */
  1787. usleep_range(200, 250);
  1788. break;
  1789. case SND_SOC_DAPM_POST_PMD:
  1790. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1791. break;
  1792. }
  1793. return 0;
  1794. }
  1795. static const char * const rx_hph_mode_mux_text[] = {
  1796. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1797. "CLS_H_ULP", "CLS_AB_HIFI",
  1798. };
  1799. const char * const tx_master_ch_text[] = {
  1800. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1801. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1802. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1803. "SWRM_PCM_IN",
  1804. };
  1805. const struct soc_enum tx_master_ch_enum =
  1806. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1807. tx_master_ch_text);
  1808. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1809. {
  1810. u8 ch_type = 0;
  1811. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1812. ch_type = ADC1;
  1813. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1814. ch_type = ADC2;
  1815. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1816. ch_type = ADC3;
  1817. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1818. ch_type = DMIC0;
  1819. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1820. ch_type = DMIC1;
  1821. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1822. ch_type = MBHC;
  1823. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1824. ch_type = DMIC2;
  1825. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1826. ch_type = DMIC3;
  1827. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1828. ch_type = DMIC4;
  1829. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1830. ch_type = DMIC5;
  1831. else
  1832. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1833. if (ch_type)
  1834. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1835. else
  1836. *ch_idx = -EINVAL;
  1837. }
  1838. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1839. struct snd_ctl_elem_value *ucontrol)
  1840. {
  1841. struct snd_soc_component *component =
  1842. snd_soc_kcontrol_component(kcontrol);
  1843. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1844. int slave_ch_idx;
  1845. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1846. if (slave_ch_idx != -EINVAL)
  1847. ucontrol->value.integer.value[0] =
  1848. wcd937x_slave_get_master_ch_val(
  1849. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1850. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1851. __func__, ucontrol->value.integer.value[0]);
  1852. return 0;
  1853. }
  1854. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1855. struct snd_ctl_elem_value *ucontrol)
  1856. {
  1857. struct snd_soc_component *component =
  1858. snd_soc_kcontrol_component(kcontrol);
  1859. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1860. int slave_ch_idx;
  1861. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1862. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1863. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1864. __func__, ucontrol->value.enumerated.item[0]);
  1865. if (slave_ch_idx != -EINVAL)
  1866. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1867. wcd937x_slave_get_master_ch(
  1868. ucontrol->value.enumerated.item[0]);
  1869. return 0;
  1870. }
  1871. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1872. "L0", "L1", "L2", "L3",
  1873. };
  1874. static const char * const wcd937x_ear_pa_gain_text[] = {
  1875. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1876. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1877. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1878. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1879. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1880. };
  1881. static const struct soc_enum rx_hph_mode_mux_enum =
  1882. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1883. rx_hph_mode_mux_text);
  1884. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1885. wcd937x_ear_pa_gain_text);
  1886. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1887. wcd937x_tx_ch_pwr_level_text);
  1888. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1889. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1890. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1891. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1892. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1893. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1894. wcd937x_get_compander, wcd937x_set_compander),
  1895. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1896. wcd937x_get_compander, wcd937x_set_compander),
  1897. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1898. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1899. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1900. analog_gain),
  1901. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1902. analog_gain),
  1903. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1904. analog_gain),
  1905. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1906. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1907. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1908. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1909. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1910. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1911. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1912. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1913. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1914. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1915. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1916. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1917. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1918. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1919. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1920. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1921. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1922. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1923. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1924. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1925. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  1926. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1927. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  1928. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1929. };
  1930. static const struct snd_kcontrol_new adc1_switch[] = {
  1931. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1932. };
  1933. static const struct snd_kcontrol_new adc2_switch[] = {
  1934. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1935. };
  1936. static const struct snd_kcontrol_new adc3_switch[] = {
  1937. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1938. };
  1939. static const struct snd_kcontrol_new dmic1_switch[] = {
  1940. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1941. };
  1942. static const struct snd_kcontrol_new dmic2_switch[] = {
  1943. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1944. };
  1945. static const struct snd_kcontrol_new dmic3_switch[] = {
  1946. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1947. };
  1948. static const struct snd_kcontrol_new dmic4_switch[] = {
  1949. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1950. };
  1951. static const struct snd_kcontrol_new dmic5_switch[] = {
  1952. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1953. };
  1954. static const struct snd_kcontrol_new dmic6_switch[] = {
  1955. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1956. };
  1957. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1958. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1959. };
  1960. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1961. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1962. };
  1963. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1964. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1965. };
  1966. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1967. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1968. };
  1969. static const char * const adc2_mux_text[] = {
  1970. "INP2", "INP3"
  1971. };
  1972. static const char * const rdac3_mux_text[] = {
  1973. "RX1", "RX3"
  1974. };
  1975. static const struct soc_enum adc2_enum =
  1976. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1977. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1978. static const struct soc_enum rdac3_enum =
  1979. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1980. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1981. static const struct snd_kcontrol_new tx_adc2_mux =
  1982. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1983. static const struct snd_kcontrol_new rx_rdac3_mux =
  1984. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1985. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1986. /*input widgets*/
  1987. SND_SOC_DAPM_INPUT("AMIC1"),
  1988. SND_SOC_DAPM_INPUT("AMIC2"),
  1989. SND_SOC_DAPM_INPUT("AMIC3"),
  1990. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1991. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1992. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1993. /*tx widgets*/
  1994. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1995. wcd937x_codec_enable_adc,
  1996. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1997. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1998. wcd937x_codec_enable_adc,
  1999. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2000. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2001. NULL, 0, wcd937x_enable_req,
  2002. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2003. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2004. NULL, 0, wcd937x_enable_req,
  2005. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2006. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2007. &tx_adc2_mux),
  2008. /*tx mixers*/
  2009. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2010. adc1_switch, ARRAY_SIZE(adc1_switch),
  2011. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2012. SND_SOC_DAPM_POST_PMD),
  2013. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2014. adc2_switch, ARRAY_SIZE(adc2_switch),
  2015. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2016. SND_SOC_DAPM_POST_PMD),
  2017. /* micbias widgets*/
  2018. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2019. wcd937x_codec_enable_micbias,
  2020. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2021. SND_SOC_DAPM_POST_PMD),
  2022. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2023. wcd937x_codec_enable_micbias,
  2024. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2025. SND_SOC_DAPM_POST_PMD),
  2026. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2027. wcd937x_codec_enable_micbias,
  2028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2029. SND_SOC_DAPM_POST_PMD),
  2030. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2031. wcd937x_codec_enable_vdd_buck,
  2032. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2033. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2034. wcd937x_enable_clsh,
  2035. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2036. /*rx widgets*/
  2037. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2038. wcd937x_codec_enable_ear_pa,
  2039. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2040. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2041. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2042. wcd937x_codec_enable_aux_pa,
  2043. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2044. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2045. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2046. wcd937x_codec_enable_hphl_pa,
  2047. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2048. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2049. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2050. wcd937x_codec_enable_hphr_pa,
  2051. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2052. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2053. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2054. wcd937x_codec_hphl_dac_event,
  2055. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2056. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2057. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2058. wcd937x_codec_hphr_dac_event,
  2059. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2060. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2061. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2062. wcd937x_codec_ear_dac_event,
  2063. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2064. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2065. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2066. wcd937x_codec_aux_dac_event,
  2067. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2068. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2069. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2070. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2071. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2072. SND_SOC_DAPM_POST_PMD),
  2073. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2074. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2075. SND_SOC_DAPM_POST_PMD),
  2076. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2077. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2078. SND_SOC_DAPM_POST_PMD),
  2079. /* rx mixer widgets*/
  2080. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2081. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2082. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2083. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2084. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2085. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2086. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2087. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2088. /*output widgets tx*/
  2089. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2090. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2091. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2092. /*output widgets rx*/
  2093. SND_SOC_DAPM_OUTPUT("EAR"),
  2094. SND_SOC_DAPM_OUTPUT("AUX"),
  2095. SND_SOC_DAPM_OUTPUT("HPHL"),
  2096. SND_SOC_DAPM_OUTPUT("HPHR"),
  2097. /* micbias pull up widgets*/
  2098. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2099. wcd937x_codec_enable_micbias_pullup,
  2100. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2101. SND_SOC_DAPM_POST_PMD),
  2102. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2103. wcd937x_codec_enable_micbias_pullup,
  2104. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2105. SND_SOC_DAPM_POST_PMD),
  2106. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2107. wcd937x_codec_enable_micbias_pullup,
  2108. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2109. SND_SOC_DAPM_POST_PMD),
  2110. };
  2111. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2112. /*input widgets*/
  2113. SND_SOC_DAPM_INPUT("AMIC4"),
  2114. /*tx widgets*/
  2115. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2116. wcd937x_codec_enable_adc,
  2117. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2118. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2119. NULL, 0, wcd937x_enable_req,
  2120. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2121. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2122. wcd937x_codec_enable_dmic,
  2123. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2124. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2125. wcd937x_codec_enable_dmic,
  2126. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2127. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2128. wcd937x_codec_enable_dmic,
  2129. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2130. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2131. wcd937x_codec_enable_dmic,
  2132. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2133. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2134. wcd937x_codec_enable_dmic,
  2135. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2136. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2137. wcd937x_codec_enable_dmic,
  2138. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2139. /*tx mixer widgets*/
  2140. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2141. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2142. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2143. SND_SOC_DAPM_POST_PMD),
  2144. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2145. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2146. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2147. SND_SOC_DAPM_POST_PMD),
  2148. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2149. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2150. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2151. SND_SOC_DAPM_POST_PMD),
  2152. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2153. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2154. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2155. SND_SOC_DAPM_POST_PMD),
  2156. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2157. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2158. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2159. SND_SOC_DAPM_POST_PMD),
  2160. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2161. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2162. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2163. SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2165. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2167. /*output widgets*/
  2168. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2169. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2170. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2171. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2172. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2173. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2174. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2175. };
  2176. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2177. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2178. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2179. {"ADC1 REQ", NULL, "ADC1"},
  2180. {"ADC1", NULL, "AMIC1"},
  2181. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2182. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2183. {"ADC2 REQ", NULL, "ADC2"},
  2184. {"ADC2", NULL, "ADC2 MUX"},
  2185. {"ADC2 MUX", "INP3", "AMIC3"},
  2186. {"ADC2 MUX", "INP2", "AMIC2"},
  2187. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2188. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2189. {"RX1", NULL, "IN1_HPHL"},
  2190. {"RDAC1", NULL, "RX1"},
  2191. {"HPHL_RDAC", "Switch", "RDAC1"},
  2192. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2193. {"HPHL", NULL, "HPHL PGA"},
  2194. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2195. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2196. {"RX2", NULL, "IN2_HPHR"},
  2197. {"RDAC2", NULL, "RX2"},
  2198. {"HPHR_RDAC", "Switch", "RDAC2"},
  2199. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2200. {"HPHR", NULL, "HPHR PGA"},
  2201. {"IN3_AUX", NULL, "VDD_BUCK"},
  2202. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2203. {"RX3", NULL, "IN3_AUX"},
  2204. {"RDAC4", NULL, "RX3"},
  2205. {"AUX_RDAC", "Switch", "RDAC4"},
  2206. {"AUX PGA", NULL, "AUX_RDAC"},
  2207. {"AUX", NULL, "AUX PGA"},
  2208. {"RDAC3_MUX", "RX3", "RX3"},
  2209. {"RDAC3_MUX", "RX1", "RX1"},
  2210. {"RDAC3", NULL, "RDAC3_MUX"},
  2211. {"EAR_RDAC", "Switch", "RDAC3"},
  2212. {"EAR PGA", NULL, "EAR_RDAC"},
  2213. {"EAR", NULL, "EAR PGA"},
  2214. };
  2215. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2216. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2217. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2218. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2219. {"ADC3 REQ", NULL, "ADC3"},
  2220. {"ADC3", NULL, "AMIC4"},
  2221. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2222. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2223. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2224. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2225. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2226. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2227. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2228. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2229. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2230. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2231. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2232. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2233. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2234. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2235. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2236. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2237. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2238. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2239. };
  2240. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2241. void *file_private_data,
  2242. struct file *file,
  2243. char __user *buf, size_t count,
  2244. loff_t pos)
  2245. {
  2246. struct wcd937x_priv *priv;
  2247. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2248. int len = 0;
  2249. priv = (struct wcd937x_priv *) entry->private_data;
  2250. if (!priv) {
  2251. pr_err("%s: wcd937x priv is null\n", __func__);
  2252. return -EINVAL;
  2253. }
  2254. switch (priv->version) {
  2255. case WCD937X_VERSION_1_0:
  2256. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2257. break;
  2258. default:
  2259. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2260. }
  2261. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2262. }
  2263. static struct snd_info_entry_ops wcd937x_info_ops = {
  2264. .read = wcd937x_version_read,
  2265. };
  2266. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2267. void *file_private_data,
  2268. struct file *file,
  2269. char __user *buf, size_t count,
  2270. loff_t pos)
  2271. {
  2272. struct wcd937x_priv *priv;
  2273. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2274. int len = 0;
  2275. priv = (struct wcd937x_priv *) entry->private_data;
  2276. if (!priv) {
  2277. pr_err("%s: wcd937x priv is null\n", __func__);
  2278. return -EINVAL;
  2279. }
  2280. switch (priv->variant) {
  2281. case WCD9370_VARIANT:
  2282. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2283. break;
  2284. case WCD9375_VARIANT:
  2285. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2286. break;
  2287. default:
  2288. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2289. }
  2290. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2291. }
  2292. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2293. .read = wcd937x_variant_read,
  2294. };
  2295. /*
  2296. * wcd937x_info_create_codec_entry - creates wcd937x module
  2297. * @codec_root: The parent directory
  2298. * @component: component instance
  2299. *
  2300. * Creates wcd937x module, variant and version entry under the given
  2301. * parent directory.
  2302. *
  2303. * Return: 0 on success or negative error code on failure.
  2304. */
  2305. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2306. struct snd_soc_component *component)
  2307. {
  2308. struct snd_info_entry *version_entry;
  2309. struct snd_info_entry *variant_entry;
  2310. struct wcd937x_priv *priv;
  2311. struct snd_soc_card *card;
  2312. if (!codec_root || !component)
  2313. return -EINVAL;
  2314. priv = snd_soc_component_get_drvdata(component);
  2315. if (priv->entry) {
  2316. dev_dbg(priv->dev,
  2317. "%s:wcd937x module already created\n", __func__);
  2318. return 0;
  2319. }
  2320. card = component->card;
  2321. priv->entry = snd_info_create_module_entry(codec_root->module,
  2322. "wcd937x", codec_root);
  2323. if (!priv->entry) {
  2324. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2325. __func__);
  2326. return -ENOMEM;
  2327. }
  2328. priv->entry->mode = S_IFDIR | 0555;
  2329. if (snd_info_register(priv->entry) < 0) {
  2330. snd_info_free_entry(priv->entry);
  2331. return -ENOMEM;
  2332. }
  2333. version_entry = snd_info_create_card_entry(card->snd_card,
  2334. "version",
  2335. priv->entry);
  2336. if (!version_entry) {
  2337. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2338. __func__);
  2339. snd_info_free_entry(priv->entry);
  2340. return -ENOMEM;
  2341. }
  2342. version_entry->private_data = priv;
  2343. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2344. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2345. version_entry->c.ops = &wcd937x_info_ops;
  2346. if (snd_info_register(version_entry) < 0) {
  2347. snd_info_free_entry(version_entry);
  2348. snd_info_free_entry(priv->entry);
  2349. return -ENOMEM;
  2350. }
  2351. priv->version_entry = version_entry;
  2352. variant_entry = snd_info_create_card_entry(card->snd_card,
  2353. "variant",
  2354. priv->entry);
  2355. if (!variant_entry) {
  2356. dev_dbg(component->dev,
  2357. "%s: failed to create wcd937x variant entry\n",
  2358. __func__);
  2359. snd_info_free_entry(version_entry);
  2360. snd_info_free_entry(priv->entry);
  2361. return -ENOMEM;
  2362. }
  2363. variant_entry->private_data = priv;
  2364. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2365. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2366. variant_entry->c.ops = &wcd937x_variant_ops;
  2367. if (snd_info_register(variant_entry) < 0) {
  2368. snd_info_free_entry(variant_entry);
  2369. snd_info_free_entry(version_entry);
  2370. snd_info_free_entry(priv->entry);
  2371. return -ENOMEM;
  2372. }
  2373. priv->variant_entry = variant_entry;
  2374. return 0;
  2375. }
  2376. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2377. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2378. struct wcd937x_pdata *pdata)
  2379. {
  2380. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2381. int rc = 0;
  2382. if (!pdata) {
  2383. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2384. return -ENODEV;
  2385. }
  2386. /* set micbias voltage */
  2387. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2388. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2389. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2390. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2391. rc = -EINVAL;
  2392. goto done;
  2393. }
  2394. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2395. vout_ctl_1);
  2396. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2397. vout_ctl_2);
  2398. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2399. vout_ctl_3);
  2400. done:
  2401. return rc;
  2402. }
  2403. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2404. {
  2405. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2406. struct snd_soc_dapm_context *dapm =
  2407. snd_soc_component_get_dapm(component);
  2408. int variant;
  2409. int ret = -EINVAL;
  2410. dev_info(component->dev, "%s()\n", __func__);
  2411. wcd937x = snd_soc_component_get_drvdata(component);
  2412. if (!wcd937x)
  2413. return -EINVAL;
  2414. wcd937x->component = component;
  2415. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2416. variant = (snd_soc_component_read32(
  2417. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2418. wcd937x->variant = variant;
  2419. wcd937x->fw_data = devm_kzalloc(component->dev,
  2420. sizeof(*(wcd937x->fw_data)),
  2421. GFP_KERNEL);
  2422. if (!wcd937x->fw_data) {
  2423. dev_err(component->dev, "Failed to allocate fw_data\n");
  2424. ret = -ENOMEM;
  2425. goto err;
  2426. }
  2427. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2428. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2429. WCD9XXX_CODEC_HWDEP_NODE, component);
  2430. if (ret < 0) {
  2431. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2432. goto err_hwdep;
  2433. }
  2434. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2435. if (ret) {
  2436. pr_err("%s: mbhc initialization failed\n", __func__);
  2437. goto err_hwdep;
  2438. }
  2439. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2440. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2441. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2442. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2443. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2444. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2445. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2446. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2447. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2448. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2449. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2450. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2451. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2452. snd_soc_dapm_sync(dapm);
  2453. wcd_cls_h_init(&wcd937x->clsh_info);
  2454. wcd937x_init_reg(component);
  2455. if (wcd937x->variant == WCD9375_VARIANT) {
  2456. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2457. ARRAY_SIZE(wcd9375_dapm_widgets));
  2458. if (ret < 0) {
  2459. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2460. __func__);
  2461. goto err_hwdep;
  2462. }
  2463. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2464. ARRAY_SIZE(wcd9375_audio_map));
  2465. if (ret < 0) {
  2466. dev_err(component->dev, "%s: Failed to add routes\n",
  2467. __func__);
  2468. goto err_hwdep;
  2469. }
  2470. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2471. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2472. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2473. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2474. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2475. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2476. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2477. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2478. snd_soc_dapm_sync(dapm);
  2479. }
  2480. wcd937x->version = WCD937X_VERSION_1_0;
  2481. /* Register event notifier */
  2482. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2483. if (wcd937x->register_notifier) {
  2484. ret = wcd937x->register_notifier(wcd937x->handle,
  2485. &wcd937x->nblock,
  2486. true);
  2487. if (ret) {
  2488. dev_err(component->dev,
  2489. "%s: Failed to register notifier %d\n",
  2490. __func__, ret);
  2491. return ret;
  2492. }
  2493. }
  2494. return ret;
  2495. err_hwdep:
  2496. wcd937x->fw_data = NULL;
  2497. err:
  2498. return ret;
  2499. }
  2500. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2501. {
  2502. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2503. if (!wcd937x)
  2504. return;
  2505. if (wcd937x->register_notifier)
  2506. wcd937x->register_notifier(wcd937x->handle,
  2507. &wcd937x->nblock,
  2508. false);
  2509. return;
  2510. }
  2511. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2512. .name = WCD937X_DRV_NAME,
  2513. .probe = wcd937x_soc_codec_probe,
  2514. .remove = wcd937x_soc_codec_remove,
  2515. .controls = wcd937x_snd_controls,
  2516. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2517. .dapm_widgets = wcd937x_dapm_widgets,
  2518. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2519. .dapm_routes = wcd937x_audio_map,
  2520. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2521. };
  2522. #ifdef CONFIG_PM_SLEEP
  2523. static int wcd937x_suspend(struct device *dev)
  2524. {
  2525. struct wcd937x_priv *wcd937x = NULL;
  2526. int ret = 0;
  2527. struct wcd937x_pdata *pdata = NULL;
  2528. if (!dev)
  2529. return -ENODEV;
  2530. wcd937x = dev_get_drvdata(dev);
  2531. if (!wcd937x)
  2532. return -EINVAL;
  2533. pdata = dev_get_platdata(wcd937x->dev);
  2534. if (!pdata) {
  2535. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2536. return -EINVAL;
  2537. }
  2538. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2539. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2540. wcd937x->supplies,
  2541. pdata->regulator,
  2542. pdata->num_supplies,
  2543. "cdc-vdd-buck");
  2544. if (ret == -EINVAL) {
  2545. dev_err(dev, "%s: vdd buck is not disabled\n",
  2546. __func__);
  2547. return 0;
  2548. }
  2549. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2550. }
  2551. return 0;
  2552. }
  2553. static int wcd937x_resume(struct device *dev)
  2554. {
  2555. return 0;
  2556. }
  2557. #endif
  2558. static int wcd937x_reset(struct device *dev)
  2559. {
  2560. struct wcd937x_priv *wcd937x = NULL;
  2561. int rc = 0;
  2562. int value = 0;
  2563. if (!dev)
  2564. return -ENODEV;
  2565. wcd937x = dev_get_drvdata(dev);
  2566. if (!wcd937x)
  2567. return -EINVAL;
  2568. if (!wcd937x->rst_np) {
  2569. dev_err(dev, "%s: reset gpio device node not specified\n",
  2570. __func__);
  2571. return -EINVAL;
  2572. }
  2573. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2574. if (value > 0)
  2575. return 0;
  2576. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2577. if (rc) {
  2578. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2579. __func__);
  2580. return rc;
  2581. }
  2582. /* 20ms sleep required after pulling the reset gpio to LOW */
  2583. usleep_range(20, 30);
  2584. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2585. if (rc) {
  2586. dev_err(dev, "%s: wcd active state request fail!\n",
  2587. __func__);
  2588. return rc;
  2589. }
  2590. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2591. usleep_range(20, 30);
  2592. return rc;
  2593. }
  2594. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2595. u32 *val)
  2596. {
  2597. int rc = 0;
  2598. rc = of_property_read_u32(dev->of_node, name, val);
  2599. if (rc)
  2600. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2601. __func__, name, dev->of_node->full_name);
  2602. return rc;
  2603. }
  2604. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2605. struct wcd937x_micbias_setting *mb)
  2606. {
  2607. u32 prop_val = 0;
  2608. int rc = 0;
  2609. /* MB1 */
  2610. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2611. NULL)) {
  2612. rc = wcd937x_read_of_property_u32(dev,
  2613. "qcom,cdc-micbias1-mv",
  2614. &prop_val);
  2615. if (!rc)
  2616. mb->micb1_mv = prop_val;
  2617. } else {
  2618. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2619. __func__);
  2620. }
  2621. /* MB2 */
  2622. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2623. NULL)) {
  2624. rc = wcd937x_read_of_property_u32(dev,
  2625. "qcom,cdc-micbias2-mv",
  2626. &prop_val);
  2627. if (!rc)
  2628. mb->micb2_mv = prop_val;
  2629. } else {
  2630. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2631. __func__);
  2632. }
  2633. /* MB3 */
  2634. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2635. NULL)) {
  2636. rc = wcd937x_read_of_property_u32(dev,
  2637. "qcom,cdc-micbias3-mv",
  2638. &prop_val);
  2639. if (!rc)
  2640. mb->micb3_mv = prop_val;
  2641. } else {
  2642. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2643. __func__);
  2644. }
  2645. }
  2646. static int wcd937x_reset_low(struct device *dev)
  2647. {
  2648. struct wcd937x_priv *wcd937x = NULL;
  2649. int rc = 0;
  2650. if (!dev)
  2651. return -ENODEV;
  2652. wcd937x = dev_get_drvdata(dev);
  2653. if (!wcd937x)
  2654. return -EINVAL;
  2655. if (!wcd937x->rst_np) {
  2656. dev_err(dev, "%s: reset gpio device node not specified\n",
  2657. __func__);
  2658. return -EINVAL;
  2659. }
  2660. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2661. if (rc) {
  2662. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2663. __func__);
  2664. return rc;
  2665. }
  2666. /* 20ms sleep required after pulling the reset gpio to LOW */
  2667. usleep_range(20, 30);
  2668. return rc;
  2669. }
  2670. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2671. {
  2672. struct wcd937x_pdata *pdata = NULL;
  2673. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2674. GFP_KERNEL);
  2675. if (!pdata)
  2676. return NULL;
  2677. pdata->rst_np = of_parse_phandle(dev->of_node,
  2678. "qcom,wcd-rst-gpio-node", 0);
  2679. if (!pdata->rst_np) {
  2680. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2681. __func__, "qcom,wcd-rst-gpio-node",
  2682. dev->of_node->full_name);
  2683. return NULL;
  2684. }
  2685. /* Parse power supplies */
  2686. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2687. &pdata->num_supplies);
  2688. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2689. dev_err(dev, "%s: no power supplies defined for codec\n",
  2690. __func__);
  2691. return NULL;
  2692. }
  2693. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2694. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2695. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2696. return pdata;
  2697. }
  2698. static int wcd937x_wakeup(void *handle, bool enable)
  2699. {
  2700. struct wcd937x_priv *priv;
  2701. if (!handle) {
  2702. pr_err("%s: NULL handle\n", __func__);
  2703. return -EINVAL;
  2704. }
  2705. priv = (struct wcd937x_priv *)handle;
  2706. if (!priv->tx_swr_dev) {
  2707. pr_err("%s: tx swr dev is NULL\n", __func__);
  2708. return -EINVAL;
  2709. }
  2710. if (enable)
  2711. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2712. else
  2713. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2714. }
  2715. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2716. {
  2717. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2718. __func__, irq);
  2719. return IRQ_HANDLED;
  2720. }
  2721. static int wcd937x_bind(struct device *dev)
  2722. {
  2723. int ret = 0, i = 0;
  2724. struct wcd937x_priv *wcd937x = NULL;
  2725. struct wcd937x_pdata *pdata = NULL;
  2726. struct wcd_ctrl_platform_data *plat_data = NULL;
  2727. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2728. if (!wcd937x)
  2729. return -ENOMEM;
  2730. dev_set_drvdata(dev, wcd937x);
  2731. pdata = wcd937x_populate_dt_data(dev);
  2732. if (!pdata) {
  2733. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2734. return -EINVAL;
  2735. }
  2736. wcd937x->dev = dev;
  2737. wcd937x->dev->platform_data = pdata;
  2738. wcd937x->rst_np = pdata->rst_np;
  2739. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2740. pdata->regulator, pdata->num_supplies);
  2741. if (!wcd937x->supplies) {
  2742. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2743. __func__);
  2744. goto err_bind_all;
  2745. }
  2746. plat_data = dev_get_platdata(dev->parent);
  2747. if (!plat_data) {
  2748. dev_err(dev, "%s: platform data from parent is NULL\n",
  2749. __func__);
  2750. ret = -EINVAL;
  2751. goto err_bind_all;
  2752. }
  2753. wcd937x->handle = (void *)plat_data->handle;
  2754. if (!wcd937x->handle) {
  2755. dev_err(dev, "%s: handle is NULL\n", __func__);
  2756. ret = -EINVAL;
  2757. goto err_bind_all;
  2758. }
  2759. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2760. if (!wcd937x->update_wcd_event) {
  2761. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2762. __func__);
  2763. ret = -EINVAL;
  2764. goto err_bind_all;
  2765. }
  2766. wcd937x->register_notifier = plat_data->register_notifier;
  2767. if (!wcd937x->register_notifier) {
  2768. dev_err(dev, "%s: register_notifier api is null!\n",
  2769. __func__);
  2770. ret = -EINVAL;
  2771. goto err_bind_all;
  2772. }
  2773. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2774. pdata->regulator,
  2775. pdata->num_supplies);
  2776. if (ret) {
  2777. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2778. __func__);
  2779. goto err_bind_all;
  2780. }
  2781. wcd937x_reset(dev);
  2782. /*
  2783. * Add 5msec delay to provide sufficient time for
  2784. * soundwire auto enumeration of slave devices as
  2785. * as per HW requirement.
  2786. */
  2787. usleep_range(5000, 5010);
  2788. wcd937x->wakeup = wcd937x_wakeup;
  2789. ret = component_bind_all(dev, wcd937x);
  2790. if (ret) {
  2791. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2792. __func__, ret);
  2793. goto err_bind_all;
  2794. }
  2795. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2796. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2797. if (ret) {
  2798. dev_err(dev, "Failed to read port mapping\n");
  2799. goto err;
  2800. }
  2801. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2802. if (!wcd937x->rx_swr_dev) {
  2803. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2804. __func__);
  2805. ret = -ENODEV;
  2806. goto err;
  2807. }
  2808. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2809. if (!wcd937x->tx_swr_dev) {
  2810. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2811. __func__);
  2812. ret = -ENODEV;
  2813. goto err;
  2814. }
  2815. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2816. &wcd937x_regmap_config);
  2817. if (!wcd937x->regmap) {
  2818. dev_err(dev, "%s: Regmap init failed\n",
  2819. __func__);
  2820. goto err;
  2821. }
  2822. /* Set all interupts as edge triggered */
  2823. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2824. regmap_write(wcd937x->regmap,
  2825. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2826. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2827. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2828. wcd937x->irq_info.codec_name = "WCD937X";
  2829. wcd937x->irq_info.regmap = wcd937x->regmap;
  2830. wcd937x->irq_info.dev = dev;
  2831. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2832. if (ret) {
  2833. dev_err(dev, "%s: IRQ init failed: %d\n",
  2834. __func__, ret);
  2835. goto err;
  2836. }
  2837. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2838. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2839. if (ret < 0) {
  2840. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2841. goto err_irq;
  2842. }
  2843. /* default L1 power setting */
  2844. wcd937x->tx_ch_pwr[0] = 1;
  2845. wcd937x->tx_ch_pwr[1] = 1;
  2846. mutex_init(&wcd937x->micb_lock);
  2847. mutex_init(&wcd937x->ana_tx_clk_lock);
  2848. /* Request for watchdog interrupt */
  2849. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2850. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2851. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2852. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2853. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2854. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2855. /* Disable watchdog interrupt for HPH and AUX */
  2856. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2857. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2858. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2859. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2860. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2861. if (ret) {
  2862. dev_err(dev, "%s: Codec registration failed\n",
  2863. __func__);
  2864. goto err_irq;
  2865. }
  2866. return ret;
  2867. err_irq:
  2868. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2869. err:
  2870. component_unbind_all(dev, wcd937x);
  2871. err_bind_all:
  2872. dev_set_drvdata(dev, NULL);
  2873. kfree(pdata);
  2874. kfree(wcd937x);
  2875. return ret;
  2876. }
  2877. static void wcd937x_unbind(struct device *dev)
  2878. {
  2879. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2880. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2881. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2882. snd_soc_unregister_component(dev);
  2883. component_unbind_all(dev, wcd937x);
  2884. mutex_destroy(&wcd937x->micb_lock);
  2885. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2886. dev_set_drvdata(dev, NULL);
  2887. kfree(pdata);
  2888. kfree(wcd937x);
  2889. }
  2890. static const struct of_device_id wcd937x_dt_match[] = {
  2891. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2892. {}
  2893. };
  2894. static const struct component_master_ops wcd937x_comp_ops = {
  2895. .bind = wcd937x_bind,
  2896. .unbind = wcd937x_unbind,
  2897. };
  2898. static int wcd937x_compare_of(struct device *dev, void *data)
  2899. {
  2900. return dev->of_node == data;
  2901. }
  2902. static void wcd937x_release_of(struct device *dev, void *data)
  2903. {
  2904. of_node_put(data);
  2905. }
  2906. static int wcd937x_add_slave_components(struct device *dev,
  2907. struct component_match **matchptr)
  2908. {
  2909. struct device_node *np, *rx_node, *tx_node;
  2910. np = dev->of_node;
  2911. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2912. if (!rx_node) {
  2913. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2914. return -ENODEV;
  2915. }
  2916. of_node_get(rx_node);
  2917. component_match_add_release(dev, matchptr,
  2918. wcd937x_release_of,
  2919. wcd937x_compare_of,
  2920. rx_node);
  2921. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2922. if (!tx_node) {
  2923. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2924. return -ENODEV;
  2925. }
  2926. of_node_get(tx_node);
  2927. component_match_add_release(dev, matchptr,
  2928. wcd937x_release_of,
  2929. wcd937x_compare_of,
  2930. tx_node);
  2931. return 0;
  2932. }
  2933. static int wcd937x_probe(struct platform_device *pdev)
  2934. {
  2935. struct component_match *match = NULL;
  2936. int ret;
  2937. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2938. if (ret)
  2939. return ret;
  2940. return component_master_add_with_match(&pdev->dev,
  2941. &wcd937x_comp_ops, match);
  2942. }
  2943. static int wcd937x_remove(struct platform_device *pdev)
  2944. {
  2945. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2946. dev_set_drvdata(&pdev->dev, NULL);
  2947. return 0;
  2948. }
  2949. #ifdef CONFIG_PM_SLEEP
  2950. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2951. SET_SYSTEM_SLEEP_PM_OPS(
  2952. wcd937x_suspend,
  2953. wcd937x_resume
  2954. )
  2955. };
  2956. #endif
  2957. static struct platform_driver wcd937x_codec_driver = {
  2958. .probe = wcd937x_probe,
  2959. .remove = wcd937x_remove,
  2960. .driver = {
  2961. .name = "wcd937x_codec",
  2962. .owner = THIS_MODULE,
  2963. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2964. #ifdef CONFIG_PM_SLEEP
  2965. .pm = &wcd937x_dev_pm_ops,
  2966. #endif
  2967. .suppress_bind_attrs = true,
  2968. },
  2969. };
  2970. module_platform_driver(wcd937x_codec_driver);
  2971. MODULE_DESCRIPTION("WCD937X Codec driver");
  2972. MODULE_LICENSE("GPL v2");