bcd97aa368
CWB, DP and WB displays tear down sequence must reset 3d_merge, ctl, pingpong_binding, etc. MDP HW blocks. This change fixes the tear down sequence register programming. It also moves flush sw reset before encoder_disable call. That allows CWB tear down to update the flush configuration on primary ctl path. Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
535 linhas
16 KiB
C
535 linhas
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_CTL_H
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#define _SDE_HW_CTL_H
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#include "sde_hw_mdss.h"
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#include "sde_hw_util.h"
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#include "sde_hw_catalog.h"
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#include "sde_hw_sspp.h"
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#include "sde_hw_blk.h"
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#define INVALID_CTL_STATUS 0xfffff88e
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/**
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* sde_ctl_mode_sel: Interface mode selection
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* SDE_CTL_MODE_SEL_VID: Video mode interface
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* SDE_CTL_MODE_SEL_CMD: Command mode interface
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*/
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enum sde_ctl_mode_sel {
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SDE_CTL_MODE_SEL_VID = 0,
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SDE_CTL_MODE_SEL_CMD
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};
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/**
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* sde_ctl_rot_op_mode - inline rotation mode
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* SDE_CTL_ROT_OP_MODE_OFFLINE: offline rotation
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* SDE_CTL_ROT_OP_MODE_RESERVED: reserved
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* SDE_CTL_ROT_OP_MODE_INLINE_SYNC: inline rotation synchronous mode
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* SDE_CTL_ROT_OP_MODE_INLINE_ASYNC: inline rotation asynchronous mode
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*/
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enum sde_ctl_rot_op_mode {
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SDE_CTL_ROT_OP_MODE_OFFLINE,
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SDE_CTL_ROT_OP_MODE_RESERVED,
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SDE_CTL_ROT_OP_MODE_INLINE_SYNC,
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SDE_CTL_ROT_OP_MODE_INLINE_ASYNC,
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};
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struct sde_hw_ctl;
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/**
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* struct sde_hw_stage_cfg - blending stage cfg
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* @stage : SSPP_ID at each stage
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* @multirect_index: index of the rectangle of SSPP.
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*/
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struct sde_hw_stage_cfg {
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enum sde_sspp stage[SDE_STAGE_MAX][PIPES_PER_STAGE];
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enum sde_sspp_multirect_index multirect_index
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[SDE_STAGE_MAX][PIPES_PER_STAGE];
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};
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/**
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* struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface
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* @intf : Interface id
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* @wb: Writeback id
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* @mode_3d: 3d mux configuration
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* @intf_mode_sel: Interface mode, cmd / vid
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* @stream_sel: Stream selection for multi-stream interfaces
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*/
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struct sde_hw_intf_cfg {
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enum sde_intf intf;
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enum sde_wb wb;
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enum sde_3d_blend_mode mode_3d;
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enum sde_ctl_mode_sel intf_mode_sel;
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int stream_sel;
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};
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/**
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* struct sde_hw_intf_cfg_v1 :Describes the data strcuture to configure the
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* output interfaces for a particular display on a
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* platform which supports ctl path version 1.
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* @intf_count: No. of active interfaces for this display
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* @intf : Interface ids of active interfaces
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* @intf_mode_sel: Interface mode, cmd / vid
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* @intf_master: Master interface for split display
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* @wb_count: No. of active writebacks
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* @wb: Writeback ids of active writebacks
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* @merge_3d_count No. of active merge_3d blocks
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* @merge_3d: Id of the active merge 3d blocks
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* @cwb_count: No. of active concurrent writebacks
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* @cwb: Id of active cwb blocks
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* @cdm_count: No. of active chroma down module
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* @cdm: Id of active cdm blocks
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*/
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struct sde_hw_intf_cfg_v1 {
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uint32_t intf_count;
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enum sde_intf intf[MAX_INTF_PER_CTL_V1];
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enum sde_ctl_mode_sel intf_mode_sel;
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enum sde_intf intf_master;
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uint32_t wb_count;
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enum sde_wb wb[MAX_WB_PER_CTL_V1];
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uint32_t merge_3d_count;
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enum sde_merge_3d merge_3d[MAX_MERGE_3D_PER_CTL_V1];
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uint32_t cwb_count;
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enum sde_cwb cwb[MAX_CWB_PER_CTL_V1];
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uint32_t cdm_count;
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enum sde_cdm cdm[MAX_CDM_PER_CTL_V1];
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};
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/**
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* struct sde_hw_ctl_dsc_cfg :Describes the DSC blocks being used for this
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* display on a platoform which supports ctl path
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* version 1.
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* @dsc_count: No. of active dsc blocks
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* @dsc: Id of active dsc blocks
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*/
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struct sde_ctl_dsc_cfg {
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uint32_t dsc_count;
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enum sde_dsc dsc[MAX_DSC_PER_CTL_V1];
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};
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/**
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* struct sde_ctl_flush_cfg - struct describing flush configuration managed
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* via set, trigger and clear ops.
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* set ops corresponding to the hw_block is called, when the block's
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* configuration is changed and needs to be committed on Hw. Flush mask caches
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* the different bits for the ongoing commit.
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* clear ops clears the bitmask and cancels the update to the corresponding
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* hw block.
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* trigger op will trigger the update on the hw for the blocks cached in the
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* pending flush mask.
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*
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* @pending_flush_mask: pending ctl_flush
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* CTL path version SDE_CTL_CFG_VERSION_1_0_0 has * two level flush mechanism
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* for lower pipe controls. individual control should be flushed before
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* exercising top level flush
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* @pending_intf_flush_mask: pending INTF flush
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* @pending_cdm_flush_mask: pending CDWN block flush
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* @pending_wb_flush_mask: pending writeback flush
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* @pending_dsc_flush_mask: pending dsc flush
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* @pending_merge_3d_flush_mask: pending 3d merge block flush
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* @pending_cwb_flush_mask: pending flush for concurrent writeback
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* @pending_periph_flush_mask: pending flush for peripheral module
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*/
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struct sde_ctl_flush_cfg {
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u32 pending_flush_mask;
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u32 pending_intf_flush_mask;
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u32 pending_cdm_flush_mask;
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u32 pending_wb_flush_mask;
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u32 pending_dsc_flush_mask;
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u32 pending_merge_3d_flush_mask;
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u32 pending_cwb_flush_mask;
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u32 pending_periph_flush_mask;
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};
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/**
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* struct sde_hw_ctl_ops - Interface to the wb Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct sde_hw_ctl_ops {
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/**
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* kickoff hw operation for Sw controlled interfaces
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* DSI cmd mode and WB interface are SW controlled
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* @ctx : ctl path ctx pointer
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* @Return: error code
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*/
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int (*trigger_start)(struct sde_hw_ctl *ctx);
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/**
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* kickoff prepare is in progress hw operation for sw
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* controlled interfaces: DSI cmd mode and WB interface
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* are SW controlled
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* @ctx : ctl path ctx pointer
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* @Return: error code
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*/
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int (*trigger_pending)(struct sde_hw_ctl *ctx);
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/**
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* kickoff rotator operation for Sw controlled interfaces
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* DSI cmd mode and WB interface are SW controlled
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* @ctx : ctl path ctx pointer
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* @Return: error code
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*/
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int (*trigger_rot_start)(struct sde_hw_ctl *ctx);
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/**
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* enable/disable UIDLE feature
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* @ctx : ctl path ctx pointer
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* @enable: true to enable the feature
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*/
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void (*uidle_enable)(struct sde_hw_ctl *ctx, bool enable);
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/**
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* Clear the value of the cached pending_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @Return: error code
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*/
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int (*clear_pending_flush)(struct sde_hw_ctl *ctx);
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/**
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* Query the value of the cached pending_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @cfg : current flush configuration
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* @Return: error code
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*/
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int (*get_pending_flush)(struct sde_hw_ctl *ctx,
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struct sde_ctl_flush_cfg *cfg);
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/**
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* OR in the given flushbits to the flush_cfg
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @cfg : flush configuration pointer
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* @Return: error code
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*/
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int (*update_pending_flush)(struct sde_hw_ctl *ctx,
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struct sde_ctl_flush_cfg *cfg);
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/**
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* Write the value of the pending_flush_mask to hardware
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* @ctx : ctl path ctx pointer
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* @Return: error code
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*/
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int (*trigger_flush)(struct sde_hw_ctl *ctx);
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/**
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* Read the value of the flush register
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* @ctx : ctl path ctx pointer
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* @Return: value of the ctl flush register.
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*/
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u32 (*get_flush_register)(struct sde_hw_ctl *ctx);
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/**
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* Setup ctl_path interface config
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* @ctx
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* @cfg : interface config structure pointer
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* @Return: error code
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*/
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int (*setup_intf_cfg)(struct sde_hw_ctl *ctx,
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struct sde_hw_intf_cfg *cfg);
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/**
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* Reset ctl_path interface config
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* @ctx : ctl path ctx pointer
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* @cfg : interface config structure pointer
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* @merge_3d_idx : index of merge3d blk
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* @Return: error code
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*/
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int (*reset_post_disable)(struct sde_hw_ctl *ctx,
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struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx);
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/** update cwb for ctl_path
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* @ctx : ctl path ctx pointer
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* @cfg : interface config structure pointer
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* @enable : enable/disable the cwb hw block
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* @Return: error code
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*/
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int (*update_cwb_cfg)(struct sde_hw_ctl *ctx,
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struct sde_hw_intf_cfg_v1 *cfg, bool enable);
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/**
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* Setup ctl_path interface config for SDE_CTL_ACTIVE_CFG
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* @ctx : ctl path ctx pointer
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* @cfg : interface config structure pointer
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* @Return: error code
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*/
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int (*setup_intf_cfg_v1)(struct sde_hw_ctl *ctx,
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struct sde_hw_intf_cfg_v1 *cfg);
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/**
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* Setup ctl_path dsc config for SDE_CTL_ACTIVE_CFG
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* @ctx : ctl path ctx pointer
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* @cfg : dsc config structure pointer
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* @Return: error code
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*/
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int (*setup_dsc_cfg)(struct sde_hw_ctl *ctx,
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struct sde_ctl_dsc_cfg *cfg);
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/** Update the interface selection with input WB config
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* @ctx : ctl path ctx pointer
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* @cfg : pointer to input wb config
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* @enable : set if true, clear otherwise
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*/
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void (*update_wb_cfg)(struct sde_hw_ctl *ctx,
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struct sde_hw_intf_cfg *cfg, bool enable);
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int (*reset)(struct sde_hw_ctl *c);
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/**
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* get_reset - check ctl reset status bit
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* @ctx : ctl path ctx pointer
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* Returns: current value of ctl reset status
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*/
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u32 (*get_reset)(struct sde_hw_ctl *ctx);
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/**
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* get_scheduler_reset - check ctl scheduler status bit
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* @ctx : ctl path ctx pointer
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* Returns: current value of ctl scheduler and idle status
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*/
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u32 (*get_scheduler_status)(struct sde_hw_ctl *ctx);
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/**
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* hard_reset - force reset on ctl_path
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* @ctx : ctl path ctx pointer
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* @enable : whether to enable/disable hard reset
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*/
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void (*hard_reset)(struct sde_hw_ctl *c, bool enable);
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/*
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* wait_reset_status - checks ctl reset status
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* @ctx : ctl path ctx pointer
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*
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* This function checks the ctl reset status bit.
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* If the reset bit is set, it keeps polling the status till the hw
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* reset is complete.
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* Returns: 0 on success or -error if reset incomplete within interval
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*/
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int (*wait_reset_status)(struct sde_hw_ctl *ctx);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_sspp)(struct sde_hw_ctl *ctx,
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enum sde_sspp blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_mixer)(struct sde_hw_ctl *ctx,
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enum sde_lm blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_dspp)(struct sde_hw_ctl *ctx,
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enum sde_dspp blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_dspp_pavlut)(struct sde_hw_ctl *ctx,
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enum sde_dspp blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_intf)(struct sde_hw_ctl *ctx,
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enum sde_intf blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_cdm)(struct sde_hw_ctl *ctx,
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enum sde_cdm blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_wb)(struct sde_hw_ctl *ctx,
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enum sde_wb blk, bool enable);
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/**
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* update_bitmask_sspp: updates mask corresponding to sspp
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_rot)(struct sde_hw_ctl *ctx,
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enum sde_rot blk, bool enable);
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/**
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* update_bitmask_dsc: updates mask corresponding to dsc
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_dsc)(struct sde_hw_ctl *ctx,
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enum sde_dsc blk, bool enable);
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/**
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* update_bitmask_merge3d: updates mask corresponding to merge_3d
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_merge3d)(struct sde_hw_ctl *ctx,
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enum sde_merge_3d blk, bool enable);
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/**
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* update_bitmask_cwb: updates mask corresponding to cwb
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_cwb)(struct sde_hw_ctl *ctx,
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enum sde_cwb blk, bool enable);
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/**
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* update_bitmask_periph: updates mask corresponding to peripheral
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* @blk : blk id
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* @enable : true to enable, 0 to disable
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*/
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int (*update_bitmask_periph)(struct sde_hw_ctl *ctx,
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enum sde_intf blk, bool enable);
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/**
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* read CTL_TOP register value and return
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* the data.
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* @ctx : ctl path ctx pointer
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* @return : CTL top register value
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*/
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u32 (*read_ctl_top)(struct sde_hw_ctl *ctx);
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/**
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* get interfaces for the active CTL .
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* @ctx : ctl path ctx pointer
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* @return : bit mask with the active interfaces for the CTL
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*/
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u32 (*get_ctl_intf)(struct sde_hw_ctl *ctx);
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/**
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* read CTL layers register value and return
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* the data.
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* @ctx : ctl path ctx pointer
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* @index : layer index for this ctl path
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* @return : CTL layers register value
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*/
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u32 (*read_ctl_layers)(struct sde_hw_ctl *ctx, int index);
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/**
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* Set all blend stages to disabled
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* @ctx : ctl path ctx pointer
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*/
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void (*clear_all_blendstages)(struct sde_hw_ctl *ctx);
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/**
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* Configure layer mixer to pipe configuration
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* @ctx : ctl path ctx pointer
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* @lm : layer mixer enumeration
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* @cfg : blend stage configuration
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*/
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void (*setup_blendstage)(struct sde_hw_ctl *ctx,
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enum sde_lm lm, struct sde_hw_stage_cfg *cfg);
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/**
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* Get all the sspp staged on a layer mixer
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* @ctx : ctl path ctx pointer
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* @lm : layer mixer enumeration
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* @info : array address to populate connected sspp index info
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* @info_max_cnt : maximum sspp info elements based on array size
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* @Return: count of sspps info elements populated
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*/
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u32 (*get_staged_sspp)(struct sde_hw_ctl *ctx, enum sde_lm lm,
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struct sde_sspp_index_info *info, u32 info_max_cnt);
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/**
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* Flush the reg dma by sending last command.
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* @ctx : ctl path ctx pointer
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* @blocking : if set to true api will block until flush is done
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* @Return: error code
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*/
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int (*reg_dma_flush)(struct sde_hw_ctl *ctx, bool blocking);
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/**
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* check if ctl start trigger state to confirm the frame pending
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* status
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* @ctx : ctl path ctx pointer
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* @Return: error code
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*/
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int (*get_start_state)(struct sde_hw_ctl *ctx);
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};
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/**
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* struct sde_hw_ctl : CTL PATH driver object
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* @base: hardware block base structure
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* @hw: block register map object
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* @idx: control path index
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* @caps: control path capabilities
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* @mixer_count: number of mixers
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* @mixer_hw_caps: mixer hardware capabilities
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* @flush: storage for pending ctl_flush managed via ops
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* @ops: operation list
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*/
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struct sde_hw_ctl {
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struct sde_hw_blk base;
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struct sde_hw_blk_reg_map hw;
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/* ctl path */
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int idx;
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const struct sde_ctl_cfg *caps;
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int mixer_count;
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const struct sde_lm_cfg *mixer_hw_caps;
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struct sde_ctl_flush_cfg flush;
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/* ops */
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struct sde_hw_ctl_ops ops;
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};
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/**
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* sde_hw_ctl - convert base object sde_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct sde_hw_ctl *to_sde_hw_ctl(struct sde_hw_blk *hw)
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{
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return container_of(hw, struct sde_hw_ctl, base);
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}
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/**
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* sde_hw_ctl_init(): Initializes the ctl_path hw driver object.
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* should be called before accessing every ctl path registers.
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* @idx: ctl_path index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m);
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/**
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* sde_hw_ctl_destroy(): Destroys ctl driver context
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* should be called to free the context
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*/
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void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx);
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#endif /*_SDE_HW_CTL_H */
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