dp_tx.c 142 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef QCA_TX_LIMIT_CHECK
  71. /**
  72. * dp_tx_limit_check - Check if allocated tx descriptors reached
  73. * soc max limit and pdev max limit
  74. * @vdev: DP vdev handle
  75. *
  76. * Return: true if allocated tx descriptors reached max configured value, else
  77. * false
  78. */
  79. static inline bool
  80. dp_tx_limit_check(struct dp_vdev *vdev)
  81. {
  82. struct dp_pdev *pdev = vdev->pdev;
  83. struct dp_soc *soc = pdev->soc;
  84. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  85. soc->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  93. pdev->num_tx_allowed) {
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  95. "%s: queued packets are more than max tx, drop the frame",
  96. __func__);
  97. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  98. return true;
  99. }
  100. return false;
  101. }
  102. /**
  103. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  104. * reached soc max limit
  105. * @vdev: DP vdev handle
  106. *
  107. * Return: true if allocated tx descriptors reached max configured value, else
  108. * false
  109. */
  110. static inline bool
  111. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  112. {
  113. struct dp_pdev *pdev = vdev->pdev;
  114. struct dp_soc *soc = pdev->soc;
  115. if (qdf_atomic_read(&soc->num_tx_exception) >=
  116. soc->num_msdu_exception_desc) {
  117. dp_info("exc packets are more than max drop the exc pkt");
  118. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  125. * @vdev: DP pdev handle
  126. *
  127. * Return: void
  128. */
  129. static inline void
  130. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  131. {
  132. struct dp_soc *soc = pdev->soc;
  133. qdf_atomic_inc(&pdev->num_tx_outstanding);
  134. qdf_atomic_inc(&soc->num_tx_outstanding);
  135. }
  136. /**
  137. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  138. * @vdev: DP pdev handle
  139. *
  140. * Return: void
  141. */
  142. static inline void
  143. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  144. {
  145. struct dp_soc *soc = pdev->soc;
  146. qdf_atomic_dec(&pdev->num_tx_outstanding);
  147. qdf_atomic_dec(&soc->num_tx_outstanding);
  148. }
  149. #else //QCA_TX_LIMIT_CHECK
  150. static inline bool
  151. dp_tx_limit_check(struct dp_vdev *vdev)
  152. {
  153. return false;
  154. }
  155. static inline bool
  156. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  157. {
  158. return false;
  159. }
  160. static inline void
  161. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  162. {
  163. qdf_atomic_inc(&pdev->num_tx_outstanding);
  164. }
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. }
  170. #endif //QCA_TX_LIMIT_CHECK
  171. #if defined(FEATURE_TSO)
  172. /**
  173. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  174. *
  175. * @soc - core txrx main context
  176. * @seg_desc - tso segment descriptor
  177. * @num_seg_desc - tso number segment descriptor
  178. */
  179. static void dp_tx_tso_unmap_segment(
  180. struct dp_soc *soc,
  181. struct qdf_tso_seg_elem_t *seg_desc,
  182. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  183. {
  184. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  185. if (qdf_unlikely(!seg_desc)) {
  186. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  187. __func__, __LINE__);
  188. qdf_assert(0);
  189. } else if (qdf_unlikely(!num_seg_desc)) {
  190. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. bool is_last_seg;
  195. /* no tso segment left to do dma unmap */
  196. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  197. return;
  198. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  199. true : false;
  200. qdf_nbuf_unmap_tso_segment(soc->osdev,
  201. seg_desc, is_last_seg);
  202. num_seg_desc->num_seg.tso_cmn_num_seg--;
  203. }
  204. }
  205. /**
  206. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  207. * back to the freelist
  208. *
  209. * @soc - soc device handle
  210. * @tx_desc - Tx software descriptor
  211. */
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  216. if (qdf_unlikely(!tx_desc->tso_desc)) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "%s %d TSO desc is NULL!",
  219. __func__, __LINE__);
  220. qdf_assert(0);
  221. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  223. "%s %d TSO num desc is NULL!",
  224. __func__, __LINE__);
  225. qdf_assert(0);
  226. } else {
  227. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  228. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  229. /* Add the tso num segment into the free list */
  230. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  231. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  232. tx_desc->tso_num_desc);
  233. tx_desc->tso_num_desc = NULL;
  234. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  235. }
  236. /* Add the tso segment into the free list*/
  237. dp_tx_tso_desc_free(soc,
  238. tx_desc->pool_id, tx_desc->tso_desc);
  239. tx_desc->tso_desc = NULL;
  240. }
  241. }
  242. #else
  243. static void dp_tx_tso_unmap_segment(
  244. struct dp_soc *soc,
  245. struct qdf_tso_seg_elem_t *seg_desc,
  246. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  247. {
  248. }
  249. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  250. struct dp_tx_desc_s *tx_desc)
  251. {
  252. }
  253. #endif
  254. /**
  255. * dp_tx_desc_release() - Release Tx Descriptor
  256. * @tx_desc : Tx Descriptor
  257. * @desc_pool_id: Descriptor Pool ID
  258. *
  259. * Deallocate all resources attached to Tx descriptor and free the Tx
  260. * descriptor.
  261. *
  262. * Return:
  263. */
  264. static void
  265. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  266. {
  267. struct dp_pdev *pdev = tx_desc->pdev;
  268. struct dp_soc *soc;
  269. uint8_t comp_status = 0;
  270. qdf_assert(pdev);
  271. soc = pdev->soc;
  272. dp_tx_outstanding_dec(pdev);
  273. if (tx_desc->frm_type == dp_tx_frm_tso)
  274. dp_tx_tso_desc_release(soc, tx_desc);
  275. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  276. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  277. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  278. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  279. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  280. qdf_atomic_dec(&soc->num_tx_exception);
  281. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  282. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  283. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  284. soc->hal_soc);
  285. else
  286. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  288. "Tx Completion Release desc %d status %d outstanding %d",
  289. tx_desc->id, comp_status,
  290. qdf_atomic_read(&pdev->num_tx_outstanding));
  291. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  292. return;
  293. }
  294. /**
  295. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  296. * @vdev: DP vdev Handle
  297. * @nbuf: skb
  298. * @msdu_info: msdu_info required to create HTT metadata
  299. *
  300. * Prepares and fills HTT metadata in the frame pre-header for special frames
  301. * that should be transmitted using varying transmit parameters.
  302. * There are 2 VDEV modes that currently needs this special metadata -
  303. * 1) Mesh Mode
  304. * 2) DSRC Mode
  305. *
  306. * Return: HTT metadata size
  307. *
  308. */
  309. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  310. struct dp_tx_msdu_info_s *msdu_info)
  311. {
  312. uint32_t *meta_data = msdu_info->meta_data;
  313. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  314. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  315. uint8_t htt_desc_size;
  316. /* Size rounded of multiple of 8 bytes */
  317. uint8_t htt_desc_size_aligned;
  318. uint8_t *hdr = NULL;
  319. /*
  320. * Metadata - HTT MSDU Extension header
  321. */
  322. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  323. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  324. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  325. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  326. meta_data[0])) {
  327. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  328. htt_desc_size_aligned)) {
  329. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  330. htt_desc_size_aligned);
  331. if (!nbuf) {
  332. /*
  333. * qdf_nbuf_realloc_headroom won't do skb_clone
  334. * as skb_realloc_headroom does. so, no free is
  335. * needed here.
  336. */
  337. DP_STATS_INC(vdev,
  338. tx_i.dropped.headroom_insufficient,
  339. 1);
  340. qdf_print(" %s[%d] skb_realloc_headroom failed",
  341. __func__, __LINE__);
  342. return 0;
  343. }
  344. }
  345. /* Fill and add HTT metaheader */
  346. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  347. if (!hdr) {
  348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  349. "Error in filling HTT metadata");
  350. return 0;
  351. }
  352. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  353. } else if (vdev->opmode == wlan_op_mode_ocb) {
  354. /* Todo - Add support for DSRC */
  355. }
  356. return htt_desc_size_aligned;
  357. }
  358. /**
  359. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  360. * @tso_seg: TSO segment to process
  361. * @ext_desc: Pointer to MSDU extension descriptor
  362. *
  363. * Return: void
  364. */
  365. #if defined(FEATURE_TSO)
  366. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  367. void *ext_desc)
  368. {
  369. uint8_t num_frag;
  370. uint32_t tso_flags;
  371. /*
  372. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  373. * tcp_flag_mask
  374. *
  375. * Checksum enable flags are set in TCL descriptor and not in Extension
  376. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  377. */
  378. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  379. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  380. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  381. tso_seg->tso_flags.ip_len);
  382. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  383. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  384. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  385. uint32_t lo = 0;
  386. uint32_t hi = 0;
  387. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  388. (tso_seg->tso_frags[num_frag].length));
  389. qdf_dmaaddr_to_32s(
  390. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  391. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  392. tso_seg->tso_frags[num_frag].length);
  393. }
  394. return;
  395. }
  396. #else
  397. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  398. void *ext_desc)
  399. {
  400. return;
  401. }
  402. #endif
  403. #if defined(FEATURE_TSO)
  404. /**
  405. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  406. * allocated and free them
  407. *
  408. * @soc: soc handle
  409. * @free_seg: list of tso segments
  410. * @msdu_info: msdu descriptor
  411. *
  412. * Return - void
  413. */
  414. static void dp_tx_free_tso_seg_list(
  415. struct dp_soc *soc,
  416. struct qdf_tso_seg_elem_t *free_seg,
  417. struct dp_tx_msdu_info_s *msdu_info)
  418. {
  419. struct qdf_tso_seg_elem_t *next_seg;
  420. while (free_seg) {
  421. next_seg = free_seg->next;
  422. dp_tx_tso_desc_free(soc,
  423. msdu_info->tx_queue.desc_pool_id,
  424. free_seg);
  425. free_seg = next_seg;
  426. }
  427. }
  428. /**
  429. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  430. * allocated and free them
  431. *
  432. * @soc: soc handle
  433. * @free_num_seg: list of tso number segments
  434. * @msdu_info: msdu descriptor
  435. * Return - void
  436. */
  437. static void dp_tx_free_tso_num_seg_list(
  438. struct dp_soc *soc,
  439. struct qdf_tso_num_seg_elem_t *free_num_seg,
  440. struct dp_tx_msdu_info_s *msdu_info)
  441. {
  442. struct qdf_tso_num_seg_elem_t *next_num_seg;
  443. while (free_num_seg) {
  444. next_num_seg = free_num_seg->next;
  445. dp_tso_num_seg_free(soc,
  446. msdu_info->tx_queue.desc_pool_id,
  447. free_num_seg);
  448. free_num_seg = next_num_seg;
  449. }
  450. }
  451. /**
  452. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  453. * do dma unmap for each segment
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @num_seg_desc: tso number segment descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_unmap_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. if (qdf_unlikely(!num_seg_desc)) {
  468. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  469. return;
  470. }
  471. while (free_seg) {
  472. next_seg = free_seg->next;
  473. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  474. free_seg = next_seg;
  475. }
  476. }
  477. #ifdef FEATURE_TSO_STATS
  478. /**
  479. * dp_tso_get_stats_idx: Retrieve the tso packet id
  480. * @pdev - pdev handle
  481. *
  482. * Return: id
  483. */
  484. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  485. {
  486. uint32_t stats_idx;
  487. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  488. % CDP_MAX_TSO_PACKETS);
  489. return stats_idx;
  490. }
  491. #else
  492. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  493. {
  494. return 0;
  495. }
  496. #endif /* FEATURE_TSO_STATS */
  497. /**
  498. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  499. * free the tso segments descriptor and
  500. * tso num segments descriptor
  501. *
  502. * @soc: soc handle
  503. * @msdu_info: msdu descriptor
  504. * @tso_seg_unmap: flag to show if dma unmap is necessary
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  509. struct dp_tx_msdu_info_s *msdu_info,
  510. bool tso_seg_unmap)
  511. {
  512. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  513. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  514. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  515. tso_info->tso_num_seg_list;
  516. /* do dma unmap for each segment */
  517. if (tso_seg_unmap)
  518. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  519. /* free all tso number segment descriptor though looks only have 1 */
  520. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  521. /* free all tso segment descriptor */
  522. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  523. }
  524. /**
  525. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  526. * @vdev: virtual device handle
  527. * @msdu: network buffer
  528. * @msdu_info: meta data associated with the msdu
  529. *
  530. * Return: QDF_STATUS_SUCCESS success
  531. */
  532. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  533. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  534. {
  535. struct qdf_tso_seg_elem_t *tso_seg;
  536. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  537. struct dp_soc *soc = vdev->pdev->soc;
  538. struct dp_pdev *pdev = vdev->pdev;
  539. struct qdf_tso_info_t *tso_info;
  540. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  541. tso_info = &msdu_info->u.tso_info;
  542. tso_info->curr_seg = NULL;
  543. tso_info->tso_seg_list = NULL;
  544. tso_info->num_segs = num_seg;
  545. msdu_info->frm_type = dp_tx_frm_tso;
  546. tso_info->tso_num_seg_list = NULL;
  547. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  548. while (num_seg) {
  549. tso_seg = dp_tx_tso_desc_alloc(
  550. soc, msdu_info->tx_queue.desc_pool_id);
  551. if (tso_seg) {
  552. tso_seg->next = tso_info->tso_seg_list;
  553. tso_info->tso_seg_list = tso_seg;
  554. num_seg--;
  555. } else {
  556. dp_err_rl("Failed to alloc tso seg desc");
  557. DP_STATS_INC_PKT(vdev->pdev,
  558. tso_stats.tso_no_mem_dropped, 1,
  559. qdf_nbuf_len(msdu));
  560. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  561. return QDF_STATUS_E_NOMEM;
  562. }
  563. }
  564. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  565. tso_num_seg = dp_tso_num_seg_alloc(soc,
  566. msdu_info->tx_queue.desc_pool_id);
  567. if (tso_num_seg) {
  568. tso_num_seg->next = tso_info->tso_num_seg_list;
  569. tso_info->tso_num_seg_list = tso_num_seg;
  570. } else {
  571. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  572. __func__);
  573. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  574. return QDF_STATUS_E_NOMEM;
  575. }
  576. msdu_info->num_seg =
  577. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  578. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  579. msdu_info->num_seg);
  580. if (!(msdu_info->num_seg)) {
  581. /*
  582. * Free allocated TSO seg desc and number seg desc,
  583. * do unmap for segments if dma map has done.
  584. */
  585. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  586. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  587. return QDF_STATUS_E_INVAL;
  588. }
  589. tso_info->curr_seg = tso_info->tso_seg_list;
  590. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  591. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  592. msdu, msdu_info->num_seg);
  593. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  594. tso_info->msdu_stats_idx);
  595. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  596. return QDF_STATUS_SUCCESS;
  597. }
  598. #else
  599. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  600. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  601. {
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. #endif
  605. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  606. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  607. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  608. /**
  609. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  610. * @vdev: DP Vdev handle
  611. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  612. * @desc_pool_id: Descriptor Pool ID
  613. *
  614. * Return:
  615. */
  616. static
  617. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  618. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  619. {
  620. uint8_t i;
  621. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  622. struct dp_tx_seg_info_s *seg_info;
  623. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  624. struct dp_soc *soc = vdev->pdev->soc;
  625. /* Allocate an extension descriptor */
  626. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  627. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  628. if (!msdu_ext_desc) {
  629. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  630. return NULL;
  631. }
  632. if (msdu_info->exception_fw &&
  633. qdf_unlikely(vdev->mesh_vdev)) {
  634. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  635. &msdu_info->meta_data[0],
  636. sizeof(struct htt_tx_msdu_desc_ext2_t));
  637. qdf_atomic_inc(&soc->num_tx_exception);
  638. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  639. }
  640. switch (msdu_info->frm_type) {
  641. case dp_tx_frm_sg:
  642. case dp_tx_frm_me:
  643. case dp_tx_frm_raw:
  644. seg_info = msdu_info->u.sg_info.curr_seg;
  645. /* Update the buffer pointers in MSDU Extension Descriptor */
  646. for (i = 0; i < seg_info->frag_cnt; i++) {
  647. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  648. seg_info->frags[i].paddr_lo,
  649. seg_info->frags[i].paddr_hi,
  650. seg_info->frags[i].len);
  651. }
  652. break;
  653. case dp_tx_frm_tso:
  654. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  655. &cached_ext_desc[0]);
  656. break;
  657. default:
  658. break;
  659. }
  660. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  661. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  662. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  663. msdu_ext_desc->vaddr);
  664. return msdu_ext_desc;
  665. }
  666. /**
  667. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  668. *
  669. * @skb: skb to be traced
  670. * @msdu_id: msdu_id of the packet
  671. * @vdev_id: vdev_id of the packet
  672. *
  673. * Return: None
  674. */
  675. #ifdef DP_DISABLE_TX_PKT_TRACE
  676. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  677. uint8_t vdev_id)
  678. {
  679. }
  680. #else
  681. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  682. uint8_t vdev_id)
  683. {
  684. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  685. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  686. DPTRACE(qdf_dp_trace_ptr(skb,
  687. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  688. QDF_TRACE_DEFAULT_PDEV_ID,
  689. qdf_nbuf_data_addr(skb),
  690. sizeof(qdf_nbuf_data(skb)),
  691. msdu_id, vdev_id));
  692. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  693. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  694. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  695. msdu_id, QDF_TX));
  696. }
  697. #endif
  698. #ifdef QCA_SUPPORT_WDS_EXTENDED
  699. /**
  700. * dp_is_tx_extended() - Configure AST override from peer ast entry
  701. *
  702. * @vdev: DP vdev handle
  703. * @tx_exc_metadata: Handle that holds exception path metadata
  704. *
  705. * Return: if this packet needs to exception to FW or not
  706. * (false: exception to wlan FW, true: do not exception)
  707. */
  708. static inline bool
  709. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  710. *tx_exc_metadata)
  711. {
  712. if (qdf_likely(!vdev->wds_ext_enabled))
  713. return false;
  714. if (tx_exc_metadata && !tx_exc_metadata->is_wds_extended)
  715. return false;
  716. return true;
  717. }
  718. /**
  719. * dp_tx_wds_ext() - Configure AST override from peer ast entry
  720. *
  721. * @soc: DP soc handle
  722. * @vdev: DP vdev handle
  723. * @peer_id: peer_id of the peer for which packet is destined
  724. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  725. *
  726. * Return: None
  727. */
  728. static inline void
  729. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  730. struct dp_tx_msdu_info_s *msdu_info)
  731. {
  732. struct dp_peer *peer = NULL;
  733. msdu_info->search_type = vdev->search_type;
  734. msdu_info->ast_idx = vdev->bss_ast_idx;
  735. msdu_info->ast_hash = vdev->bss_ast_hash;
  736. if (qdf_likely(!vdev->wds_ext_enabled))
  737. return;
  738. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_TX);
  739. if (qdf_unlikely(!peer))
  740. return;
  741. msdu_info->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  742. msdu_info->ast_idx = peer->self_ast_entry->ast_idx;
  743. msdu_info->ast_hash = peer->self_ast_entry->ast_hash_value;
  744. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  745. msdu_info->exception_fw = 0;
  746. }
  747. #else
  748. static inline bool
  749. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  750. *tx_exc_metadata)
  751. {
  752. return false;
  753. }
  754. static inline void
  755. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  756. struct dp_tx_msdu_info_s *msdu_info)
  757. {
  758. msdu_info->search_type = vdev->search_type;
  759. msdu_info->ast_idx = vdev->bss_ast_idx;
  760. msdu_info->ast_hash = vdev->bss_ast_hash;
  761. }
  762. #endif
  763. /**
  764. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  765. * @vdev: DP vdev handle
  766. * @nbuf: skb
  767. * @desc_pool_id: Descriptor pool ID
  768. * @meta_data: Metadata to the fw
  769. * @tx_exc_metadata: Handle that holds exception path metadata
  770. * Allocate and prepare Tx descriptor with msdu information.
  771. *
  772. * Return: Pointer to Tx Descriptor on success,
  773. * NULL on failure
  774. */
  775. static
  776. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  777. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  778. struct dp_tx_msdu_info_s *msdu_info,
  779. struct cdp_tx_exception_metadata *tx_exc_metadata)
  780. {
  781. uint8_t align_pad;
  782. uint8_t is_exception = 0;
  783. uint8_t htt_hdr_size;
  784. struct dp_tx_desc_s *tx_desc;
  785. struct dp_pdev *pdev = vdev->pdev;
  786. struct dp_soc *soc = pdev->soc;
  787. if (dp_tx_limit_check(vdev))
  788. return NULL;
  789. /* Allocate software Tx descriptor */
  790. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  791. if (qdf_unlikely(!tx_desc)) {
  792. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  793. return NULL;
  794. }
  795. dp_tx_outstanding_inc(pdev);
  796. /* Initialize the SW tx descriptor */
  797. tx_desc->nbuf = nbuf;
  798. tx_desc->frm_type = dp_tx_frm_std;
  799. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  800. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  801. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  802. tx_desc->vdev_id = vdev->vdev_id;
  803. tx_desc->pdev = pdev;
  804. tx_desc->msdu_ext_desc = NULL;
  805. tx_desc->pkt_offset = 0;
  806. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  807. if (qdf_unlikely(vdev->multipass_en)) {
  808. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  809. goto failure;
  810. }
  811. if (qdf_unlikely(dp_is_tx_extended(vdev, tx_exc_metadata)))
  812. return tx_desc;
  813. /*
  814. * For special modes (vdev_type == ocb or mesh), data frames should be
  815. * transmitted using varying transmit parameters (tx spec) which include
  816. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  817. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  818. * These frames are sent as exception packets to firmware.
  819. *
  820. * HW requirement is that metadata should always point to a
  821. * 8-byte aligned address. So we add alignment pad to start of buffer.
  822. * HTT Metadata should be ensured to be multiple of 8-bytes,
  823. * to get 8-byte aligned start address along with align_pad added
  824. *
  825. * |-----------------------------|
  826. * | |
  827. * |-----------------------------| <-----Buffer Pointer Address given
  828. * | | ^ in HW descriptor (aligned)
  829. * | HTT Metadata | |
  830. * | | |
  831. * | | | Packet Offset given in descriptor
  832. * | | |
  833. * |-----------------------------| |
  834. * | Alignment Pad | v
  835. * |-----------------------------| <----- Actual buffer start address
  836. * | SKB Data | (Unaligned)
  837. * | |
  838. * | |
  839. * | |
  840. * | |
  841. * | |
  842. * |-----------------------------|
  843. */
  844. if (qdf_unlikely((msdu_info->exception_fw)) ||
  845. (vdev->opmode == wlan_op_mode_ocb) ||
  846. (tx_exc_metadata &&
  847. tx_exc_metadata->is_tx_sniffer)) {
  848. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  849. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  850. DP_STATS_INC(vdev,
  851. tx_i.dropped.headroom_insufficient, 1);
  852. goto failure;
  853. }
  854. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  856. "qdf_nbuf_push_head failed");
  857. goto failure;
  858. }
  859. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  860. msdu_info);
  861. if (htt_hdr_size == 0)
  862. goto failure;
  863. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  864. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  865. is_exception = 1;
  866. }
  867. #if !TQM_BYPASS_WAR
  868. if (is_exception || tx_exc_metadata)
  869. #endif
  870. {
  871. /* Temporary WAR due to TQM VP issues */
  872. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  873. qdf_atomic_inc(&soc->num_tx_exception);
  874. }
  875. return tx_desc;
  876. failure:
  877. dp_tx_desc_release(tx_desc, desc_pool_id);
  878. return NULL;
  879. }
  880. /**
  881. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  882. * @vdev: DP vdev handle
  883. * @nbuf: skb
  884. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  885. * @desc_pool_id : Descriptor Pool ID
  886. *
  887. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  888. * information. For frames wth fragments, allocate and prepare
  889. * an MSDU extension descriptor
  890. *
  891. * Return: Pointer to Tx Descriptor on success,
  892. * NULL on failure
  893. */
  894. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  895. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  896. uint8_t desc_pool_id)
  897. {
  898. struct dp_tx_desc_s *tx_desc;
  899. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  900. struct dp_pdev *pdev = vdev->pdev;
  901. struct dp_soc *soc = pdev->soc;
  902. if (dp_tx_limit_check(vdev))
  903. return NULL;
  904. /* Allocate software Tx descriptor */
  905. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  906. if (!tx_desc) {
  907. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  908. return NULL;
  909. }
  910. dp_tx_outstanding_inc(pdev);
  911. /* Initialize the SW tx descriptor */
  912. tx_desc->nbuf = nbuf;
  913. tx_desc->frm_type = msdu_info->frm_type;
  914. tx_desc->tx_encap_type = vdev->tx_encap_type;
  915. tx_desc->vdev_id = vdev->vdev_id;
  916. tx_desc->pdev = pdev;
  917. tx_desc->pkt_offset = 0;
  918. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  919. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  920. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  921. /* Handle scattered frames - TSO/SG/ME */
  922. /* Allocate and prepare an extension descriptor for scattered frames */
  923. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  924. if (!msdu_ext_desc) {
  925. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  926. "%s Tx Extension Descriptor Alloc Fail",
  927. __func__);
  928. goto failure;
  929. }
  930. #if TQM_BYPASS_WAR
  931. /* Temporary WAR due to TQM VP issues */
  932. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  933. qdf_atomic_inc(&soc->num_tx_exception);
  934. #endif
  935. if (qdf_unlikely(msdu_info->exception_fw))
  936. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  937. tx_desc->msdu_ext_desc = msdu_ext_desc;
  938. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  939. return tx_desc;
  940. failure:
  941. dp_tx_desc_release(tx_desc, desc_pool_id);
  942. return NULL;
  943. }
  944. /**
  945. * dp_tx_prepare_raw() - Prepare RAW packet TX
  946. * @vdev: DP vdev handle
  947. * @nbuf: buffer pointer
  948. * @seg_info: Pointer to Segment info Descriptor to be prepared
  949. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  950. * descriptor
  951. *
  952. * Return:
  953. */
  954. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  955. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  956. {
  957. qdf_nbuf_t curr_nbuf = NULL;
  958. uint16_t total_len = 0;
  959. qdf_dma_addr_t paddr;
  960. int32_t i;
  961. int32_t mapped_buf_num = 0;
  962. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  963. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  964. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  965. /* Continue only if frames are of DATA type */
  966. if (!DP_FRAME_IS_DATA(qos_wh)) {
  967. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  968. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  969. "Pkt. recd is of not data type");
  970. goto error;
  971. }
  972. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  973. if (vdev->raw_mode_war &&
  974. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  975. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  976. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  977. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  978. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  979. /*
  980. * Number of nbuf's must not exceed the size of the frags
  981. * array in seg_info.
  982. */
  983. if (i >= DP_TX_MAX_NUM_FRAGS) {
  984. dp_err_rl("nbuf cnt exceeds the max number of segs");
  985. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  986. goto error;
  987. }
  988. if (QDF_STATUS_SUCCESS !=
  989. qdf_nbuf_map_nbytes_single(vdev->osdev,
  990. curr_nbuf,
  991. QDF_DMA_TO_DEVICE,
  992. curr_nbuf->len)) {
  993. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  994. "%s dma map error ", __func__);
  995. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  996. goto error;
  997. }
  998. /* Update the count of mapped nbuf's */
  999. mapped_buf_num++;
  1000. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1001. seg_info->frags[i].paddr_lo = paddr;
  1002. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1003. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1004. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1005. total_len += qdf_nbuf_len(curr_nbuf);
  1006. }
  1007. seg_info->frag_cnt = i;
  1008. seg_info->total_len = total_len;
  1009. seg_info->next = NULL;
  1010. sg_info->curr_seg = seg_info;
  1011. msdu_info->frm_type = dp_tx_frm_raw;
  1012. msdu_info->num_seg = 1;
  1013. return nbuf;
  1014. error:
  1015. i = 0;
  1016. while (nbuf) {
  1017. curr_nbuf = nbuf;
  1018. if (i < mapped_buf_num) {
  1019. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1020. QDF_DMA_TO_DEVICE,
  1021. curr_nbuf->len);
  1022. i++;
  1023. }
  1024. nbuf = qdf_nbuf_next(nbuf);
  1025. qdf_nbuf_free(curr_nbuf);
  1026. }
  1027. return NULL;
  1028. }
  1029. /**
  1030. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1031. * @soc: DP soc handle
  1032. * @nbuf: Buffer pointer
  1033. *
  1034. * unmap the chain of nbufs that belong to this RAW frame.
  1035. *
  1036. * Return: None
  1037. */
  1038. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1039. qdf_nbuf_t nbuf)
  1040. {
  1041. qdf_nbuf_t cur_nbuf = nbuf;
  1042. do {
  1043. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1044. QDF_DMA_TO_DEVICE,
  1045. cur_nbuf->len);
  1046. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1047. } while (cur_nbuf);
  1048. }
  1049. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1050. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1051. { \
  1052. qdf_nbuf_t nbuf_local; \
  1053. struct dp_vdev *vdev_local = vdev_hdl; \
  1054. do { \
  1055. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1056. break; \
  1057. nbuf_local = nbuf; \
  1058. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1059. htt_cmn_pkt_type_raw)) \
  1060. break; \
  1061. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1062. break; \
  1063. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1064. break; \
  1065. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1066. (nbuf_local), \
  1067. NULL, 1, 0); \
  1068. } while (0); \
  1069. }
  1070. #else
  1071. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1072. #endif
  1073. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1074. /**
  1075. * dp_tx_update_stats() - Update soc level tx stats
  1076. * @soc: DP soc handle
  1077. * @nbuf: packet being transmitted
  1078. *
  1079. * Returns: none
  1080. */
  1081. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1082. qdf_nbuf_t nbuf)
  1083. {
  1084. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1085. }
  1086. /**
  1087. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1088. * @soc: Datapath soc handle
  1089. * @tx_desc: tx packet descriptor
  1090. * @tid: TID for pkt transmission
  1091. *
  1092. * Returns: 1, if coalescing is to be done
  1093. * 0, if coalescing is not to be done
  1094. */
  1095. static inline int
  1096. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1097. struct dp_tx_desc_s *tx_desc,
  1098. uint8_t tid)
  1099. {
  1100. struct dp_swlm *swlm = &soc->swlm;
  1101. union swlm_data swlm_query_data;
  1102. struct dp_swlm_tcl_data tcl_data;
  1103. QDF_STATUS status;
  1104. int ret;
  1105. if (qdf_unlikely(!swlm->is_enabled))
  1106. return 0;
  1107. tcl_data.nbuf = tx_desc->nbuf;
  1108. tcl_data.tid = tid;
  1109. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1110. swlm_query_data.tcl_data = &tcl_data;
  1111. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1112. if (QDF_IS_STATUS_ERROR(status)) {
  1113. dp_swlm_tcl_reset_session_data(soc);
  1114. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1115. return 0;
  1116. }
  1117. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1118. if (ret) {
  1119. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1120. } else {
  1121. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1122. }
  1123. return ret;
  1124. }
  1125. /**
  1126. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1127. * @soc: Datapath soc handle
  1128. * @hal_ring_hdl: HAL ring handle
  1129. * @coalesce: Coalesce the current write or not
  1130. *
  1131. * Returns: none
  1132. */
  1133. static inline void
  1134. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1135. int coalesce)
  1136. {
  1137. if (coalesce)
  1138. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1139. else
  1140. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1141. }
  1142. #else
  1143. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1144. qdf_nbuf_t nbuf)
  1145. {
  1146. }
  1147. static inline int
  1148. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1149. struct dp_tx_desc_s *tx_desc,
  1150. uint8_t tid)
  1151. {
  1152. return 0;
  1153. }
  1154. static inline void
  1155. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1156. int coalesce)
  1157. {
  1158. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1159. }
  1160. #endif
  1161. /**
  1162. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1163. * @soc: DP Soc Handle
  1164. * @vdev: DP vdev handle
  1165. * @tx_desc: Tx Descriptor Handle
  1166. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1167. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1168. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1169. * @tx_exc_metadata: Handle that holds exception path meta data
  1170. *
  1171. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1172. * from software Tx descriptor
  1173. *
  1174. * Return: QDF_STATUS_SUCCESS: success
  1175. * QDF_STATUS_E_RESOURCES: Error return
  1176. */
  1177. static QDF_STATUS
  1178. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1179. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1180. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1181. struct dp_tx_msdu_info_s *msdu_info)
  1182. {
  1183. uint8_t type;
  1184. void *hal_tx_desc;
  1185. uint32_t *hal_tx_desc_cached;
  1186. int coalesce = 0;
  1187. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1188. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1189. uint8_t tid = msdu_info->tid;
  1190. /*
  1191. * Setting it initialization statically here to avoid
  1192. * a memset call jump with qdf_mem_set call
  1193. */
  1194. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1195. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1196. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1197. tx_exc_metadata->sec_type : vdev->sec_type);
  1198. /* Return Buffer Manager ID */
  1199. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1200. hal_ring_handle_t hal_ring_hdl = NULL;
  1201. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1202. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1203. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1204. return QDF_STATUS_E_RESOURCES;
  1205. }
  1206. hal_tx_desc_cached = (void *) cached_desc;
  1207. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1208. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1209. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1210. if (tx_desc->msdu_ext_desc->flags &
  1211. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1212. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1213. else
  1214. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1215. } else {
  1216. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1217. tx_desc->pkt_offset;
  1218. type = HAL_TX_BUF_TYPE_BUFFER;
  1219. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1220. }
  1221. qdf_assert_always(tx_desc->dma_addr);
  1222. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1223. tx_desc->dma_addr, bm_id, tx_desc->id,
  1224. type);
  1225. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1226. vdev->lmac_id);
  1227. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1228. msdu_info->search_type);
  1229. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1230. msdu_info->ast_idx);
  1231. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1232. vdev->dscp_tid_map_id);
  1233. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1234. sec_type_map[sec_type]);
  1235. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1236. (msdu_info->ast_hash & 0xF));
  1237. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1238. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1239. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1240. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1241. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1242. vdev->hal_desc_addr_search_flags);
  1243. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1244. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1245. /* verify checksum offload configuration*/
  1246. if (vdev->csum_enabled &&
  1247. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1248. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1249. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1250. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1251. }
  1252. if (tid != HTT_TX_EXT_TID_INVALID)
  1253. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1254. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1255. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1256. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1257. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1258. soc->wlan_cfg_ctx)))
  1259. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1260. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1261. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1262. tx_desc->pkt_offset, tx_desc->id);
  1263. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1264. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1265. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1266. "%s %d : HAL RING Access Failed -- %pK",
  1267. __func__, __LINE__, hal_ring_hdl);
  1268. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1269. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1270. return status;
  1271. }
  1272. /* Sync cached descriptor with HW */
  1273. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1274. if (qdf_unlikely(!hal_tx_desc)) {
  1275. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1276. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1277. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1278. goto ring_access_fail;
  1279. }
  1280. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1281. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1282. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1283. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1284. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1285. dp_tx_update_stats(soc, tx_desc->nbuf);
  1286. status = QDF_STATUS_SUCCESS;
  1287. ring_access_fail:
  1288. if (hif_pm_runtime_get(soc->hif_handle,
  1289. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1290. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1291. hif_pm_runtime_put(soc->hif_handle,
  1292. RTPM_ID_DW_TX_HW_ENQUEUE);
  1293. } else {
  1294. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1295. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1296. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1297. }
  1298. return status;
  1299. }
  1300. /**
  1301. * dp_cce_classify() - Classify the frame based on CCE rules
  1302. * @vdev: DP vdev handle
  1303. * @nbuf: skb
  1304. *
  1305. * Classify frames based on CCE rules
  1306. * Return: bool( true if classified,
  1307. * else false)
  1308. */
  1309. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1310. {
  1311. qdf_ether_header_t *eh = NULL;
  1312. uint16_t ether_type;
  1313. qdf_llc_t *llcHdr;
  1314. qdf_nbuf_t nbuf_clone = NULL;
  1315. qdf_dot3_qosframe_t *qos_wh = NULL;
  1316. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1317. /*
  1318. * In case of mesh packets or hlos tid override enabled,
  1319. * don't do any classification
  1320. */
  1321. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1322. & DP_TX_SKIP_CCE_CLASSIFY))
  1323. return false;
  1324. }
  1325. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1326. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1327. ether_type = eh->ether_type;
  1328. llcHdr = (qdf_llc_t *)(nbuf->data +
  1329. sizeof(qdf_ether_header_t));
  1330. } else {
  1331. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1332. /* For encrypted packets don't do any classification */
  1333. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1334. return false;
  1335. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1336. if (qdf_unlikely(
  1337. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1338. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1339. ether_type = *(uint16_t *)(nbuf->data
  1340. + QDF_IEEE80211_4ADDR_HDR_LEN
  1341. + sizeof(qdf_llc_t)
  1342. - sizeof(ether_type));
  1343. llcHdr = (qdf_llc_t *)(nbuf->data +
  1344. QDF_IEEE80211_4ADDR_HDR_LEN);
  1345. } else {
  1346. ether_type = *(uint16_t *)(nbuf->data
  1347. + QDF_IEEE80211_3ADDR_HDR_LEN
  1348. + sizeof(qdf_llc_t)
  1349. - sizeof(ether_type));
  1350. llcHdr = (qdf_llc_t *)(nbuf->data +
  1351. QDF_IEEE80211_3ADDR_HDR_LEN);
  1352. }
  1353. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1354. && (ether_type ==
  1355. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1356. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1357. return true;
  1358. }
  1359. }
  1360. return false;
  1361. }
  1362. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1363. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1364. sizeof(*llcHdr));
  1365. nbuf_clone = qdf_nbuf_clone(nbuf);
  1366. if (qdf_unlikely(nbuf_clone)) {
  1367. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1368. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1369. qdf_nbuf_pull_head(nbuf_clone,
  1370. sizeof(qdf_net_vlanhdr_t));
  1371. }
  1372. }
  1373. } else {
  1374. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1375. nbuf_clone = qdf_nbuf_clone(nbuf);
  1376. if (qdf_unlikely(nbuf_clone)) {
  1377. qdf_nbuf_pull_head(nbuf_clone,
  1378. sizeof(qdf_net_vlanhdr_t));
  1379. }
  1380. }
  1381. }
  1382. if (qdf_unlikely(nbuf_clone))
  1383. nbuf = nbuf_clone;
  1384. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1385. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1386. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1387. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1388. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1389. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1390. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1391. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1392. if (qdf_unlikely(nbuf_clone))
  1393. qdf_nbuf_free(nbuf_clone);
  1394. return true;
  1395. }
  1396. if (qdf_unlikely(nbuf_clone))
  1397. qdf_nbuf_free(nbuf_clone);
  1398. return false;
  1399. }
  1400. /**
  1401. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1402. * @vdev: DP vdev handle
  1403. * @nbuf: skb
  1404. *
  1405. * Extract the DSCP or PCP information from frame and map into TID value.
  1406. *
  1407. * Return: void
  1408. */
  1409. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. uint8_t tos = 0, dscp_tid_override = 0;
  1413. uint8_t *hdr_ptr, *L3datap;
  1414. uint8_t is_mcast = 0;
  1415. qdf_ether_header_t *eh = NULL;
  1416. qdf_ethervlan_header_t *evh = NULL;
  1417. uint16_t ether_type;
  1418. qdf_llc_t *llcHdr;
  1419. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1420. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1421. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1422. eh = (qdf_ether_header_t *)nbuf->data;
  1423. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1424. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1425. } else {
  1426. qdf_dot3_qosframe_t *qos_wh =
  1427. (qdf_dot3_qosframe_t *) nbuf->data;
  1428. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1429. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1430. return;
  1431. }
  1432. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1433. ether_type = eh->ether_type;
  1434. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1435. /*
  1436. * Check if packet is dot3 or eth2 type.
  1437. */
  1438. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1439. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1440. sizeof(*llcHdr));
  1441. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1442. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1443. sizeof(*llcHdr);
  1444. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1445. + sizeof(*llcHdr) +
  1446. sizeof(qdf_net_vlanhdr_t));
  1447. } else {
  1448. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1449. sizeof(*llcHdr);
  1450. }
  1451. } else {
  1452. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1453. evh = (qdf_ethervlan_header_t *) eh;
  1454. ether_type = evh->ether_type;
  1455. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1456. }
  1457. }
  1458. /*
  1459. * Find priority from IP TOS DSCP field
  1460. */
  1461. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1462. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1463. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1464. /* Only for unicast frames */
  1465. if (!is_mcast) {
  1466. /* send it on VO queue */
  1467. msdu_info->tid = DP_VO_TID;
  1468. }
  1469. } else {
  1470. /*
  1471. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1472. * from TOS byte.
  1473. */
  1474. tos = ip->ip_tos;
  1475. dscp_tid_override = 1;
  1476. }
  1477. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1478. /* TODO
  1479. * use flowlabel
  1480. *igmpmld cases to be handled in phase 2
  1481. */
  1482. unsigned long ver_pri_flowlabel;
  1483. unsigned long pri;
  1484. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1485. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1486. DP_IPV6_PRIORITY_SHIFT;
  1487. tos = pri;
  1488. dscp_tid_override = 1;
  1489. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1490. msdu_info->tid = DP_VO_TID;
  1491. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1492. /* Only for unicast frames */
  1493. if (!is_mcast) {
  1494. /* send ucast arp on VO queue */
  1495. msdu_info->tid = DP_VO_TID;
  1496. }
  1497. }
  1498. /*
  1499. * Assign all MCAST packets to BE
  1500. */
  1501. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1502. if (is_mcast) {
  1503. tos = 0;
  1504. dscp_tid_override = 1;
  1505. }
  1506. }
  1507. if (dscp_tid_override == 1) {
  1508. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1509. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1510. }
  1511. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1512. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1513. return;
  1514. }
  1515. /**
  1516. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1517. * @vdev: DP vdev handle
  1518. * @nbuf: skb
  1519. *
  1520. * Software based TID classification is required when more than 2 DSCP-TID
  1521. * mapping tables are needed.
  1522. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1523. *
  1524. * Return: void
  1525. */
  1526. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1527. struct dp_tx_msdu_info_s *msdu_info)
  1528. {
  1529. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1530. /*
  1531. * skip_sw_tid_classification flag will set in below cases-
  1532. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1533. * 2. hlos_tid_override enabled for vdev
  1534. * 3. mesh mode enabled for vdev
  1535. */
  1536. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1537. /* Update tid in msdu_info from skb priority */
  1538. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1539. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1540. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1541. return;
  1542. }
  1543. return;
  1544. }
  1545. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1546. }
  1547. #ifdef FEATURE_WLAN_TDLS
  1548. /**
  1549. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1550. * @soc: datapath SOC
  1551. * @vdev: datapath vdev
  1552. * @tx_desc: TX descriptor
  1553. *
  1554. * Return: None
  1555. */
  1556. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1557. struct dp_vdev *vdev,
  1558. struct dp_tx_desc_s *tx_desc)
  1559. {
  1560. if (vdev) {
  1561. if (vdev->is_tdls_frame) {
  1562. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1563. vdev->is_tdls_frame = false;
  1564. }
  1565. }
  1566. }
  1567. /**
  1568. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1569. * @soc: dp_soc handle
  1570. * @tx_desc: TX descriptor
  1571. * @vdev: datapath vdev handle
  1572. *
  1573. * Return: None
  1574. */
  1575. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1576. struct dp_tx_desc_s *tx_desc)
  1577. {
  1578. struct hal_tx_completion_status ts = {0};
  1579. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1580. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1581. DP_MOD_ID_TDLS);
  1582. if (qdf_unlikely(!vdev)) {
  1583. dp_err_rl("vdev is null!");
  1584. goto error;
  1585. }
  1586. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1587. if (vdev->tx_non_std_data_callback.func) {
  1588. qdf_nbuf_set_next(nbuf, NULL);
  1589. vdev->tx_non_std_data_callback.func(
  1590. vdev->tx_non_std_data_callback.ctxt,
  1591. nbuf, ts.status);
  1592. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1593. return;
  1594. } else {
  1595. dp_err_rl("callback func is null");
  1596. }
  1597. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1598. error:
  1599. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1600. qdf_nbuf_free(nbuf);
  1601. }
  1602. /**
  1603. * dp_tx_msdu_single_map() - do nbuf map
  1604. * @vdev: DP vdev handle
  1605. * @tx_desc: DP TX descriptor pointer
  1606. * @nbuf: skb pointer
  1607. *
  1608. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1609. * operation done in other component.
  1610. *
  1611. * Return: QDF_STATUS
  1612. */
  1613. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1614. struct dp_tx_desc_s *tx_desc,
  1615. qdf_nbuf_t nbuf)
  1616. {
  1617. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1618. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1619. nbuf,
  1620. QDF_DMA_TO_DEVICE,
  1621. nbuf->len);
  1622. else
  1623. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1624. QDF_DMA_TO_DEVICE);
  1625. }
  1626. #else
  1627. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1628. struct dp_vdev *vdev,
  1629. struct dp_tx_desc_s *tx_desc)
  1630. {
  1631. }
  1632. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1633. struct dp_tx_desc_s *tx_desc)
  1634. {
  1635. }
  1636. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1637. struct dp_tx_desc_s *tx_desc,
  1638. qdf_nbuf_t nbuf)
  1639. {
  1640. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1641. nbuf,
  1642. QDF_DMA_TO_DEVICE,
  1643. nbuf->len);
  1644. }
  1645. #endif
  1646. #ifdef MESH_MODE_SUPPORT
  1647. /**
  1648. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1649. * @soc: datapath SOC
  1650. * @vdev: datapath vdev
  1651. * @tx_desc: TX descriptor
  1652. *
  1653. * Return: None
  1654. */
  1655. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1656. struct dp_vdev *vdev,
  1657. struct dp_tx_desc_s *tx_desc)
  1658. {
  1659. if (qdf_unlikely(vdev->mesh_vdev))
  1660. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1661. }
  1662. /**
  1663. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1664. * @soc: dp_soc handle
  1665. * @tx_desc: TX descriptor
  1666. * @vdev: datapath vdev handle
  1667. *
  1668. * Return: None
  1669. */
  1670. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1671. struct dp_tx_desc_s *tx_desc)
  1672. {
  1673. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1674. struct dp_vdev *vdev = NULL;
  1675. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1676. qdf_nbuf_free(nbuf);
  1677. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1678. } else {
  1679. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1680. DP_MOD_ID_MESH);
  1681. if (vdev && vdev->osif_tx_free_ext)
  1682. vdev->osif_tx_free_ext((nbuf));
  1683. else
  1684. qdf_nbuf_free(nbuf);
  1685. if (vdev)
  1686. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1687. }
  1688. }
  1689. #else
  1690. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1691. struct dp_vdev *vdev,
  1692. struct dp_tx_desc_s *tx_desc)
  1693. {
  1694. }
  1695. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1696. struct dp_tx_desc_s *tx_desc)
  1697. {
  1698. }
  1699. #endif
  1700. /**
  1701. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1702. * @vdev: DP vdev handle
  1703. * @nbuf: skb
  1704. *
  1705. * Return: 1 if frame needs to be dropped else 0
  1706. */
  1707. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1708. {
  1709. struct dp_pdev *pdev = NULL;
  1710. struct dp_ast_entry *src_ast_entry = NULL;
  1711. struct dp_ast_entry *dst_ast_entry = NULL;
  1712. struct dp_soc *soc = NULL;
  1713. qdf_assert(vdev);
  1714. pdev = vdev->pdev;
  1715. qdf_assert(pdev);
  1716. soc = pdev->soc;
  1717. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1718. (soc, dstmac, vdev->pdev->pdev_id);
  1719. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1720. (soc, srcmac, vdev->pdev->pdev_id);
  1721. if (dst_ast_entry && src_ast_entry) {
  1722. if (dst_ast_entry->peer_id ==
  1723. src_ast_entry->peer_id)
  1724. return 1;
  1725. }
  1726. return 0;
  1727. }
  1728. /**
  1729. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1730. * @vdev: DP vdev handle
  1731. * @nbuf: skb
  1732. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1733. * @meta_data: Metadata to the fw
  1734. * @tx_q: Tx queue to be used for this Tx frame
  1735. * @peer_id: peer_id of the peer in case of NAWDS frames
  1736. * @tx_exc_metadata: Handle that holds exception path metadata
  1737. *
  1738. * Return: NULL on success,
  1739. * nbuf when it fails to send
  1740. */
  1741. qdf_nbuf_t
  1742. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1743. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1744. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1745. {
  1746. struct dp_pdev *pdev = vdev->pdev;
  1747. struct dp_soc *soc = pdev->soc;
  1748. struct dp_tx_desc_s *tx_desc;
  1749. QDF_STATUS status;
  1750. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1751. uint16_t htt_tcl_metadata = 0;
  1752. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1753. uint8_t tid = msdu_info->tid;
  1754. struct cdp_tid_tx_stats *tid_stats = NULL;
  1755. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1756. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1757. msdu_info, tx_exc_metadata);
  1758. if (!tx_desc) {
  1759. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1760. vdev, tx_q->desc_pool_id);
  1761. drop_code = TX_DESC_ERR;
  1762. goto fail_return;
  1763. }
  1764. if (qdf_unlikely(soc->cce_disable)) {
  1765. if (dp_cce_classify(vdev, nbuf) == true) {
  1766. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1767. tid = DP_VO_TID;
  1768. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1769. }
  1770. }
  1771. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1772. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1773. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1774. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1775. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1776. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1777. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1778. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1779. peer_id);
  1780. } else
  1781. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1782. if (msdu_info->exception_fw)
  1783. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1784. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1785. !pdev->enhanced_stats_en);
  1786. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1787. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1788. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1789. /* Handle failure */
  1790. dp_err("qdf_nbuf_map failed");
  1791. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1792. drop_code = TX_DMA_MAP_ERR;
  1793. goto release_desc;
  1794. }
  1795. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1796. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1797. tx_exc_metadata, msdu_info);
  1798. if (status != QDF_STATUS_SUCCESS) {
  1799. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1800. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1801. __func__, tx_desc, tx_q->ring_id);
  1802. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1803. QDF_DMA_TO_DEVICE,
  1804. nbuf->len);
  1805. drop_code = TX_HW_ENQUEUE;
  1806. goto release_desc;
  1807. }
  1808. return NULL;
  1809. release_desc:
  1810. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1811. fail_return:
  1812. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1813. tid_stats = &pdev->stats.tid_stats.
  1814. tid_tx_stats[tx_q->ring_id][tid];
  1815. tid_stats->swdrop_cnt[drop_code]++;
  1816. return nbuf;
  1817. }
  1818. /**
  1819. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1820. * @vdev: DP vdev handle
  1821. * @nbuf: skb
  1822. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1823. *
  1824. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1825. *
  1826. * Return: NULL on success,
  1827. * nbuf when it fails to send
  1828. */
  1829. #if QDF_LOCK_STATS
  1830. noinline
  1831. #else
  1832. #endif
  1833. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1834. struct dp_tx_msdu_info_s *msdu_info)
  1835. {
  1836. uint32_t i;
  1837. struct dp_pdev *pdev = vdev->pdev;
  1838. struct dp_soc *soc = pdev->soc;
  1839. struct dp_tx_desc_s *tx_desc;
  1840. bool is_cce_classified = false;
  1841. QDF_STATUS status;
  1842. uint16_t htt_tcl_metadata = 0;
  1843. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1844. struct cdp_tid_tx_stats *tid_stats = NULL;
  1845. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1846. if (qdf_unlikely(soc->cce_disable)) {
  1847. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1848. if (is_cce_classified) {
  1849. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1850. msdu_info->tid = DP_VO_TID;
  1851. }
  1852. }
  1853. if (msdu_info->frm_type == dp_tx_frm_me)
  1854. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1855. i = 0;
  1856. /* Print statement to track i and num_seg */
  1857. /*
  1858. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1859. * descriptors using information in msdu_info
  1860. */
  1861. while (i < msdu_info->num_seg) {
  1862. /*
  1863. * Setup Tx descriptor for an MSDU, and MSDU extension
  1864. * descriptor
  1865. */
  1866. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1867. tx_q->desc_pool_id);
  1868. if (!tx_desc) {
  1869. if (msdu_info->frm_type == dp_tx_frm_me) {
  1870. prep_desc_fail++;
  1871. dp_tx_me_free_buf(pdev,
  1872. (void *)(msdu_info->u.sg_info
  1873. .curr_seg->frags[0].vaddr));
  1874. if (prep_desc_fail == msdu_info->num_seg) {
  1875. /*
  1876. * Unmap is needed only if descriptor
  1877. * preparation failed for all segments.
  1878. */
  1879. qdf_nbuf_unmap(soc->osdev,
  1880. msdu_info->u.sg_info.
  1881. curr_seg->nbuf,
  1882. QDF_DMA_TO_DEVICE);
  1883. }
  1884. /*
  1885. * Free the nbuf for the current segment
  1886. * and make it point to the next in the list.
  1887. * For me, there are as many segments as there
  1888. * are no of clients.
  1889. */
  1890. qdf_nbuf_free(msdu_info->u.sg_info
  1891. .curr_seg->nbuf);
  1892. if (msdu_info->u.sg_info.curr_seg->next)
  1893. msdu_info->u.sg_info.curr_seg =
  1894. msdu_info->u.sg_info
  1895. .curr_seg->next;
  1896. i++;
  1897. continue;
  1898. }
  1899. goto done;
  1900. }
  1901. if (msdu_info->frm_type == dp_tx_frm_me) {
  1902. tx_desc->me_buffer =
  1903. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1904. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1905. }
  1906. if (is_cce_classified)
  1907. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1908. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1909. if (msdu_info->exception_fw) {
  1910. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1911. }
  1912. /*
  1913. * Enqueue the Tx MSDU descriptor to HW for transmit
  1914. */
  1915. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1916. NULL, msdu_info);
  1917. if (status != QDF_STATUS_SUCCESS) {
  1918. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1919. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1920. __func__, tx_desc, tx_q->ring_id);
  1921. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1922. tid_stats = &pdev->stats.tid_stats.
  1923. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1924. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1925. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1926. if (msdu_info->frm_type == dp_tx_frm_me) {
  1927. hw_enq_fail++;
  1928. if (hw_enq_fail == msdu_info->num_seg) {
  1929. /*
  1930. * Unmap is needed only if enqueue
  1931. * failed for all segments.
  1932. */
  1933. qdf_nbuf_unmap(soc->osdev,
  1934. msdu_info->u.sg_info.
  1935. curr_seg->nbuf,
  1936. QDF_DMA_TO_DEVICE);
  1937. }
  1938. /*
  1939. * Free the nbuf for the current segment
  1940. * and make it point to the next in the list.
  1941. * For me, there are as many segments as there
  1942. * are no of clients.
  1943. */
  1944. qdf_nbuf_free(msdu_info->u.sg_info
  1945. .curr_seg->nbuf);
  1946. if (msdu_info->u.sg_info.curr_seg->next)
  1947. msdu_info->u.sg_info.curr_seg =
  1948. msdu_info->u.sg_info
  1949. .curr_seg->next;
  1950. i++;
  1951. continue;
  1952. }
  1953. goto done;
  1954. }
  1955. /*
  1956. * TODO
  1957. * if tso_info structure can be modified to have curr_seg
  1958. * as first element, following 2 blocks of code (for TSO and SG)
  1959. * can be combined into 1
  1960. */
  1961. /*
  1962. * For frames with multiple segments (TSO, ME), jump to next
  1963. * segment.
  1964. */
  1965. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1966. if (msdu_info->u.tso_info.curr_seg->next) {
  1967. msdu_info->u.tso_info.curr_seg =
  1968. msdu_info->u.tso_info.curr_seg->next;
  1969. /*
  1970. * If this is a jumbo nbuf, then increment the number of
  1971. * nbuf users for each additional segment of the msdu.
  1972. * This will ensure that the skb is freed only after
  1973. * receiving tx completion for all segments of an nbuf
  1974. */
  1975. qdf_nbuf_inc_users(nbuf);
  1976. /* Check with MCL if this is needed */
  1977. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1978. }
  1979. }
  1980. /*
  1981. * For Multicast-Unicast converted packets,
  1982. * each converted frame (for a client) is represented as
  1983. * 1 segment
  1984. */
  1985. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1986. (msdu_info->frm_type == dp_tx_frm_me)) {
  1987. if (msdu_info->u.sg_info.curr_seg->next) {
  1988. msdu_info->u.sg_info.curr_seg =
  1989. msdu_info->u.sg_info.curr_seg->next;
  1990. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1991. }
  1992. }
  1993. i++;
  1994. }
  1995. nbuf = NULL;
  1996. done:
  1997. return nbuf;
  1998. }
  1999. /**
  2000. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2001. * for SG frames
  2002. * @vdev: DP vdev handle
  2003. * @nbuf: skb
  2004. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2005. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2006. *
  2007. * Return: NULL on success,
  2008. * nbuf when it fails to send
  2009. */
  2010. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2011. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2012. {
  2013. uint32_t cur_frag, nr_frags, i;
  2014. qdf_dma_addr_t paddr;
  2015. struct dp_tx_sg_info_s *sg_info;
  2016. sg_info = &msdu_info->u.sg_info;
  2017. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2018. if (QDF_STATUS_SUCCESS !=
  2019. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2020. QDF_DMA_TO_DEVICE,
  2021. qdf_nbuf_headlen(nbuf))) {
  2022. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2023. "dma map error");
  2024. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2025. qdf_nbuf_free(nbuf);
  2026. return NULL;
  2027. }
  2028. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2029. seg_info->frags[0].paddr_lo = paddr;
  2030. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2031. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2032. seg_info->frags[0].vaddr = (void *) nbuf;
  2033. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2034. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2035. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2037. "frag dma map error");
  2038. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2039. goto map_err;
  2040. }
  2041. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2042. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2043. seg_info->frags[cur_frag + 1].paddr_hi =
  2044. ((uint64_t) paddr) >> 32;
  2045. seg_info->frags[cur_frag + 1].len =
  2046. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2047. }
  2048. seg_info->frag_cnt = (cur_frag + 1);
  2049. seg_info->total_len = qdf_nbuf_len(nbuf);
  2050. seg_info->next = NULL;
  2051. sg_info->curr_seg = seg_info;
  2052. msdu_info->frm_type = dp_tx_frm_sg;
  2053. msdu_info->num_seg = 1;
  2054. return nbuf;
  2055. map_err:
  2056. /* restore paddr into nbuf before calling unmap */
  2057. qdf_nbuf_mapped_paddr_set(nbuf,
  2058. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2059. ((uint64_t)
  2060. seg_info->frags[0].paddr_hi) << 32));
  2061. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2062. QDF_DMA_TO_DEVICE,
  2063. seg_info->frags[0].len);
  2064. for (i = 1; i <= cur_frag; i++) {
  2065. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2066. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2067. seg_info->frags[i].paddr_hi) << 32),
  2068. seg_info->frags[i].len,
  2069. QDF_DMA_TO_DEVICE);
  2070. }
  2071. qdf_nbuf_free(nbuf);
  2072. return NULL;
  2073. }
  2074. /**
  2075. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2076. * @vdev: DP vdev handle
  2077. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2078. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2079. *
  2080. * Return: NULL on failure,
  2081. * nbuf when extracted successfully
  2082. */
  2083. static
  2084. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2085. struct dp_tx_msdu_info_s *msdu_info,
  2086. uint16_t ppdu_cookie)
  2087. {
  2088. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2089. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2090. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2091. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2092. (msdu_info->meta_data[5], 1);
  2093. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2094. (msdu_info->meta_data[5], 1);
  2095. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2096. (msdu_info->meta_data[6], ppdu_cookie);
  2097. msdu_info->exception_fw = 1;
  2098. msdu_info->is_tx_sniffer = 1;
  2099. }
  2100. #ifdef MESH_MODE_SUPPORT
  2101. /**
  2102. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2103. and prepare msdu_info for mesh frames.
  2104. * @vdev: DP vdev handle
  2105. * @nbuf: skb
  2106. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2107. *
  2108. * Return: NULL on failure,
  2109. * nbuf when extracted successfully
  2110. */
  2111. static
  2112. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2113. struct dp_tx_msdu_info_s *msdu_info)
  2114. {
  2115. struct meta_hdr_s *mhdr;
  2116. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2117. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2118. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2119. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2120. msdu_info->exception_fw = 0;
  2121. goto remove_meta_hdr;
  2122. }
  2123. msdu_info->exception_fw = 1;
  2124. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2125. meta_data->host_tx_desc_pool = 1;
  2126. meta_data->update_peer_cache = 1;
  2127. meta_data->learning_frame = 1;
  2128. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2129. meta_data->power = mhdr->power;
  2130. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2131. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2132. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2133. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2134. meta_data->dyn_bw = 1;
  2135. meta_data->valid_pwr = 1;
  2136. meta_data->valid_mcs_mask = 1;
  2137. meta_data->valid_nss_mask = 1;
  2138. meta_data->valid_preamble_type = 1;
  2139. meta_data->valid_retries = 1;
  2140. meta_data->valid_bw_info = 1;
  2141. }
  2142. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2143. meta_data->encrypt_type = 0;
  2144. meta_data->valid_encrypt_type = 1;
  2145. meta_data->learning_frame = 0;
  2146. }
  2147. meta_data->valid_key_flags = 1;
  2148. meta_data->key_flags = (mhdr->keyix & 0x3);
  2149. remove_meta_hdr:
  2150. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2151. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2152. "qdf_nbuf_pull_head failed");
  2153. qdf_nbuf_free(nbuf);
  2154. return NULL;
  2155. }
  2156. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2158. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2159. " tid %d to_fw %d",
  2160. __func__, msdu_info->meta_data[0],
  2161. msdu_info->meta_data[1],
  2162. msdu_info->meta_data[2],
  2163. msdu_info->meta_data[3],
  2164. msdu_info->meta_data[4],
  2165. msdu_info->meta_data[5],
  2166. msdu_info->tid, msdu_info->exception_fw);
  2167. return nbuf;
  2168. }
  2169. #else
  2170. static
  2171. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2172. struct dp_tx_msdu_info_s *msdu_info)
  2173. {
  2174. return nbuf;
  2175. }
  2176. #endif
  2177. /**
  2178. * dp_check_exc_metadata() - Checks if parameters are valid
  2179. * @tx_exc - holds all exception path parameters
  2180. *
  2181. * Returns true when all the parameters are valid else false
  2182. *
  2183. */
  2184. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2185. {
  2186. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2187. HTT_INVALID_TID);
  2188. bool invalid_encap_type =
  2189. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2190. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2191. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2192. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2193. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2194. tx_exc->ppdu_cookie == 0);
  2195. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2196. invalid_cookie) {
  2197. return false;
  2198. }
  2199. return true;
  2200. }
  2201. #ifdef ATH_SUPPORT_IQUE
  2202. /**
  2203. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2204. * @vdev: vdev handle
  2205. * @nbuf: skb
  2206. *
  2207. * Return: true on success,
  2208. * false on failure
  2209. */
  2210. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2211. {
  2212. qdf_ether_header_t *eh;
  2213. /* Mcast to Ucast Conversion*/
  2214. if (qdf_likely(!vdev->mcast_enhancement_en))
  2215. return true;
  2216. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2217. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2218. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2219. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2220. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2221. qdf_nbuf_len(nbuf));
  2222. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2223. QDF_STATUS_SUCCESS) {
  2224. return false;
  2225. }
  2226. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2227. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2228. QDF_STATUS_SUCCESS) {
  2229. return false;
  2230. }
  2231. }
  2232. }
  2233. return true;
  2234. }
  2235. #else
  2236. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2237. {
  2238. return true;
  2239. }
  2240. #endif
  2241. /**
  2242. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2243. * @nbuf: qdf_nbuf_t
  2244. * @vdev: struct dp_vdev *
  2245. *
  2246. * Allow packet for processing only if it is for peer client which is
  2247. * connected with same vap. Drop packet if client is connected to
  2248. * different vap.
  2249. *
  2250. * Return: QDF_STATUS
  2251. */
  2252. static inline QDF_STATUS
  2253. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2254. {
  2255. struct dp_ast_entry *dst_ast_entry = NULL;
  2256. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2257. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2258. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2259. return QDF_STATUS_SUCCESS;
  2260. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2261. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2262. eh->ether_dhost,
  2263. vdev->vdev_id);
  2264. /* If there is no ast entry, return failure */
  2265. if (qdf_unlikely(!dst_ast_entry)) {
  2266. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2267. return QDF_STATUS_E_FAILURE;
  2268. }
  2269. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2270. return QDF_STATUS_SUCCESS;
  2271. }
  2272. /**
  2273. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2274. * @soc: DP soc handle
  2275. * @vdev_id: id of DP vdev handle
  2276. * @nbuf: skb
  2277. * @tx_exc_metadata: Handle that holds exception path meta data
  2278. *
  2279. * Entry point for Core Tx layer (DP_TX) invoked from
  2280. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2281. *
  2282. * Return: NULL on success,
  2283. * nbuf when it fails to send
  2284. */
  2285. qdf_nbuf_t
  2286. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2287. qdf_nbuf_t nbuf,
  2288. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2289. {
  2290. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2291. qdf_ether_header_t *eh = NULL;
  2292. struct dp_tx_msdu_info_s msdu_info;
  2293. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2294. DP_MOD_ID_TX_EXCEPTION);
  2295. if (qdf_unlikely(!vdev))
  2296. goto fail;
  2297. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2298. if (!tx_exc_metadata)
  2299. goto fail;
  2300. msdu_info.tid = tx_exc_metadata->tid;
  2301. dp_tx_wds_ext(soc, vdev, tx_exc_metadata->peer_id, &msdu_info);
  2302. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2303. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2304. QDF_MAC_ADDR_REF(nbuf->data));
  2305. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2306. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2307. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2308. "Invalid parameters in exception path");
  2309. goto fail;
  2310. }
  2311. /* Basic sanity checks for unsupported packets */
  2312. /* MESH mode */
  2313. if (qdf_unlikely(vdev->mesh_vdev)) {
  2314. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2315. "Mesh mode is not supported in exception path");
  2316. goto fail;
  2317. }
  2318. /*
  2319. * Classify the frame and call corresponding
  2320. * "prepare" function which extracts the segment (TSO)
  2321. * and fragmentation information (for TSO , SG, ME, or Raw)
  2322. * into MSDU_INFO structure which is later used to fill
  2323. * SW and HW descriptors.
  2324. */
  2325. if (qdf_nbuf_is_tso(nbuf)) {
  2326. dp_verbose_debug("TSO frame %pK", vdev);
  2327. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2328. qdf_nbuf_len(nbuf));
  2329. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2330. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2331. qdf_nbuf_len(nbuf));
  2332. return nbuf;
  2333. }
  2334. goto send_multiple;
  2335. }
  2336. /* SG */
  2337. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2338. struct dp_tx_seg_info_s seg_info = {0};
  2339. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2340. if (!nbuf)
  2341. return NULL;
  2342. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2343. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2344. qdf_nbuf_len(nbuf));
  2345. goto send_multiple;
  2346. }
  2347. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2348. return NULL;
  2349. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2350. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2351. qdf_nbuf_len(nbuf));
  2352. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2353. tx_exc_metadata->ppdu_cookie);
  2354. }
  2355. /*
  2356. * Get HW Queue to use for this frame.
  2357. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2358. * dedicated for data and 1 for command.
  2359. * "queue_id" maps to one hardware ring.
  2360. * With each ring, we also associate a unique Tx descriptor pool
  2361. * to minimize lock contention for these resources.
  2362. */
  2363. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2364. /*
  2365. * Check exception descriptors
  2366. */
  2367. if (dp_tx_exception_limit_check(vdev))
  2368. goto fail;
  2369. /* Single linear frame */
  2370. /*
  2371. * If nbuf is a simple linear frame, use send_single function to
  2372. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2373. * SRNG. There is no need to setup a MSDU extension descriptor.
  2374. */
  2375. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2376. tx_exc_metadata->peer_id, tx_exc_metadata);
  2377. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2378. return nbuf;
  2379. send_multiple:
  2380. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2381. fail:
  2382. if (vdev)
  2383. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2384. dp_verbose_debug("pkt send failed");
  2385. return nbuf;
  2386. }
  2387. /**
  2388. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2389. * in exception path in special case to avoid regular exception path chk.
  2390. * @soc: DP soc handle
  2391. * @vdev_id: id of DP vdev handle
  2392. * @nbuf: skb
  2393. * @tx_exc_metadata: Handle that holds exception path meta data
  2394. *
  2395. * Entry point for Core Tx layer (DP_TX) invoked from
  2396. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2397. *
  2398. * Return: NULL on success,
  2399. * nbuf when it fails to send
  2400. */
  2401. qdf_nbuf_t
  2402. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2403. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2404. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2405. {
  2406. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2407. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2408. DP_MOD_ID_TX_EXCEPTION);
  2409. if (qdf_unlikely(!vdev))
  2410. goto fail;
  2411. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2412. == QDF_STATUS_E_FAILURE)) {
  2413. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2414. goto fail;
  2415. }
  2416. /* Unref count as it will agin be taken inside dp_tx_exception */
  2417. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2418. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2419. fail:
  2420. if (vdev)
  2421. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2422. dp_verbose_debug("pkt send failed");
  2423. return nbuf;
  2424. }
  2425. /**
  2426. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2427. * @soc: DP soc handle
  2428. * @vdev_id: DP vdev handle
  2429. * @nbuf: skb
  2430. *
  2431. * Entry point for Core Tx layer (DP_TX) invoked from
  2432. * hard_start_xmit in OSIF/HDD
  2433. *
  2434. * Return: NULL on success,
  2435. * nbuf when it fails to send
  2436. */
  2437. #ifdef MESH_MODE_SUPPORT
  2438. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2439. qdf_nbuf_t nbuf)
  2440. {
  2441. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2442. struct meta_hdr_s *mhdr;
  2443. qdf_nbuf_t nbuf_mesh = NULL;
  2444. qdf_nbuf_t nbuf_clone = NULL;
  2445. struct dp_vdev *vdev;
  2446. uint8_t no_enc_frame = 0;
  2447. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2448. if (!nbuf_mesh) {
  2449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2450. "qdf_nbuf_unshare failed");
  2451. return nbuf;
  2452. }
  2453. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2454. if (!vdev) {
  2455. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2456. "vdev is NULL for vdev_id %d", vdev_id);
  2457. return nbuf;
  2458. }
  2459. nbuf = nbuf_mesh;
  2460. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2461. if ((vdev->sec_type != cdp_sec_type_none) &&
  2462. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2463. no_enc_frame = 1;
  2464. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2465. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2466. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2467. !no_enc_frame) {
  2468. nbuf_clone = qdf_nbuf_clone(nbuf);
  2469. if (!nbuf_clone) {
  2470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2471. "qdf_nbuf_clone failed");
  2472. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2473. return nbuf;
  2474. }
  2475. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2476. }
  2477. if (nbuf_clone) {
  2478. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2479. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2480. } else {
  2481. qdf_nbuf_free(nbuf_clone);
  2482. }
  2483. }
  2484. if (no_enc_frame)
  2485. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2486. else
  2487. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2488. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2489. if ((!nbuf) && no_enc_frame) {
  2490. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2491. }
  2492. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2493. return nbuf;
  2494. }
  2495. #else
  2496. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2497. qdf_nbuf_t nbuf)
  2498. {
  2499. return dp_tx_send(soc, vdev_id, nbuf);
  2500. }
  2501. #endif
  2502. /**
  2503. * dp_tx_nawds_handler() - NAWDS handler
  2504. *
  2505. * @soc: DP soc handle
  2506. * @vdev_id: id of DP vdev handle
  2507. * @msdu_info: msdu_info required to create HTT metadata
  2508. * @nbuf: skb
  2509. *
  2510. * This API transfers the multicast frames with the peer id
  2511. * on NAWDS enabled peer.
  2512. * Return: none
  2513. */
  2514. static inline
  2515. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2516. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2517. {
  2518. struct dp_peer *peer = NULL;
  2519. qdf_nbuf_t nbuf_clone = NULL;
  2520. uint16_t peer_id = DP_INVALID_PEER;
  2521. uint16_t sa_peer_id = DP_INVALID_PEER;
  2522. struct dp_ast_entry *ast_entry = NULL;
  2523. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2524. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2525. qdf_spin_lock_bh(&soc->ast_lock);
  2526. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2527. (soc,
  2528. (uint8_t *)(eh->ether_shost),
  2529. vdev->pdev->pdev_id);
  2530. if (ast_entry)
  2531. sa_peer_id = ast_entry->peer_id;
  2532. qdf_spin_unlock_bh(&soc->ast_lock);
  2533. }
  2534. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2535. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2536. if (!peer->bss_peer && peer->nawds_enabled) {
  2537. peer_id = peer->peer_id;
  2538. /* Multicast packets needs to be
  2539. * dropped in case of intra bss forwarding
  2540. */
  2541. if (sa_peer_id == peer->peer_id) {
  2542. QDF_TRACE(QDF_MODULE_ID_DP,
  2543. QDF_TRACE_LEVEL_DEBUG,
  2544. " %s: multicast packet", __func__);
  2545. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2546. continue;
  2547. }
  2548. nbuf_clone = qdf_nbuf_clone(nbuf);
  2549. if (!nbuf_clone) {
  2550. QDF_TRACE(QDF_MODULE_ID_DP,
  2551. QDF_TRACE_LEVEL_ERROR,
  2552. FL("nbuf clone failed"));
  2553. break;
  2554. }
  2555. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2556. msdu_info, peer_id,
  2557. NULL);
  2558. if (nbuf_clone) {
  2559. QDF_TRACE(QDF_MODULE_ID_DP,
  2560. QDF_TRACE_LEVEL_DEBUG,
  2561. FL("pkt send failed"));
  2562. qdf_nbuf_free(nbuf_clone);
  2563. } else {
  2564. if (peer_id != DP_INVALID_PEER)
  2565. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2566. 1, qdf_nbuf_len(nbuf));
  2567. }
  2568. }
  2569. }
  2570. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2571. }
  2572. /**
  2573. * dp_tx_send() - Transmit a frame on a given VAP
  2574. * @soc: DP soc handle
  2575. * @vdev_id: id of DP vdev handle
  2576. * @nbuf: skb
  2577. *
  2578. * Entry point for Core Tx layer (DP_TX) invoked from
  2579. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2580. * cases
  2581. *
  2582. * Return: NULL on success,
  2583. * nbuf when it fails to send
  2584. */
  2585. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2586. qdf_nbuf_t nbuf)
  2587. {
  2588. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2589. uint16_t peer_id = HTT_INVALID_PEER;
  2590. /*
  2591. * doing a memzero is causing additional function call overhead
  2592. * so doing static stack clearing
  2593. */
  2594. struct dp_tx_msdu_info_s msdu_info = {0};
  2595. struct dp_vdev *vdev = NULL;
  2596. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2597. return nbuf;
  2598. /*
  2599. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2600. * this in per packet path.
  2601. *
  2602. * As in this path vdev memory is already protected with netdev
  2603. * tx lock
  2604. */
  2605. vdev = soc->vdev_id_map[vdev_id];
  2606. if (qdf_unlikely(!vdev))
  2607. return nbuf;
  2608. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2609. QDF_MAC_ADDR_REF(nbuf->data));
  2610. /*
  2611. * Set Default Host TID value to invalid TID
  2612. * (TID override disabled)
  2613. */
  2614. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2615. dp_tx_wds_ext(soc, vdev, peer_id, &msdu_info);
  2616. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2617. if (qdf_unlikely(vdev->mesh_vdev)) {
  2618. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2619. &msdu_info);
  2620. if (!nbuf_mesh) {
  2621. dp_verbose_debug("Extracting mesh metadata failed");
  2622. return nbuf;
  2623. }
  2624. nbuf = nbuf_mesh;
  2625. }
  2626. /*
  2627. * Get HW Queue to use for this frame.
  2628. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2629. * dedicated for data and 1 for command.
  2630. * "queue_id" maps to one hardware ring.
  2631. * With each ring, we also associate a unique Tx descriptor pool
  2632. * to minimize lock contention for these resources.
  2633. */
  2634. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2635. /*
  2636. * TCL H/W supports 2 DSCP-TID mapping tables.
  2637. * Table 1 - Default DSCP-TID mapping table
  2638. * Table 2 - 1 DSCP-TID override table
  2639. *
  2640. * If we need a different DSCP-TID mapping for this vap,
  2641. * call tid_classify to extract DSCP/ToS from frame and
  2642. * map to a TID and store in msdu_info. This is later used
  2643. * to fill in TCL Input descriptor (per-packet TID override).
  2644. */
  2645. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2646. /*
  2647. * Classify the frame and call corresponding
  2648. * "prepare" function which extracts the segment (TSO)
  2649. * and fragmentation information (for TSO , SG, ME, or Raw)
  2650. * into MSDU_INFO structure which is later used to fill
  2651. * SW and HW descriptors.
  2652. */
  2653. if (qdf_nbuf_is_tso(nbuf)) {
  2654. dp_verbose_debug("TSO frame %pK", vdev);
  2655. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2656. qdf_nbuf_len(nbuf));
  2657. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2658. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2659. qdf_nbuf_len(nbuf));
  2660. return nbuf;
  2661. }
  2662. goto send_multiple;
  2663. }
  2664. /* SG */
  2665. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2666. struct dp_tx_seg_info_s seg_info = {0};
  2667. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2668. if (!nbuf)
  2669. return NULL;
  2670. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2671. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2672. qdf_nbuf_len(nbuf));
  2673. goto send_multiple;
  2674. }
  2675. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2676. return NULL;
  2677. /* RAW */
  2678. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2679. struct dp_tx_seg_info_s seg_info = {0};
  2680. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2681. if (!nbuf)
  2682. return NULL;
  2683. dp_verbose_debug("Raw frame %pK", vdev);
  2684. goto send_multiple;
  2685. }
  2686. if (qdf_unlikely(vdev->nawds_enabled)) {
  2687. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2688. qdf_nbuf_data(nbuf);
  2689. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2690. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2691. peer_id = DP_INVALID_PEER;
  2692. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2693. 1, qdf_nbuf_len(nbuf));
  2694. }
  2695. /* Single linear frame */
  2696. /*
  2697. * If nbuf is a simple linear frame, use send_single function to
  2698. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2699. * SRNG. There is no need to setup a MSDU extension descriptor.
  2700. */
  2701. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2702. return nbuf;
  2703. send_multiple:
  2704. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2705. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2706. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2707. return nbuf;
  2708. }
  2709. /**
  2710. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2711. * case to vaoid check in perpkt path.
  2712. * @soc: DP soc handle
  2713. * @vdev_id: id of DP vdev handle
  2714. * @nbuf: skb
  2715. *
  2716. * Entry point for Core Tx layer (DP_TX) invoked from
  2717. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2718. * with special condition to avoid per pkt check in dp_tx_send
  2719. *
  2720. * Return: NULL on success,
  2721. * nbuf when it fails to send
  2722. */
  2723. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2724. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2725. {
  2726. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2727. struct dp_vdev *vdev = NULL;
  2728. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2729. return nbuf;
  2730. /*
  2731. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2732. * this in per packet path.
  2733. *
  2734. * As in this path vdev memory is already protected with netdev
  2735. * tx lock
  2736. */
  2737. vdev = soc->vdev_id_map[vdev_id];
  2738. if (qdf_unlikely(!vdev))
  2739. return nbuf;
  2740. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2741. == QDF_STATUS_E_FAILURE)) {
  2742. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2743. return nbuf;
  2744. }
  2745. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2746. }
  2747. /**
  2748. * dp_tx_reinject_handler() - Tx Reinject Handler
  2749. * @soc: datapath soc handle
  2750. * @vdev: datapath vdev handle
  2751. * @tx_desc: software descriptor head pointer
  2752. * @status : Tx completion status from HTT descriptor
  2753. *
  2754. * This function reinjects frames back to Target.
  2755. * Todo - Host queue needs to be added
  2756. *
  2757. * Return: none
  2758. */
  2759. static
  2760. void dp_tx_reinject_handler(struct dp_soc *soc,
  2761. struct dp_vdev *vdev,
  2762. struct dp_tx_desc_s *tx_desc,
  2763. uint8_t *status)
  2764. {
  2765. struct dp_peer *peer = NULL;
  2766. uint32_t peer_id = HTT_INVALID_PEER;
  2767. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2768. qdf_nbuf_t nbuf_copy = NULL;
  2769. struct dp_tx_msdu_info_s msdu_info;
  2770. #ifdef WDS_VENDOR_EXTENSION
  2771. int is_mcast = 0, is_ucast = 0;
  2772. int num_peers_3addr = 0;
  2773. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2774. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2775. #endif
  2776. qdf_assert(vdev);
  2777. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2778. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2780. "%s Tx reinject path", __func__);
  2781. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2782. qdf_nbuf_len(tx_desc->nbuf));
  2783. #ifdef WDS_VENDOR_EXTENSION
  2784. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2785. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2786. } else {
  2787. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2788. }
  2789. is_ucast = !is_mcast;
  2790. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2791. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2792. if (peer->bss_peer)
  2793. continue;
  2794. /* Detect wds peers that use 3-addr framing for mcast.
  2795. * if there are any, the bss_peer is used to send the
  2796. * the mcast frame using 3-addr format. all wds enabled
  2797. * peers that use 4-addr framing for mcast frames will
  2798. * be duplicated and sent as 4-addr frames below.
  2799. */
  2800. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2801. num_peers_3addr = 1;
  2802. break;
  2803. }
  2804. }
  2805. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2806. #endif
  2807. if (qdf_unlikely(vdev->mesh_vdev)) {
  2808. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2809. } else {
  2810. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2811. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2812. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2813. #ifdef WDS_VENDOR_EXTENSION
  2814. /*
  2815. * . if 3-addr STA, then send on BSS Peer
  2816. * . if Peer WDS enabled and accept 4-addr mcast,
  2817. * send mcast on that peer only
  2818. * . if Peer WDS enabled and accept 4-addr ucast,
  2819. * send ucast on that peer only
  2820. */
  2821. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2822. (peer->wds_enabled &&
  2823. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2824. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2825. #else
  2826. ((peer->bss_peer &&
  2827. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2828. #endif
  2829. peer_id = DP_INVALID_PEER;
  2830. nbuf_copy = qdf_nbuf_copy(nbuf);
  2831. if (!nbuf_copy) {
  2832. QDF_TRACE(QDF_MODULE_ID_DP,
  2833. QDF_TRACE_LEVEL_DEBUG,
  2834. FL("nbuf copy failed"));
  2835. break;
  2836. }
  2837. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2838. nbuf_copy,
  2839. &msdu_info,
  2840. peer_id,
  2841. NULL);
  2842. if (nbuf_copy) {
  2843. QDF_TRACE(QDF_MODULE_ID_DP,
  2844. QDF_TRACE_LEVEL_DEBUG,
  2845. FL("pkt send failed"));
  2846. qdf_nbuf_free(nbuf_copy);
  2847. }
  2848. }
  2849. }
  2850. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2851. }
  2852. qdf_nbuf_free(nbuf);
  2853. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2854. }
  2855. /**
  2856. * dp_tx_inspect_handler() - Tx Inspect Handler
  2857. * @soc: datapath soc handle
  2858. * @vdev: datapath vdev handle
  2859. * @tx_desc: software descriptor head pointer
  2860. * @status : Tx completion status from HTT descriptor
  2861. *
  2862. * Handles Tx frames sent back to Host for inspection
  2863. * (ProxyARP)
  2864. *
  2865. * Return: none
  2866. */
  2867. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2868. struct dp_vdev *vdev,
  2869. struct dp_tx_desc_s *tx_desc,
  2870. uint8_t *status)
  2871. {
  2872. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2873. "%s Tx inspect path",
  2874. __func__);
  2875. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2876. qdf_nbuf_len(tx_desc->nbuf));
  2877. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2878. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2879. }
  2880. #ifdef FEATURE_PERPKT_INFO
  2881. /**
  2882. * dp_get_completion_indication_for_stack() - send completion to stack
  2883. * @soc : dp_soc handle
  2884. * @pdev: dp_pdev handle
  2885. * @peer: dp peer handle
  2886. * @ts: transmit completion status structure
  2887. * @netbuf: Buffer pointer for free
  2888. *
  2889. * This function is used for indication whether buffer needs to be
  2890. * sent to stack for freeing or not
  2891. */
  2892. QDF_STATUS
  2893. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2894. struct dp_pdev *pdev,
  2895. struct dp_peer *peer,
  2896. struct hal_tx_completion_status *ts,
  2897. qdf_nbuf_t netbuf,
  2898. uint64_t time_latency)
  2899. {
  2900. struct tx_capture_hdr *ppdu_hdr;
  2901. uint16_t peer_id = ts->peer_id;
  2902. uint32_t ppdu_id = ts->ppdu_id;
  2903. uint8_t first_msdu = ts->first_msdu;
  2904. uint8_t last_msdu = ts->last_msdu;
  2905. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2906. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2907. !pdev->latency_capture_enable))
  2908. return QDF_STATUS_E_NOSUPPORT;
  2909. if (!peer) {
  2910. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2911. FL("Peer Invalid"));
  2912. return QDF_STATUS_E_INVAL;
  2913. }
  2914. if (pdev->mcopy_mode) {
  2915. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2916. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2917. * for each MPDU
  2918. */
  2919. if (pdev->mcopy_mode == M_COPY) {
  2920. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2921. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2922. return QDF_STATUS_E_INVAL;
  2923. }
  2924. }
  2925. if (!first_msdu)
  2926. return QDF_STATUS_E_INVAL;
  2927. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2928. pdev->m_copy_id.tx_peer_id = peer_id;
  2929. }
  2930. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2931. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2932. if (!netbuf) {
  2933. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2934. FL("No headroom"));
  2935. return QDF_STATUS_E_NOMEM;
  2936. }
  2937. }
  2938. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2940. FL("No headroom"));
  2941. return QDF_STATUS_E_NOMEM;
  2942. }
  2943. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2944. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2945. QDF_MAC_ADDR_SIZE);
  2946. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2947. QDF_MAC_ADDR_SIZE);
  2948. ppdu_hdr->ppdu_id = ppdu_id;
  2949. ppdu_hdr->peer_id = peer_id;
  2950. ppdu_hdr->first_msdu = first_msdu;
  2951. ppdu_hdr->last_msdu = last_msdu;
  2952. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2953. ppdu_hdr->tsf = ts->tsf;
  2954. ppdu_hdr->time_latency = time_latency;
  2955. }
  2956. return QDF_STATUS_SUCCESS;
  2957. }
  2958. /**
  2959. * dp_send_completion_to_stack() - send completion to stack
  2960. * @soc : dp_soc handle
  2961. * @pdev: dp_pdev handle
  2962. * @peer_id: peer_id of the peer for which completion came
  2963. * @ppdu_id: ppdu_id
  2964. * @netbuf: Buffer pointer for free
  2965. *
  2966. * This function is used to send completion to stack
  2967. * to free buffer
  2968. */
  2969. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2970. uint16_t peer_id, uint32_t ppdu_id,
  2971. qdf_nbuf_t netbuf)
  2972. {
  2973. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2974. netbuf, peer_id,
  2975. WDI_NO_VAL, pdev->pdev_id);
  2976. }
  2977. #else
  2978. static QDF_STATUS
  2979. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2980. struct dp_pdev *pdev,
  2981. struct dp_peer *peer,
  2982. struct hal_tx_completion_status *ts,
  2983. qdf_nbuf_t netbuf,
  2984. uint64_t time_latency)
  2985. {
  2986. return QDF_STATUS_E_NOSUPPORT;
  2987. }
  2988. static void
  2989. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2990. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2991. {
  2992. }
  2993. #endif
  2994. /**
  2995. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2996. * @soc: Soc handle
  2997. * @desc: software Tx descriptor to be processed
  2998. *
  2999. * Return: none
  3000. */
  3001. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  3002. struct dp_tx_desc_s *desc)
  3003. {
  3004. qdf_nbuf_t nbuf = desc->nbuf;
  3005. /* nbuf already freed in vdev detach path */
  3006. if (!nbuf)
  3007. return;
  3008. /* If it is TDLS mgmt, don't unmap or free the frame */
  3009. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  3010. return dp_non_std_tx_comp_free_buff(soc, desc);
  3011. /* 0 : MSDU buffer, 1 : MLE */
  3012. if (desc->msdu_ext_desc) {
  3013. /* TSO free */
  3014. if (hal_tx_ext_desc_get_tso_enable(
  3015. desc->msdu_ext_desc->vaddr)) {
  3016. /* unmap eash TSO seg before free the nbuf */
  3017. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  3018. desc->tso_num_desc);
  3019. qdf_nbuf_free(nbuf);
  3020. return;
  3021. }
  3022. }
  3023. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  3024. QDF_DMA_TO_DEVICE, nbuf->len);
  3025. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  3026. return dp_mesh_tx_comp_free_buff(soc, desc);
  3027. qdf_nbuf_free(nbuf);
  3028. }
  3029. #ifdef MESH_MODE_SUPPORT
  3030. /**
  3031. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3032. * in mesh meta header
  3033. * @tx_desc: software descriptor head pointer
  3034. * @ts: pointer to tx completion stats
  3035. * Return: none
  3036. */
  3037. static
  3038. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3039. struct hal_tx_completion_status *ts)
  3040. {
  3041. struct meta_hdr_s *mhdr;
  3042. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3043. if (!tx_desc->msdu_ext_desc) {
  3044. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3046. "netbuf %pK offset %d",
  3047. netbuf, tx_desc->pkt_offset);
  3048. return;
  3049. }
  3050. }
  3051. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3052. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3053. "netbuf %pK offset %lu", netbuf,
  3054. sizeof(struct meta_hdr_s));
  3055. return;
  3056. }
  3057. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3058. mhdr->rssi = ts->ack_frame_rssi;
  3059. mhdr->band = tx_desc->pdev->operating_channel.band;
  3060. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3061. }
  3062. #else
  3063. static
  3064. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3065. struct hal_tx_completion_status *ts)
  3066. {
  3067. }
  3068. #endif
  3069. #ifdef QCA_PEER_EXT_STATS
  3070. /*
  3071. * dp_tx_compute_tid_delay() - Compute per TID delay
  3072. * @stats: Per TID delay stats
  3073. * @tx_desc: Software Tx descriptor
  3074. *
  3075. * Compute the software enqueue and hw enqueue delays and
  3076. * update the respective histograms
  3077. *
  3078. * Return: void
  3079. */
  3080. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3081. struct dp_tx_desc_s *tx_desc)
  3082. {
  3083. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3084. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3085. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3086. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3087. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3088. timestamp_hw_enqueue = tx_desc->timestamp;
  3089. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3090. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3091. timestamp_hw_enqueue);
  3092. /*
  3093. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3094. */
  3095. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3096. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3097. }
  3098. /*
  3099. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3100. * @peer: DP peer context
  3101. * @tx_desc: Tx software descriptor
  3102. * @tid: Transmission ID
  3103. * @ring_id: Rx CPU context ID/CPU_ID
  3104. *
  3105. * Update the peer extended stats. These are enhanced other
  3106. * delay stats per msdu level.
  3107. *
  3108. * Return: void
  3109. */
  3110. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3111. struct dp_tx_desc_s *tx_desc,
  3112. uint8_t tid, uint8_t ring_id)
  3113. {
  3114. struct dp_pdev *pdev = peer->vdev->pdev;
  3115. struct dp_soc *soc = NULL;
  3116. struct cdp_peer_ext_stats *pext_stats = NULL;
  3117. soc = pdev->soc;
  3118. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3119. return;
  3120. pext_stats = peer->pext_stats;
  3121. qdf_assert(pext_stats);
  3122. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3123. /*
  3124. * For non-TID packets use the TID 9
  3125. */
  3126. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3127. tid = CDP_MAX_DATA_TIDS - 1;
  3128. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3129. tx_desc);
  3130. }
  3131. #else
  3132. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3133. struct dp_tx_desc_s *tx_desc,
  3134. uint8_t tid, uint8_t ring_id)
  3135. {
  3136. }
  3137. #endif
  3138. /**
  3139. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3140. * to pass in correct fields
  3141. *
  3142. * @vdev: pdev handle
  3143. * @tx_desc: tx descriptor
  3144. * @tid: tid value
  3145. * @ring_id: TCL or WBM ring number for transmit path
  3146. * Return: none
  3147. */
  3148. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3149. struct dp_tx_desc_s *tx_desc,
  3150. uint8_t tid, uint8_t ring_id)
  3151. {
  3152. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3153. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3154. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3155. return;
  3156. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3157. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3158. timestamp_hw_enqueue = tx_desc->timestamp;
  3159. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3160. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3161. timestamp_hw_enqueue);
  3162. interframe_delay = (uint32_t)(timestamp_ingress -
  3163. vdev->prev_tx_enq_tstamp);
  3164. /*
  3165. * Delay in software enqueue
  3166. */
  3167. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3168. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3169. /*
  3170. * Delay between packet enqueued to HW and Tx completion
  3171. */
  3172. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3173. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3174. /*
  3175. * Update interframe delay stats calculated at hardstart receive point.
  3176. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3177. * interframe delay will not be calculate correctly for 1st frame.
  3178. * On the other side, this will help in avoiding extra per packet check
  3179. * of !vdev->prev_tx_enq_tstamp.
  3180. */
  3181. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3182. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3183. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3184. }
  3185. #ifdef DISABLE_DP_STATS
  3186. static
  3187. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3188. {
  3189. }
  3190. #else
  3191. static
  3192. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3193. {
  3194. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3195. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3196. if (subtype != QDF_PROTO_INVALID)
  3197. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3198. }
  3199. #endif
  3200. /**
  3201. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3202. * per wbm ring
  3203. *
  3204. * @tx_desc: software descriptor head pointer
  3205. * @ts: Tx completion status
  3206. * @peer: peer handle
  3207. * @ring_id: ring number
  3208. *
  3209. * Return: None
  3210. */
  3211. static inline void
  3212. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3213. struct hal_tx_completion_status *ts,
  3214. struct dp_peer *peer, uint8_t ring_id)
  3215. {
  3216. struct dp_pdev *pdev = peer->vdev->pdev;
  3217. struct dp_soc *soc = NULL;
  3218. uint8_t mcs, pkt_type;
  3219. uint8_t tid = ts->tid;
  3220. uint32_t length;
  3221. struct cdp_tid_tx_stats *tid_stats;
  3222. if (!pdev)
  3223. return;
  3224. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3225. tid = CDP_MAX_DATA_TIDS - 1;
  3226. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3227. soc = pdev->soc;
  3228. mcs = ts->mcs;
  3229. pkt_type = ts->pkt_type;
  3230. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3231. dp_err("Release source is not from TQM");
  3232. return;
  3233. }
  3234. length = qdf_nbuf_len(tx_desc->nbuf);
  3235. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3236. if (qdf_unlikely(pdev->delay_stats_flag))
  3237. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3238. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3239. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3240. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3241. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3242. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3243. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3244. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3245. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3246. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3247. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3248. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3249. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3250. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3251. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3252. /*
  3253. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3254. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3255. * are no completions for failed cases. Hence updating tx_failed from
  3256. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3257. * then this has to be removed
  3258. */
  3259. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3260. peer->stats.tx.dropped.fw_rem_notx +
  3261. peer->stats.tx.dropped.fw_rem_tx +
  3262. peer->stats.tx.dropped.age_out +
  3263. peer->stats.tx.dropped.fw_reason1 +
  3264. peer->stats.tx.dropped.fw_reason2 +
  3265. peer->stats.tx.dropped.fw_reason3;
  3266. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3267. tid_stats->tqm_status_cnt[ts->status]++;
  3268. }
  3269. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3270. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3271. return;
  3272. }
  3273. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3274. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3275. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3276. /*
  3277. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3278. * Return from here if HTT PPDU events are enabled.
  3279. */
  3280. if (!(soc->process_tx_status))
  3281. return;
  3282. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3283. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3284. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3285. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3286. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3287. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3288. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3289. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3290. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3291. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3292. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3293. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3294. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3295. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3296. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3297. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3298. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3299. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3300. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3301. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3302. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3303. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3304. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3305. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3306. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3307. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3308. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3309. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3310. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3311. &peer->stats, ts->peer_id,
  3312. UPDATE_PEER_STATS, pdev->pdev_id);
  3313. #endif
  3314. }
  3315. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3316. /**
  3317. * dp_tx_flow_pool_lock() - take flow pool lock
  3318. * @soc: core txrx main context
  3319. * @tx_desc: tx desc
  3320. *
  3321. * Return: None
  3322. */
  3323. static inline
  3324. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3325. struct dp_tx_desc_s *tx_desc)
  3326. {
  3327. struct dp_tx_desc_pool_s *pool;
  3328. uint8_t desc_pool_id;
  3329. desc_pool_id = tx_desc->pool_id;
  3330. pool = &soc->tx_desc[desc_pool_id];
  3331. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3332. }
  3333. /**
  3334. * dp_tx_flow_pool_unlock() - release flow pool lock
  3335. * @soc: core txrx main context
  3336. * @tx_desc: tx desc
  3337. *
  3338. * Return: None
  3339. */
  3340. static inline
  3341. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3342. struct dp_tx_desc_s *tx_desc)
  3343. {
  3344. struct dp_tx_desc_pool_s *pool;
  3345. uint8_t desc_pool_id;
  3346. desc_pool_id = tx_desc->pool_id;
  3347. pool = &soc->tx_desc[desc_pool_id];
  3348. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3349. }
  3350. #else
  3351. static inline
  3352. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3353. {
  3354. }
  3355. static inline
  3356. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3357. {
  3358. }
  3359. #endif
  3360. /**
  3361. * dp_tx_notify_completion() - Notify tx completion for this desc
  3362. * @soc: core txrx main context
  3363. * @vdev: datapath vdev handle
  3364. * @tx_desc: tx desc
  3365. * @netbuf: buffer
  3366. * @status: tx status
  3367. *
  3368. * Return: none
  3369. */
  3370. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3371. struct dp_vdev *vdev,
  3372. struct dp_tx_desc_s *tx_desc,
  3373. qdf_nbuf_t netbuf,
  3374. uint8_t status)
  3375. {
  3376. void *osif_dev;
  3377. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3378. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3379. qdf_assert(tx_desc);
  3380. dp_tx_flow_pool_lock(soc, tx_desc);
  3381. if (!vdev ||
  3382. !vdev->osif_vdev) {
  3383. dp_tx_flow_pool_unlock(soc, tx_desc);
  3384. return;
  3385. }
  3386. osif_dev = vdev->osif_vdev;
  3387. tx_compl_cbk = vdev->tx_comp;
  3388. dp_tx_flow_pool_unlock(soc, tx_desc);
  3389. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3390. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3391. if (tx_compl_cbk)
  3392. tx_compl_cbk(netbuf, osif_dev, flag);
  3393. }
  3394. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3395. * @pdev: pdev handle
  3396. * @tid: tid value
  3397. * @txdesc_ts: timestamp from txdesc
  3398. * @ppdu_id: ppdu id
  3399. *
  3400. * Return: none
  3401. */
  3402. #ifdef FEATURE_PERPKT_INFO
  3403. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3404. struct dp_peer *peer,
  3405. uint8_t tid,
  3406. uint64_t txdesc_ts,
  3407. uint32_t ppdu_id)
  3408. {
  3409. uint64_t delta_ms;
  3410. struct cdp_tx_sojourn_stats *sojourn_stats;
  3411. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3412. return;
  3413. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3414. tid >= CDP_DATA_TID_MAX))
  3415. return;
  3416. if (qdf_unlikely(!pdev->sojourn_buf))
  3417. return;
  3418. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3419. qdf_nbuf_data(pdev->sojourn_buf);
  3420. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3421. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3422. txdesc_ts;
  3423. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3424. delta_ms);
  3425. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3426. sojourn_stats->num_msdus[tid] = 1;
  3427. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3428. peer->avg_sojourn_msdu[tid].internal;
  3429. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3430. pdev->sojourn_buf, HTT_INVALID_PEER,
  3431. WDI_NO_VAL, pdev->pdev_id);
  3432. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3433. sojourn_stats->num_msdus[tid] = 0;
  3434. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3435. }
  3436. #else
  3437. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3438. struct dp_peer *peer,
  3439. uint8_t tid,
  3440. uint64_t txdesc_ts,
  3441. uint32_t ppdu_id)
  3442. {
  3443. }
  3444. #endif
  3445. /**
  3446. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3447. * @soc: DP Soc handle
  3448. * @tx_desc: software Tx descriptor
  3449. * @ts : Tx completion status from HAL/HTT descriptor
  3450. *
  3451. * Return: none
  3452. */
  3453. static inline void
  3454. dp_tx_comp_process_desc(struct dp_soc *soc,
  3455. struct dp_tx_desc_s *desc,
  3456. struct hal_tx_completion_status *ts,
  3457. struct dp_peer *peer)
  3458. {
  3459. uint64_t time_latency = 0;
  3460. /*
  3461. * m_copy/tx_capture modes are not supported for
  3462. * scatter gather packets
  3463. */
  3464. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3465. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3466. desc->timestamp);
  3467. }
  3468. if (!(desc->msdu_ext_desc)) {
  3469. if (QDF_STATUS_SUCCESS ==
  3470. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3471. return;
  3472. }
  3473. if (QDF_STATUS_SUCCESS ==
  3474. dp_get_completion_indication_for_stack(soc,
  3475. desc->pdev,
  3476. peer, ts,
  3477. desc->nbuf,
  3478. time_latency)) {
  3479. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3480. QDF_DMA_TO_DEVICE,
  3481. desc->nbuf->len);
  3482. dp_send_completion_to_stack(soc,
  3483. desc->pdev,
  3484. ts->peer_id,
  3485. ts->ppdu_id,
  3486. desc->nbuf);
  3487. return;
  3488. }
  3489. }
  3490. dp_tx_comp_free_buf(soc, desc);
  3491. }
  3492. #ifdef DISABLE_DP_STATS
  3493. /**
  3494. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3495. * @soc: core txrx main context
  3496. * @tx_desc: tx desc
  3497. * @status: tx status
  3498. *
  3499. * Return: none
  3500. */
  3501. static inline
  3502. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3503. struct dp_vdev *vdev,
  3504. struct dp_tx_desc_s *tx_desc,
  3505. uint8_t status)
  3506. {
  3507. }
  3508. #else
  3509. static inline
  3510. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3511. struct dp_vdev *vdev,
  3512. struct dp_tx_desc_s *tx_desc,
  3513. uint8_t status)
  3514. {
  3515. void *osif_dev;
  3516. ol_txrx_stats_rx_fp stats_cbk;
  3517. uint8_t pkt_type;
  3518. qdf_assert(tx_desc);
  3519. if (!vdev ||
  3520. !vdev->osif_vdev ||
  3521. !vdev->stats_cb)
  3522. return;
  3523. osif_dev = vdev->osif_vdev;
  3524. stats_cbk = vdev->stats_cb;
  3525. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3526. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3527. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3528. &pkt_type);
  3529. }
  3530. #endif
  3531. /**
  3532. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3533. * @soc: DP soc handle
  3534. * @tx_desc: software descriptor head pointer
  3535. * @ts: Tx completion status
  3536. * @peer: peer handle
  3537. * @ring_id: ring number
  3538. *
  3539. * Return: none
  3540. */
  3541. static inline
  3542. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3543. struct dp_tx_desc_s *tx_desc,
  3544. struct hal_tx_completion_status *ts,
  3545. struct dp_peer *peer, uint8_t ring_id)
  3546. {
  3547. uint32_t length;
  3548. qdf_ether_header_t *eh;
  3549. struct dp_vdev *vdev = NULL;
  3550. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3551. uint8_t dp_status;
  3552. if (!nbuf) {
  3553. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3554. goto out;
  3555. }
  3556. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3557. length = qdf_nbuf_len(nbuf);
  3558. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3559. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3560. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3561. QDF_TRACE_DEFAULT_PDEV_ID,
  3562. qdf_nbuf_data_addr(nbuf),
  3563. sizeof(qdf_nbuf_data(nbuf)),
  3564. tx_desc->id,
  3565. dp_status));
  3566. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3567. "-------------------- \n"
  3568. "Tx Completion Stats: \n"
  3569. "-------------------- \n"
  3570. "ack_frame_rssi = %d \n"
  3571. "first_msdu = %d \n"
  3572. "last_msdu = %d \n"
  3573. "msdu_part_of_amsdu = %d \n"
  3574. "rate_stats valid = %d \n"
  3575. "bw = %d \n"
  3576. "pkt_type = %d \n"
  3577. "stbc = %d \n"
  3578. "ldpc = %d \n"
  3579. "sgi = %d \n"
  3580. "mcs = %d \n"
  3581. "ofdma = %d \n"
  3582. "tones_in_ru = %d \n"
  3583. "tsf = %d \n"
  3584. "ppdu_id = %d \n"
  3585. "transmit_cnt = %d \n"
  3586. "tid = %d \n"
  3587. "peer_id = %d\n",
  3588. ts->ack_frame_rssi, ts->first_msdu,
  3589. ts->last_msdu, ts->msdu_part_of_amsdu,
  3590. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3591. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3592. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3593. ts->transmit_cnt, ts->tid, ts->peer_id);
  3594. /* Update SoC level stats */
  3595. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3596. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3597. if (!peer) {
  3598. dp_err_rl("peer is null or deletion in progress");
  3599. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3600. goto out;
  3601. }
  3602. vdev = peer->vdev;
  3603. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3604. /* Update per-packet stats for mesh mode */
  3605. if (qdf_unlikely(vdev->mesh_vdev) &&
  3606. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3607. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3608. /* Update peer level stats */
  3609. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3610. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3611. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3612. if ((peer->vdev->tx_encap_type ==
  3613. htt_cmn_pkt_type_ethernet) &&
  3614. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3615. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3616. }
  3617. }
  3618. } else {
  3619. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3620. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3621. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3622. if (qdf_unlikely(peer->in_twt)) {
  3623. DP_STATS_INC_PKT(peer,
  3624. tx.tx_success_twt,
  3625. 1, length);
  3626. }
  3627. }
  3628. }
  3629. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3630. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3631. #ifdef QCA_SUPPORT_RDK_STATS
  3632. if (soc->rdkstats_enabled)
  3633. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3634. tx_desc->timestamp,
  3635. ts->ppdu_id);
  3636. #endif
  3637. out:
  3638. return;
  3639. }
  3640. /**
  3641. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3642. * @soc: core txrx main context
  3643. * @comp_head: software descriptor head pointer
  3644. * @ring_id: ring number
  3645. *
  3646. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3647. * and release the software descriptors after processing is complete
  3648. *
  3649. * Return: none
  3650. */
  3651. static void
  3652. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3653. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3654. {
  3655. struct dp_tx_desc_s *desc;
  3656. struct dp_tx_desc_s *next;
  3657. struct hal_tx_completion_status ts;
  3658. struct dp_peer *peer = NULL;
  3659. uint16_t peer_id = DP_INVALID_PEER;
  3660. qdf_nbuf_t netbuf;
  3661. desc = comp_head;
  3662. while (desc) {
  3663. if (peer_id != desc->peer_id) {
  3664. if (peer)
  3665. dp_peer_unref_delete(peer,
  3666. DP_MOD_ID_TX_COMP);
  3667. peer_id = desc->peer_id;
  3668. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3669. DP_MOD_ID_TX_COMP);
  3670. }
  3671. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3672. struct dp_pdev *pdev = desc->pdev;
  3673. if (qdf_likely(peer)) {
  3674. /*
  3675. * Increment peer statistics
  3676. * Minimal statistics update done here
  3677. */
  3678. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3679. desc->length);
  3680. if (desc->tx_status !=
  3681. HAL_TX_TQM_RR_FRAME_ACKED)
  3682. DP_STATS_INC(peer, tx.tx_failed, 1);
  3683. }
  3684. qdf_assert(pdev);
  3685. dp_tx_outstanding_dec(pdev);
  3686. /*
  3687. * Calling a QDF WRAPPER here is creating signifcant
  3688. * performance impact so avoided the wrapper call here
  3689. */
  3690. next = desc->next;
  3691. qdf_mem_unmap_nbytes_single(soc->osdev,
  3692. desc->dma_addr,
  3693. QDF_DMA_TO_DEVICE,
  3694. desc->length);
  3695. qdf_nbuf_free(desc->nbuf);
  3696. dp_tx_desc_free(soc, desc, desc->pool_id);
  3697. desc = next;
  3698. continue;
  3699. }
  3700. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3701. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3702. netbuf = desc->nbuf;
  3703. /* check tx complete notification */
  3704. if (peer &&
  3705. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3706. dp_tx_notify_completion(soc, peer->vdev, desc,
  3707. netbuf, ts.status);
  3708. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3709. next = desc->next;
  3710. dp_tx_desc_release(desc, desc->pool_id);
  3711. desc = next;
  3712. }
  3713. if (peer)
  3714. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3715. }
  3716. /**
  3717. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3718. * @tx_desc: software descriptor head pointer
  3719. * @status : Tx completion status from HTT descriptor
  3720. * @ring_id: ring number
  3721. *
  3722. * This function will process HTT Tx indication messages from Target
  3723. *
  3724. * Return: none
  3725. */
  3726. static
  3727. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3728. uint8_t ring_id)
  3729. {
  3730. uint8_t tx_status;
  3731. struct dp_pdev *pdev;
  3732. struct dp_vdev *vdev;
  3733. struct dp_soc *soc;
  3734. struct hal_tx_completion_status ts = {0};
  3735. uint32_t *htt_desc = (uint32_t *)status;
  3736. struct dp_peer *peer;
  3737. struct cdp_tid_tx_stats *tid_stats = NULL;
  3738. struct htt_soc *htt_handle;
  3739. /*
  3740. * If the descriptor is already freed in vdev_detach,
  3741. * continue to next descriptor
  3742. */
  3743. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3744. QDF_TRACE(QDF_MODULE_ID_DP,
  3745. QDF_TRACE_LEVEL_INFO,
  3746. "Descriptor freed in vdev_detach %d",
  3747. tx_desc->id);
  3748. return;
  3749. }
  3750. pdev = tx_desc->pdev;
  3751. soc = pdev->soc;
  3752. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3753. QDF_TRACE(QDF_MODULE_ID_DP,
  3754. QDF_TRACE_LEVEL_INFO,
  3755. "pdev in down state %d",
  3756. tx_desc->id);
  3757. dp_tx_comp_free_buf(soc, tx_desc);
  3758. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3759. return;
  3760. }
  3761. qdf_assert(tx_desc->pdev);
  3762. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3763. DP_MOD_ID_HTT_COMP);
  3764. if (!vdev)
  3765. return;
  3766. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3767. htt_handle = (struct htt_soc *)soc->htt_handle;
  3768. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3769. switch (tx_status) {
  3770. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3771. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3772. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3773. {
  3774. uint8_t tid;
  3775. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3776. ts.peer_id =
  3777. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3778. htt_desc[2]);
  3779. ts.tid =
  3780. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3781. htt_desc[2]);
  3782. } else {
  3783. ts.peer_id = HTT_INVALID_PEER;
  3784. ts.tid = HTT_INVALID_TID;
  3785. }
  3786. ts.ppdu_id =
  3787. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3788. htt_desc[1]);
  3789. ts.ack_frame_rssi =
  3790. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3791. htt_desc[1]);
  3792. ts.tsf = htt_desc[3];
  3793. ts.first_msdu = 1;
  3794. ts.last_msdu = 1;
  3795. tid = ts.tid;
  3796. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3797. tid = CDP_MAX_DATA_TIDS - 1;
  3798. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3799. if (qdf_unlikely(pdev->delay_stats_flag))
  3800. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3801. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3802. tid_stats->htt_status_cnt[tx_status]++;
  3803. }
  3804. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3805. DP_MOD_ID_HTT_COMP);
  3806. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3807. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3808. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3809. if (qdf_likely(peer))
  3810. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3811. break;
  3812. }
  3813. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3814. {
  3815. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3816. break;
  3817. }
  3818. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3819. {
  3820. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3821. break;
  3822. }
  3823. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3824. {
  3825. dp_tx_mec_handler(vdev, status);
  3826. break;
  3827. }
  3828. default:
  3829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3830. "%s Invalid HTT tx_status %d\n",
  3831. __func__, tx_status);
  3832. break;
  3833. }
  3834. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3835. }
  3836. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3837. static inline
  3838. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3839. {
  3840. bool limit_hit = false;
  3841. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3842. limit_hit =
  3843. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3844. if (limit_hit)
  3845. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3846. return limit_hit;
  3847. }
  3848. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3849. {
  3850. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3851. }
  3852. #else
  3853. static inline
  3854. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3855. {
  3856. return false;
  3857. }
  3858. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3859. {
  3860. return false;
  3861. }
  3862. #endif
  3863. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3864. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3865. uint32_t quota)
  3866. {
  3867. void *tx_comp_hal_desc;
  3868. uint8_t buffer_src;
  3869. uint8_t pool_id;
  3870. uint32_t tx_desc_id;
  3871. struct dp_tx_desc_s *tx_desc = NULL;
  3872. struct dp_tx_desc_s *head_desc = NULL;
  3873. struct dp_tx_desc_s *tail_desc = NULL;
  3874. uint32_t num_processed = 0;
  3875. uint32_t count;
  3876. uint32_t num_avail_for_reap = 0;
  3877. bool force_break = false;
  3878. DP_HIST_INIT();
  3879. more_data:
  3880. /* Re-initialize local variables to be re-used */
  3881. head_desc = NULL;
  3882. tail_desc = NULL;
  3883. count = 0;
  3884. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3885. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3886. return 0;
  3887. }
  3888. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3889. if (num_avail_for_reap >= quota)
  3890. num_avail_for_reap = quota;
  3891. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3892. /* Find head descriptor from completion ring */
  3893. while (qdf_likely(num_avail_for_reap)) {
  3894. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3895. if (qdf_unlikely(!tx_comp_hal_desc))
  3896. break;
  3897. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3898. /* If this buffer was not released by TQM or FW, then it is not
  3899. * Tx completion indication, assert */
  3900. if (qdf_unlikely(buffer_src !=
  3901. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3902. (qdf_unlikely(buffer_src !=
  3903. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3904. uint8_t wbm_internal_error;
  3905. dp_err_rl(
  3906. "Tx comp release_src != TQM | FW but from %d",
  3907. buffer_src);
  3908. hal_dump_comp_desc(tx_comp_hal_desc);
  3909. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3910. /* When WBM sees NULL buffer_addr_info in any of
  3911. * ingress rings it sends an error indication,
  3912. * with wbm_internal_error=1, to a specific ring.
  3913. * The WBM2SW ring used to indicate these errors is
  3914. * fixed in HW, and that ring is being used as Tx
  3915. * completion ring. These errors are not related to
  3916. * Tx completions, and should just be ignored
  3917. */
  3918. wbm_internal_error = hal_get_wbm_internal_error(
  3919. soc->hal_soc,
  3920. tx_comp_hal_desc);
  3921. if (wbm_internal_error) {
  3922. dp_err_rl("Tx comp wbm_internal_error!!");
  3923. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3924. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3925. buffer_src)
  3926. dp_handle_wbm_internal_error(
  3927. soc,
  3928. tx_comp_hal_desc,
  3929. hal_tx_comp_get_buffer_type(
  3930. tx_comp_hal_desc));
  3931. } else {
  3932. dp_err_rl("Tx comp wbm_internal_error false");
  3933. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3934. }
  3935. continue;
  3936. }
  3937. /* Get descriptor id */
  3938. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3939. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3940. DP_TX_DESC_ID_POOL_OS;
  3941. /* Find Tx descriptor */
  3942. tx_desc = dp_tx_desc_find(soc, pool_id,
  3943. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3944. DP_TX_DESC_ID_PAGE_OS,
  3945. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3946. DP_TX_DESC_ID_OFFSET_OS);
  3947. /*
  3948. * If the release source is FW, process the HTT status
  3949. */
  3950. if (qdf_unlikely(buffer_src ==
  3951. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3952. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3953. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3954. htt_tx_status);
  3955. dp_tx_process_htt_completion(tx_desc,
  3956. htt_tx_status, ring_id);
  3957. } else {
  3958. tx_desc->peer_id =
  3959. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3960. tx_desc->tx_status =
  3961. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3962. /*
  3963. * If the fast completion mode is enabled extended
  3964. * metadata from descriptor is not copied
  3965. */
  3966. if (qdf_likely(tx_desc->flags &
  3967. DP_TX_DESC_FLAG_SIMPLE))
  3968. goto add_to_pool;
  3969. /*
  3970. * If the descriptor is already freed in vdev_detach,
  3971. * continue to next descriptor
  3972. */
  3973. if (qdf_unlikely
  3974. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3975. !tx_desc->flags)) {
  3976. QDF_TRACE(QDF_MODULE_ID_DP,
  3977. QDF_TRACE_LEVEL_INFO,
  3978. "Descriptor freed in vdev_detach %d",
  3979. tx_desc_id);
  3980. continue;
  3981. }
  3982. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3983. QDF_TRACE(QDF_MODULE_ID_DP,
  3984. QDF_TRACE_LEVEL_INFO,
  3985. "pdev in down state %d",
  3986. tx_desc_id);
  3987. dp_tx_comp_free_buf(soc, tx_desc);
  3988. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3989. goto next_desc;
  3990. }
  3991. /* Pool id is not matching. Error */
  3992. if (tx_desc->pool_id != pool_id) {
  3993. QDF_TRACE(QDF_MODULE_ID_DP,
  3994. QDF_TRACE_LEVEL_FATAL,
  3995. "Tx Comp pool id %d not matched %d",
  3996. pool_id, tx_desc->pool_id);
  3997. qdf_assert_always(0);
  3998. }
  3999. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4000. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4001. QDF_TRACE(QDF_MODULE_ID_DP,
  4002. QDF_TRACE_LEVEL_FATAL,
  4003. "Txdesc invalid, flgs = %x,id = %d",
  4004. tx_desc->flags, tx_desc_id);
  4005. qdf_assert_always(0);
  4006. }
  4007. /* Collect hw completion contents */
  4008. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4009. &tx_desc->comp, 1);
  4010. add_to_pool:
  4011. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4012. /* First ring descriptor on the cycle */
  4013. if (!head_desc) {
  4014. head_desc = tx_desc;
  4015. tail_desc = tx_desc;
  4016. }
  4017. tail_desc->next = tx_desc;
  4018. tx_desc->next = NULL;
  4019. tail_desc = tx_desc;
  4020. }
  4021. next_desc:
  4022. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4023. /*
  4024. * Processed packet count is more than given quota
  4025. * stop to processing
  4026. */
  4027. count++;
  4028. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  4029. break;
  4030. }
  4031. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4032. /* Process the reaped descriptors */
  4033. if (head_desc)
  4034. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4035. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4036. if (num_processed >= quota)
  4037. force_break = true;
  4038. if (!force_break &&
  4039. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4040. hal_ring_hdl)) {
  4041. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4042. if (!hif_exec_should_yield(soc->hif_handle,
  4043. int_ctx->dp_intr_id))
  4044. goto more_data;
  4045. }
  4046. }
  4047. DP_TX_HIST_STATS_PER_PDEV();
  4048. return num_processed;
  4049. }
  4050. #ifdef FEATURE_WLAN_TDLS
  4051. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4052. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4053. {
  4054. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4055. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4056. DP_MOD_ID_TDLS);
  4057. if (!vdev) {
  4058. dp_err("vdev handle for id %d is NULL", vdev_id);
  4059. return NULL;
  4060. }
  4061. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4062. vdev->is_tdls_frame = true;
  4063. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4064. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4065. }
  4066. #endif
  4067. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4068. {
  4069. struct wlan_cfg_dp_soc_ctxt *cfg;
  4070. struct dp_soc *soc;
  4071. soc = vdev->pdev->soc;
  4072. if (!soc)
  4073. return;
  4074. cfg = soc->wlan_cfg_ctx;
  4075. if (!cfg)
  4076. return;
  4077. if (vdev->opmode == wlan_op_mode_ndi)
  4078. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4079. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4080. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4081. (vdev->subtype == wlan_op_subtype_p2p_go))
  4082. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4083. else
  4084. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4085. }
  4086. /**
  4087. * dp_tx_vdev_attach() - attach vdev to dp tx
  4088. * @vdev: virtual device instance
  4089. *
  4090. * Return: QDF_STATUS_SUCCESS: success
  4091. * QDF_STATUS_E_RESOURCES: Error return
  4092. */
  4093. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4094. {
  4095. int pdev_id;
  4096. /*
  4097. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4098. */
  4099. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4100. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4101. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4102. vdev->vdev_id);
  4103. pdev_id =
  4104. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4105. vdev->pdev->pdev_id);
  4106. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4107. /*
  4108. * Set HTT Extension Valid bit to 0 by default
  4109. */
  4110. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4111. dp_tx_vdev_update_search_flags(vdev);
  4112. dp_tx_vdev_update_feature_flags(vdev);
  4113. return QDF_STATUS_SUCCESS;
  4114. }
  4115. #ifndef FEATURE_WDS
  4116. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4117. {
  4118. return false;
  4119. }
  4120. #endif
  4121. /**
  4122. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4123. * @vdev: virtual device instance
  4124. *
  4125. * Return: void
  4126. *
  4127. */
  4128. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4129. {
  4130. struct dp_soc *soc = vdev->pdev->soc;
  4131. /*
  4132. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4133. * for TDLS link
  4134. *
  4135. * Enable AddrY (SA based search) only for non-WDS STA and
  4136. * ProxySTA VAP (in HKv1) modes.
  4137. *
  4138. * In all other VAP modes, only DA based search should be
  4139. * enabled
  4140. */
  4141. if (vdev->opmode == wlan_op_mode_sta &&
  4142. vdev->tdls_link_connected)
  4143. vdev->hal_desc_addr_search_flags =
  4144. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4145. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4146. !dp_tx_da_search_override(vdev))
  4147. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4148. else
  4149. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4150. /* Set search type only when peer map v2 messaging is enabled
  4151. * as we will have the search index (AST hash) only when v2 is
  4152. * enabled
  4153. */
  4154. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4155. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4156. else
  4157. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4158. }
  4159. static inline bool
  4160. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4161. struct dp_vdev *vdev,
  4162. struct dp_tx_desc_s *tx_desc)
  4163. {
  4164. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4165. return false;
  4166. /*
  4167. * if vdev is given, then only check whether desc
  4168. * vdev match. if vdev is NULL, then check whether
  4169. * desc pdev match.
  4170. */
  4171. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4172. (tx_desc->pdev == pdev);
  4173. }
  4174. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4175. /**
  4176. * dp_tx_desc_flush() - release resources associated
  4177. * to TX Desc
  4178. *
  4179. * @dp_pdev: Handle to DP pdev structure
  4180. * @vdev: virtual device instance
  4181. * NULL: no specific Vdev is required and check all allcated TX desc
  4182. * on this pdev.
  4183. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4184. *
  4185. * @force_free:
  4186. * true: flush the TX desc.
  4187. * false: only reset the Vdev in each allocated TX desc
  4188. * that associated to current Vdev.
  4189. *
  4190. * This function will go through the TX desc pool to flush
  4191. * the outstanding TX data or reset Vdev to NULL in associated TX
  4192. * Desc.
  4193. */
  4194. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4195. bool force_free)
  4196. {
  4197. uint8_t i;
  4198. uint32_t j;
  4199. uint32_t num_desc, page_id, offset;
  4200. uint16_t num_desc_per_page;
  4201. struct dp_soc *soc = pdev->soc;
  4202. struct dp_tx_desc_s *tx_desc = NULL;
  4203. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4204. if (!vdev && !force_free) {
  4205. dp_err("Reset TX desc vdev, Vdev param is required!");
  4206. return;
  4207. }
  4208. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4209. tx_desc_pool = &soc->tx_desc[i];
  4210. if (!(tx_desc_pool->pool_size) ||
  4211. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4212. !(tx_desc_pool->desc_pages.cacheable_pages))
  4213. continue;
  4214. /*
  4215. * Add flow pool lock protection in case pool is freed
  4216. * due to all tx_desc is recycled when handle TX completion.
  4217. * this is not necessary when do force flush as:
  4218. * a. double lock will happen if dp_tx_desc_release is
  4219. * also trying to acquire it.
  4220. * b. dp interrupt has been disabled before do force TX desc
  4221. * flush in dp_pdev_deinit().
  4222. */
  4223. if (!force_free)
  4224. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4225. num_desc = tx_desc_pool->pool_size;
  4226. num_desc_per_page =
  4227. tx_desc_pool->desc_pages.num_element_per_page;
  4228. for (j = 0; j < num_desc; j++) {
  4229. page_id = j / num_desc_per_page;
  4230. offset = j % num_desc_per_page;
  4231. if (qdf_unlikely(!(tx_desc_pool->
  4232. desc_pages.cacheable_pages)))
  4233. break;
  4234. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4235. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4236. /*
  4237. * Free TX desc if force free is
  4238. * required, otherwise only reset vdev
  4239. * in this TX desc.
  4240. */
  4241. if (force_free) {
  4242. dp_tx_comp_free_buf(soc, tx_desc);
  4243. dp_tx_desc_release(tx_desc, i);
  4244. } else {
  4245. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4246. }
  4247. }
  4248. }
  4249. if (!force_free)
  4250. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4251. }
  4252. }
  4253. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4254. /**
  4255. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4256. *
  4257. * @soc: Handle to DP soc structure
  4258. * @tx_desc: pointer of one TX desc
  4259. * @desc_pool_id: TX Desc pool id
  4260. */
  4261. static inline void
  4262. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4263. uint8_t desc_pool_id)
  4264. {
  4265. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4266. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4267. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4268. }
  4269. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4270. bool force_free)
  4271. {
  4272. uint8_t i, num_pool;
  4273. uint32_t j;
  4274. uint32_t num_desc, page_id, offset;
  4275. uint16_t num_desc_per_page;
  4276. struct dp_soc *soc = pdev->soc;
  4277. struct dp_tx_desc_s *tx_desc = NULL;
  4278. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4279. if (!vdev && !force_free) {
  4280. dp_err("Reset TX desc vdev, Vdev param is required!");
  4281. return;
  4282. }
  4283. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4284. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4285. for (i = 0; i < num_pool; i++) {
  4286. tx_desc_pool = &soc->tx_desc[i];
  4287. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4288. continue;
  4289. num_desc_per_page =
  4290. tx_desc_pool->desc_pages.num_element_per_page;
  4291. for (j = 0; j < num_desc; j++) {
  4292. page_id = j / num_desc_per_page;
  4293. offset = j % num_desc_per_page;
  4294. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4295. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4296. if (force_free) {
  4297. dp_tx_comp_free_buf(soc, tx_desc);
  4298. dp_tx_desc_release(tx_desc, i);
  4299. } else {
  4300. dp_tx_desc_reset_vdev(soc, tx_desc,
  4301. i);
  4302. }
  4303. }
  4304. }
  4305. }
  4306. }
  4307. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4308. /**
  4309. * dp_tx_vdev_detach() - detach vdev from dp tx
  4310. * @vdev: virtual device instance
  4311. *
  4312. * Return: QDF_STATUS_SUCCESS: success
  4313. * QDF_STATUS_E_RESOURCES: Error return
  4314. */
  4315. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4316. {
  4317. struct dp_pdev *pdev = vdev->pdev;
  4318. /* Reset TX desc associated to this Vdev as NULL */
  4319. dp_tx_desc_flush(pdev, vdev, false);
  4320. dp_tx_vdev_multipass_deinit(vdev);
  4321. return QDF_STATUS_SUCCESS;
  4322. }
  4323. /**
  4324. * dp_tx_pdev_attach() - attach pdev to dp tx
  4325. * @pdev: physical device instance
  4326. *
  4327. * Return: QDF_STATUS_SUCCESS: success
  4328. * QDF_STATUS_E_RESOURCES: Error return
  4329. */
  4330. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4331. {
  4332. struct dp_soc *soc = pdev->soc;
  4333. /* Initialize Flow control counters */
  4334. qdf_atomic_init(&pdev->num_tx_outstanding);
  4335. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4336. /* Initialize descriptors in TCL Ring */
  4337. hal_tx_init_data_ring(soc->hal_soc,
  4338. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4339. }
  4340. return QDF_STATUS_SUCCESS;
  4341. }
  4342. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4343. /* Pools will be allocated dynamically */
  4344. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4345. int num_desc)
  4346. {
  4347. uint8_t i;
  4348. for (i = 0; i < num_pool; i++) {
  4349. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4350. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4351. }
  4352. return QDF_STATUS_SUCCESS;
  4353. }
  4354. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4355. int num_desc)
  4356. {
  4357. return QDF_STATUS_SUCCESS;
  4358. }
  4359. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4360. {
  4361. }
  4362. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4363. {
  4364. uint8_t i;
  4365. for (i = 0; i < num_pool; i++)
  4366. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4367. }
  4368. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4369. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4370. int num_desc)
  4371. {
  4372. uint8_t i, count;
  4373. /* Allocate software Tx descriptor pools */
  4374. for (i = 0; i < num_pool; i++) {
  4375. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4377. FL("Tx Desc Pool alloc %d failed %pK"),
  4378. i, soc);
  4379. goto fail;
  4380. }
  4381. }
  4382. return QDF_STATUS_SUCCESS;
  4383. fail:
  4384. for (count = 0; count < i; count++)
  4385. dp_tx_desc_pool_free(soc, count);
  4386. return QDF_STATUS_E_NOMEM;
  4387. }
  4388. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4389. int num_desc)
  4390. {
  4391. uint8_t i;
  4392. for (i = 0; i < num_pool; i++) {
  4393. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4394. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4395. FL("Tx Desc Pool init %d failed %pK"),
  4396. i, soc);
  4397. return QDF_STATUS_E_NOMEM;
  4398. }
  4399. }
  4400. return QDF_STATUS_SUCCESS;
  4401. }
  4402. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4403. {
  4404. uint8_t i;
  4405. for (i = 0; i < num_pool; i++)
  4406. dp_tx_desc_pool_deinit(soc, i);
  4407. }
  4408. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4409. {
  4410. uint8_t i;
  4411. for (i = 0; i < num_pool; i++)
  4412. dp_tx_desc_pool_free(soc, i);
  4413. }
  4414. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4415. /**
  4416. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4417. * @soc: core txrx main context
  4418. * @num_pool: number of pools
  4419. *
  4420. */
  4421. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4422. {
  4423. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4424. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4425. }
  4426. /**
  4427. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4428. * @soc: core txrx main context
  4429. * @num_pool: number of pools
  4430. *
  4431. */
  4432. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4433. {
  4434. dp_tx_tso_desc_pool_free(soc, num_pool);
  4435. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4436. }
  4437. /**
  4438. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4439. * @soc: core txrx main context
  4440. *
  4441. * This function frees all tx related descriptors as below
  4442. * 1. Regular TX descriptors (static pools)
  4443. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4444. * 3. TSO descriptors
  4445. *
  4446. */
  4447. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4448. {
  4449. uint8_t num_pool;
  4450. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4451. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4452. dp_tx_ext_desc_pool_free(soc, num_pool);
  4453. dp_tx_delete_static_pools(soc, num_pool);
  4454. }
  4455. /**
  4456. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4457. * @soc: core txrx main context
  4458. *
  4459. * This function de-initializes all tx related descriptors as below
  4460. * 1. Regular TX descriptors (static pools)
  4461. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4462. * 3. TSO descriptors
  4463. *
  4464. */
  4465. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4466. {
  4467. uint8_t num_pool;
  4468. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4469. dp_tx_flow_control_deinit(soc);
  4470. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4471. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4472. dp_tx_deinit_static_pools(soc, num_pool);
  4473. }
  4474. /**
  4475. * dp_tso_attach() - TSO attach handler
  4476. * @txrx_soc: Opaque Dp handle
  4477. *
  4478. * Reserve TSO descriptor buffers
  4479. *
  4480. * Return: QDF_STATUS_E_FAILURE on failure or
  4481. * QDF_STATUS_SUCCESS on success
  4482. */
  4483. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4484. uint8_t num_pool,
  4485. uint16_t num_desc)
  4486. {
  4487. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4488. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4489. return QDF_STATUS_E_FAILURE;
  4490. }
  4491. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4492. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4493. num_pool, soc);
  4494. return QDF_STATUS_E_FAILURE;
  4495. }
  4496. return QDF_STATUS_SUCCESS;
  4497. }
  4498. /**
  4499. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4500. * @soc: DP soc handle
  4501. * @num_pool: Number of pools
  4502. * @num_desc: Number of descriptors
  4503. *
  4504. * Initialize TSO descriptor pools
  4505. *
  4506. * Return: QDF_STATUS_E_FAILURE on failure or
  4507. * QDF_STATUS_SUCCESS on success
  4508. */
  4509. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4510. uint8_t num_pool,
  4511. uint16_t num_desc)
  4512. {
  4513. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4514. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4515. return QDF_STATUS_E_FAILURE;
  4516. }
  4517. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4518. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4519. num_pool, soc);
  4520. return QDF_STATUS_E_FAILURE;
  4521. }
  4522. return QDF_STATUS_SUCCESS;
  4523. }
  4524. /**
  4525. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4526. * @soc: core txrx main context
  4527. *
  4528. * This function allocates memory for following descriptor pools
  4529. * 1. regular sw tx descriptor pools (static pools)
  4530. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4531. * 3. TSO descriptor pools
  4532. *
  4533. * Return: QDF_STATUS_SUCCESS: success
  4534. * QDF_STATUS_E_RESOURCES: Error return
  4535. */
  4536. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4537. {
  4538. uint8_t num_pool;
  4539. uint32_t num_desc;
  4540. uint32_t num_ext_desc;
  4541. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4542. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4543. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4545. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4546. __func__, num_pool, num_desc);
  4547. if ((num_pool > MAX_TXDESC_POOLS) ||
  4548. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4549. goto fail1;
  4550. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4551. goto fail1;
  4552. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4553. goto fail2;
  4554. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4555. return QDF_STATUS_SUCCESS;
  4556. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4557. goto fail3;
  4558. return QDF_STATUS_SUCCESS;
  4559. fail3:
  4560. dp_tx_ext_desc_pool_free(soc, num_pool);
  4561. fail2:
  4562. dp_tx_delete_static_pools(soc, num_pool);
  4563. fail1:
  4564. return QDF_STATUS_E_RESOURCES;
  4565. }
  4566. /**
  4567. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4568. * @soc: core txrx main context
  4569. *
  4570. * This function initializes the following TX descriptor pools
  4571. * 1. regular sw tx descriptor pools (static pools)
  4572. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4573. * 3. TSO descriptor pools
  4574. *
  4575. * Return: QDF_STATUS_SUCCESS: success
  4576. * QDF_STATUS_E_RESOURCES: Error return
  4577. */
  4578. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4579. {
  4580. uint8_t num_pool;
  4581. uint32_t num_desc;
  4582. uint32_t num_ext_desc;
  4583. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4584. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4585. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4586. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4587. goto fail1;
  4588. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4589. goto fail2;
  4590. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4591. return QDF_STATUS_SUCCESS;
  4592. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4593. goto fail3;
  4594. dp_tx_flow_control_init(soc);
  4595. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4596. return QDF_STATUS_SUCCESS;
  4597. fail3:
  4598. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4599. fail2:
  4600. dp_tx_deinit_static_pools(soc, num_pool);
  4601. fail1:
  4602. return QDF_STATUS_E_RESOURCES;
  4603. }
  4604. /**
  4605. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4606. * @txrx_soc: dp soc handle
  4607. *
  4608. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4609. * QDF_STATUS_E_FAILURE
  4610. */
  4611. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4612. {
  4613. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4614. uint8_t num_pool;
  4615. uint32_t num_desc;
  4616. uint32_t num_ext_desc;
  4617. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4618. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4619. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4620. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4621. return QDF_STATUS_E_FAILURE;
  4622. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4623. return QDF_STATUS_E_FAILURE;
  4624. return QDF_STATUS_SUCCESS;
  4625. }
  4626. /**
  4627. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4628. * @txrx_soc: dp soc handle
  4629. *
  4630. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4631. */
  4632. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4633. {
  4634. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4635. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4636. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4637. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4638. return QDF_STATUS_SUCCESS;
  4639. }