sde_rm.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s] " fmt, __func__
  6. #include "sde_kms.h"
  7. #include "sde_hw_lm.h"
  8. #include "sde_hw_ctl.h"
  9. #include "sde_hw_cdm.h"
  10. #include "sde_hw_dspp.h"
  11. #include "sde_hw_ds.h"
  12. #include "sde_hw_pingpong.h"
  13. #include "sde_hw_intf.h"
  14. #include "sde_hw_wb.h"
  15. #include "sde_encoder.h"
  16. #include "sde_connector.h"
  17. #include "sde_hw_dsc.h"
  18. #include "sde_hw_vdc.h"
  19. #include "sde_crtc.h"
  20. #include "sde_hw_qdss.h"
  21. #define RESERVED_BY_OTHER(h, r) \
  22. (((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
  23. ((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
  24. #define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
  25. #define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
  26. #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
  27. #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
  28. #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
  29. #define RM_RQ_DCWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DCWB))
  30. #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
  31. (t).num_comp_enc == (r).num_enc && \
  32. (t).num_intf == (r).num_intf && \
  33. (t).comp_type == (r).comp_type)
  34. #define IS_COMPATIBLE_PP_DSC(p, d) (p % 2 == d % 2)
  35. /* ~one vsync poll time for rsvp_nxt to cleared by modeset from commit thread */
  36. #define RM_NXT_CLEAR_POLL_TIMEOUT_US 16600
  37. /**
  38. * toplogy information to be used when ctl path version does not
  39. * support driving more than one interface per ctl_path
  40. */
  41. static const struct sde_rm_topology_def g_top_table[SDE_RM_TOPOLOGY_MAX] = {
  42. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  43. MSM_DISPLAY_COMPRESSION_NONE },
  44. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  45. MSM_DISPLAY_COMPRESSION_NONE },
  46. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  47. MSM_DISPLAY_COMPRESSION_DSC },
  48. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true,
  49. MSM_DISPLAY_COMPRESSION_NONE },
  50. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true,
  51. MSM_DISPLAY_COMPRESSION_DSC },
  52. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  53. MSM_DISPLAY_COMPRESSION_NONE },
  54. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  55. MSM_DISPLAY_COMPRESSION_DSC },
  56. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  57. MSM_DISPLAY_COMPRESSION_DSC },
  58. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  59. MSM_DISPLAY_COMPRESSION_NONE },
  60. };
  61. /**
  62. * topology information to be used when the ctl path version
  63. * is SDE_CTL_CFG_VERSION_1_0_0
  64. */
  65. static const struct sde_rm_topology_def g_top_table_v1[SDE_RM_TOPOLOGY_MAX] = {
  66. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  67. MSM_DISPLAY_COMPRESSION_NONE },
  68. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  69. MSM_DISPLAY_COMPRESSION_NONE },
  70. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  71. MSM_DISPLAY_COMPRESSION_DSC },
  72. { SDE_RM_TOPOLOGY_SINGLEPIPE_VDC, 1, 1, 1, 1, false,
  73. MSM_DISPLAY_COMPRESSION_VDC },
  74. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 1, false,
  75. MSM_DISPLAY_COMPRESSION_NONE },
  76. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 1, false,
  77. MSM_DISPLAY_COMPRESSION_DSC },
  78. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  79. MSM_DISPLAY_COMPRESSION_NONE },
  80. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  81. MSM_DISPLAY_COMPRESSION_DSC },
  82. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC, 2, 1, 1, 1, false,
  83. MSM_DISPLAY_COMPRESSION_VDC },
  84. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  85. MSM_DISPLAY_COMPRESSION_DSC },
  86. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, false,
  87. MSM_DISPLAY_COMPRESSION_NONE },
  88. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE, 4, 0, 2, 1, false,
  89. MSM_DISPLAY_COMPRESSION_NONE },
  90. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE_DSC, 4, 3, 2, 1, false,
  91. MSM_DISPLAY_COMPRESSION_DSC },
  92. { SDE_RM_TOPOLOGY_QUADPIPE_DSCMERGE, 4, 4, 2, 1, false,
  93. MSM_DISPLAY_COMPRESSION_DSC },
  94. { SDE_RM_TOPOLOGY_QUADPIPE_DSC4HSMERGE, 4, 4, 1, 1, false,
  95. MSM_DISPLAY_COMPRESSION_DSC },
  96. };
  97. char sde_hw_blk_str[SDE_HW_BLK_MAX][SDE_HW_BLK_NAME_LEN] = {
  98. "top",
  99. "sspp",
  100. "lm",
  101. "dspp",
  102. "ds",
  103. "ctl",
  104. "cdm",
  105. "pingpong",
  106. "intf",
  107. "wb",
  108. "dsc",
  109. "vdc",
  110. "merge_3d",
  111. "qdss",
  112. };
  113. /**
  114. * struct sde_rm_requirements - Reservation requirements parameter bundle
  115. * @top_ctrl: topology control preference from kernel client
  116. * @top: selected topology for the display
  117. * @hw_res: Hardware resources required as reported by the encoders
  118. */
  119. struct sde_rm_requirements {
  120. uint64_t top_ctrl;
  121. const struct sde_rm_topology_def *topology;
  122. struct sde_encoder_hw_resources hw_res;
  123. };
  124. /**
  125. * struct sde_rm_rsvp - Use Case Reservation tagging structure
  126. * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
  127. * By using as a tag, rather than lists of pointers to HW blocks used
  128. * we can avoid some list management since we don't know how many blocks
  129. * of each type a given use case may require.
  130. * @list: List head for list of all reservations
  131. * @seq: Global RSVP sequence number for debugging, especially for
  132. * differentiating differenct allocations for same encoder.
  133. * @enc_id: Reservations are tracked by Encoder DRM object ID.
  134. * CRTCs may be connected to multiple Encoders.
  135. * An encoder or connector id identifies the display path.
  136. * @topology DRM<->HW topology use case
  137. */
  138. struct sde_rm_rsvp {
  139. struct list_head list;
  140. uint32_t seq;
  141. uint32_t enc_id;
  142. enum sde_rm_topology_name topology;
  143. };
  144. /**
  145. * struct sde_rm_hw_blk - hardware block tracking list member
  146. * @list: List head for list of all hardware blocks tracking items
  147. * @rsvp: Pointer to use case reservation if reserved by a client
  148. * @rsvp_nxt: Temporary pointer used during reservation to the incoming
  149. * request. Will be swapped into rsvp if proposal is accepted
  150. * @type: Type of hardware block this structure tracks
  151. * @id: Hardware ID number, within it's own space, ie. LM_X
  152. * @catalog: Pointer to the hardware catalog entry for this block
  153. * @hw: Pointer to the hardware register access object for this block
  154. */
  155. struct sde_rm_hw_blk {
  156. struct list_head list;
  157. struct sde_rm_rsvp *rsvp;
  158. struct sde_rm_rsvp *rsvp_nxt;
  159. enum sde_hw_blk_type type;
  160. uint32_t id;
  161. struct sde_hw_blk *hw;
  162. };
  163. /**
  164. * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
  165. */
  166. enum sde_rm_dbg_rsvp_stage {
  167. SDE_RM_STAGE_BEGIN,
  168. SDE_RM_STAGE_AFTER_CLEAR,
  169. SDE_RM_STAGE_AFTER_RSVPNEXT,
  170. SDE_RM_STAGE_FINAL
  171. };
  172. static void _sde_rm_inc_resource_info_lm(struct sde_rm *rm,
  173. struct msm_resource_caps_info *avail_res,
  174. struct sde_rm_hw_blk *blk)
  175. {
  176. struct sde_rm_hw_blk *blk2;
  177. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  178. avail_res->num_lm++;
  179. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  180. /* Check for 3d muxes by comparing paired lms */
  181. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  182. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  183. /*
  184. * If lm2 is free, or
  185. * lm1 & lm2 reserved by same enc, check mask
  186. */
  187. if ((!blk2->rsvp || (blk->rsvp &&
  188. blk2->rsvp->enc_id == blk->rsvp->enc_id
  189. && lm_cfg->id > lm_cfg2->id)) &&
  190. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  191. avail_res->num_3dmux++;
  192. }
  193. }
  194. static void _sde_rm_dec_resource_info_lm(struct sde_rm *rm,
  195. struct msm_resource_caps_info *avail_res,
  196. struct sde_rm_hw_blk *blk)
  197. {
  198. struct sde_rm_hw_blk *blk2;
  199. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  200. avail_res->num_lm--;
  201. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  202. /* Check for 3d muxes by comparing paired lms */
  203. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  204. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  205. /* If lm2 is free and lm1 is now being reserved */
  206. if (!blk2->rsvp &&
  207. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  208. avail_res->num_3dmux--;
  209. }
  210. }
  211. static void _sde_rm_inc_resource_info(struct sde_rm *rm,
  212. struct msm_resource_caps_info *avail_res,
  213. struct sde_rm_hw_blk *blk)
  214. {
  215. enum sde_hw_blk_type type = blk->type;
  216. if (type == SDE_HW_BLK_LM)
  217. _sde_rm_inc_resource_info_lm(rm, avail_res, blk);
  218. else if (type == SDE_HW_BLK_CTL)
  219. avail_res->num_ctl++;
  220. else if (type == SDE_HW_BLK_DSC)
  221. avail_res->num_dsc++;
  222. else if (type == SDE_HW_BLK_VDC)
  223. avail_res->num_vdc++;
  224. }
  225. static void _sde_rm_dec_resource_info(struct sde_rm *rm,
  226. struct msm_resource_caps_info *avail_res,
  227. struct sde_rm_hw_blk *blk)
  228. {
  229. enum sde_hw_blk_type type = blk->type;
  230. if (type == SDE_HW_BLK_LM)
  231. _sde_rm_dec_resource_info_lm(rm, avail_res, blk);
  232. else if (type == SDE_HW_BLK_CTL)
  233. avail_res->num_ctl--;
  234. else if (type == SDE_HW_BLK_DSC)
  235. avail_res->num_dsc--;
  236. else if (type == SDE_HW_BLK_VDC)
  237. avail_res->num_vdc--;
  238. }
  239. void sde_rm_get_resource_info(struct sde_rm *rm,
  240. struct drm_encoder *drm_enc,
  241. struct msm_resource_caps_info *avail_res)
  242. {
  243. struct sde_rm_hw_blk *blk;
  244. enum sde_hw_blk_type type;
  245. struct sde_rm_rsvp rsvp;
  246. memcpy(avail_res, &rm->avail_res,
  247. sizeof(rm->avail_res));
  248. if (!drm_enc)
  249. return;
  250. rsvp.enc_id = drm_enc->base.id;
  251. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  252. list_for_each_entry(blk, &rm->hw_blks[type], list)
  253. if (blk->rsvp && blk->rsvp->enc_id == rsvp.enc_id)
  254. _sde_rm_inc_resource_info(rm, avail_res, blk);
  255. }
  256. static void _sde_rm_print_rsvps(
  257. struct sde_rm *rm,
  258. enum sde_rm_dbg_rsvp_stage stage)
  259. {
  260. struct sde_rm_rsvp *rsvp;
  261. struct sde_rm_hw_blk *blk;
  262. enum sde_hw_blk_type type;
  263. SDE_DEBUG("%d\n", stage);
  264. list_for_each_entry(rsvp, &rm->rsvps, list) {
  265. SDE_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
  266. rsvp->enc_id, rsvp->topology);
  267. SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
  268. }
  269. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  270. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  271. if (!blk->rsvp && !blk->rsvp_nxt)
  272. continue;
  273. SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
  274. (blk->rsvp) ? blk->rsvp->seq : 0,
  275. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  276. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  277. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  278. blk->type, blk->id);
  279. SDE_EVT32(stage,
  280. (blk->rsvp) ? blk->rsvp->seq : 0,
  281. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  282. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  283. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  284. blk->type, blk->id);
  285. }
  286. }
  287. }
  288. static void _sde_rm_print_rsvps_by_type(
  289. struct sde_rm *rm,
  290. enum sde_hw_blk_type type)
  291. {
  292. struct sde_rm_hw_blk *blk;
  293. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  294. if (!blk->rsvp && !blk->rsvp_nxt)
  295. continue;
  296. SDE_ERROR("rsvp[s%ue%u->s%ue%u] %d %d\n",
  297. (blk->rsvp) ? blk->rsvp->seq : 0,
  298. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  299. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  300. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  301. blk->type, blk->id);
  302. SDE_EVT32((blk->rsvp) ? blk->rsvp->seq : 0,
  303. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  304. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  305. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  306. blk->type, blk->id);
  307. }
  308. }
  309. struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
  310. {
  311. return rm->hw_mdp;
  312. }
  313. void sde_rm_init_hw_iter(
  314. struct sde_rm_hw_iter *iter,
  315. uint32_t enc_id,
  316. enum sde_hw_blk_type type)
  317. {
  318. memset(iter, 0, sizeof(*iter));
  319. iter->enc_id = enc_id;
  320. iter->type = type;
  321. }
  322. enum sde_rm_topology_name sde_rm_get_topology_name(struct sde_rm *rm,
  323. struct msm_display_topology topology)
  324. {
  325. int i;
  326. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  327. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  328. topology))
  329. return rm->topology_tbl[i].top_name;
  330. return SDE_RM_TOPOLOGY_NONE;
  331. }
  332. static bool _sde_rm_get_hw_locked(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  333. {
  334. struct list_head *blk_list;
  335. if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
  336. SDE_ERROR("invalid rm\n");
  337. return false;
  338. }
  339. i->hw = NULL;
  340. blk_list = &rm->hw_blks[i->type];
  341. if (i->blk && (&i->blk->list == blk_list)) {
  342. SDE_DEBUG("attempt resume iteration past last\n");
  343. return false;
  344. }
  345. i->blk = list_prepare_entry(i->blk, blk_list, list);
  346. list_for_each_entry_continue(i->blk, blk_list, list) {
  347. struct sde_rm_rsvp *rsvp = i->blk->rsvp;
  348. if (i->blk->type != i->type) {
  349. SDE_ERROR("found incorrect block type %d on %d list\n",
  350. i->blk->type, i->type);
  351. return false;
  352. }
  353. if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
  354. i->hw = i->blk->hw;
  355. SDE_DEBUG("found type %d id %d for enc %d\n",
  356. i->type, i->blk->id, i->enc_id);
  357. return true;
  358. }
  359. }
  360. SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
  361. return false;
  362. }
  363. static bool _sde_rm_request_hw_blk_locked(struct sde_rm *rm,
  364. struct sde_rm_hw_request *hw_blk_info)
  365. {
  366. struct list_head *blk_list;
  367. struct sde_rm_hw_blk *blk = NULL;
  368. if (!rm || !hw_blk_info || hw_blk_info->type >= SDE_HW_BLK_MAX) {
  369. SDE_ERROR("invalid rm\n");
  370. return false;
  371. }
  372. hw_blk_info->hw = NULL;
  373. blk_list = &rm->hw_blks[hw_blk_info->type];
  374. blk = list_prepare_entry(blk, blk_list, list);
  375. list_for_each_entry_continue(blk, blk_list, list) {
  376. if (blk->type != hw_blk_info->type) {
  377. SDE_ERROR("found incorrect block type %d on %d list\n",
  378. blk->type, hw_blk_info->type);
  379. return false;
  380. }
  381. if (blk->hw->id == hw_blk_info->id) {
  382. hw_blk_info->hw = blk->hw;
  383. SDE_DEBUG("found type %d id %d\n",
  384. blk->type, blk->id);
  385. return true;
  386. }
  387. }
  388. SDE_DEBUG("no match, type %d id %d\n", hw_blk_info->type,
  389. hw_blk_info->id);
  390. return false;
  391. }
  392. bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  393. {
  394. bool ret;
  395. mutex_lock(&rm->rm_lock);
  396. ret = _sde_rm_get_hw_locked(rm, i);
  397. mutex_unlock(&rm->rm_lock);
  398. return ret;
  399. }
  400. bool sde_rm_request_hw_blk(struct sde_rm *rm, struct sde_rm_hw_request *hw)
  401. {
  402. bool ret;
  403. mutex_lock(&rm->rm_lock);
  404. ret = _sde_rm_request_hw_blk_locked(rm, hw);
  405. mutex_unlock(&rm->rm_lock);
  406. return ret;
  407. }
  408. static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, void *hw)
  409. {
  410. switch (type) {
  411. case SDE_HW_BLK_LM:
  412. sde_hw_lm_destroy(hw);
  413. break;
  414. case SDE_HW_BLK_DSPP:
  415. sde_hw_dspp_destroy(hw);
  416. break;
  417. case SDE_HW_BLK_DS:
  418. sde_hw_ds_destroy(hw);
  419. break;
  420. case SDE_HW_BLK_CTL:
  421. sde_hw_ctl_destroy(hw);
  422. break;
  423. case SDE_HW_BLK_CDM:
  424. sde_hw_cdm_destroy(hw);
  425. break;
  426. case SDE_HW_BLK_PINGPONG:
  427. sde_hw_pingpong_destroy(hw);
  428. break;
  429. case SDE_HW_BLK_INTF:
  430. sde_hw_intf_destroy(hw);
  431. break;
  432. case SDE_HW_BLK_WB:
  433. sde_hw_wb_destroy(hw);
  434. break;
  435. case SDE_HW_BLK_DSC:
  436. sde_hw_dsc_destroy(hw);
  437. break;
  438. case SDE_HW_BLK_VDC:
  439. sde_hw_vdc_destroy(hw);
  440. break;
  441. case SDE_HW_BLK_QDSS:
  442. sde_hw_qdss_destroy(hw);
  443. break;
  444. case SDE_HW_BLK_SSPP:
  445. /* SSPPs are not managed by the resource manager */
  446. case SDE_HW_BLK_TOP:
  447. /* Top is a singleton, not managed in hw_blks list */
  448. case SDE_HW_BLK_MAX:
  449. default:
  450. SDE_ERROR("unsupported block type %d\n", type);
  451. break;
  452. }
  453. }
  454. int sde_rm_destroy(struct sde_rm *rm)
  455. {
  456. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  457. struct sde_rm_hw_blk *hw_cur, *hw_nxt;
  458. enum sde_hw_blk_type type;
  459. if (!rm) {
  460. SDE_ERROR("invalid rm\n");
  461. return -EINVAL;
  462. }
  463. list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
  464. list_del(&rsvp_cur->list);
  465. kfree(rsvp_cur);
  466. }
  467. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  468. list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
  469. list) {
  470. list_del(&hw_cur->list);
  471. _sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
  472. kfree(hw_cur);
  473. }
  474. }
  475. sde_hw_mdp_destroy(rm->hw_mdp);
  476. rm->hw_mdp = NULL;
  477. mutex_destroy(&rm->rm_lock);
  478. return 0;
  479. }
  480. static int _sde_rm_hw_blk_create(
  481. struct sde_rm *rm,
  482. struct sde_mdss_cfg *cat,
  483. void __iomem *mmio,
  484. enum sde_hw_blk_type type,
  485. uint32_t id,
  486. void *hw_catalog_info)
  487. {
  488. struct sde_rm_hw_blk *blk;
  489. struct sde_hw_mdp *hw_mdp;
  490. void *hw;
  491. hw_mdp = rm->hw_mdp;
  492. switch (type) {
  493. case SDE_HW_BLK_LM:
  494. hw = sde_hw_lm_init(id, mmio, cat);
  495. break;
  496. case SDE_HW_BLK_DSPP:
  497. hw = sde_hw_dspp_init(id, mmio, cat);
  498. break;
  499. case SDE_HW_BLK_DS:
  500. hw = sde_hw_ds_init(id, mmio, cat);
  501. break;
  502. case SDE_HW_BLK_CTL:
  503. hw = sde_hw_ctl_init(id, mmio, cat);
  504. break;
  505. case SDE_HW_BLK_CDM:
  506. hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
  507. break;
  508. case SDE_HW_BLK_PINGPONG:
  509. hw = sde_hw_pingpong_init(id, mmio, cat);
  510. break;
  511. case SDE_HW_BLK_INTF:
  512. hw = sde_hw_intf_init(id, mmio, cat);
  513. break;
  514. case SDE_HW_BLK_WB:
  515. hw = sde_hw_wb_init(id, mmio, cat, hw_mdp);
  516. break;
  517. case SDE_HW_BLK_DSC:
  518. hw = sde_hw_dsc_init(id, mmio, cat);
  519. break;
  520. case SDE_HW_BLK_VDC:
  521. hw = sde_hw_vdc_init(id, mmio, cat);
  522. break;
  523. case SDE_HW_BLK_QDSS:
  524. hw = sde_hw_qdss_init(id, mmio, cat);
  525. break;
  526. case SDE_HW_BLK_SSPP:
  527. /* SSPPs are not managed by the resource manager */
  528. case SDE_HW_BLK_TOP:
  529. /* Top is a singleton, not managed in hw_blks list */
  530. case SDE_HW_BLK_MAX:
  531. default:
  532. SDE_ERROR("unsupported block type %d\n", type);
  533. return -EINVAL;
  534. }
  535. if (IS_ERR_OR_NULL(hw)) {
  536. SDE_ERROR("failed hw object creation: type %d, err %ld\n",
  537. type, PTR_ERR(hw));
  538. return -EFAULT;
  539. }
  540. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  541. if (!blk) {
  542. _sde_rm_hw_destroy(type, hw);
  543. return -ENOMEM;
  544. }
  545. blk->type = type;
  546. blk->id = id;
  547. blk->hw = hw;
  548. list_add_tail(&blk->list, &rm->hw_blks[type]);
  549. _sde_rm_inc_resource_info(rm, &rm->avail_res, blk);
  550. return 0;
  551. }
  552. static int _sde_rm_hw_blk_create_new(struct sde_rm *rm,
  553. struct sde_mdss_cfg *cat,
  554. void __iomem *mmio)
  555. {
  556. int i, rc = 0;
  557. for (i = 0; i < cat->dspp_count; i++) {
  558. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
  559. cat->dspp[i].id, &cat->dspp[i]);
  560. if (rc) {
  561. SDE_ERROR("failed: dspp hw not available\n");
  562. goto fail;
  563. }
  564. }
  565. if (cat->mdp[0].has_dest_scaler) {
  566. for (i = 0; i < cat->ds_count; i++) {
  567. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DS,
  568. cat->ds[i].id, &cat->ds[i]);
  569. if (rc) {
  570. SDE_ERROR("failed: ds hw not available\n");
  571. goto fail;
  572. }
  573. }
  574. }
  575. for (i = 0; i < cat->pingpong_count; i++) {
  576. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
  577. cat->pingpong[i].id, &cat->pingpong[i]);
  578. if (rc) {
  579. SDE_ERROR("failed: pp hw not available\n");
  580. goto fail;
  581. }
  582. }
  583. for (i = 0; i < cat->dsc_count; i++) {
  584. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSC,
  585. cat->dsc[i].id, &cat->dsc[i]);
  586. if (rc) {
  587. SDE_ERROR("failed: dsc hw not available\n");
  588. goto fail;
  589. }
  590. }
  591. for (i = 0; i < cat->vdc_count; i++) {
  592. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_VDC,
  593. cat->vdc[i].id, &cat->vdc[i]);
  594. if (rc) {
  595. SDE_ERROR("failed: vdc hw not available\n");
  596. goto fail;
  597. }
  598. }
  599. for (i = 0; i < cat->intf_count; i++) {
  600. if (cat->intf[i].type == INTF_NONE) {
  601. SDE_DEBUG("skip intf %d with type none\n", i);
  602. continue;
  603. }
  604. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
  605. cat->intf[i].id, &cat->intf[i]);
  606. if (rc) {
  607. SDE_ERROR("failed: intf hw not available\n");
  608. goto fail;
  609. }
  610. }
  611. for (i = 0; i < cat->wb_count; i++) {
  612. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
  613. cat->wb[i].id, &cat->wb[i]);
  614. if (rc) {
  615. SDE_ERROR("failed: wb hw not available\n");
  616. goto fail;
  617. }
  618. }
  619. for (i = 0; i < cat->ctl_count; i++) {
  620. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
  621. cat->ctl[i].id, &cat->ctl[i]);
  622. if (rc) {
  623. SDE_ERROR("failed: ctl hw not available\n");
  624. goto fail;
  625. }
  626. }
  627. for (i = 0; i < cat->cdm_count; i++) {
  628. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
  629. cat->cdm[i].id, &cat->cdm[i]);
  630. if (rc) {
  631. SDE_ERROR("failed: cdm hw not available\n");
  632. goto fail;
  633. }
  634. }
  635. for (i = 0; i < cat->qdss_count; i++) {
  636. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_QDSS,
  637. cat->qdss[i].id, &cat->qdss[i]);
  638. if (rc) {
  639. SDE_ERROR("failed: qdss hw not available\n");
  640. goto fail;
  641. }
  642. }
  643. fail:
  644. return rc;
  645. }
  646. #ifdef CONFIG_DEBUG_FS
  647. static int _sde_rm_status_show(struct seq_file *s, void *data)
  648. {
  649. struct sde_rm *rm;
  650. struct sde_rm_hw_blk *blk;
  651. u32 type, allocated, unallocated;
  652. if (!s || !s->private)
  653. return -EINVAL;
  654. rm = s->private;
  655. for (type = SDE_HW_BLK_LM; type < SDE_HW_BLK_MAX; type++) {
  656. allocated = 0;
  657. unallocated = 0;
  658. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  659. if (!blk->rsvp && !blk->rsvp_nxt)
  660. unallocated++;
  661. else
  662. allocated++;
  663. }
  664. seq_printf(s, "type:%d blk:%s allocated:%d unallocated:%d\n",
  665. type, sde_hw_blk_str[type], allocated, unallocated);
  666. }
  667. return 0;
  668. }
  669. static int _sde_rm_debugfs_status_open(struct inode *inode,
  670. struct file *file)
  671. {
  672. return single_open(file, _sde_rm_status_show, inode->i_private);
  673. }
  674. void sde_rm_debugfs_init(struct sde_rm *sde_rm, struct dentry *parent)
  675. {
  676. static const struct file_operations debugfs_rm_status_fops = {
  677. .open = _sde_rm_debugfs_status_open,
  678. .read = seq_read,
  679. };
  680. debugfs_create_file("rm_status", 0400, parent, sde_rm, &debugfs_rm_status_fops);
  681. }
  682. #else
  683. void sde_rm_debugfs_init(struct sde_rm *rm, struct dentry *parent)
  684. {
  685. }
  686. #endif
  687. int sde_rm_init(struct sde_rm *rm,
  688. struct sde_mdss_cfg *cat,
  689. void __iomem *mmio,
  690. struct drm_device *dev)
  691. {
  692. int i, rc = 0;
  693. enum sde_hw_blk_type type;
  694. if (!rm || !cat || !mmio || !dev) {
  695. SDE_ERROR("invalid input params\n");
  696. return -EINVAL;
  697. }
  698. /* Clear, setup lists */
  699. memset(rm, 0, sizeof(*rm));
  700. mutex_init(&rm->rm_lock);
  701. INIT_LIST_HEAD(&rm->rsvps);
  702. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  703. INIT_LIST_HEAD(&rm->hw_blks[type]);
  704. rm->dev = dev;
  705. if (IS_SDE_CTL_REV_100(cat->ctl_rev))
  706. rm->topology_tbl = g_top_table_v1;
  707. else
  708. rm->topology_tbl = g_top_table;
  709. /* Some of the sub-blocks require an mdptop to be created */
  710. rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
  711. if (IS_ERR_OR_NULL(rm->hw_mdp)) {
  712. rc = PTR_ERR(rm->hw_mdp);
  713. rm->hw_mdp = NULL;
  714. SDE_ERROR("failed: mdp hw not available\n");
  715. goto fail;
  716. }
  717. /* Interrogate HW catalog and create tracking items for hw blocks */
  718. for (i = 0; i < cat->mixer_count; i++) {
  719. struct sde_lm_cfg *lm = &cat->mixer[i];
  720. if (lm->pingpong == PINGPONG_MAX) {
  721. SDE_ERROR("mixer %d without pingpong\n", lm->id);
  722. goto fail;
  723. }
  724. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
  725. cat->mixer[i].id, &cat->mixer[i]);
  726. if (rc) {
  727. SDE_ERROR("failed: lm hw not available\n");
  728. goto fail;
  729. }
  730. if (!rm->lm_max_width) {
  731. rm->lm_max_width = lm->sblk->maxwidth;
  732. } else if (rm->lm_max_width != lm->sblk->maxwidth) {
  733. /*
  734. * Don't expect to have hw where lm max widths differ.
  735. * If found, take the min.
  736. */
  737. SDE_ERROR("unsupported: lm maxwidth differs\n");
  738. if (rm->lm_max_width > lm->sblk->maxwidth)
  739. rm->lm_max_width = lm->sblk->maxwidth;
  740. }
  741. }
  742. rc = _sde_rm_hw_blk_create_new(rm, cat, mmio);
  743. if (!rc)
  744. return 0;
  745. fail:
  746. sde_rm_destroy(rm);
  747. return rc;
  748. }
  749. static bool _sde_rm_check_lm(
  750. struct sde_rm *rm,
  751. struct sde_rm_rsvp *rsvp,
  752. struct sde_rm_requirements *reqs,
  753. const struct sde_lm_cfg *lm_cfg,
  754. struct sde_rm_hw_blk *lm,
  755. struct sde_rm_hw_blk **dspp,
  756. struct sde_rm_hw_blk **ds,
  757. struct sde_rm_hw_blk **pp)
  758. {
  759. bool is_valid_dspp, is_valid_ds, ret = true;
  760. is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
  761. is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
  762. /**
  763. * RM_RQ_X: specification of which LMs to choose
  764. * is_valid_X: indicates whether LM is tied with block X
  765. * ret: true if given LM matches the user requirement,
  766. * false otherwise
  767. */
  768. if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
  769. ret = (is_valid_dspp && is_valid_ds);
  770. else if (RM_RQ_DSPP(reqs))
  771. ret = is_valid_dspp;
  772. else if (RM_RQ_DS(reqs))
  773. ret = is_valid_ds;
  774. if (!ret) {
  775. SDE_DEBUG(
  776. "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
  777. lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
  778. lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
  779. lm_cfg->ds);
  780. return ret;
  781. }
  782. return true;
  783. }
  784. static bool _sde_rm_reserve_dspp(
  785. struct sde_rm *rm,
  786. struct sde_rm_rsvp *rsvp,
  787. const struct sde_lm_cfg *lm_cfg,
  788. struct sde_rm_hw_blk *lm,
  789. struct sde_rm_hw_blk **dspp)
  790. {
  791. struct sde_rm_hw_iter iter;
  792. if (lm_cfg->dspp != DSPP_MAX) {
  793. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
  794. while (_sde_rm_get_hw_locked(rm, &iter)) {
  795. if (iter.blk->id == lm_cfg->dspp) {
  796. *dspp = iter.blk;
  797. break;
  798. }
  799. }
  800. if (!*dspp) {
  801. SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
  802. lm_cfg->dspp);
  803. return false;
  804. }
  805. if (RESERVED_BY_OTHER(*dspp, rsvp)) {
  806. SDE_DEBUG("lm %d dspp %d already reserved\n",
  807. lm->id, (*dspp)->id);
  808. return false;
  809. }
  810. }
  811. return true;
  812. }
  813. static bool _sde_rm_reserve_ds(
  814. struct sde_rm *rm,
  815. struct sde_rm_rsvp *rsvp,
  816. const struct sde_lm_cfg *lm_cfg,
  817. struct sde_rm_hw_blk *lm,
  818. struct sde_rm_hw_blk **ds)
  819. {
  820. struct sde_rm_hw_iter iter;
  821. if (lm_cfg->ds != DS_MAX) {
  822. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DS);
  823. while (_sde_rm_get_hw_locked(rm, &iter)) {
  824. if (iter.blk->id == lm_cfg->ds) {
  825. *ds = iter.blk;
  826. break;
  827. }
  828. }
  829. if (!*ds) {
  830. SDE_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
  831. lm_cfg->ds);
  832. return false;
  833. }
  834. if (RESERVED_BY_OTHER(*ds, rsvp)) {
  835. SDE_DEBUG("lm %d ds %d already reserved\n",
  836. lm->id, (*ds)->id);
  837. return false;
  838. }
  839. }
  840. return true;
  841. }
  842. static bool _sde_rm_reserve_pp(
  843. struct sde_rm *rm,
  844. struct sde_rm_rsvp *rsvp,
  845. struct sde_rm_requirements *reqs,
  846. const struct sde_lm_cfg *lm_cfg,
  847. const struct sde_pingpong_cfg *pp_cfg,
  848. struct sde_rm_hw_blk *lm,
  849. struct sde_rm_hw_blk **dspp,
  850. struct sde_rm_hw_blk **ds,
  851. struct sde_rm_hw_blk **pp)
  852. {
  853. struct sde_rm_hw_iter iter;
  854. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
  855. while (_sde_rm_get_hw_locked(rm, &iter)) {
  856. if (iter.blk->id == lm_cfg->pingpong) {
  857. *pp = iter.blk;
  858. break;
  859. }
  860. }
  861. if (!*pp) {
  862. SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
  863. return false;
  864. }
  865. if (RESERVED_BY_OTHER(*pp, rsvp)) {
  866. SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
  867. (*pp)->id);
  868. *dspp = NULL;
  869. *ds = NULL;
  870. return false;
  871. }
  872. pp_cfg = to_sde_hw_pingpong((*pp)->hw)->caps;
  873. if ((reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
  874. !(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
  875. SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
  876. *dspp = NULL;
  877. *ds = NULL;
  878. return false;
  879. }
  880. return true;
  881. }
  882. /**
  883. * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
  884. * proposed use case requirements, incl. hardwired dependent blocks like
  885. * pingpong, and dspp.
  886. * @rm: sde resource manager handle
  887. * @rsvp: reservation currently being created
  888. * @reqs: proposed use case requirements
  889. * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  890. * blocks connected to the lm (pp, dspp) are available and appropriate
  891. * @dspp: output parameter, dspp block attached to the layer mixer.
  892. * NULL if dspp was not available, or not matching requirements.
  893. * @pp: output parameter, pingpong block attached to the layer mixer.
  894. * NULL if dspp was not available, or not matching requirements.
  895. * @primary_lm: if non-null, this function check if lm is compatible primary_lm
  896. * as well as satisfying all other requirements
  897. * @Return: true if lm matches all requirements, false otherwise
  898. */
  899. static bool _sde_rm_check_lm_and_get_connected_blks(
  900. struct sde_rm *rm,
  901. struct sde_rm_rsvp *rsvp,
  902. struct sde_rm_requirements *reqs,
  903. struct sde_rm_hw_blk *lm,
  904. struct sde_rm_hw_blk **dspp,
  905. struct sde_rm_hw_blk **ds,
  906. struct sde_rm_hw_blk **pp,
  907. struct sde_rm_hw_blk *primary_lm)
  908. {
  909. const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
  910. const struct sde_pingpong_cfg *pp_cfg;
  911. bool ret, is_conn_primary, is_conn_secondary;
  912. u32 lm_primary_pref, lm_secondary_pref, cwb_pref, dcwb_pref;
  913. *dspp = NULL;
  914. *ds = NULL;
  915. *pp = NULL;
  916. lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
  917. lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
  918. cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
  919. dcwb_pref = lm_cfg->features & BIT(SDE_DISP_DCWB_PREF);
  920. is_conn_primary = (reqs->hw_res.display_type ==
  921. SDE_CONNECTOR_PRIMARY) ? true : false;
  922. is_conn_secondary = (reqs->hw_res.display_type ==
  923. SDE_CONNECTOR_SECONDARY) ? true : false;
  924. SDE_DEBUG("check lm %d: dspp %d ds %d pp %d features %d disp type %d\n",
  925. lm_cfg->id, lm_cfg->dspp, lm_cfg->ds, lm_cfg->pingpong,
  926. lm_cfg->features, (int)reqs->hw_res.display_type);
  927. /* Check if this layer mixer is a peer of the proposed primary LM */
  928. if (primary_lm) {
  929. const struct sde_lm_cfg *prim_lm_cfg =
  930. to_sde_hw_mixer(primary_lm->hw)->cap;
  931. if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
  932. SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
  933. prim_lm_cfg->id);
  934. return false;
  935. }
  936. }
  937. /* bypass rest of the checks if LM for primary display is found */
  938. if (!lm_primary_pref && !lm_secondary_pref) {
  939. /* Check lm for valid requirements */
  940. ret = _sde_rm_check_lm(rm, rsvp, reqs, lm_cfg, lm,
  941. dspp, ds, pp);
  942. if (!ret)
  943. return ret;
  944. /**
  945. * If CWB is enabled and LM is not CWB supported
  946. * then return false.
  947. */
  948. if ((RM_RQ_CWB(reqs) && !cwb_pref) ||
  949. (RM_RQ_DCWB(reqs) && !dcwb_pref)) {
  950. SDE_DEBUG("fail: cwb/dcwb supported lm not allocated\n");
  951. return false;
  952. }
  953. } else if ((!is_conn_primary && lm_primary_pref) ||
  954. (!is_conn_secondary && lm_secondary_pref)) {
  955. SDE_DEBUG(
  956. "display preference is not met. display_type: %d lm_features: %x\n",
  957. (int)reqs->hw_res.display_type, lm_cfg->features);
  958. return false;
  959. }
  960. /* Already reserved? */
  961. if (RESERVED_BY_OTHER(lm, rsvp)) {
  962. SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
  963. return false;
  964. }
  965. /* Reserve dspp */
  966. ret = _sde_rm_reserve_dspp(rm, rsvp, lm_cfg, lm, dspp);
  967. if (!ret)
  968. return ret;
  969. /* Reserve ds */
  970. ret = _sde_rm_reserve_ds(rm, rsvp, lm_cfg, lm, ds);
  971. if (!ret)
  972. return ret;
  973. /* Reserve pp */
  974. ret = _sde_rm_reserve_pp(rm, rsvp, reqs, lm_cfg, pp_cfg, lm,
  975. dspp, ds, pp);
  976. if (!ret)
  977. return ret;
  978. return true;
  979. }
  980. static int _sde_rm_reserve_lms(
  981. struct sde_rm *rm,
  982. struct sde_rm_rsvp *rsvp,
  983. struct sde_rm_requirements *reqs,
  984. u8 *_lm_ids)
  985. {
  986. struct sde_rm_hw_blk *lm[MAX_BLOCKS];
  987. struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
  988. struct sde_rm_hw_blk *ds[MAX_BLOCKS];
  989. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  990. struct sde_rm_hw_iter iter_i, iter_j;
  991. u32 lm_mask = 0;
  992. int lm_count = 0;
  993. int i, rc = 0;
  994. if (!reqs->topology->num_lm) {
  995. SDE_DEBUG("invalid number of lm: %d\n", reqs->topology->num_lm);
  996. return 0;
  997. }
  998. /* Find a primary mixer */
  999. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
  1000. while (lm_count != reqs->topology->num_lm &&
  1001. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1002. if (lm_mask & (1 << iter_i.blk->id))
  1003. continue;
  1004. lm[lm_count] = iter_i.blk;
  1005. dspp[lm_count] = NULL;
  1006. ds[lm_count] = NULL;
  1007. pp[lm_count] = NULL;
  1008. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  1009. iter_i.blk->id,
  1010. lm_count,
  1011. _lm_ids ? _lm_ids[lm_count] : -1);
  1012. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  1013. continue;
  1014. if (!_sde_rm_check_lm_and_get_connected_blks(
  1015. rm, rsvp, reqs, lm[lm_count],
  1016. &dspp[lm_count], &ds[lm_count],
  1017. &pp[lm_count], NULL))
  1018. continue;
  1019. lm_mask |= (1 << iter_i.blk->id);
  1020. ++lm_count;
  1021. /* Return if peer is not needed */
  1022. if (lm_count == reqs->topology->num_lm)
  1023. break;
  1024. /* Valid primary mixer found, find matching peers */
  1025. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
  1026. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1027. if (lm_mask & (1 << iter_j.blk->id))
  1028. continue;
  1029. lm[lm_count] = iter_j.blk;
  1030. dspp[lm_count] = NULL;
  1031. ds[lm_count] = NULL;
  1032. pp[lm_count] = NULL;
  1033. if (!_sde_rm_check_lm_and_get_connected_blks(
  1034. rm, rsvp, reqs, iter_j.blk,
  1035. &dspp[lm_count], &ds[lm_count],
  1036. &pp[lm_count], iter_i.blk))
  1037. continue;
  1038. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  1039. iter_j.blk->id,
  1040. lm_count,
  1041. _lm_ids ? _lm_ids[lm_count] : -1);
  1042. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  1043. continue;
  1044. lm_mask |= (1 << iter_j.blk->id);
  1045. ++lm_count;
  1046. break;
  1047. }
  1048. /* Rollback primary LM if peer is not found */
  1049. if (!iter_j.hw) {
  1050. lm_mask &= ~(1 << iter_i.blk->id);
  1051. --lm_count;
  1052. }
  1053. }
  1054. if (lm_count != reqs->topology->num_lm) {
  1055. SDE_DEBUG("unable to find appropriate mixers\n");
  1056. return -ENAVAIL;
  1057. }
  1058. for (i = 0; i < lm_count; i++) {
  1059. lm[i]->rsvp_nxt = rsvp;
  1060. pp[i]->rsvp_nxt = rsvp;
  1061. if (dspp[i])
  1062. dspp[i]->rsvp_nxt = rsvp;
  1063. if (ds[i])
  1064. ds[i]->rsvp_nxt = rsvp;
  1065. SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
  1066. dspp[i] ? dspp[i]->id : 0,
  1067. ds[i] ? ds[i]->id : 0);
  1068. }
  1069. if (reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
  1070. /* reserve a free PINGPONG_SLAVE block */
  1071. rc = -ENAVAIL;
  1072. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
  1073. while (_sde_rm_get_hw_locked(rm, &iter_i)) {
  1074. const struct sde_hw_pingpong *pp =
  1075. to_sde_hw_pingpong(iter_i.blk->hw);
  1076. const struct sde_pingpong_cfg *pp_cfg = pp->caps;
  1077. if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
  1078. continue;
  1079. if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
  1080. continue;
  1081. iter_i.blk->rsvp_nxt = rsvp;
  1082. rc = 0;
  1083. break;
  1084. }
  1085. }
  1086. return rc;
  1087. }
  1088. static int _sde_rm_reserve_ctls(
  1089. struct sde_rm *rm,
  1090. struct sde_rm_rsvp *rsvp,
  1091. struct sde_rm_requirements *reqs,
  1092. const struct sde_rm_topology_def *top,
  1093. u8 *_ctl_ids)
  1094. {
  1095. struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
  1096. struct sde_rm_hw_iter iter;
  1097. int i = 0;
  1098. if (!top->num_ctl) {
  1099. SDE_DEBUG("invalid number of ctl: %d\n", top->num_ctl);
  1100. return 0;
  1101. }
  1102. memset(&ctls, 0, sizeof(ctls));
  1103. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  1104. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1105. const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  1106. unsigned long features = ctl->caps->features;
  1107. bool has_split_display, has_ppsplit, primary_pref;
  1108. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1109. continue;
  1110. has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
  1111. has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
  1112. primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
  1113. SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
  1114. /*
  1115. * bypass rest feature checks on finding CTL preferred
  1116. * for primary displays.
  1117. */
  1118. if (!primary_pref && !_ctl_ids) {
  1119. if (top->needs_split_display != has_split_display)
  1120. continue;
  1121. if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
  1122. !has_ppsplit)
  1123. continue;
  1124. } else if (!(reqs->hw_res.display_type ==
  1125. SDE_CONNECTOR_PRIMARY && primary_pref) && !_ctl_ids) {
  1126. SDE_DEBUG(
  1127. "display pref not met. display_type: %d primary_pref: %d\n",
  1128. reqs->hw_res.display_type, primary_pref);
  1129. continue;
  1130. }
  1131. ctls[i] = iter.blk;
  1132. SDE_DEBUG("blk id = %d, _ctl_ids[%d] = %d\n",
  1133. iter.blk->id, i,
  1134. _ctl_ids ? _ctl_ids[i] : -1);
  1135. if (_ctl_ids && (ctls[i]->id != _ctl_ids[i]))
  1136. continue;
  1137. SDE_DEBUG("ctl %d match\n", iter.blk->id);
  1138. if (++i == top->num_ctl)
  1139. break;
  1140. }
  1141. if (i != top->num_ctl)
  1142. return -ENAVAIL;
  1143. for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
  1144. ctls[i]->rsvp_nxt = rsvp;
  1145. SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
  1146. }
  1147. return 0;
  1148. }
  1149. static bool _sde_rm_check_dsc(struct sde_rm *rm,
  1150. struct sde_rm_rsvp *rsvp,
  1151. struct sde_rm_hw_blk *dsc,
  1152. struct sde_rm_hw_blk *paired_dsc,
  1153. struct sde_rm_hw_blk *pp_blk)
  1154. {
  1155. const struct sde_dsc_cfg *dsc_cfg = to_sde_hw_dsc(dsc->hw)->caps;
  1156. /* Already reserved? */
  1157. if (RESERVED_BY_OTHER(dsc, rsvp)) {
  1158. SDE_DEBUG("dsc %d already reserved\n", dsc_cfg->id);
  1159. return false;
  1160. }
  1161. /**
  1162. * This check is required for routing even numbered DSC
  1163. * blks to any of the even numbered PP blks and odd numbered
  1164. * DSC blks to any of the odd numbered PP blks.
  1165. */
  1166. if (!pp_blk || !IS_COMPATIBLE_PP_DSC(pp_blk->id, dsc->id))
  1167. return false;
  1168. /* Check if this dsc is a peer of the proposed paired DSC */
  1169. if (paired_dsc) {
  1170. const struct sde_dsc_cfg *paired_dsc_cfg =
  1171. to_sde_hw_dsc(paired_dsc->hw)->caps;
  1172. if (!test_bit(dsc_cfg->id, paired_dsc_cfg->dsc_pair_mask)) {
  1173. SDE_DEBUG("dsc %d not peer of dsc %d\n", dsc_cfg->id,
  1174. paired_dsc_cfg->id);
  1175. return false;
  1176. }
  1177. }
  1178. return true;
  1179. }
  1180. static bool _sde_rm_check_vdc(struct sde_rm *rm,
  1181. struct sde_rm_rsvp *rsvp,
  1182. struct sde_rm_hw_blk *vdc)
  1183. {
  1184. const struct sde_vdc_cfg *vdc_cfg = to_sde_hw_vdc(vdc->hw)->caps;
  1185. /* Already reserved? */
  1186. if (RESERVED_BY_OTHER(vdc, rsvp)) {
  1187. SDE_DEBUG("vdc %d already reserved\n", vdc_cfg->id);
  1188. return false;
  1189. }
  1190. return true;
  1191. }
  1192. static void sde_rm_get_rsvp_nxt_hw_blks(
  1193. struct sde_rm *rm,
  1194. struct sde_rm_rsvp *rsvp,
  1195. int type,
  1196. struct sde_rm_hw_blk **blk_arr)
  1197. {
  1198. struct sde_rm_hw_blk *blk;
  1199. int i = 0;
  1200. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1201. if (blk->rsvp_nxt && blk->rsvp_nxt->seq ==
  1202. rsvp->seq)
  1203. blk_arr[i++] = blk;
  1204. }
  1205. }
  1206. static int _sde_rm_reserve_dsc(
  1207. struct sde_rm *rm,
  1208. struct sde_rm_rsvp *rsvp,
  1209. struct sde_rm_requirements *reqs,
  1210. u8 *_dsc_ids)
  1211. {
  1212. struct sde_rm_hw_iter iter_i, iter_j;
  1213. struct sde_rm_hw_blk *dsc[MAX_BLOCKS];
  1214. u32 reserve_mask = 0;
  1215. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1216. int alloc_count = 0;
  1217. int num_dsc_enc;
  1218. struct msm_display_dsc_info *dsc_info;
  1219. int i;
  1220. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_DSC) {
  1221. SDE_DEBUG("compression blk dsc not required\n");
  1222. return 0;
  1223. }
  1224. num_dsc_enc = reqs->topology->num_comp_enc;
  1225. dsc_info = &reqs->hw_res.comp_info->dsc_info;
  1226. if ((!num_dsc_enc) || !dsc_info) {
  1227. SDE_DEBUG("invalid topoplogy params: %d, %d\n",
  1228. num_dsc_enc, !(dsc_info == NULL));
  1229. return 0;
  1230. }
  1231. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_DSC);
  1232. sde_rm_get_rsvp_nxt_hw_blks(rm, rsvp, SDE_HW_BLK_PINGPONG, pp);
  1233. /* Find a first DSC */
  1234. while (alloc_count != num_dsc_enc &&
  1235. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1236. const struct sde_hw_dsc *hw_dsc = to_sde_hw_dsc(
  1237. iter_i.blk->hw);
  1238. unsigned long features = hw_dsc->caps->features;
  1239. bool has_422_420_support =
  1240. BIT(SDE_DSC_NATIVE_422_EN) & features;
  1241. if (reserve_mask & (1 << iter_i.blk->id))
  1242. continue;
  1243. if (_dsc_ids && (iter_i.blk->id != _dsc_ids[alloc_count]))
  1244. continue;
  1245. /* if this hw block does not support required feature */
  1246. if (!_dsc_ids && (dsc_info->config.native_422 ||
  1247. dsc_info->config.native_420) && !has_422_420_support)
  1248. continue;
  1249. if (!_sde_rm_check_dsc(rm, rsvp, iter_i.blk, NULL,
  1250. pp[alloc_count]))
  1251. continue;
  1252. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1253. iter_i.blk->id,
  1254. alloc_count,
  1255. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1256. reserve_mask |= (1 << iter_i.blk->id);
  1257. dsc[alloc_count++] = iter_i.blk;
  1258. /* Return if peer is not needed */
  1259. if (alloc_count == num_dsc_enc)
  1260. break;
  1261. /* Valid first dsc found, find matching peers */
  1262. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_DSC);
  1263. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1264. if (reserve_mask & (1 << iter_j.blk->id))
  1265. continue;
  1266. if (_dsc_ids && (iter_j.blk->id !=
  1267. _dsc_ids[alloc_count]))
  1268. continue;
  1269. if (!_sde_rm_check_dsc(rm, rsvp, iter_j.blk,
  1270. iter_i.blk, pp[alloc_count]))
  1271. continue;
  1272. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1273. iter_j.blk->id,
  1274. alloc_count,
  1275. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1276. reserve_mask |= (1 << iter_j.blk->id);
  1277. dsc[alloc_count++] = iter_j.blk;
  1278. break;
  1279. }
  1280. /* Rollback primary DSC if peer is not found */
  1281. if (!iter_j.hw) {
  1282. reserve_mask &= ~(1 << iter_i.blk->id);
  1283. --alloc_count;
  1284. }
  1285. }
  1286. if (alloc_count != num_dsc_enc) {
  1287. SDE_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
  1288. num_dsc_enc, rsvp->enc_id);
  1289. return -EINVAL;
  1290. }
  1291. for (i = 0; i < alloc_count; i++) {
  1292. if (!dsc[i])
  1293. break;
  1294. dsc[i]->rsvp_nxt = rsvp;
  1295. SDE_EVT32(dsc[i]->type, rsvp->enc_id, dsc[i]->id);
  1296. }
  1297. return 0;
  1298. }
  1299. static int _sde_rm_reserve_vdc(
  1300. struct sde_rm *rm,
  1301. struct sde_rm_rsvp *rsvp,
  1302. struct sde_rm_requirements *reqs,
  1303. const struct sde_rm_topology_def *top,
  1304. u8 *_vdc_ids)
  1305. {
  1306. struct sde_rm_hw_iter iter_i;
  1307. struct sde_rm_hw_blk *vdc[MAX_BLOCKS];
  1308. int alloc_count = 0;
  1309. int num_vdc_enc = top->num_comp_enc;
  1310. int i;
  1311. if (!top->num_comp_enc)
  1312. return 0;
  1313. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_VDC)
  1314. return 0;
  1315. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_VDC);
  1316. /* Find a VDC */
  1317. while (alloc_count != num_vdc_enc &&
  1318. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1319. memset(&vdc, 0, sizeof(vdc));
  1320. alloc_count = 0;
  1321. if (_vdc_ids && (iter_i.blk->id != _vdc_ids[alloc_count]))
  1322. continue;
  1323. if (!_sde_rm_check_vdc(rm, rsvp, iter_i.blk))
  1324. continue;
  1325. SDE_DEBUG("blk id = %d, _vdc_ids[%d] = %d\n",
  1326. iter_i.blk->id,
  1327. alloc_count,
  1328. _vdc_ids ? _vdc_ids[alloc_count] : -1);
  1329. vdc[alloc_count++] = iter_i.blk;
  1330. }
  1331. if (alloc_count != num_vdc_enc) {
  1332. SDE_ERROR("couldn't reserve %d vdc blocks for enc id %d\n",
  1333. num_vdc_enc, rsvp->enc_id);
  1334. return -EINVAL;
  1335. }
  1336. for (i = 0; i < ARRAY_SIZE(vdc); i++) {
  1337. if (!vdc[i])
  1338. break;
  1339. vdc[i]->rsvp_nxt = rsvp;
  1340. SDE_EVT32(vdc[i]->type, rsvp->enc_id, vdc[i]->id);
  1341. }
  1342. return 0;
  1343. }
  1344. static int _sde_rm_reserve_qdss(
  1345. struct sde_rm *rm,
  1346. struct sde_rm_rsvp *rsvp,
  1347. const struct sde_rm_topology_def *top,
  1348. u8 *_qdss_ids)
  1349. {
  1350. struct sde_rm_hw_iter iter;
  1351. struct msm_drm_private *priv = rm->dev->dev_private;
  1352. struct sde_kms *sde_kms;
  1353. if (!priv->kms) {
  1354. SDE_ERROR("invalid kms\n");
  1355. return -EINVAL;
  1356. }
  1357. sde_kms = to_sde_kms(priv->kms);
  1358. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_QDSS);
  1359. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1360. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1361. continue;
  1362. SDE_DEBUG("blk id = %d\n", iter.blk->id);
  1363. iter.blk->rsvp_nxt = rsvp;
  1364. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1365. return 0;
  1366. }
  1367. if (!iter.hw && sde_kms->catalog->qdss_count) {
  1368. SDE_DEBUG("couldn't reserve qdss for type %d id %d\n",
  1369. SDE_HW_BLK_QDSS, iter.blk->id);
  1370. return -ENAVAIL;
  1371. }
  1372. return 0;
  1373. }
  1374. static int _sde_rm_reserve_cdm(
  1375. struct sde_rm *rm,
  1376. struct sde_rm_rsvp *rsvp,
  1377. uint32_t id,
  1378. enum sde_hw_blk_type type)
  1379. {
  1380. struct sde_rm_hw_iter iter;
  1381. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
  1382. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1383. const struct sde_hw_cdm *cdm = to_sde_hw_cdm(iter.blk->hw);
  1384. const struct sde_cdm_cfg *caps = cdm->caps;
  1385. bool match = false;
  1386. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1387. continue;
  1388. if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
  1389. match = test_bit(id, &caps->intf_connect);
  1390. else if (type == SDE_HW_BLK_WB && id != WB_MAX)
  1391. match = test_bit(id, &caps->wb_connect);
  1392. SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
  1393. type, id, caps->intf_connect, caps->wb_connect,
  1394. match);
  1395. if (!match)
  1396. continue;
  1397. iter.blk->rsvp_nxt = rsvp;
  1398. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1399. break;
  1400. }
  1401. if (!iter.hw) {
  1402. SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
  1403. return -ENAVAIL;
  1404. }
  1405. return 0;
  1406. }
  1407. static int _sde_rm_reserve_intf_or_wb(
  1408. struct sde_rm *rm,
  1409. struct sde_rm_rsvp *rsvp,
  1410. uint32_t id,
  1411. enum sde_hw_blk_type type,
  1412. bool needs_cdm)
  1413. {
  1414. struct sde_rm_hw_iter iter;
  1415. int ret = 0;
  1416. /* Find the block entry in the rm, and note the reservation */
  1417. sde_rm_init_hw_iter(&iter, 0, type);
  1418. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1419. if (iter.blk->id != id)
  1420. continue;
  1421. if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
  1422. SDE_ERROR("type %d id %d already reserved\n", type, id);
  1423. return -ENAVAIL;
  1424. }
  1425. iter.blk->rsvp_nxt = rsvp;
  1426. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1427. break;
  1428. }
  1429. /* Shouldn't happen since wbs / intfs are fixed at probe */
  1430. if (!iter.hw) {
  1431. SDE_ERROR("couldn't find type %d id %d\n", type, id);
  1432. return -EINVAL;
  1433. }
  1434. /* Expected only one intf or wb will request cdm */
  1435. if (needs_cdm)
  1436. ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
  1437. return ret;
  1438. }
  1439. static int _sde_rm_reserve_intf_related_hw(
  1440. struct sde_rm *rm,
  1441. struct sde_rm_rsvp *rsvp,
  1442. struct sde_encoder_hw_resources *hw_res)
  1443. {
  1444. int i, ret = 0;
  1445. u32 id;
  1446. for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
  1447. if (hw_res->intfs[i] == INTF_MODE_NONE)
  1448. continue;
  1449. id = i + INTF_0;
  1450. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1451. SDE_HW_BLK_INTF, hw_res->needs_cdm);
  1452. if (ret)
  1453. return ret;
  1454. }
  1455. for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
  1456. if (hw_res->wbs[i] == INTF_MODE_NONE)
  1457. continue;
  1458. id = i + WB_0;
  1459. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1460. SDE_HW_BLK_WB, hw_res->needs_cdm);
  1461. if (ret)
  1462. return ret;
  1463. }
  1464. return ret;
  1465. }
  1466. static bool _sde_rm_is_display_in_cont_splash(struct sde_kms *sde_kms,
  1467. struct drm_encoder *enc)
  1468. {
  1469. int i;
  1470. struct sde_splash_display *splash_dpy;
  1471. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1472. splash_dpy = &sde_kms->splash_data.splash_display[i];
  1473. if (splash_dpy->encoder == enc)
  1474. return splash_dpy->cont_splash_enabled;
  1475. }
  1476. return false;
  1477. }
  1478. static int _sde_rm_make_lm_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1479. struct sde_rm_requirements *reqs,
  1480. struct sde_splash_display *splash_display)
  1481. {
  1482. int ret, i;
  1483. u8 *hw_ids = NULL;
  1484. /* Check if splash data provided lm_ids */
  1485. if (splash_display) {
  1486. hw_ids = splash_display->lm_ids;
  1487. for (i = 0; i < splash_display->lm_cnt; i++)
  1488. SDE_DEBUG("splash_display->lm_ids[%d] = %d\n",
  1489. i, splash_display->lm_ids[i]);
  1490. if (splash_display->lm_cnt != reqs->topology->num_lm)
  1491. SDE_DEBUG("Configured splash LMs != needed LM cnt\n");
  1492. }
  1493. /*
  1494. * Assign LMs and blocks whose usage is tied to them:
  1495. * DSPP & Pingpong.
  1496. */
  1497. ret = _sde_rm_reserve_lms(rm, rsvp, reqs, hw_ids);
  1498. return ret;
  1499. }
  1500. static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1501. struct sde_rm_requirements *reqs,
  1502. struct sde_splash_display *splash_display)
  1503. {
  1504. int ret, i;
  1505. u8 *hw_ids = NULL;
  1506. struct sde_rm_topology_def topology;
  1507. /* Check if splash data provided ctl_ids */
  1508. if (splash_display) {
  1509. hw_ids = splash_display->ctl_ids;
  1510. for (i = 0; i < splash_display->ctl_cnt; i++)
  1511. SDE_DEBUG("splash_display->ctl_ids[%d] = %d\n",
  1512. i, splash_display->ctl_ids[i]);
  1513. }
  1514. /*
  1515. * Do assignment preferring to give away low-resource CTLs first:
  1516. * - Check mixers without Split Display
  1517. * - Only then allow to grab from CTLs with split display capability
  1518. */
  1519. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology, hw_ids);
  1520. if (ret && !reqs->topology->needs_split_display &&
  1521. reqs->topology->num_ctl > SINGLE_CTL) {
  1522. memcpy(&topology, reqs->topology, sizeof(topology));
  1523. topology.needs_split_display = true;
  1524. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology, hw_ids);
  1525. }
  1526. return ret;
  1527. }
  1528. static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1529. struct sde_rm_requirements *reqs,
  1530. struct sde_splash_display *splash_display)
  1531. {
  1532. int i;
  1533. u8 *hw_ids = NULL;
  1534. /* Check if splash data provided dsc_ids */
  1535. if (splash_display) {
  1536. hw_ids = splash_display->dsc_ids;
  1537. if (splash_display->dsc_cnt)
  1538. reqs->hw_res.comp_info->comp_type =
  1539. MSM_DISPLAY_COMPRESSION_DSC;
  1540. for (i = 0; i < splash_display->dsc_cnt; i++)
  1541. SDE_DEBUG("splash_data.dsc_ids[%d] = %d\n",
  1542. i, splash_display->dsc_ids[i]);
  1543. }
  1544. return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
  1545. }
  1546. static int _sde_rm_make_vdc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1547. struct sde_rm_requirements *reqs,
  1548. struct sde_splash_display *splash_display)
  1549. {
  1550. int ret, i;
  1551. u8 *hw_ids = NULL;
  1552. /* Check if splash data provided vdc_ids */
  1553. if (splash_display) {
  1554. hw_ids = splash_display->vdc_ids;
  1555. for (i = 0; i < splash_display->vdc_cnt; i++)
  1556. SDE_DEBUG("splash_data.vdc_ids[%d] = %d\n",
  1557. i, splash_display->vdc_ids[i]);
  1558. }
  1559. ret = _sde_rm_reserve_vdc(rm, rsvp, reqs, reqs->topology, hw_ids);
  1560. return ret;
  1561. }
  1562. static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
  1563. struct drm_crtc_state *crtc_state,
  1564. struct drm_connector_state *conn_state,
  1565. struct sde_rm_rsvp *rsvp,
  1566. struct sde_rm_requirements *reqs)
  1567. {
  1568. struct msm_drm_private *priv;
  1569. struct sde_kms *sde_kms;
  1570. struct sde_splash_display *splash_display = NULL;
  1571. struct sde_splash_data *splash_data;
  1572. int i, ret;
  1573. priv = enc->dev->dev_private;
  1574. sde_kms = to_sde_kms(priv->kms);
  1575. splash_data = &sde_kms->splash_data;
  1576. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1577. for (i = 0; i < ARRAY_SIZE(splash_data->splash_display); i++) {
  1578. if (enc == splash_data->splash_display[i].encoder)
  1579. splash_display =
  1580. &splash_data->splash_display[i];
  1581. }
  1582. if (!splash_display) {
  1583. SDE_ERROR("rm is in cont_splash but data not found\n");
  1584. return -EINVAL;
  1585. }
  1586. }
  1587. /* Create reservation info, tag reserved blocks with it as we go */
  1588. rsvp->seq = ++rm->rsvp_next_seq;
  1589. rsvp->enc_id = enc->base.id;
  1590. rsvp->topology = reqs->topology->top_name;
  1591. list_add_tail(&rsvp->list, &rm->rsvps);
  1592. ret = _sde_rm_make_lm_rsvp(rm, rsvp, reqs, splash_display);
  1593. if (ret) {
  1594. SDE_ERROR("unable to find appropriate mixers\n");
  1595. _sde_rm_print_rsvps_by_type(rm, SDE_HW_BLK_LM);
  1596. return ret;
  1597. }
  1598. ret = _sde_rm_make_ctl_rsvp(rm, rsvp, reqs, splash_display);
  1599. if (ret) {
  1600. SDE_ERROR("unable to find appropriate CTL\n");
  1601. return ret;
  1602. }
  1603. /* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
  1604. ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
  1605. if (ret)
  1606. return ret;
  1607. ret = _sde_rm_make_dsc_rsvp(rm, rsvp, reqs, splash_display);
  1608. if (ret)
  1609. return ret;
  1610. ret = _sde_rm_make_vdc_rsvp(rm, rsvp, reqs, splash_display);
  1611. if (ret)
  1612. return ret;
  1613. ret = _sde_rm_reserve_qdss(rm, rsvp, reqs->topology, NULL);
  1614. if (ret)
  1615. return ret;
  1616. return ret;
  1617. }
  1618. /**
  1619. * _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
  1620. * and populate the connected HW blk ids in sde_splash_display
  1621. * @rm: Pointer to resource manager structure
  1622. * @ctl: Pointer to CTL hardware block
  1623. * @splash_display: Pointer to struct sde_splash_display
  1624. * return: number of active LM blocks for this CTL block
  1625. */
  1626. static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
  1627. struct sde_hw_ctl *ctl,
  1628. struct sde_splash_display *splash_display)
  1629. {
  1630. u32 lm_reg;
  1631. struct sde_rm_hw_iter iter_lm, iter_dsc;
  1632. struct sde_kms *sde_kms;
  1633. if (!rm || !ctl || !splash_display) {
  1634. SDE_ERROR("invalid input parameters\n");
  1635. return 0;
  1636. }
  1637. sde_kms = container_of(rm, struct sde_kms, rm);
  1638. sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
  1639. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1640. while (_sde_rm_get_hw_locked(rm, &iter_lm)) {
  1641. if (splash_display->lm_cnt >= MAX_DATA_PATH_PER_DSIPLAY)
  1642. break;
  1643. lm_reg = ctl->ops.read_ctl_layers(ctl, iter_lm.blk->id);
  1644. if (!lm_reg)
  1645. continue;
  1646. splash_display->lm_ids[splash_display->lm_cnt++] =
  1647. iter_lm.blk->id;
  1648. SDE_DEBUG("lm_cnt=%d lm_reg[%d]=0x%x\n", splash_display->lm_cnt,
  1649. iter_lm.blk->id - LM_0, lm_reg);
  1650. if (ctl->ops.get_staged_sspp &&
  1651. ctl->ops.get_staged_sspp(ctl, iter_lm.blk->id,
  1652. &splash_display->pipes[
  1653. splash_display->pipe_cnt], 1)) {
  1654. splash_display->pipe_cnt++;
  1655. } else if (sde_kms->splash_data.type == SDE_VM_HANDOFF) {
  1656. /* Allow VM handoff without any pipes, as it is a
  1657. * valid case to have NULL commit before the
  1658. * transition.
  1659. */
  1660. SDE_DEBUG("VM handoff with no pipes staged\n");
  1661. } else {
  1662. SDE_ERROR("no pipe detected on LM-%d\n",
  1663. iter_lm.blk->id - LM_0);
  1664. return 0;
  1665. }
  1666. }
  1667. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1668. if (ctl->ops.read_active_status &&
  1669. !(ctl->ops.read_active_status(ctl,
  1670. SDE_HW_BLK_DSC,
  1671. iter_dsc.blk->id)))
  1672. continue;
  1673. splash_display->dsc_ids[splash_display->dsc_cnt++] =
  1674. iter_dsc.blk->id;
  1675. SDE_DEBUG("CTL[%d] path, using dsc[%d]\n",
  1676. ctl->idx,
  1677. iter_dsc.blk->id - DSC_0);
  1678. }
  1679. return splash_display->lm_cnt;
  1680. }
  1681. int sde_rm_cont_splash_res_init(struct msm_drm_private *priv,
  1682. struct sde_rm *rm,
  1683. struct sde_splash_data *splash_data,
  1684. struct sde_mdss_cfg *cat)
  1685. {
  1686. struct sde_rm_hw_iter iter_c;
  1687. int index = 0, ctl_top_cnt;
  1688. struct sde_kms *sde_kms = NULL;
  1689. struct sde_hw_mdp *hw_mdp;
  1690. struct sde_splash_display *splash_display;
  1691. u8 intf_sel;
  1692. if (!priv || !rm || !cat || !splash_data) {
  1693. SDE_ERROR("invalid input parameters\n");
  1694. return -EINVAL;
  1695. }
  1696. SDE_DEBUG("mixer_count=%d, ctl_count=%d, dsc_count=%d\n",
  1697. cat->mixer_count,
  1698. cat->ctl_count,
  1699. cat->dsc_count);
  1700. ctl_top_cnt = cat->ctl_count;
  1701. if (!priv->kms) {
  1702. SDE_ERROR("invalid kms\n");
  1703. return -EINVAL;
  1704. }
  1705. sde_kms = to_sde_kms(priv->kms);
  1706. hw_mdp = sde_rm_get_mdp(rm);
  1707. sde_rm_init_hw_iter(&iter_c, 0, SDE_HW_BLK_CTL);
  1708. while (_sde_rm_get_hw_locked(rm, &iter_c)
  1709. && (index < splash_data->num_splash_displays)) {
  1710. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter_c.blk->hw);
  1711. if (!ctl->ops.get_ctl_intf) {
  1712. SDE_ERROR("get_ctl_intf not initialized\n");
  1713. return -EINVAL;
  1714. }
  1715. intf_sel = ctl->ops.get_ctl_intf(ctl);
  1716. if (intf_sel) {
  1717. splash_display = &splash_data->splash_display[index];
  1718. SDE_DEBUG("finding resources for display=%d ctl=%d\n",
  1719. index, iter_c.blk->id - CTL_0);
  1720. _sde_rm_get_hw_blk_for_cont_splash(rm,
  1721. ctl, splash_display);
  1722. splash_display->cont_splash_enabled = true;
  1723. splash_display->ctl_ids[splash_display->ctl_cnt++] =
  1724. iter_c.blk->id;
  1725. }
  1726. index++;
  1727. }
  1728. return 0;
  1729. }
  1730. static int _sde_rm_populate_requirements(
  1731. struct sde_rm *rm,
  1732. struct drm_encoder *enc,
  1733. struct drm_crtc_state *crtc_state,
  1734. struct drm_connector_state *conn_state,
  1735. struct sde_mdss_cfg *cfg,
  1736. struct sde_rm_requirements *reqs)
  1737. {
  1738. const struct drm_display_mode *mode = &crtc_state->mode;
  1739. int i, num_lm;
  1740. reqs->top_ctrl = sde_connector_get_property(conn_state,
  1741. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1742. sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
  1743. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++) {
  1744. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  1745. reqs->hw_res.topology)) {
  1746. reqs->topology = &rm->topology_tbl[i];
  1747. break;
  1748. }
  1749. }
  1750. if (!reqs->topology) {
  1751. SDE_ERROR("invalid topology for the display\n");
  1752. return -EINVAL;
  1753. }
  1754. /*
  1755. * select dspp HW block for all dsi displays and ds for only
  1756. * primary dsi display.
  1757. */
  1758. if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
  1759. if (!RM_RQ_DSPP(reqs))
  1760. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
  1761. if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
  1762. sde_encoder_is_primary_display(enc))
  1763. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);
  1764. }
  1765. /**
  1766. * Set the requirement for LM which has CWB support if CWB is
  1767. * found enabled.
  1768. */
  1769. if ((!RM_RQ_CWB(reqs) || !RM_RQ_DCWB(reqs))
  1770. && sde_encoder_in_clone_mode(enc)) {
  1771. if (cfg->has_dedicated_cwb_support)
  1772. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DCWB);
  1773. else
  1774. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
  1775. /*
  1776. * topology selection based on conn mode is not valid for CWB
  1777. * as WB conn populates modes based on max_mixer_width check
  1778. * but primary can be using dual LMs. This topology override for
  1779. * CWB is to check number of datapath active in primary and
  1780. * allocate same number of LM/PP blocks reserved for CWB
  1781. */
  1782. reqs->topology =
  1783. &rm->topology_tbl[SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE];
  1784. num_lm = sde_crtc_get_num_datapath(crtc_state->crtc,
  1785. conn_state->connector);
  1786. if (num_lm == 1)
  1787. reqs->topology =
  1788. &rm->topology_tbl[SDE_RM_TOPOLOGY_SINGLEPIPE];
  1789. else if (num_lm == 0)
  1790. SDE_ERROR("Primary layer mixer is not set\n");
  1791. SDE_EVT32(num_lm, reqs->topology->num_lm,
  1792. reqs->topology->top_name, reqs->topology->num_ctl);
  1793. }
  1794. SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
  1795. reqs->hw_res.display_num_of_h_tiles);
  1796. SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
  1797. reqs->topology->num_lm, reqs->topology->num_ctl,
  1798. reqs->topology->top_name,
  1799. reqs->topology->needs_split_display);
  1800. SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
  1801. reqs->top_ctrl, reqs->topology->top_name,
  1802. reqs->topology->num_ctl);
  1803. return 0;
  1804. }
  1805. static struct sde_rm_rsvp *_sde_rm_get_rsvp(
  1806. struct sde_rm *rm,
  1807. struct drm_encoder *enc)
  1808. {
  1809. struct sde_rm_rsvp *i;
  1810. if (!rm || !enc) {
  1811. SDE_ERROR("invalid params\n");
  1812. return NULL;
  1813. }
  1814. if (list_empty(&rm->rsvps))
  1815. return NULL;
  1816. list_for_each_entry(i, &rm->rsvps, list)
  1817. if (i->enc_id == enc->base.id)
  1818. return i;
  1819. return NULL;
  1820. }
  1821. static struct sde_rm_rsvp *_sde_rm_get_rsvp_nxt(
  1822. struct sde_rm *rm,
  1823. struct drm_encoder *enc)
  1824. {
  1825. struct sde_rm_rsvp *i;
  1826. if (list_empty(&rm->rsvps))
  1827. return NULL;
  1828. list_for_each_entry(i, &rm->rsvps, list)
  1829. if (i->enc_id == enc->base.id)
  1830. break;
  1831. list_for_each_entry_continue(i, &rm->rsvps, list)
  1832. if (i->enc_id == enc->base.id)
  1833. return i;
  1834. return NULL;
  1835. }
  1836. static struct drm_connector *_sde_rm_get_connector(
  1837. struct drm_encoder *enc)
  1838. {
  1839. struct drm_connector *conn = NULL, *conn_search;
  1840. struct sde_connector *c_conn = NULL;
  1841. struct drm_connector_list_iter conn_iter;
  1842. drm_connector_list_iter_begin(enc->dev, &conn_iter);
  1843. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1844. c_conn = to_sde_connector(conn_search);
  1845. if (c_conn->encoder == enc) {
  1846. conn = conn_search;
  1847. break;
  1848. }
  1849. }
  1850. drm_connector_list_iter_end(&conn_iter);
  1851. return conn;
  1852. }
  1853. int sde_rm_update_topology(struct sde_rm *rm,
  1854. struct drm_connector_state *conn_state,
  1855. struct msm_display_topology *topology)
  1856. {
  1857. int i, ret = 0;
  1858. struct msm_display_topology top;
  1859. enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
  1860. if (!conn_state)
  1861. return -EINVAL;
  1862. if (topology) {
  1863. top = *topology;
  1864. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  1865. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i], top)) {
  1866. top_name = rm->topology_tbl[i].top_name;
  1867. break;
  1868. }
  1869. }
  1870. ret = msm_property_set_property(
  1871. sde_connector_get_propinfo(conn_state->connector),
  1872. sde_connector_get_property_state(conn_state),
  1873. CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
  1874. return ret;
  1875. }
  1876. bool sde_rm_topology_is_group(struct sde_rm *rm,
  1877. struct drm_crtc_state *state,
  1878. enum sde_rm_topology_group group)
  1879. {
  1880. int i, ret = 0;
  1881. struct sde_crtc_state *cstate;
  1882. struct drm_connector *conn;
  1883. struct drm_connector_state *conn_state;
  1884. struct msm_display_topology topology;
  1885. enum sde_rm_topology_name name;
  1886. if ((!rm) || (!state) || (!state->state)) {
  1887. pr_err("invalid arguments: rm:%d state:%d atomic state:%d\n",
  1888. !rm, !state, state ? (!state->state) : 0);
  1889. return false;
  1890. }
  1891. cstate = to_sde_crtc_state(state);
  1892. for (i = 0; i < cstate->num_connectors; i++) {
  1893. conn = cstate->connectors[i];
  1894. if (!conn) {
  1895. SDE_DEBUG("invalid connector\n");
  1896. continue;
  1897. }
  1898. conn_state = drm_atomic_get_new_connector_state(state->state,
  1899. conn);
  1900. if (!conn_state) {
  1901. SDE_DEBUG("%s invalid connector state\n", conn->name);
  1902. continue;
  1903. }
  1904. ret = sde_connector_state_get_topology(conn_state, &topology);
  1905. if (ret) {
  1906. SDE_DEBUG("%s invalid topology\n", conn->name);
  1907. continue;
  1908. }
  1909. name = sde_rm_get_topology_name(rm, topology);
  1910. switch (group) {
  1911. case SDE_RM_TOPOLOGY_GROUP_SINGLEPIPE:
  1912. if (TOPOLOGY_SINGLEPIPE_MODE(name))
  1913. return true;
  1914. break;
  1915. case SDE_RM_TOPOLOGY_GROUP_DUALPIPE:
  1916. if (TOPOLOGY_DUALPIPE_MODE(name))
  1917. return true;
  1918. break;
  1919. case SDE_RM_TOPOLOGY_GROUP_QUADPIPE:
  1920. if (TOPOLOGY_QUADPIPE_MODE(name))
  1921. return true;
  1922. break;
  1923. case SDE_RM_TOPOLOGY_GROUP_3DMERGE:
  1924. if (topology.num_lm > topology.num_intf &&
  1925. !topology.num_enc)
  1926. return true;
  1927. break;
  1928. case SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC:
  1929. if (topology.num_lm > topology.num_enc &&
  1930. topology.num_enc)
  1931. return true;
  1932. break;
  1933. case SDE_RM_TOPOLOGY_GROUP_DSCMERGE:
  1934. if (topology.num_lm == topology.num_enc &&
  1935. topology.num_enc)
  1936. return true;
  1937. break;
  1938. default:
  1939. SDE_ERROR("invalid topology group\n");
  1940. return false;
  1941. }
  1942. }
  1943. return false;
  1944. }
  1945. /**
  1946. * _sde_rm_release_rsvp - release resources and release a reservation
  1947. * @rm: KMS handle
  1948. * @rsvp: RSVP pointer to release and release resources for
  1949. */
  1950. static void _sde_rm_release_rsvp(
  1951. struct sde_rm *rm,
  1952. struct sde_rm_rsvp *rsvp,
  1953. struct drm_connector *conn)
  1954. {
  1955. struct sde_rm_rsvp *rsvp_c, *rsvp_n;
  1956. struct sde_rm_hw_blk *blk;
  1957. enum sde_hw_blk_type type;
  1958. if (!rsvp)
  1959. return;
  1960. SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
  1961. list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
  1962. if (rsvp == rsvp_c) {
  1963. list_del(&rsvp_c->list);
  1964. break;
  1965. }
  1966. }
  1967. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  1968. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1969. if (blk->rsvp == rsvp) {
  1970. blk->rsvp = NULL;
  1971. SDE_DEBUG("rel rsvp %d enc %d %d %d\n",
  1972. rsvp->seq, rsvp->enc_id,
  1973. blk->type, blk->id);
  1974. _sde_rm_inc_resource_info(rm,
  1975. &rm->avail_res, blk);
  1976. }
  1977. if (blk->rsvp_nxt == rsvp) {
  1978. blk->rsvp_nxt = NULL;
  1979. SDE_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
  1980. rsvp->seq, rsvp->enc_id,
  1981. blk->type, blk->id);
  1982. }
  1983. }
  1984. }
  1985. kfree(rsvp);
  1986. }
  1987. void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  1988. {
  1989. struct sde_rm_rsvp *rsvp;
  1990. struct drm_connector *conn = NULL;
  1991. struct msm_drm_private *priv;
  1992. struct sde_kms *sde_kms;
  1993. uint64_t top_ctrl = 0;
  1994. if (!rm || !enc) {
  1995. SDE_ERROR("invalid params\n");
  1996. return;
  1997. }
  1998. priv = enc->dev->dev_private;
  1999. if (!priv->kms) {
  2000. SDE_ERROR("invalid kms\n");
  2001. return;
  2002. }
  2003. sde_kms = to_sde_kms(priv->kms);
  2004. mutex_lock(&rm->rm_lock);
  2005. if (nxt)
  2006. rsvp = _sde_rm_get_rsvp_nxt(rm, enc);
  2007. else
  2008. rsvp = _sde_rm_get_rsvp(rm, enc);
  2009. if (!rsvp) {
  2010. SDE_DEBUG("failed to find rsvp for enc %d, nxt %d",
  2011. enc->base.id, nxt);
  2012. goto end;
  2013. }
  2014. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  2015. _sde_rm_release_rsvp(rm, rsvp, conn);
  2016. goto end;
  2017. }
  2018. conn = _sde_rm_get_connector(enc);
  2019. if (!conn) {
  2020. SDE_EVT32(enc->base.id, 0x0, 0xffffffff);
  2021. _sde_rm_release_rsvp(rm, rsvp, conn);
  2022. SDE_DEBUG("failed to get conn for enc %d nxt %d\n",
  2023. enc->base.id, nxt);
  2024. goto end;
  2025. }
  2026. top_ctrl = sde_connector_get_property(conn->state,
  2027. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  2028. SDE_EVT32(enc->base.id, conn->base.id, rsvp->seq, top_ctrl, nxt);
  2029. if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
  2030. SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
  2031. rsvp->seq, rsvp->enc_id);
  2032. } else {
  2033. SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
  2034. rsvp->enc_id);
  2035. _sde_rm_release_rsvp(rm, rsvp, conn);
  2036. }
  2037. end:
  2038. mutex_unlock(&rm->rm_lock);
  2039. }
  2040. static int _sde_rm_commit_rsvp(
  2041. struct sde_rm *rm,
  2042. struct sde_rm_rsvp *rsvp,
  2043. struct drm_connector_state *conn_state)
  2044. {
  2045. struct sde_rm_hw_blk *blk;
  2046. enum sde_hw_blk_type type;
  2047. int ret = 0;
  2048. /* Swap next rsvp to be the active */
  2049. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2050. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  2051. if (blk->rsvp_nxt && conn_state->best_encoder->base.id
  2052. == blk->rsvp_nxt->enc_id) {
  2053. blk->rsvp = blk->rsvp_nxt;
  2054. blk->rsvp_nxt = NULL;
  2055. _sde_rm_dec_resource_info(rm,
  2056. &rm->avail_res, blk);
  2057. }
  2058. }
  2059. }
  2060. if (!ret) {
  2061. SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id,
  2062. rsvp->topology);
  2063. SDE_EVT32(rsvp->enc_id, rsvp->topology);
  2064. }
  2065. return ret;
  2066. }
  2067. /* call this only after rm_mutex held */
  2068. struct sde_rm_rsvp *_sde_rm_poll_get_rsvp_nxt_locked(struct sde_rm *rm,
  2069. struct drm_encoder *enc)
  2070. {
  2071. int i;
  2072. u32 loop_count = 20;
  2073. struct sde_rm_rsvp *rsvp_nxt = NULL;
  2074. u32 sleep = RM_NXT_CLEAR_POLL_TIMEOUT_US / loop_count;
  2075. for (i = 0; i < loop_count; i++) {
  2076. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2077. if (!rsvp_nxt)
  2078. return rsvp_nxt;
  2079. mutex_unlock(&rm->rm_lock);
  2080. SDE_DEBUG("iteration i:%d sleep range:%uus to %uus\n",
  2081. i, sleep, sleep * 2);
  2082. usleep_range(sleep, sleep * 2);
  2083. mutex_lock(&rm->rm_lock);
  2084. }
  2085. /* make sure to get latest rsvp_next to avoid use after free issues */
  2086. return _sde_rm_get_rsvp_nxt(rm, enc);
  2087. }
  2088. int sde_rm_reserve(
  2089. struct sde_rm *rm,
  2090. struct drm_encoder *enc,
  2091. struct drm_crtc_state *crtc_state,
  2092. struct drm_connector_state *conn_state,
  2093. bool test_only)
  2094. {
  2095. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  2096. struct sde_rm_requirements reqs = {0,};
  2097. struct msm_drm_private *priv;
  2098. struct sde_kms *sde_kms;
  2099. struct msm_compression_info *comp_info;
  2100. int ret;
  2101. if (!rm || !enc || !crtc_state || !conn_state) {
  2102. SDE_ERROR("invalid arguments\n");
  2103. return -EINVAL;
  2104. }
  2105. if (!enc->dev || !enc->dev->dev_private) {
  2106. SDE_ERROR("drm device invalid\n");
  2107. return -EINVAL;
  2108. }
  2109. priv = enc->dev->dev_private;
  2110. if (!priv->kms) {
  2111. SDE_ERROR("invalid kms\n");
  2112. return -EINVAL;
  2113. }
  2114. sde_kms = to_sde_kms(priv->kms);
  2115. /* Check if this is just a page-flip */
  2116. if (!_sde_rm_is_display_in_cont_splash(sde_kms, enc) &&
  2117. !msm_atomic_needs_modeset(crtc_state))
  2118. return 0;
  2119. comp_info = kzalloc(sizeof(*comp_info), GFP_KERNEL);
  2120. if (!comp_info)
  2121. return -ENOMEM;
  2122. SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
  2123. conn_state->connector->base.id, enc->base.id,
  2124. crtc_state->crtc->base.id, test_only);
  2125. SDE_EVT32(enc->base.id, conn_state->connector->base.id);
  2126. mutex_lock(&rm->rm_lock);
  2127. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
  2128. rsvp_cur = _sde_rm_get_rsvp(rm, enc);
  2129. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2130. /*
  2131. * RM currently relies on rsvp_nxt assigned to the hw blocks to
  2132. * commit rsvps. This rsvp_nxt can be cleared by a back to back
  2133. * check_only commit with modeset when its predecessor atomic
  2134. * commit is delayed / not committed the reservation yet.
  2135. * Poll for rsvp_nxt clear, allow the check_only commit if rsvp_nxt
  2136. * gets cleared and bailout if it does not get cleared before timeout.
  2137. */
  2138. if (test_only && rsvp_cur && rsvp_nxt) {
  2139. rsvp_nxt = _sde_rm_poll_get_rsvp_nxt_locked(rm, enc);
  2140. if (rsvp_nxt) {
  2141. SDE_ERROR("poll timeout cur %d nxt %d enc %d\n",
  2142. rsvp_cur->seq, rsvp_nxt->seq, enc->base.id);
  2143. ret = -EINVAL;
  2144. goto end;
  2145. }
  2146. }
  2147. if (!test_only && rsvp_nxt)
  2148. goto commit_rsvp;
  2149. reqs.hw_res.comp_info = comp_info;
  2150. ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
  2151. conn_state, sde_kms->catalog, &reqs);
  2152. if (ret) {
  2153. SDE_ERROR("failed to populate hw requirements\n");
  2154. goto end;
  2155. }
  2156. /*
  2157. * We only support one active reservation per-hw-block. But to implement
  2158. * transactional semantics for test-only, and for allowing failure while
  2159. * modifying your existing reservation, over the course of this
  2160. * function we can have two reservations:
  2161. * Current: Existing reservation
  2162. * Next: Proposed reservation. The proposed reservation may fail, or may
  2163. * be discarded if in test-only mode.
  2164. * If reservation is successful, and we're not in test-only, then we
  2165. * replace the current with the next.
  2166. */
  2167. rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
  2168. if (!rsvp_nxt) {
  2169. ret = -ENOMEM;
  2170. goto end;
  2171. }
  2172. /*
  2173. * User can request that we clear out any reservation during the
  2174. * atomic_check phase by using this CLEAR bit
  2175. */
  2176. if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
  2177. SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
  2178. rsvp_cur->seq, rsvp_cur->enc_id);
  2179. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2180. rsvp_cur = NULL;
  2181. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
  2182. }
  2183. /* Check the proposed reservation, store it in hw's "next" field */
  2184. ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
  2185. rsvp_nxt, &reqs);
  2186. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
  2187. if (ret) {
  2188. SDE_ERROR("failed to reserve hw resources: %d, test_only %d\n",
  2189. ret, test_only);
  2190. _sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
  2191. goto end;
  2192. } else if (test_only && !RM_RQ_LOCK(&reqs)) {
  2193. /*
  2194. * Normally, if test_only, test the reservation and then undo
  2195. * However, if the user requests LOCK, then keep the reservation
  2196. * made during the atomic_check phase.
  2197. */
  2198. SDE_DEBUG("test_only: rsvp[s%de%d]\n",
  2199. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2200. goto end;
  2201. } else {
  2202. if (test_only && RM_RQ_LOCK(&reqs))
  2203. SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
  2204. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2205. }
  2206. commit_rsvp:
  2207. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2208. ret = _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
  2209. end:
  2210. kfree(comp_info);
  2211. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
  2212. mutex_unlock(&rm->rm_lock);
  2213. return ret;
  2214. }
  2215. int sde_rm_ext_blk_create_reserve(struct sde_rm *rm,
  2216. struct sde_hw_blk *hw, struct drm_encoder *enc)
  2217. {
  2218. struct sde_rm_hw_blk *blk;
  2219. struct sde_rm_rsvp *rsvp;
  2220. int ret = 0;
  2221. if (!rm || !hw || !enc) {
  2222. SDE_ERROR("invalid parameters\n");
  2223. return -EINVAL;
  2224. }
  2225. if (hw->type >= SDE_HW_BLK_MAX) {
  2226. SDE_ERROR("invalid HW type\n");
  2227. return -EINVAL;
  2228. }
  2229. mutex_lock(&rm->rm_lock);
  2230. rsvp = _sde_rm_get_rsvp(rm, enc);
  2231. if (!rsvp) {
  2232. rsvp = kzalloc(sizeof(*rsvp), GFP_KERNEL);
  2233. if (!rsvp) {
  2234. ret = -ENOMEM;
  2235. goto end;
  2236. }
  2237. rsvp->seq = ++rm->rsvp_next_seq;
  2238. rsvp->enc_id = enc->base.id;
  2239. list_add_tail(&rsvp->list, &rm->rsvps);
  2240. SDE_DEBUG("create rsvp %d for enc %d\n",
  2241. rsvp->seq, rsvp->enc_id);
  2242. }
  2243. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  2244. if (!blk) {
  2245. ret = -ENOMEM;
  2246. goto end;
  2247. }
  2248. blk->type = hw->type;
  2249. blk->id = hw->id;
  2250. blk->hw = hw;
  2251. blk->rsvp = rsvp;
  2252. list_add_tail(&blk->list, &rm->hw_blks[hw->type]);
  2253. SDE_DEBUG("create blk %d %d for rsvp %d enc %d\n", blk->type, blk->id,
  2254. rsvp->seq, rsvp->enc_id);
  2255. end:
  2256. mutex_unlock(&rm->rm_lock);
  2257. return ret;
  2258. }
  2259. int sde_rm_ext_blk_destroy(struct sde_rm *rm,
  2260. struct drm_encoder *enc)
  2261. {
  2262. struct sde_rm_hw_blk *blk = NULL, *p;
  2263. struct sde_rm_rsvp *rsvp;
  2264. enum sde_hw_blk_type type;
  2265. int ret = 0;
  2266. if (!rm || !enc) {
  2267. SDE_ERROR("invalid parameters\n");
  2268. return -EINVAL;
  2269. }
  2270. mutex_lock(&rm->rm_lock);
  2271. rsvp = _sde_rm_get_rsvp(rm, enc);
  2272. if (!rsvp) {
  2273. ret = -ENOENT;
  2274. SDE_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
  2275. goto end;
  2276. }
  2277. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2278. list_for_each_entry_safe(blk, p, &rm->hw_blks[type], list) {
  2279. if (blk->rsvp == rsvp) {
  2280. list_del(&blk->list);
  2281. SDE_DEBUG("del blk %d %d from rsvp %d enc %d\n",
  2282. blk->type, blk->id,
  2283. rsvp->seq, rsvp->enc_id);
  2284. kfree(blk);
  2285. }
  2286. }
  2287. }
  2288. SDE_DEBUG("del rsvp %d\n", rsvp->seq);
  2289. list_del(&rsvp->list);
  2290. kfree(rsvp);
  2291. end:
  2292. mutex_unlock(&rm->rm_lock);
  2293. return ret;
  2294. }