sde_kms.c 117 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706
  1. /*
  2. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. sde_rm_debugfs_init(&sde_kms->rm, debugfs_root);
  133. if (sde_kms->catalog->qdss_count)
  134. debugfs_create_u32("qdss", 0600, debugfs_root,
  135. (u32 *)&sde_kms->qdss_enabled);
  136. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  137. (u32 *)&sde_kms->pm_suspend_clk_dump);
  138. return 0;
  139. }
  140. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  141. {
  142. struct sde_kms *sde_kms = to_sde_kms(kms);
  143. /* don't need to NULL check debugfs_root */
  144. if (sde_kms) {
  145. sde_debugfs_vbif_destroy(sde_kms);
  146. sde_debugfs_core_irq_destroy(sde_kms);
  147. }
  148. }
  149. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  150. {
  151. int i;
  152. struct device *dev = sde_kms->dev->dev;
  153. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  154. for (i = 0; i < sde_kms->dsi_display_count; i++)
  155. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  156. return 0;
  157. }
  158. #else
  159. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  160. {
  161. return 0;
  162. }
  163. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  164. {
  165. }
  166. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  167. {
  168. return 0;
  169. }
  170. #endif
  171. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  172. struct drm_crtc *crtc)
  173. {
  174. struct drm_encoder *encoder;
  175. struct drm_device *dev;
  176. int ret;
  177. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  178. SDE_ERROR("invalid params\n");
  179. return;
  180. }
  181. if (!crtc->state->enable) {
  182. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  183. return;
  184. }
  185. if (!crtc->state->active) {
  186. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  187. return;
  188. }
  189. dev = crtc->dev;
  190. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  191. if (encoder->crtc != crtc)
  192. continue;
  193. /*
  194. * Video Mode - Wait for VSYNC
  195. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  196. * complete
  197. */
  198. SDE_EVT32_VERBOSE(DRMID(crtc));
  199. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  200. if (ret && ret != -EWOULDBLOCK) {
  201. SDE_ERROR(
  202. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  203. crtc->base.id, encoder->base.id, ret);
  204. break;
  205. }
  206. }
  207. }
  208. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  209. struct drm_crtc *crtc, bool enable)
  210. {
  211. struct drm_device *dev;
  212. struct msm_drm_private *priv;
  213. struct sde_mdss_cfg *sde_cfg;
  214. struct drm_plane *plane;
  215. int i, ret;
  216. dev = sde_kms->dev;
  217. priv = dev->dev_private;
  218. sde_cfg = sde_kms->catalog;
  219. ret = sde_vbif_halt_xin_mask(sde_kms,
  220. sde_cfg->sui_block_xin_mask, enable);
  221. if (ret) {
  222. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  223. return ret;
  224. }
  225. if (enable) {
  226. for (i = 0; i < priv->num_planes; i++) {
  227. plane = priv->planes[i];
  228. sde_plane_secure_ctrl_xin_client(plane, crtc);
  229. }
  230. }
  231. return 0;
  232. }
  233. /**
  234. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  235. * @sde_kms: Pointer to sde_kms struct
  236. * @vimd: switch the stage 2 translation to this VMID
  237. */
  238. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  239. {
  240. struct device dummy = {};
  241. dma_addr_t dma_handle;
  242. uint32_t num_sids;
  243. uint32_t *sec_sid;
  244. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  245. int ret = 0, i;
  246. struct qtee_shm shm;
  247. bool qtee_en = qtee_shmbridge_is_enabled();
  248. phys_addr_t mem_addr;
  249. u64 mem_size;
  250. num_sids = sde_cfg->sec_sid_mask_count;
  251. if (!num_sids) {
  252. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  253. return -EINVAL;
  254. }
  255. if (qtee_en) {
  256. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  257. &shm);
  258. if (ret)
  259. return -ENOMEM;
  260. sec_sid = (uint32_t *) shm.vaddr;
  261. mem_addr = shm.paddr;
  262. /**
  263. * SMMUSecureModeSwitch requires the size to be number of SID's
  264. * but shm allocates size in pages. Modify the args as per
  265. * client requirement.
  266. */
  267. mem_size = sizeof(uint32_t) * num_sids;
  268. } else {
  269. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  270. if (!sec_sid)
  271. return -ENOMEM;
  272. mem_addr = virt_to_phys(sec_sid);
  273. mem_size = sizeof(uint32_t) * num_sids;
  274. }
  275. for (i = 0; i < num_sids; i++) {
  276. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  277. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  278. }
  279. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  280. if (ret) {
  281. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  282. goto map_error;
  283. }
  284. set_dma_ops(&dummy, NULL);
  285. dma_handle = dma_map_single(&dummy, sec_sid,
  286. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  287. if (dma_mapping_error(&dummy, dma_handle)) {
  288. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  289. vmid);
  290. goto map_error;
  291. }
  292. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  293. vmid, num_sids, qtee_en);
  294. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  295. mem_size, vmid);
  296. if (ret)
  297. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  298. vmid, ret);
  299. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  300. vmid, qtee_en, num_sids, ret);
  301. dma_unmap_single(&dummy, dma_handle,
  302. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  303. map_error:
  304. if (qtee_en)
  305. qtee_shmbridge_free_shm(&shm);
  306. else
  307. kfree(sec_sid);
  308. return ret;
  309. }
  310. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  311. {
  312. u32 ret;
  313. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  314. return 0;
  315. /* detach_all_contexts */
  316. ret = sde_kms_mmu_detach(sde_kms, false);
  317. if (ret) {
  318. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  319. goto mmu_error;
  320. }
  321. ret = _sde_kms_scm_call(sde_kms, vmid);
  322. if (ret) {
  323. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  324. goto scm_error;
  325. }
  326. return 0;
  327. scm_error:
  328. sde_kms_mmu_attach(sde_kms, false);
  329. mmu_error:
  330. atomic_dec(&sde_kms->detach_all_cb);
  331. return ret;
  332. }
  333. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  334. u32 old_vmid)
  335. {
  336. u32 ret;
  337. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  338. return 0;
  339. ret = _sde_kms_scm_call(sde_kms, vmid);
  340. if (ret) {
  341. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  342. goto scm_error;
  343. }
  344. /* attach_all_contexts */
  345. ret = sde_kms_mmu_attach(sde_kms, false);
  346. if (ret) {
  347. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  348. goto mmu_error;
  349. }
  350. return 0;
  351. mmu_error:
  352. _sde_kms_scm_call(sde_kms, old_vmid);
  353. scm_error:
  354. atomic_inc(&sde_kms->detach_all_cb);
  355. return ret;
  356. }
  357. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  358. {
  359. u32 ret;
  360. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  361. return 0;
  362. /* detach secure_context */
  363. ret = sde_kms_mmu_detach(sde_kms, true);
  364. if (ret) {
  365. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  366. goto mmu_error;
  367. }
  368. ret = _sde_kms_scm_call(sde_kms, vmid);
  369. if (ret) {
  370. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  371. goto scm_error;
  372. }
  373. return 0;
  374. scm_error:
  375. sde_kms_mmu_attach(sde_kms, true);
  376. mmu_error:
  377. atomic_dec(&sde_kms->detach_sec_cb);
  378. return ret;
  379. }
  380. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  381. u32 old_vmid)
  382. {
  383. u32 ret;
  384. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  385. return 0;
  386. ret = _sde_kms_scm_call(sde_kms, vmid);
  387. if (ret) {
  388. goto scm_error;
  389. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  390. }
  391. ret = sde_kms_mmu_attach(sde_kms, true);
  392. if (ret) {
  393. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  394. goto mmu_error;
  395. }
  396. return 0;
  397. mmu_error:
  398. _sde_kms_scm_call(sde_kms, old_vmid);
  399. scm_error:
  400. atomic_inc(&sde_kms->detach_sec_cb);
  401. return ret;
  402. }
  403. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  404. struct drm_crtc *crtc, bool enable)
  405. {
  406. int ret;
  407. if (enable) {
  408. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  409. if (ret < 0) {
  410. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  411. return ret;
  412. }
  413. sde_crtc_misr_setup(crtc, true, 1);
  414. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  415. if (ret) {
  416. sde_crtc_misr_setup(crtc, false, 0);
  417. pm_runtime_put_sync(sde_kms->dev->dev);
  418. return ret;
  419. }
  420. } else {
  421. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  422. sde_crtc_misr_setup(crtc, false, 0);
  423. pm_runtime_put_sync(sde_kms->dev->dev);
  424. }
  425. return 0;
  426. }
  427. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  428. bool post_commit)
  429. {
  430. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  431. int old_smmu_state = smmu_state->state;
  432. int ret = 0;
  433. u32 vmid;
  434. if (!sde_kms || !crtc) {
  435. SDE_ERROR("invalid argument(s)\n");
  436. return -EINVAL;
  437. }
  438. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  439. post_commit, smmu_state->sui_misr_state,
  440. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  441. if ((!smmu_state->transition_type) ||
  442. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  443. /* Bail out */
  444. return 0;
  445. /* enable sui misr if requested, before the transition */
  446. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  447. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  448. if (ret) {
  449. smmu_state->sui_misr_state = NONE;
  450. goto end;
  451. }
  452. }
  453. mutex_lock(&sde_kms->secure_transition_lock);
  454. switch (smmu_state->state) {
  455. case DETACH_ALL_REQ:
  456. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  457. if (!ret)
  458. smmu_state->state = DETACHED;
  459. break;
  460. case ATTACH_ALL_REQ:
  461. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  462. VMID_CP_SEC_DISPLAY);
  463. if (!ret) {
  464. smmu_state->state = ATTACHED;
  465. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  466. }
  467. break;
  468. case DETACH_SEC_REQ:
  469. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  470. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  471. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  472. if (!ret)
  473. smmu_state->state = DETACHED_SEC;
  474. break;
  475. case ATTACH_SEC_REQ:
  476. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  477. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  478. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  479. if (!ret) {
  480. smmu_state->state = ATTACHED;
  481. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  482. }
  483. break;
  484. default:
  485. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  486. DRMID(crtc), smmu_state->state,
  487. smmu_state->transition_type);
  488. ret = -EINVAL;
  489. break;
  490. }
  491. mutex_unlock(&sde_kms->secure_transition_lock);
  492. /* disable sui misr if requested, after the transition */
  493. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  494. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  495. if (ret)
  496. goto end;
  497. }
  498. end:
  499. smmu_state->transition_error = false;
  500. if (ret) {
  501. smmu_state->transition_error = true;
  502. SDE_ERROR(
  503. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  504. DRMID(crtc), old_smmu_state, smmu_state->state,
  505. smmu_state->secure_level, ret);
  506. smmu_state->state = smmu_state->prev_state;
  507. smmu_state->secure_level = smmu_state->prev_secure_level;
  508. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  509. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  510. }
  511. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  512. DRMID(crtc), old_smmu_state, smmu_state->state,
  513. smmu_state->secure_level, ret);
  514. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  515. smmu_state->transition_type,
  516. smmu_state->transition_error,
  517. smmu_state->secure_level, smmu_state->prev_secure_level,
  518. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  519. smmu_state->sui_misr_state = NONE;
  520. smmu_state->transition_type = NONE;
  521. return ret;
  522. }
  523. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  524. struct drm_atomic_state *state)
  525. {
  526. struct drm_crtc *crtc;
  527. struct drm_crtc_state *old_crtc_state;
  528. struct drm_plane_state *old_plane_state, *new_plane_state;
  529. struct drm_plane *plane;
  530. struct drm_plane_state *plane_state;
  531. struct sde_kms *sde_kms = to_sde_kms(kms);
  532. struct drm_device *dev = sde_kms->dev;
  533. int i, ops = 0, ret = 0;
  534. bool old_valid_fb = false;
  535. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  536. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  537. if (!crtc->state || !crtc->state->active)
  538. continue;
  539. /*
  540. * It is safe to assume only one active crtc,
  541. * and compatible translation modes on the
  542. * planes staged on this crtc.
  543. * otherwise validation would have failed.
  544. * For this CRTC,
  545. */
  546. /*
  547. * 1. Check if old state on the CRTC has planes
  548. * staged with valid fbs
  549. */
  550. for_each_old_plane_in_state(state, plane, plane_state, i) {
  551. if (!plane_state->crtc)
  552. continue;
  553. if (plane_state->fb) {
  554. old_valid_fb = true;
  555. break;
  556. }
  557. }
  558. /*
  559. * 2.Get the operations needed to be performed before
  560. * secure transition can be initiated.
  561. */
  562. ops = sde_crtc_get_secure_transition_ops(crtc,
  563. old_crtc_state, old_valid_fb);
  564. if (ops < 0) {
  565. SDE_ERROR("invalid secure operations %x\n", ops);
  566. return ops;
  567. }
  568. if (!ops) {
  569. smmu_state->transition_error = false;
  570. goto no_ops;
  571. }
  572. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  573. crtc->base.id, ops, crtc->state);
  574. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  575. /* 3. Perform operations needed for secure transition */
  576. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  577. SDE_DEBUG("wait_for_transfer_done\n");
  578. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  579. }
  580. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  581. SDE_DEBUG("cleanup planes\n");
  582. drm_atomic_helper_cleanup_planes(dev, state);
  583. for_each_oldnew_plane_in_state(state, plane,
  584. old_plane_state, new_plane_state, i)
  585. sde_plane_destroy_fb(old_plane_state);
  586. }
  587. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  588. SDE_DEBUG("secure ctrl\n");
  589. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  590. }
  591. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  592. SDE_DEBUG("prepare planes %d",
  593. crtc->state->plane_mask);
  594. drm_atomic_crtc_for_each_plane(plane,
  595. crtc) {
  596. const struct drm_plane_helper_funcs *funcs;
  597. plane_state = plane->state;
  598. funcs = plane->helper_private;
  599. SDE_DEBUG("psde:%d FB[%u]\n",
  600. plane->base.id,
  601. plane->fb->base.id);
  602. if (!funcs)
  603. continue;
  604. if (funcs->prepare_fb(plane, plane_state)) {
  605. ret = funcs->prepare_fb(plane,
  606. plane_state);
  607. if (ret)
  608. return ret;
  609. }
  610. }
  611. }
  612. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  613. SDE_DEBUG("secure operations completed\n");
  614. }
  615. no_ops:
  616. return 0;
  617. }
  618. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  619. unsigned int splash_buffer_size,
  620. unsigned int ramdump_base,
  621. unsigned int ramdump_buffer_size)
  622. {
  623. unsigned long pfn_start, pfn_end, pfn_idx;
  624. int ret = 0;
  625. if (!mem_addr || !splash_buffer_size) {
  626. SDE_ERROR("invalid params\n");
  627. return -EINVAL;
  628. }
  629. /* leave ramdump memory only if base address matches */
  630. if (ramdump_base == mem_addr &&
  631. ramdump_buffer_size <= splash_buffer_size) {
  632. mem_addr += ramdump_buffer_size;
  633. splash_buffer_size -= ramdump_buffer_size;
  634. }
  635. pfn_start = mem_addr >> PAGE_SHIFT;
  636. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  637. ret = memblock_free(mem_addr, splash_buffer_size);
  638. if (ret) {
  639. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  640. return ret;
  641. }
  642. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  643. free_reserved_page(pfn_to_page(pfn_idx));
  644. return ret;
  645. }
  646. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  647. struct sde_splash_mem *splash)
  648. {
  649. struct msm_mmu *mmu = NULL;
  650. int ret = 0;
  651. if (!sde_kms->aspace[0]) {
  652. SDE_ERROR("aspace not found for sde kms node\n");
  653. return -EINVAL;
  654. }
  655. mmu = sde_kms->aspace[0]->mmu;
  656. if (!mmu) {
  657. SDE_ERROR("mmu not found for aspace\n");
  658. return -EINVAL;
  659. }
  660. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  661. SDE_ERROR("invalid input params for map\n");
  662. return -EINVAL;
  663. }
  664. if (!splash->ref_cnt) {
  665. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  666. splash->splash_buf_base,
  667. splash->splash_buf_size,
  668. IOMMU_READ | IOMMU_NOEXEC);
  669. if (ret)
  670. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  671. }
  672. splash->ref_cnt++;
  673. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  674. splash->splash_buf_base,
  675. splash->splash_buf_size,
  676. splash->ref_cnt);
  677. return ret;
  678. }
  679. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  680. {
  681. int i = 0;
  682. int ret = 0;
  683. if (!sde_kms)
  684. return -EINVAL;
  685. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  686. ret = _sde_kms_splash_mem_get(sde_kms,
  687. sde_kms->splash_data.splash_display[i].splash);
  688. if (ret)
  689. return ret;
  690. }
  691. return ret;
  692. }
  693. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  694. struct sde_splash_mem *splash)
  695. {
  696. struct msm_mmu *mmu = NULL;
  697. int rc = 0;
  698. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  699. SDE_ERROR("invalid params\n");
  700. return -EINVAL;
  701. }
  702. mmu = sde_kms->aspace[0]->mmu;
  703. if (!splash || !splash->ref_cnt ||
  704. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  705. return -EINVAL;
  706. splash->ref_cnt--;
  707. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  708. splash->splash_buf_base, splash->ref_cnt);
  709. if (!splash->ref_cnt) {
  710. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  711. splash->splash_buf_size);
  712. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  713. splash->splash_buf_size, splash->ramdump_base,
  714. splash->ramdump_size);
  715. splash->splash_buf_base = 0;
  716. splash->splash_buf_size = 0;
  717. }
  718. return rc;
  719. }
  720. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  721. {
  722. int i = 0;
  723. int ret = 0;
  724. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  725. return -EINVAL;
  726. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  727. ret = _sde_kms_splash_mem_put(sde_kms,
  728. sde_kms->splash_data.splash_display[i].splash);
  729. if (ret)
  730. return ret;
  731. }
  732. return ret;
  733. }
  734. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  735. struct drm_connector_state *conn_state)
  736. {
  737. int lp_mode, blank;
  738. if (crtc_state->active)
  739. lp_mode = sde_connector_get_property(conn_state,
  740. CONNECTOR_PROP_LP);
  741. else
  742. lp_mode = SDE_MODE_DPMS_OFF;
  743. switch (lp_mode) {
  744. case SDE_MODE_DPMS_ON:
  745. blank = DRM_PANEL_BLANK_UNBLANK;
  746. break;
  747. case SDE_MODE_DPMS_LP1:
  748. case SDE_MODE_DPMS_LP2:
  749. blank = DRM_PANEL_BLANK_LP;
  750. break;
  751. case SDE_MODE_DPMS_OFF:
  752. default:
  753. blank = DRM_PANEL_BLANK_POWERDOWN;
  754. break;
  755. }
  756. return blank;
  757. }
  758. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  759. unsigned long event)
  760. {
  761. struct drm_connector *connector;
  762. struct drm_connector_state *old_conn_state;
  763. struct drm_crtc_state *old_crtc_state;
  764. struct drm_crtc *crtc;
  765. struct sde_connector *c_conn;
  766. int i, old_mode, new_mode, old_fps, new_fps;
  767. for_each_old_connector_in_state(old_state, connector,
  768. old_conn_state, i) {
  769. crtc = connector->state->crtc ? connector->state->crtc :
  770. old_conn_state->crtc;
  771. if (!crtc)
  772. continue;
  773. new_fps = drm_mode_vrefresh(&crtc->state->mode);
  774. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  775. if (old_conn_state->crtc) {
  776. old_crtc_state = drm_atomic_get_existing_crtc_state(
  777. old_state, old_conn_state->crtc);
  778. old_fps = drm_mode_vrefresh(&old_crtc_state->mode);
  779. old_mode = _sde_kms_get_blank(old_crtc_state,
  780. old_conn_state);
  781. } else {
  782. old_fps = 0;
  783. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  784. }
  785. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  786. c_conn = to_sde_connector(connector);
  787. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  788. c_conn->panel, crtc->state->active,
  789. old_conn_state->crtc, event);
  790. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  791. old_mode, new_mode, old_fps, new_fps);
  792. /* If suspend resume and fps change are happening
  793. * at the same time, give preference to power mode
  794. * changes rather than fps change.
  795. */
  796. if ((old_mode == new_mode) && (old_fps != new_fps))
  797. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  798. }
  799. }
  800. }
  801. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  802. struct drm_atomic_state *state)
  803. {
  804. int i;
  805. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  806. struct drm_crtc *crtc, *vm_crtc = NULL;
  807. struct drm_crtc_state *new_cstate, *old_cstate;
  808. struct sde_crtc_state *vm_cstate;
  809. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  810. if (!new_cstate->active && !old_cstate->active)
  811. continue;
  812. vm_cstate = to_sde_crtc_state(new_cstate);
  813. vm_req = sde_crtc_get_property(vm_cstate,
  814. CRTC_PROP_VM_REQ_STATE);
  815. if (vm_req != VM_REQ_NONE) {
  816. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  817. vm_req, crtc->base.id);
  818. vm_crtc = crtc;
  819. break;
  820. }
  821. }
  822. return vm_crtc;
  823. }
  824. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  825. struct drm_atomic_state *state)
  826. {
  827. struct drm_device *ddev;
  828. struct drm_crtc *crtc;
  829. struct drm_crtc_state *new_cstate;
  830. struct drm_encoder *encoder;
  831. struct drm_connector *connector;
  832. struct sde_vm_ops *vm_ops;
  833. struct sde_crtc_state *cstate;
  834. enum sde_crtc_vm_req vm_req;
  835. int rc = 0;
  836. ddev = sde_kms->dev;
  837. vm_ops = sde_vm_get_ops(sde_kms);
  838. if (!vm_ops)
  839. return -EINVAL;
  840. crtc = sde_kms_vm_get_vm_crtc(state);
  841. if (!crtc)
  842. return 0;
  843. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  844. cstate = to_sde_crtc_state(new_cstate);
  845. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  846. if (vm_req != VM_REQ_ACQUIRE)
  847. return 0;
  848. /* enable MDSS irq line */
  849. sde_irq_update(&sde_kms->base, true);
  850. /* clear the stale IRQ status bits */
  851. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  852. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  853. /* enable the display path IRQ's */
  854. drm_for_each_encoder_mask(encoder, crtc->dev,
  855. crtc->state->encoder_mask) {
  856. if (sde_encoder_in_clone_mode(encoder))
  857. continue;
  858. sde_encoder_irq_control(encoder, true);
  859. }
  860. /* Schedule ESD work */
  861. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  862. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  863. sde_connector_schedule_status_work(connector, true);
  864. /* enable vblank events */
  865. drm_crtc_vblank_on(crtc);
  866. /* handle non-SDE pre_acquire */
  867. if (vm_ops->vm_client_post_acquire)
  868. rc = vm_ops->vm_client_post_acquire(sde_kms);
  869. return rc;
  870. }
  871. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  872. struct drm_atomic_state *state)
  873. {
  874. struct drm_device *ddev;
  875. struct drm_plane *plane;
  876. struct drm_crtc *crtc;
  877. struct drm_crtc_state *new_cstate;
  878. struct sde_crtc_state *cstate;
  879. enum sde_crtc_vm_req vm_req;
  880. ddev = sde_kms->dev;
  881. crtc = sde_kms_vm_get_vm_crtc(state);
  882. if (!crtc)
  883. return 0;
  884. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  885. cstate = to_sde_crtc_state(new_cstate);
  886. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  887. if (vm_req != VM_REQ_ACQUIRE)
  888. return 0;
  889. /* Clear the stale IRQ status bits */
  890. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  891. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  892. /* Program the SID's for the trusted VM */
  893. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  894. sde_plane_set_sid(plane, 1);
  895. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  896. return 0;
  897. }
  898. static void sde_kms_prepare_commit(struct msm_kms *kms,
  899. struct drm_atomic_state *state)
  900. {
  901. struct sde_kms *sde_kms;
  902. struct msm_drm_private *priv;
  903. struct drm_device *dev;
  904. struct drm_encoder *encoder;
  905. struct drm_crtc *crtc;
  906. struct drm_crtc_state *crtc_state;
  907. struct sde_vm_ops *vm_ops;
  908. int i, rc;
  909. if (!kms)
  910. return;
  911. sde_kms = to_sde_kms(kms);
  912. dev = sde_kms->dev;
  913. if (!dev || !dev->dev_private)
  914. return;
  915. priv = dev->dev_private;
  916. SDE_ATRACE_BEGIN("prepare_commit");
  917. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  918. if (rc < 0) {
  919. SDE_ERROR("failed to enable power resources %d\n", rc);
  920. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  921. goto end;
  922. }
  923. if (sde_kms->first_kickoff) {
  924. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  925. sde_kms->first_kickoff = false;
  926. }
  927. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  928. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  929. head) {
  930. if (encoder->crtc != crtc)
  931. continue;
  932. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  933. SDE_ERROR("crtc:%d, initiating hw reset\n",
  934. DRMID(crtc));
  935. sde_encoder_needs_hw_reset(encoder);
  936. sde_crtc_set_needs_hw_reset(crtc);
  937. }
  938. }
  939. }
  940. /*
  941. * NOTE: for secure use cases we want to apply the new HW
  942. * configuration only after completing preparation for secure
  943. * transitions prepare below if any transtions is required.
  944. */
  945. sde_kms_prepare_secure_transition(kms, state);
  946. vm_ops = sde_vm_get_ops(sde_kms);
  947. if (!vm_ops)
  948. goto end_vm;
  949. if (vm_ops->vm_prepare_commit)
  950. vm_ops->vm_prepare_commit(sde_kms, state);
  951. end_vm:
  952. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  953. end:
  954. SDE_ATRACE_END("prepare_commit");
  955. }
  956. static void sde_kms_commit(struct msm_kms *kms,
  957. struct drm_atomic_state *old_state)
  958. {
  959. struct sde_kms *sde_kms;
  960. struct drm_crtc *crtc;
  961. struct drm_crtc_state *old_crtc_state;
  962. int i;
  963. if (!kms || !old_state)
  964. return;
  965. sde_kms = to_sde_kms(kms);
  966. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  967. SDE_ERROR("power resource is not enabled\n");
  968. return;
  969. }
  970. SDE_ATRACE_BEGIN("sde_kms_commit");
  971. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  972. if (crtc->state->active) {
  973. SDE_EVT32(DRMID(crtc), old_state);
  974. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  975. }
  976. }
  977. SDE_ATRACE_END("sde_kms_commit");
  978. }
  979. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  980. struct sde_splash_display *splash_display)
  981. {
  982. if (!sde_kms || !splash_display ||
  983. !sde_kms->splash_data.num_splash_displays)
  984. return;
  985. if (sde_kms->splash_data.num_splash_regions)
  986. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  987. sde_kms->splash_data.num_splash_displays--;
  988. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  989. sde_kms->splash_data.num_splash_displays);
  990. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  991. }
  992. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  993. struct drm_crtc *crtc)
  994. {
  995. struct msm_drm_private *priv;
  996. struct sde_splash_display *splash_display;
  997. int i;
  998. if (!sde_kms || !crtc)
  999. return;
  1000. priv = sde_kms->dev->dev_private;
  1001. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1002. return;
  1003. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1004. sde_kms->splash_data.num_splash_displays);
  1005. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1006. splash_display = &sde_kms->splash_data.splash_display[i];
  1007. if (splash_display->encoder &&
  1008. crtc == splash_display->encoder->crtc)
  1009. break;
  1010. }
  1011. if (i >= MAX_DSI_DISPLAYS)
  1012. return;
  1013. if (splash_display->cont_splash_enabled) {
  1014. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1015. splash_display, false);
  1016. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1017. }
  1018. /* remove the votes if all displays are done with splash */
  1019. if (!sde_kms->splash_data.num_splash_displays) {
  1020. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1021. sde_power_data_bus_set_quota(&priv->phandle, i,
  1022. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1023. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1024. pm_runtime_put_sync(sde_kms->dev->dev);
  1025. }
  1026. }
  1027. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1028. struct drm_atomic_state *state)
  1029. {
  1030. struct sde_vm_ops *vm_ops;
  1031. struct drm_device *ddev;
  1032. struct drm_crtc *crtc;
  1033. struct drm_plane *plane;
  1034. struct drm_encoder *encoder;
  1035. struct sde_crtc_state *cstate;
  1036. struct drm_crtc_state *new_cstate;
  1037. enum sde_crtc_vm_req vm_req;
  1038. int rc = 0;
  1039. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1040. return -EINVAL;
  1041. vm_ops = sde_vm_get_ops(sde_kms);
  1042. ddev = sde_kms->dev;
  1043. crtc = sde_kms_vm_get_vm_crtc(state);
  1044. if (!crtc)
  1045. return 0;
  1046. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1047. cstate = to_sde_crtc_state(new_cstate);
  1048. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1049. if (vm_req != VM_REQ_RELEASE)
  1050. return 0;
  1051. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1052. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1053. drm_for_each_encoder_mask(encoder, crtc->dev,
  1054. crtc->state->encoder_mask) {
  1055. if (sde_encoder_in_clone_mode(encoder))
  1056. continue;
  1057. sde_encoder_irq_control(encoder, false);
  1058. }
  1059. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1060. sde_plane_set_sid(plane, 0);
  1061. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1062. sde_vm_lock(sde_kms);
  1063. if (vm_ops->vm_release)
  1064. rc = vm_ops->vm_release(sde_kms);
  1065. sde_vm_unlock(sde_kms);
  1066. return rc;
  1067. }
  1068. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1069. struct drm_atomic_state *state)
  1070. {
  1071. struct drm_device *ddev;
  1072. struct drm_crtc *crtc;
  1073. struct drm_encoder *encoder;
  1074. struct drm_connector *connector;
  1075. int rc = 0;
  1076. ddev = sde_kms->dev;
  1077. crtc = sde_kms_vm_get_vm_crtc(state);
  1078. if (!crtc)
  1079. return 0;
  1080. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1081. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1082. /* disable ESD work */
  1083. list_for_each_entry(connector,
  1084. &ddev->mode_config.connector_list, head) {
  1085. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1086. sde_connector_schedule_status_work(connector, false);
  1087. }
  1088. /* disable SDE irq's */
  1089. drm_for_each_encoder_mask(encoder, crtc->dev,
  1090. crtc->state->encoder_mask) {
  1091. if (sde_encoder_in_clone_mode(encoder))
  1092. continue;
  1093. sde_encoder_irq_control(encoder, false);
  1094. }
  1095. /* disable IRQ line */
  1096. sde_irq_update(&sde_kms->base, false);
  1097. /* disable vblank events */
  1098. drm_crtc_vblank_off(crtc);
  1099. /* reset sw state */
  1100. sde_crtc_reset_sw_state(crtc);
  1101. return rc;
  1102. }
  1103. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1104. struct drm_atomic_state *state)
  1105. {
  1106. struct sde_vm_ops *vm_ops;
  1107. struct sde_crtc_state *cstate;
  1108. struct drm_crtc *crtc;
  1109. struct drm_crtc_state *new_cstate;
  1110. enum sde_crtc_vm_req vm_req;
  1111. int rc = 0;
  1112. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1113. return -EINVAL;
  1114. vm_ops = sde_vm_get_ops(sde_kms);
  1115. crtc = sde_kms_vm_get_vm_crtc(state);
  1116. if (!crtc)
  1117. return 0;
  1118. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1119. cstate = to_sde_crtc_state(new_cstate);
  1120. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1121. if (vm_req != VM_REQ_RELEASE)
  1122. return 0;
  1123. /* handle SDE pre-release */
  1124. rc = sde_kms_vm_pre_release(sde_kms, state);
  1125. if (rc) {
  1126. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1127. goto exit;
  1128. }
  1129. /* properly handoff color processing features */
  1130. sde_cp_crtc_vm_primary_handoff(crtc);
  1131. /* handle non-SDE clients pre-release */
  1132. if (vm_ops->vm_client_pre_release) {
  1133. rc = vm_ops->vm_client_pre_release(sde_kms);
  1134. if (rc) {
  1135. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1136. rc);
  1137. goto exit;
  1138. }
  1139. }
  1140. sde_vm_lock(sde_kms);
  1141. /* release HW */
  1142. if (vm_ops->vm_release) {
  1143. rc = vm_ops->vm_release(sde_kms);
  1144. if (rc)
  1145. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1146. }
  1147. sde_vm_unlock(sde_kms);
  1148. exit:
  1149. return rc;
  1150. }
  1151. static void sde_kms_complete_commit(struct msm_kms *kms,
  1152. struct drm_atomic_state *old_state)
  1153. {
  1154. struct sde_kms *sde_kms;
  1155. struct msm_drm_private *priv;
  1156. struct drm_crtc *crtc;
  1157. struct drm_crtc_state *old_crtc_state;
  1158. struct drm_connector *connector;
  1159. struct drm_connector_state *old_conn_state;
  1160. struct msm_display_conn_params params;
  1161. struct sde_vm_ops *vm_ops;
  1162. int i, rc = 0;
  1163. if (!kms || !old_state)
  1164. return;
  1165. sde_kms = to_sde_kms(kms);
  1166. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1167. return;
  1168. priv = sde_kms->dev->dev_private;
  1169. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1170. SDE_ERROR("power resource is not enabled\n");
  1171. return;
  1172. }
  1173. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1174. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1175. sde_crtc_complete_commit(crtc, old_crtc_state);
  1176. /* complete secure transitions if any */
  1177. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1178. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1179. }
  1180. for_each_old_connector_in_state(old_state, connector,
  1181. old_conn_state, i) {
  1182. struct sde_connector *c_conn;
  1183. c_conn = to_sde_connector(connector);
  1184. if (!c_conn->ops.post_kickoff)
  1185. continue;
  1186. memset(&params, 0, sizeof(params));
  1187. sde_connector_complete_qsync_commit(connector, &params);
  1188. rc = c_conn->ops.post_kickoff(connector, &params);
  1189. if (rc) {
  1190. pr_err("Connector Post kickoff failed rc=%d\n",
  1191. rc);
  1192. }
  1193. }
  1194. vm_ops = sde_vm_get_ops(sde_kms);
  1195. if (vm_ops && vm_ops->vm_post_commit) {
  1196. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1197. if (rc)
  1198. SDE_ERROR("vm post commit failed, rc = %d\n",
  1199. rc);
  1200. }
  1201. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1202. pm_runtime_put_sync(sde_kms->dev->dev);
  1203. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1204. _sde_kms_release_splash_resource(sde_kms, crtc);
  1205. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1206. SDE_ATRACE_END("sde_kms_complete_commit");
  1207. }
  1208. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1209. struct drm_crtc *crtc)
  1210. {
  1211. struct drm_encoder *encoder;
  1212. struct drm_device *dev;
  1213. int ret;
  1214. bool cwb_disabling;
  1215. if (!kms || !crtc || !crtc->state) {
  1216. SDE_ERROR("invalid params\n");
  1217. return;
  1218. }
  1219. dev = crtc->dev;
  1220. if (!crtc->state->enable) {
  1221. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1222. return;
  1223. }
  1224. if (!crtc->state->active) {
  1225. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1226. return;
  1227. }
  1228. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1229. SDE_ERROR("power resource is not enabled\n");
  1230. return;
  1231. }
  1232. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1233. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1234. cwb_disabling = false;
  1235. if (encoder->crtc != crtc) {
  1236. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1237. crtc);
  1238. if (!cwb_disabling)
  1239. continue;
  1240. }
  1241. /*
  1242. * Wait for post-flush if necessary to delay before
  1243. * plane_cleanup. For example, wait for vsync in case of video
  1244. * mode panels. This may be a no-op for command mode panels.
  1245. */
  1246. SDE_EVT32_VERBOSE(DRMID(crtc));
  1247. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1248. if (ret && ret != -EWOULDBLOCK) {
  1249. SDE_ERROR("wait for commit done returned %d\n", ret);
  1250. sde_crtc_request_frame_reset(crtc);
  1251. break;
  1252. }
  1253. sde_crtc_complete_flip(crtc, NULL);
  1254. if (cwb_disabling)
  1255. sde_encoder_virt_reset(encoder);
  1256. }
  1257. sde_crtc_static_cache_read_kickoff(crtc);
  1258. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1259. }
  1260. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1261. struct drm_atomic_state *old_state)
  1262. {
  1263. struct drm_crtc *crtc;
  1264. struct drm_crtc_state *old_crtc_state;
  1265. int i, rc;
  1266. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1267. SDE_ERROR("invalid argument(s)\n");
  1268. return;
  1269. }
  1270. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1271. retry:
  1272. /* attempt to acquire ww mutex for connection */
  1273. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1274. old_state->acquire_ctx);
  1275. if (rc == -EDEADLK) {
  1276. drm_modeset_backoff(old_state->acquire_ctx);
  1277. goto retry;
  1278. }
  1279. /* old_state actually contains updated crtc pointers */
  1280. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1281. if (crtc->state->active || crtc->state->active_changed)
  1282. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1283. }
  1284. SDE_ATRACE_END("sde_kms_prepare_fence");
  1285. }
  1286. /**
  1287. * _sde_kms_get_displays - query for underlying display handles and cache them
  1288. * @sde_kms: Pointer to sde kms structure
  1289. * Returns: Zero on success
  1290. */
  1291. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1292. {
  1293. int rc = -ENOMEM;
  1294. if (!sde_kms) {
  1295. SDE_ERROR("invalid sde kms\n");
  1296. return -EINVAL;
  1297. }
  1298. /* dsi */
  1299. sde_kms->dsi_displays = NULL;
  1300. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1301. if (sde_kms->dsi_display_count) {
  1302. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1303. sizeof(void *),
  1304. GFP_KERNEL);
  1305. if (!sde_kms->dsi_displays) {
  1306. SDE_ERROR("failed to allocate dsi displays\n");
  1307. goto exit_deinit_dsi;
  1308. }
  1309. sde_kms->dsi_display_count =
  1310. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1311. sde_kms->dsi_display_count);
  1312. }
  1313. /* wb */
  1314. sde_kms->wb_displays = NULL;
  1315. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1316. if (sde_kms->wb_display_count) {
  1317. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1318. sizeof(void *),
  1319. GFP_KERNEL);
  1320. if (!sde_kms->wb_displays) {
  1321. SDE_ERROR("failed to allocate wb displays\n");
  1322. goto exit_deinit_wb;
  1323. }
  1324. sde_kms->wb_display_count =
  1325. wb_display_get_displays(sde_kms->wb_displays,
  1326. sde_kms->wb_display_count);
  1327. }
  1328. /* dp */
  1329. sde_kms->dp_displays = NULL;
  1330. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1331. if (sde_kms->dp_display_count) {
  1332. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1333. sizeof(void *), GFP_KERNEL);
  1334. if (!sde_kms->dp_displays) {
  1335. SDE_ERROR("failed to allocate dp displays\n");
  1336. goto exit_deinit_dp;
  1337. }
  1338. sde_kms->dp_display_count =
  1339. dp_display_get_displays(sde_kms->dp_displays,
  1340. sde_kms->dp_display_count);
  1341. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1342. }
  1343. return 0;
  1344. exit_deinit_dp:
  1345. kfree(sde_kms->dp_displays);
  1346. sde_kms->dp_stream_count = 0;
  1347. sde_kms->dp_display_count = 0;
  1348. sde_kms->dp_displays = NULL;
  1349. exit_deinit_wb:
  1350. kfree(sde_kms->wb_displays);
  1351. sde_kms->wb_display_count = 0;
  1352. sde_kms->wb_displays = NULL;
  1353. exit_deinit_dsi:
  1354. kfree(sde_kms->dsi_displays);
  1355. sde_kms->dsi_display_count = 0;
  1356. sde_kms->dsi_displays = NULL;
  1357. return rc;
  1358. }
  1359. /**
  1360. * _sde_kms_release_displays - release cache of underlying display handles
  1361. * @sde_kms: Pointer to sde kms structure
  1362. */
  1363. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1364. {
  1365. if (!sde_kms) {
  1366. SDE_ERROR("invalid sde kms\n");
  1367. return;
  1368. }
  1369. kfree(sde_kms->wb_displays);
  1370. sde_kms->wb_displays = NULL;
  1371. sde_kms->wb_display_count = 0;
  1372. kfree(sde_kms->dsi_displays);
  1373. sde_kms->dsi_displays = NULL;
  1374. sde_kms->dsi_display_count = 0;
  1375. }
  1376. /**
  1377. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1378. * for underlying displays
  1379. * @dev: Pointer to drm device structure
  1380. * @priv: Pointer to private drm device data
  1381. * @sde_kms: Pointer to sde kms structure
  1382. * Returns: Zero on success
  1383. */
  1384. static int _sde_kms_setup_displays(struct drm_device *dev,
  1385. struct msm_drm_private *priv,
  1386. struct sde_kms *sde_kms)
  1387. {
  1388. static const struct sde_connector_ops dsi_ops = {
  1389. .set_info_blob = dsi_conn_set_info_blob,
  1390. .detect = dsi_conn_detect,
  1391. .get_modes = dsi_connector_get_modes,
  1392. .pre_destroy = dsi_connector_put_modes,
  1393. .mode_valid = dsi_conn_mode_valid,
  1394. .get_info = dsi_display_get_info,
  1395. .set_backlight = dsi_display_set_backlight,
  1396. .soft_reset = dsi_display_soft_reset,
  1397. .pre_kickoff = dsi_conn_pre_kickoff,
  1398. .clk_ctrl = dsi_display_clk_ctrl,
  1399. .set_power = dsi_display_set_power,
  1400. .get_mode_info = dsi_conn_get_mode_info,
  1401. .get_dst_format = dsi_display_get_dst_format,
  1402. .post_kickoff = dsi_conn_post_kickoff,
  1403. .check_status = dsi_display_check_status,
  1404. .enable_event = dsi_conn_enable_event,
  1405. .cmd_transfer = dsi_display_cmd_transfer,
  1406. .cont_splash_config = dsi_display_cont_splash_config,
  1407. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1408. .get_panel_vfp = dsi_display_get_panel_vfp,
  1409. .get_default_lms = dsi_display_get_default_lms,
  1410. .cmd_receive = dsi_display_cmd_receive,
  1411. .install_properties = NULL,
  1412. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1413. .get_qsync_min_fps = dsi_display_get_qsync_min_fps,
  1414. .prepare_commit = dsi_conn_prepare_commit,
  1415. };
  1416. static const struct sde_connector_ops wb_ops = {
  1417. .post_init = sde_wb_connector_post_init,
  1418. .set_info_blob = sde_wb_connector_set_info_blob,
  1419. .detect = sde_wb_connector_detect,
  1420. .get_modes = sde_wb_connector_get_modes,
  1421. .set_property = sde_wb_connector_set_property,
  1422. .get_info = sde_wb_get_info,
  1423. .soft_reset = NULL,
  1424. .get_mode_info = sde_wb_get_mode_info,
  1425. .get_dst_format = NULL,
  1426. .check_status = NULL,
  1427. .cmd_transfer = NULL,
  1428. .cont_splash_config = NULL,
  1429. .cont_splash_res_disable = NULL,
  1430. .get_panel_vfp = NULL,
  1431. .cmd_receive = NULL,
  1432. .install_properties = NULL,
  1433. .set_allowed_mode_switch = NULL,
  1434. };
  1435. static const struct sde_connector_ops dp_ops = {
  1436. .post_init = dp_connector_post_init,
  1437. .detect = dp_connector_detect,
  1438. .get_modes = dp_connector_get_modes,
  1439. .atomic_check = dp_connector_atomic_check,
  1440. .mode_valid = dp_connector_mode_valid,
  1441. .get_info = dp_connector_get_info,
  1442. .get_mode_info = dp_connector_get_mode_info,
  1443. .post_open = dp_connector_post_open,
  1444. .check_status = NULL,
  1445. .set_colorspace = dp_connector_set_colorspace,
  1446. .config_hdr = dp_connector_config_hdr,
  1447. .cmd_transfer = NULL,
  1448. .cont_splash_config = NULL,
  1449. .cont_splash_res_disable = NULL,
  1450. .get_panel_vfp = NULL,
  1451. .update_pps = dp_connector_update_pps,
  1452. .cmd_receive = NULL,
  1453. .install_properties = dp_connector_install_properties,
  1454. .set_allowed_mode_switch = NULL,
  1455. };
  1456. struct msm_display_info info;
  1457. struct drm_encoder *encoder;
  1458. void *display, *connector;
  1459. int i, max_encoders;
  1460. int rc = 0;
  1461. u32 dsc_count = 0, mixer_count = 0;
  1462. u32 max_dp_dsc_count, max_dp_mixer_count;
  1463. if (!dev || !priv || !sde_kms) {
  1464. SDE_ERROR("invalid argument(s)\n");
  1465. return -EINVAL;
  1466. }
  1467. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1468. sde_kms->dp_display_count +
  1469. sde_kms->dp_stream_count;
  1470. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1471. max_encoders = ARRAY_SIZE(priv->encoders);
  1472. SDE_ERROR("capping number of displays to %d", max_encoders);
  1473. }
  1474. /* wb */
  1475. for (i = 0; i < sde_kms->wb_display_count &&
  1476. priv->num_encoders < max_encoders; ++i) {
  1477. display = sde_kms->wb_displays[i];
  1478. encoder = NULL;
  1479. memset(&info, 0x0, sizeof(info));
  1480. rc = sde_wb_get_info(NULL, &info, display);
  1481. if (rc) {
  1482. SDE_ERROR("wb get_info %d failed\n", i);
  1483. continue;
  1484. }
  1485. encoder = sde_encoder_init(dev, &info);
  1486. if (IS_ERR_OR_NULL(encoder)) {
  1487. SDE_ERROR("encoder init failed for wb %d\n", i);
  1488. continue;
  1489. }
  1490. rc = sde_wb_drm_init(display, encoder);
  1491. if (rc) {
  1492. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1493. sde_encoder_destroy(encoder);
  1494. continue;
  1495. }
  1496. connector = sde_connector_init(dev,
  1497. encoder,
  1498. 0,
  1499. display,
  1500. &wb_ops,
  1501. DRM_CONNECTOR_POLL_HPD,
  1502. DRM_MODE_CONNECTOR_VIRTUAL);
  1503. if (connector) {
  1504. priv->encoders[priv->num_encoders++] = encoder;
  1505. priv->connectors[priv->num_connectors++] = connector;
  1506. } else {
  1507. SDE_ERROR("wb %d connector init failed\n", i);
  1508. sde_wb_drm_deinit(display);
  1509. sde_encoder_destroy(encoder);
  1510. }
  1511. }
  1512. /* dsi */
  1513. for (i = 0; i < sde_kms->dsi_display_count &&
  1514. priv->num_encoders < max_encoders; ++i) {
  1515. display = sde_kms->dsi_displays[i];
  1516. encoder = NULL;
  1517. memset(&info, 0x0, sizeof(info));
  1518. rc = dsi_display_get_info(NULL, &info, display);
  1519. if (rc) {
  1520. SDE_ERROR("dsi get_info %d failed\n", i);
  1521. continue;
  1522. }
  1523. encoder = sde_encoder_init(dev, &info);
  1524. if (IS_ERR_OR_NULL(encoder)) {
  1525. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1526. continue;
  1527. }
  1528. rc = dsi_display_drm_bridge_init(display, encoder);
  1529. if (rc) {
  1530. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1531. sde_encoder_destroy(encoder);
  1532. continue;
  1533. }
  1534. connector = sde_connector_init(dev,
  1535. encoder,
  1536. dsi_display_get_drm_panel(display),
  1537. display,
  1538. &dsi_ops,
  1539. DRM_CONNECTOR_POLL_HPD,
  1540. DRM_MODE_CONNECTOR_DSI);
  1541. if (connector) {
  1542. priv->encoders[priv->num_encoders++] = encoder;
  1543. priv->connectors[priv->num_connectors++] = connector;
  1544. } else {
  1545. SDE_ERROR("dsi %d connector init failed\n", i);
  1546. dsi_display_drm_bridge_deinit(display);
  1547. sde_encoder_destroy(encoder);
  1548. continue;
  1549. }
  1550. rc = dsi_display_drm_ext_bridge_init(display,
  1551. encoder, connector);
  1552. if (rc) {
  1553. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1554. dsi_display_drm_bridge_deinit(display);
  1555. sde_connector_destroy(connector);
  1556. sde_encoder_destroy(encoder);
  1557. }
  1558. dsc_count += info.dsc_count;
  1559. mixer_count += info.lm_count;
  1560. }
  1561. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1562. sde_kms->catalog->mixer_count - mixer_count : 0;
  1563. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1564. sde_kms->catalog->dsc_count - dsc_count : 0;
  1565. /* dp */
  1566. for (i = 0; i < sde_kms->dp_display_count &&
  1567. priv->num_encoders < max_encoders; ++i) {
  1568. int idx;
  1569. display = sde_kms->dp_displays[i];
  1570. encoder = NULL;
  1571. memset(&info, 0x0, sizeof(info));
  1572. rc = dp_connector_get_info(NULL, &info, display);
  1573. if (rc) {
  1574. SDE_ERROR("dp get_info %d failed\n", i);
  1575. continue;
  1576. }
  1577. encoder = sde_encoder_init(dev, &info);
  1578. if (IS_ERR_OR_NULL(encoder)) {
  1579. SDE_ERROR("dp encoder init failed %d\n", i);
  1580. continue;
  1581. }
  1582. rc = dp_drm_bridge_init(display, encoder,
  1583. max_dp_mixer_count, max_dp_dsc_count);
  1584. if (rc) {
  1585. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1586. sde_encoder_destroy(encoder);
  1587. continue;
  1588. }
  1589. connector = sde_connector_init(dev,
  1590. encoder,
  1591. NULL,
  1592. display,
  1593. &dp_ops,
  1594. DRM_CONNECTOR_POLL_HPD,
  1595. DRM_MODE_CONNECTOR_DisplayPort);
  1596. if (connector) {
  1597. priv->encoders[priv->num_encoders++] = encoder;
  1598. priv->connectors[priv->num_connectors++] = connector;
  1599. } else {
  1600. SDE_ERROR("dp %d connector init failed\n", i);
  1601. dp_drm_bridge_deinit(display);
  1602. sde_encoder_destroy(encoder);
  1603. }
  1604. /* update display cap to MST_MODE for DP MST encoders */
  1605. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1606. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1607. priv->num_encoders < max_encoders; idx++) {
  1608. info.h_tile_instance[0] = idx;
  1609. encoder = sde_encoder_init(dev, &info);
  1610. if (IS_ERR_OR_NULL(encoder)) {
  1611. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1612. continue;
  1613. }
  1614. rc = dp_mst_drm_bridge_init(display, encoder);
  1615. if (rc) {
  1616. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1617. i, rc);
  1618. sde_encoder_destroy(encoder);
  1619. continue;
  1620. }
  1621. priv->encoders[priv->num_encoders++] = encoder;
  1622. }
  1623. }
  1624. return 0;
  1625. }
  1626. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1627. {
  1628. struct msm_drm_private *priv;
  1629. int i;
  1630. if (!sde_kms) {
  1631. SDE_ERROR("invalid sde_kms\n");
  1632. return;
  1633. } else if (!sde_kms->dev) {
  1634. SDE_ERROR("invalid dev\n");
  1635. return;
  1636. } else if (!sde_kms->dev->dev_private) {
  1637. SDE_ERROR("invalid dev_private\n");
  1638. return;
  1639. }
  1640. priv = sde_kms->dev->dev_private;
  1641. for (i = 0; i < priv->num_crtcs; i++)
  1642. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1643. priv->num_crtcs = 0;
  1644. for (i = 0; i < priv->num_planes; i++)
  1645. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1646. priv->num_planes = 0;
  1647. for (i = 0; i < priv->num_connectors; i++)
  1648. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1649. priv->num_connectors = 0;
  1650. for (i = 0; i < priv->num_encoders; i++)
  1651. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1652. priv->num_encoders = 0;
  1653. _sde_kms_release_displays(sde_kms);
  1654. }
  1655. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1656. {
  1657. struct drm_device *dev;
  1658. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1659. struct drm_crtc *crtc;
  1660. struct msm_drm_private *priv;
  1661. struct sde_mdss_cfg *catalog;
  1662. int primary_planes_idx = 0, i, ret;
  1663. int max_crtc_count;
  1664. u32 sspp_id[MAX_PLANES];
  1665. u32 master_plane_id[MAX_PLANES];
  1666. u32 num_virt_planes = 0;
  1667. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1668. SDE_ERROR("invalid sde_kms\n");
  1669. return -EINVAL;
  1670. }
  1671. dev = sde_kms->dev;
  1672. priv = dev->dev_private;
  1673. catalog = sde_kms->catalog;
  1674. ret = sde_core_irq_domain_add(sde_kms);
  1675. if (ret)
  1676. goto fail_irq;
  1677. /*
  1678. * Query for underlying display drivers, and create connectors,
  1679. * bridges and encoders for them.
  1680. */
  1681. if (!_sde_kms_get_displays(sde_kms))
  1682. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1683. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1684. /* Create the planes */
  1685. for (i = 0; i < catalog->sspp_count; i++) {
  1686. bool primary = true;
  1687. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1688. || primary_planes_idx >= max_crtc_count)
  1689. primary = false;
  1690. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1691. (1UL << max_crtc_count) - 1, 0);
  1692. if (IS_ERR(plane)) {
  1693. SDE_ERROR("sde_plane_init failed\n");
  1694. ret = PTR_ERR(plane);
  1695. goto fail;
  1696. }
  1697. priv->planes[priv->num_planes++] = plane;
  1698. if (primary)
  1699. primary_planes[primary_planes_idx++] = plane;
  1700. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1701. sde_is_custom_client()) {
  1702. int priority =
  1703. catalog->sspp[i].sblk->smart_dma_priority;
  1704. sspp_id[priority - 1] = catalog->sspp[i].id;
  1705. master_plane_id[priority - 1] = plane->base.id;
  1706. num_virt_planes++;
  1707. }
  1708. }
  1709. /* Initialize smart DMA virtual planes */
  1710. for (i = 0; i < num_virt_planes; i++) {
  1711. plane = sde_plane_init(dev, sspp_id[i], false,
  1712. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1713. if (IS_ERR(plane)) {
  1714. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1715. ret = PTR_ERR(plane);
  1716. goto fail;
  1717. }
  1718. priv->planes[priv->num_planes++] = plane;
  1719. }
  1720. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1721. /* Create one CRTC per encoder */
  1722. for (i = 0; i < max_crtc_count; i++) {
  1723. crtc = sde_crtc_init(dev, primary_planes[i]);
  1724. if (IS_ERR(crtc)) {
  1725. ret = PTR_ERR(crtc);
  1726. goto fail;
  1727. }
  1728. priv->crtcs[priv->num_crtcs++] = crtc;
  1729. }
  1730. if (sde_is_custom_client()) {
  1731. /* All CRTCs are compatible with all planes */
  1732. for (i = 0; i < priv->num_planes; i++)
  1733. priv->planes[i]->possible_crtcs =
  1734. (1 << priv->num_crtcs) - 1;
  1735. }
  1736. /* All CRTCs are compatible with all encoders */
  1737. for (i = 0; i < priv->num_encoders; i++)
  1738. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1739. return 0;
  1740. fail:
  1741. _sde_kms_drm_obj_destroy(sde_kms);
  1742. fail_irq:
  1743. sde_core_irq_domain_fini(sde_kms);
  1744. return ret;
  1745. }
  1746. /**
  1747. * sde_kms_timeline_status - provides current timeline status
  1748. * This API should be called without mode config lock.
  1749. * @dev: Pointer to drm device
  1750. */
  1751. void sde_kms_timeline_status(struct drm_device *dev)
  1752. {
  1753. struct drm_crtc *crtc;
  1754. struct drm_connector *conn;
  1755. struct drm_connector_list_iter conn_iter;
  1756. if (!dev) {
  1757. SDE_ERROR("invalid drm device node\n");
  1758. return;
  1759. }
  1760. drm_for_each_crtc(crtc, dev)
  1761. sde_crtc_timeline_status(crtc);
  1762. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1763. /*
  1764. *Probably locked from last close dumping status anyway
  1765. */
  1766. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1767. drm_connector_list_iter_begin(dev, &conn_iter);
  1768. drm_for_each_connector_iter(conn, &conn_iter)
  1769. sde_conn_timeline_status(conn);
  1770. drm_connector_list_iter_end(&conn_iter);
  1771. return;
  1772. }
  1773. mutex_lock(&dev->mode_config.mutex);
  1774. drm_connector_list_iter_begin(dev, &conn_iter);
  1775. drm_for_each_connector_iter(conn, &conn_iter)
  1776. sde_conn_timeline_status(conn);
  1777. drm_connector_list_iter_end(&conn_iter);
  1778. mutex_unlock(&dev->mode_config.mutex);
  1779. }
  1780. static int sde_kms_postinit(struct msm_kms *kms)
  1781. {
  1782. struct sde_kms *sde_kms = to_sde_kms(kms);
  1783. struct drm_device *dev;
  1784. struct drm_crtc *crtc;
  1785. int rc;
  1786. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1787. SDE_ERROR("invalid sde_kms\n");
  1788. return -EINVAL;
  1789. }
  1790. dev = sde_kms->dev;
  1791. rc = _sde_debugfs_init(sde_kms);
  1792. if (rc)
  1793. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1794. drm_for_each_crtc(crtc, dev)
  1795. sde_crtc_post_init(dev, crtc);
  1796. return rc;
  1797. }
  1798. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1799. struct drm_encoder *encoder)
  1800. {
  1801. return rate;
  1802. }
  1803. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1804. struct platform_device *pdev)
  1805. {
  1806. struct drm_device *dev;
  1807. struct msm_drm_private *priv;
  1808. struct sde_vm_ops *vm_ops;
  1809. int i;
  1810. if (!sde_kms || !pdev)
  1811. return;
  1812. dev = sde_kms->dev;
  1813. if (!dev)
  1814. return;
  1815. priv = dev->dev_private;
  1816. if (!priv)
  1817. return;
  1818. if (sde_kms->genpd_init) {
  1819. sde_kms->genpd_init = false;
  1820. pm_genpd_remove(&sde_kms->genpd);
  1821. of_genpd_del_provider(pdev->dev.of_node);
  1822. }
  1823. vm_ops = sde_vm_get_ops(sde_kms);
  1824. if (vm_ops && vm_ops->vm_deinit)
  1825. vm_ops->vm_deinit(sde_kms, vm_ops);
  1826. if (sde_kms->hw_intr)
  1827. sde_hw_intr_destroy(sde_kms->hw_intr);
  1828. sde_kms->hw_intr = NULL;
  1829. if (sde_kms->power_event)
  1830. sde_power_handle_unregister_event(
  1831. &priv->phandle, sde_kms->power_event);
  1832. _sde_kms_release_displays(sde_kms);
  1833. _sde_kms_unmap_all_splash_regions(sde_kms);
  1834. if (sde_kms->catalog) {
  1835. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1836. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1837. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1838. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1839. }
  1840. }
  1841. if (sde_kms->rm_init)
  1842. sde_rm_destroy(&sde_kms->rm);
  1843. sde_kms->rm_init = false;
  1844. if (sde_kms->catalog)
  1845. sde_hw_catalog_deinit(sde_kms->catalog);
  1846. sde_kms->catalog = NULL;
  1847. if (sde_kms->sid)
  1848. msm_iounmap(pdev, sde_kms->sid);
  1849. sde_kms->sid = NULL;
  1850. if (sde_kms->reg_dma)
  1851. msm_iounmap(pdev, sde_kms->reg_dma);
  1852. sde_kms->reg_dma = NULL;
  1853. if (sde_kms->vbif[VBIF_NRT])
  1854. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1855. sde_kms->vbif[VBIF_NRT] = NULL;
  1856. if (sde_kms->vbif[VBIF_RT])
  1857. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1858. sde_kms->vbif[VBIF_RT] = NULL;
  1859. if (sde_kms->mmio)
  1860. msm_iounmap(pdev, sde_kms->mmio);
  1861. sde_kms->mmio = NULL;
  1862. sde_reg_dma_deinit();
  1863. _sde_kms_mmu_destroy(sde_kms);
  1864. }
  1865. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1866. {
  1867. int i;
  1868. if (!sde_kms)
  1869. return -EINVAL;
  1870. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1871. struct msm_mmu *mmu;
  1872. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1873. if (!aspace)
  1874. continue;
  1875. mmu = sde_kms->aspace[i]->mmu;
  1876. if (secure_only &&
  1877. !aspace->mmu->funcs->is_domain_secure(mmu))
  1878. continue;
  1879. /* cleanup aspace before detaching */
  1880. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1881. SDE_DEBUG("Detaching domain:%d\n", i);
  1882. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1883. ARRAY_SIZE(iommu_ports));
  1884. aspace->domain_attached = false;
  1885. }
  1886. return 0;
  1887. }
  1888. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1889. {
  1890. int i;
  1891. if (!sde_kms)
  1892. return -EINVAL;
  1893. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1894. struct msm_mmu *mmu;
  1895. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1896. if (!aspace)
  1897. continue;
  1898. mmu = sde_kms->aspace[i]->mmu;
  1899. if (secure_only &&
  1900. !aspace->mmu->funcs->is_domain_secure(mmu))
  1901. continue;
  1902. SDE_DEBUG("Attaching domain:%d\n", i);
  1903. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1904. ARRAY_SIZE(iommu_ports));
  1905. aspace->domain_attached = true;
  1906. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1907. }
  1908. return 0;
  1909. }
  1910. static void sde_kms_destroy(struct msm_kms *kms)
  1911. {
  1912. struct sde_kms *sde_kms;
  1913. struct drm_device *dev;
  1914. if (!kms) {
  1915. SDE_ERROR("invalid kms\n");
  1916. return;
  1917. }
  1918. sde_kms = to_sde_kms(kms);
  1919. dev = sde_kms->dev;
  1920. if (!dev || !dev->dev) {
  1921. SDE_ERROR("invalid device\n");
  1922. return;
  1923. }
  1924. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1925. kfree(sde_kms);
  1926. }
  1927. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1928. struct drm_atomic_state *state)
  1929. {
  1930. struct drm_device *dev = sde_kms->dev;
  1931. struct drm_plane *plane;
  1932. struct drm_plane_state *plane_state;
  1933. struct drm_crtc *crtc;
  1934. struct drm_crtc_state *crtc_state;
  1935. struct drm_connector *conn;
  1936. struct drm_connector_state *conn_state;
  1937. struct drm_connector_list_iter conn_iter;
  1938. int ret = 0;
  1939. drm_for_each_plane(plane, dev) {
  1940. plane_state = drm_atomic_get_plane_state(state, plane);
  1941. if (IS_ERR(plane_state)) {
  1942. ret = PTR_ERR(plane_state);
  1943. SDE_ERROR("error %d getting plane %d state\n",
  1944. ret, DRMID(plane));
  1945. return ret;
  1946. }
  1947. ret = sde_plane_helper_reset_custom_properties(plane,
  1948. plane_state);
  1949. if (ret) {
  1950. SDE_ERROR("error %d resetting plane props %d\n",
  1951. ret, DRMID(plane));
  1952. return ret;
  1953. }
  1954. }
  1955. drm_for_each_crtc(crtc, dev) {
  1956. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1957. if (IS_ERR(crtc_state)) {
  1958. ret = PTR_ERR(crtc_state);
  1959. SDE_ERROR("error %d getting crtc %d state\n",
  1960. ret, DRMID(crtc));
  1961. return ret;
  1962. }
  1963. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1964. if (ret) {
  1965. SDE_ERROR("error %d resetting crtc props %d\n",
  1966. ret, DRMID(crtc));
  1967. return ret;
  1968. }
  1969. }
  1970. drm_connector_list_iter_begin(dev, &conn_iter);
  1971. drm_for_each_connector_iter(conn, &conn_iter) {
  1972. conn_state = drm_atomic_get_connector_state(state, conn);
  1973. if (IS_ERR(conn_state)) {
  1974. ret = PTR_ERR(conn_state);
  1975. SDE_ERROR("error %d getting connector %d state\n",
  1976. ret, DRMID(conn));
  1977. return ret;
  1978. }
  1979. ret = sde_connector_helper_reset_custom_properties(conn,
  1980. conn_state);
  1981. if (ret) {
  1982. SDE_ERROR("error %d resetting connector props %d\n",
  1983. ret, DRMID(conn));
  1984. return ret;
  1985. }
  1986. }
  1987. drm_connector_list_iter_end(&conn_iter);
  1988. return ret;
  1989. }
  1990. static void sde_kms_lastclose(struct msm_kms *kms)
  1991. {
  1992. struct sde_kms *sde_kms;
  1993. struct drm_device *dev;
  1994. struct drm_atomic_state *state;
  1995. struct drm_modeset_acquire_ctx ctx;
  1996. int ret;
  1997. if (!kms) {
  1998. SDE_ERROR("invalid argument\n");
  1999. return;
  2000. }
  2001. sde_kms = to_sde_kms(kms);
  2002. dev = sde_kms->dev;
  2003. drm_modeset_acquire_init(&ctx, 0);
  2004. state = drm_atomic_state_alloc(dev);
  2005. if (!state) {
  2006. ret = -ENOMEM;
  2007. goto out_ctx;
  2008. }
  2009. state->acquire_ctx = &ctx;
  2010. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2011. retry:
  2012. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2013. if (ret)
  2014. goto out_state;
  2015. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2016. if (ret)
  2017. goto out_state;
  2018. ret = drm_atomic_commit(state);
  2019. out_state:
  2020. if (ret == -EDEADLK)
  2021. goto backoff;
  2022. drm_atomic_state_put(state);
  2023. out_ctx:
  2024. drm_modeset_drop_locks(&ctx);
  2025. drm_modeset_acquire_fini(&ctx);
  2026. if (ret)
  2027. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2028. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2029. return;
  2030. backoff:
  2031. drm_atomic_state_clear(state);
  2032. drm_modeset_backoff(&ctx);
  2033. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2034. goto retry;
  2035. }
  2036. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2037. struct drm_atomic_state *state)
  2038. {
  2039. struct sde_kms *sde_kms;
  2040. struct drm_device *dev;
  2041. struct drm_crtc *crtc;
  2042. struct drm_encoder *encoder;
  2043. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2044. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2045. uint32_t crtc_encoder_cnt = 0;
  2046. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2047. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2048. struct sde_vm_ops *vm_ops;
  2049. bool vm_req_active = false;
  2050. enum sde_crtc_idle_pc_state idle_pc_state;
  2051. struct sde_mdss_cfg *catalog;
  2052. int rc = 0;
  2053. struct sde_connector *sde_conn;
  2054. struct dsi_display *dsi_display;
  2055. struct drm_connector *connector;
  2056. struct drm_connector_state *new_connstate;
  2057. if (!kms || !state)
  2058. return -EINVAL;
  2059. sde_kms = to_sde_kms(kms);
  2060. dev = sde_kms->dev;
  2061. catalog = sde_kms->catalog;
  2062. vm_ops = sde_vm_get_ops(sde_kms);
  2063. if (!vm_ops)
  2064. return 0;
  2065. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw ||
  2066. !vm_ops->vm_acquire)
  2067. return -EINVAL;
  2068. sde_vm_lock(sde_kms);
  2069. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2070. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2071. if (!new_cstate->active && !old_cstate->active)
  2072. continue;
  2073. new_state = to_sde_crtc_state(new_cstate);
  2074. new_vm_req = sde_crtc_get_property(new_state,
  2075. CRTC_PROP_VM_REQ_STATE);
  2076. old_state = to_sde_crtc_state(old_cstate);
  2077. old_vm_req = sde_crtc_get_property(old_state,
  2078. CRTC_PROP_VM_REQ_STATE);
  2079. /*
  2080. * No active request if the transition is from
  2081. * VM_REQ_NONE to VM_REQ_NONE
  2082. */
  2083. if (old_vm_req || new_vm_req) {
  2084. rc = vm_ops->vm_request_valid(sde_kms,
  2085. old_vm_req, new_vm_req);
  2086. if (rc) {
  2087. SDE_ERROR(
  2088. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2089. old_vm_req, new_vm_req,
  2090. vm_ops->vm_owns_hw(sde_kms), rc);
  2091. goto end;
  2092. } else if (old_vm_req == VM_REQ_ACQUIRE &&
  2093. new_vm_req == VM_REQ_NONE) {
  2094. SDE_DEBUG(
  2095. "VM transition valid; ignore further checks\n");
  2096. } else {
  2097. vm_req_active = true;
  2098. }
  2099. }
  2100. idle_pc_state = sde_crtc_get_property(new_state,
  2101. CRTC_PROP_IDLE_PC_STATE);
  2102. active_crtc = crtc;
  2103. active_cstate = new_cstate;
  2104. commit_crtc_cnt++;
  2105. }
  2106. /* return early if no active vm request */
  2107. if (!vm_req_active)
  2108. goto end;
  2109. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2110. if (!crtc->state->active)
  2111. continue;
  2112. global_crtc_cnt++;
  2113. global_active_crtc = crtc;
  2114. }
  2115. if (active_crtc) {
  2116. drm_for_each_encoder_mask(encoder, active_crtc->dev,
  2117. active_cstate->encoder_mask)
  2118. crtc_encoder_cnt++;
  2119. }
  2120. SDE_EVT32(old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2121. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d\n", old_vm_req,
  2122. new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2123. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2124. int conn_mask = active_cstate->connector_mask;
  2125. if (drm_connector_mask(connector) & conn_mask) {
  2126. sde_conn = to_sde_connector(connector);
  2127. dsi_display = (struct dsi_display *) sde_conn->display;
  2128. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i,
  2129. dsi_display->type,
  2130. dsi_display->trusted_vm_env);
  2131. SDE_DEBUG(
  2132. "VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d,",
  2133. dsi_display->name, DRMID(connector),
  2134. DRMID(active_crtc), dsi_display->type,
  2135. dsi_display->trusted_vm_env);
  2136. break;
  2137. }
  2138. }
  2139. /* Check for single crtc commits only on valid VM requests */
  2140. if (active_crtc && global_active_crtc &&
  2141. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2142. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2143. active_crtc != global_active_crtc)) {
  2144. SDE_ERROR(
  2145. "VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2146. catalog->max_trusted_vm_displays,
  2147. commit_crtc_cnt, global_crtc_cnt, DRMID(active_crtc),
  2148. DRMID(global_active_crtc));
  2149. rc = -E2BIG;
  2150. goto end;
  2151. } else if ((new_vm_req == VM_REQ_RELEASE) &&
  2152. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2153. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2154. /*
  2155. * disable idle-pc before releasing the HW
  2156. * allow only specified number of encoders on a given crtc
  2157. */
  2158. SDE_ERROR(
  2159. "VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2160. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC,
  2161. crtc_encoder_cnt);
  2162. rc = -EINVAL;
  2163. goto end;
  2164. }
  2165. if ((new_vm_req == VM_REQ_ACQUIRE) && !vm_ops->vm_owns_hw(sde_kms)) {
  2166. rc = vm_ops->vm_acquire(sde_kms);
  2167. if (rc) {
  2168. SDE_ERROR(
  2169. "VM acquire failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2170. old_vm_req, new_vm_req,
  2171. vm_ops->vm_owns_hw(sde_kms), rc);
  2172. goto end;
  2173. }
  2174. if (vm_ops->vm_resource_init)
  2175. rc = vm_ops->vm_resource_init(sde_kms, state);
  2176. }
  2177. end:
  2178. sde_vm_unlock(sde_kms);
  2179. return rc;
  2180. }
  2181. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2182. struct drm_atomic_state *state)
  2183. {
  2184. struct sde_kms *sde_kms;
  2185. struct drm_device *dev;
  2186. struct drm_crtc *crtc;
  2187. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2188. struct drm_crtc_state *crtc_state;
  2189. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2190. bool sec_session = false, global_sec_session = false;
  2191. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2192. int i;
  2193. if (!kms || !state) {
  2194. return -EINVAL;
  2195. SDE_ERROR("invalid arguments\n");
  2196. }
  2197. sde_kms = to_sde_kms(kms);
  2198. dev = sde_kms->dev;
  2199. /* iterate state object for active secure/non-secure crtc */
  2200. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2201. if (!crtc_state->active)
  2202. continue;
  2203. active_crtc_cnt++;
  2204. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2205. &fb_sec, &fb_sec_dir);
  2206. if (fb_sec_dir)
  2207. sec_session = true;
  2208. cur_crtc = crtc;
  2209. }
  2210. /* iterate global list for active and secure/non-secure crtc */
  2211. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2212. if (!crtc->state->active)
  2213. continue;
  2214. global_active_crtc_cnt++;
  2215. /* update only when crtc is not the same as current crtc */
  2216. if (crtc != cur_crtc) {
  2217. fb_ns = fb_sec = fb_sec_dir = 0;
  2218. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2219. &fb_sec, &fb_sec_dir);
  2220. if (fb_sec_dir)
  2221. global_sec_session = true;
  2222. global_crtc = crtc;
  2223. }
  2224. }
  2225. if (!global_sec_session && !sec_session)
  2226. return 0;
  2227. /*
  2228. * - fail crtc commit, if secure-camera/secure-ui session is
  2229. * in-progress in any other display
  2230. * - fail secure-camera/secure-ui crtc commit, if any other display
  2231. * session is in-progress
  2232. */
  2233. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2234. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2235. SDE_ERROR(
  2236. "crtc%d secure check failed global_active:%d active:%d\n",
  2237. cur_crtc ? cur_crtc->base.id : -1,
  2238. global_active_crtc_cnt, active_crtc_cnt);
  2239. return -EPERM;
  2240. /*
  2241. * As only one crtc is allowed during secure session, the crtc
  2242. * in this commit should match with the global crtc
  2243. */
  2244. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2245. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2246. cur_crtc->base.id, sec_session,
  2247. global_crtc->base.id, global_sec_session);
  2248. return -EPERM;
  2249. }
  2250. return 0;
  2251. }
  2252. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2253. struct drm_atomic_state *state)
  2254. {
  2255. struct drm_crtc *crtc;
  2256. struct drm_crtc_state *new_cstate;
  2257. struct sde_crtc_state *cstate;
  2258. struct sde_vm_ops *vm_ops;
  2259. enum sde_crtc_vm_req vm_req;
  2260. struct sde_kms *sde_kms = to_sde_kms(kms);
  2261. vm_ops = sde_vm_get_ops(sde_kms);
  2262. if (!vm_ops)
  2263. return;
  2264. crtc = sde_kms_vm_get_vm_crtc(state);
  2265. if (!crtc)
  2266. return;
  2267. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2268. cstate = to_sde_crtc_state(new_cstate);
  2269. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2270. if (vm_req != VM_REQ_ACQUIRE)
  2271. return;
  2272. sde_vm_lock(sde_kms);
  2273. if (vm_ops->vm_acquire_fail_handler)
  2274. vm_ops->vm_acquire_fail_handler(sde_kms);
  2275. sde_vm_unlock(sde_kms);
  2276. }
  2277. static int sde_kms_atomic_check(struct msm_kms *kms,
  2278. struct drm_atomic_state *state)
  2279. {
  2280. struct sde_kms *sde_kms;
  2281. struct drm_device *dev;
  2282. int ret;
  2283. if (!kms || !state)
  2284. return -EINVAL;
  2285. sde_kms = to_sde_kms(kms);
  2286. dev = sde_kms->dev;
  2287. SDE_ATRACE_BEGIN("atomic_check");
  2288. if (sde_kms_is_suspend_blocked(dev)) {
  2289. SDE_DEBUG("suspended, skip atomic_check\n");
  2290. ret = -EBUSY;
  2291. goto end;
  2292. }
  2293. ret = sde_kms_check_vm_request(kms, state);
  2294. if (ret) {
  2295. SDE_ERROR("vm switch request checks failed\n");
  2296. goto end;
  2297. }
  2298. ret = drm_atomic_helper_check(dev, state);
  2299. if (ret)
  2300. goto vm_clean_up;
  2301. /*
  2302. * Check if any secure transition(moving CRTC between secure and
  2303. * non-secure state and vice-versa) is allowed or not. when moving
  2304. * to secure state, planes with fb_mode set to dir_translated only can
  2305. * be staged on the CRTC, and only one CRTC can be active during
  2306. * Secure state
  2307. */
  2308. ret = sde_kms_check_secure_transition(kms, state);
  2309. if (ret)
  2310. goto vm_clean_up;
  2311. goto end;
  2312. vm_clean_up:
  2313. sde_kms_vm_res_release(kms, state);
  2314. end:
  2315. SDE_ATRACE_END("atomic_check");
  2316. return ret;
  2317. }
  2318. static struct msm_gem_address_space*
  2319. _sde_kms_get_address_space(struct msm_kms *kms,
  2320. unsigned int domain)
  2321. {
  2322. struct sde_kms *sde_kms;
  2323. if (!kms) {
  2324. SDE_ERROR("invalid kms\n");
  2325. return NULL;
  2326. }
  2327. sde_kms = to_sde_kms(kms);
  2328. if (!sde_kms) {
  2329. SDE_ERROR("invalid sde_kms\n");
  2330. return NULL;
  2331. }
  2332. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2333. return NULL;
  2334. return (sde_kms->aspace[domain] &&
  2335. sde_kms->aspace[domain]->domain_attached) ?
  2336. sde_kms->aspace[domain] : NULL;
  2337. }
  2338. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2339. unsigned int domain)
  2340. {
  2341. struct sde_kms *sde_kms;
  2342. struct msm_gem_address_space *aspace;
  2343. if (!kms) {
  2344. SDE_ERROR("invalid kms\n");
  2345. return NULL;
  2346. }
  2347. sde_kms = to_sde_kms(kms);
  2348. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2349. SDE_ERROR("invalid params\n");
  2350. return NULL;
  2351. }
  2352. aspace = _sde_kms_get_address_space(kms, domain);
  2353. return (aspace && aspace->domain_attached) ?
  2354. msm_gem_get_aspace_device(aspace) : NULL;
  2355. }
  2356. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2357. {
  2358. struct drm_device *dev = NULL;
  2359. struct sde_kms *sde_kms = NULL;
  2360. struct drm_connector *connector = NULL;
  2361. struct drm_connector_list_iter conn_iter;
  2362. struct sde_connector *sde_conn = NULL;
  2363. if (!kms) {
  2364. SDE_ERROR("invalid kms\n");
  2365. return;
  2366. }
  2367. sde_kms = to_sde_kms(kms);
  2368. dev = sde_kms->dev;
  2369. if (!dev) {
  2370. SDE_ERROR("invalid device\n");
  2371. return;
  2372. }
  2373. if (!dev->mode_config.poll_enabled)
  2374. return;
  2375. mutex_lock(&dev->mode_config.mutex);
  2376. drm_connector_list_iter_begin(dev, &conn_iter);
  2377. drm_for_each_connector_iter(connector, &conn_iter) {
  2378. /* Only handle HPD capable connectors. */
  2379. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2380. continue;
  2381. sde_conn = to_sde_connector(connector);
  2382. if (sde_conn->ops.post_open)
  2383. sde_conn->ops.post_open(&sde_conn->base,
  2384. sde_conn->display);
  2385. }
  2386. drm_connector_list_iter_end(&conn_iter);
  2387. mutex_unlock(&dev->mode_config.mutex);
  2388. }
  2389. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2390. struct sde_splash_display *splash_display,
  2391. struct drm_crtc *crtc)
  2392. {
  2393. struct msm_drm_private *priv;
  2394. struct drm_plane *plane;
  2395. struct sde_splash_mem *splash;
  2396. enum sde_sspp plane_id;
  2397. bool is_virtual;
  2398. int i, j;
  2399. if (!sde_kms || !splash_display || !crtc) {
  2400. SDE_ERROR("invalid input args\n");
  2401. return -EINVAL;
  2402. }
  2403. priv = sde_kms->dev->dev_private;
  2404. for (i = 0; i < priv->num_planes; i++) {
  2405. plane = priv->planes[i];
  2406. plane_id = sde_plane_pipe(plane);
  2407. is_virtual = is_sde_plane_virtual(plane);
  2408. splash = splash_display->splash;
  2409. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2410. if ((plane_id != splash_display->pipes[j].sspp) ||
  2411. (splash_display->pipes[j].is_virtual
  2412. != is_virtual))
  2413. continue;
  2414. if (splash && sde_plane_validate_src_addr(plane,
  2415. splash->splash_buf_base,
  2416. splash->splash_buf_size)) {
  2417. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2418. plane_id, crtc->base.id);
  2419. }
  2420. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2421. crtc->base.id, plane_id, is_virtual);
  2422. }
  2423. }
  2424. return 0;
  2425. }
  2426. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2427. struct dsi_display *dsi_display)
  2428. {
  2429. void *display;
  2430. struct drm_encoder *encoder = NULL;
  2431. struct msm_display_info info;
  2432. struct drm_device *dev;
  2433. struct sde_kms *sde_kms;
  2434. struct drm_connector_list_iter conn_iter;
  2435. struct drm_connector *connector = NULL;
  2436. struct sde_connector *sde_conn = NULL;
  2437. int rc = 0;
  2438. sde_kms = to_sde_kms(kms);
  2439. dev = sde_kms->dev;
  2440. display = dsi_display;
  2441. if (dsi_display) {
  2442. if (dsi_display->bridge->base.encoder) {
  2443. encoder = dsi_display->bridge->base.encoder;
  2444. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2445. }
  2446. memset(&info, 0x0, sizeof(info));
  2447. rc = dsi_display_get_info(NULL, &info, display);
  2448. if (rc) {
  2449. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2450. rc, __func__);
  2451. encoder = NULL;
  2452. }
  2453. }
  2454. drm_connector_list_iter_begin(dev, &conn_iter);
  2455. drm_for_each_connector_iter(connector, &conn_iter) {
  2456. struct drm_encoder *c_encoder;
  2457. drm_connector_for_each_possible_encoder(connector,
  2458. c_encoder)
  2459. break;
  2460. if (!c_encoder) {
  2461. SDE_ERROR("c_encoder not found\n");
  2462. return -EINVAL;
  2463. }
  2464. /**
  2465. * Inform cont_splash is disabled to each interface/connector.
  2466. * This is currently supported for DSI interface.
  2467. */
  2468. sde_conn = to_sde_connector(connector);
  2469. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2470. if (!dsi_display || !encoder) {
  2471. sde_conn->ops.cont_splash_res_disable
  2472. (sde_conn->display);
  2473. } else if (c_encoder->base.id == encoder->base.id) {
  2474. /**
  2475. * This handles dual DSI
  2476. * configuration where one DSI
  2477. * interface has cont_splash
  2478. * enabled and the other doesn't.
  2479. */
  2480. sde_conn->ops.cont_splash_res_disable
  2481. (sde_conn->display);
  2482. break;
  2483. }
  2484. }
  2485. }
  2486. drm_connector_list_iter_end(&conn_iter);
  2487. return 0;
  2488. }
  2489. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2490. {
  2491. int i;
  2492. void *display;
  2493. struct dsi_display *dsi_display;
  2494. struct drm_encoder *encoder;
  2495. if (!sde_kms)
  2496. return -EINVAL;
  2497. if (!sde_in_trusted_vm(sde_kms))
  2498. return 0;
  2499. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2500. display = sde_kms->dsi_displays[i];
  2501. dsi_display = (struct dsi_display *)display;
  2502. if (!dsi_display->bridge->base.encoder) {
  2503. SDE_ERROR("no encoder on dsi display:%d", i);
  2504. return -EINVAL;
  2505. }
  2506. encoder = dsi_display->bridge->base.encoder;
  2507. encoder->possible_crtcs = 1 << i;
  2508. SDE_DEBUG(
  2509. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2510. encoder->index, encoder->base.id,
  2511. encoder->name, encoder->possible_crtcs);
  2512. }
  2513. return 0;
  2514. }
  2515. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2516. struct sde_kms *sde_kms, struct drm_connector *connector,
  2517. struct drm_atomic_state *state)
  2518. {
  2519. struct drm_display_mode *mode, *cur_mode = NULL;
  2520. struct drm_crtc *crtc;
  2521. struct drm_crtc_state *new_cstate, *old_cstate;
  2522. u32 i = 0;
  2523. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2524. list_for_each_entry(mode, &connector->modes, head) {
  2525. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2526. cur_mode = mode;
  2527. break;
  2528. }
  2529. }
  2530. } else if (state) {
  2531. /* get the mode from first atomic_check phase for trusted_vm*/
  2532. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2533. new_cstate, i) {
  2534. if (!new_cstate->active && !old_cstate->active)
  2535. continue;
  2536. list_for_each_entry(mode, &connector->modes, head) {
  2537. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2538. cur_mode = mode;
  2539. break;
  2540. }
  2541. }
  2542. }
  2543. }
  2544. return cur_mode;
  2545. }
  2546. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2547. struct drm_atomic_state *state)
  2548. {
  2549. void *display;
  2550. struct dsi_display *dsi_display;
  2551. struct msm_display_info info;
  2552. struct drm_encoder *encoder = NULL;
  2553. struct drm_crtc *crtc = NULL;
  2554. int i, rc = 0;
  2555. struct drm_display_mode *drm_mode = NULL;
  2556. struct drm_device *dev;
  2557. struct msm_drm_private *priv;
  2558. struct sde_kms *sde_kms;
  2559. struct drm_connector_list_iter conn_iter;
  2560. struct drm_connector *connector = NULL;
  2561. struct sde_connector *sde_conn = NULL;
  2562. struct sde_splash_display *splash_display;
  2563. if (!kms) {
  2564. SDE_ERROR("invalid kms\n");
  2565. return -EINVAL;
  2566. }
  2567. sde_kms = to_sde_kms(kms);
  2568. dev = sde_kms->dev;
  2569. if (!dev) {
  2570. SDE_ERROR("invalid device\n");
  2571. return -EINVAL;
  2572. }
  2573. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2574. if (rc) {
  2575. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2576. return -EINVAL;
  2577. }
  2578. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2579. && (!sde_kms->splash_data.num_splash_regions)) ||
  2580. !sde_kms->splash_data.num_splash_displays) {
  2581. DRM_INFO("cont_splash feature not enabled\n");
  2582. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2583. return rc;
  2584. }
  2585. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2586. sde_kms->splash_data.num_splash_displays,
  2587. sde_kms->dsi_display_count);
  2588. /* dsi */
  2589. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2590. display = sde_kms->dsi_displays[i];
  2591. dsi_display = (struct dsi_display *)display;
  2592. splash_display = &sde_kms->splash_data.splash_display[i];
  2593. if (!splash_display->cont_splash_enabled) {
  2594. SDE_DEBUG("display->name = %s splash not enabled\n",
  2595. dsi_display->name);
  2596. sde_kms_inform_cont_splash_res_disable(kms,
  2597. dsi_display);
  2598. continue;
  2599. }
  2600. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2601. if (dsi_display->bridge->base.encoder) {
  2602. encoder = dsi_display->bridge->base.encoder;
  2603. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2604. }
  2605. memset(&info, 0x0, sizeof(info));
  2606. rc = dsi_display_get_info(NULL, &info, display);
  2607. if (rc) {
  2608. SDE_ERROR("dsi get_info %d failed\n", i);
  2609. encoder = NULL;
  2610. continue;
  2611. }
  2612. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2613. ((info.is_connected) ? "true" : "false"),
  2614. info.display_type);
  2615. if (!encoder) {
  2616. SDE_ERROR("encoder not initialized\n");
  2617. return -EINVAL;
  2618. }
  2619. priv = sde_kms->dev->dev_private;
  2620. encoder->crtc = priv->crtcs[i];
  2621. crtc = encoder->crtc;
  2622. splash_display->encoder = encoder;
  2623. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2624. i, crtc->index, crtc->base.id, encoder->index,
  2625. encoder->base.id);
  2626. mutex_lock(&dev->mode_config.mutex);
  2627. drm_connector_list_iter_begin(dev, &conn_iter);
  2628. drm_for_each_connector_iter(connector, &conn_iter) {
  2629. struct drm_encoder *c_encoder;
  2630. drm_connector_for_each_possible_encoder(connector,
  2631. c_encoder)
  2632. break;
  2633. if (!c_encoder) {
  2634. SDE_ERROR("c_encoder not found\n");
  2635. mutex_unlock(&dev->mode_config.mutex);
  2636. return -EINVAL;
  2637. }
  2638. /**
  2639. * SDE_KMS doesn't attach more than one encoder to
  2640. * a DSI connector. So it is safe to check only with
  2641. * the first encoder entry. Revisit this logic if we
  2642. * ever have to support continuous splash for
  2643. * external displays in MST configuration.
  2644. */
  2645. if (c_encoder->base.id == encoder->base.id)
  2646. break;
  2647. }
  2648. drm_connector_list_iter_end(&conn_iter);
  2649. if (!connector) {
  2650. SDE_ERROR("connector not initialized\n");
  2651. mutex_unlock(&dev->mode_config.mutex);
  2652. return -EINVAL;
  2653. }
  2654. mutex_unlock(&dev->mode_config.mutex);
  2655. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2656. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  2657. if (!drm_mode) {
  2658. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  2659. sde_kms->splash_data.type);
  2660. return -EINVAL;
  2661. }
  2662. SDE_DEBUG(
  2663. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  2664. drm_mode->name, drm_mode->type,
  2665. drm_mode->flags, sde_kms->splash_data.type);
  2666. /* Update CRTC drm structure */
  2667. crtc->state->active = true;
  2668. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2669. if (rc) {
  2670. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2671. return rc;
  2672. }
  2673. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2674. drm_mode_copy(&crtc->mode, drm_mode);
  2675. /* Update encoder structure */
  2676. sde_encoder_update_caps_for_cont_splash(encoder,
  2677. splash_display, true);
  2678. sde_crtc_update_cont_splash_settings(crtc);
  2679. sde_conn = to_sde_connector(connector);
  2680. if (sde_conn && sde_conn->ops.cont_splash_config)
  2681. sde_conn->ops.cont_splash_config(sde_conn->display);
  2682. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2683. splash_display, crtc);
  2684. if (rc) {
  2685. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2686. return rc;
  2687. }
  2688. }
  2689. return rc;
  2690. }
  2691. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2692. {
  2693. struct sde_kms *sde_kms;
  2694. if (!kms) {
  2695. SDE_ERROR("invalid kms\n");
  2696. return false;
  2697. }
  2698. sde_kms = to_sde_kms(kms);
  2699. return sde_kms->splash_data.num_splash_displays;
  2700. }
  2701. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2702. const struct drm_display_mode *mode,
  2703. const struct msm_resource_caps_info *res, u32 *num_lm)
  2704. {
  2705. struct sde_kms *sde_kms;
  2706. s64 mode_clock_hz = 0;
  2707. s64 max_mdp_clock_hz = 0;
  2708. s64 max_lm_width = 0;
  2709. s64 hdisplay_fp = 0;
  2710. s64 htotal_fp = 0;
  2711. s64 vtotal_fp = 0;
  2712. s64 vrefresh_fp = 0;
  2713. s64 mdp_fudge_factor = 0;
  2714. s64 num_lm_fp = 0;
  2715. s64 lm_clk_fp = 0;
  2716. s64 lm_width_fp = 0;
  2717. int rc = 0;
  2718. if (!num_lm) {
  2719. SDE_ERROR("invalid num_lm pointer\n");
  2720. return -EINVAL;
  2721. }
  2722. /* default to 1 layer mixer */
  2723. *num_lm = 1;
  2724. if (!kms || !mode || !res) {
  2725. SDE_ERROR("invalid input args\n");
  2726. return -EINVAL;
  2727. }
  2728. sde_kms = to_sde_kms(kms);
  2729. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2730. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2731. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2732. htotal_fp = drm_int2fixp(mode->htotal);
  2733. vtotal_fp = drm_int2fixp(mode->vtotal);
  2734. vrefresh_fp = drm_int2fixp(drm_mode_vrefresh(mode));
  2735. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2736. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2737. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2738. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2739. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2740. if (mode_clock_hz > max_mdp_clock_hz ||
  2741. hdisplay_fp > max_lm_width) {
  2742. *num_lm = 0;
  2743. do {
  2744. *num_lm += 2;
  2745. num_lm_fp = drm_int2fixp(*num_lm);
  2746. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2747. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2748. if (*num_lm > 4) {
  2749. rc = -EINVAL;
  2750. goto error;
  2751. }
  2752. } while (lm_clk_fp > max_mdp_clock_hz ||
  2753. lm_width_fp > max_lm_width);
  2754. mode_clock_hz = lm_clk_fp;
  2755. }
  2756. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2757. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  2758. *num_lm, drm_fixp2int(mode_clock_hz),
  2759. sde_kms->perf.max_core_clk_rate);
  2760. return 0;
  2761. error:
  2762. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2763. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2764. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  2765. *num_lm, drm_fixp2int(mode_clock_hz),
  2766. sde_kms->perf.max_core_clk_rate);
  2767. return rc;
  2768. }
  2769. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2770. u32 hdisplay, u32 *num_dsc)
  2771. {
  2772. struct sde_kms *sde_kms;
  2773. uint32_t max_dsc_width;
  2774. if (!num_dsc) {
  2775. SDE_ERROR("invalid num_dsc pointer\n");
  2776. return -EINVAL;
  2777. }
  2778. *num_dsc = 0;
  2779. if (!kms || !hdisplay) {
  2780. SDE_ERROR("invalid input args\n");
  2781. return -EINVAL;
  2782. }
  2783. sde_kms = to_sde_kms(kms);
  2784. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2785. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2786. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2787. hdisplay, max_dsc_width,
  2788. *num_dsc);
  2789. return 0;
  2790. }
  2791. static void _sde_kms_null_commit(struct drm_device *dev,
  2792. struct drm_encoder *enc)
  2793. {
  2794. struct drm_modeset_acquire_ctx ctx;
  2795. struct drm_connector *conn = NULL;
  2796. struct drm_connector *tmp_conn = NULL;
  2797. struct drm_connector_list_iter conn_iter;
  2798. struct drm_atomic_state *state = NULL;
  2799. struct drm_crtc_state *crtc_state = NULL;
  2800. struct drm_connector_state *conn_state = NULL;
  2801. int retry_cnt = 0;
  2802. int ret = 0;
  2803. drm_modeset_acquire_init(&ctx, 0);
  2804. retry:
  2805. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2806. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2807. drm_modeset_backoff(&ctx);
  2808. retry_cnt++;
  2809. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2810. goto retry;
  2811. } else if (WARN_ON(ret)) {
  2812. goto end;
  2813. }
  2814. state = drm_atomic_state_alloc(dev);
  2815. if (!state) {
  2816. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2817. goto end;
  2818. }
  2819. state->acquire_ctx = &ctx;
  2820. drm_connector_list_iter_begin(dev, &conn_iter);
  2821. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2822. if (enc == tmp_conn->state->best_encoder) {
  2823. conn = tmp_conn;
  2824. break;
  2825. }
  2826. }
  2827. drm_connector_list_iter_end(&conn_iter);
  2828. if (!conn) {
  2829. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2830. goto end;
  2831. }
  2832. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2833. conn_state = drm_atomic_get_connector_state(state, conn);
  2834. if (IS_ERR(conn_state)) {
  2835. SDE_ERROR("error %d getting connector %d state\n",
  2836. ret, DRMID(conn));
  2837. goto end;
  2838. }
  2839. crtc_state->active = true;
  2840. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2841. if (ret)
  2842. SDE_ERROR("error %d setting the crtc\n", ret);
  2843. ret = drm_atomic_commit(state);
  2844. if (ret)
  2845. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2846. end:
  2847. if (state)
  2848. drm_atomic_state_put(state);
  2849. drm_modeset_drop_locks(&ctx);
  2850. drm_modeset_acquire_fini(&ctx);
  2851. }
  2852. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2853. const int32_t connector_id)
  2854. {
  2855. struct drm_connector_list_iter conn_iter;
  2856. struct drm_connector *conn;
  2857. struct drm_encoder *drm_enc;
  2858. drm_connector_list_iter_begin(dev, &conn_iter);
  2859. drm_for_each_connector_iter(conn, &conn_iter) {
  2860. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2861. connector_id != conn->base.id)
  2862. continue;
  2863. if (conn->state && conn->state->best_encoder)
  2864. drm_enc = conn->state->best_encoder;
  2865. else
  2866. drm_enc = conn->encoder;
  2867. if (drm_enc)
  2868. sde_encoder_early_wakeup(drm_enc);
  2869. }
  2870. drm_connector_list_iter_end(&conn_iter);
  2871. }
  2872. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2873. struct device *dev)
  2874. {
  2875. int i, ret, crtc_id = 0;
  2876. struct drm_device *ddev = dev_get_drvdata(dev);
  2877. struct drm_connector *conn;
  2878. struct drm_connector_list_iter conn_iter;
  2879. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2880. drm_connector_list_iter_begin(ddev, &conn_iter);
  2881. drm_for_each_connector_iter(conn, &conn_iter) {
  2882. uint64_t lp;
  2883. lp = sde_connector_get_lp(conn);
  2884. if (lp != SDE_MODE_DPMS_LP2)
  2885. continue;
  2886. if (sde_encoder_in_clone_mode(conn->encoder))
  2887. continue;
  2888. ret = sde_encoder_wait_for_event(conn->encoder,
  2889. MSM_ENC_TX_COMPLETE);
  2890. if (ret && ret != -EWOULDBLOCK) {
  2891. SDE_ERROR(
  2892. "[conn: %d] wait for commit done returned %d\n",
  2893. conn->base.id, ret);
  2894. } else if (!ret) {
  2895. crtc_id = drm_crtc_index(conn->state->crtc);
  2896. if (priv->event_thread[crtc_id].thread)
  2897. kthread_flush_worker(
  2898. &priv->event_thread[crtc_id].worker);
  2899. sde_encoder_idle_request(conn->encoder);
  2900. }
  2901. }
  2902. drm_connector_list_iter_end(&conn_iter);
  2903. for (i = 0; i < priv->num_crtcs; i++) {
  2904. if (priv->disp_thread[i].thread)
  2905. kthread_flush_worker(
  2906. &priv->disp_thread[i].worker);
  2907. if (priv->event_thread[i].thread)
  2908. kthread_flush_worker(
  2909. &priv->event_thread[i].worker);
  2910. }
  2911. kthread_flush_worker(&priv->pp_event_worker);
  2912. }
  2913. struct msm_display_mode *sde_kms_get_msm_mode(struct drm_crtc_state *c_state)
  2914. {
  2915. return sde_crtc_get_msm_mode(c_state);
  2916. }
  2917. static int sde_kms_pm_suspend(struct device *dev)
  2918. {
  2919. struct drm_device *ddev;
  2920. struct drm_modeset_acquire_ctx ctx;
  2921. struct drm_connector *conn;
  2922. struct drm_encoder *enc;
  2923. struct drm_connector_list_iter conn_iter;
  2924. struct drm_atomic_state *state = NULL;
  2925. struct sde_kms *sde_kms;
  2926. int ret = 0, num_crtcs = 0;
  2927. if (!dev)
  2928. return -EINVAL;
  2929. ddev = dev_get_drvdata(dev);
  2930. if (!ddev || !ddev_to_msm_kms(ddev))
  2931. return -EINVAL;
  2932. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2933. SDE_EVT32(0);
  2934. /* disable hot-plug polling */
  2935. drm_kms_helper_poll_disable(ddev);
  2936. /* if a display stuck in CS trigger a null commit to complete handoff */
  2937. drm_for_each_encoder(enc, ddev) {
  2938. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2939. _sde_kms_null_commit(ddev, enc);
  2940. }
  2941. /* acquire modeset lock(s) */
  2942. drm_modeset_acquire_init(&ctx, 0);
  2943. retry:
  2944. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2945. if (ret)
  2946. goto unlock;
  2947. /* save current state for resume */
  2948. if (sde_kms->suspend_state)
  2949. drm_atomic_state_put(sde_kms->suspend_state);
  2950. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2951. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2952. ret = PTR_ERR(sde_kms->suspend_state);
  2953. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2954. sde_kms->suspend_state = NULL;
  2955. goto unlock;
  2956. }
  2957. /* create atomic state to disable all CRTCs */
  2958. state = drm_atomic_state_alloc(ddev);
  2959. if (!state) {
  2960. ret = -ENOMEM;
  2961. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2962. goto unlock;
  2963. }
  2964. state->acquire_ctx = &ctx;
  2965. drm_connector_list_iter_begin(ddev, &conn_iter);
  2966. drm_for_each_connector_iter(conn, &conn_iter) {
  2967. struct drm_crtc_state *crtc_state;
  2968. uint64_t lp;
  2969. if (!conn->state || !conn->state->crtc ||
  2970. conn->dpms != DRM_MODE_DPMS_ON ||
  2971. sde_encoder_in_clone_mode(conn->encoder))
  2972. continue;
  2973. lp = sde_connector_get_lp(conn);
  2974. if (lp == SDE_MODE_DPMS_LP1) {
  2975. /* transition LP1->LP2 on pm suspend */
  2976. ret = sde_connector_set_property_for_commit(conn, state,
  2977. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2978. if (ret) {
  2979. DRM_ERROR("failed to set lp2 for conn %d\n",
  2980. conn->base.id);
  2981. drm_connector_list_iter_end(&conn_iter);
  2982. goto unlock;
  2983. }
  2984. }
  2985. if (lp != SDE_MODE_DPMS_LP2) {
  2986. /* force CRTC to be inactive */
  2987. crtc_state = drm_atomic_get_crtc_state(state,
  2988. conn->state->crtc);
  2989. if (IS_ERR_OR_NULL(crtc_state)) {
  2990. DRM_ERROR("failed to get crtc %d state\n",
  2991. conn->state->crtc->base.id);
  2992. drm_connector_list_iter_end(&conn_iter);
  2993. goto unlock;
  2994. }
  2995. if (lp != SDE_MODE_DPMS_LP1)
  2996. crtc_state->active = false;
  2997. ++num_crtcs;
  2998. }
  2999. }
  3000. drm_connector_list_iter_end(&conn_iter);
  3001. /* check for nothing to do */
  3002. if (num_crtcs == 0) {
  3003. DRM_DEBUG("all crtcs are already in the off state\n");
  3004. sde_kms->suspend_block = true;
  3005. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3006. goto unlock;
  3007. }
  3008. /* commit the "disable all" state */
  3009. ret = drm_atomic_commit(state);
  3010. if (ret < 0) {
  3011. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3012. goto unlock;
  3013. }
  3014. sde_kms->suspend_block = true;
  3015. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3016. unlock:
  3017. if (state) {
  3018. drm_atomic_state_put(state);
  3019. state = NULL;
  3020. }
  3021. if (ret == -EDEADLK) {
  3022. drm_modeset_backoff(&ctx);
  3023. goto retry;
  3024. }
  3025. drm_modeset_drop_locks(&ctx);
  3026. drm_modeset_acquire_fini(&ctx);
  3027. /*
  3028. * pm runtime driver avoids multiple runtime_suspend API call by
  3029. * checking runtime_status. However, this call helps when there is a
  3030. * race condition between pm_suspend call and doze_suspend/power_off
  3031. * commit. It removes the extra vote from suspend and adds it back
  3032. * later to allow power collapse during pm_suspend call
  3033. */
  3034. pm_runtime_put_sync(dev);
  3035. pm_runtime_get_noresume(dev);
  3036. /* dump clock state before entering suspend */
  3037. if (sde_kms->pm_suspend_clk_dump)
  3038. _sde_kms_dump_clks_state(sde_kms);
  3039. return ret;
  3040. }
  3041. static int sde_kms_pm_resume(struct device *dev)
  3042. {
  3043. struct drm_device *ddev;
  3044. struct sde_kms *sde_kms;
  3045. struct drm_modeset_acquire_ctx ctx;
  3046. int ret, i;
  3047. if (!dev)
  3048. return -EINVAL;
  3049. ddev = dev_get_drvdata(dev);
  3050. if (!ddev || !ddev_to_msm_kms(ddev))
  3051. return -EINVAL;
  3052. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3053. SDE_EVT32(sde_kms->suspend_state != NULL);
  3054. drm_mode_config_reset(ddev);
  3055. drm_modeset_acquire_init(&ctx, 0);
  3056. retry:
  3057. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3058. if (ret == -EDEADLK) {
  3059. drm_modeset_backoff(&ctx);
  3060. goto retry;
  3061. } else if (WARN_ON(ret)) {
  3062. goto end;
  3063. }
  3064. sde_kms->suspend_block = false;
  3065. if (sde_kms->suspend_state) {
  3066. sde_kms->suspend_state->acquire_ctx = &ctx;
  3067. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3068. ret = drm_atomic_helper_commit_duplicated_state(
  3069. sde_kms->suspend_state, &ctx);
  3070. if (ret != -EDEADLK)
  3071. break;
  3072. drm_modeset_backoff(&ctx);
  3073. }
  3074. if (ret < 0)
  3075. DRM_ERROR("failed to restore state, %d\n", ret);
  3076. drm_atomic_state_put(sde_kms->suspend_state);
  3077. sde_kms->suspend_state = NULL;
  3078. }
  3079. end:
  3080. drm_modeset_drop_locks(&ctx);
  3081. drm_modeset_acquire_fini(&ctx);
  3082. /* enable hot-plug polling */
  3083. drm_kms_helper_poll_enable(ddev);
  3084. return 0;
  3085. }
  3086. static const struct msm_kms_funcs kms_funcs = {
  3087. .hw_init = sde_kms_hw_init,
  3088. .postinit = sde_kms_postinit,
  3089. .irq_preinstall = sde_irq_preinstall,
  3090. .irq_postinstall = sde_irq_postinstall,
  3091. .irq_uninstall = sde_irq_uninstall,
  3092. .irq = sde_irq,
  3093. .lastclose = sde_kms_lastclose,
  3094. .prepare_fence = sde_kms_prepare_fence,
  3095. .prepare_commit = sde_kms_prepare_commit,
  3096. .commit = sde_kms_commit,
  3097. .complete_commit = sde_kms_complete_commit,
  3098. .get_msm_mode = sde_kms_get_msm_mode,
  3099. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3100. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3101. .check_modified_format = sde_format_check_modified_format,
  3102. .atomic_check = sde_kms_atomic_check,
  3103. .get_format = sde_get_msm_format,
  3104. .round_pixclk = sde_kms_round_pixclk,
  3105. .display_early_wakeup = sde_kms_display_early_wakeup,
  3106. .pm_suspend = sde_kms_pm_suspend,
  3107. .pm_resume = sde_kms_pm_resume,
  3108. .destroy = sde_kms_destroy,
  3109. .debugfs_destroy = sde_kms_debugfs_destroy,
  3110. .cont_splash_config = sde_kms_cont_splash_config,
  3111. .register_events = _sde_kms_register_events,
  3112. .get_address_space = _sde_kms_get_address_space,
  3113. .get_address_space_device = _sde_kms_get_address_space_device,
  3114. .postopen = _sde_kms_post_open,
  3115. .check_for_splash = sde_kms_check_for_splash,
  3116. .get_mixer_count = sde_kms_get_mixer_count,
  3117. .get_dsc_count = sde_kms_get_dsc_count,
  3118. };
  3119. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3120. {
  3121. int i;
  3122. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3123. if (!sde_kms->aspace[i])
  3124. continue;
  3125. msm_gem_address_space_put(sde_kms->aspace[i]);
  3126. sde_kms->aspace[i] = NULL;
  3127. }
  3128. return 0;
  3129. }
  3130. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3131. {
  3132. struct msm_mmu *mmu;
  3133. int i, ret;
  3134. int early_map = 0;
  3135. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3136. return -EINVAL;
  3137. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3138. struct msm_gem_address_space *aspace;
  3139. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3140. if (IS_ERR(mmu)) {
  3141. ret = PTR_ERR(mmu);
  3142. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3143. i, ret);
  3144. continue;
  3145. }
  3146. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3147. mmu, "sde");
  3148. if (IS_ERR(aspace)) {
  3149. ret = PTR_ERR(aspace);
  3150. mmu->funcs->destroy(mmu);
  3151. goto fail;
  3152. }
  3153. sde_kms->aspace[i] = aspace;
  3154. aspace->domain_attached = true;
  3155. /* Mapping splash memory block */
  3156. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3157. sde_kms->splash_data.num_splash_regions) {
  3158. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3159. if (ret) {
  3160. SDE_ERROR("failed to map ret:%d\n", ret);
  3161. goto fail;
  3162. }
  3163. }
  3164. /*
  3165. * disable early-map which would have been enabled during
  3166. * bootup by smmu through the device-tree hint for cont-spash
  3167. */
  3168. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3169. &early_map);
  3170. if (ret) {
  3171. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3172. ret, early_map);
  3173. goto early_map_fail;
  3174. }
  3175. }
  3176. sde_kms->base.aspace = sde_kms->aspace[0];
  3177. return 0;
  3178. early_map_fail:
  3179. _sde_kms_unmap_all_splash_regions(sde_kms);
  3180. fail:
  3181. _sde_kms_mmu_destroy(sde_kms);
  3182. return ret;
  3183. }
  3184. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3185. {
  3186. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3187. return;
  3188. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3189. }
  3190. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3191. {
  3192. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3193. return;
  3194. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3195. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3196. sde_kms->catalog);
  3197. }
  3198. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3199. {
  3200. struct sde_vbif_set_qos_params qos_params;
  3201. struct sde_mdss_cfg *catalog;
  3202. if (!sde_kms->catalog)
  3203. return;
  3204. catalog = sde_kms->catalog;
  3205. memset(&qos_params, 0, sizeof(qos_params));
  3206. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3207. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3208. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3209. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3210. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3211. }
  3212. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3213. {
  3214. struct sde_hw_uidle *uidle;
  3215. if (!sde_kms) {
  3216. SDE_ERROR("invalid kms\n");
  3217. return -EINVAL;
  3218. }
  3219. uidle = sde_kms->hw_uidle;
  3220. if (uidle && uidle->ops.active_override_enable)
  3221. uidle->ops.active_override_enable(uidle, enable);
  3222. return 0;
  3223. }
  3224. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3225. {
  3226. struct device *cpu_dev;
  3227. int cpu = 0;
  3228. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3229. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3230. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3231. return;
  3232. }
  3233. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3234. cpu_dev = get_cpu_device(cpu);
  3235. if (!cpu_dev) {
  3236. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3237. cpu);
  3238. continue;
  3239. }
  3240. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3241. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3242. cpu_irq_latency);
  3243. else
  3244. dev_pm_qos_add_request(cpu_dev,
  3245. &sde_kms->pm_qos_irq_req[cpu],
  3246. DEV_PM_QOS_RESUME_LATENCY,
  3247. cpu_irq_latency);
  3248. }
  3249. }
  3250. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3251. {
  3252. struct device *cpu_dev;
  3253. int cpu = 0;
  3254. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3255. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3256. return;
  3257. }
  3258. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3259. cpu_dev = get_cpu_device(cpu);
  3260. if (!cpu_dev) {
  3261. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3262. cpu);
  3263. continue;
  3264. }
  3265. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3266. dev_pm_qos_remove_request(
  3267. &sde_kms->pm_qos_irq_req[cpu]);
  3268. }
  3269. }
  3270. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3271. {
  3272. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3273. mutex_lock(&priv->phandle.phandle_lock);
  3274. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3275. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3276. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3277. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3278. mutex_unlock(&priv->phandle.phandle_lock);
  3279. }
  3280. static void sde_kms_irq_affinity_notify(
  3281. struct irq_affinity_notify *affinity_notify,
  3282. const cpumask_t *mask)
  3283. {
  3284. struct msm_drm_private *priv;
  3285. struct sde_kms *sde_kms = container_of(affinity_notify,
  3286. struct sde_kms, affinity_notify);
  3287. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3288. return;
  3289. priv = sde_kms->dev->dev_private;
  3290. mutex_lock(&priv->phandle.phandle_lock);
  3291. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3292. // save irq cpu mask
  3293. sde_kms->irq_cpu_mask = *mask;
  3294. // request vote with updated irq cpu mask
  3295. if (atomic_read(&sde_kms->irq_vote_count))
  3296. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3297. mutex_unlock(&priv->phandle.phandle_lock);
  3298. }
  3299. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3300. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3301. {
  3302. struct sde_kms *sde_kms = usr;
  3303. struct msm_kms *msm_kms;
  3304. msm_kms = &sde_kms->base;
  3305. if (!sde_kms)
  3306. return;
  3307. SDE_DEBUG("event_type:%d\n", event_type);
  3308. SDE_EVT32_VERBOSE(event_type);
  3309. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3310. sde_irq_update(msm_kms, true);
  3311. sde_kms->first_kickoff = true;
  3312. /**
  3313. * Rotator sid needs to be programmed since uefi doesn't
  3314. * configure it during continuous splash
  3315. */
  3316. sde_kms_init_rot_sid_hw(sde_kms);
  3317. if (sde_kms->splash_data.num_splash_displays ||
  3318. sde_in_trusted_vm(sde_kms))
  3319. return;
  3320. sde_vbif_init_memtypes(sde_kms);
  3321. sde_kms_init_shared_hw(sde_kms);
  3322. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3323. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3324. sde_irq_update(msm_kms, false);
  3325. sde_kms->first_kickoff = false;
  3326. if (sde_in_trusted_vm(sde_kms))
  3327. return;
  3328. _sde_kms_active_override(sde_kms, true);
  3329. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3330. sde_vbif_axi_halt_request(sde_kms);
  3331. }
  3332. }
  3333. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3334. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3335. {
  3336. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3337. int rc = -EINVAL;
  3338. SDE_DEBUG("\n");
  3339. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3340. if (rc > 0)
  3341. rc = 0;
  3342. SDE_EVT32(rc, genpd->device_count);
  3343. return rc;
  3344. }
  3345. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3346. {
  3347. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3348. SDE_DEBUG("\n");
  3349. pm_runtime_put_sync(sde_kms->dev->dev);
  3350. SDE_EVT32(genpd->device_count);
  3351. return 0;
  3352. }
  3353. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3354. struct sde_splash_data *data)
  3355. {
  3356. int i = 0;
  3357. int ret = 0;
  3358. struct device_node *parent, *node, *node1;
  3359. struct resource r, r1;
  3360. const char *node_name = "splash_region";
  3361. struct sde_splash_mem *mem;
  3362. bool share_splash_mem = false;
  3363. int num_displays, num_regions;
  3364. struct sde_splash_display *splash_display;
  3365. if (!data)
  3366. return -EINVAL;
  3367. memset(data, 0, sizeof(*data));
  3368. parent = of_find_node_by_path("/reserved-memory");
  3369. if (!parent) {
  3370. SDE_ERROR("failed to find reserved-memory node\n");
  3371. return -EINVAL;
  3372. }
  3373. node = of_find_node_by_name(parent, node_name);
  3374. if (!node) {
  3375. SDE_DEBUG("failed to find node %s\n", node_name);
  3376. return -EINVAL;
  3377. }
  3378. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3379. if (!node1)
  3380. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3381. /**
  3382. * Support sharing a single splash memory for all the built in displays
  3383. * and also independent splash region per displays. Incase of
  3384. * independent splash region for each connected display, dtsi node of
  3385. * cont_splash_region should be collection of all memory regions
  3386. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3387. */
  3388. num_displays = dsi_display_get_num_of_displays();
  3389. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3390. data->num_splash_displays = num_displays;
  3391. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3392. if (num_displays > num_regions) {
  3393. share_splash_mem = true;
  3394. pr_info(":%d displays share same splash buf\n", num_displays);
  3395. }
  3396. for (i = 0; i < num_displays; i++) {
  3397. splash_display = &data->splash_display[i];
  3398. if (!i || !share_splash_mem) {
  3399. if (of_address_to_resource(node, i, &r)) {
  3400. SDE_ERROR("invalid data for:%s\n", node_name);
  3401. return -EINVAL;
  3402. }
  3403. mem = &data->splash_mem[i];
  3404. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3405. SDE_DEBUG("failed to find ramdump memory\n");
  3406. mem->ramdump_base = 0;
  3407. mem->ramdump_size = 0;
  3408. } else {
  3409. mem->ramdump_base = (unsigned long)r1.start;
  3410. mem->ramdump_size = (r1.end - r1.start) + 1;
  3411. }
  3412. mem->splash_buf_base = (unsigned long)r.start;
  3413. mem->splash_buf_size = (r.end - r.start) + 1;
  3414. mem->ref_cnt = 0;
  3415. splash_display->splash = mem;
  3416. data->num_splash_regions++;
  3417. } else {
  3418. data->splash_display[i].splash = &data->splash_mem[0];
  3419. }
  3420. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3421. splash_display->splash->splash_buf_base,
  3422. splash_display->splash->splash_buf_size);
  3423. }
  3424. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3425. return ret;
  3426. }
  3427. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3428. struct platform_device *platformdev)
  3429. {
  3430. int rc = -EINVAL;
  3431. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3432. if (IS_ERR(sde_kms->mmio)) {
  3433. rc = PTR_ERR(sde_kms->mmio);
  3434. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3435. sde_kms->mmio = NULL;
  3436. goto error;
  3437. }
  3438. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3439. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3440. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3441. sde_kms->mmio_len);
  3442. if (rc)
  3443. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3444. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3445. "vbif_phys");
  3446. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3447. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3448. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3449. sde_kms->vbif[VBIF_RT] = NULL;
  3450. goto error;
  3451. }
  3452. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3453. "vbif_phys");
  3454. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3455. sde_kms->vbif_len[VBIF_RT]);
  3456. if (rc)
  3457. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3458. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3459. "vbif_nrt_phys");
  3460. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3461. sde_kms->vbif[VBIF_NRT] = NULL;
  3462. SDE_DEBUG("VBIF NRT is not defined");
  3463. } else {
  3464. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3465. "vbif_nrt_phys");
  3466. rc = sde_dbg_reg_register_base("vbif_nrt",
  3467. sde_kms->vbif[VBIF_NRT],
  3468. sde_kms->vbif_len[VBIF_NRT]);
  3469. if (rc)
  3470. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3471. rc);
  3472. }
  3473. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3474. "regdma_phys");
  3475. if (IS_ERR(sde_kms->reg_dma)) {
  3476. sde_kms->reg_dma = NULL;
  3477. SDE_DEBUG("REG_DMA is not defined");
  3478. } else {
  3479. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3480. "regdma_phys");
  3481. rc = sde_dbg_reg_register_base("reg_dma",
  3482. sde_kms->reg_dma,
  3483. sde_kms->reg_dma_len);
  3484. if (rc)
  3485. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3486. rc);
  3487. }
  3488. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3489. "sid_phys");
  3490. if (IS_ERR(sde_kms->sid)) {
  3491. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3492. sde_kms->sid = NULL;
  3493. } else {
  3494. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3495. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3496. sde_kms->sid_len);
  3497. if (rc)
  3498. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3499. }
  3500. error:
  3501. return rc;
  3502. }
  3503. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3504. struct sde_kms *sde_kms)
  3505. {
  3506. int rc = 0;
  3507. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3508. sde_kms->genpd.name = dev->unique;
  3509. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3510. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3511. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3512. if (rc < 0) {
  3513. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3514. sde_kms->genpd.name, rc);
  3515. return rc;
  3516. }
  3517. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3518. &sde_kms->genpd);
  3519. if (rc < 0) {
  3520. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3521. sde_kms->genpd.name, rc);
  3522. pm_genpd_remove(&sde_kms->genpd);
  3523. return rc;
  3524. }
  3525. sde_kms->genpd_init = true;
  3526. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3527. }
  3528. return rc;
  3529. }
  3530. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3531. struct drm_device *dev,
  3532. struct msm_drm_private *priv)
  3533. {
  3534. struct sde_rm *rm = NULL;
  3535. int i, rc = -EINVAL;
  3536. sde_kms->catalog = sde_hw_catalog_init(dev);
  3537. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3538. rc = PTR_ERR(sde_kms->catalog);
  3539. if (!sde_kms->catalog)
  3540. rc = -EINVAL;
  3541. SDE_ERROR("catalog init failed: %d\n", rc);
  3542. sde_kms->catalog = NULL;
  3543. goto power_error;
  3544. }
  3545. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3546. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3547. /* initialize power domain if defined */
  3548. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3549. if (rc) {
  3550. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3551. goto genpd_err;
  3552. }
  3553. rc = _sde_kms_mmu_init(sde_kms);
  3554. if (rc) {
  3555. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3556. goto power_error;
  3557. }
  3558. /* Initialize reg dma block which is a singleton */
  3559. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3560. sde_kms->dev);
  3561. if (rc) {
  3562. SDE_ERROR("failed: reg dma init failed\n");
  3563. goto power_error;
  3564. }
  3565. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3566. rm = &sde_kms->rm;
  3567. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3568. sde_kms->dev);
  3569. if (rc) {
  3570. SDE_ERROR("rm init failed: %d\n", rc);
  3571. goto power_error;
  3572. }
  3573. sde_kms->rm_init = true;
  3574. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3575. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3576. rc = PTR_ERR(sde_kms->hw_intr);
  3577. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3578. sde_kms->hw_intr = NULL;
  3579. goto hw_intr_init_err;
  3580. }
  3581. /*
  3582. * Attempt continuous splash handoff only if reserved
  3583. * splash memory is found & release resources on any error
  3584. * in finding display hw config in splash
  3585. */
  3586. if (sde_kms->splash_data.num_splash_regions) {
  3587. struct sde_splash_display *display;
  3588. int ret, display_count =
  3589. sde_kms->splash_data.num_splash_displays;
  3590. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3591. &sde_kms->splash_data, sde_kms->catalog);
  3592. for (i = 0; i < display_count; i++) {
  3593. display = &sde_kms->splash_data.splash_display[i];
  3594. /*
  3595. * free splash region on resource init failure and
  3596. * cont-splash disabled case
  3597. */
  3598. if (!display->cont_splash_enabled || ret)
  3599. _sde_kms_free_splash_display_data(
  3600. sde_kms, display);
  3601. }
  3602. }
  3603. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3604. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3605. rc = PTR_ERR(sde_kms->hw_mdp);
  3606. if (!sde_kms->hw_mdp)
  3607. rc = -EINVAL;
  3608. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3609. sde_kms->hw_mdp = NULL;
  3610. goto power_error;
  3611. }
  3612. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3613. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3614. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3615. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3616. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3617. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3618. if (!sde_kms->hw_vbif[vbif_idx])
  3619. rc = -EINVAL;
  3620. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3621. sde_kms->hw_vbif[vbif_idx] = NULL;
  3622. goto power_error;
  3623. }
  3624. }
  3625. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3626. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3627. sde_kms->mmio_len, sde_kms->catalog);
  3628. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3629. rc = PTR_ERR(sde_kms->hw_uidle);
  3630. if (!sde_kms->hw_uidle)
  3631. rc = -EINVAL;
  3632. /* uidle is optional, so do not make it a fatal error */
  3633. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3634. sde_kms->hw_uidle = NULL;
  3635. rc = 0;
  3636. }
  3637. } else {
  3638. sde_kms->hw_uidle = NULL;
  3639. }
  3640. if (sde_kms->sid) {
  3641. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3642. sde_kms->sid_len, sde_kms->catalog);
  3643. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3644. rc = PTR_ERR(sde_kms->hw_sid);
  3645. SDE_ERROR("failed to init sid %ld\n", rc);
  3646. sde_kms->hw_sid = NULL;
  3647. goto power_error;
  3648. }
  3649. }
  3650. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3651. &priv->phandle, "core_clk");
  3652. if (rc) {
  3653. SDE_ERROR("failed to init perf %d\n", rc);
  3654. goto perf_err;
  3655. }
  3656. /*
  3657. * set the disable_immediate flag when driver supports the precise vsync
  3658. * timestamp as the DRM hooks for vblank timestamp/counters would be set
  3659. * based on the feature
  3660. */
  3661. if (sde_kms->catalog->has_precise_vsync_ts)
  3662. dev->vblank_disable_immediate = true;
  3663. /*
  3664. * _sde_kms_drm_obj_init should create the DRM related objects
  3665. * i.e. CRTCs, planes, encoders, connectors and so forth
  3666. */
  3667. rc = _sde_kms_drm_obj_init(sde_kms);
  3668. if (rc) {
  3669. SDE_ERROR("modeset init failed: %d\n", rc);
  3670. goto drm_obj_init_err;
  3671. }
  3672. return 0;
  3673. genpd_err:
  3674. drm_obj_init_err:
  3675. sde_core_perf_destroy(&sde_kms->perf);
  3676. hw_intr_init_err:
  3677. perf_err:
  3678. power_error:
  3679. return rc;
  3680. }
  3681. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3682. {
  3683. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3684. int rc = 0;
  3685. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3686. if (rc) {
  3687. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3688. return rc;
  3689. }
  3690. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3691. if (rc) {
  3692. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3693. return rc;
  3694. }
  3695. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3696. if (rc) {
  3697. SDE_ERROR("failed to get io irq for KMS");
  3698. return rc;
  3699. }
  3700. return rc;
  3701. }
  3702. static int sde_kms_hw_init(struct msm_kms *kms)
  3703. {
  3704. struct sde_kms *sde_kms;
  3705. struct drm_device *dev;
  3706. struct msm_drm_private *priv;
  3707. struct platform_device *platformdev;
  3708. int i, irq_num, rc = -EINVAL;
  3709. if (!kms) {
  3710. SDE_ERROR("invalid kms\n");
  3711. goto end;
  3712. }
  3713. sde_kms = to_sde_kms(kms);
  3714. dev = sde_kms->dev;
  3715. if (!dev || !dev->dev) {
  3716. SDE_ERROR("invalid device\n");
  3717. goto end;
  3718. }
  3719. platformdev = to_platform_device(dev->dev);
  3720. priv = dev->dev_private;
  3721. if (!priv) {
  3722. SDE_ERROR("invalid private data\n");
  3723. goto end;
  3724. }
  3725. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3726. if (rc)
  3727. goto error;
  3728. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3729. if (rc)
  3730. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3731. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3732. if (rc)
  3733. goto error;
  3734. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3735. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3736. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3737. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3738. mutex_init(&sde_kms->secure_transition_lock);
  3739. atomic_set(&sde_kms->detach_sec_cb, 0);
  3740. atomic_set(&sde_kms->detach_all_cb, 0);
  3741. atomic_set(&sde_kms->irq_vote_count, 0);
  3742. /*
  3743. * Support format modifiers for compression etc.
  3744. */
  3745. dev->mode_config.allow_fb_modifiers = true;
  3746. /*
  3747. * Handle (re)initializations during power enable
  3748. */
  3749. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3750. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3751. SDE_POWER_EVENT_POST_ENABLE |
  3752. SDE_POWER_EVENT_PRE_DISABLE,
  3753. sde_kms_handle_power_event, sde_kms, "kms");
  3754. if (sde_kms->splash_data.num_splash_displays) {
  3755. SDE_DEBUG("Skipping MDP Resources disable\n");
  3756. } else {
  3757. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3758. sde_power_data_bus_set_quota(&priv->phandle, i,
  3759. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3760. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3761. pm_runtime_put_sync(sde_kms->dev->dev);
  3762. }
  3763. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3764. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3765. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3766. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3767. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3768. if (sde_in_trusted_vm(sde_kms))
  3769. rc = sde_vm_trusted_init(sde_kms);
  3770. else
  3771. rc = sde_vm_primary_init(sde_kms);
  3772. if (rc) {
  3773. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3774. goto error;
  3775. }
  3776. return 0;
  3777. error:
  3778. _sde_kms_hw_destroy(sde_kms, platformdev);
  3779. end:
  3780. return rc;
  3781. }
  3782. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3783. {
  3784. struct msm_drm_private *priv;
  3785. struct sde_kms *sde_kms;
  3786. if (!dev || !dev->dev_private) {
  3787. SDE_ERROR("drm device node invalid\n");
  3788. return ERR_PTR(-EINVAL);
  3789. }
  3790. priv = dev->dev_private;
  3791. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3792. if (!sde_kms) {
  3793. SDE_ERROR("failed to allocate sde kms\n");
  3794. return ERR_PTR(-ENOMEM);
  3795. }
  3796. msm_kms_init(&sde_kms->base, &kms_funcs);
  3797. sde_kms->dev = dev;
  3798. return &sde_kms->base;
  3799. }
  3800. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3801. {
  3802. struct dsi_display *display;
  3803. struct sde_splash_display *handoff_display;
  3804. int i;
  3805. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3806. handoff_display = &sde_kms->splash_data.splash_display[i];
  3807. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3808. if (handoff_display->cont_splash_enabled)
  3809. _sde_kms_free_splash_display_data(sde_kms,
  3810. handoff_display);
  3811. dsi_display_set_active_state(display, false);
  3812. }
  3813. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3814. }
  3815. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  3816. struct drm_atomic_state *state)
  3817. {
  3818. struct drm_device *dev;
  3819. struct msm_drm_private *priv;
  3820. struct sde_splash_display *handoff_display;
  3821. struct dsi_display *display;
  3822. int ret, i;
  3823. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3824. SDE_ERROR("invalid params\n");
  3825. return -EINVAL;
  3826. }
  3827. dev = sde_kms->dev;
  3828. priv = dev->dev_private;
  3829. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3830. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3831. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3832. &sde_kms->splash_data, sde_kms->catalog);
  3833. if (ret) {
  3834. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  3835. return -EINVAL;
  3836. }
  3837. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3838. handoff_display = &sde_kms->splash_data.splash_display[i];
  3839. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3840. if (!handoff_display->cont_splash_enabled || ret)
  3841. _sde_kms_free_splash_display_data(sde_kms,
  3842. handoff_display);
  3843. else
  3844. dsi_display_set_active_state(display, true);
  3845. }
  3846. if (sde_kms->splash_data.num_splash_displays != 1) {
  3847. SDE_ERROR("no. of displays not supported:%d\n",
  3848. sde_kms->splash_data.num_splash_displays);
  3849. goto error;
  3850. }
  3851. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  3852. if (ret) {
  3853. SDE_ERROR("error in setting handoff configs\n");
  3854. goto error;
  3855. }
  3856. /**
  3857. * fill-in vote for the continuous splash hanodff path, which will be
  3858. * removed on the successful first commit.
  3859. */
  3860. pm_runtime_get_sync(sde_kms->dev->dev);
  3861. return 0;
  3862. error:
  3863. return ret;
  3864. }
  3865. static int _sde_kms_register_events(struct msm_kms *kms,
  3866. struct drm_mode_object *obj, u32 event, bool en)
  3867. {
  3868. int ret = 0;
  3869. struct drm_crtc *crtc = NULL;
  3870. struct drm_connector *conn = NULL;
  3871. struct sde_kms *sde_kms = NULL;
  3872. struct sde_vm_ops *vm_ops;
  3873. if (!kms || !obj) {
  3874. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3875. return -EINVAL;
  3876. }
  3877. sde_kms = to_sde_kms(kms);
  3878. /* check vm ownership, if event registration requires HW access */
  3879. switch (obj->type) {
  3880. case DRM_MODE_OBJECT_CRTC:
  3881. vm_ops = sde_vm_get_ops(sde_kms);
  3882. sde_vm_lock(sde_kms);
  3883. if (vm_ops && vm_ops->vm_owns_hw
  3884. && !vm_ops->vm_owns_hw(sde_kms)) {
  3885. sde_vm_unlock(sde_kms);
  3886. SDE_DEBUG("HW is owned by other VM\n");
  3887. return -EACCES;
  3888. }
  3889. crtc = obj_to_crtc(obj);
  3890. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3891. sde_vm_unlock(sde_kms);
  3892. break;
  3893. case DRM_MODE_OBJECT_CONNECTOR:
  3894. conn = obj_to_connector(obj);
  3895. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3896. en);
  3897. break;
  3898. }
  3899. return ret;
  3900. }
  3901. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3902. {
  3903. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3904. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3905. }