dp_ipa.c 124 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifdef IPA_OFFLOAD
  18. #include <wlan_ipa_ucfg_api.h>
  19. #include <wlan_ipa_core.h>
  20. #include <qdf_ipa_wdi3.h>
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <hal_hw_headers.h>
  24. #include <hal_api.h>
  25. #include <hal_reo.h>
  26. #include <hif.h>
  27. #include <htt.h>
  28. #include <wdi_event.h>
  29. #include <queue.h>
  30. #include "dp_types.h"
  31. #include "dp_htt.h"
  32. #include "dp_tx.h"
  33. #include "dp_rx.h"
  34. #include "dp_ipa.h"
  35. #include "dp_internal.h"
  36. #ifdef WIFI_MONITOR_SUPPORT
  37. #include "dp_mon.h"
  38. #endif
  39. #ifdef FEATURE_WDS
  40. #include "dp_txrx_wds.h"
  41. #endif
  42. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  43. #include <pld_common.h>
  44. #endif
  45. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  46. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  47. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  48. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  49. * This causes back pressure, resulting in a FW crash.
  50. * By leaving some entries with no buffer attached, WBM will be able to write
  51. * to the ring, and from dumps we can figure out the buffer which is causing
  52. * this issue.
  53. */
  54. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  55. /**
  56. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  57. * @timestamp: Timestamp when remap occurs
  58. * @ix0_reg: reo destination ring IX0 value
  59. * @ix2_reg: reo destination ring IX2 value
  60. * @ix3_reg: reo destination ring IX3 value
  61. */
  62. struct dp_ipa_reo_remap_record {
  63. uint64_t timestamp;
  64. uint32_t ix0_reg;
  65. uint32_t ix2_reg;
  66. uint32_t ix3_reg;
  67. };
  68. #define WLAN_IPA_AST_META_DATA_MASK htonl(0x000000FF)
  69. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  70. #define REO_REMAP_HISTORY_SIZE 32
  71. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  72. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  73. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  74. {
  75. int next = qdf_atomic_inc_return(index);
  76. if (next == REO_REMAP_HISTORY_SIZE)
  77. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  78. return next % REO_REMAP_HISTORY_SIZE;
  79. }
  80. /**
  81. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  82. * @ix0_val: reo destination ring IX0 value
  83. * @ix2_val: reo destination ring IX2 value
  84. * @ix3_val: reo destination ring IX3 value
  85. *
  86. * Return: None
  87. */
  88. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  89. uint32_t ix3_val)
  90. {
  91. int idx = dp_ipa_reo_remap_record_index_next(
  92. &dp_ipa_reo_remap_history_index);
  93. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  94. record->timestamp = qdf_get_log_timestamp();
  95. record->ix0_reg = ix0_val;
  96. record->ix2_reg = ix2_val;
  97. record->ix3_reg = ix3_val;
  98. }
  99. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  100. qdf_nbuf_t nbuf,
  101. uint32_t size,
  102. bool create,
  103. const char *func,
  104. uint32_t line)
  105. {
  106. qdf_mem_info_t mem_map_table = {0};
  107. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  108. qdf_ipa_wdi_hdl_t hdl;
  109. /* Need to handle the case when one soc will
  110. * have multiple pdev(radio's), Currently passing
  111. * pdev_id as 0 assuming 1 soc has only 1 radio.
  112. */
  113. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  114. if (hdl == DP_IPA_HDL_INVALID) {
  115. dp_err("IPA handle is invalid");
  116. return QDF_STATUS_E_INVAL;
  117. }
  118. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  119. qdf_nbuf_get_frag_paddr(nbuf, 0),
  120. size);
  121. if (create) {
  122. /* Assert if PA is zero */
  123. qdf_assert_always(mem_map_table.pa);
  124. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  125. func, line);
  126. } else {
  127. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  128. func, line);
  129. }
  130. qdf_assert_always(!ret);
  131. /* Return status of mapping/unmapping is stored in
  132. * mem_map_table.result field, assert if the result
  133. * is failure
  134. */
  135. if (create)
  136. qdf_assert_always(!mem_map_table.result);
  137. else
  138. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  139. return ret;
  140. }
  141. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  142. qdf_nbuf_t nbuf,
  143. uint32_t size,
  144. bool create, const char *func,
  145. uint32_t line)
  146. {
  147. struct dp_pdev *pdev;
  148. int i;
  149. for (i = 0; i < soc->pdev_count; i++) {
  150. pdev = soc->pdev_list[i];
  151. if (pdev && dp_monitor_is_configured(pdev))
  152. return QDF_STATUS_SUCCESS;
  153. }
  154. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  155. !qdf_mem_smmu_s1_enabled(soc->osdev))
  156. return QDF_STATUS_SUCCESS;
  157. /*
  158. * Even if ipa pipes is disabled, but if it's unmap
  159. * operation and nbuf has done ipa smmu map before,
  160. * do ipa smmu unmap as well.
  161. */
  162. if (!(qdf_atomic_read(&soc->ipa_pipes_enabled) &&
  163. qdf_atomic_read(&soc->ipa_map_allowed))) {
  164. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  165. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  166. } else {
  167. return QDF_STATUS_SUCCESS;
  168. }
  169. }
  170. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  171. if (create) {
  172. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  173. } else {
  174. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  175. }
  176. return QDF_STATUS_E_INVAL;
  177. }
  178. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  179. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  180. func, line);
  181. }
  182. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  183. struct dp_soc *soc,
  184. struct dp_pdev *pdev,
  185. bool create,
  186. const char *func,
  187. uint32_t line)
  188. {
  189. uint32_t index;
  190. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  191. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  192. qdf_nbuf_t nbuf;
  193. uint32_t buf_len;
  194. if (!ipa_is_ready()) {
  195. dp_info("IPA is not READY");
  196. return 0;
  197. }
  198. for (index = 0; index < tx_buffer_cnt; index++) {
  199. nbuf = (qdf_nbuf_t)
  200. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  201. if (!nbuf)
  202. continue;
  203. buf_len = qdf_nbuf_get_data_len(nbuf);
  204. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  205. create, func, line);
  206. }
  207. return ret;
  208. }
  209. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  210. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  211. bool lock_required)
  212. {
  213. hal_ring_handle_t hal_ring_hdl;
  214. int ring;
  215. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  216. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  217. hal_srng_lock(hal_ring_hdl);
  218. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  219. hal_srng_unlock(hal_ring_hdl);
  220. }
  221. }
  222. #else
  223. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  224. bool lock_required)
  225. {
  226. }
  227. #endif
  228. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  229. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  230. struct dp_pdev *pdev,
  231. bool create,
  232. const char *func,
  233. uint32_t line)
  234. {
  235. struct rx_desc_pool *rx_pool;
  236. uint8_t pdev_id;
  237. uint32_t num_desc, page_id, offset, i;
  238. uint16_t num_desc_per_page;
  239. union dp_rx_desc_list_elem_t *rx_desc_elem;
  240. struct dp_rx_desc *rx_desc;
  241. qdf_nbuf_t nbuf;
  242. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  243. if (!qdf_ipa_is_ready())
  244. return ret;
  245. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  246. return ret;
  247. pdev_id = pdev->pdev_id;
  248. rx_pool = &soc->rx_desc_buf[pdev_id];
  249. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  250. qdf_spin_lock_bh(&rx_pool->lock);
  251. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  252. num_desc = rx_pool->pool_size;
  253. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  254. for (i = 0; i < num_desc; i++) {
  255. page_id = i / num_desc_per_page;
  256. offset = i % num_desc_per_page;
  257. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  258. break;
  259. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  260. rx_desc = &rx_desc_elem->rx_desc;
  261. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  262. continue;
  263. nbuf = rx_desc->nbuf;
  264. if (qdf_unlikely(create ==
  265. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  266. if (create) {
  267. DP_STATS_INC(soc,
  268. rx.err.ipa_smmu_map_dup, 1);
  269. } else {
  270. DP_STATS_INC(soc,
  271. rx.err.ipa_smmu_unmap_dup, 1);
  272. }
  273. continue;
  274. }
  275. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  276. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  277. rx_pool->buf_size,
  278. create, func, line);
  279. }
  280. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  281. qdf_spin_unlock_bh(&rx_pool->lock);
  282. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  283. return ret;
  284. }
  285. #else
  286. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  287. struct dp_soc *soc,
  288. struct dp_pdev *pdev,
  289. bool create,
  290. const char *func,
  291. uint32_t line)
  292. {
  293. struct rx_desc_pool *rx_pool;
  294. uint8_t pdev_id;
  295. qdf_nbuf_t nbuf;
  296. int i;
  297. if (!qdf_ipa_is_ready())
  298. return QDF_STATUS_SUCCESS;
  299. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  300. return QDF_STATUS_SUCCESS;
  301. pdev_id = pdev->pdev_id;
  302. rx_pool = &soc->rx_desc_buf[pdev_id];
  303. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  304. qdf_spin_lock_bh(&rx_pool->lock);
  305. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  306. for (i = 0; i < rx_pool->pool_size; i++) {
  307. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  308. rx_pool->array[i].rx_desc.unmapped)
  309. continue;
  310. nbuf = rx_pool->array[i].rx_desc.nbuf;
  311. if (qdf_unlikely(create ==
  312. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  313. if (create) {
  314. DP_STATS_INC(soc,
  315. rx.err.ipa_smmu_map_dup, 1);
  316. } else {
  317. DP_STATS_INC(soc,
  318. rx.err.ipa_smmu_unmap_dup, 1);
  319. }
  320. continue;
  321. }
  322. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  323. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  324. create, func, line);
  325. }
  326. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  327. qdf_spin_unlock_bh(&rx_pool->lock);
  328. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  329. return QDF_STATUS_SUCCESS;
  330. }
  331. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  332. QDF_STATUS dp_ipa_set_smmu_mapped(struct cdp_soc_t *soc_hdl, int val)
  333. {
  334. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  335. qdf_atomic_set(&soc->ipa_map_allowed, val);
  336. return QDF_STATUS_SUCCESS;
  337. }
  338. int dp_ipa_get_smmu_mapped(struct cdp_soc_t *soc_hdl)
  339. {
  340. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  341. return qdf_atomic_read(&soc->ipa_map_allowed);
  342. }
  343. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  344. qdf_shared_mem_t *shared_mem,
  345. void *cpu_addr,
  346. qdf_dma_addr_t dma_addr,
  347. uint32_t size)
  348. {
  349. qdf_dma_addr_t paddr;
  350. int ret;
  351. shared_mem->vaddr = cpu_addr;
  352. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  353. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  354. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  355. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  356. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  357. shared_mem->vaddr, dma_addr, size);
  358. if (ret) {
  359. dp_err("Unable to get DMA sgtable");
  360. return QDF_STATUS_E_NOMEM;
  361. }
  362. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  363. return QDF_STATUS_SUCCESS;
  364. }
  365. /**
  366. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  367. * @soc: dp_soc handle
  368. * @bank_id: out parameter for bank id
  369. *
  370. * Return: QDF_STATUS
  371. */
  372. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  373. {
  374. if (soc->arch_ops.ipa_get_bank_id) {
  375. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  376. if (*bank_id < 0) {
  377. return QDF_STATUS_E_INVAL;
  378. } else {
  379. dp_info("bank_id %u", *bank_id);
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. } else {
  383. return QDF_STATUS_E_NOSUPPORT;
  384. }
  385. }
  386. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  387. defined(CONFIG_IPA_WDI_UNIFIED_API)
  388. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  389. qdf_ipa_wdi_pipe_setup_info_t *tx)
  390. {
  391. uint8_t bank_id;
  392. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  393. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  394. }
  395. static void
  396. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  397. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  398. {
  399. uint8_t bank_id;
  400. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  401. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  402. }
  403. #else
  404. static inline void
  405. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  406. qdf_ipa_wdi_pipe_setup_info_t *tx)
  407. {
  408. }
  409. static inline void
  410. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  411. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  412. {
  413. }
  414. #endif
  415. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  416. static void
  417. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  418. qdf_ipa_wdi_pipe_setup_info_t *tx)
  419. {
  420. uint8_t pmac_id = 0;
  421. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  422. if (soc->pdev_count > 1)
  423. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  424. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  425. }
  426. static void
  427. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  428. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  429. {
  430. uint8_t pmac_id = 0;
  431. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  432. if (soc->pdev_count > 1)
  433. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  434. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  435. }
  436. static void
  437. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  438. qdf_ipa_wdi_pipe_setup_info_t *tx)
  439. {
  440. uint8_t pmac_id;
  441. pmac_id = soc->pdev_list[0]->lmac_id;
  442. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  443. }
  444. static void
  445. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  446. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  447. {
  448. uint8_t pmac_id;
  449. pmac_id = soc->pdev_list[0]->lmac_id;
  450. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  451. }
  452. #else
  453. static inline void
  454. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  455. qdf_ipa_wdi_pipe_setup_info_t *tx)
  456. {
  457. }
  458. static inline void
  459. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  460. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  461. {
  462. }
  463. static inline void
  464. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  465. qdf_ipa_wdi_pipe_setup_info_t *tx)
  466. {
  467. }
  468. static inline void
  469. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  470. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  471. {
  472. }
  473. #endif
  474. #ifdef IPA_WDI3_TX_TWO_PIPES
  475. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  476. {
  477. struct dp_ipa_resources *ipa_res;
  478. qdf_nbuf_t nbuf;
  479. int idx;
  480. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  481. nbuf = (qdf_nbuf_t)
  482. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  483. if (!nbuf)
  484. continue;
  485. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  486. qdf_mem_dp_tx_skb_cnt_dec();
  487. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  488. qdf_nbuf_free(nbuf);
  489. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  490. (void *)NULL;
  491. }
  492. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  493. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  494. ipa_res = &pdev->ipa_resource;
  495. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  496. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  497. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  498. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  499. }
  500. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  501. {
  502. uint32_t tx_buffer_count;
  503. uint32_t ring_base_align = 8;
  504. qdf_dma_addr_t buffer_paddr;
  505. struct hal_srng *wbm_srng = (struct hal_srng *)
  506. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  507. struct hal_srng_params srng_params;
  508. uint32_t wbm_bm_id;
  509. void *ring_entry;
  510. int num_entries;
  511. qdf_nbuf_t nbuf;
  512. int retval = QDF_STATUS_SUCCESS;
  513. int max_alloc_count = 0;
  514. /*
  515. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  516. * unsigned int uc_tx_buf_sz =
  517. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  518. */
  519. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  520. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  521. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  522. IPA_TX_ALT_RING_IDX);
  523. hal_get_srng_params(soc->hal_soc,
  524. hal_srng_to_hal_ring_handle(wbm_srng),
  525. &srng_params);
  526. num_entries = srng_params.num_entries;
  527. max_alloc_count =
  528. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  529. if (max_alloc_count <= 0) {
  530. dp_err("incorrect value for buffer count %u", max_alloc_count);
  531. return -EINVAL;
  532. }
  533. dp_info("requested %d buffers to be posted to wbm ring",
  534. max_alloc_count);
  535. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  536. qdf_mem_malloc(num_entries *
  537. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  538. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  539. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  540. return -ENOMEM;
  541. }
  542. hal_srng_access_start_unlocked(soc->hal_soc,
  543. hal_srng_to_hal_ring_handle(wbm_srng));
  544. /*
  545. * Allocate Tx buffers as many as possible.
  546. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  547. * Populate Tx buffers into WBM2IPA ring
  548. * This initial buffer population will simulate H/W as source ring,
  549. * and update HP
  550. */
  551. for (tx_buffer_count = 0;
  552. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  553. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  554. 256, FALSE);
  555. if (!nbuf)
  556. break;
  557. ring_entry = hal_srng_dst_get_next_hp(
  558. soc->hal_soc,
  559. hal_srng_to_hal_ring_handle(wbm_srng));
  560. if (!ring_entry) {
  561. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  562. "%s: Failed to get WBM ring entry",
  563. __func__);
  564. qdf_nbuf_free(nbuf);
  565. break;
  566. }
  567. qdf_nbuf_map_single(soc->osdev, nbuf,
  568. QDF_DMA_BIDIRECTIONAL);
  569. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  570. qdf_mem_dp_tx_skb_cnt_inc();
  571. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  572. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  573. buffer_paddr, 0, wbm_bm_id);
  574. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  575. tx_buffer_count] = (void *)nbuf;
  576. }
  577. hal_srng_access_end_unlocked(soc->hal_soc,
  578. hal_srng_to_hal_ring_handle(wbm_srng));
  579. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  580. if (tx_buffer_count) {
  581. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  582. } else {
  583. dp_err("Failed to allocate IPA TX buffer pool2");
  584. qdf_mem_free(
  585. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  586. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  587. retval = -ENOMEM;
  588. }
  589. return retval;
  590. }
  591. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  592. {
  593. struct dp_soc *soc = pdev->soc;
  594. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  595. ipa_res->tx_alt_ring_num_alloc_buffer =
  596. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  597. dp_ipa_get_shared_mem_info(
  598. soc->osdev, &ipa_res->tx_alt_ring,
  599. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  600. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  601. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  602. dp_ipa_get_shared_mem_info(
  603. soc->osdev, &ipa_res->tx_alt_comp_ring,
  604. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  605. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  606. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  607. if (!qdf_mem_get_dma_addr(soc->osdev,
  608. &ipa_res->tx_alt_comp_ring.mem_info))
  609. return QDF_STATUS_E_FAILURE;
  610. return QDF_STATUS_SUCCESS;
  611. }
  612. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  613. {
  614. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  615. struct hal_srng *hal_srng;
  616. struct hal_srng_params srng_params;
  617. unsigned long addr_offset, dev_base_paddr;
  618. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  619. hal_srng = (struct hal_srng *)
  620. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  621. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  622. hal_srng_to_hal_ring_handle(hal_srng),
  623. &srng_params);
  624. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  625. srng_params.ring_base_paddr;
  626. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  627. srng_params.ring_base_vaddr;
  628. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  629. (srng_params.num_entries * srng_params.entry_size) << 2;
  630. /*
  631. * For the register backed memory addresses, use the scn->mem_pa to
  632. * calculate the physical address of the shadow registers
  633. */
  634. dev_base_paddr =
  635. (unsigned long)
  636. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  637. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  638. (unsigned long)(hal_soc->dev_base_addr);
  639. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  640. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  641. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  642. (unsigned int)addr_offset,
  643. (unsigned int)dev_base_paddr,
  644. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  645. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  646. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  647. srng_params.num_entries,
  648. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  649. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  650. hal_srng = (struct hal_srng *)
  651. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  652. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  653. hal_srng_to_hal_ring_handle(hal_srng),
  654. &srng_params);
  655. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  656. srng_params.ring_base_paddr;
  657. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  658. srng_params.ring_base_vaddr;
  659. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  660. (srng_params.num_entries * srng_params.entry_size) << 2;
  661. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  662. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  663. hal_srng_to_hal_ring_handle(hal_srng));
  664. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  665. (unsigned long)(hal_soc->dev_base_addr);
  666. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  667. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  668. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  669. (unsigned int)addr_offset,
  670. (unsigned int)dev_base_paddr,
  671. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  672. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  673. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  674. srng_params.num_entries,
  675. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  676. }
  677. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  678. {
  679. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  680. uint32_t rx_ready_doorbell_dmaaddr;
  681. uint32_t tx_comp_doorbell_dmaaddr;
  682. struct dp_soc *soc = pdev->soc;
  683. int ret = 0;
  684. if (ipa_res->is_db_ddr_mapped)
  685. ipa_res->tx_comp_doorbell_vaddr =
  686. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  687. else
  688. ipa_res->tx_comp_doorbell_vaddr =
  689. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  690. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  691. ret = pld_smmu_map(soc->osdev->dev,
  692. ipa_res->tx_comp_doorbell_paddr,
  693. &tx_comp_doorbell_dmaaddr,
  694. sizeof(uint32_t));
  695. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  696. qdf_assert_always(!ret);
  697. ret = pld_smmu_map(soc->osdev->dev,
  698. ipa_res->rx_ready_doorbell_paddr,
  699. &rx_ready_doorbell_dmaaddr,
  700. sizeof(uint32_t));
  701. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  702. qdf_assert_always(!ret);
  703. }
  704. /* Setup for alternative TX pipe */
  705. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  706. return;
  707. if (ipa_res->is_db_ddr_mapped)
  708. ipa_res->tx_alt_comp_doorbell_vaddr =
  709. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  710. else
  711. ipa_res->tx_alt_comp_doorbell_vaddr =
  712. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  713. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  714. ret = pld_smmu_map(soc->osdev->dev,
  715. ipa_res->tx_alt_comp_doorbell_paddr,
  716. &tx_comp_doorbell_dmaaddr,
  717. sizeof(uint32_t));
  718. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  719. qdf_assert_always(!ret);
  720. }
  721. }
  722. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  723. {
  724. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  725. struct dp_soc *soc = pdev->soc;
  726. int ret = 0;
  727. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  728. return;
  729. /* Unmap must be in reverse order of map */
  730. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  731. ret = pld_smmu_unmap(soc->osdev->dev,
  732. ipa_res->tx_alt_comp_doorbell_paddr,
  733. sizeof(uint32_t));
  734. qdf_assert_always(!ret);
  735. }
  736. ret = pld_smmu_unmap(soc->osdev->dev,
  737. ipa_res->rx_ready_doorbell_paddr,
  738. sizeof(uint32_t));
  739. qdf_assert_always(!ret);
  740. ret = pld_smmu_unmap(soc->osdev->dev,
  741. ipa_res->tx_comp_doorbell_paddr,
  742. sizeof(uint32_t));
  743. qdf_assert_always(!ret);
  744. }
  745. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  746. struct dp_pdev *pdev,
  747. bool create, const char *func,
  748. uint32_t line)
  749. {
  750. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  751. struct ipa_dp_tx_rsc *rsc;
  752. uint32_t tx_buffer_cnt;
  753. uint32_t buf_len;
  754. qdf_nbuf_t nbuf;
  755. uint32_t index;
  756. if (!ipa_is_ready()) {
  757. dp_info("IPA is not READY");
  758. return QDF_STATUS_SUCCESS;
  759. }
  760. rsc = &soc->ipa_uc_tx_rsc_alt;
  761. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  762. for (index = 0; index < tx_buffer_cnt; index++) {
  763. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  764. if (!nbuf)
  765. continue;
  766. buf_len = qdf_nbuf_get_data_len(nbuf);
  767. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  768. create, func, line);
  769. }
  770. return ret;
  771. }
  772. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  773. struct dp_ipa_resources *ipa_res,
  774. qdf_ipa_wdi_pipe_setup_info_t *tx)
  775. {
  776. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  777. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  778. qdf_mem_get_dma_addr(soc->osdev,
  779. &ipa_res->tx_alt_comp_ring.mem_info);
  780. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  781. qdf_mem_get_dma_size(soc->osdev,
  782. &ipa_res->tx_alt_comp_ring.mem_info);
  783. /* WBM Tail Pointer Address */
  784. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  785. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  786. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  787. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  788. qdf_mem_get_dma_addr(soc->osdev,
  789. &ipa_res->tx_alt_ring.mem_info);
  790. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  791. qdf_mem_get_dma_size(soc->osdev,
  792. &ipa_res->tx_alt_ring.mem_info);
  793. /* TCL Head Pointer Address */
  794. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  795. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  796. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  797. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  798. ipa_res->tx_alt_ring_num_alloc_buffer;
  799. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  800. dp_ipa_setup_tx_params_bank_id(soc, tx);
  801. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  802. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  803. }
  804. static void
  805. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  806. struct dp_ipa_resources *ipa_res,
  807. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  808. {
  809. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  810. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  811. &ipa_res->tx_alt_comp_ring.sgtable,
  812. sizeof(sgtable_t));
  813. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  814. qdf_mem_get_dma_size(soc->osdev,
  815. &ipa_res->tx_alt_comp_ring.mem_info);
  816. /* WBM Tail Pointer Address */
  817. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  818. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  819. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  820. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  821. &ipa_res->tx_alt_ring.sgtable,
  822. sizeof(sgtable_t));
  823. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  824. qdf_mem_get_dma_size(soc->osdev,
  825. &ipa_res->tx_alt_ring.mem_info);
  826. /* TCL Head Pointer Address */
  827. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  828. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  829. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  830. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  831. ipa_res->tx_alt_ring_num_alloc_buffer;
  832. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  833. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  834. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  835. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  836. }
  837. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  838. struct dp_ipa_resources *res,
  839. qdf_ipa_wdi_conn_in_params_t *in)
  840. {
  841. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  842. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  843. qdf_ipa_ep_cfg_t *tx_cfg;
  844. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  845. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  846. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  847. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  848. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  849. } else {
  850. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  851. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  852. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  853. }
  854. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  855. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  856. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  857. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  858. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  859. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  860. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  861. }
  862. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  863. qdf_ipa_wdi_conn_out_params_t *out)
  864. {
  865. res->tx_comp_doorbell_paddr =
  866. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  867. res->rx_ready_doorbell_paddr =
  868. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  869. res->tx_alt_comp_doorbell_paddr =
  870. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  871. }
  872. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  873. uint8_t session_id)
  874. {
  875. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  876. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  877. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  878. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  879. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  880. }
  881. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  882. struct dp_ipa_resources *res)
  883. {
  884. struct hal_srng *wbm_srng;
  885. /* Init first TX comp ring */
  886. wbm_srng = (struct hal_srng *)
  887. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  888. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  889. res->tx_comp_doorbell_vaddr);
  890. /* Init the alternate TX comp ring */
  891. if (!res->tx_alt_comp_doorbell_paddr)
  892. return;
  893. wbm_srng = (struct hal_srng *)
  894. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  895. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  896. res->tx_alt_comp_doorbell_vaddr);
  897. }
  898. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  899. struct dp_ipa_resources *ipa_res)
  900. {
  901. struct hal_srng *wbm_srng;
  902. wbm_srng = (struct hal_srng *)
  903. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  904. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  905. ipa_res->tx_comp_doorbell_paddr);
  906. dp_info("paddr %pK vaddr %pK",
  907. (void *)ipa_res->tx_comp_doorbell_paddr,
  908. (void *)ipa_res->tx_comp_doorbell_vaddr);
  909. /* Setup for alternative TX comp ring */
  910. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  911. return;
  912. wbm_srng = (struct hal_srng *)
  913. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  914. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  915. ipa_res->tx_alt_comp_doorbell_paddr);
  916. dp_info("paddr %pK vaddr %pK",
  917. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  918. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  919. }
  920. #ifdef IPA_SET_RESET_TX_DB_PA
  921. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  922. struct dp_ipa_resources *ipa_res)
  923. {
  924. hal_ring_handle_t wbm_srng;
  925. qdf_dma_addr_t hp_addr;
  926. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  927. if (!wbm_srng)
  928. return QDF_STATUS_E_FAILURE;
  929. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  930. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  931. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  932. /* Reset alternative TX comp ring */
  933. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  934. if (!wbm_srng)
  935. return QDF_STATUS_E_FAILURE;
  936. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  937. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  938. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  939. return QDF_STATUS_SUCCESS;
  940. }
  941. #endif /* IPA_SET_RESET_TX_DB_PA */
  942. #else /* !IPA_WDI3_TX_TWO_PIPES */
  943. static inline
  944. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  945. {
  946. }
  947. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  948. {
  949. }
  950. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  951. {
  952. return 0;
  953. }
  954. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  955. {
  956. return QDF_STATUS_SUCCESS;
  957. }
  958. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  959. {
  960. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  961. uint32_t rx_ready_doorbell_dmaaddr;
  962. uint32_t tx_comp_doorbell_dmaaddr;
  963. struct dp_soc *soc = pdev->soc;
  964. int ret = 0;
  965. if (ipa_res->is_db_ddr_mapped)
  966. ipa_res->tx_comp_doorbell_vaddr =
  967. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  968. else
  969. ipa_res->tx_comp_doorbell_vaddr =
  970. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  971. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  972. ret = pld_smmu_map(soc->osdev->dev,
  973. ipa_res->tx_comp_doorbell_paddr,
  974. &tx_comp_doorbell_dmaaddr,
  975. sizeof(uint32_t));
  976. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  977. qdf_assert_always(!ret);
  978. ret = pld_smmu_map(soc->osdev->dev,
  979. ipa_res->rx_ready_doorbell_paddr,
  980. &rx_ready_doorbell_dmaaddr,
  981. sizeof(uint32_t));
  982. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  983. qdf_assert_always(!ret);
  984. }
  985. }
  986. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  987. {
  988. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  989. struct dp_soc *soc = pdev->soc;
  990. int ret = 0;
  991. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  992. return;
  993. ret = pld_smmu_unmap(soc->osdev->dev,
  994. ipa_res->rx_ready_doorbell_paddr,
  995. sizeof(uint32_t));
  996. qdf_assert_always(!ret);
  997. ret = pld_smmu_unmap(soc->osdev->dev,
  998. ipa_res->tx_comp_doorbell_paddr,
  999. sizeof(uint32_t));
  1000. qdf_assert_always(!ret);
  1001. }
  1002. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  1003. struct dp_pdev *pdev,
  1004. bool create,
  1005. const char *func,
  1006. uint32_t line)
  1007. {
  1008. return QDF_STATUS_SUCCESS;
  1009. }
  1010. static inline
  1011. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  1012. qdf_ipa_wdi_conn_in_params_t *in)
  1013. {
  1014. }
  1015. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1016. qdf_ipa_wdi_conn_out_params_t *out)
  1017. {
  1018. res->tx_comp_doorbell_paddr =
  1019. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1020. res->rx_ready_doorbell_paddr =
  1021. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1022. }
  1023. #ifdef IPA_WDS_EASYMESH_FEATURE
  1024. /**
  1025. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1026. * @in: ipa in params
  1027. * @session_id: vdev id
  1028. *
  1029. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1030. * is stored at higher nibble so, no shift is required.
  1031. *
  1032. * Return: none
  1033. */
  1034. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1035. uint8_t session_id)
  1036. {
  1037. if (ucfg_ipa_is_wds_enabled())
  1038. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1039. else
  1040. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1041. }
  1042. #else
  1043. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1044. uint8_t session_id)
  1045. {
  1046. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1047. }
  1048. #endif
  1049. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1050. struct dp_ipa_resources *res)
  1051. {
  1052. struct hal_srng *wbm_srng = (struct hal_srng *)
  1053. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1054. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1055. res->tx_comp_doorbell_vaddr);
  1056. }
  1057. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1058. struct dp_ipa_resources *ipa_res)
  1059. {
  1060. struct hal_srng *wbm_srng = (struct hal_srng *)
  1061. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1062. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1063. ipa_res->tx_comp_doorbell_paddr);
  1064. dp_info("paddr %pK vaddr %pK",
  1065. (void *)ipa_res->tx_comp_doorbell_paddr,
  1066. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1067. }
  1068. #ifdef IPA_SET_RESET_TX_DB_PA
  1069. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1070. struct dp_ipa_resources *ipa_res)
  1071. {
  1072. hal_ring_handle_t wbm_srng =
  1073. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1074. qdf_dma_addr_t hp_addr;
  1075. if (!wbm_srng)
  1076. return QDF_STATUS_E_FAILURE;
  1077. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1078. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1079. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1080. return QDF_STATUS_SUCCESS;
  1081. }
  1082. #endif /* IPA_SET_RESET_TX_DB_PA */
  1083. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1084. /**
  1085. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1086. * @soc: data path instance
  1087. * @pdev: core txrx pdev context
  1088. *
  1089. * Free allocated TX buffers with WBM SRNG
  1090. *
  1091. * Return: none
  1092. */
  1093. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1094. {
  1095. int idx;
  1096. qdf_nbuf_t nbuf;
  1097. struct dp_ipa_resources *ipa_res;
  1098. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1099. nbuf = (qdf_nbuf_t)
  1100. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1101. if (!nbuf)
  1102. continue;
  1103. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1104. qdf_mem_dp_tx_skb_cnt_dec();
  1105. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1106. qdf_nbuf_free(nbuf);
  1107. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1108. (void *)NULL;
  1109. }
  1110. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1111. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1112. ipa_res = &pdev->ipa_resource;
  1113. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1114. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1115. }
  1116. /**
  1117. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1118. * @soc: data path instance
  1119. * @pdev: core txrx pdev context
  1120. *
  1121. * This function will detach DP RX into main device context
  1122. * will free DP Rx resources.
  1123. *
  1124. * Return: none
  1125. */
  1126. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1127. {
  1128. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1129. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1130. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1131. }
  1132. /**
  1133. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1134. * @soc: data path instance
  1135. * @pdev: core txrx pdev context
  1136. *
  1137. * This function will detach DP RX into main device context
  1138. * will free DP Rx resources.
  1139. *
  1140. * Return: none
  1141. */
  1142. #ifdef IPA_WDI3_VLAN_SUPPORT
  1143. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1144. {
  1145. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1146. if (!wlan_ipa_is_vlan_enabled())
  1147. return;
  1148. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1149. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1150. }
  1151. #else
  1152. static inline
  1153. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1154. { }
  1155. #endif
  1156. /**
  1157. * dp_ipa_opt_wifi_dp_cleanup() - Cleanup ipa opt wifi dp filter setup
  1158. * @soc: data path instance
  1159. * @pdev: core txrx pdev context
  1160. *
  1161. * This function will cleanup filter setup for optional wifi dp.
  1162. *
  1163. * Return: none
  1164. */
  1165. #ifdef IPA_OPT_WIFI_DP
  1166. static void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1167. {
  1168. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1169. struct hif_softc *hif = (struct hif_softc *)(hal_soc->hif_handle);
  1170. int count = qdf_atomic_read(&hif->opt_wifi_dp_rtpm_cnt);
  1171. int i;
  1172. for (i = count; i > 0; i--) {
  1173. dp_info("opt_dp: cleanup call pcie link down");
  1174. dp_ipa_pcie_link_down((struct cdp_soc_t *)soc);
  1175. }
  1176. }
  1177. #else
  1178. static inline
  1179. void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1180. {
  1181. }
  1182. #endif
  1183. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1184. {
  1185. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1186. return QDF_STATUS_SUCCESS;
  1187. /* TX resource detach */
  1188. dp_tx_ipa_uc_detach(soc, pdev);
  1189. /* Cleanup 2nd TX pipe resources */
  1190. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1191. /* RX resource detach */
  1192. dp_rx_ipa_uc_detach(soc, pdev);
  1193. /* Cleanup 2nd RX pipe resources */
  1194. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1195. dp_ipa_opt_wifi_dp_cleanup(soc, pdev);
  1196. return QDF_STATUS_SUCCESS; /* success */
  1197. }
  1198. /**
  1199. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1200. * @soc: data path instance
  1201. * @pdev: Physical device handle
  1202. *
  1203. * Allocate TX buffer from non-cacheable memory
  1204. * Attach allocated TX buffers with WBM SRNG
  1205. *
  1206. * Return: int
  1207. */
  1208. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1209. {
  1210. uint32_t tx_buffer_count;
  1211. uint32_t ring_base_align = 8;
  1212. qdf_dma_addr_t buffer_paddr;
  1213. struct hal_srng *wbm_srng = (struct hal_srng *)
  1214. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1215. struct hal_srng_params srng_params;
  1216. void *ring_entry;
  1217. int num_entries;
  1218. qdf_nbuf_t nbuf;
  1219. int retval = QDF_STATUS_SUCCESS;
  1220. int max_alloc_count = 0;
  1221. uint32_t wbm_bm_id;
  1222. /*
  1223. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1224. * unsigned int uc_tx_buf_sz =
  1225. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1226. */
  1227. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1228. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1229. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1230. IPA_TCL_DATA_RING_IDX);
  1231. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1232. &srng_params);
  1233. num_entries = srng_params.num_entries;
  1234. max_alloc_count =
  1235. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1236. if (max_alloc_count <= 0) {
  1237. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1238. return -EINVAL;
  1239. }
  1240. dp_info("requested %d buffers to be posted to wbm ring",
  1241. max_alloc_count);
  1242. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1243. qdf_mem_malloc(num_entries *
  1244. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1245. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1246. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1247. return -ENOMEM;
  1248. }
  1249. hal_srng_access_start_unlocked(soc->hal_soc,
  1250. hal_srng_to_hal_ring_handle(wbm_srng));
  1251. /*
  1252. * Allocate Tx buffers as many as possible.
  1253. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1254. * Populate Tx buffers into WBM2IPA ring
  1255. * This initial buffer population will simulate H/W as source ring,
  1256. * and update HP
  1257. */
  1258. for (tx_buffer_count = 0;
  1259. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1260. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  1261. 256, FALSE);
  1262. if (!nbuf)
  1263. break;
  1264. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1265. hal_srng_to_hal_ring_handle(wbm_srng));
  1266. if (!ring_entry) {
  1267. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1268. "%s: Failed to get WBM ring entry",
  1269. __func__);
  1270. qdf_nbuf_free(nbuf);
  1271. break;
  1272. }
  1273. retval = qdf_nbuf_map_single(soc->osdev, nbuf,
  1274. QDF_DMA_BIDIRECTIONAL);
  1275. if (qdf_unlikely(retval != QDF_STATUS_SUCCESS)) {
  1276. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1277. "%s: nbuf map failed", __func__);
  1278. qdf_nbuf_free(nbuf);
  1279. retval = -EFAULT;
  1280. break;
  1281. }
  1282. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1283. qdf_mem_dp_tx_skb_cnt_inc();
  1284. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1285. /*
  1286. * TODO - KIWI code can directly call the be handler
  1287. * instead of hal soc ops.
  1288. */
  1289. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1290. buffer_paddr, 0, wbm_bm_id);
  1291. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1292. = (void *)nbuf;
  1293. }
  1294. hal_srng_access_end_unlocked(soc->hal_soc,
  1295. hal_srng_to_hal_ring_handle(wbm_srng));
  1296. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1297. if (tx_buffer_count) {
  1298. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1299. } else {
  1300. dp_err("No IPA WDI TX buffer allocated!");
  1301. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1302. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1303. retval = -ENOMEM;
  1304. }
  1305. return retval;
  1306. }
  1307. /**
  1308. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1309. * @soc: data path instance
  1310. * @pdev: core txrx pdev context
  1311. *
  1312. * This function will attach a DP RX instance into the main
  1313. * device (SOC) context.
  1314. *
  1315. * Return: QDF_STATUS_SUCCESS: success
  1316. * QDF_STATUS_E_RESOURCES: Error return
  1317. */
  1318. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1319. {
  1320. return QDF_STATUS_SUCCESS;
  1321. }
  1322. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1323. {
  1324. int error;
  1325. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1326. return QDF_STATUS_SUCCESS;
  1327. /* TX resource attach */
  1328. error = dp_tx_ipa_uc_attach(soc, pdev);
  1329. if (error) {
  1330. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1331. "%s: DP IPA UC TX attach fail code %d",
  1332. __func__, error);
  1333. if (error == -EFAULT)
  1334. dp_tx_ipa_uc_detach(soc, pdev);
  1335. return error;
  1336. }
  1337. /* Setup 2nd TX pipe */
  1338. error = dp_ipa_tx_alt_pool_attach(soc);
  1339. if (error) {
  1340. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1341. "%s: DP IPA TX pool2 attach fail code %d",
  1342. __func__, error);
  1343. dp_tx_ipa_uc_detach(soc, pdev);
  1344. return error;
  1345. }
  1346. /* RX resource attach */
  1347. error = dp_rx_ipa_uc_attach(soc, pdev);
  1348. if (error) {
  1349. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1350. "%s: DP IPA UC RX attach fail code %d",
  1351. __func__, error);
  1352. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1353. dp_tx_ipa_uc_detach(soc, pdev);
  1354. return error;
  1355. }
  1356. return QDF_STATUS_SUCCESS; /* success */
  1357. }
  1358. #ifdef IPA_WDI3_VLAN_SUPPORT
  1359. /**
  1360. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1361. * @soc: data path SoC handle
  1362. * @pdev: data path pdev handle
  1363. *
  1364. * Return: none
  1365. */
  1366. static
  1367. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1368. {
  1369. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1370. struct hal_srng *hal_srng;
  1371. struct hal_srng_params srng_params;
  1372. unsigned long addr_offset, dev_base_paddr;
  1373. qdf_dma_addr_t hp_addr;
  1374. if (!wlan_ipa_is_vlan_enabled())
  1375. return;
  1376. dev_base_paddr =
  1377. (unsigned long)
  1378. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1379. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1380. hal_srng = (struct hal_srng *)
  1381. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1382. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1383. hal_srng_to_hal_ring_handle(hal_srng),
  1384. &srng_params);
  1385. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1386. srng_params.ring_base_paddr;
  1387. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1388. srng_params.ring_base_vaddr;
  1389. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1390. (srng_params.num_entries * srng_params.entry_size) << 2;
  1391. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1392. (unsigned long)(hal_soc->dev_base_addr);
  1393. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1394. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1395. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1396. (unsigned int)addr_offset,
  1397. (unsigned int)dev_base_paddr,
  1398. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1399. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1400. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1401. srng_params.num_entries,
  1402. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1403. hal_srng = (struct hal_srng *)
  1404. pdev->rx_refill_buf_ring3.hal_srng;
  1405. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1406. hal_srng_to_hal_ring_handle(hal_srng),
  1407. &srng_params);
  1408. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1409. srng_params.ring_base_paddr;
  1410. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1411. srng_params.ring_base_vaddr;
  1412. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1413. (srng_params.num_entries * srng_params.entry_size) << 2;
  1414. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1415. hal_srng_to_hal_ring_handle(hal_srng));
  1416. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1417. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1418. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1419. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1420. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1421. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1422. srng_params.num_entries,
  1423. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1424. }
  1425. #else
  1426. static inline
  1427. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1428. { }
  1429. #endif
  1430. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1431. struct dp_pdev *pdev)
  1432. {
  1433. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1434. struct hal_srng *hal_srng;
  1435. struct hal_srng_params srng_params;
  1436. qdf_dma_addr_t hp_addr;
  1437. unsigned long addr_offset, dev_base_paddr;
  1438. uint32_t ix0;
  1439. uint8_t ix0_map[8];
  1440. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1441. return QDF_STATUS_SUCCESS;
  1442. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1443. hal_srng = (struct hal_srng *)
  1444. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1445. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1446. hal_srng_to_hal_ring_handle(hal_srng),
  1447. &srng_params);
  1448. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1449. srng_params.ring_base_paddr;
  1450. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1451. srng_params.ring_base_vaddr;
  1452. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1453. (srng_params.num_entries * srng_params.entry_size) << 2;
  1454. /*
  1455. * For the register backed memory addresses, use the scn->mem_pa to
  1456. * calculate the physical address of the shadow registers
  1457. */
  1458. dev_base_paddr =
  1459. (unsigned long)
  1460. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1461. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1462. (unsigned long)(hal_soc->dev_base_addr);
  1463. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1464. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1465. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1466. (unsigned int)addr_offset,
  1467. (unsigned int)dev_base_paddr,
  1468. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1469. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1470. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1471. srng_params.num_entries,
  1472. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1473. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1474. hal_srng = (struct hal_srng *)
  1475. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1476. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1477. hal_srng_to_hal_ring_handle(hal_srng),
  1478. &srng_params);
  1479. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1480. srng_params.ring_base_paddr;
  1481. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1482. srng_params.ring_base_vaddr;
  1483. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1484. (srng_params.num_entries * srng_params.entry_size) << 2;
  1485. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1486. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1487. hal_srng_to_hal_ring_handle(hal_srng));
  1488. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1489. (unsigned long)(hal_soc->dev_base_addr);
  1490. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1491. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1492. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1493. (unsigned int)addr_offset,
  1494. (unsigned int)dev_base_paddr,
  1495. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1496. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1497. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1498. srng_params.num_entries,
  1499. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1500. dp_ipa_tx_alt_ring_resource_setup(soc);
  1501. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1502. hal_srng = (struct hal_srng *)
  1503. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1504. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1505. hal_srng_to_hal_ring_handle(hal_srng),
  1506. &srng_params);
  1507. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1508. srng_params.ring_base_paddr;
  1509. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1510. srng_params.ring_base_vaddr;
  1511. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1512. (srng_params.num_entries * srng_params.entry_size) << 2;
  1513. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1514. (unsigned long)(hal_soc->dev_base_addr);
  1515. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1516. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1517. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1518. (unsigned int)addr_offset,
  1519. (unsigned int)dev_base_paddr,
  1520. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1521. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1522. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1523. srng_params.num_entries,
  1524. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1525. hal_srng = (struct hal_srng *)
  1526. pdev->rx_refill_buf_ring2.hal_srng;
  1527. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1528. hal_srng_to_hal_ring_handle(hal_srng),
  1529. &srng_params);
  1530. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1531. srng_params.ring_base_paddr;
  1532. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1533. srng_params.ring_base_vaddr;
  1534. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1535. (srng_params.num_entries * srng_params.entry_size) << 2;
  1536. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1537. hal_srng_to_hal_ring_handle(hal_srng));
  1538. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1539. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1540. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1541. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1542. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1543. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1544. srng_params.num_entries,
  1545. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1546. /*
  1547. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1548. * DESTINATION_RING_CTRL_IX_0.
  1549. */
  1550. ix0_map[0] = REO_REMAP_SW1;
  1551. ix0_map[1] = REO_REMAP_SW1;
  1552. ix0_map[2] = REO_REMAP_SW2;
  1553. ix0_map[3] = REO_REMAP_SW3;
  1554. ix0_map[4] = REO_REMAP_SW2;
  1555. ix0_map[5] = REO_REMAP_RELEASE;
  1556. ix0_map[6] = REO_REMAP_FW;
  1557. ix0_map[7] = REO_REMAP_FW;
  1558. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1559. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1560. ix0_map);
  1561. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1562. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1563. return 0;
  1564. }
  1565. #ifdef IPA_WDI3_VLAN_SUPPORT
  1566. /**
  1567. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1568. * @pdev: data path pdev handle
  1569. *
  1570. * Return: Success if resourece is found
  1571. */
  1572. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1573. {
  1574. struct dp_soc *soc = pdev->soc;
  1575. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1576. if (!wlan_ipa_is_vlan_enabled())
  1577. return QDF_STATUS_SUCCESS;
  1578. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1579. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1580. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1581. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1582. dp_ipa_get_shared_mem_info(
  1583. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1584. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1585. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1586. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1587. if (!qdf_mem_get_dma_addr(soc->osdev,
  1588. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1589. !qdf_mem_get_dma_addr(soc->osdev,
  1590. &ipa_res->rx_alt_refill_ring.mem_info))
  1591. return QDF_STATUS_E_FAILURE;
  1592. return QDF_STATUS_SUCCESS;
  1593. }
  1594. #else
  1595. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1596. {
  1597. return QDF_STATUS_SUCCESS;
  1598. }
  1599. #endif
  1600. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1601. {
  1602. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1603. struct dp_pdev *pdev =
  1604. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1605. struct dp_ipa_resources *ipa_res;
  1606. if (!pdev) {
  1607. dp_err("Invalid instance");
  1608. return QDF_STATUS_E_FAILURE;
  1609. }
  1610. ipa_res = &pdev->ipa_resource;
  1611. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1612. return QDF_STATUS_SUCCESS;
  1613. ipa_res->tx_num_alloc_buffer =
  1614. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1615. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1616. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1617. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1618. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1619. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1620. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1621. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1622. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1623. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1624. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1625. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1626. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1627. dp_ipa_get_shared_mem_info(
  1628. soc->osdev, &ipa_res->rx_refill_ring,
  1629. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1630. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1631. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1632. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1633. !qdf_mem_get_dma_addr(soc->osdev,
  1634. &ipa_res->tx_comp_ring.mem_info) ||
  1635. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1636. !qdf_mem_get_dma_addr(soc->osdev,
  1637. &ipa_res->rx_refill_ring.mem_info))
  1638. return QDF_STATUS_E_FAILURE;
  1639. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1640. return QDF_STATUS_E_FAILURE;
  1641. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1642. return QDF_STATUS_E_FAILURE;
  1643. return QDF_STATUS_SUCCESS;
  1644. }
  1645. #ifdef IPA_SET_RESET_TX_DB_PA
  1646. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1647. #else
  1648. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1649. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1650. #endif
  1651. #ifdef IPA_WDI3_VLAN_SUPPORT
  1652. /**
  1653. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1654. * @pdev: data path pdev handle
  1655. *
  1656. * Return: none
  1657. */
  1658. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1659. {
  1660. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1661. uint32_t rx_ready_doorbell_dmaaddr;
  1662. struct dp_soc *soc = pdev->soc;
  1663. struct hal_srng *reo_srng = (struct hal_srng *)
  1664. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1665. int ret = 0;
  1666. if (!wlan_ipa_is_vlan_enabled())
  1667. return;
  1668. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1669. ret = pld_smmu_map(soc->osdev->dev,
  1670. ipa_res->rx_alt_ready_doorbell_paddr,
  1671. &rx_ready_doorbell_dmaaddr,
  1672. sizeof(uint32_t));
  1673. ipa_res->rx_alt_ready_doorbell_paddr =
  1674. rx_ready_doorbell_dmaaddr;
  1675. qdf_assert_always(!ret);
  1676. }
  1677. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1678. ipa_res->rx_alt_ready_doorbell_paddr);
  1679. }
  1680. /**
  1681. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1682. * @pdev: data path pdev handle
  1683. *
  1684. * Return: none
  1685. */
  1686. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1687. {
  1688. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1689. struct dp_soc *soc = pdev->soc;
  1690. int ret = 0;
  1691. if (!wlan_ipa_is_vlan_enabled())
  1692. return;
  1693. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1694. return;
  1695. ret = pld_smmu_unmap(soc->osdev->dev,
  1696. ipa_res->rx_alt_ready_doorbell_paddr,
  1697. sizeof(uint32_t));
  1698. qdf_assert_always(!ret);
  1699. }
  1700. #else
  1701. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1702. { }
  1703. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1704. { }
  1705. #endif
  1706. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1707. {
  1708. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1709. struct dp_pdev *pdev =
  1710. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1711. struct dp_ipa_resources *ipa_res;
  1712. struct hal_srng *reo_srng = (struct hal_srng *)
  1713. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1714. if (!pdev) {
  1715. dp_err("Invalid instance");
  1716. return QDF_STATUS_E_FAILURE;
  1717. }
  1718. ipa_res = &pdev->ipa_resource;
  1719. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1720. return QDF_STATUS_SUCCESS;
  1721. dp_ipa_map_ring_doorbell_paddr(pdev);
  1722. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1723. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1724. /*
  1725. * For RX, REO module on Napier/Hastings does reordering on incoming
  1726. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1727. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1728. * to IPA.
  1729. * Set the doorbell addr for the REO ring.
  1730. */
  1731. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1732. ipa_res->rx_ready_doorbell_paddr);
  1733. return QDF_STATUS_SUCCESS;
  1734. }
  1735. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1736. uint8_t pdev_id)
  1737. {
  1738. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1739. struct dp_pdev *pdev =
  1740. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1741. struct dp_ipa_resources *ipa_res;
  1742. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1743. return QDF_STATUS_SUCCESS;
  1744. if (!pdev) {
  1745. dp_err("Invalid instance");
  1746. return QDF_STATUS_E_FAILURE;
  1747. }
  1748. ipa_res = &pdev->ipa_resource;
  1749. if (!ipa_res->is_db_ddr_mapped)
  1750. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1751. return QDF_STATUS_SUCCESS;
  1752. }
  1753. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1754. uint8_t *op_msg)
  1755. {
  1756. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1757. struct dp_pdev *pdev =
  1758. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1759. if (!pdev) {
  1760. dp_err("Invalid instance");
  1761. return QDF_STATUS_E_FAILURE;
  1762. }
  1763. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1764. return QDF_STATUS_SUCCESS;
  1765. if (pdev->ipa_uc_op_cb) {
  1766. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1767. } else {
  1768. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1769. "%s: IPA callback function is not registered", __func__);
  1770. qdf_mem_free(op_msg);
  1771. return QDF_STATUS_E_FAILURE;
  1772. }
  1773. return QDF_STATUS_SUCCESS;
  1774. }
  1775. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1776. ipa_uc_op_cb_type op_cb,
  1777. void *usr_ctxt)
  1778. {
  1779. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1780. struct dp_pdev *pdev =
  1781. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1782. if (!pdev) {
  1783. dp_err("Invalid instance");
  1784. return QDF_STATUS_E_FAILURE;
  1785. }
  1786. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1787. return QDF_STATUS_SUCCESS;
  1788. pdev->ipa_uc_op_cb = op_cb;
  1789. pdev->usr_ctxt = usr_ctxt;
  1790. return QDF_STATUS_SUCCESS;
  1791. }
  1792. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1793. {
  1794. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1795. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1796. if (!pdev) {
  1797. dp_err("Invalid instance");
  1798. return;
  1799. }
  1800. dp_debug("Deregister OP handler callback");
  1801. pdev->ipa_uc_op_cb = NULL;
  1802. pdev->usr_ctxt = NULL;
  1803. }
  1804. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1805. {
  1806. /* TBD */
  1807. return QDF_STATUS_SUCCESS;
  1808. }
  1809. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1810. qdf_nbuf_t skb)
  1811. {
  1812. qdf_nbuf_t ret;
  1813. /* Terminate the (single-element) list of tx frames */
  1814. qdf_nbuf_set_next(skb, NULL);
  1815. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1816. if (ret) {
  1817. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1818. "%s: Failed to tx", __func__);
  1819. return ret;
  1820. }
  1821. return NULL;
  1822. }
  1823. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1824. /**
  1825. * dp_ipa_is_target_ready() - check if target is ready or not
  1826. * @soc: datapath soc handle
  1827. *
  1828. * Return: true if target is ready
  1829. */
  1830. static inline
  1831. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1832. {
  1833. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1834. return false;
  1835. else
  1836. return true;
  1837. }
  1838. /**
  1839. * dp_ipa_update_txr_db_status() - Indicate transfer ring DB is SMMU mapped or not
  1840. * @dev: Pointer to device
  1841. * @txrx_smmu: WDI TX/RX configuration
  1842. *
  1843. * Return: None
  1844. */
  1845. static inline
  1846. void dp_ipa_update_txr_db_status(struct device *dev,
  1847. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1848. {
  1849. int pcie_slot = pld_get_pci_slot(dev);
  1850. if (pcie_slot)
  1851. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1852. else
  1853. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1854. }
  1855. /**
  1856. * dp_ipa_update_evt_db_status() - Indicate evt ring DB is SMMU mapped or not
  1857. * @dev: Pointer to device
  1858. * @txrx_smmu: WDI TX/RX configuration
  1859. *
  1860. * Return: None
  1861. */
  1862. static inline
  1863. void dp_ipa_update_evt_db_status(struct device *dev,
  1864. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1865. {
  1866. int pcie_slot = pld_get_pci_slot(dev);
  1867. if (pcie_slot)
  1868. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1869. else
  1870. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1871. }
  1872. #else
  1873. static inline
  1874. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1875. {
  1876. return true;
  1877. }
  1878. static inline
  1879. void dp_ipa_update_txr_db_status(struct device *dev,
  1880. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1881. {
  1882. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1883. }
  1884. static inline
  1885. void dp_ipa_update_evt_db_status(struct device *dev,
  1886. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1887. {
  1888. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1889. }
  1890. #endif
  1891. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1892. {
  1893. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1894. struct dp_pdev *pdev =
  1895. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1896. uint32_t ix0;
  1897. uint32_t ix2;
  1898. uint8_t ix_map[8];
  1899. if (!pdev) {
  1900. dp_err("Invalid instance");
  1901. return QDF_STATUS_E_FAILURE;
  1902. }
  1903. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1904. return QDF_STATUS_SUCCESS;
  1905. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1906. return QDF_STATUS_E_AGAIN;
  1907. if (!dp_ipa_is_target_ready(soc))
  1908. return QDF_STATUS_E_AGAIN;
  1909. /* Call HAL API to remap REO rings to REO2IPA ring */
  1910. ix_map[0] = REO_REMAP_SW1;
  1911. ix_map[1] = REO_REMAP_SW4;
  1912. ix_map[2] = REO_REMAP_SW1;
  1913. if (wlan_ipa_is_vlan_enabled())
  1914. ix_map[3] = REO_REMAP_SW3;
  1915. else
  1916. ix_map[3] = REO_REMAP_SW4;
  1917. ix_map[4] = REO_REMAP_SW4;
  1918. ix_map[5] = REO_REMAP_RELEASE;
  1919. ix_map[6] = REO_REMAP_FW;
  1920. ix_map[7] = REO_REMAP_FW;
  1921. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1922. ix_map);
  1923. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1924. ix_map[0] = REO_REMAP_SW4;
  1925. ix_map[1] = REO_REMAP_SW4;
  1926. ix_map[2] = REO_REMAP_SW4;
  1927. ix_map[3] = REO_REMAP_SW4;
  1928. ix_map[4] = REO_REMAP_SW4;
  1929. ix_map[5] = REO_REMAP_SW4;
  1930. ix_map[6] = REO_REMAP_SW4;
  1931. ix_map[7] = REO_REMAP_SW4;
  1932. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1933. ix_map);
  1934. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1935. &ix2, &ix2);
  1936. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1937. } else {
  1938. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1939. NULL, NULL);
  1940. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1941. }
  1942. return QDF_STATUS_SUCCESS;
  1943. }
  1944. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1945. {
  1946. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1947. struct dp_pdev *pdev =
  1948. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1949. uint8_t ix0_map[8];
  1950. uint32_t ix0;
  1951. uint32_t ix1;
  1952. uint32_t ix2;
  1953. uint32_t ix3;
  1954. if (!pdev) {
  1955. dp_err("Invalid instance");
  1956. return QDF_STATUS_E_FAILURE;
  1957. }
  1958. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1959. return QDF_STATUS_SUCCESS;
  1960. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1961. return QDF_STATUS_E_AGAIN;
  1962. if (!dp_ipa_is_target_ready(soc))
  1963. return QDF_STATUS_E_AGAIN;
  1964. ix0_map[0] = REO_REMAP_SW1;
  1965. ix0_map[1] = REO_REMAP_SW1;
  1966. ix0_map[2] = REO_REMAP_SW2;
  1967. ix0_map[3] = REO_REMAP_SW3;
  1968. ix0_map[4] = REO_REMAP_SW2;
  1969. ix0_map[5] = REO_REMAP_RELEASE;
  1970. ix0_map[6] = REO_REMAP_FW;
  1971. ix0_map[7] = REO_REMAP_FW;
  1972. /* Call HAL API to remap REO rings to REO2IPA ring */
  1973. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1974. ix0_map);
  1975. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1976. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1977. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1978. &ix2, &ix3);
  1979. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1980. } else {
  1981. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1982. NULL, NULL);
  1983. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1984. }
  1985. return QDF_STATUS_SUCCESS;
  1986. }
  1987. /* This should be configurable per H/W configuration enable status */
  1988. #define L3_HEADER_PADDING 2
  1989. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  1990. defined(CONFIG_IPA_WDI_UNIFIED_API)
  1991. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  1992. static inline void dp_setup_mcc_sys_pipes(
  1993. qdf_ipa_sys_connect_params_t *sys_in,
  1994. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1995. {
  1996. int i = 0;
  1997. /* Setup MCC sys pipe */
  1998. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  1999. DP_IPA_MAX_IFACE;
  2000. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  2001. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  2002. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  2003. }
  2004. #else
  2005. static inline void dp_setup_mcc_sys_pipes(
  2006. qdf_ipa_sys_connect_params_t *sys_in,
  2007. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  2008. {
  2009. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  2010. }
  2011. #endif
  2012. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  2013. struct dp_ipa_resources *ipa_res,
  2014. qdf_ipa_wdi_pipe_setup_info_t *tx,
  2015. bool over_gsi)
  2016. {
  2017. if (over_gsi)
  2018. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  2019. else
  2020. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2021. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2022. qdf_mem_get_dma_addr(soc->osdev,
  2023. &ipa_res->tx_comp_ring.mem_info);
  2024. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2025. qdf_mem_get_dma_size(soc->osdev,
  2026. &ipa_res->tx_comp_ring.mem_info);
  2027. /* WBM Tail Pointer Address */
  2028. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2029. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2030. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  2031. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2032. qdf_mem_get_dma_addr(soc->osdev,
  2033. &ipa_res->tx_ring.mem_info);
  2034. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  2035. qdf_mem_get_dma_size(soc->osdev,
  2036. &ipa_res->tx_ring.mem_info);
  2037. /* TCL Head Pointer Address */
  2038. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2039. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2040. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  2041. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2042. ipa_res->tx_num_alloc_buffer;
  2043. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2044. dp_ipa_setup_tx_params_bank_id(soc, tx);
  2045. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  2046. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  2047. }
  2048. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  2049. struct dp_ipa_resources *ipa_res,
  2050. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2051. bool over_gsi)
  2052. {
  2053. if (over_gsi)
  2054. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2055. IPA_CLIENT_WLAN2_PROD;
  2056. else
  2057. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2058. IPA_CLIENT_WLAN1_PROD;
  2059. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2060. qdf_mem_get_dma_addr(soc->osdev,
  2061. &ipa_res->rx_rdy_ring.mem_info);
  2062. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2063. qdf_mem_get_dma_size(soc->osdev,
  2064. &ipa_res->rx_rdy_ring.mem_info);
  2065. /* REO Tail Pointer Address */
  2066. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2067. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2068. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2069. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2070. qdf_mem_get_dma_addr(soc->osdev,
  2071. &ipa_res->rx_refill_ring.mem_info);
  2072. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2073. qdf_mem_get_dma_size(soc->osdev,
  2074. &ipa_res->rx_refill_ring.mem_info);
  2075. /* FW Head Pointer Address */
  2076. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2077. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2078. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2079. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2080. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2081. }
  2082. static void
  2083. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  2084. struct dp_ipa_resources *ipa_res,
  2085. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  2086. bool over_gsi,
  2087. qdf_ipa_wdi_hdl_t hdl)
  2088. {
  2089. if (over_gsi) {
  2090. if (hdl == DP_IPA_HDL_FIRST)
  2091. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2092. IPA_CLIENT_WLAN2_CONS;
  2093. else if (hdl == DP_IPA_HDL_SECOND)
  2094. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2095. IPA_CLIENT_WLAN4_CONS;
  2096. else if (hdl == DP_IPA_HDL_THIRD)
  2097. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2098. IPA_CLIENT_WLAN1_CONS;
  2099. } else {
  2100. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2101. IPA_CLIENT_WLAN1_CONS;
  2102. }
  2103. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2104. &ipa_res->tx_comp_ring.sgtable,
  2105. sizeof(sgtable_t));
  2106. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2107. qdf_mem_get_dma_size(soc->osdev,
  2108. &ipa_res->tx_comp_ring.mem_info);
  2109. /* WBM Tail Pointer Address */
  2110. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2111. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2112. dp_ipa_update_txr_db_status(soc->osdev->dev, tx_smmu);
  2113. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2114. &ipa_res->tx_ring.sgtable,
  2115. sizeof(sgtable_t));
  2116. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2117. qdf_mem_get_dma_size(soc->osdev,
  2118. &ipa_res->tx_ring.mem_info);
  2119. /* TCL Head Pointer Address */
  2120. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2121. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2122. dp_ipa_update_evt_db_status(soc->osdev->dev, tx_smmu);
  2123. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2124. ipa_res->tx_num_alloc_buffer;
  2125. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2126. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2127. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2128. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2129. }
  2130. static void
  2131. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2132. struct dp_ipa_resources *ipa_res,
  2133. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2134. bool over_gsi,
  2135. qdf_ipa_wdi_hdl_t hdl)
  2136. {
  2137. if (over_gsi) {
  2138. if (hdl == DP_IPA_HDL_FIRST)
  2139. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2140. IPA_CLIENT_WLAN2_PROD;
  2141. else if (hdl == DP_IPA_HDL_SECOND)
  2142. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2143. IPA_CLIENT_WLAN3_PROD;
  2144. else if (hdl == DP_IPA_HDL_THIRD)
  2145. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2146. IPA_CLIENT_WLAN1_PROD;
  2147. } else {
  2148. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2149. IPA_CLIENT_WLAN1_PROD;
  2150. }
  2151. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2152. &ipa_res->rx_rdy_ring.sgtable,
  2153. sizeof(sgtable_t));
  2154. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2155. qdf_mem_get_dma_size(soc->osdev,
  2156. &ipa_res->rx_rdy_ring.mem_info);
  2157. /* REO Tail Pointer Address */
  2158. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2159. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2160. dp_ipa_update_txr_db_status(soc->osdev->dev, rx_smmu);
  2161. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2162. &ipa_res->rx_refill_ring.sgtable,
  2163. sizeof(sgtable_t));
  2164. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2165. qdf_mem_get_dma_size(soc->osdev,
  2166. &ipa_res->rx_refill_ring.mem_info);
  2167. /* FW Head Pointer Address */
  2168. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2169. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2170. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2171. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2172. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2173. }
  2174. #ifdef IPA_WDI3_VLAN_SUPPORT
  2175. /**
  2176. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2177. * @soc: data path soc handle
  2178. * @ipa_res: ipa resource pointer
  2179. * @rx_smmu: smmu pipe info handle
  2180. * @over_gsi: flag for IPA offload over gsi
  2181. * @hdl: ipa registered handle
  2182. *
  2183. * Return: none
  2184. */
  2185. static void
  2186. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2187. struct dp_ipa_resources *ipa_res,
  2188. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2189. bool over_gsi,
  2190. qdf_ipa_wdi_hdl_t hdl)
  2191. {
  2192. if (!wlan_ipa_is_vlan_enabled())
  2193. return;
  2194. if (over_gsi) {
  2195. if (hdl == DP_IPA_HDL_FIRST)
  2196. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2197. IPA_CLIENT_WLAN2_PROD1;
  2198. else if (hdl == DP_IPA_HDL_SECOND)
  2199. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2200. IPA_CLIENT_WLAN3_PROD1;
  2201. else if (hdl == DP_IPA_HDL_THIRD)
  2202. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx_smmu) =
  2203. IPA_CLIENT_WLAN1_PROD1;
  2204. } else {
  2205. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2206. IPA_CLIENT_WLAN1_PROD;
  2207. }
  2208. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2209. &ipa_res->rx_alt_rdy_ring.sgtable,
  2210. sizeof(sgtable_t));
  2211. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2212. qdf_mem_get_dma_size(soc->osdev,
  2213. &ipa_res->rx_alt_rdy_ring.mem_info);
  2214. /* REO Tail Pointer Address */
  2215. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2216. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2217. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2218. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2219. &ipa_res->rx_alt_refill_ring.sgtable,
  2220. sizeof(sgtable_t));
  2221. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2222. qdf_mem_get_dma_size(soc->osdev,
  2223. &ipa_res->rx_alt_refill_ring.mem_info);
  2224. /* FW Head Pointer Address */
  2225. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2226. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2227. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2228. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2229. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2230. }
  2231. /**
  2232. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2233. * @soc: data path soc handle
  2234. * @ipa_res: ipa resource pointer
  2235. * @rx: pipe info handle
  2236. * @over_gsi: flag for IPA offload over gsi
  2237. * @hdl: ipa registered handle
  2238. *
  2239. * Return: none
  2240. */
  2241. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2242. struct dp_ipa_resources *ipa_res,
  2243. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2244. bool over_gsi,
  2245. qdf_ipa_wdi_hdl_t hdl)
  2246. {
  2247. if (!wlan_ipa_is_vlan_enabled())
  2248. return;
  2249. if (over_gsi) {
  2250. if (hdl == DP_IPA_HDL_FIRST)
  2251. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2252. IPA_CLIENT_WLAN2_PROD1;
  2253. else if (hdl == DP_IPA_HDL_SECOND)
  2254. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2255. IPA_CLIENT_WLAN3_PROD1;
  2256. else if (hdl == DP_IPA_HDL_THIRD)
  2257. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2258. IPA_CLIENT_WLAN1_PROD1;
  2259. } else {
  2260. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2261. IPA_CLIENT_WLAN1_PROD;
  2262. }
  2263. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2264. qdf_mem_get_dma_addr(soc->osdev,
  2265. &ipa_res->rx_alt_rdy_ring.mem_info);
  2266. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2267. qdf_mem_get_dma_size(soc->osdev,
  2268. &ipa_res->rx_alt_rdy_ring.mem_info);
  2269. /* REO Tail Pointer Address */
  2270. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2271. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2272. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2273. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2274. qdf_mem_get_dma_addr(soc->osdev,
  2275. &ipa_res->rx_alt_refill_ring.mem_info);
  2276. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2277. qdf_mem_get_dma_size(soc->osdev,
  2278. &ipa_res->rx_alt_refill_ring.mem_info);
  2279. /* FW Head Pointer Address */
  2280. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2281. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2282. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2283. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2284. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2285. }
  2286. /**
  2287. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2288. * @soc: data path soc handle
  2289. * @res: ipa resource pointer
  2290. * @in: pipe in handle
  2291. * @over_gsi: flag for IPA offload over gsi
  2292. * @hdl: ipa registered handle
  2293. *
  2294. * Return: none
  2295. */
  2296. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2297. struct dp_ipa_resources *res,
  2298. qdf_ipa_wdi_conn_in_params_t *in,
  2299. bool over_gsi,
  2300. qdf_ipa_wdi_hdl_t hdl)
  2301. {
  2302. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2303. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2304. qdf_ipa_ep_cfg_t *rx_cfg;
  2305. if (!wlan_ipa_is_vlan_enabled())
  2306. return;
  2307. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2308. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2309. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2310. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2311. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2312. over_gsi, hdl);
  2313. } else {
  2314. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2315. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2316. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2317. }
  2318. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2319. /* Update with wds len(96) + 4 if wds support is enabled */
  2320. if (ucfg_ipa_is_wds_enabled())
  2321. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2322. else
  2323. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2324. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2325. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2326. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2327. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2328. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2329. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2330. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2331. }
  2332. /**
  2333. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2334. * @res: ipa resource pointer
  2335. * @out: pipe out handle
  2336. *
  2337. * Return: none
  2338. */
  2339. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2340. qdf_ipa_wdi_conn_out_params_t *out)
  2341. {
  2342. if (!wlan_ipa_is_vlan_enabled())
  2343. return;
  2344. res->rx_alt_ready_doorbell_paddr =
  2345. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2346. dp_debug("Setting DB 0x%x for RX alt pipe",
  2347. res->rx_alt_ready_doorbell_paddr);
  2348. }
  2349. #else
  2350. static inline
  2351. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2352. struct dp_ipa_resources *res,
  2353. qdf_ipa_wdi_conn_in_params_t *in,
  2354. bool over_gsi,
  2355. qdf_ipa_wdi_hdl_t hdl)
  2356. { }
  2357. static inline
  2358. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2359. qdf_ipa_wdi_conn_out_params_t *out)
  2360. { }
  2361. #endif
  2362. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2363. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2364. void *ipa_wdi_meter_notifier_cb,
  2365. uint32_t ipa_desc_size, void *ipa_priv,
  2366. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2367. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2368. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2369. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2370. void *ipa_ast_notify_cb)
  2371. {
  2372. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2373. struct dp_pdev *pdev =
  2374. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2375. struct dp_ipa_resources *ipa_res;
  2376. qdf_ipa_ep_cfg_t *tx_cfg;
  2377. qdf_ipa_ep_cfg_t *rx_cfg;
  2378. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2379. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2380. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2381. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2382. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2383. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2384. int ret;
  2385. if (!pdev) {
  2386. dp_err("Invalid instance");
  2387. return QDF_STATUS_E_FAILURE;
  2388. }
  2389. ipa_res = &pdev->ipa_resource;
  2390. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2391. return QDF_STATUS_SUCCESS;
  2392. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2393. if (!pipe_in)
  2394. return QDF_STATUS_E_NOMEM;
  2395. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2396. if (is_smmu_enabled)
  2397. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2398. else
  2399. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2400. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2401. /* TX PIPE */
  2402. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2403. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2404. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2405. } else {
  2406. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2407. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2408. }
  2409. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2410. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2411. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2412. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2413. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2414. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2415. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2416. /*
  2417. * Transfer Ring: WBM Ring
  2418. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2419. * Event Ring: TCL ring
  2420. * Event Ring Doorbell PA: TCL Head Pointer Address
  2421. */
  2422. if (is_smmu_enabled)
  2423. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2424. else
  2425. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2426. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2427. /* RX PIPE */
  2428. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2429. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2430. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2431. } else {
  2432. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2433. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2434. }
  2435. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2436. if (ucfg_ipa_is_wds_enabled())
  2437. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2438. else
  2439. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2440. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2441. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2442. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2443. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2444. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2445. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2446. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2447. /*
  2448. * Transfer Ring: REO Ring
  2449. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2450. * Event Ring: FW ring
  2451. * Event Ring Doorbell PA: FW Head Pointer Address
  2452. */
  2453. if (is_smmu_enabled)
  2454. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2455. else
  2456. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2457. /* setup 2nd rx pipe */
  2458. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2459. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2460. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2461. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2462. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2463. /* Connect WDI IPA PIPEs */
  2464. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2465. if (ret) {
  2466. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2467. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2468. __func__, ret);
  2469. qdf_mem_free(pipe_in);
  2470. return QDF_STATUS_E_FAILURE;
  2471. }
  2472. /* IPA uC Doorbell registers */
  2473. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2474. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2475. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2476. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2477. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2478. ipa_res->is_db_ddr_mapped =
  2479. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2480. soc->ipa_first_tx_db_access = true;
  2481. qdf_mem_free(pipe_in);
  2482. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2483. soc->ipa_rx_buf_map_lock_initialized = true;
  2484. return QDF_STATUS_SUCCESS;
  2485. }
  2486. #ifdef IPA_WDI3_VLAN_SUPPORT
  2487. /**
  2488. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2489. * @in: pipe in handle
  2490. *
  2491. * Return: none
  2492. */
  2493. static inline
  2494. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2495. {
  2496. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2497. }
  2498. /**
  2499. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2500. * @in: pipe in handle
  2501. * @hdr: pointer to hdr
  2502. *
  2503. * Return: none
  2504. */
  2505. static inline
  2506. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2507. qdf_ipa_wdi_hdr_info_t *hdr)
  2508. {
  2509. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2510. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2511. }
  2512. /**
  2513. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2514. * @in: pipe in handle
  2515. * @hdr: pointer to hdr
  2516. *
  2517. * Return: none
  2518. */
  2519. static inline
  2520. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2521. qdf_ipa_wdi_hdr_info_t *hdr)
  2522. {
  2523. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2524. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2525. }
  2526. #else
  2527. static inline
  2528. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2529. { }
  2530. static inline
  2531. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2532. qdf_ipa_wdi_hdr_info_t *hdr)
  2533. { }
  2534. static inline
  2535. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2536. qdf_ipa_wdi_hdr_info_t *hdr)
  2537. { }
  2538. #endif
  2539. #ifdef IPA_WDS_EASYMESH_FEATURE
  2540. /**
  2541. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2542. * @hdr_info: Header info
  2543. *
  2544. * Return: None
  2545. */
  2546. static inline void
  2547. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2548. {
  2549. if (ucfg_ipa_is_wds_enabled())
  2550. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2551. IPA_HDR_L2_ETHERNET_II_AST;
  2552. else
  2553. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2554. IPA_HDR_L2_ETHERNET_II;
  2555. }
  2556. /**
  2557. * dp_ipa_setup_meta_data_mask() - Pass meta data mask to IPA
  2558. * @in: ipa in params
  2559. *
  2560. * Pass meta data mask to IPA.
  2561. *
  2562. * Return: none
  2563. */
  2564. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2565. {
  2566. if (ucfg_ipa_is_wds_enabled())
  2567. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_AST_META_DATA_MASK;
  2568. else
  2569. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2570. }
  2571. #else
  2572. static inline void
  2573. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2574. {
  2575. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2576. }
  2577. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2578. {
  2579. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2580. }
  2581. #endif
  2582. #ifdef IPA_WDI3_VLAN_SUPPORT
  2583. /**
  2584. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2585. * @hdr_info: Header info
  2586. *
  2587. * Return: None
  2588. */
  2589. static inline void
  2590. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2591. {
  2592. if (ucfg_ipa_is_wds_enabled())
  2593. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2594. IPA_HDR_L2_802_1Q_AST;
  2595. else
  2596. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2597. IPA_HDR_L2_802_1Q;
  2598. }
  2599. #else
  2600. static inline void
  2601. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2602. { }
  2603. #endif
  2604. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2605. qdf_ipa_client_type_t prod_client,
  2606. qdf_ipa_client_type_t cons_client,
  2607. uint8_t session_id, bool is_ipv6_enabled,
  2608. qdf_ipa_wdi_hdl_t hdl)
  2609. {
  2610. qdf_ipa_wdi_reg_intf_in_params_t in;
  2611. qdf_ipa_wdi_hdr_info_t hdr_info;
  2612. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2613. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2614. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2615. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2616. int ret = -EINVAL;
  2617. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2618. /* Need to reset the values to 0 as all the fields are not
  2619. * updated in the Header, Unused fields will be set to 0.
  2620. */
  2621. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2622. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2623. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2624. QDF_MAC_ADDR_REF(mac_addr));
  2625. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2626. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2627. /* IPV4 header */
  2628. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2629. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2630. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2631. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2632. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2633. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2634. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2635. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2636. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2637. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2638. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2639. dp_ipa_setup_meta_data_mask(&in);
  2640. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2641. dp_ipa_setup_iface_session_id(&in, session_id);
  2642. dp_debug("registering for session_id: %u", session_id);
  2643. /* IPV6 header */
  2644. if (is_ipv6_enabled) {
  2645. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2646. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2647. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2648. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2649. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2650. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2651. }
  2652. if (wlan_ipa_is_vlan_enabled()) {
  2653. /* Add vlan specific headers if vlan supporti is enabled */
  2654. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2655. dp_ipa_set_rx1_used(&in);
  2656. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2657. /* IPV4 Vlan header */
  2658. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2659. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2660. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2661. (uint8_t *)&uc_tx_vlan_hdr;
  2662. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2663. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2664. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2665. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2666. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2667. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2668. /* IPV6 Vlan header */
  2669. if (is_ipv6_enabled) {
  2670. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2671. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2672. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2673. qdf_htons(ETH_P_8021Q);
  2674. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2675. qdf_htons(ETH_P_IPV6);
  2676. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2677. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2678. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2679. }
  2680. }
  2681. ret = qdf_ipa_wdi_reg_intf(&in);
  2682. if (ret) {
  2683. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2684. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2685. __func__, ret);
  2686. return QDF_STATUS_E_FAILURE;
  2687. }
  2688. return QDF_STATUS_SUCCESS;
  2689. }
  2690. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2691. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2692. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2693. void *ipa_wdi_meter_notifier_cb,
  2694. uint32_t ipa_desc_size, void *ipa_priv,
  2695. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2696. uint32_t *rx_pipe_handle)
  2697. {
  2698. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2699. struct dp_pdev *pdev =
  2700. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2701. struct dp_ipa_resources *ipa_res;
  2702. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2703. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2704. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2705. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2706. struct tcl_data_cmd *tcl_desc_ptr;
  2707. uint8_t *desc_addr;
  2708. uint32_t desc_size;
  2709. int ret;
  2710. if (!pdev) {
  2711. dp_err("Invalid instance");
  2712. return QDF_STATUS_E_FAILURE;
  2713. }
  2714. ipa_res = &pdev->ipa_resource;
  2715. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2716. return QDF_STATUS_SUCCESS;
  2717. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2718. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2719. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2720. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2721. /* TX PIPE */
  2722. /*
  2723. * Transfer Ring: WBM Ring
  2724. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2725. * Event Ring: TCL ring
  2726. * Event Ring Doorbell PA: TCL Head Pointer Address
  2727. */
  2728. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2729. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2730. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2731. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2732. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2733. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2734. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2735. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2736. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2737. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2738. ipa_res->tx_comp_ring_base_paddr;
  2739. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2740. ipa_res->tx_comp_ring_size;
  2741. /* WBM Tail Pointer Address */
  2742. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2743. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2744. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2745. ipa_res->tx_ring_base_paddr;
  2746. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2747. /* TCL Head Pointer Address */
  2748. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2749. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2750. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2751. ipa_res->tx_num_alloc_buffer;
  2752. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2753. /* Preprogram TCL descriptor */
  2754. desc_addr =
  2755. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2756. desc_size = sizeof(struct tcl_data_cmd);
  2757. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2758. tcl_desc_ptr = (struct tcl_data_cmd *)
  2759. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2760. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2761. HAL_RX_BUF_RBM_SW2_BM;
  2762. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2763. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2764. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2765. /* RX PIPE */
  2766. /*
  2767. * Transfer Ring: REO Ring
  2768. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2769. * Event Ring: FW ring
  2770. * Event Ring Doorbell PA: FW Head Pointer Address
  2771. */
  2772. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2773. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2774. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2775. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2776. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2777. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2778. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2779. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2780. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2781. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2782. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2783. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2784. ipa_res->rx_rdy_ring_base_paddr;
  2785. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2786. ipa_res->rx_rdy_ring_size;
  2787. /* REO Tail Pointer Address */
  2788. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2789. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2790. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2791. ipa_res->rx_refill_ring_base_paddr;
  2792. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2793. ipa_res->rx_refill_ring_size;
  2794. /* FW Head Pointer Address */
  2795. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2796. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2797. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2798. L3_HEADER_PADDING;
  2799. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2800. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2801. /* Connect WDI IPA PIPE */
  2802. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2803. if (ret) {
  2804. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2805. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2806. __func__, ret);
  2807. return QDF_STATUS_E_FAILURE;
  2808. }
  2809. /* IPA uC Doorbell registers */
  2810. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2811. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2812. __func__,
  2813. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2814. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2815. ipa_res->tx_comp_doorbell_paddr =
  2816. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2817. ipa_res->tx_comp_doorbell_vaddr =
  2818. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2819. ipa_res->rx_ready_doorbell_paddr =
  2820. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2821. soc->ipa_first_tx_db_access = true;
  2822. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2823. soc->ipa_rx_buf_map_lock_initialized = true;
  2824. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2825. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2826. __func__,
  2827. "transfer_ring_base_pa",
  2828. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2829. "transfer_ring_size",
  2830. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2831. "transfer_ring_doorbell_pa",
  2832. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2833. "event_ring_base_pa",
  2834. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2835. "event_ring_size",
  2836. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2837. "event_ring_doorbell_pa",
  2838. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2839. "num_pkt_buffers",
  2840. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2841. "tx_comp_doorbell_paddr",
  2842. (void *)ipa_res->tx_comp_doorbell_paddr);
  2843. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2844. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2845. __func__,
  2846. "transfer_ring_base_pa",
  2847. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2848. "transfer_ring_size",
  2849. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2850. "transfer_ring_doorbell_pa",
  2851. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2852. "event_ring_base_pa",
  2853. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2854. "event_ring_size",
  2855. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2856. "event_ring_doorbell_pa",
  2857. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2858. "num_pkt_buffers",
  2859. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2860. "tx_comp_doorbell_paddr",
  2861. (void *)ipa_res->rx_ready_doorbell_paddr);
  2862. return QDF_STATUS_SUCCESS;
  2863. }
  2864. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2865. qdf_ipa_client_type_t prod_client,
  2866. qdf_ipa_client_type_t cons_client,
  2867. uint8_t session_id, bool is_ipv6_enabled,
  2868. qdf_ipa_wdi_hdl_t hdl)
  2869. {
  2870. qdf_ipa_wdi_reg_intf_in_params_t in;
  2871. qdf_ipa_wdi_hdr_info_t hdr_info;
  2872. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2873. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2874. int ret = -EINVAL;
  2875. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2876. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2877. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2878. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2879. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2880. /* IPV4 header */
  2881. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2882. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2883. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2884. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2885. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2886. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2887. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2888. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2889. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2890. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2891. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2892. htonl(session_id << 16);
  2893. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2894. /* IPV6 header */
  2895. if (is_ipv6_enabled) {
  2896. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2897. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2898. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2899. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2900. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2901. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2902. }
  2903. ret = qdf_ipa_wdi_reg_intf(&in);
  2904. if (ret) {
  2905. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2906. ret);
  2907. return QDF_STATUS_E_FAILURE;
  2908. }
  2909. return QDF_STATUS_SUCCESS;
  2910. }
  2911. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2912. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2913. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2914. qdf_ipa_wdi_hdl_t hdl)
  2915. {
  2916. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2917. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2918. struct dp_pdev *pdev;
  2919. int ret;
  2920. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2921. if (ret) {
  2922. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2923. ret);
  2924. status = QDF_STATUS_E_FAILURE;
  2925. }
  2926. if (soc->ipa_rx_buf_map_lock_initialized) {
  2927. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2928. soc->ipa_rx_buf_map_lock_initialized = false;
  2929. }
  2930. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2931. if (qdf_unlikely(!pdev)) {
  2932. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2933. status = QDF_STATUS_E_FAILURE;
  2934. goto exit;
  2935. }
  2936. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2937. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2938. exit:
  2939. return status;
  2940. }
  2941. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2942. qdf_ipa_wdi_hdl_t hdl)
  2943. {
  2944. int ret;
  2945. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2946. if (ret) {
  2947. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2948. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2949. __func__, ret);
  2950. return QDF_STATUS_E_FAILURE;
  2951. }
  2952. return QDF_STATUS_SUCCESS;
  2953. }
  2954. #ifdef IPA_SET_RESET_TX_DB_PA
  2955. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2956. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2957. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2958. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2959. #else
  2960. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2961. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2962. #endif
  2963. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2964. qdf_ipa_wdi_hdl_t hdl)
  2965. {
  2966. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2967. struct dp_pdev *pdev =
  2968. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2969. struct dp_ipa_resources *ipa_res;
  2970. QDF_STATUS result;
  2971. if (!pdev) {
  2972. dp_err("Invalid instance");
  2973. return QDF_STATUS_E_FAILURE;
  2974. }
  2975. ipa_res = &pdev->ipa_resource;
  2976. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2977. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2978. if (!ipa_config_is_opt_wifi_dp_enabled()) {
  2979. qdf_atomic_set(&soc->ipa_map_allowed, 1);
  2980. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2981. __func__, __LINE__);
  2982. }
  2983. result = qdf_ipa_wdi_enable_pipes(hdl);
  2984. if (result) {
  2985. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2986. "%s: Enable WDI PIPE fail, code %d",
  2987. __func__, result);
  2988. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2989. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2990. if (qdf_atomic_read(&soc->ipa_map_allowed)) {
  2991. qdf_atomic_set(&soc->ipa_map_allowed, 0);
  2992. dp_ipa_handle_rx_buf_pool_smmu_mapping(
  2993. soc, pdev, false, __func__, __LINE__);
  2994. }
  2995. return QDF_STATUS_E_FAILURE;
  2996. }
  2997. if (soc->ipa_first_tx_db_access) {
  2998. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2999. soc->ipa_first_tx_db_access = false;
  3000. }
  3001. return QDF_STATUS_SUCCESS;
  3002. }
  3003. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3004. qdf_ipa_wdi_hdl_t hdl)
  3005. {
  3006. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3007. struct dp_pdev *pdev =
  3008. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3009. QDF_STATUS result;
  3010. struct dp_ipa_resources *ipa_res;
  3011. if (!pdev) {
  3012. dp_err("Invalid instance");
  3013. return QDF_STATUS_E_FAILURE;
  3014. }
  3015. ipa_res = &pdev->ipa_resource;
  3016. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  3017. /*
  3018. * Reset the tx completion doorbell address before invoking IPA disable
  3019. * pipes API to ensure that there is no access to IPA tx doorbell
  3020. * address post disable pipes.
  3021. */
  3022. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  3023. result = qdf_ipa_wdi_disable_pipes(hdl);
  3024. if (result) {
  3025. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3026. "%s: Disable WDI PIPE fail, code %d",
  3027. __func__, result);
  3028. qdf_assert_always(0);
  3029. return QDF_STATUS_E_FAILURE;
  3030. }
  3031. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  3032. if (!ipa_config_is_opt_wifi_dp_enabled()) {
  3033. qdf_atomic_set(&soc->ipa_map_allowed, 0);
  3034. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  3035. __func__, __LINE__);
  3036. }
  3037. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  3038. }
  3039. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  3040. qdf_ipa_wdi_hdl_t hdl)
  3041. {
  3042. qdf_ipa_wdi_perf_profile_t profile;
  3043. QDF_STATUS result;
  3044. profile.client = client;
  3045. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  3046. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  3047. if (result) {
  3048. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3049. "%s: ipa_wdi_set_perf_profile fail, code %d",
  3050. __func__, result);
  3051. return QDF_STATUS_E_FAILURE;
  3052. }
  3053. return QDF_STATUS_SUCCESS;
  3054. }
  3055. #ifdef QCA_SUPPORT_WDS_EXTENDED
  3056. /**
  3057. * dp_ipa_rx_wdsext_iface() - Forward RX exception packets to wdsext interface
  3058. * @soc_hdl: data path soc handle
  3059. * @peer_id: Peer id to get respective peer
  3060. * @skb: socket buffer
  3061. *
  3062. * Return: true on success, else false
  3063. */
  3064. bool dp_ipa_rx_wdsext_iface(struct cdp_soc_t *soc_hdl, uint8_t peer_id,
  3065. qdf_nbuf_t skb)
  3066. {
  3067. struct dp_txrx_peer *txrx_peer;
  3068. dp_txrx_ref_handle txrx_ref_handle = NULL;
  3069. struct dp_soc *dp_soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3070. bool status = false;
  3071. txrx_peer = dp_tgt_txrx_peer_get_ref_by_id(soc_hdl, peer_id,
  3072. &txrx_ref_handle,
  3073. DP_MOD_ID_IPA);
  3074. if (qdf_likely(txrx_peer)) {
  3075. if (dp_rx_deliver_to_stack_ext(dp_soc, txrx_peer->vdev,
  3076. txrx_peer, skb)
  3077. status = true;
  3078. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_IPA);
  3079. }
  3080. return status;
  3081. }
  3082. #endif
  3083. /**
  3084. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  3085. * @pdev: pdev
  3086. * @vdev: vdev
  3087. * @nbuf: skb
  3088. *
  3089. * Return: nbuf if TX fails and NULL if TX succeeds
  3090. */
  3091. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  3092. struct dp_vdev *vdev,
  3093. qdf_nbuf_t nbuf)
  3094. {
  3095. struct dp_peer *vdev_peer;
  3096. uint16_t len;
  3097. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  3098. if (qdf_unlikely(!vdev_peer))
  3099. return nbuf;
  3100. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  3101. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3102. return nbuf;
  3103. }
  3104. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  3105. len = qdf_nbuf_len(nbuf);
  3106. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  3107. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3108. rx.intra_bss.fail, 1, len,
  3109. 0);
  3110. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3111. return nbuf;
  3112. }
  3113. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3114. rx.intra_bss.pkts, 1, len, 0);
  3115. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3116. return NULL;
  3117. }
  3118. #ifdef IPA_OPT_WIFI_DP
  3119. /**
  3120. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  3121. *
  3122. * @soc_hdl: cdp soc
  3123. * @flt_params: filter tuple
  3124. *
  3125. * Return: QDF_STATUS
  3126. */
  3127. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  3128. void *flt_params)
  3129. {
  3130. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3131. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  3132. }
  3133. /**
  3134. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  3135. * add/remove result to ipa
  3136. *
  3137. * @flt0_rslt : result for filter0 add/remove
  3138. * @flt1_rslt : result for filter1 add/remove
  3139. *
  3140. * Return: void
  3141. */
  3142. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  3143. {
  3144. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  3145. }
  3146. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  3147. {
  3148. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3149. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3150. int response = 0;
  3151. response = hif_prevent_l1((hal_soc->hif_handle));
  3152. return response;
  3153. }
  3154. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  3155. {
  3156. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3157. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3158. hif_allow_l1(hal_soc->hif_handle);
  3159. }
  3160. /**
  3161. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  3162. * notification to ipa
  3163. *
  3164. * @flt0_rslt : result for filter0 release
  3165. * @flt1_rslt : result for filter1 release
  3166. *
  3167. *Return: void
  3168. */
  3169. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3170. {
  3171. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3172. }
  3173. /**
  3174. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3175. * notification to ipa
  3176. *
  3177. *@is_success : result of filter reservatiom
  3178. *
  3179. *Return: void
  3180. */
  3181. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3182. {
  3183. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3184. }
  3185. #endif
  3186. #ifdef IPA_WDS_EASYMESH_FEATURE
  3187. /**
  3188. * dp_ipa_peer_check() - Check for peer for given mac
  3189. * @soc: dp soc object
  3190. * @peer_mac_addr: peer mac address
  3191. * @vdev_id: vdev id
  3192. *
  3193. * Return: true if peer is found, else false
  3194. */
  3195. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3196. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3197. {
  3198. struct dp_ast_entry *ast_entry = NULL;
  3199. struct dp_peer *peer = NULL;
  3200. qdf_spin_lock_bh(&soc->ast_lock);
  3201. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3202. if ((!ast_entry) ||
  3203. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3204. qdf_spin_unlock_bh(&soc->ast_lock);
  3205. return false;
  3206. }
  3207. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3208. DP_MOD_ID_IPA);
  3209. if (!peer) {
  3210. qdf_spin_unlock_bh(&soc->ast_lock);
  3211. return false;
  3212. } else {
  3213. if (peer->vdev->vdev_id == vdev_id) {
  3214. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3215. qdf_spin_unlock_bh(&soc->ast_lock);
  3216. return true;
  3217. }
  3218. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3219. qdf_spin_unlock_bh(&soc->ast_lock);
  3220. return false;
  3221. }
  3222. }
  3223. #else
  3224. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3225. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3226. {
  3227. struct cdp_peer_info peer_info = {0};
  3228. struct dp_peer *peer = NULL;
  3229. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3230. CDP_WILD_PEER_TYPE);
  3231. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3232. if (peer) {
  3233. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3234. return true;
  3235. } else {
  3236. return false;
  3237. }
  3238. }
  3239. #endif
  3240. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3241. qdf_nbuf_t nbuf, bool *fwd_success)
  3242. {
  3243. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3244. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3245. DP_MOD_ID_IPA);
  3246. struct dp_pdev *pdev;
  3247. qdf_nbuf_t nbuf_copy;
  3248. uint8_t da_is_bcmc;
  3249. struct ethhdr *eh;
  3250. bool status = false;
  3251. *fwd_success = false; /* set default as failure */
  3252. /*
  3253. * WDI 3.0 skb->cb[] info from IPA driver
  3254. * skb->cb[0] = vdev_id
  3255. * skb->cb[1].bit#1 = da_is_bcmc
  3256. */
  3257. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3258. if (qdf_unlikely(!vdev))
  3259. return false;
  3260. pdev = vdev->pdev;
  3261. if (qdf_unlikely(!pdev))
  3262. goto out;
  3263. /* no fwd for station mode and just pass up to stack */
  3264. if (vdev->opmode == wlan_op_mode_sta)
  3265. goto out;
  3266. if (da_is_bcmc) {
  3267. nbuf_copy = qdf_nbuf_copy(nbuf);
  3268. if (!nbuf_copy)
  3269. goto out;
  3270. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3271. qdf_nbuf_free(nbuf_copy);
  3272. else
  3273. *fwd_success = true;
  3274. /* return false to pass original pkt up to stack */
  3275. goto out;
  3276. }
  3277. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3278. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3279. goto out;
  3280. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3281. goto out;
  3282. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3283. goto out;
  3284. /*
  3285. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3286. * Need to add skb to internal tracking table to avoid nbuf memory
  3287. * leak check for unallocated skb.
  3288. */
  3289. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3290. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3291. qdf_nbuf_free(nbuf);
  3292. else
  3293. *fwd_success = true;
  3294. status = true;
  3295. out:
  3296. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3297. return status;
  3298. }
  3299. #ifdef MDM_PLATFORM
  3300. bool dp_ipa_is_mdm_platform(void)
  3301. {
  3302. return true;
  3303. }
  3304. #else
  3305. bool dp_ipa_is_mdm_platform(void)
  3306. {
  3307. return false;
  3308. }
  3309. #endif
  3310. /**
  3311. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3312. * @soc: soc
  3313. * @nbuf: source skb
  3314. *
  3315. * Return: new nbuf if success and otherwise NULL
  3316. */
  3317. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3318. qdf_nbuf_t nbuf)
  3319. {
  3320. uint8_t *src_nbuf_data;
  3321. uint8_t *dst_nbuf_data;
  3322. qdf_nbuf_t dst_nbuf;
  3323. qdf_nbuf_t temp_nbuf = nbuf;
  3324. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3325. bool is_nbuf_head = true;
  3326. uint32_t copy_len = 0;
  3327. uint16_t buf_size;
  3328. buf_size = wlan_cfg_rx_buffer_size(soc->wlan_cfg_ctx);
  3329. dst_nbuf = qdf_nbuf_alloc(soc->osdev, buf_size,
  3330. RX_BUFFER_RESERVATION,
  3331. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3332. if (!dst_nbuf) {
  3333. dp_err_rl("nbuf allocate fail");
  3334. return NULL;
  3335. }
  3336. if ((nbuf_len + L3_HEADER_PADDING) > buf_size) {
  3337. qdf_nbuf_free(dst_nbuf);
  3338. dp_err_rl("nbuf is jumbo data");
  3339. return NULL;
  3340. }
  3341. /* prepeare to copy all data into new skb */
  3342. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3343. while (temp_nbuf) {
  3344. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3345. /* first head nbuf */
  3346. if (is_nbuf_head) {
  3347. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3348. soc->rx_pkt_tlv_size);
  3349. /* leave extra 2 bytes L3_HEADER_PADDING */
  3350. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3351. L3_HEADER_PADDING);
  3352. src_nbuf_data += soc->rx_pkt_tlv_size;
  3353. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3354. soc->rx_pkt_tlv_size;
  3355. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3356. is_nbuf_head = false;
  3357. } else {
  3358. copy_len = qdf_nbuf_len(temp_nbuf);
  3359. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3360. }
  3361. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3362. dst_nbuf_data += copy_len;
  3363. }
  3364. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3365. /* copy is done, free original nbuf */
  3366. qdf_nbuf_free(nbuf);
  3367. return dst_nbuf;
  3368. }
  3369. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3370. {
  3371. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3372. return nbuf;
  3373. /* WLAN IPA is run-time disabled */
  3374. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3375. return nbuf;
  3376. if (!qdf_nbuf_is_frag(nbuf))
  3377. return nbuf;
  3378. /* linearize skb for IPA */
  3379. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3380. }
  3381. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3382. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3383. const char *func, uint32_t line)
  3384. {
  3385. QDF_STATUS ret;
  3386. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3387. struct dp_pdev *pdev =
  3388. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3389. if (!pdev) {
  3390. dp_err("Invalid instance");
  3391. return QDF_STATUS_E_FAILURE;
  3392. }
  3393. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3394. dp_debug("SMMU S1 disabled");
  3395. return QDF_STATUS_SUCCESS;
  3396. }
  3397. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3398. if (ret)
  3399. return ret;
  3400. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3401. if (ret)
  3402. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3403. return ret;
  3404. }
  3405. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3406. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3407. uint32_t line)
  3408. {
  3409. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3410. struct dp_pdev *pdev =
  3411. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3412. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3413. dp_debug("SMMU S1 disabled");
  3414. return QDF_STATUS_SUCCESS;
  3415. }
  3416. if (!pdev) {
  3417. dp_err("Invalid pdev instance pdev_id:%d", pdev_id);
  3418. return QDF_STATUS_E_FAILURE;
  3419. }
  3420. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3421. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3422. return QDF_STATUS_E_FAILURE;
  3423. return QDF_STATUS_SUCCESS;
  3424. }
  3425. QDF_STATUS dp_ipa_rx_buf_pool_smmu_mapping(
  3426. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3427. bool create, const char *func, uint32_t line)
  3428. {
  3429. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3430. struct dp_pdev *pdev =
  3431. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3432. if (!pdev) {
  3433. dp_err("Invalid instance");
  3434. return QDF_STATUS_E_FAILURE;
  3435. }
  3436. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3437. dp_debug("SMMU S1 disabled");
  3438. return QDF_STATUS_SUCCESS;
  3439. }
  3440. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, create, func, line);
  3441. return QDF_STATUS_SUCCESS;
  3442. }
  3443. #ifdef IPA_WDS_EASYMESH_FEATURE
  3444. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3445. qdf_ipa_ast_info_type_t *data)
  3446. {
  3447. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3448. uint8_t *rx_tlv_hdr;
  3449. struct dp_peer *peer;
  3450. struct hal_rx_msdu_metadata msdu_metadata;
  3451. qdf_ipa_ast_info_type_t *ast_info;
  3452. if (!data) {
  3453. dp_err("Data is NULL !!!");
  3454. return QDF_STATUS_E_FAILURE;
  3455. }
  3456. ast_info = data;
  3457. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3458. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3459. DP_MOD_ID_IPA);
  3460. if (!peer) {
  3461. dp_err("Peer is NULL !!!!");
  3462. return QDF_STATUS_E_FAILURE;
  3463. }
  3464. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3465. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3466. ast_info->mac_addr_ad4_valid,
  3467. ast_info->first_msdu_in_mpdu_flag);
  3468. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3469. return QDF_STATUS_SUCCESS;
  3470. }
  3471. #endif
  3472. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3473. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3474. uint8_t vdev_id, uint8_t *peer_mac,
  3475. qdf_nbuf_t nbuf)
  3476. {
  3477. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3478. peer_mac, 0, vdev_id,
  3479. DP_MOD_ID_IPA);
  3480. struct dp_txrx_peer *txrx_peer;
  3481. uint8_t da_is_bcmc;
  3482. qdf_ether_header_t *eh;
  3483. if (!peer)
  3484. return QDF_STATUS_E_FAILURE;
  3485. txrx_peer = dp_get_txrx_peer(peer);
  3486. if (!txrx_peer) {
  3487. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3488. return QDF_STATUS_E_FAILURE;
  3489. }
  3490. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3491. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3492. if (da_is_bcmc) {
  3493. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3494. qdf_nbuf_len(nbuf), 0);
  3495. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3496. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3497. 1, qdf_nbuf_len(nbuf), 0);
  3498. }
  3499. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3500. return QDF_STATUS_SUCCESS;
  3501. }
  3502. void
  3503. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3504. {
  3505. uint8_t i = 0;
  3506. struct dp_rx_tid *rx_tid = NULL;
  3507. struct cdp_pkt_info rx_total = {0};
  3508. struct dp_txrx_peer *txrx_peer = NULL;
  3509. if (!peer->rx_tid)
  3510. return;
  3511. txrx_peer = dp_get_txrx_peer(peer);
  3512. if (!txrx_peer)
  3513. return;
  3514. for (i = 0; i < DP_MAX_TIDS; i++) {
  3515. rx_tid = &peer->rx_tid[i];
  3516. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3517. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3518. }
  3519. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3520. rx_total.num, 0);
  3521. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3522. rx_total.bytes, 0);
  3523. }
  3524. /**
  3525. * dp_ipa_update_vdev_stats(): update vdev stats
  3526. * @soc: soc handle
  3527. * @srcobj: DP_PEER object
  3528. * @arg: point to vdev stats structure
  3529. *
  3530. * Return: void
  3531. */
  3532. static inline
  3533. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3534. void *arg)
  3535. {
  3536. dp_peer_aggregate_tid_stats(srcobj);
  3537. dp_update_vdev_stats(soc, srcobj, arg);
  3538. }
  3539. /**
  3540. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3541. * @vdev: Data path vdev
  3542. * @vdev_stats: buffer to hold vdev stats
  3543. *
  3544. * Return: void
  3545. */
  3546. static inline
  3547. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3548. struct cdp_vdev_stats *vdev_stats)
  3549. {
  3550. struct dp_soc *soc = NULL;
  3551. if (!vdev || !vdev->pdev)
  3552. return;
  3553. soc = vdev->pdev->soc;
  3554. dp_update_vdev_ingress_stats(vdev);
  3555. dp_copy_vdev_stats_to_tgt_buf(vdev_stats, &vdev->stats, DP_XMIT_LINK);
  3556. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3557. DP_MOD_ID_GENERIC_STATS);
  3558. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3559. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3560. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3561. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3562. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3563. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3564. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3565. vdev_stats->rx.multicast.num;
  3566. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3567. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3568. vdev_stats->rx.multicast.bytes;
  3569. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3570. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3571. }
  3572. /**
  3573. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3574. * @pdev: Data path pdev
  3575. *
  3576. * Return: void
  3577. */
  3578. static inline
  3579. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3580. {
  3581. struct dp_vdev *vdev = NULL;
  3582. struct dp_soc *soc;
  3583. struct cdp_vdev_stats *vdev_stats =
  3584. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3585. if (!vdev_stats) {
  3586. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3587. pdev->soc);
  3588. return;
  3589. }
  3590. soc = pdev->soc;
  3591. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3592. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3593. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3594. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3595. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3596. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3597. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3598. dp_update_pdev_stats(pdev, vdev_stats);
  3599. dp_update_pdev_ingress_stats(pdev, vdev);
  3600. }
  3601. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3602. qdf_mem_free(vdev_stats);
  3603. }
  3604. /**
  3605. * dp_ipa_get_peer_stats - Get peer stats
  3606. * @peer: Data path peer
  3607. * @peer_stats: buffer to hold peer stats
  3608. *
  3609. * Return: void
  3610. */
  3611. static
  3612. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3613. struct cdp_peer_stats *peer_stats)
  3614. {
  3615. dp_peer_aggregate_tid_stats(peer);
  3616. dp_get_peer_stats(peer, peer_stats);
  3617. peer_stats->tx.tx_success.num =
  3618. peer_stats->tx.tx_ucast_success.num;
  3619. peer_stats->tx.tx_success.bytes =
  3620. peer_stats->tx.tx_ucast_success.bytes;
  3621. peer_stats->tx.ucast.num =
  3622. peer_stats->tx.tx_ucast_total.num;
  3623. peer_stats->tx.ucast.bytes =
  3624. peer_stats->tx.tx_ucast_total.bytes;
  3625. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3626. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3627. peer_stats->rx.multicast.num;
  3628. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3629. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3630. peer_stats->rx.multicast.bytes;
  3631. }
  3632. QDF_STATUS
  3633. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3634. struct cdp_pdev_stats *pdev_stats)
  3635. {
  3636. struct dp_pdev *pdev =
  3637. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3638. pdev_id);
  3639. if (!pdev)
  3640. return QDF_STATUS_E_FAILURE;
  3641. dp_ipa_aggregate_pdev_stats(pdev);
  3642. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3643. return QDF_STATUS_SUCCESS;
  3644. }
  3645. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3646. void *buf, bool is_aggregate)
  3647. {
  3648. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3649. struct cdp_vdev_stats *vdev_stats;
  3650. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3651. DP_MOD_ID_IPA);
  3652. if (!vdev)
  3653. return 1;
  3654. vdev_stats = (struct cdp_vdev_stats *)buf;
  3655. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3656. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3657. return 0;
  3658. }
  3659. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3660. uint8_t *peer_mac,
  3661. struct cdp_peer_stats *peer_stats)
  3662. {
  3663. struct dp_peer *peer = NULL;
  3664. struct cdp_peer_info peer_info = { 0 };
  3665. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3666. CDP_WILD_PEER_TYPE);
  3667. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3668. DP_MOD_ID_IPA);
  3669. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3670. if (!peer)
  3671. return QDF_STATUS_E_FAILURE;
  3672. dp_ipa_get_peer_stats(peer, peer_stats);
  3673. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3674. return QDF_STATUS_SUCCESS;
  3675. }
  3676. #endif
  3677. /**
  3678. * dp_ipa_get_wdi_version() - Get WDI version
  3679. * @soc_hdl: data path soc handle
  3680. * @wdi_ver: Out parameter for wdi version
  3681. *
  3682. * Get WDI version based on soc arch
  3683. *
  3684. * Return: None
  3685. */
  3686. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3687. {
  3688. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3689. if (soc->arch_ops.ipa_get_wdi_ver)
  3690. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3691. else
  3692. *wdi_ver = IPA_WDI_3;
  3693. }
  3694. #endif