dp_be_tx.c 56 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "hal_tx.h"
  25. #include <hal_be_api.h>
  26. #include <hal_be_tx.h>
  27. #include <dp_htt.h>
  28. #include "dp_internal.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  33. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_mutex_create(lock)
  34. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_mutex_destroy(lock)
  35. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_mutex_acquire(lock)
  36. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_mutex_release(lock)
  37. #else
  38. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_spinlock_create(lock)
  39. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_spinlock_destroy(lock)
  40. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_spin_lock_bh(lock)
  41. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_spin_unlock_bh(lock)
  42. #endif
  43. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  44. #ifdef WLAN_MCAST_MLO
  45. /* MLO peer id for reinject*/
  46. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  47. #define MAX_GSN_NUM 0x0FFF
  48. #ifdef QCA_MULTIPASS_SUPPORT
  49. #define INVALID_VLAN_ID 0xFFFF
  50. #define MULTIPASS_WITH_VLAN_ID 0xFFFE
  51. /**
  52. * struct dp_mlo_mpass_buf - Multipass buffer
  53. * @vlan_id: vlan_id of frame
  54. * @nbuf: pointer to skb buf
  55. */
  56. struct dp_mlo_mpass_buf {
  57. uint16_t vlan_id;
  58. qdf_nbuf_t nbuf;
  59. };
  60. #endif
  61. #endif
  62. #endif
  63. #define DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(_var) \
  64. HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var)
  65. #define DP_TX_WBM_COMPLETION_V3_VALID_GET(_var) \
  66. HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var)
  67. #define DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(_var) \
  68. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var)
  69. #define DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(_var) \
  70. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var)
  71. #define DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(_var) \
  72. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var)
  73. #define DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(_var) \
  74. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var)
  75. #define DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(_var) \
  76. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var)
  77. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  78. #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK
  79. /*
  80. * Value to mark ring desc is invalidated by buffer_virt_addr_63_32 field
  81. * of WBM2SW ring Desc.
  82. */
  83. #define DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE 0x12121212
  84. /**
  85. * dp_tx_comp_desc_check_and_invalidate() - sanity check for ring desc and
  86. * invalidate it after each reaping
  87. * @tx_comp_hal_desc: ring desc virtual address
  88. * @r_tx_desc: pointer to current dp TX Desc pointer
  89. * @tx_desc_va: the original 64 bits Desc VA got from ring Desc
  90. * @hw_cc_done: HW cookie conversion done or not
  91. *
  92. * If HW CC is done, check the buffer_virt_addr_63_32 value to know if
  93. * ring Desc is stale or not. if HW CC is not done, then compare PA between
  94. * ring Desc and current TX desc.
  95. *
  96. * Return: None.
  97. */
  98. static inline
  99. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  100. struct dp_tx_desc_s **r_tx_desc,
  101. uint64_t tx_desc_va,
  102. bool hw_cc_done)
  103. {
  104. qdf_dma_addr_t desc_dma_addr;
  105. if (qdf_likely(hw_cc_done)) {
  106. /* Check upper 32 bits */
  107. if (DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE ==
  108. (tx_desc_va >> 32))
  109. *r_tx_desc = NULL;
  110. /* Invalidate the ring desc for 32 ~ 63 bits of VA */
  111. hal_tx_comp_set_desc_va_63_32(
  112. tx_comp_hal_desc,
  113. DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE);
  114. } else {
  115. /* Compare PA between ring desc and current TX desc stored */
  116. desc_dma_addr = hal_tx_comp_get_paddr(tx_comp_hal_desc);
  117. if (desc_dma_addr != (*r_tx_desc)->dma_addr)
  118. *r_tx_desc = NULL;
  119. }
  120. }
  121. #else
  122. static inline
  123. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  124. struct dp_tx_desc_s **r_tx_desc,
  125. uint64_t tx_desc_va,
  126. bool hw_cc_done)
  127. {
  128. }
  129. #endif
  130. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  131. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  132. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  133. void *tx_comp_hal_desc,
  134. struct dp_tx_desc_s **r_tx_desc)
  135. {
  136. uint32_t tx_desc_id;
  137. uint64_t tx_desc_va = 0;
  138. bool hw_cc_done =
  139. hal_tx_comp_get_cookie_convert_done(tx_comp_hal_desc);
  140. if (qdf_likely(hw_cc_done)) {
  141. /* HW cookie conversion done */
  142. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  143. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  144. } else {
  145. /* SW do cookie conversion to VA */
  146. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  147. *r_tx_desc =
  148. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  149. }
  150. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  151. r_tx_desc, tx_desc_va,
  152. hw_cc_done);
  153. if (*r_tx_desc)
  154. (*r_tx_desc)->peer_id =
  155. dp_tx_comp_get_peer_id_be(soc,
  156. tx_comp_hal_desc);
  157. }
  158. #else
  159. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  160. void *tx_comp_hal_desc,
  161. struct dp_tx_desc_s **r_tx_desc)
  162. {
  163. uint64_t tx_desc_va;
  164. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  165. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  166. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  167. r_tx_desc,
  168. tx_desc_va,
  169. true);
  170. if (*r_tx_desc)
  171. (*r_tx_desc)->peer_id =
  172. dp_tx_comp_get_peer_id_be(soc,
  173. tx_comp_hal_desc);
  174. }
  175. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  176. #else
  177. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  178. void *tx_comp_hal_desc,
  179. struct dp_tx_desc_s **r_tx_desc)
  180. {
  181. uint32_t tx_desc_id;
  182. /* SW do cookie conversion to VA */
  183. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  184. *r_tx_desc =
  185. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  186. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  187. r_tx_desc, 0,
  188. false);
  189. if (*r_tx_desc)
  190. (*r_tx_desc)->peer_id =
  191. dp_tx_comp_get_peer_id_be(soc,
  192. tx_comp_hal_desc);
  193. }
  194. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  195. static inline
  196. void dp_tx_process_mec_notify_be(struct dp_soc *soc, uint8_t *status)
  197. {
  198. struct dp_vdev *vdev;
  199. uint8_t vdev_id;
  200. uint32_t *htt_desc = (uint32_t *)status;
  201. dp_assert_always_internal(soc->mec_fw_offload);
  202. /*
  203. * Get vdev id from HTT status word in case of MEC
  204. * notification
  205. */
  206. vdev_id = DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(htt_desc[4]);
  207. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  208. return;
  209. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  210. DP_MOD_ID_HTT_COMP);
  211. if (!vdev)
  212. return;
  213. dp_tx_mec_handler(vdev, status);
  214. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  215. }
  216. void dp_tx_process_htt_completion_be(struct dp_soc *soc,
  217. struct dp_tx_desc_s *tx_desc,
  218. uint8_t *status,
  219. uint8_t ring_id)
  220. {
  221. uint8_t tx_status;
  222. struct dp_pdev *pdev;
  223. struct dp_vdev *vdev = NULL;
  224. struct hal_tx_completion_status ts = {0};
  225. uint32_t *htt_desc = (uint32_t *)status;
  226. struct dp_txrx_peer *txrx_peer;
  227. dp_txrx_ref_handle txrx_ref_handle = NULL;
  228. struct cdp_tid_tx_stats *tid_stats = NULL;
  229. struct htt_soc *htt_handle;
  230. uint8_t vdev_id;
  231. uint16_t peer_id;
  232. uint8_t xmit_type;
  233. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  234. htt_handle = (struct htt_soc *)soc->htt_handle;
  235. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  236. /*
  237. * There can be scenario where WBM consuming descriptor enqueued
  238. * from TQM2WBM first and TQM completion can happen before MEC
  239. * notification comes from FW2WBM. Avoid access any field of tx
  240. * descriptor in case of MEC notify.
  241. */
  242. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  243. return dp_tx_process_mec_notify_be(soc, status);
  244. /*
  245. * If the descriptor is already freed in vdev_detach,
  246. * continue to next descriptor
  247. */
  248. if (qdf_unlikely(!tx_desc->flags)) {
  249. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  250. tx_desc->id);
  251. return;
  252. }
  253. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  254. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  255. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  256. goto release_tx_desc;
  257. }
  258. pdev = tx_desc->pdev;
  259. if (qdf_unlikely(!pdev)) {
  260. dp_tx_comp_warn("The pdev in TX desc is NULL, dropped.");
  261. dp_tx_comp_warn("tx_status: %u", tx_status);
  262. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  263. goto release_tx_desc;
  264. }
  265. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  266. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  267. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  268. goto release_tx_desc;
  269. }
  270. qdf_assert(tx_desc->pdev);
  271. vdev_id = tx_desc->vdev_id;
  272. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  273. DP_MOD_ID_HTT_COMP);
  274. if (qdf_unlikely(!vdev)) {
  275. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  276. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  277. goto release_tx_desc;
  278. }
  279. switch (tx_status) {
  280. case HTT_TX_FW2WBM_TX_STATUS_OK:
  281. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  282. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  283. {
  284. uint8_t tid;
  285. uint8_t transmit_cnt_valid = 0;
  286. if (DP_TX_WBM_COMPLETION_V3_VALID_GET(htt_desc[3])) {
  287. ts.peer_id =
  288. DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(
  289. htt_desc[3]);
  290. ts.tid =
  291. DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(
  292. htt_desc[3]);
  293. } else {
  294. ts.peer_id = HTT_INVALID_PEER;
  295. ts.tid = HTT_INVALID_TID;
  296. }
  297. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  298. ts.ppdu_id =
  299. DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(
  300. htt_desc[2]);
  301. ts.ack_frame_rssi =
  302. DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(
  303. htt_desc[2]);
  304. transmit_cnt_valid =
  305. DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(
  306. htt_desc[3]);
  307. if (transmit_cnt_valid)
  308. ts.transmit_cnt =
  309. HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(
  310. htt_desc[1]);
  311. ts.tsf = htt_desc[4];
  312. ts.first_msdu = 1;
  313. ts.last_msdu = 1;
  314. switch (tx_status) {
  315. case HTT_TX_FW2WBM_TX_STATUS_OK:
  316. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  317. break;
  318. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  319. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  320. break;
  321. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  322. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  323. break;
  324. }
  325. tid = ts.tid;
  326. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  327. tid = CDP_MAX_DATA_TIDS - 1;
  328. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  329. if (qdf_unlikely(pdev->delay_stats_flag) ||
  330. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  331. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  332. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  333. tid_stats->htt_status_cnt[tx_status]++;
  334. peer_id = dp_tx_comp_adjust_peer_id_be(soc, ts.peer_id);
  335. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  336. &txrx_ref_handle,
  337. DP_MOD_ID_HTT_COMP);
  338. if (qdf_likely(txrx_peer))
  339. dp_tx_update_peer_basic_stats(
  340. txrx_peer,
  341. qdf_nbuf_len(tx_desc->nbuf),
  342. tx_status,
  343. pdev->enhanced_stats_en);
  344. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  345. ring_id);
  346. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  347. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  348. if (qdf_likely(txrx_peer))
  349. dp_txrx_peer_unref_delete(txrx_ref_handle,
  350. DP_MOD_ID_HTT_COMP);
  351. break;
  352. }
  353. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  354. {
  355. uint8_t reinject_reason;
  356. reinject_reason =
  357. HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(
  358. htt_desc[1]);
  359. dp_tx_reinject_handler(soc, vdev, tx_desc,
  360. status, reinject_reason);
  361. break;
  362. }
  363. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  364. {
  365. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  366. break;
  367. }
  368. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  369. {
  370. xmit_type = qdf_nbuf_get_vdev_xmit_type(tx_desc->nbuf);
  371. DP_STATS_INC(vdev,
  372. tx_i[xmit_type].dropped.fail_per_pkt_vdev_id_check,
  373. 1);
  374. goto release_tx_desc;
  375. }
  376. default:
  377. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  378. tx_status);
  379. goto release_tx_desc;
  380. }
  381. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  382. return;
  383. release_tx_desc:
  384. dp_tx_comp_free_buf(soc, tx_desc, false);
  385. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  386. if (vdev)
  387. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  388. }
  389. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  390. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  391. /**
  392. * dp_tx_get_rbm_id_be() - Get the RBM ID for data transmission completion.
  393. * @soc: DP soc structure pointer
  394. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  395. *
  396. * Return: RBM ID corresponding to TCL ring_id
  397. */
  398. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  399. uint8_t ring_id)
  400. {
  401. return 0;
  402. }
  403. #else
  404. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  405. uint8_t ring_id)
  406. {
  407. return (ring_id ? soc->wbm_sw0_bm_id + (ring_id - 1) :
  408. HAL_WBM_SW2_BM_ID(soc->wbm_sw0_bm_id));
  409. }
  410. #endif /*DP_TX_IMPLICIT_RBM_MAPPING*/
  411. #else
  412. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  413. uint8_t tcl_index)
  414. {
  415. uint8_t rbm;
  416. rbm = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_index);
  417. dp_verbose_debug("tcl_id %u rbm %u", tcl_index, rbm);
  418. return rbm;
  419. }
  420. #endif
  421. #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES
  422. /**
  423. * dp_tx_set_min_rates_for_critical_frames()- sets min-rates for critical pkts
  424. * @soc: DP soc structure pointer
  425. * @hal_tx_desc: HAL descriptor where fields are set
  426. * @nbuf: skb to be considered for min rates
  427. *
  428. * The function relies on upper layers to set QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL
  429. * and uses it to determine if the frame is critical. For a critical frame,
  430. * flow override bits are set to classify the frame into HW's high priority
  431. * queue. The HW will pick pre-configured min rates for such packets.
  432. *
  433. * Return: None
  434. */
  435. static void
  436. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  437. uint32_t *hal_tx_desc,
  438. qdf_nbuf_t nbuf)
  439. {
  440. /*
  441. * Critical frames should be queued to the high priority queue for the TID on
  442. * on which they are sent out (for the concerned peer).
  443. * FW is using HTT_MSDU_Q_IDX 2 for HOL (high priority) queue.
  444. * htt_msdu_idx = (2 * who_classify_info_sel) + flow_override
  445. * Hence, using who_classify_info_sel = 1, flow_override = 0 to select
  446. * HOL queue.
  447. */
  448. if (QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL(nbuf)) {
  449. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  450. hal_tx_desc_set_flow_override(hal_tx_desc, 0);
  451. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  452. hal_tx_desc_set_tx_notify_frame(hal_tx_desc,
  453. TX_SEMI_HARD_NOTIFY_E);
  454. }
  455. }
  456. #else
  457. static inline void
  458. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  459. uint32_t *hal_tx_desc_cached,
  460. qdf_nbuf_t nbuf)
  461. {
  462. }
  463. #endif
  464. #ifdef DP_TX_PACKET_INSPECT_FOR_ILP
  465. /**
  466. * dp_tx_set_particular_tx_queue() - set particular TX TQM flow queue 3 for
  467. * TX packets, currently TCP ACK only
  468. * @soc: DP soc structure pointer
  469. * @hal_tx_desc: HAL descriptor where fields are set
  470. * @nbuf: skb to be considered for particular TX queue
  471. *
  472. * Return: None
  473. */
  474. static inline
  475. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  476. uint32_t *hal_tx_desc,
  477. qdf_nbuf_t nbuf)
  478. {
  479. if (!soc->tx_ilp_enable)
  480. return;
  481. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  482. QDF_NBUF_CB_PACKET_TYPE_TCP_ACK)) {
  483. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  484. hal_tx_desc_set_flow_override(hal_tx_desc, 1);
  485. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  486. }
  487. }
  488. #else
  489. static inline
  490. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  491. uint32_t *hal_tx_desc,
  492. qdf_nbuf_t nbuf)
  493. {
  494. }
  495. #endif
  496. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  497. defined(WLAN_MCAST_MLO)
  498. #ifdef QCA_MULTIPASS_SUPPORT
  499. /**
  500. * dp_tx_mlo_mcast_multipass_lookup() - lookup vlan_id in mpass peer list
  501. * @be_vdev: Handle to DP be_vdev structure
  502. * @ptnr_vdev: DP ptnr_vdev handle
  503. * @arg: pointer to dp_mlo_mpass_ buf
  504. *
  505. * Return: None
  506. */
  507. static void
  508. dp_tx_mlo_mcast_multipass_lookup(struct dp_vdev_be *be_vdev,
  509. struct dp_vdev *ptnr_vdev,
  510. void *arg)
  511. {
  512. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  513. struct dp_txrx_peer *txrx_peer = NULL;
  514. struct vlan_ethhdr *veh = NULL;
  515. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(ptr->nbuf);
  516. uint16_t vlan_id = 0;
  517. bool not_vlan = ((ptnr_vdev->tx_encap_type == htt_cmn_pkt_type_raw) ||
  518. (htons(eh->ether_type) != ETH_P_8021Q));
  519. if (qdf_unlikely(not_vlan))
  520. return;
  521. veh = (struct vlan_ethhdr *)eh;
  522. vlan_id = (ntohs(veh->h_vlan_TCI) & VLAN_VID_MASK);
  523. qdf_spin_lock_bh(&ptnr_vdev->mpass_peer_mutex);
  524. TAILQ_FOREACH(txrx_peer, &ptnr_vdev->mpass_peer_list,
  525. mpass_peer_list_elem) {
  526. if (vlan_id == txrx_peer->vlan_id) {
  527. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  528. ptr->vlan_id = vlan_id;
  529. return;
  530. }
  531. }
  532. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  533. }
  534. /**
  535. * dp_tx_mlo_mcast_multipass_send() - send multipass MLO Mcast packets
  536. * @be_vdev: Handle to DP be_vdev structure
  537. * @ptnr_vdev: DP ptnr_vdev handle
  538. * @arg: pointer to dp_mlo_mpass_ buf
  539. *
  540. * Return: None
  541. */
  542. static void
  543. dp_tx_mlo_mcast_multipass_send(struct dp_vdev_be *be_vdev,
  544. struct dp_vdev *ptnr_vdev,
  545. void *arg)
  546. {
  547. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  548. struct dp_tx_msdu_info_s msdu_info;
  549. struct dp_vdev_be *be_ptnr_vdev = NULL;
  550. qdf_nbuf_t nbuf_clone;
  551. uint16_t group_key = 0;
  552. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  553. if (be_vdev != be_ptnr_vdev) {
  554. nbuf_clone = qdf_nbuf_clone(ptr->nbuf);
  555. if (qdf_unlikely(!nbuf_clone)) {
  556. dp_tx_debug("nbuf clone failed");
  557. return;
  558. }
  559. } else {
  560. nbuf_clone = ptr->nbuf;
  561. }
  562. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  563. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  564. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  565. msdu_info.xmit_type = qdf_nbuf_get_vdev_xmit_type(ptr->nbuf);
  566. if (ptr->vlan_id == MULTIPASS_WITH_VLAN_ID) {
  567. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  568. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(
  569. msdu_info.meta_data[0], 1);
  570. } else {
  571. /* return when vlan map is not initialized */
  572. if (!ptnr_vdev->iv_vlan_map)
  573. goto nbuf_free;
  574. group_key = ptnr_vdev->iv_vlan_map[ptr->vlan_id];
  575. /*
  576. * If group key is not installed, drop the frame.
  577. */
  578. if (!group_key)
  579. goto nbuf_free;
  580. dp_tx_remove_vlan_tag(ptnr_vdev, nbuf_clone);
  581. dp_tx_add_groupkey_metadata(ptnr_vdev, &msdu_info, group_key);
  582. msdu_info.exception_fw = 1;
  583. }
  584. nbuf_clone = dp_tx_send_msdu_single(
  585. ptnr_vdev,
  586. nbuf_clone,
  587. &msdu_info,
  588. DP_MLO_MCAST_REINJECT_PEER_ID,
  589. NULL);
  590. nbuf_free:
  591. if (qdf_unlikely(nbuf_clone)) {
  592. dp_info("pkt send failed");
  593. qdf_nbuf_free(nbuf_clone);
  594. return;
  595. }
  596. }
  597. /**
  598. * dp_tx_mlo_mcast_multipass_handler - If frame needs multipass processing
  599. * @soc: DP soc handle
  600. * @vdev: DP vdev handle
  601. * @nbuf: nbuf to be enqueued
  602. *
  603. * Return: true if handling is done else false
  604. */
  605. static bool
  606. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc,
  607. struct dp_vdev *vdev,
  608. qdf_nbuf_t nbuf)
  609. {
  610. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  611. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  612. qdf_nbuf_t nbuf_copy = NULL;
  613. struct dp_mlo_mpass_buf mpass_buf;
  614. memset(&mpass_buf, 0, sizeof(struct dp_mlo_mpass_buf));
  615. mpass_buf.vlan_id = INVALID_VLAN_ID;
  616. mpass_buf.nbuf = nbuf;
  617. dp_tx_mlo_mcast_multipass_lookup(be_vdev, vdev, &mpass_buf);
  618. if (mpass_buf.vlan_id == INVALID_VLAN_ID) {
  619. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  620. dp_tx_mlo_mcast_multipass_lookup,
  621. &mpass_buf, DP_MOD_ID_TX,
  622. DP_ALL_VDEV_ITER,
  623. DP_VDEV_ITERATE_SKIP_SELF);
  624. /*
  625. * Do not drop the frame when vlan_id doesn't match.
  626. * Send the frame as it is.
  627. */
  628. if (mpass_buf.vlan_id == INVALID_VLAN_ID)
  629. return false;
  630. }
  631. /* AP can have classic clients, special clients &
  632. * classic repeaters.
  633. * 1. Classic clients & special client:
  634. * Remove vlan header, find corresponding group key
  635. * index, fill in metaheader and enqueue multicast
  636. * frame to TCL.
  637. * 2. Classic repeater:
  638. * Pass through to classic repeater with vlan tag
  639. * intact without any group key index. Hardware
  640. * will know which key to use to send frame to
  641. * repeater.
  642. */
  643. nbuf_copy = qdf_nbuf_copy(nbuf);
  644. /*
  645. * Send multicast frame to special peers even
  646. * if pass through to classic repeater fails.
  647. */
  648. if (nbuf_copy) {
  649. struct dp_mlo_mpass_buf mpass_buf_copy = {0};
  650. mpass_buf_copy.vlan_id = MULTIPASS_WITH_VLAN_ID;
  651. mpass_buf_copy.nbuf = nbuf_copy;
  652. /* send frame on partner vdevs */
  653. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  654. dp_tx_mlo_mcast_multipass_send,
  655. &mpass_buf_copy, DP_MOD_ID_TX,
  656. DP_LINK_VDEV_ITER,
  657. DP_VDEV_ITERATE_SKIP_SELF);
  658. /* send frame on mcast primary vdev */
  659. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf_copy);
  660. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  661. be_vdev->mlo_dev_ctxt->seq_num = 0;
  662. else
  663. be_vdev->mlo_dev_ctxt->seq_num++;
  664. }
  665. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  666. dp_tx_mlo_mcast_multipass_send,
  667. &mpass_buf, DP_MOD_ID_TX, DP_LINK_VDEV_ITER,
  668. DP_VDEV_ITERATE_SKIP_SELF);
  669. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf);
  670. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  671. be_vdev->mlo_dev_ctxt->seq_num = 0;
  672. else
  673. be_vdev->mlo_dev_ctxt->seq_num++;
  674. return true;
  675. }
  676. #else
  677. static bool
  678. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  679. qdf_nbuf_t nbuf)
  680. {
  681. return false;
  682. }
  683. #endif
  684. void
  685. dp_tx_mlo_mcast_pkt_send(struct dp_vdev_be *be_vdev,
  686. struct dp_vdev *ptnr_vdev,
  687. void *arg)
  688. {
  689. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  690. qdf_nbuf_t nbuf_clone;
  691. struct dp_vdev_be *be_ptnr_vdev = NULL;
  692. struct dp_tx_msdu_info_s msdu_info;
  693. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  694. if (be_vdev != be_ptnr_vdev) {
  695. nbuf_clone = qdf_nbuf_clone(nbuf);
  696. if (qdf_unlikely(!nbuf_clone)) {
  697. dp_tx_debug("nbuf clone failed");
  698. return;
  699. }
  700. } else {
  701. nbuf_clone = nbuf;
  702. }
  703. /* NAWDS clients will accepts on 4 addr format MCAST packets
  704. * This will ensure to send packets in 4 addr format to NAWDS clients.
  705. */
  706. if (qdf_unlikely(ptnr_vdev->nawds_enabled)) {
  707. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  708. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  709. dp_tx_nawds_handler(ptnr_vdev->pdev->soc, ptnr_vdev,
  710. &msdu_info, nbuf_clone, DP_INVALID_PEER);
  711. }
  712. if (qdf_unlikely(dp_tx_proxy_arp(ptnr_vdev, nbuf_clone) !=
  713. QDF_STATUS_SUCCESS)) {
  714. qdf_nbuf_free(nbuf_clone);
  715. return;
  716. }
  717. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  718. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  719. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  720. msdu_info.xmit_type = qdf_nbuf_get_vdev_xmit_type(nbuf_clone);
  721. DP_STATS_INC(ptnr_vdev,
  722. tx_i[msdu_info.xmit_type].mlo_mcast.send_pkt_count, 1);
  723. nbuf_clone = dp_tx_send_msdu_single(
  724. ptnr_vdev,
  725. nbuf_clone,
  726. &msdu_info,
  727. DP_MLO_MCAST_REINJECT_PEER_ID,
  728. NULL);
  729. if (qdf_unlikely(nbuf_clone)) {
  730. DP_STATS_INC(ptnr_vdev,
  731. tx_i[msdu_info.xmit_type].mlo_mcast.fail_pkt_count,
  732. 1);
  733. dp_info("pkt send failed");
  734. qdf_nbuf_free(nbuf_clone);
  735. return;
  736. }
  737. }
  738. static inline void
  739. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  740. struct dp_vdev *vdev,
  741. struct dp_tx_msdu_info_s *msdu_info)
  742. {
  743. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, msdu_info->vdev_id);
  744. }
  745. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  746. struct dp_vdev *vdev,
  747. qdf_nbuf_t nbuf)
  748. {
  749. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  750. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  751. if (qdf_unlikely(vdev->multipass_en) &&
  752. dp_tx_mlo_mcast_multipass_handler(soc, vdev, nbuf))
  753. return;
  754. /* send frame on partner vdevs */
  755. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  756. dp_tx_mlo_mcast_pkt_send,
  757. nbuf, DP_MOD_ID_REINJECT, DP_LINK_VDEV_ITER,
  758. DP_VDEV_ITERATE_SKIP_SELF);
  759. /* send frame on mcast primary vdev */
  760. dp_tx_mlo_mcast_pkt_send(be_vdev, vdev, nbuf);
  761. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  762. be_vdev->mlo_dev_ctxt->seq_num = 0;
  763. else
  764. be_vdev->mlo_dev_ctxt->seq_num++;
  765. }
  766. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  767. struct dp_vdev *vdev)
  768. {
  769. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  770. if (be_vdev->mcast_primary)
  771. return true;
  772. return false;
  773. }
  774. #if defined(CONFIG_MLO_SINGLE_DEV)
  775. static void
  776. dp_tx_mlo_mcast_enhance_be(struct dp_vdev_be *be_vdev,
  777. struct dp_vdev *ptnr_vdev,
  778. void *arg)
  779. {
  780. struct dp_vdev *vdev = (struct dp_vdev *)be_vdev;
  781. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  782. if (vdev == ptnr_vdev)
  783. return;
  784. /*
  785. * Hold the reference to avoid free of nbuf in
  786. * dp_tx_mcast_enhance() in case of successful
  787. * conversion
  788. */
  789. qdf_nbuf_ref(nbuf);
  790. if (qdf_unlikely(!dp_tx_mcast_enhance(ptnr_vdev, nbuf)))
  791. return;
  792. qdf_nbuf_free(nbuf);
  793. }
  794. qdf_nbuf_t
  795. dp_tx_mlo_mcast_send_be(struct dp_soc *soc, struct dp_vdev *vdev,
  796. qdf_nbuf_t nbuf,
  797. struct cdp_tx_exception_metadata *tx_exc_metadata)
  798. {
  799. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  800. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  801. if (!tx_exc_metadata->is_mlo_mcast)
  802. return nbuf;
  803. if (!be_vdev->mcast_primary) {
  804. qdf_nbuf_free(nbuf);
  805. return NULL;
  806. }
  807. /*
  808. * In the single netdev model avoid reinjection path as mcast
  809. * packet is identified in upper layers while peer search to find
  810. * primary TQM based on dest mac addr
  811. *
  812. * New bonding interface added into the bridge so MCSD will update
  813. * snooping table and wifi driver populates the entries in appropriate
  814. * child net devices.
  815. */
  816. if (vdev->mcast_enhancement_en) {
  817. /*
  818. * As dp_tx_mcast_enhance() can consume the nbuf incase of
  819. * successful conversion hold the reference of nbuf.
  820. *
  821. * Hold the reference to tx on partner links
  822. */
  823. qdf_nbuf_ref(nbuf);
  824. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf))) {
  825. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  826. dp_tx_mlo_mcast_enhance_be,
  827. nbuf, DP_MOD_ID_TX,
  828. DP_ALL_VDEV_ITER,
  829. DP_VDEV_ITERATE_SKIP_SELF);
  830. qdf_nbuf_free(nbuf);
  831. return NULL;
  832. }
  833. /* release reference taken above */
  834. qdf_nbuf_free(nbuf);
  835. }
  836. dp_tx_mlo_mcast_handler_be(soc, vdev, nbuf);
  837. return NULL;
  838. }
  839. #endif
  840. #else
  841. static inline void
  842. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  843. struct dp_vdev *vdev,
  844. struct dp_tx_msdu_info_s *msdu_info)
  845. {
  846. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, vdev->vdev_id);
  847. }
  848. #endif
  849. #if defined(WLAN_FEATURE_11BE_MLO) && !defined(WLAN_MLO_MULTI_CHIP) && \
  850. !defined(WLAN_MCAST_MLO)
  851. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  852. struct dp_vdev *vdev,
  853. qdf_nbuf_t nbuf)
  854. {
  855. }
  856. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  857. struct dp_vdev *vdev)
  858. {
  859. return false;
  860. }
  861. #endif
  862. #ifdef CONFIG_SAWF
  863. /**
  864. * dp_sawf_config_be - Configure sawf specific fields in tcl
  865. *
  866. * @soc: DP soc handle
  867. * @hal_tx_desc_cached: tx descriptor
  868. * @fw_metadata: firmware metadata
  869. * @nbuf: skb buffer
  870. * @msdu_info: msdu info
  871. *
  872. * Return: tid value in mark metadata
  873. */
  874. uint8_t dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  875. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  876. struct dp_tx_msdu_info_s *msdu_info)
  877. {
  878. uint8_t q_id = 0;
  879. uint8_t tid = HTT_TX_EXT_TID_INVALID;
  880. q_id = dp_sawf_queue_id_get(nbuf);
  881. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  882. return HTT_TX_EXT_TID_INVALID;
  883. tid = (q_id & (CDP_DATA_TID_MAX - 1));
  884. if (msdu_info)
  885. msdu_info->tid = tid;
  886. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  887. (q_id & (CDP_DATA_TID_MAX - 1)));
  888. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  889. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  890. return tid;
  891. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  892. return tid;
  893. if (fw_metadata)
  894. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  895. hal_tx_desc_set_flow_override_enable(hal_tx_desc_cached,
  896. DP_TX_FLOW_OVERRIDE_ENABLE);
  897. hal_tx_desc_set_flow_override(hal_tx_desc_cached,
  898. DP_TX_FLOW_OVERRIDE_GET(q_id));
  899. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc_cached,
  900. DP_TX_WHO_CLFY_INF_SEL_GET(q_id));
  901. return tid;
  902. }
  903. #else
  904. static inline
  905. uint8_t dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  906. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  907. struct dp_tx_msdu_info_s *msdu_info)
  908. {
  909. return HTT_TX_EXT_TID_INVALID;
  910. }
  911. static inline
  912. QDF_STATUS dp_sawf_tx_enqueue_peer_stats(struct dp_soc *soc,
  913. struct dp_tx_desc_s *tx_desc)
  914. {
  915. return QDF_STATUS_SUCCESS;
  916. }
  917. static inline
  918. QDF_STATUS dp_sawf_tx_enqueue_fail_peer_stats(struct dp_soc *soc,
  919. struct dp_tx_desc_s *tx_desc)
  920. {
  921. return QDF_STATUS_SUCCESS;
  922. }
  923. #endif
  924. #ifdef WLAN_SUPPORT_PPEDS
  925. /**
  926. * dp_ppeds_stats() - Accounting fw2wbm_tx_drop drops in Tx path
  927. * @soc: Handle to DP Soc structure
  928. * @peer_id: Peer ID in the descriptor
  929. *
  930. * Return: NONE
  931. */
  932. static inline
  933. void dp_ppeds_stats(struct dp_soc *soc, uint16_t peer_id)
  934. {
  935. struct dp_vdev *vdev = NULL;
  936. struct dp_txrx_peer *txrx_peer = NULL;
  937. dp_txrx_ref_handle txrx_ref_handle = NULL;
  938. DP_STATS_INC(soc, tx.fw2wbm_tx_drop, 1);
  939. txrx_peer = dp_txrx_peer_get_ref_by_id(soc,
  940. peer_id,
  941. &txrx_ref_handle,
  942. DP_MOD_ID_TX_COMP);
  943. if (txrx_peer) {
  944. vdev = txrx_peer->vdev;
  945. DP_STATS_INC(vdev, tx_i[DP_XMIT_LINK].dropped.fw2wbm_tx_drop, 1);
  946. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  947. }
  948. }
  949. int dp_ppeds_tx_comp_handler(struct dp_soc_be *be_soc, uint32_t quota)
  950. {
  951. uint32_t num_avail_for_reap = 0;
  952. void *tx_comp_hal_desc;
  953. uint8_t buf_src, status = 0;
  954. uint32_t count = 0;
  955. struct dp_tx_desc_s *tx_desc = NULL;
  956. struct dp_tx_desc_s *head_desc = NULL;
  957. struct dp_tx_desc_s *tail_desc = NULL;
  958. struct dp_soc *soc = &be_soc->soc;
  959. void *last_prefetch_hw_desc = NULL;
  960. struct dp_tx_desc_s *last_prefetch_sw_desc = NULL;
  961. qdf_nbuf_t nbuf;
  962. hal_soc_handle_t hal_soc = soc->hal_soc;
  963. hal_ring_handle_t hal_ring_hdl =
  964. be_soc->ppeds_wbm_release_ring.hal_srng;
  965. struct dp_txrx_peer *txrx_peer = NULL;
  966. uint16_t peer_id = CDP_INVALID_PEER;
  967. dp_txrx_ref_handle txrx_ref_handle = NULL;
  968. struct dp_vdev *vdev = NULL;
  969. struct dp_pdev *pdev = NULL;
  970. struct dp_srng *srng;
  971. if (qdf_unlikely(dp_srng_access_start(NULL, soc, hal_ring_hdl))) {
  972. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  973. return 0;
  974. }
  975. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  976. if (num_avail_for_reap >= quota)
  977. num_avail_for_reap = quota;
  978. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  979. last_prefetch_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  980. num_avail_for_reap);
  981. srng = &be_soc->ppeds_wbm_release_ring;
  982. if (srng) {
  983. hal_update_ring_util(soc->hal_soc, srng->hal_srng,
  984. WBM2SW_RELEASE,
  985. &be_soc->ppeds_wbm_release_ring.stats);
  986. }
  987. while (qdf_likely(num_avail_for_reap--)) {
  988. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  989. if (qdf_unlikely(!tx_comp_hal_desc))
  990. break;
  991. buf_src = hal_tx_comp_get_buffer_source(hal_soc,
  992. tx_comp_hal_desc);
  993. if (qdf_unlikely(buf_src != HAL_TX_COMP_RELEASE_SOURCE_TQM &&
  994. buf_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  995. dp_err("Tx comp release_src != TQM | FW but from %d",
  996. buf_src);
  997. dp_assert_always_internal_ds_stat(0, be_soc,
  998. tx.tx_comp_buf_src);
  999. continue;
  1000. }
  1001. dp_tx_comp_get_params_from_hal_desc_be(soc, tx_comp_hal_desc,
  1002. &tx_desc);
  1003. if (!tx_desc) {
  1004. dp_err("unable to retrieve tx_desc!");
  1005. dp_assert_always_internal_ds_stat(0, be_soc,
  1006. tx.tx_comp_desc_null);
  1007. continue;
  1008. }
  1009. if (qdf_unlikely(!(tx_desc->flags &
  1010. DP_TX_DESC_FLAG_ALLOCATED) ||
  1011. !(tx_desc->flags & DP_TX_DESC_FLAG_PPEDS))) {
  1012. dp_assert_always_internal_ds_stat(0, be_soc,
  1013. tx.tx_comp_invalid_flag);
  1014. continue;
  1015. }
  1016. tx_desc->buffer_src = buf_src;
  1017. if (qdf_unlikely(buf_src == HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1018. status = hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1019. if (status != HTT_TX_FW2WBM_TX_STATUS_OK)
  1020. dp_ppeds_stats(soc, tx_desc->peer_id);
  1021. nbuf = dp_ppeds_tx_desc_free(soc, tx_desc);
  1022. qdf_nbuf_free(nbuf);
  1023. } else {
  1024. tx_desc->tx_status =
  1025. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1026. /*
  1027. * Add desc sync to account for extended statistics
  1028. * during Tx completion.
  1029. */
  1030. if (peer_id != tx_desc->peer_id) {
  1031. if (txrx_peer) {
  1032. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1033. DP_MOD_ID_TX_COMP);
  1034. txrx_peer = NULL;
  1035. vdev = NULL;
  1036. pdev = NULL;
  1037. }
  1038. peer_id = tx_desc->peer_id;
  1039. txrx_peer =
  1040. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  1041. &txrx_ref_handle,
  1042. DP_MOD_ID_TX_COMP);
  1043. if (txrx_peer) {
  1044. vdev = txrx_peer->vdev;
  1045. if (!vdev)
  1046. goto next_desc;
  1047. pdev = vdev->pdev;
  1048. if (!pdev)
  1049. goto next_desc;
  1050. dp_tx_desc_update_fast_comp_flag(soc,
  1051. tx_desc,
  1052. !pdev->enhanced_stats_en);
  1053. if (pdev->enhanced_stats_en) {
  1054. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1055. &tx_desc->comp, 1);
  1056. }
  1057. }
  1058. } else if (txrx_peer && vdev && pdev) {
  1059. dp_tx_desc_update_fast_comp_flag(soc,
  1060. tx_desc,
  1061. !pdev->enhanced_stats_en);
  1062. if (pdev->enhanced_stats_en) {
  1063. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1064. &tx_desc->comp, 1);
  1065. }
  1066. }
  1067. next_desc:
  1068. if (!head_desc) {
  1069. head_desc = tx_desc;
  1070. tail_desc = tx_desc;
  1071. }
  1072. tail_desc->next = tx_desc;
  1073. tx_desc->next = NULL;
  1074. tail_desc = tx_desc;
  1075. count++;
  1076. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  1077. num_avail_for_reap,
  1078. hal_ring_hdl,
  1079. &last_prefetch_hw_desc,
  1080. &last_prefetch_sw_desc);
  1081. }
  1082. }
  1083. dp_srng_access_end(NULL, soc, hal_ring_hdl);
  1084. if (txrx_peer)
  1085. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1086. DP_MOD_ID_TX_COMP);
  1087. if (head_desc)
  1088. dp_tx_comp_process_desc_list(soc, head_desc,
  1089. CDP_MAX_TX_COMP_PPE_RING);
  1090. return count;
  1091. }
  1092. #endif
  1093. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  1094. static inline void
  1095. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1096. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1097. uint16_t *ast_idx, uint16_t *ast_hash)
  1098. {
  1099. struct dp_peer *peer = NULL;
  1100. if (tx_exc_metadata->is_wds_extended) {
  1101. peer = dp_peer_get_ref_by_id(soc, tx_exc_metadata->peer_id,
  1102. DP_MOD_ID_TX);
  1103. if (peer) {
  1104. *ast_idx = peer->ast_idx;
  1105. *ast_hash = peer->ast_hash;
  1106. hal_tx_desc_set_index_lookup_override
  1107. (soc->hal_soc,
  1108. hal_tx_desc_cached,
  1109. 0x1);
  1110. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  1111. }
  1112. } else {
  1113. return;
  1114. }
  1115. }
  1116. #else
  1117. static inline void
  1118. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1119. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1120. uint16_t *ast_idx, uint16_t *ast_hash)
  1121. {
  1122. }
  1123. #endif
  1124. QDF_STATUS
  1125. dp_tx_hw_enqueue_be(struct dp_soc *soc, struct dp_vdev *vdev,
  1126. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1127. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1128. struct dp_tx_msdu_info_s *msdu_info)
  1129. {
  1130. void *hal_tx_desc;
  1131. uint32_t *hal_tx_desc_cached;
  1132. int coalesce = 0;
  1133. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1134. uint8_t ring_id = tx_q->ring_id;
  1135. uint8_t tid;
  1136. struct dp_vdev_be *be_vdev;
  1137. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1138. uint8_t bm_id = dp_tx_get_rbm_id_be(soc, ring_id);
  1139. hal_ring_handle_t hal_ring_hdl = NULL;
  1140. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1141. uint8_t num_desc_bytes = HAL_TX_DESC_LEN_BYTES;
  1142. uint16_t ast_idx = vdev->bss_ast_idx;
  1143. uint16_t ast_hash = vdev->bss_ast_hash;
  1144. be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1145. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1146. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1147. return QDF_STATUS_E_RESOURCES;
  1148. }
  1149. if (qdf_unlikely(tx_exc_metadata)) {
  1150. qdf_assert_always((tx_exc_metadata->tx_encap_type ==
  1151. CDP_INVALID_TX_ENCAP_TYPE) ||
  1152. (tx_exc_metadata->tx_encap_type ==
  1153. vdev->tx_encap_type));
  1154. if (tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)
  1155. qdf_assert_always((tx_exc_metadata->sec_type ==
  1156. CDP_INVALID_SEC_TYPE) ||
  1157. tx_exc_metadata->sec_type ==
  1158. vdev->sec_type);
  1159. dp_get_peer_from_tx_exc_meta(soc, (void *)cached_desc,
  1160. tx_exc_metadata,
  1161. &ast_idx, &ast_hash);
  1162. }
  1163. hal_tx_desc_cached = (void *)cached_desc;
  1164. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  1165. dp_sawf_config_be(soc, hal_tx_desc_cached,
  1166. &fw_metadata, tx_desc->nbuf, msdu_info);
  1167. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  1168. }
  1169. hal_tx_desc_set_buf_addr_be(soc->hal_soc, hal_tx_desc_cached,
  1170. tx_desc->dma_addr, bm_id, tx_desc->id,
  1171. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1172. hal_tx_desc_set_lmac_id_be(soc->hal_soc, hal_tx_desc_cached,
  1173. vdev->lmac_id);
  1174. hal_tx_desc_set_search_index_be(soc->hal_soc, hal_tx_desc_cached,
  1175. ast_idx);
  1176. /*
  1177. * Bank_ID is used as DSCP_TABLE number in beryllium
  1178. * So there is no explicit field used for DSCP_TID_TABLE_NUM.
  1179. */
  1180. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1181. (ast_hash & 0xF));
  1182. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1183. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1184. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1185. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1186. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1187. /* verify checksum offload configuration*/
  1188. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  1189. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  1190. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  1191. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1192. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1193. }
  1194. hal_tx_desc_set_bank_id(hal_tx_desc_cached, vdev->bank_id);
  1195. dp_tx_vdev_id_set_hal_tx_desc(hal_tx_desc_cached, vdev, msdu_info);
  1196. tid = msdu_info->tid;
  1197. if (tid != HTT_TX_EXT_TID_INVALID)
  1198. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1199. dp_tx_set_min_rates_for_critical_frames(soc, hal_tx_desc_cached,
  1200. tx_desc->nbuf);
  1201. dp_tx_set_particular_tx_queue(soc, hal_tx_desc_cached,
  1202. tx_desc->nbuf);
  1203. dp_tx_desc_set_ktimestamp(vdev, tx_desc);
  1204. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1205. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1206. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1207. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1208. DP_STATS_INC(vdev,
  1209. tx_i[msdu_info->xmit_type].dropped.enqueue_fail,
  1210. 1);
  1211. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1212. return status;
  1213. }
  1214. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1215. if (qdf_unlikely(!hal_tx_desc)) {
  1216. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1217. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1218. DP_STATS_INC(vdev,
  1219. tx_i[msdu_info->xmit_type].dropped.enqueue_fail,
  1220. 1);
  1221. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1222. goto ring_access_fail;
  1223. }
  1224. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1225. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1226. /* Sync cached descriptor with HW */
  1227. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc, num_desc_bytes);
  1228. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  1229. msdu_info, ring_id);
  1230. DP_STATS_INC_PKT(vdev, tx_i[msdu_info->xmit_type].processed, 1,
  1231. dp_tx_get_pkt_len(tx_desc));
  1232. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  1233. dp_tx_update_stats(soc, tx_desc, ring_id);
  1234. status = QDF_STATUS_SUCCESS;
  1235. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  1236. hal_ring_hdl, soc, ring_id);
  1237. ring_access_fail:
  1238. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1239. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  1240. qdf_get_log_timestamp(), tx_desc->nbuf);
  1241. return status;
  1242. }
  1243. #ifdef IPA_OFFLOAD
  1244. static void
  1245. dp_tx_get_ipa_bank_config(struct dp_soc_be *be_soc,
  1246. union hal_tx_bank_config *bank_config)
  1247. {
  1248. bank_config->epd = 0;
  1249. bank_config->encap_type = wlan_cfg_pkt_type(be_soc->soc.wlan_cfg_ctx);
  1250. bank_config->encrypt_type = 0;
  1251. bank_config->src_buffer_swap = 0;
  1252. bank_config->link_meta_swap = 0;
  1253. bank_config->index_lookup_enable = 0;
  1254. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1255. bank_config->addrx_en = 1;
  1256. bank_config->addry_en = 1;
  1257. bank_config->mesh_enable = 0;
  1258. bank_config->dscp_tid_map_id = 0;
  1259. bank_config->vdev_id_check_en = 0;
  1260. bank_config->pmac_id = 0;
  1261. }
  1262. static void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1263. {
  1264. union hal_tx_bank_config ipa_config = {0};
  1265. int bid;
  1266. if (!wlan_cfg_is_ipa_enabled(be_soc->soc.wlan_cfg_ctx)) {
  1267. be_soc->ipa_bank_id = DP_BE_INVALID_BANK_ID;
  1268. return;
  1269. }
  1270. dp_tx_get_ipa_bank_config(be_soc, &ipa_config);
  1271. /* Let IPA use last HOST owned bank */
  1272. bid = be_soc->num_bank_profiles - 1;
  1273. be_soc->bank_profiles[bid].is_configured = true;
  1274. be_soc->bank_profiles[bid].bank_config.val = ipa_config.val;
  1275. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1276. &be_soc->bank_profiles[bid].bank_config,
  1277. bid);
  1278. qdf_atomic_inc(&be_soc->bank_profiles[bid].ref_count);
  1279. dp_info("IPA bank at slot %d config:0x%x", bid,
  1280. be_soc->bank_profiles[bid].bank_config.val);
  1281. be_soc->ipa_bank_id = bid;
  1282. }
  1283. #else /* !IPA_OFFLOAD */
  1284. static inline void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1285. {
  1286. }
  1287. #endif /* IPA_OFFLOAD */
  1288. QDF_STATUS dp_tx_init_bank_profiles(struct dp_soc_be *be_soc)
  1289. {
  1290. int i, num_tcl_banks;
  1291. num_tcl_banks = hal_tx_get_num_tcl_banks(be_soc->soc.hal_soc);
  1292. dp_assert_always_internal(num_tcl_banks);
  1293. be_soc->num_bank_profiles = num_tcl_banks;
  1294. be_soc->bank_profiles = qdf_mem_malloc(num_tcl_banks *
  1295. sizeof(*be_soc->bank_profiles));
  1296. if (!be_soc->bank_profiles) {
  1297. dp_err("unable to allocate memory for DP TX Profiles!");
  1298. return QDF_STATUS_E_NOMEM;
  1299. }
  1300. DP_TX_BANK_LOCK_CREATE(&be_soc->tx_bank_lock);
  1301. for (i = 0; i < num_tcl_banks; i++) {
  1302. be_soc->bank_profiles[i].is_configured = false;
  1303. qdf_atomic_init(&be_soc->bank_profiles[i].ref_count);
  1304. }
  1305. dp_info("initialized %u bank profiles", be_soc->num_bank_profiles);
  1306. dp_tx_init_ipa_bank_profile(be_soc);
  1307. return QDF_STATUS_SUCCESS;
  1308. }
  1309. void dp_tx_deinit_bank_profiles(struct dp_soc_be *be_soc)
  1310. {
  1311. qdf_mem_free(be_soc->bank_profiles);
  1312. DP_TX_BANK_LOCK_DESTROY(&be_soc->tx_bank_lock);
  1313. }
  1314. static
  1315. void dp_tx_get_vdev_bank_config(struct dp_vdev_be *be_vdev,
  1316. union hal_tx_bank_config *bank_config)
  1317. {
  1318. struct dp_vdev *vdev = &be_vdev->vdev;
  1319. bank_config->epd = 0;
  1320. bank_config->encap_type = vdev->tx_encap_type;
  1321. /* Only valid for raw frames. Needs work for RAW mode */
  1322. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) {
  1323. bank_config->encrypt_type = sec_type_map[vdev->sec_type];
  1324. } else {
  1325. bank_config->encrypt_type = 0;
  1326. }
  1327. bank_config->src_buffer_swap = 0;
  1328. bank_config->link_meta_swap = 0;
  1329. if ((vdev->search_type == HAL_TX_ADDR_INDEX_SEARCH) &&
  1330. vdev->opmode == wlan_op_mode_sta) {
  1331. bank_config->index_lookup_enable = 1;
  1332. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_MEC_NOTIFY;
  1333. bank_config->addrx_en = 0;
  1334. bank_config->addry_en = 0;
  1335. } else {
  1336. bank_config->index_lookup_enable = 0;
  1337. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1338. bank_config->addrx_en =
  1339. (vdev->hal_desc_addr_search_flags &
  1340. HAL_TX_DESC_ADDRX_EN) ? 1 : 0;
  1341. bank_config->addry_en =
  1342. (vdev->hal_desc_addr_search_flags &
  1343. HAL_TX_DESC_ADDRY_EN) ? 1 : 0;
  1344. }
  1345. bank_config->mesh_enable = vdev->mesh_vdev ? 1 : 0;
  1346. bank_config->dscp_tid_map_id = vdev->dscp_tid_map_id;
  1347. /* Disabling vdev id check for now. Needs revist. */
  1348. bank_config->vdev_id_check_en = be_vdev->vdev_id_check_en;
  1349. bank_config->pmac_id = vdev->lmac_id;
  1350. }
  1351. int dp_tx_get_bank_profile(struct dp_soc_be *be_soc,
  1352. struct dp_vdev_be *be_vdev)
  1353. {
  1354. char *temp_str = "";
  1355. bool found_match = false;
  1356. int bank_id = DP_BE_INVALID_BANK_ID;
  1357. int i;
  1358. int unconfigured_slot = DP_BE_INVALID_BANK_ID;
  1359. int zero_ref_count_slot = DP_BE_INVALID_BANK_ID;
  1360. union hal_tx_bank_config vdev_config = {0};
  1361. /* convert vdev params into hal_tx_bank_config */
  1362. dp_tx_get_vdev_bank_config(be_vdev, &vdev_config);
  1363. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1364. /* go over all banks and find a matching/unconfigured/unused bank */
  1365. for (i = 0; i < be_soc->num_bank_profiles; i++) {
  1366. if (be_soc->bank_profiles[i].is_configured &&
  1367. (be_soc->bank_profiles[i].bank_config.val ^
  1368. vdev_config.val) == 0) {
  1369. found_match = true;
  1370. break;
  1371. }
  1372. if (unconfigured_slot == DP_BE_INVALID_BANK_ID &&
  1373. !be_soc->bank_profiles[i].is_configured)
  1374. unconfigured_slot = i;
  1375. else if (zero_ref_count_slot == DP_BE_INVALID_BANK_ID &&
  1376. !qdf_atomic_read(&be_soc->bank_profiles[i].ref_count))
  1377. zero_ref_count_slot = i;
  1378. }
  1379. if (found_match) {
  1380. temp_str = "matching";
  1381. bank_id = i;
  1382. goto inc_ref_and_return;
  1383. }
  1384. if (unconfigured_slot != DP_BE_INVALID_BANK_ID) {
  1385. temp_str = "unconfigured";
  1386. bank_id = unconfigured_slot;
  1387. goto configure_and_return;
  1388. }
  1389. if (zero_ref_count_slot != DP_BE_INVALID_BANK_ID) {
  1390. temp_str = "zero_ref_count";
  1391. bank_id = zero_ref_count_slot;
  1392. }
  1393. if (bank_id == DP_BE_INVALID_BANK_ID) {
  1394. dp_alert("unable to find TX bank!");
  1395. QDF_BUG(0);
  1396. return bank_id;
  1397. }
  1398. configure_and_return:
  1399. be_soc->bank_profiles[bank_id].is_configured = true;
  1400. be_soc->bank_profiles[bank_id].bank_config.val = vdev_config.val;
  1401. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1402. &be_soc->bank_profiles[bank_id].bank_config,
  1403. bank_id);
  1404. inc_ref_and_return:
  1405. qdf_atomic_inc(&be_soc->bank_profiles[bank_id].ref_count);
  1406. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1407. dp_info("found %s slot at index %d, input:0x%x match:0x%x ref_count %u",
  1408. temp_str, bank_id, vdev_config.val,
  1409. be_soc->bank_profiles[bank_id].bank_config.val,
  1410. qdf_atomic_read(&be_soc->bank_profiles[bank_id].ref_count));
  1411. dp_info("epd:%x encap:%x encryp:%x src_buf_swap:%x link_meta_swap:%x addrx_en:%x addry_en:%x mesh_en:%x vdev_id_check:%x pmac_id:%x mcast_pkt_ctrl:%x",
  1412. be_soc->bank_profiles[bank_id].bank_config.epd,
  1413. be_soc->bank_profiles[bank_id].bank_config.encap_type,
  1414. be_soc->bank_profiles[bank_id].bank_config.encrypt_type,
  1415. be_soc->bank_profiles[bank_id].bank_config.src_buffer_swap,
  1416. be_soc->bank_profiles[bank_id].bank_config.link_meta_swap,
  1417. be_soc->bank_profiles[bank_id].bank_config.addrx_en,
  1418. be_soc->bank_profiles[bank_id].bank_config.addry_en,
  1419. be_soc->bank_profiles[bank_id].bank_config.mesh_enable,
  1420. be_soc->bank_profiles[bank_id].bank_config.vdev_id_check_en,
  1421. be_soc->bank_profiles[bank_id].bank_config.pmac_id,
  1422. be_soc->bank_profiles[bank_id].bank_config.mcast_pkt_ctrl);
  1423. return bank_id;
  1424. }
  1425. void dp_tx_put_bank_profile(struct dp_soc_be *be_soc,
  1426. struct dp_vdev_be *be_vdev)
  1427. {
  1428. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1429. qdf_atomic_dec(&be_soc->bank_profiles[be_vdev->bank_id].ref_count);
  1430. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1431. }
  1432. void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
  1433. struct dp_vdev_be *be_vdev)
  1434. {
  1435. dp_tx_put_bank_profile(be_soc, be_vdev);
  1436. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  1437. be_vdev->vdev.bank_id = be_vdev->bank_id;
  1438. }
  1439. QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
  1440. uint32_t num_elem,
  1441. uint8_t pool_id,
  1442. bool spcl_tx_desc)
  1443. {
  1444. struct dp_tx_desc_pool_s *tx_desc_pool;
  1445. struct dp_hw_cookie_conversion_t *cc_ctx;
  1446. struct dp_spt_page_desc *page_desc;
  1447. struct dp_tx_desc_s *tx_desc;
  1448. uint32_t ppt_idx = 0;
  1449. uint32_t avail_entry_index = 0;
  1450. if (!num_elem) {
  1451. dp_err("desc_num 0 !!");
  1452. return QDF_STATUS_E_FAILURE;
  1453. }
  1454. if (spcl_tx_desc) {
  1455. tx_desc_pool = dp_get_spcl_tx_desc_pool(soc, pool_id);
  1456. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1457. } else {
  1458. tx_desc_pool = dp_get_tx_desc_pool(soc, pool_id);;
  1459. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1460. }
  1461. tx_desc = tx_desc_pool->freelist;
  1462. page_desc = &cc_ctx->page_desc_base[0];
  1463. while (tx_desc) {
  1464. if (avail_entry_index == 0) {
  1465. if (ppt_idx >= cc_ctx->total_page_num) {
  1466. dp_alert("insufficient secondary page tables");
  1467. qdf_assert_always(0);
  1468. }
  1469. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  1470. }
  1471. /* put each TX Desc VA to SPT pages and
  1472. * get corresponding ID
  1473. */
  1474. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  1475. avail_entry_index,
  1476. tx_desc);
  1477. tx_desc->id =
  1478. dp_cc_desc_id_generate(page_desc->ppt_index,
  1479. avail_entry_index);
  1480. tx_desc->pool_id = pool_id;
  1481. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  1482. tx_desc = tx_desc->next;
  1483. avail_entry_index = (avail_entry_index + 1) &
  1484. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  1485. }
  1486. return QDF_STATUS_SUCCESS;
  1487. }
  1488. void dp_tx_desc_pool_deinit_be(struct dp_soc *soc,
  1489. struct dp_tx_desc_pool_s *tx_desc_pool,
  1490. uint8_t pool_id, bool spcl_tx_desc)
  1491. {
  1492. struct dp_spt_page_desc *page_desc;
  1493. int i = 0;
  1494. struct dp_hw_cookie_conversion_t *cc_ctx;
  1495. if (spcl_tx_desc)
  1496. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1497. else
  1498. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1499. for (i = 0; i < cc_ctx->total_page_num; i++) {
  1500. page_desc = &cc_ctx->page_desc_base[i];
  1501. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  1502. }
  1503. }
  1504. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1505. uint32_t dp_tx_comp_nf_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  1506. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  1507. uint32_t quota)
  1508. {
  1509. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  1510. uint32_t work_done = 0;
  1511. if (dp_srng_get_near_full_level(soc, tx_comp_ring) <
  1512. DP_SRNG_THRESH_NEAR_FULL)
  1513. return 0;
  1514. qdf_atomic_set(&tx_comp_ring->near_full, 1);
  1515. work_done++;
  1516. return work_done;
  1517. }
  1518. #endif
  1519. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1520. defined(WLAN_CONFIG_TX_DELAY)
  1521. #define PPDUID_GET_HW_LINK_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  1522. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  1523. #define HW_TX_DELAY_MAX 0x1000000
  1524. #define TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US 10
  1525. #define HW_TX_DELAY_MASK 0x1FFFFFFF
  1526. #define TX_COMPL_BUFFER_TSTAMP_US(TSTAMP) \
  1527. (((TSTAMP) << TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US) & \
  1528. HW_TX_DELAY_MASK)
  1529. static inline
  1530. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1531. struct dp_vdev *vdev,
  1532. struct hal_tx_completion_status *ts,
  1533. uint32_t *delay_us)
  1534. {
  1535. uint32_t ppdu_id;
  1536. uint8_t link_id_offset, link_id_bits;
  1537. uint8_t hw_link_id;
  1538. uint32_t msdu_tqm_enqueue_tstamp_us, final_msdu_tqm_enqueue_tstamp_us;
  1539. uint32_t msdu_compl_tsf_tstamp_us, final_msdu_compl_tsf_tstamp_us;
  1540. uint32_t delay;
  1541. int32_t delta_tsf2, delta_tqm;
  1542. if (!ts->valid)
  1543. return QDF_STATUS_E_INVAL;
  1544. link_id_offset = soc->link_id_offset;
  1545. link_id_bits = soc->link_id_bits;
  1546. ppdu_id = ts->ppdu_id;
  1547. hw_link_id = PPDUID_GET_HW_LINK_ID(ppdu_id, link_id_offset,
  1548. link_id_bits);
  1549. msdu_tqm_enqueue_tstamp_us =
  1550. TX_COMPL_BUFFER_TSTAMP_US(ts->buffer_timestamp);
  1551. msdu_compl_tsf_tstamp_us = ts->tsf;
  1552. delta_tsf2 = dp_mlo_get_delta_tsf2_wrt_mlo_offset(soc, hw_link_id);
  1553. delta_tqm = dp_mlo_get_delta_tqm_wrt_mlo_offset(soc);
  1554. final_msdu_tqm_enqueue_tstamp_us = (msdu_tqm_enqueue_tstamp_us +
  1555. delta_tqm) & HW_TX_DELAY_MASK;
  1556. final_msdu_compl_tsf_tstamp_us = (msdu_compl_tsf_tstamp_us +
  1557. delta_tsf2) & HW_TX_DELAY_MASK;
  1558. delay = (final_msdu_compl_tsf_tstamp_us -
  1559. final_msdu_tqm_enqueue_tstamp_us) & HW_TX_DELAY_MASK;
  1560. if (delay > HW_TX_DELAY_MAX)
  1561. return QDF_STATUS_E_FAILURE;
  1562. if (delay_us)
  1563. *delay_us = delay;
  1564. return QDF_STATUS_SUCCESS;
  1565. }
  1566. #else
  1567. static inline
  1568. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1569. struct dp_vdev *vdev,
  1570. struct hal_tx_completion_status *ts,
  1571. uint32_t *delay_us)
  1572. {
  1573. return QDF_STATUS_SUCCESS;
  1574. }
  1575. #endif
  1576. QDF_STATUS dp_tx_compute_tx_delay_be(struct dp_soc *soc,
  1577. struct dp_vdev *vdev,
  1578. struct hal_tx_completion_status *ts,
  1579. uint32_t *delay_us)
  1580. {
  1581. return dp_mlo_compute_hw_delay_us(soc, vdev, ts, delay_us);
  1582. }
  1583. static inline
  1584. qdf_dma_addr_t dp_tx_nbuf_map_be(struct dp_vdev *vdev,
  1585. struct dp_tx_desc_s *tx_desc,
  1586. qdf_nbuf_t nbuf)
  1587. {
  1588. qdf_nbuf_dma_clean_range_no_dsb((void *)nbuf->data,
  1589. (void *)(nbuf->data + 256));
  1590. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1591. }
  1592. static inline
  1593. void dp_tx_nbuf_unmap_be(struct dp_soc *soc,
  1594. struct dp_tx_desc_s *desc)
  1595. {
  1596. }
  1597. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  1598. qdf_nbuf_t dp_tx_fast_send_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1599. qdf_nbuf_t nbuf)
  1600. {
  1601. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1602. struct dp_vdev *vdev = NULL;
  1603. struct dp_pdev *pdev = NULL;
  1604. struct dp_tx_desc_s *tx_desc;
  1605. uint16_t desc_pool_id;
  1606. uint16_t pkt_len;
  1607. qdf_dma_addr_t paddr;
  1608. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1609. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1610. hal_ring_handle_t hal_ring_hdl = NULL;
  1611. uint32_t *hal_tx_desc_cached;
  1612. void *hal_tx_desc;
  1613. uint8_t tid = HTT_TX_EXT_TID_INVALID;
  1614. uint8_t xmit_type = qdf_nbuf_get_vdev_xmit_type(nbuf);
  1615. uint8_t sawf_tid = HTT_TX_EXT_TID_INVALID;
  1616. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  1617. return nbuf;
  1618. vdev = soc->vdev_id_map[vdev_id];
  1619. if (qdf_unlikely(!vdev))
  1620. return nbuf;
  1621. desc_pool_id = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  1622. pkt_len = qdf_nbuf_headlen(nbuf);
  1623. DP_STATS_INC_PKT(vdev, tx_i[xmit_type].rcvd, 1, pkt_len);
  1624. DP_STATS_INC(vdev, tx_i[xmit_type].rcvd_in_fast_xmit_flow, 1);
  1625. DP_STATS_INC(vdev, tx_i[xmit_type].rcvd_per_core[desc_pool_id], 1);
  1626. pdev = vdev->pdev;
  1627. if (dp_tx_limit_check(vdev, nbuf))
  1628. return nbuf;
  1629. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1630. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1631. tid = qdf_nbuf_get_priority(nbuf);
  1632. if (tid >= DP_TX_INVALID_QOS_TAG)
  1633. tid = HTT_TX_EXT_TID_INVALID;
  1634. }
  1635. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1636. if (qdf_unlikely(!tx_desc)) {
  1637. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.desc_na.num, 1);
  1638. DP_STATS_INC(vdev,
  1639. tx_i[xmit_type].dropped.desc_na_exc_alloc_fail.num,
  1640. 1);
  1641. return nbuf;
  1642. }
  1643. dp_tx_outstanding_inc(pdev);
  1644. /* Initialize the SW tx descriptor */
  1645. tx_desc->nbuf = nbuf;
  1646. tx_desc->frm_type = dp_tx_frm_std;
  1647. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1648. tx_desc->vdev_id = vdev_id;
  1649. tx_desc->pdev = pdev;
  1650. tx_desc->pkt_offset = 0;
  1651. tx_desc->length = pkt_len;
  1652. tx_desc->flags |= pdev->tx_fast_flag;
  1653. tx_desc->nbuf->fast_recycled = 1;
  1654. if (nbuf->is_from_recycler && nbuf->fast_xmit)
  1655. tx_desc->flags |= DP_TX_DESC_FLAG_FAST;
  1656. paddr = dp_tx_nbuf_map_be(vdev, tx_desc, nbuf);
  1657. if (!paddr) {
  1658. /* Handle failure */
  1659. dp_err("qdf_nbuf_map failed");
  1660. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.dma_error, 1);
  1661. goto release_desc;
  1662. }
  1663. tx_desc->dma_addr = paddr;
  1664. hal_tx_desc_cached = (void *)cached_desc;
  1665. hal_tx_desc_cached[0] = (uint32_t)tx_desc->dma_addr;
  1666. hal_tx_desc_cached[1] = tx_desc->id <<
  1667. TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  1668. /* bank_id */
  1669. hal_tx_desc_cached[2] = vdev->bank_id << TCL_DATA_CMD_BANK_ID_LSB;
  1670. hal_tx_desc_cached[3] = vdev->htt_tcl_metadata <<
  1671. TCL_DATA_CMD_TCL_CMD_NUMBER_LSB;
  1672. hal_tx_desc_cached[4] = tx_desc->length;
  1673. /* l3 and l4 checksum enable */
  1674. hal_tx_desc_cached[4] |= DP_TX_L3_L4_CSUM_ENABLE <<
  1675. TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB;
  1676. hal_tx_desc_cached[5] = vdev->lmac_id << TCL_DATA_CMD_PMAC_ID_LSB;
  1677. hal_tx_desc_cached[5] |= vdev->vdev_id << TCL_DATA_CMD_VDEV_ID_LSB;
  1678. if (qdf_unlikely(dp_sawf_tag_valid_get(nbuf))) {
  1679. sawf_tid = dp_sawf_config_be(soc, hal_tx_desc_cached,
  1680. NULL, nbuf, NULL);
  1681. if (sawf_tid != HTT_TX_EXT_TID_INVALID)
  1682. tid = sawf_tid;
  1683. }
  1684. if (tid != HTT_TX_EXT_TID_INVALID) {
  1685. hal_tx_desc_cached[5] |= tid << TCL_DATA_CMD_HLOS_TID_LSB;
  1686. hal_tx_desc_cached[5] |= 1 << TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB;
  1687. }
  1688. if (vdev->opmode == wlan_op_mode_sta)
  1689. hal_tx_desc_cached[6] = vdev->bss_ast_idx |
  1690. ((vdev->bss_ast_hash & 0xF) <<
  1691. TCL_DATA_CMD_CACHE_SET_NUM_LSB);
  1692. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, desc_pool_id);
  1693. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1694. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1695. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1696. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.enqueue_fail, 1);
  1697. goto ring_access_fail2;
  1698. }
  1699. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1700. if (qdf_unlikely(!hal_tx_desc)) {
  1701. dp_verbose_debug("TCL ring full ring_id:%d", desc_pool_id);
  1702. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1703. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.enqueue_fail, 1);
  1704. goto ring_access_fail;
  1705. }
  1706. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1707. /* Sync cached descriptor with HW */
  1708. qdf_mem_copy(hal_tx_desc, hal_tx_desc_cached, DP_TX_FAST_DESC_SIZE);
  1709. qdf_dsb();
  1710. DP_STATS_INC_PKT(vdev, tx_i[xmit_type].processed, 1, tx_desc->length);
  1711. DP_STATS_INC(soc, tx.tcl_enq[desc_pool_id], 1);
  1712. status = QDF_STATUS_SUCCESS;
  1713. ring_access_fail:
  1714. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1715. ring_access_fail2:
  1716. if (status != QDF_STATUS_SUCCESS) {
  1717. dp_tx_nbuf_unmap_be(soc, tx_desc);
  1718. goto release_desc;
  1719. }
  1720. return NULL;
  1721. release_desc:
  1722. dp_tx_desc_release(soc, tx_desc, desc_pool_id);
  1723. return nbuf;
  1724. }
  1725. #endif
  1726. QDF_STATUS dp_tx_desc_pool_alloc_be(struct dp_soc *soc, uint32_t num_elem,
  1727. uint8_t pool_id)
  1728. {
  1729. return QDF_STATUS_SUCCESS;
  1730. }
  1731. void dp_tx_desc_pool_free_be(struct dp_soc *soc, uint8_t pool_id)
  1732. {
  1733. }