wcd938x.c 76 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. enum {
  29. WCD9380 = 0,
  30. WCD9385,
  31. WCD9385FX,
  32. };
  33. enum {
  34. CODEC_TX = 0,
  35. CODEC_RX,
  36. };
  37. enum {
  38. ALLOW_BUCK_DISABLE,
  39. HPH_COMP_DELAY,
  40. HPH_PA_DELAY,
  41. };
  42. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  43. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  44. static int wcd938x_handle_post_irq(void *data);
  45. static int wcd938x_reset(struct device *dev);
  46. static int wcd938x_reset_low(struct device *dev);
  47. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  48. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  49. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  50. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  51. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  52. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  53. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  54. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  55. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  56. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  57. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  58. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  59. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  60. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  61. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  62. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  63. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  64. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  65. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  66. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  68. };
  69. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  70. .name = "wcd938x",
  71. .irqs = wcd938x_irqs,
  72. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  73. .num_regs = 3,
  74. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  75. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  76. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  77. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  78. .use_ack = 1,
  79. .clear_ack = 1,
  80. .runtime_pm = true,
  81. .handle_post_irq = wcd938x_handle_post_irq,
  82. .irq_drv_data = NULL,
  83. };
  84. static int wcd938x_handle_post_irq(void *data)
  85. {
  86. struct wcd938x_priv *wcd938x = data;
  87. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  88. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  89. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  90. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  91. wcd938x->tx_swr_dev->slave_irq_pending =
  92. ((sts1 || sts2 || sts3) ? true : false);
  93. return IRQ_HANDLED;
  94. }
  95. static int wcd938x_init_reg(struct snd_soc_component *component)
  96. {
  97. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  98. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  99. /* 1 msec delay as per HW requirement */
  100. usleep_range(1000, 1010);
  101. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  102. /* 1 msec delay as per HW requirement */
  103. usleep_range(1000, 1010);
  104. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  105. 0x10, 0x00);
  106. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  107. 0xF0, 0x80);
  108. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  109. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  110. /* 10 msec delay as per HW requirement */
  111. usleep_range(10000, 10010);
  112. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  113. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  114. 0xFF, 0x3A);
  115. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  116. 0x0F, 0x02);
  117. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  118. 0x01, 0x01);
  119. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  120. 0x01, 0x01);
  121. return 0;
  122. }
  123. static int wcd938x_set_port_params(struct snd_soc_component *component,
  124. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  125. u8 *ch_mask, u32 *ch_rate,
  126. u8 *port_type, u8 path)
  127. {
  128. int i, j;
  129. u8 num_ports;
  130. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  131. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  132. switch (path) {
  133. case CODEC_RX:
  134. map = &wcd938x->rx_port_mapping;
  135. num_ports = wcd938x->num_rx_ports;
  136. break;
  137. case CODEC_TX:
  138. map = &wcd938x->tx_port_mapping;
  139. num_ports = wcd938x->num_tx_ports;
  140. break;
  141. }
  142. for (i = 0; i <= num_ports; i++) {
  143. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  144. if ((*map)[i][j].port_type == slv_prt_type)
  145. goto found;
  146. }
  147. }
  148. found:
  149. if (i > num_ports || j == MAX_CH_PER_PORT) {
  150. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  151. __func__, slv_prt_type);
  152. return -EINVAL;
  153. }
  154. *port_id = i;
  155. *num_ch = (*map)[i][j].num_ch;
  156. *ch_mask = (*map)[i][j].ch_mask;
  157. *ch_rate = (*map)[i][j].ch_rate;
  158. *port_type = (*map)[i][j].master_port_type;
  159. return 0;
  160. }
  161. static int wcd938x_parse_port_mapping(struct device *dev,
  162. char *prop, u8 path)
  163. {
  164. u32 *dt_array, map_size, map_length;
  165. u32 port_num, ch_mask, ch_rate, old_port_num = 0;
  166. u32 slave_port_type, master_port_type;
  167. u32 i, ch_iter = 0;
  168. int ret = 0;
  169. u8 *num_ports;
  170. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  171. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  172. switch (path) {
  173. case CODEC_RX:
  174. map = &wcd938x->rx_port_mapping;
  175. num_ports = &wcd938x->num_rx_ports;
  176. break;
  177. case CODEC_TX:
  178. map = &wcd938x->tx_port_mapping;
  179. num_ports = &wcd938x->num_tx_ports;
  180. break;
  181. }
  182. if (!of_find_property(dev->of_node, prop,
  183. &map_size)) {
  184. dev_err(dev, "missing port mapping prop %s\n", prop);
  185. ret = -EINVAL;
  186. goto err_port_map;
  187. }
  188. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  189. dt_array = kzalloc(map_size, GFP_KERNEL);
  190. if (!dt_array) {
  191. ret = -ENOMEM;
  192. goto err_alloc;
  193. }
  194. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  195. NUM_SWRS_DT_PARAMS * map_length);
  196. if (ret) {
  197. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  198. __func__, prop);
  199. goto err_pdata_fail;
  200. }
  201. for (i = 0; i < map_length; i++) {
  202. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  203. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  204. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  205. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  206. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  207. if (port_num != old_port_num)
  208. ch_iter = 0;
  209. (*map)[port_num][ch_iter].port_type = slave_port_type;
  210. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  211. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  212. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  213. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  214. old_port_num = port_num;
  215. }
  216. *num_ports = port_num;
  217. kfree(dt_array);
  218. return 0;
  219. err_pdata_fail:
  220. kfree(dt_array);
  221. err_alloc:
  222. err_port_map:
  223. return ret;
  224. }
  225. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  226. u8 slv_port_type, u8 enable)
  227. {
  228. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  229. u8 port_id, num_ch, ch_mask, port_type;
  230. u32 ch_rate;
  231. u8 num_port = 1;
  232. int ret = 0;
  233. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  234. &num_ch, &ch_mask, &ch_rate,
  235. &port_type, CODEC_TX);
  236. if (ret)
  237. return ret;
  238. if (enable)
  239. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  240. num_port, &ch_mask, &ch_rate,
  241. &num_ch, &port_type);
  242. else
  243. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  244. num_port, &ch_mask, &port_type);
  245. return ret;
  246. }
  247. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  248. u8 slv_port_type, u8 enable)
  249. {
  250. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  251. u8 port_id, num_ch, ch_mask, port_type;
  252. u32 ch_rate;
  253. u8 num_port = 1;
  254. int ret = 0;
  255. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  256. &num_ch, &ch_mask, &ch_rate,
  257. &port_type, CODEC_RX);
  258. if (ret)
  259. return ret;
  260. if (enable)
  261. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  262. num_port, &ch_mask, &ch_rate,
  263. &num_ch, &port_type);
  264. else
  265. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  266. num_port, &ch_mask, &port_type);
  267. return ret;
  268. }
  269. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  270. {
  271. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  272. if (wcd938x->rx_clk_cnt == 0) {
  273. snd_soc_component_update_bits(component,
  274. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  275. snd_soc_component_update_bits(component,
  276. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  277. snd_soc_component_update_bits(component,
  278. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  279. snd_soc_component_update_bits(component,
  280. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  281. snd_soc_component_update_bits(component,
  282. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  283. snd_soc_component_update_bits(component,
  284. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  285. snd_soc_component_update_bits(component,
  286. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  287. }
  288. wcd938x->rx_clk_cnt++;
  289. return 0;
  290. }
  291. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  292. {
  293. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  294. wcd938x->rx_clk_cnt--;
  295. if (wcd938x->rx_clk_cnt == 0) {
  296. snd_soc_component_update_bits(component,
  297. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  298. snd_soc_component_update_bits(component,
  299. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  300. snd_soc_component_update_bits(component,
  301. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  302. snd_soc_component_update_bits(component,
  303. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  304. snd_soc_component_update_bits(component,
  305. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  306. }
  307. return 0;
  308. }
  309. /*
  310. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  311. * @component: handle to snd_soc_component *
  312. *
  313. * return wcd938x_mbhc handle or error code in case of failure
  314. */
  315. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  316. {
  317. struct wcd938x_priv *wcd938x;
  318. if (!component) {
  319. pr_err("%s: Invalid params, NULL component\n", __func__);
  320. return NULL;
  321. }
  322. wcd938x = snd_soc_component_get_drvdata(component);
  323. if (!wcd938x) {
  324. pr_err("%s: wcd938x is NULL\n", __func__);
  325. return NULL;
  326. }
  327. return wcd938x->mbhc;
  328. }
  329. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  330. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  331. struct snd_kcontrol *kcontrol,
  332. int event)
  333. {
  334. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  335. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  336. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  337. w->name, event);
  338. switch (event) {
  339. case SND_SOC_DAPM_PRE_PMU:
  340. wcd938x_rx_clk_enable(component);
  341. snd_soc_component_update_bits(component,
  342. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  343. snd_soc_component_update_bits(component,
  344. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  345. snd_soc_component_update_bits(component,
  346. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  347. break;
  348. case SND_SOC_DAPM_POST_PMU:
  349. snd_soc_component_update_bits(component,
  350. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  351. if (wcd938x->comp1_enable) {
  352. snd_soc_component_update_bits(component,
  353. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  354. /* 5msec compander delay as per HW requirement */
  355. if (!wcd938x->comp2_enable ||
  356. (snd_soc_component_read(component,
  357. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  358. usleep_range(5000, 5010);
  359. snd_soc_component_update_bits(component,
  360. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  361. } else {
  362. snd_soc_component_update_bits(component,
  363. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  364. 0x02, 0x00);
  365. snd_soc_component_update_bits(component,
  366. WCD938X_HPH_L_EN, 0x20, 0x20);
  367. }
  368. break;
  369. case SND_SOC_DAPM_POST_PMD:
  370. snd_soc_component_update_bits(component,
  371. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  372. 0x0F, 0x01);
  373. break;
  374. }
  375. return 0;
  376. }
  377. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  378. struct snd_kcontrol *kcontrol,
  379. int event)
  380. {
  381. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  382. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  383. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  384. w->name, event);
  385. switch (event) {
  386. case SND_SOC_DAPM_PRE_PMU:
  387. wcd938x_rx_clk_enable(component);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  390. snd_soc_component_update_bits(component,
  391. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  392. snd_soc_component_update_bits(component,
  393. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  394. break;
  395. case SND_SOC_DAPM_POST_PMU:
  396. snd_soc_component_update_bits(component,
  397. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  398. if (wcd938x->comp2_enable) {
  399. snd_soc_component_update_bits(component,
  400. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  401. /* 5msec compander delay as per HW requirement */
  402. if (!wcd938x->comp1_enable ||
  403. (snd_soc_component_read(component,
  404. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  405. usleep_range(5000, 5010);
  406. snd_soc_component_update_bits(component,
  407. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  408. } else {
  409. snd_soc_component_update_bits(component,
  410. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  411. 0x01, 0x00);
  412. snd_soc_component_update_bits(component,
  413. WCD938X_HPH_R_EN, 0x20, 0x20);
  414. }
  415. break;
  416. case SND_SOC_DAPM_POST_PMD:
  417. snd_soc_component_update_bits(component,
  418. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  419. 0x0F, 0x01);
  420. break;
  421. }
  422. return 0;
  423. }
  424. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  425. struct snd_kcontrol *kcontrol,
  426. int event)
  427. {
  428. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  429. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  430. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  431. w->name, event);
  432. switch (event) {
  433. case SND_SOC_DAPM_PRE_PMU:
  434. wcd938x_rx_clk_enable(component);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  441. /* 5 msec delay as per HW requirement */
  442. usleep_range(5000, 5010);
  443. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  444. WCD_CLSH_EVENT_PRE_DAC,
  445. WCD_CLSH_STATE_EAR,
  446. wcd938x->hph_mode);
  447. break;
  448. case SND_SOC_DAPM_POST_PMD:
  449. break;
  450. };
  451. return 0;
  452. }
  453. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  454. struct snd_kcontrol *kcontrol,
  455. int event)
  456. {
  457. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  458. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  459. int ret = 0;
  460. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  461. w->name, event);
  462. switch (event) {
  463. case SND_SOC_DAPM_PRE_PMU:
  464. wcd938x_rx_clk_enable(component);
  465. snd_soc_component_update_bits(component,
  466. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  467. snd_soc_component_update_bits(component,
  468. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  469. snd_soc_component_update_bits(component,
  470. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  471. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  472. WCD_CLSH_EVENT_PRE_DAC,
  473. WCD_CLSH_STATE_AUX,
  474. wcd938x->hph_mode);
  475. break;
  476. case SND_SOC_DAPM_POST_PMD:
  477. wcd938x_rx_clk_disable(component);
  478. snd_soc_component_update_bits(component,
  479. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  480. break;
  481. };
  482. return ret;
  483. }
  484. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  485. struct snd_kcontrol *kcontrol,
  486. int event)
  487. {
  488. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  489. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  490. int ret = 0;
  491. int hph_mode = wcd938x->hph_mode;
  492. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  493. w->name, event);
  494. switch (event) {
  495. case SND_SOC_DAPM_PRE_PMU:
  496. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  497. wcd938x->rx_swr_dev->dev_num,
  498. true);
  499. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  500. WCD_CLSH_EVENT_PRE_DAC,
  501. WCD_CLSH_STATE_HPHR,
  502. hph_mode);
  503. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  504. 0x10, 0x10);
  505. /* 100 usec delay as per HW requirement */
  506. usleep_range(100, 110);
  507. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  508. break;
  509. case SND_SOC_DAPM_POST_PMU:
  510. /*
  511. * 7ms sleep is required if compander is enabled as per
  512. * HW requirement. If compander is disabled, then
  513. * 20ms delay is required.
  514. */
  515. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  516. if (!wcd938x->comp2_enable)
  517. usleep_range(20000, 20100);
  518. else
  519. usleep_range(7000, 7100);
  520. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  521. }
  522. snd_soc_component_update_bits(component,
  523. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  524. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  525. snd_soc_component_update_bits(component,
  526. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  527. if (wcd938x->update_wcd_event)
  528. wcd938x->update_wcd_event(wcd938x->handle,
  529. WCD_BOLERO_EVT_RX_MUTE,
  530. (WCD_RX2 << 0x10));
  531. break;
  532. case SND_SOC_DAPM_PRE_PMD:
  533. if (wcd938x->update_wcd_event)
  534. wcd938x->update_wcd_event(wcd938x->handle,
  535. WCD_BOLERO_EVT_RX_MUTE,
  536. (WCD_RX2 << 0x10 | 0x1));
  537. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  538. WCD_EVENT_PRE_HPHR_PA_OFF,
  539. &wcd938x->mbhc->wcd_mbhc);
  540. break;
  541. case SND_SOC_DAPM_POST_PMD:
  542. /* 7 msec delay as per HW requirement */
  543. usleep_range(7000, 7010);
  544. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  545. WCD_EVENT_POST_HPHR_PA_OFF,
  546. &wcd938x->mbhc->wcd_mbhc);
  547. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  548. 0x10, 0x00);
  549. wcd_cls_h_fsm(component, &wcd93x->clsh_info,
  550. WCD_CLSH_EVENT_POST_PA,
  551. WCD_CLSH_STATE_HPHR,
  552. hph_mode);
  553. break;
  554. };
  555. return ret;
  556. }
  557. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  558. struct snd_kcontrol *kcontrol,
  559. int event)
  560. {
  561. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  562. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  563. int ret = 0;
  564. int hph_mode = wcd938x->hph_mode;
  565. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  566. w->name, event);
  567. switch (event) {
  568. case SND_SOC_DAPM_PRE_PMU:
  569. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  570. wcd938x->rx_swr_dev->dev_num,
  571. true);
  572. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  573. WCD_CLSH_EVENT_PRE_DAC,
  574. WCD_CLSH_STATE_HPHL,
  575. hph_mode);
  576. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  577. 0x20, 0x20);
  578. /* 100 usec delay as per HW requirement */
  579. usleep_range(100, 110);
  580. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  581. break;
  582. case SND_SOC_DAPM_POST_PMU:
  583. /*
  584. * 7ms sleep is required if compander is enabled as per
  585. * HW requirement. If compander is disabled, then
  586. * 20ms delay is required.
  587. */
  588. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  589. if (!wcd938x->comp1_enable)
  590. usleep_range(20000, 20100);
  591. else
  592. usleep_range(7000, 7100);
  593. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  594. }
  595. snd_soc_component_update_bits(component,
  596. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  597. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  598. snd_soc_component_update_bits(component,
  599. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  600. if (wcd938x->update_wcd_event)
  601. wcd938x->update_wcd_event(wcd938x->handle,
  602. WCD_BOLERO_EVT_RX_MUTE,
  603. (WCD_RX1 << 0x10));
  604. break;
  605. case SND_SOC_DAPM_PRE_PMD:
  606. if (wcd938x->update_wcd_event)
  607. wcd938x->update_wcd_event(wcd938x->handle,
  608. WCD_BOLERO_EVT_RX_MUTE,
  609. (WCD_RX1 << 0x10 | 0x1));
  610. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  611. WCD_EVENT_PRE_HPHL_PA_OFF,
  612. &wcd938x->mbhc->wcd_mbhc);
  613. break;
  614. case SND_SOC_DAPM_POST_PMD:
  615. /* 7 msec delay as per HW requirement */
  616. usleep_range(7000, 7010);
  617. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  618. WCD_EVENT_POST_HPHL_PA_OFF,
  619. &wcd938x->mbhc->wcd_mbhc);
  620. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  621. 0x20, 0x00);
  622. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  623. WCD_CLSH_EVENT_POST_PA,
  624. WCD_CLSH_STATE_HPHL,
  625. hph_mode);
  626. break;
  627. };
  628. return ret;
  629. }
  630. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  631. struct snd_kcontrol *kcontrol,
  632. int event)
  633. {
  634. struct snd_soc_component *component =
  635. snd_soc_dapm_to_component(w->dapm);
  636. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  637. int hph_mode = wcd938x->hph_mode;
  638. int ret = 0;
  639. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  640. w->name, event);
  641. switch (event) {
  642. case SND_SOC_DAPM_PRE_PMU:
  643. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  644. wcd938x->rx_swr_dev->dev_num,
  645. true);
  646. break;
  647. case SND_SOC_DAPM_POST_PMU:
  648. /* 1 msec delay as per HW requirement */
  649. usleep_range(1000, 1010);
  650. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  651. snd_soc_component_update_bits(component,
  652. WCD938X_ANA_RX_SUPPLIES,
  653. 0x20, 0x20);
  654. if (wcd938x->update_wcd_event)
  655. wcd938x->update_wcd_event(wcd938x->handle,
  656. WCD_BOLERO_EVT_RX_MUTE,
  657. (WCD_RX3 << 0x10));
  658. break;
  659. case SND_SOC_DAPM_PRE_PMD:
  660. if (wcd938x->update_wcd_event)
  661. wcd938x->update_wcd_event(wcd938x->handle,
  662. WCD_BOLERO_EVT_RX_MUTE,
  663. (WCD_RX3 << 0x10 | 0x1));
  664. break;
  665. case SND_SOC_DAPM_POST_PMD:
  666. /* 1 msec delay as per HW requirement */
  667. usleep_range(1000, 1010);
  668. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  669. WCD_CLSH_EVENT_POST_PA,
  670. WCD_CLSH_STATE_AUX,
  671. hph_mode);
  672. break;
  673. };
  674. return ret;
  675. }
  676. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  677. struct snd_kcontrol *kcontrol,
  678. int event)
  679. {
  680. struct snd_soc_component *component =
  681. snd_soc_dapm_to_component(w->dapm);
  682. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  683. int hph_mode = wcd938x->hph_mode;
  684. int ret = 0;
  685. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  686. w->name, event);
  687. switch (event) {
  688. case SND_SOC_DAPM_PRE_PMU:
  689. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  690. wcd938x->rx_swr_dev->dev_num,
  691. true);
  692. break;
  693. case SND_SOC_DAPM_POST_PMU:
  694. /* 6 msec delay as per HW requirement */
  695. usleep_range(6000, 6010);
  696. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  697. snd_soc_component_update_bits(component,
  698. WCD938X_ANA_RX_SUPPLIES,
  699. 0x02, 0x02);
  700. if (wcd938x->update_wcd_event)
  701. wcd938x->update_wcd_event(wcd938x->handle,
  702. WCD_BOLERO_EVT_RX_MUTE,
  703. (WCD_RX1 << 0x10));
  704. break;
  705. case SND_SOC_DAPM_PRE_PMD:
  706. if (wcd938x->update_wcd_event)
  707. wcd938x->update_wcd_event(wcd938x->handle,
  708. WCD_BOLERO_EVT_RX_MUTE,
  709. (WCD_RX1 << 0x10 | 0x1));
  710. break;
  711. case SND_SOC_DAPM_POST_PMD:
  712. /* 7 msec delay as per HW requirement */
  713. usleep_range(7000, 7010);
  714. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  715. WCD_CLSH_EVENT_POST_PA,
  716. WCD_CLSH_STATE_EAR,
  717. hph_mode);
  718. break;
  719. };
  720. return ret;
  721. }
  722. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  723. struct snd_kcontrol *kcontrol,
  724. int event)
  725. {
  726. struct snd_soc_component *component =
  727. snd_soc_dapm_to_component(w->dapm);
  728. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  729. int mode = wcd938x->hph_mode;
  730. int ret = 0;
  731. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  732. w->name, event);
  733. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  734. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  735. wcd938x_rx_connect_port(component, CLSH,
  736. SND_SOC_DAPM_EVENT_ON(event));
  737. }
  738. if (SND_SOC_DAPM_EVENT_OFF(event))
  739. ret = swr_slvdev_datapath_control(
  740. wcd938x->rx_swr_dev,
  741. wcd938x->rx_swr_dev->dev_num,
  742. false);
  743. return ret;
  744. }
  745. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  746. struct snd_kcontrol *kcontrol,
  747. int event)
  748. {
  749. struct snd_soc_component *component =
  750. snd_soc_dapm_to_component(w->dapm);
  751. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  752. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  753. w->name, event);
  754. switch (event) {
  755. case SND_SOC_DAPM_PRE_PMU:
  756. wcd938x_rx_connect_port(component, HPH_L, true);
  757. if (wcd938x->comp1_enable)
  758. wcd938x_rx_connect_port(component, COMP_L, true);
  759. break;
  760. case SND_SOC_DAPM_POST_PMD:
  761. wcd938x_rx_connect_port(component, HPH_L, false);
  762. if (wcd938x->comp1_enable)
  763. wcd938x_rx_connect_port(component, COMP_L, false);
  764. wcd938x_rx_clk_disable(component);
  765. snd_soc_component_update_bits(component,
  766. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  767. 0x01, 0x00);
  768. break;
  769. };
  770. return 0;
  771. }
  772. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  773. struct snd_kcontrol *kcontrol, int event)
  774. {
  775. struct snd_soc_component *component =
  776. snd_soc_dapm_to_component(w->dapm);
  777. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  778. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  779. w->name, event);
  780. switch (event) {
  781. case SND_SOC_DAPM_PRE_PMU:
  782. wcd938x_rx_connect_port(component, HPH_R, true);
  783. if (wcd938x->comp2_enable)
  784. wcd938x_rx_connect_port(component, COMP_R, true);
  785. break;
  786. case SND_SOC_DAPM_POST_PMD:
  787. wcd938x_rx_connect_port(component, HPH_R, false);
  788. if (wcd938x->comp2_enable)
  789. wcd938x_rx_connect_port(component, COMP_R, false);
  790. wcd938x_rx_clk_disable(component);
  791. snd_soc_component_update_bits(component,
  792. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  793. 0x02, 0x00);
  794. break;
  795. };
  796. return 0;
  797. }
  798. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  799. struct snd_kcontrol *kcontrol,
  800. int event)
  801. {
  802. struct snd_soc_component *component =
  803. snd_soc_dapm_to_component(w->dapm);
  804. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  805. w->name, event);
  806. switch (event) {
  807. case SND_SOC_DAPM_PRE_PMU:
  808. wcd938x_rx_connect_port(component, LO, true);
  809. break;
  810. case SND_SOC_DAPM_POST_PMD:
  811. wcd938x_rx_connect_port(component, LO, false);
  812. /* 6 msec delay as per HW requirement */
  813. usleep_range(6000, 6010);
  814. wcd938x_rx_clk_disable(component);
  815. snd_soc_component_update_bits(component,
  816. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  817. break;
  818. }
  819. return 0;
  820. }
  821. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  822. struct snd_kcontrol *kcontrol,
  823. int event)
  824. {
  825. struct snd_soc_component *component =
  826. snd_soc_dapm_to_component(w->dapm);
  827. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  828. u16 dmic_clk_reg;
  829. s32 *dmic_clk_cnt;
  830. unsigned int dmic;
  831. char *wname;
  832. int ret = 0;
  833. wname = strpbrk(w->name, "012345");
  834. if (!wname) {
  835. dev_err(component->dev, "%s: widget not found\n", __func__);
  836. return -EINVAL;
  837. }
  838. ret = kstrtouint(wname, 10, &dmic);
  839. if (ret < 0) {
  840. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  841. __func__);
  842. return -EINVAL;
  843. }
  844. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  845. w->name, event);
  846. switch (dmic) {
  847. case 0:
  848. case 1:
  849. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  850. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_CTL;
  851. break;
  852. case 2:
  853. case 3:
  854. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  855. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  856. break;
  857. case 4:
  858. case 5:
  859. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  860. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  861. break;
  862. default:
  863. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  864. __func__);
  865. return -EINVAL;
  866. };
  867. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  868. __func__, event, dmic, *dmic_clk_cnt);
  869. switch (event) {
  870. case SND_SOC_DAPM_PRE_PMU:
  871. snd_soc_component_update_bits(component,
  872. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  873. snd_soc_component_update_bits(component,
  874. dmic_clk_reg, 0x07, 0x02);
  875. snd_soc_component_update_bits(component,
  876. dmic_clk_reg, 0x08, 0x08);
  877. snd_soc_component_update_bits(component,
  878. dmic_clk_reg, 0x70, 0x20);
  879. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  880. break;
  881. case SND_SOC_DAPM_POST_PMD:
  882. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  883. break;
  884. };
  885. return 0;
  886. }
  887. /*
  888. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  889. * @micb_mv: micbias in mv
  890. *
  891. * return register value converted
  892. */
  893. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  894. {
  895. /* min micbias voltage is 1V and maximum is 2.85V */
  896. if (micb_mv < 1000 || micb_mv > 2850) {
  897. pr_err("%s: unsupported micbias voltage\n", __func__);
  898. return -EINVAL;
  899. }
  900. return (micb_mv - 1000) / 50;
  901. }
  902. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  903. /*
  904. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  905. * @component: handle to snd_soc_component *
  906. * @req_volt: micbias voltage to be set
  907. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  908. *
  909. * return 0 if adjustment is success or error code in case of failure
  910. */
  911. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  912. int req_volt, int micb_num)
  913. {
  914. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  915. int cur_vout_ctl, req_vout_ctl;
  916. int micb_reg, micb_val, micb_en;
  917. int ret = 0;
  918. switch (micb_num) {
  919. case MIC_BIAS_1:
  920. micb_reg = WCD938X_ANA_MICB1;
  921. break;
  922. case MIC_BIAS_2:
  923. micb_reg = WCD938X_ANA_MICB2;
  924. break;
  925. case MIC_BIAS_3:
  926. micb_reg = WCD938X_ANA_MICB3;
  927. break;
  928. case MIC_BIAS_4:
  929. micb_reg = WCD938X_ANA_MICB4;
  930. break;
  931. default:
  932. return -EINVAL;
  933. }
  934. mutex_lock(&wcd938x->micb_lock);
  935. /*
  936. * If requested micbias voltage is same as current micbias
  937. * voltage, then just return. Otherwise, adjust voltage as
  938. * per requested value. If micbias is already enabled, then
  939. * to avoid slow micbias ramp-up or down enable pull-up
  940. * momentarily, change the micbias value and then re-enable
  941. * micbias.
  942. */
  943. micb_val = snd_soc_component_read32(component, micb_reg);
  944. micb_en = (micb_val & 0xC0) >> 6;
  945. cur_vout_ctl = micb_val & 0x3F;
  946. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  947. if (req_vout_ctl < 0) {
  948. ret = -EINVAL;
  949. goto exit;
  950. }
  951. if (cur_vout_ctl == req_vout_ctl) {
  952. ret = 0;
  953. goto exit;
  954. }
  955. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  956. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  957. req_volt, micb_en);
  958. if (micb_en == 0x1)
  959. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  960. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  961. if (micb_en == 0x1) {
  962. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  963. /*
  964. * Add 2ms delay as per HW requirement after enabling
  965. * micbias
  966. */
  967. usleep_range(2000, 2100);
  968. }
  969. exit:
  970. mutex_unlock(&wcd938x->micb_lock);
  971. return ret;
  972. }
  973. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  974. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  975. struct snd_kcontrol *kcontrol,
  976. int event)
  977. {
  978. struct snd_soc_component *component =
  979. snd_soc_dapm_to_component(w->dapm);
  980. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  981. int ret = 0;
  982. switch (event) {
  983. case SND_SOC_DAPM_PRE_PMU:
  984. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  985. wcd938x->tx_swr_dev->dev_num,
  986. true);
  987. break;
  988. case SND_SOC_DAPM_POST_PMD:
  989. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  990. wcd938x->tx_swr_dev->dev_num,
  991. false);
  992. break;
  993. };
  994. return ret;
  995. }
  996. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  997. struct snd_kcontrol *kcontrol,
  998. int event){
  999. struct snd_soc_component *component =
  1000. snd_soc_dapm_to_component(w->dapm);
  1001. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1002. w->name, event);
  1003. switch (event) {
  1004. case SND_SOC_DAPM_PRE_PMU:
  1005. snd_soc_component_update_bits(component,
  1006. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1007. snd_soc_component_update_bits(component,
  1008. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1009. snd_soc_component_update_bits(component,
  1010. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1011. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1012. break;
  1013. case SND_SOC_DAPM_POST_PMD:
  1014. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1015. snd_soc_component_update_bits(component,
  1016. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1017. break;
  1018. };
  1019. return 0;
  1020. }
  1021. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1022. struct snd_kcontrol *kcontrol, int event)
  1023. {
  1024. struct snd_soc_component *component =
  1025. snd_soc_dapm_to_component(w->dapm);
  1026. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1027. w->name, event);
  1028. switch (event) {
  1029. case SND_SOC_DAPM_PRE_PMU:
  1030. snd_soc_component_update_bits(component,
  1031. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1032. snd_soc_component_update_bits(component,
  1033. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1034. snd_soc_component_update_bits(component,
  1035. WCD938X_ANA_TX_CH2, 0x40, 0x40);
  1036. snd_soc_component_update_bits(component,
  1037. WCD938X_ANA_TX_CH2, 0x20, 0x20);
  1038. snd_soc_component_update_bits(component,
  1039. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1040. snd_soc_component_update_bits(component,
  1041. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1042. snd_soc_component_update_bits(component,
  1043. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1044. snd_soc_component_update_bits(component,
  1045. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1046. snd_soc_component_update_bits(component,
  1047. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1048. break;
  1049. case SND_SOC_DAPM_POST_PMD:
  1050. snd_soc_component_update_bits(component,
  1051. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1052. snd_soc_component_update_bits(component,
  1053. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1054. snd_soc_component_update_bits(component,
  1055. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1056. snd_soc_component_update_bits(component,
  1057. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1058. snd_soc_component_update_bits(component,
  1059. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1060. break;
  1061. };
  1062. return 0;
  1063. }
  1064. int wcd938x_micbias_control(struct snd_soc_component *component,
  1065. int micb_num, int req, bool is_dapm)
  1066. {
  1067. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1068. int micb_index = micb_num - 1;
  1069. u16 micb_reg;
  1070. int pre_off_event = 0, post_off_event = 0;
  1071. int post_on_event = 0, post_dapm_off = 0;
  1072. int post_dapm_on = 0;
  1073. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1074. dev_err(component->dev,
  1075. "%s: Invalid micbias index, micb_ind:%d\n",
  1076. __func__, micb_index);
  1077. return -EINVAL;
  1078. }
  1079. switch (micb_num) {
  1080. case MIC_BIAS_1:
  1081. micb_reg = WCD938X_ANA_MICB1;
  1082. break;
  1083. case MIC_BIAS_2:
  1084. micb_reg = WCD938X_ANA_MICB2;
  1085. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1086. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1087. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1088. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1089. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1090. break;
  1091. case MIC_BIAS_3:
  1092. micb_reg = WCD938X_ANA_MICB3;
  1093. break;
  1094. case MIC_BIAS_4:
  1095. micb_reg = WCD938X_ANA_MICB4;
  1096. break;
  1097. default:
  1098. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1099. __func__, micb_num);
  1100. return -EINVAL;
  1101. };
  1102. mutex_lock(&wcd938x->micb_lock);
  1103. switch (req) {
  1104. case MICB_PULLUP_ENABLE:
  1105. wcd938x->pullup_ref[micb_index]++;
  1106. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1107. (wcd938x->micb_ref[micb_index] == 0))
  1108. snd_soc_component_update_bits(component, micb_reg,
  1109. 0xC0, 0x80);
  1110. break;
  1111. case MICB_PULLUP_DISABLE:
  1112. if (wcd938x->pullup_ref[micb_index] > 0)
  1113. wcd938x->pullup_ref[micb_index]--;
  1114. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1115. (wcd938x->micb_ref[micb_index] == 0))
  1116. snd_soc_component_update_bits(component, micb_reg,
  1117. 0xC0, 0x00);
  1118. break;
  1119. case MICB_ENABLE:
  1120. wcd938x->micb_ref[micb_index]++;
  1121. if (wcd938x->micb_ref[micb_index] == 1) {
  1122. snd_soc_component_update_bits(component,
  1123. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1124. snd_soc_component_update_bits(component,
  1125. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1126. snd_soc_component_update_bits(component,
  1127. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1128. snd_soc_component_update_bits(component,
  1129. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1130. snd_soc_component_update_bits(component,
  1131. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1132. snd_soc_component_update_bits(component,
  1133. micb_reg, 0xC0, 0x40);
  1134. if (post_on_event)
  1135. blocking_notifier_call_chain(
  1136. &wcd938x->mbhc->notifier,
  1137. post_on_event,
  1138. &wcd938x->mbhc->wcd_mbhc);
  1139. }
  1140. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1141. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1142. post_dapm_on,
  1143. &wcd938x->mbhc->wcd_mbhc);
  1144. break;
  1145. case MICB_DISABLE:
  1146. if (wcd938x->micb_ref[micb_index] > 0)
  1147. wcd938x->micb_ref[micb_index]--;
  1148. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1149. (wcd938x->pullup_ref[micb_index] > 0))
  1150. snd_soc_component_update_bits(component, micb_reg,
  1151. 0xC0, 0x80);
  1152. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1153. (wcd938x->pullup_ref[micb_index] == 0)) {
  1154. if (pre_off_event && wcd938x->mbhc)
  1155. blocking_notifier_call_chain(
  1156. &wcd938x->mbhc->notifier,
  1157. pre_off_event,
  1158. &wcd938x->mbhc->wcd_mbhc);
  1159. snd_soc_component_update_bits(component, micb_reg,
  1160. 0xC0, 0x00);
  1161. if (post_off_event && wcd938x->mbhc)
  1162. blocking_notifier_call_chain(
  1163. &wcd938x->mbhc->notifier,
  1164. post_off_event,
  1165. &wcd938x->mbhc->wcd_mbhc);
  1166. }
  1167. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1168. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1169. post_dapm_off,
  1170. &wcd938x->mbhc->wcd_mbhc);
  1171. break;
  1172. };
  1173. dev_dbg(component->dev,
  1174. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1175. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1176. wcd938x->pullup_ref[micb_index]);
  1177. mutex_unlock(&wcd938x->micb_lock);
  1178. return 0;
  1179. }
  1180. EXPORT_SYMBOL(wcd938x_micbias_control);
  1181. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1182. {
  1183. int ret = 0;
  1184. uint8_t devnum = 0;
  1185. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1186. if (ret) {
  1187. dev_err(&swr_dev->dev,
  1188. "%s get devnum %d for dev addr %lx failed\n",
  1189. __func__, devnum, swr_dev->addr);
  1190. swr_remove_device(swr_dev);
  1191. return ret;
  1192. }
  1193. swr_dev->dev_num = devnum;
  1194. return 0;
  1195. }
  1196. static int wcd938x_event_notify(struct notifier_block *block,
  1197. unsigned long val,
  1198. void *data)
  1199. {
  1200. u16 event = (val & 0xffff);
  1201. u16 amic;
  1202. u16 mask = 0x40, reg = 0x0;
  1203. int ret = 0;
  1204. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1205. struct snd_soc_component *component = wcd938x->component;
  1206. struct wcd_mbhc *mbhc;
  1207. switch (event) {
  1208. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1209. amic = (val >> 0x10);
  1210. if (amic == 0x1 || amic == 0x2)
  1211. reg = WCD938X_ANA_TX_CH2;
  1212. else if (amic == 0x3)
  1213. reg = WCD938X_ANA_TX_CH3_HPF;
  1214. else
  1215. return 0;
  1216. if (amic == 0x2)
  1217. mask = 0x20;
  1218. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1219. break;
  1220. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1221. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1222. 0xC0, 0x00);
  1223. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1224. 0x80, 0x00);
  1225. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1226. 0x80, 0x00);
  1227. break;
  1228. case BOLERO_WCD_EVT_SSR_DOWN:
  1229. wcd938x_reset_low(wcd938x->dev);
  1230. break;
  1231. case BOLERO_WCD_EVT_SSR_UP:
  1232. wcd938x_reset(wcd938x->dev);
  1233. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1234. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1235. regcache_mark_dirty(wcd938x->regmap);
  1236. regcache_sync(wcd938x->regmap);
  1237. /* Initialize MBHC module */
  1238. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1239. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1240. if (ret) {
  1241. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1242. __func__);
  1243. } else {
  1244. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1245. }
  1246. break;
  1247. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1248. snd_soc_update_bits(codec, WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1249. ((val >> 0x10) << 0x01));
  1250. break;
  1251. default:
  1252. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1253. break;
  1254. }
  1255. return 0;
  1256. }
  1257. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1258. int event)
  1259. {
  1260. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1261. int micb_num;
  1262. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1263. __func__, w->name, event);
  1264. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1265. micb_num = MIC_BIAS_1;
  1266. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1267. micb_num = MIC_BIAS_2;
  1268. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1269. micb_num = MIC_BIAS_3;
  1270. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1271. micb_num = MIC_BIAS_4;
  1272. else
  1273. return -EINVAL;
  1274. switch (event) {
  1275. case SND_SOC_DAPM_PRE_PMU:
  1276. wcd938x_micbias_control(component, micb_num,
  1277. MICB_ENABLE, true);
  1278. break;
  1279. case SND_SOC_DAPM_POST_PMU:
  1280. /* 1 msec delay as per HW requirement */
  1281. usleep_range(1000, 1100);
  1282. break;
  1283. case SND_SOC_DAPM_POST_PMD:
  1284. wcd938x_micbias_control(component, micb_num,
  1285. MICB_DISABLE, true);
  1286. break;
  1287. };
  1288. return 0;
  1289. }
  1290. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1291. struct snd_kcontrol *kcontrol,
  1292. int event)
  1293. {
  1294. return __wcd938x_codec_enable_micbias(w, event);
  1295. }
  1296. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1297. struct snd_ctl_elem_value *ucontrol)
  1298. {
  1299. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1300. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1301. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1302. return 0;
  1303. }
  1304. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1305. struct snd_ctl_elem_value *ucontrol)
  1306. {
  1307. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1308. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1309. u32 mode_val;
  1310. mode_val = ucontrol->value.enumerated.item[0];
  1311. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1312. if (mode_val == 0) {
  1313. dev_info(component->dev,
  1314. "%s:Invalid HPH Mode, default to class_AB\n",
  1315. __func__);
  1316. mode_val = 3; /* enum will be updated later */
  1317. }
  1318. wcd938x->hph_mode = mode_val;
  1319. return 0;
  1320. }
  1321. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. struct snd_soc_component *component =
  1325. snd_soc_kcontrol_component(kcontrol);
  1326. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1327. bool hphr;
  1328. struct soc_multi_mixer_control *mc;
  1329. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1330. hphr = mc->shift;
  1331. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1332. wcd938x->comp1_enable;
  1333. return 0;
  1334. }
  1335. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1336. struct snd_ctl_elem_value *ucontrol)
  1337. {
  1338. struct snd_soc_component *component =
  1339. snd_soc_kcontrol_component(kcontrol);
  1340. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1341. int value = ucontrol->value.integer.value[0];
  1342. bool hphr;
  1343. struct soc_multi_mixer_control *mc;
  1344. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1345. hphr = mc->shift;
  1346. if (hphr)
  1347. wcd938x->comp2_enable = value;
  1348. else
  1349. wcd938x->comp1_enable = value;
  1350. return 0;
  1351. }
  1352. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1353. struct snd_kcontrol *kcontrol,
  1354. int event)
  1355. {
  1356. struct snd_soc_component *component =
  1357. snd_soc_dapm_to_component(w->dapm);
  1358. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1359. struct wcd938x_pdata *pdata = NULL;
  1360. int ret = 0;
  1361. pdata = dev_get_platdata(wcd938x->dev);
  1362. if (!pdata) {
  1363. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1364. return -EINVAL;
  1365. }
  1366. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1367. w->name, event);
  1368. switch (event) {
  1369. case SND_SOC_DAPM_PRE_PMU:
  1370. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  1371. wcd938x->supplies,
  1372. pdata->regulator,
  1373. pdata->num_supplies,
  1374. "cdc-vdd-buck");
  1375. if (ret == -EINVAL) {
  1376. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1377. __func__);
  1378. return ret;
  1379. }
  1380. /*
  1381. * 200us sleep is required after LDO15 is enabled as per
  1382. * HW requirement
  1383. */
  1384. usleep_range(200, 250);
  1385. break;
  1386. case SND_SOC_DAPM_POST_PMD:
  1387. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  1388. wcd938x->supplies,
  1389. pdata->regulator,
  1390. pdata->num_supplies,
  1391. "cdc-vdd-buck");
  1392. if (ret == -EINVAL) {
  1393. dev_err(dev, "%s: vdd buck is not disabled\n",
  1394. __func__);
  1395. return 0;
  1396. }
  1397. break;
  1398. }
  1399. return 0;
  1400. }
  1401. static int wcd938x_tx_hdr_get(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_value *ucontrol)
  1403. {
  1404. struct snd_soc_component *component =
  1405. snd_soc_kcontrol_component(kcontrol);
  1406. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1407. int hdr = ((struct soc_multi_mixer_control *)
  1408. kcontrol->private_value)->shift;
  1409. ucontrol->value.integer.value[0] = wcd938x->hdr_en[hdr];
  1410. return 0;
  1411. }
  1412. static int wcd938x_tx_hdr_put(struct snd_kcontrol *kcontrol,
  1413. struct snd_ctl_elem_value *ucontrol)
  1414. {
  1415. struct snd_soc_component *component =
  1416. snd_soc_kcontrol_component(kcontrol);
  1417. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1418. int hdr = ((struct soc_multi_mixer_control *)
  1419. kcontrol->private_value)->shift;
  1420. int val = ucontrol->value.integer.value[0];
  1421. u8 mask = 0;
  1422. wcd938x->hdr_en[hdr] = val;
  1423. switch(val) {
  1424. case TX_HDR12:
  1425. mask = (1 << 4);
  1426. val = (val << 4);
  1427. break;
  1428. case TX_HDR34:
  1429. mask = (1 << 3);
  1430. val = (val << 3);
  1431. break;
  1432. default:
  1433. dev_err(component->dev, "%s: unknown HDR input: %d\n",
  1434. __func__, hdr);
  1435. break;
  1436. }
  1437. if (mask)
  1438. snd_soc_component_update_bits(component,
  1439. WCD938X_TX_NEW_AMIC_MUX_CFG, mask, val);
  1440. return 0;
  1441. }
  1442. static const char * const rx_hph_mode_mux_text[] = {
  1443. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1444. "CLS_H_ULP", "CLS_AB_HIFI",
  1445. };
  1446. static const struct soc_enum rx_hph_mode_mux_enum =
  1447. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1448. rx_hph_mode_mux_text);
  1449. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1450. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1451. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1452. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1453. wcd938x_get_compander, wcd938x_set_compander),
  1454. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1455. wcd938x_get_compander, wcd938x_set_compander),
  1456. SOC_SINGLE_EXT("TX HDR12", SND_SOC_NOPM, TX_HDR12, 1, 0,
  1457. wcd938x_tx_hdr_get, wcd938x_tx_hdr_put),
  1458. SOC_SINGLE_EXT("TX HDR34", SND_SOC_NOPM, TX_HDR34, 1, 0,
  1459. wcd938x_tx_hdr_get, wcd938x_tx_hdr_put),
  1460. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1461. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1462. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1463. analog_gain),
  1464. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1465. analog_gain),
  1466. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1467. analog_gain),
  1468. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1469. analog_gain),
  1470. };
  1471. static const struct snd_kcontrol_new adc1_switch[] = {
  1472. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1473. };
  1474. static const struct snd_kcontrol_new adc2_switch[] = {
  1475. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1476. };
  1477. static const struct snd_kcontrol_new adc3_switch[] = {
  1478. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1479. };
  1480. static const struct snd_kcontrol_new adc4_switch[] = {
  1481. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1482. };
  1483. static const struct snd_kcontrol_new dmic1_switch[] = {
  1484. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1485. };
  1486. static const struct snd_kcontrol_new dmic2_switch[] = {
  1487. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1488. };
  1489. static const struct snd_kcontrol_new dmic3_switch[] = {
  1490. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1491. };
  1492. static const struct snd_kcontrol_new dmic4_switch[] = {
  1493. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1494. };
  1495. static const struct snd_kcontrol_new dmic5_switch[] = {
  1496. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1497. };
  1498. static const struct snd_kcontrol_new dmic6_switch[] = {
  1499. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1500. };
  1501. static const struct snd_kcontrol_new dmic7_switch[] = {
  1502. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1503. };
  1504. static const struct snd_kcontrol_new dmic8_switch[] = {
  1505. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1506. };
  1507. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1508. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1509. };
  1510. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1511. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1512. };
  1513. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1514. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1515. };
  1516. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1517. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1518. };
  1519. static const char * const adc2_mux_text[] = {
  1520. "INP2", "INP3"
  1521. };
  1522. static const struct soc_enum adc2_enum =
  1523. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1524. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1525. static const struct snd_kcontrol_new tx_adc2_mux =
  1526. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1527. static const char * const adc3_mux_text[] = {
  1528. "INP4", "INP6"
  1529. };
  1530. static const struct soc_enum adc3_enum =
  1531. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1532. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1533. static const struct snd_kcontrol_new tx_adc3_mux =
  1534. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1535. static const char * const adc4_mux_text[] = {
  1536. "INP5", "INP7"
  1537. };
  1538. static const struct soc_enum adc4_enum =
  1539. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1540. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1541. static const struct snd_kcontrol_new tx_adc4_mux =
  1542. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1543. static const char * const rdac3_mux_text[] = {
  1544. "RX1", "RX3"
  1545. };
  1546. static const struct soc_enum rdac3_enum =
  1547. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1548. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1549. static const struct snd_kcontrol_new rx_rdac3_mux =
  1550. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1551. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1552. /*input widgets*/
  1553. SND_SOC_DAPM_INPUT("AMIC1"),
  1554. SND_SOC_DAPM_INPUT("AMIC2"),
  1555. SND_SOC_DAPM_INPUT("AMIC3"),
  1556. SND_SOC_DAPM_INPUT("AMIC4"),
  1557. SND_SOC_DAPM_INPUT("AMIC5"),
  1558. SND_SOC_DAPM_INPUT("AMIC6"),
  1559. SND_SOC_DAPM_INPUT("AMIC7"),
  1560. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1561. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1562. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1563. /*tx widgets*/
  1564. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1565. wcd938x_codec_enable_adc,
  1566. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1567. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 0, 1,
  1568. wcd938x_codec_enable_adc,
  1569. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1570. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 0, 2,
  1571. wcd938x_codec_enable_adc,
  1572. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1573. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 0, 3,
  1574. wcd938x_codec_enable_adc,
  1575. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1576. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1577. wcd938x_codec_enable_dmic,
  1578. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1579. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 1,
  1580. wcd938x_codec_enable_dmic,
  1581. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1582. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 2,
  1583. wcd938x_codec_enable_dmic,
  1584. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1585. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 3,
  1586. wcd938x_codec_enable_dmic,
  1587. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1588. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 4,
  1589. wcd938x_codec_enable_dmic,
  1590. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1591. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 0, 5,
  1592. wcd938x_codec_enable_dmic,
  1593. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1594. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 0, 6,
  1595. wcd938x_codec_enable_dmic,
  1596. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1597. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 0, 7,
  1598. wcd938x_codec_enable_dmic,
  1599. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1600. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1601. NULL, 0, wcd938x_enable_req,
  1602. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1603. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1604. NULL, 0, wcd938x_enable_req,
  1605. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1606. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1607. NULL, 0, wcd938x_enable_req,
  1608. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1609. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 0, 0,
  1610. NULL, 0, wcd938x_enable_req,
  1611. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1612. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1613. &tx_adc2_mux),
  1614. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1615. &tx_adc3_mux),
  1616. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1617. &tx_adc4_mux),
  1618. /*tx mixers*/
  1619. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1620. adc1_switch, ARRAY_SIZE(adc1_switch),
  1621. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1622. SND_SOC_DAPM_POST_PMD),
  1623. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1624. adc2_switch, ARRAY_SIZE(adc2_switch),
  1625. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1626. SND_SOC_DAPM_POST_PMD),
  1627. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1628. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1629. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1630. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1631. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1632. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1633. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1634. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1635. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1636. SND_SOC_DAPM_POST_PMD),
  1637. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1638. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1639. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1640. SND_SOC_DAPM_POST_PMD),
  1641. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1642. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1643. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1644. SND_SOC_DAPM_POST_PMD),
  1645. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1646. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1647. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1648. SND_SOC_DAPM_POST_PMD),
  1649. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1650. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1651. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1652. SND_SOC_DAPM_POST_PMD),
  1653. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1654. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1655. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1656. SND_SOC_DAPM_POST_PMD),
  1657. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1658. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1659. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1660. SND_SOC_DAPM_POST_PMD),
  1661. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1662. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1663. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1664. SND_SOC_DAPM_POST_PMD),
  1665. /* micbias widgets*/
  1666. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1667. wcd938x_codec_enable_micbias,
  1668. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1669. SND_SOC_DAPM_POST_PMD),
  1670. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1671. wcd938x_codec_enable_micbias,
  1672. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1673. SND_SOC_DAPM_POST_PMD),
  1674. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1675. wcd938x_codec_enable_micbias,
  1676. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1677. SND_SOC_DAPM_POST_PMD),
  1678. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1679. wcd938x_codec_enable_micbias,
  1680. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1681. SND_SOC_DAPM_POST_PMD),
  1682. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1683. wcd938x_codec_enable_vdd_buck,
  1684. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1685. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1686. wcd938x_enable_clsh,
  1687. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1688. /*rx widgets*/
  1689. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1690. wcd938x_codec_enable_ear_pa,
  1691. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1692. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1693. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1694. wcd938x_codec_enable_aux_pa,
  1695. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1696. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1697. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1698. wcd938x_codec_enable_hphl_pa,
  1699. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1700. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1701. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1702. wcd938x_codec_enable_hphr_pa,
  1703. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1704. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1705. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1706. wcd938x_codec_hphl_dac_event,
  1707. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1708. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1709. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1710. wcd938x_codec_hphr_dac_event,
  1711. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1712. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1713. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1714. wcd938x_codec_ear_dac_event,
  1715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1716. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1717. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1718. wcd938x_codec_aux_dac_event,
  1719. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1720. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1721. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1722. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1723. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1724. SND_SOC_DAPM_POST_PMD),
  1725. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1726. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1727. SND_SOC_DAPM_POST_PMD),
  1728. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1729. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1730. SND_SOC_DAPM_POST_PMD),
  1731. /* rx mixer widgets*/
  1732. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1733. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1734. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1735. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1736. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1737. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1738. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1739. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1740. /*output widgets tx*/
  1741. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1742. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1743. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1744. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  1745. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1746. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1747. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1748. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1749. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1750. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1751. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  1752. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  1753. /*output widgets rx*/
  1754. SND_SOC_DAPM_OUTPUT("EAR"),
  1755. SND_SOC_DAPM_OUTPUT("AUX"),
  1756. SND_SOC_DAPM_OUTPUT("HPHL"),
  1757. SND_SOC_DAPM_OUTPUT("HPHR"),
  1758. };
  1759. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  1760. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1761. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1762. {"ADC1 REQ", NULL, "ADC1"},
  1763. {"ADC1", NULL, "AMIC1"},
  1764. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1765. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1766. {"ADC2 REQ", NULL, "ADC2"},
  1767. {"ADC2", NULL, "ADC2 MUX"},
  1768. {"ADC2 MUX", "INP3", "AMIC3"},
  1769. {"ADC2 MUX", "INP2", "AMIC2"},
  1770. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1771. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1772. {"ADC3 REQ", NULL, "ADC3"},
  1773. {"ADC3", NULL, "ADC3 MUX"},
  1774. {"ADC3 MUX", "INP4", "AMIC4"},
  1775. {"ADC3 MUX", "INP6", "AMIC6"},
  1776. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  1777. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  1778. {"ADC4 REQ", NULL, "ADC4"},
  1779. {"ADC4", NULL, "ADC4 MUX"},
  1780. {"ADC4 MUX", "INP5", "AMIC5"},
  1781. {"ADC4 MUX", "INP7", "AMIC7"},
  1782. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1783. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1784. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1785. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1786. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1787. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1788. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1789. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1790. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1791. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1792. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1793. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1794. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  1795. {"DMIC7_MIXER", "Switch", "DMIC7"},
  1796. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  1797. {"DMIC8_MIXER", "Switch", "DMIC8"},
  1798. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1799. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1800. {"RX1", NULL, "IN1_HPHL"},
  1801. {"RDAC1", NULL, "RX1"},
  1802. {"HPHL_RDAC", "Switch", "RDAC1"},
  1803. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1804. {"HPHL", NULL, "HPHL PGA"},
  1805. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1806. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1807. {"RX2", NULL, "IN2_HPHR"},
  1808. {"RDAC2", NULL, "RX2"},
  1809. {"HPHR_RDAC", "Switch", "RDAC2"},
  1810. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1811. {"HPHR", NULL, "HPHR PGA"},
  1812. {"IN3_AUX", NULL, "VDD_BUCK"},
  1813. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1814. {"RX3", NULL, "IN3_AUX"},
  1815. {"RDAC4", NULL, "RX3"},
  1816. {"AUX_RDAC", "Switch", "RDAC4"},
  1817. {"AUX PGA", NULL, "AUX_RDAC"},
  1818. {"AUX", NULL, "AUX PGA"},
  1819. {"RDAC3_MUX", "RX3", "RX3"},
  1820. {"RDAC3_MUX", "RX1", "RX1"},
  1821. {"RDAC3", NULL, "RDAC3_MUX"},
  1822. {"EAR_RDAC", "Switch", "RDAC3"},
  1823. {"EAR PGA", NULL, "EAR_RDAC"},
  1824. {"EAR", NULL, "EAR PGA"},
  1825. };
  1826. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  1827. void *file_private_data,
  1828. struct file *file,
  1829. char __user *buf, size_t count,
  1830. loff_t pos)
  1831. {
  1832. struct wcd938x_priv *priv;
  1833. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  1834. int len = 0;
  1835. priv = (struct wcd938x_priv *) entry->private_data;
  1836. if (!priv) {
  1837. pr_err("%s: wcd938x priv is null\n", __func__);
  1838. return -EINVAL;
  1839. }
  1840. switch (priv->version) {
  1841. case WCD938X_VERSION_1_0:
  1842. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  1843. break;
  1844. default:
  1845. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1846. }
  1847. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1848. }
  1849. static struct snd_info_entry_ops wcd938x_info_ops = {
  1850. .read = wcd938x_version_read,
  1851. };
  1852. /*
  1853. * wcd938x_info_create_codec_entry - creates wcd938x module
  1854. * @codec_root: The parent directory
  1855. * @component: component instance
  1856. *
  1857. * Creates wcd938x module and version entry under the given
  1858. * parent directory.
  1859. *
  1860. * Return: 0 on success or negative error code on failure.
  1861. */
  1862. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  1863. struct snd_soc_component *component)
  1864. {
  1865. struct snd_info_entry *version_entry;
  1866. struct wcd938x_priv *priv;
  1867. struct snd_soc_card *card;
  1868. if (!codec_root || !component)
  1869. return -EINVAL;
  1870. priv = snd_soc_component_get_drvdata(component);
  1871. if (priv->entry) {
  1872. dev_dbg(priv->dev,
  1873. "%s:wcd938x module already created\n", __func__);
  1874. return 0;
  1875. }
  1876. card = component->card;
  1877. priv->entry = snd_info_create_subdir(codec_root->module,
  1878. "wcd938x", codec_root);
  1879. if (!priv->entry) {
  1880. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  1881. __func__);
  1882. return -ENOMEM;
  1883. }
  1884. version_entry = snd_info_create_card_entry(card->snd_card,
  1885. "version",
  1886. priv->entry);
  1887. if (!version_entry) {
  1888. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  1889. __func__);
  1890. return -ENOMEM;
  1891. }
  1892. version_entry->private_data = priv;
  1893. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  1894. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  1895. version_entry->c.ops = &wcd938x_info_ops;
  1896. if (snd_info_register(version_entry) < 0) {
  1897. snd_info_free_entry(version_entry);
  1898. return -ENOMEM;
  1899. }
  1900. priv->version_entry = version_entry;
  1901. return 0;
  1902. }
  1903. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  1904. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  1905. {
  1906. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1907. int variant;
  1908. int ret = -EINVAL;
  1909. dev_info(component->dev, "%s()\n", __func__);
  1910. wcd938x = snd_soc_component_get_drvdata(component);
  1911. if (!wcd938x)
  1912. return -EINVAL;
  1913. wcd938x->component = component;
  1914. snd_soc_component_init_regmap(component, wcd938x->regmap);
  1915. variant = (snd_soc_component_read32(component,
  1916. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  1917. wcd938x->variant = variant;
  1918. wcd938x->fw_data = devm_kzalloc(component->dev,
  1919. sizeof(*(wcd938x->fw_data)),
  1920. GFP_KERNEL);
  1921. if (!wcd938x->fw_data) {
  1922. dev_err(component->dev, "Failed to allocate fw_data\n");
  1923. ret = -ENOMEM;
  1924. goto err;
  1925. }
  1926. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  1927. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  1928. WCD9XXX_CODEC_HWDEP_NODE, component);
  1929. if (ret < 0) {
  1930. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  1931. goto err_hwdep;
  1932. }
  1933. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  1934. if (ret) {
  1935. pr_err("%s: mbhc initialization failed\n", __func__);
  1936. goto err_hwdep;
  1937. }
  1938. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  1939. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  1940. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  1941. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  1942. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  1943. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  1944. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  1945. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  1946. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  1947. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  1948. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  1949. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  1950. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  1951. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  1952. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  1953. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  1954. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  1955. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  1956. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  1957. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  1958. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  1959. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  1960. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  1961. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  1962. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  1963. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  1964. snd_soc_dapm_sync(dapm);
  1965. wcd_cls_h_init(&wcd938x->clsh_info);
  1966. wcd938x_init_reg(component);
  1967. wcd938x->version = WCD938X_VERSION_1_0;
  1968. /* Register event notifier */
  1969. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  1970. if (wcd938x->register_notifier) {
  1971. ret = wcd938x->register_notifier(wcd938x->handle,
  1972. &wcd938x->nblock,
  1973. true);
  1974. if (ret) {
  1975. dev_err(component->dev,
  1976. "%s: Failed to register notifier %d\n",
  1977. __func__, ret);
  1978. return ret;
  1979. }
  1980. }
  1981. return ret;
  1982. err_hwdep:
  1983. wcd938x->fw_data = NULL;
  1984. err:
  1985. return ret;
  1986. }
  1987. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  1988. {
  1989. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1990. if (!wcd938x) {
  1991. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  1992. __func__);
  1993. return;
  1994. }
  1995. if (wcd938x->register_notifier)
  1996. wcd938x->register_notifier(wcd938x->handle,
  1997. &wcd938x->nblock,
  1998. false);
  1999. }
  2000. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2001. .name = WCD938X_DRV_NAME,
  2002. .probe = wcd938x_soc_codec_probe,
  2003. .remove = wcd938x_soc_codec_remove,
  2004. .controls = wcd938x_snd_controls,
  2005. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2006. .dapm_widgets = wcd938x_dapm_widgets,
  2007. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2008. .dapm_routes = wcd938x_audio_map,
  2009. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2010. };
  2011. static int wcd938x_reset(struct device *dev)
  2012. {
  2013. struct wcd938x_priv *wcd938x = NULL;
  2014. int rc = 0;
  2015. int value = 0;
  2016. if (!dev)
  2017. return -ENODEV;
  2018. wcd938x = dev_get_drvdata(dev);
  2019. if (!wcd938x)
  2020. return -EINVAL;
  2021. if (!wcd938x->rst_np) {
  2022. dev_err(dev, "%s: reset gpio device node not specified\n",
  2023. __func__);
  2024. return -EINVAL;
  2025. }
  2026. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2027. if (value > 0)
  2028. return 0;
  2029. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2030. if (rc) {
  2031. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2032. __func__);
  2033. return rc;
  2034. }
  2035. /* 20us sleep required after pulling the reset gpio to LOW */
  2036. usleep_range(20, 30);
  2037. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2038. if (rc) {
  2039. dev_err(dev, "%s: wcd active state request fail!\n",
  2040. __func__);
  2041. return rc;
  2042. }
  2043. /* 20us sleep required after pulling the reset gpio to HIGH */
  2044. usleep_range(20, 30);
  2045. return rc;
  2046. }
  2047. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2048. u32 *val)
  2049. {
  2050. int rc = 0;
  2051. rc = of_property_read_u32(dev->of_node, name, val);
  2052. if (rc)
  2053. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2054. __func__, name, dev->of_node->full_name);
  2055. return rc;
  2056. }
  2057. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2058. struct wcd938x_micbias_setting *mb)
  2059. {
  2060. u32 prop_val = 0;
  2061. int rc = 0;
  2062. /* MB1 */
  2063. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2064. NULL)) {
  2065. rc = wcd938x_read_of_property_u32(dev,
  2066. "qcom,cdc-micbias1-mv",
  2067. &prop_val);
  2068. if (!rc)
  2069. mb->micb1_mv = prop_val;
  2070. } else {
  2071. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2072. __func__);
  2073. }
  2074. /* MB2 */
  2075. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2076. NULL)) {
  2077. rc = wcd938x_read_of_property_u32(dev,
  2078. "qcom,cdc-micbias2-mv",
  2079. &prop_val);
  2080. if (!rc)
  2081. mb->micb2_mv = prop_val;
  2082. } else {
  2083. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2084. __func__);
  2085. }
  2086. /* MB3 */
  2087. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2088. NULL)) {
  2089. rc = wcd938x_read_of_property_u32(dev,
  2090. "qcom,cdc-micbias3-mv",
  2091. &prop_val);
  2092. if (!rc)
  2093. mb->micb3_mv = prop_val;
  2094. } else {
  2095. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2096. __func__);
  2097. }
  2098. }
  2099. static int wcd938x_reset_low(struct device *dev)
  2100. {
  2101. struct wcd938x_priv *wcd938x = NULL;
  2102. int rc = 0;
  2103. if (!dev)
  2104. return -ENODEV;
  2105. wcd938x = dev_get_drvdata(dev);
  2106. if (!wcd938x)
  2107. return -EINVAL;
  2108. if (!wcd938x->rst_np) {
  2109. dev_err(dev, "%s: reset gpio device node not specified\n",
  2110. __func__);
  2111. return -EINVAL;
  2112. }
  2113. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2114. if (rc) {
  2115. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2116. __func__);
  2117. return rc;
  2118. }
  2119. /* 20us sleep required after pulling the reset gpio to LOW */
  2120. usleep_range(20, 30);
  2121. return rc;
  2122. }
  2123. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2124. {
  2125. struct wcd938x_pdata *pdata = NULL;
  2126. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2127. GFP_KERNEL);
  2128. if (!pdata)
  2129. return NULL;
  2130. pdata->rst_np = of_parse_phandle(dev->of_node,
  2131. "qcom,wcd-rst-gpio-node", 0);
  2132. if (!pdata->rst_np) {
  2133. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2134. __func__, "qcom,wcd-rst-gpio-node",
  2135. dev->of_node->full_name);
  2136. return NULL;
  2137. }
  2138. /* Parse power supplies */
  2139. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2140. &pdata->num_supplies);
  2141. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2142. dev_err(dev, "%s: no power supplies defined for codec\n",
  2143. __func__);
  2144. return NULL;
  2145. }
  2146. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-swr-slave", 0);
  2147. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-swr-slave", 0);
  2148. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2149. return pdata;
  2150. }
  2151. static int wcd938x_bind(struct device *dev)
  2152. {
  2153. int ret = 0, i = 0;
  2154. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2155. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2156. /*
  2157. * Add 5msec delay to provide sufficient time for
  2158. * soundwire auto enumeration of slave devices as
  2159. * as per HW requirement.
  2160. */
  2161. usleep_range(5000, 5010);
  2162. ret = component_bind_all(dev, wcd938x);
  2163. if (ret) {
  2164. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2165. __func__, ret);
  2166. return ret;
  2167. }
  2168. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2169. if (!wcd938x->rx_swr_dev) {
  2170. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2171. __func__);
  2172. ret = -ENODEV;
  2173. goto err;
  2174. }
  2175. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2176. if (!wcd938x->tx_swr_dev) {
  2177. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2178. __func__);
  2179. ret = -ENODEV;
  2180. goto err;
  2181. }
  2182. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2183. &wcd938x_regmap_config);
  2184. if (!wcd938x->regmap) {
  2185. dev_err(dev, "%s: Regmap init failed\n",
  2186. __func__);
  2187. goto err;
  2188. }
  2189. /* Set all interupts as edge triggered */
  2190. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2191. regmap_write(wcd938x->regmap,
  2192. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2193. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2194. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2195. wcd938x->irq_info.codec_name = "WCD938X";
  2196. wcd938x->irq_info.regmap = wcd938x->regmap;
  2197. wcd938x->irq_info.dev = dev;
  2198. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2199. if (ret) {
  2200. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2201. __func__, ret);
  2202. goto err;
  2203. }
  2204. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2205. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2206. NULL, 0);
  2207. if (ret) {
  2208. dev_err(dev, "%s: Codec registration failed\n",
  2209. __func__);
  2210. goto err_irq;
  2211. }
  2212. return ret;
  2213. err_irq:
  2214. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2215. err:
  2216. component_unbind_all(dev, wcd938x);
  2217. return ret;
  2218. }
  2219. static void wcd938x_unbind(struct device *dev)
  2220. {
  2221. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2222. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2223. snd_soc_unregister_component(dev);
  2224. component_unbind_all(dev, wcd938x);
  2225. }
  2226. static const struct of_device_id wcd938x_dt_match[] = {
  2227. { .compatible = "qcom,wcd938x-codec" },
  2228. {}
  2229. };
  2230. static const struct component_master_ops wcd938x_comp_ops = {
  2231. .bind = wcd938x_bind,
  2232. .unbind = wcd938x_unbind,
  2233. };
  2234. static int wcd938x_compare_of(struct device *dev, void *data)
  2235. {
  2236. return dev->of_node == data;
  2237. }
  2238. static void wcd938x_release_of(struct device *dev, void *data)
  2239. {
  2240. of_node_put(data);
  2241. }
  2242. static int wcd938x_add_slave_components(struct device *dev,
  2243. struct component_match **matchptr)
  2244. {
  2245. struct device_node *np, *rx_node, *tx_node;
  2246. np = dev->of_node;
  2247. rx_node = of_parse_phandle(np, "qcom,rx-swr-slave", 0);
  2248. if (!rx_node) {
  2249. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2250. return -ENODEV;
  2251. }
  2252. of_node_get(rx_node);
  2253. component_match_add_release(dev, matchptr,
  2254. wcd938x_release_of,
  2255. wcd938x_compare_of,
  2256. rx_node);
  2257. tx_node = of_parse_phandle(np, "qcom,tx-swr-slave", 0);
  2258. if (!tx_node) {
  2259. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2260. return -ENODEV;
  2261. }
  2262. of_node_get(tx_node);
  2263. component_match_add_release(dev, matchptr,
  2264. wcd938x_release_of,
  2265. wcd938x_compare_of,
  2266. tx_node);
  2267. return 0;
  2268. }
  2269. static int wcd938x_probe(struct platform_device *pdev)
  2270. {
  2271. struct component_match *match = NULL;
  2272. struct wcd938x_priv *wcd938x = NULL;
  2273. struct wcd938x_pdata *pdata = NULL;
  2274. int ret;
  2275. wcd938x = devm_kzalloc(&pdev->dev, sizeof(struct wcd938x_priv),
  2276. GFP_KERNEL);
  2277. if (!wcd938x)
  2278. return -ENOMEM;
  2279. dev_set_drvdata(&pdev->dev, wcd938x);
  2280. pdata = wcd938x_populate_dt_data(&pdev->dev);
  2281. if (!pdata) {
  2282. dev_err(&pdev->dev, "%s: Fail to obtain platform data\n", __func__);
  2283. return -EINVAL;
  2284. }
  2285. dev->platform_data = pdata;
  2286. wcd938x->rst_np = pdata->rst_np;
  2287. ret = msm_cdc_init_supplies(&pdev->dev, &wcd938x->supplies,
  2288. pdata->regulator, pdata->num_supplies);
  2289. if (!wcd938x->supplies) {
  2290. dev_err(&pdev->dev, "%s: Cannot init wcd supplies\n",
  2291. __func__);
  2292. return ret;
  2293. }
  2294. wcd938x->handle = (void *)pdata->handle;
  2295. if (!wcd938x->handle) {
  2296. dev_err(dev, "%s: handle is NULL\n", __func__);
  2297. return -EINVAL;
  2298. }
  2299. wcd938x->update_wcd_event = pdata->update_wcd_event;
  2300. if (!wcd938x->update_wcd_event) {
  2301. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2302. __func__);
  2303. return -EINVAL;
  2304. }
  2305. wcd938x->register_notifier = pdata->register_notifier;
  2306. if (!wcd938x->register_notifier) {
  2307. dev_err(dev, "%s: register_notifier api is null!\n",
  2308. __func__);
  2309. return -EINVAL;
  2310. }
  2311. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2312. pdata->regulator,
  2313. pdata->num_supplies);
  2314. if (ret) {
  2315. dev_err(&pdev->dev, "%s: wcd static supply enable failed!\n",
  2316. __func__);
  2317. return ret;
  2318. }
  2319. ret = wcd938x_parse_port_mapping(&pdev->dev, "qcom,rx_swr_ch_map",
  2320. CODEC_RX);
  2321. ret |= wcd938x_parse_port_mapping(&pdev->dev, "qcom,tx_swr_ch_map",
  2322. CODEC_TX);
  2323. if (ret) {
  2324. dev_err(&pdev->dev, "Failed to read port mapping\n");
  2325. goto err;
  2326. }
  2327. ret = wcd938x_add_slave_components(&pdev->dev, &match);
  2328. if (ret)
  2329. goto err;
  2330. wcd938x_reset(dev);
  2331. return component_master_add_with_match(&pdev->dev,
  2332. &wcd938x_comp_ops, match);
  2333. err:
  2334. return ret;
  2335. }
  2336. static int wcd938x_remove(struct platform_device *pdev)
  2337. {
  2338. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2339. dev_set_drvdata(&pdev->dev, NULL);
  2340. return 0;
  2341. }
  2342. #ifdef CONFIG_PM_SLEEP
  2343. static int wcd938x_suspend(struct device *dev)
  2344. {
  2345. return 0;
  2346. }
  2347. static int wcd938x_resume(struct device *dev)
  2348. {
  2349. return 0;
  2350. }
  2351. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2352. SET_SYSTEM_SLEEP_PM_OPS(
  2353. wcd938x_suspend,
  2354. wcd938x_resume
  2355. )
  2356. };
  2357. #endif
  2358. static struct platform_driver wcd938x_codec_driver = {
  2359. .probe = wcd938x_probe,
  2360. .remove = wcd938x_remove,
  2361. .driver = {
  2362. .name = "wcd938x_codec",
  2363. .owner = THIS_MODULE,
  2364. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2365. #ifdef CONFIG_PM_SLEEP
  2366. .pm = &wcd938x_dev_pm_ops,
  2367. #endif
  2368. },
  2369. };
  2370. module_platform_driver(wcd938x_codec_driver);
  2371. MODULE_DESCRIPTION("WCD938X Codec driver");
  2372. MODULE_LICENSE("GPL v2");