internal.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _WCD938X_INTERNAL_H
  6. #define _WCD938X_INTERNAL_H
  7. #include <asoc/wcd-mbhc-v2.h>
  8. #include <asoc/wcd-irq.h>
  9. #include "wcd938x-mbhc.h"
  10. #define WCD938X_MAX_MICBIAS 4
  11. /* Convert from vout ctl to micbias voltage in mV */
  12. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  13. #define MAX_PORT 8
  14. #define MAX_CH_PER_PORT 8
  15. enum {
  16. TX_HDR12 = 0,
  17. TX_HDR34,
  18. TX_HDR_MAX,
  19. };
  20. extern struct regmap_config wcd938x_regmap_config;
  21. struct codec_port_info {
  22. u32 slave_port_type;
  23. u32 master_port_type;
  24. u32 ch_mask;
  25. u32 num_ch;
  26. u32 ch_rate;
  27. };
  28. struct wcd938x_priv {
  29. struct device *dev;
  30. int variant;
  31. struct snd_soc_component *component;
  32. struct device_node *rst_np;
  33. struct regmap *regmap;
  34. struct swr_device *rx_swr_dev;
  35. struct swr_device *tx_swr_dev;
  36. s32 micb_ref[WCD938X_MAX_MICBIAS];
  37. s32 pullup_ref[WCD938X_MAX_MICBIAS];
  38. struct fw_info *fw_data;
  39. struct device_node *wcd_rst_np;
  40. struct mutex micb_lock;
  41. s32 dmic_0_1_clk_cnt;
  42. s32 dmic_2_3_clk_cnt;
  43. s32 dmic_4_5_clk_cnt;
  44. s32 dmic_6_7_clk_cnt;
  45. int hdr_en[TX_HDR_MAX];
  46. /* class h specific info */
  47. struct wcd_clsh_cdc_info clsh_info;
  48. /* mbhc module */
  49. struct wcd938x_mbhc *mbhc;
  50. u32 hph_mode;
  51. bool comp1_enable;
  52. bool comp2_enable;
  53. struct irq_domain *virq;
  54. struct wcd_irq_info irq_info;
  55. u32 rx_clk_cnt;
  56. int num_irq_regs;
  57. /* to track the status */
  58. unsigned long status_mask;
  59. u8 num_tx_ports;
  60. u8 num_rx_ports;
  61. struct codec_port_info
  62. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  63. struct codec_port_info
  64. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  65. struct regulator_bulk_data *supplies;
  66. struct notifier_block nblock;
  67. /* wcd callback to bolero */
  68. void *handle;
  69. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  70. int (*register_notifier)(void *handle,
  71. struct notifier_block *nblock,
  72. bool enable);
  73. u32 version;
  74. /* Entry for version info */
  75. struct snd_info_entry *entry;
  76. struct snd_info_entry *version_entry;
  77. };
  78. struct wcd938x_micbias_setting {
  79. u8 ldoh_v;
  80. u32 cfilt1_mv;
  81. u32 micb1_mv;
  82. u32 micb2_mv;
  83. u32 micb3_mv;
  84. u32 micb4_mv;
  85. u8 bias1_cfilt_sel;
  86. };
  87. struct wcd938x_pdata {
  88. struct device_node *rst_np;
  89. struct device_node *rx_slave;
  90. struct device_node *tx_slave;
  91. struct wcd938x_micbias_setting micbias;
  92. struct cdc_regulator *regulator;
  93. int num_supplies;
  94. };
  95. struct wcd_ctrl_platform_data {
  96. void *handle;
  97. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  98. int (*register_notifier)(void *handle,
  99. struct notifier_block *nblock,
  100. bool enable);
  101. };
  102. enum {
  103. WCD_RX1,
  104. WCD_RX2,
  105. WCD_RX3
  106. };
  107. enum {
  108. BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
  109. BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
  110. BOLERO_WCD_EVT_SSR_DOWN,
  111. BOLERO_WCD_EVT_SSR_UP,
  112. BOLERO_WCD_EVT_CLK_NOTIFY,
  113. };
  114. enum {
  115. WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
  116. WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
  117. WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
  118. };
  119. enum {
  120. /* INTR_CTRL_INT_MASK_0 */
  121. WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
  122. WCD938X_IRQ_MBHC_BUTTON_PRESS_DET,
  123. WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
  124. WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  125. WCD938X_IRQ_MBHC_SW_DET,
  126. WCD938X_IRQ_HPHR_OCP_INT,
  127. WCD938X_IRQ_HPHR_CNP_INT,
  128. WCD938X_IRQ_HPHL_OCP_INT,
  129. /* INTR_CTRL_INT_MASK_1 */
  130. WCD938X_IRQ_HPHL_CNP_INT,
  131. WCD938X_IRQ_EAR_CNP_INT,
  132. WCD938X_IRQ_EAR_SCD_INT,
  133. WCD938X_IRQ_AUX_CNP_INT,
  134. WCD938X_IRQ_AUX_SCD_INT,
  135. WCD938X_IRQ_HPHL_PDM_WD_INT,
  136. WCD938X_IRQ_HPHR_PDM_WD_INT,
  137. WCD938X_IRQ_AUX_PDM_WD_INT,
  138. /* INTR_CTRL_INT_MASK_2 */
  139. WCD938X_IRQ_LDORT_SCD_INT,
  140. WCD938X_IRQ_MBHC_MOISTURE_INT,
  141. WCD938X_IRQ_HPHL_SURGE_DET_INT,
  142. WCD938X_IRQ_HPHR_SURGE_DET_INT,
  143. WCD938X_NUM_IRQS,
  144. };
  145. extern struct wcd938x_mbhc *wcd938x_soc_get_mbhc(
  146. struct snd_soc_component *component);
  147. extern int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  148. int volt, int micb_num);
  149. extern int wcd938x_get_micb_vout_ctl_val(u32 micb_mv);
  150. extern int wcd938x_micbias_control(struct snd_soc_component *component,
  151. int micb_num, int req, bool is_dapm);
  152. extern int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  153. struct snd_soc_component *component);
  154. #endif /* _WCD938X_INTERNAL_H */