dsi_phy_hw.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DSI_PHY_HW_H_
  6. #define _DSI_PHY_HW_H_
  7. #include "dsi_defs.h"
  8. #include "dsi_hw.h"
  9. #define DSI_MAX_SETTINGS 8
  10. #define DSI_PHY_TIMING_V3_SIZE 12
  11. #define DSI_PHY_TIMING_V4_SIZE 14
  12. #define DSI_PHY_DBG(p, fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: DSI_%d: "\
  13. fmt, p ? p->index : -1, ##__VA_ARGS__)
  14. #define DSI_PHY_ERR(p, fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: DSI_%d: "\
  15. fmt, p ? p->index : -1, ##__VA_ARGS__)
  16. #define DSI_PHY_INFO(p, fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: DSI_%d: "\
  17. fmt, p ? p->index : -1, ##__VA_ARGS__)
  18. #define DSI_PHY_WARN(p, fmt, ...) DRM_WARN("[msm-dsi-warn]: DSI_%d: " fmt,\
  19. p ? p->index : -1, ##__VA_ARGS__)
  20. #define DSI_MISC_R32(dsi_phy_hw, off) DSI_GEN_R32((dsi_phy_hw)->phy_clamp_base, off)
  21. #define DSI_MISC_W32(dsi_phy_hw, off, val) \
  22. DSI_GEN_W32_DEBUG((dsi_phy_hw)->phy_clamp_base, (dsi_phy_hw)->index, off, val)
  23. /**
  24. * enum dsi_phy_version - DSI PHY version enumeration
  25. * @DSI_PHY_VERSION_UNKNOWN: Unknown version.
  26. * @DSI_PHY_VERSION_3_0: 10nm
  27. * @DSI_PHY_VERSION_4_0: 7nm
  28. * @DSI_PHY_VERSION_4_1: 7nm
  29. * @DSI_PHY_VERSION_4_2: 5nm
  30. * @DSI_PHY_VERSION_4_3: 5nm
  31. * @DSI_PHY_VERSION_5_2: 4nm
  32. * @DSI_PHY_VERSION_MAX:
  33. */
  34. enum dsi_phy_version {
  35. DSI_PHY_VERSION_UNKNOWN,
  36. DSI_PHY_VERSION_3_0, /* 10nm */
  37. DSI_PHY_VERSION_4_0, /* 7nm */
  38. DSI_PHY_VERSION_4_1, /* 7nm */
  39. DSI_PHY_VERSION_4_2, /* 5nm */
  40. DSI_PHY_VERSION_4_3, /* 5nm */
  41. DSI_PHY_VERSION_5_2, /* 4nm */
  42. DSI_PHY_VERSION_MAX
  43. };
  44. /**
  45. * enum dsi_pll_version - DSI PHY PLL version enumeration
  46. * @DSI_PLL_VERSION_5NM: 5nm PLL
  47. * @DSI_PLL_VERSION_10NM: 10nm PLL
  48. * @DSI_PLL_VERSION_UNKNOWN: Unknown PLL version
  49. */
  50. enum dsi_pll_version {
  51. DSI_PLL_VERSION_5NM,
  52. DSI_PLL_VERSION_10NM,
  53. DSI_PLL_VERSION_UNKNOWN
  54. };
  55. /**
  56. * enum dsi_phy_hw_features - features supported by DSI PHY hardware
  57. * @DSI_PHY_DPHY: Supports DPHY
  58. * @DSI_PHY_CPHY: Supports CPHY
  59. * @DSI_PHY_SPLIT_LINK: Supports Split Link
  60. * @DSI_PHY_MAX_FEATURES:
  61. */
  62. enum dsi_phy_hw_features {
  63. DSI_PHY_DPHY,
  64. DSI_PHY_CPHY,
  65. DSI_PHY_SPLIT_LINK,
  66. DSI_PHY_MAX_FEATURES
  67. };
  68. /**
  69. * enum dsi_phy_pll_source - pll clock source for PHY.
  70. * @DSI_PLL_SOURCE_STANDALONE: Clock is sourced from native PLL and is not
  71. * shared by other PHYs.
  72. * @DSI_PLL_SOURCE_NATIVE: Clock is sourced from native PLL and is
  73. * shared by other PHYs.
  74. * @DSI_PLL_SOURCE_NON_NATIVE: Clock is sourced from other PHYs.
  75. * @DSI_PLL_SOURCE_MAX:
  76. */
  77. enum dsi_phy_pll_source {
  78. DSI_PLL_SOURCE_STANDALONE = 0,
  79. DSI_PLL_SOURCE_NATIVE,
  80. DSI_PLL_SOURCE_NON_NATIVE,
  81. DSI_PLL_SOURCE_MAX
  82. };
  83. /**
  84. * struct dsi_phy_per_lane_cfgs - Holds register values for PHY parameters
  85. * @lane: A set of maximum 8 values for each lane.
  86. * @lane_v3: A set of maximum 12 values for each lane.
  87. * @count_per_lane: Number of values per each lane.
  88. */
  89. struct dsi_phy_per_lane_cfgs {
  90. u8 lane[DSI_LANE_MAX][DSI_MAX_SETTINGS];
  91. u8 lane_v3[DSI_PHY_TIMING_V3_SIZE];
  92. u8 lane_v4[DSI_PHY_TIMING_V4_SIZE];
  93. u32 count_per_lane;
  94. };
  95. /**
  96. * struct dsi_phy_cfg - DSI PHY configuration
  97. * @lanecfg: Lane configuration settings.
  98. * @strength: Strength settings for lanes.
  99. * @timing: Timing parameters for lanes.
  100. * @is_phy_timing_present: Boolean whether phy timings are defined.
  101. * @regulators: Regulator settings for lanes.
  102. * @pll_source: PLL source.
  103. * @lane_map: DSI logical to PHY lane mapping.
  104. * @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.
  105. * @phy_type: Phy-type (Dphy/Cphy).
  106. * @bit_clk_rate_hz: DSI bit clk rate in HZ.
  107. * @split_link: DSI split link config data.
  108. */
  109. struct dsi_phy_cfg {
  110. struct dsi_phy_per_lane_cfgs lanecfg;
  111. struct dsi_phy_per_lane_cfgs strength;
  112. struct dsi_phy_per_lane_cfgs timing;
  113. bool is_phy_timing_present;
  114. struct dsi_phy_per_lane_cfgs regulators;
  115. enum dsi_phy_pll_source pll_source;
  116. struct dsi_lane_map lane_map;
  117. bool force_clk_lane_hs;
  118. enum dsi_phy_type phy_type;
  119. unsigned long bit_clk_rate_hz;
  120. struct dsi_split_link_config split_link;
  121. };
  122. struct dsi_phy_hw;
  123. struct phy_ulps_config_ops {
  124. /**
  125. * wait_for_lane_idle() - wait for DSI lanes to go to idle state
  126. * @phy: Pointer to DSI PHY hardware instance.
  127. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  128. * to be checked to be in idle state.
  129. */
  130. int (*wait_for_lane_idle)(struct dsi_phy_hw *phy, u32 lanes);
  131. /**
  132. * ulps_request() - request ulps entry for specified lanes
  133. * @phy: Pointer to DSI PHY hardware instance.
  134. * @cfg: Per lane configurations for timing, strength and lane
  135. * configurations.
  136. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  137. * to enter ULPS.
  138. *
  139. * Caller should check if lanes are in ULPS mode by calling
  140. * get_lanes_in_ulps() operation.
  141. */
  142. void (*ulps_request)(struct dsi_phy_hw *phy,
  143. struct dsi_phy_cfg *cfg, u32 lanes);
  144. /**
  145. * ulps_exit() - exit ULPS on specified lanes
  146. * @phy: Pointer to DSI PHY hardware instance.
  147. * @cfg: Per lane configurations for timing, strength and lane
  148. * configurations.
  149. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  150. * to exit ULPS.
  151. *
  152. * Caller should check if lanes are in active mode by calling
  153. * get_lanes_in_ulps() operation.
  154. */
  155. void (*ulps_exit)(struct dsi_phy_hw *phy,
  156. struct dsi_phy_cfg *cfg, u32 lanes);
  157. /**
  158. * get_lanes_in_ulps() - returns the list of lanes in ULPS mode
  159. * @phy: Pointer to DSI PHY hardware instance.
  160. *
  161. * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
  162. * state.
  163. *
  164. * Return: List of lanes in ULPS state.
  165. */
  166. u32 (*get_lanes_in_ulps)(struct dsi_phy_hw *phy);
  167. /**
  168. * is_lanes_in_ulps() - checks if the given lanes are in ulps
  169. * @lanes: lanes to be checked.
  170. * @ulps_lanes: lanes in ulps currenly.
  171. *
  172. * Return: true if all the given lanes are in ulps; false otherwise.
  173. */
  174. bool (*is_lanes_in_ulps)(u32 ulps, u32 ulps_lanes);
  175. };
  176. struct phy_dyn_refresh_ops {
  177. /**
  178. * dyn_refresh_helper - helper function to config particular registers
  179. * @phy: Pointer to DSI PHY hardware instance.
  180. * @offset: register offset to program.
  181. */
  182. void (*dyn_refresh_helper)(struct dsi_phy_hw *phy, u32 offset);
  183. /**
  184. * dyn_refresh_trigger_sel - configure trigger_sel to frame flush
  185. * @phy: Pointer to DSI PHY hardware instance.
  186. * @is_master: Boolean to indicate whether master or slave.
  187. */
  188. void (*dyn_refresh_trigger_sel)(struct dsi_phy_hw *phy,
  189. bool is_master);
  190. /**
  191. * dyn_refresh_config - configure dynamic refresh ctrl registers
  192. * @phy: Pointer to DSI PHY hardware instance.
  193. * @cfg: Pointer to DSI PHY timings.
  194. * @is_master: Boolean to indicate whether for master or slave.
  195. */
  196. void (*dyn_refresh_config)(struct dsi_phy_hw *phy,
  197. struct dsi_phy_cfg *cfg, bool is_master);
  198. /**
  199. * dyn_refresh_pipe_delay - configure pipe delay registers for dynamic
  200. * refresh.
  201. * @phy: Pointer to DSI PHY hardware instance.
  202. * @delay: structure containing all the delays to be programed.
  203. */
  204. void (*dyn_refresh_pipe_delay)(struct dsi_phy_hw *phy,
  205. struct dsi_dyn_clk_delay *delay);
  206. /**
  207. * cache_phy_timings - cache the phy timings calculated as part of
  208. * dynamic refresh.
  209. * @timings: Pointer to calculated phy timing parameters.
  210. * @dst: Pointer to cache location.
  211. * @size: Number of phy lane settings.
  212. */
  213. int (*cache_phy_timings)(struct dsi_phy_per_lane_cfgs *timings,
  214. u32 *dst, u32 size);
  215. };
  216. /**
  217. * struct dsi_phy_hw_ops - Operations for DSI PHY hardware.
  218. * @regulator_enable: Enable PHY regulators.
  219. * @regulator_disable: Disable PHY regulators.
  220. * @enable: Enable PHY.
  221. * @disable: Disable PHY.
  222. * @calculate_timing_params: Calculate PHY timing params from mode information
  223. */
  224. struct dsi_phy_hw_ops {
  225. /**
  226. * regulator_enable() - enable regulators for DSI PHY
  227. * @phy: Pointer to DSI PHY hardware object.
  228. * @reg_cfg: Regulator configuration for all DSI lanes.
  229. */
  230. void (*regulator_enable)(struct dsi_phy_hw *phy,
  231. struct dsi_phy_per_lane_cfgs *reg_cfg);
  232. /**
  233. * regulator_disable() - disable regulators
  234. * @phy: Pointer to DSI PHY hardware object.
  235. */
  236. void (*regulator_disable)(struct dsi_phy_hw *phy);
  237. /**
  238. * enable() - Enable PHY hardware
  239. * @phy: Pointer to DSI PHY hardware object.
  240. * @cfg: Per lane configurations for timing, strength and lane
  241. * configurations.
  242. */
  243. void (*enable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  244. /**
  245. * disable() - Disable PHY hardware
  246. * @phy: Pointer to DSI PHY hardware object.
  247. * @cfg: Per lane configurations for timing, strength and lane
  248. * configurations.
  249. */
  250. void (*disable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  251. /**
  252. * phy_idle_on() - Enable PHY hardware when entering idle screen
  253. * @phy: Pointer to DSI PHY hardware object.
  254. * @cfg: Per lane configurations for timing, strength and lane
  255. * configurations.
  256. */
  257. void (*phy_idle_on)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  258. /**
  259. * phy_idle_off() - Disable PHY hardware when exiting idle screen
  260. * @phy: Pointer to DSI PHY hardware object.
  261. */
  262. void (*phy_idle_off)(struct dsi_phy_hw *phy);
  263. /**
  264. * calculate_timing_params() - calculates timing parameters.
  265. * @phy: Pointer to DSI PHY hardware object.
  266. * @mode: Mode information for which timing has to be calculated.
  267. * @config: DSI host configuration for this mode.
  268. * @timing: Timing parameters for each lane which will be returned.
  269. * @use_mode_bit_clk: Boolean to indicate whether reacalculate dsi
  270. * bitclk or use the existing bitclk(for dynamic clk case).
  271. */
  272. int (*calculate_timing_params)(struct dsi_phy_hw *phy,
  273. struct dsi_mode_info *mode,
  274. struct dsi_host_common_cfg *config,
  275. struct dsi_phy_per_lane_cfgs *timing,
  276. bool use_mode_bit_clk);
  277. /**
  278. * phy_timing_val() - Gets PHY timing values.
  279. * @timing_val: Timing parameters for each lane which will be returned.
  280. * @timing: Array containing PHY timing values
  281. * @size: Size of the array
  282. */
  283. int (*phy_timing_val)(struct dsi_phy_per_lane_cfgs *timing_val,
  284. u32 *timing, u32 size);
  285. /**
  286. * clamp_ctrl() - configure clamps for DSI lanes
  287. * @phy: DSI PHY handle.
  288. * @enable: boolean to specify clamp enable/disable.
  289. * Return: error code.
  290. */
  291. void (*clamp_ctrl)(struct dsi_phy_hw *phy, bool enable);
  292. /**
  293. * phy_lane_reset() - Reset dsi phy lanes in case of error.
  294. * @phy: Pointer to DSI PHY hardware object.
  295. * Return: error code.
  296. */
  297. int (*phy_lane_reset)(struct dsi_phy_hw *phy);
  298. /**
  299. * toggle_resync_fifo() - toggle resync retime FIFO to sync data paths
  300. * @phy: Pointer to DSI PHY hardware object.
  301. * Return: error code.
  302. */
  303. void (*toggle_resync_fifo)(struct dsi_phy_hw *phy);
  304. /**
  305. * reset_clk_en_sel() - reset clk_en_sel on phy cmn_clk_cfg1 register
  306. * @phy: Pointer to DSI PHY hardware object.
  307. */
  308. void (*reset_clk_en_sel)(struct dsi_phy_hw *phy);
  309. /**
  310. * set_continuous_clk() - Set continuous clock
  311. * @phy: Pointer to DSI PHY hardware object
  312. * @enable: Bool to control continuous clock request.
  313. */
  314. void (*set_continuous_clk)(struct dsi_phy_hw *phy, bool enable);
  315. /**
  316. * commit_phy_timing() - Commit PHY timing
  317. * @phy: Pointer to DSI PHY hardware object.
  318. * @timing: Pointer to PHY timing array
  319. */
  320. void (*commit_phy_timing)(struct dsi_phy_hw *phy,
  321. struct dsi_phy_per_lane_cfgs *timing);
  322. void *timing_ops;
  323. struct phy_ulps_config_ops ulps_ops;
  324. struct phy_dyn_refresh_ops dyn_refresh_ops;
  325. /**
  326. * configure() - Configure the DSI PHY PLL
  327. * @pll: Pointer to DSI PLL.
  328. * @commit: boolean to specify if calculated PHY configuration
  329. needs to be committed. Set to false in case of
  330. dynamic clock switch.
  331. */
  332. int (*configure)(void *pll, bool commit);
  333. /**
  334. * pll_toggle() - Toggle the DSI PHY PLL
  335. * @pll: Pointer to DSI PLL.
  336. * @prepare: specify if PLL needs to be turned on or off.
  337. */
  338. int (*pll_toggle)(void *pll, bool prepare);
  339. };
  340. /**
  341. * struct dsi_phy_hw - DSI phy hardware object specific to an instance
  342. * @base: VA for the DSI PHY base address.
  343. * @length: Length of the DSI PHY register base map.
  344. * @dyn_pll_base: VA for the DSI dynamic refresh base address.
  345. * @length: Length of the DSI dynamic refresh register base map.
  346. * @index: Instance ID of the controller.
  347. * @version: DSI PHY version.
  348. * @phy_clamp_base: Base address of phy clamp register map.
  349. * @feature_map: Features supported by DSI PHY.
  350. * @ops: Function pointer to PHY operations.
  351. */
  352. struct dsi_phy_hw {
  353. void __iomem *base;
  354. u32 length;
  355. void __iomem *dyn_pll_base;
  356. u32 dyn_refresh_len;
  357. u32 index;
  358. enum dsi_phy_version version;
  359. void __iomem *phy_clamp_base;
  360. DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES);
  361. struct dsi_phy_hw_ops ops;
  362. };
  363. /**
  364. * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane
  365. * @lane_map: logical lane
  366. * @phy_lane: physical lane
  367. *
  368. * Return: Error code on failure. Lane number on success.
  369. */
  370. int dsi_phy_conv_phy_to_logical_lane(
  371. struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane);
  372. /**
  373. * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane
  374. * @lane_map: physical lane
  375. * @lane: logical lane
  376. *
  377. * Return: Error code on failure. Lane number on success.
  378. */
  379. int dsi_phy_conv_logical_to_phy_lane(
  380. struct dsi_lane_map *lane_map, enum dsi_logical_lane lane);
  381. #endif /* _DSI_PHY_HW_H_ */