dsi_catalog.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/errno.h>
  6. #include "dsi_catalog.h"
  7. /**
  8. * dsi_catalog_cmn_init() - catalog init for dsi controller v1.4
  9. */
  10. static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,
  11. enum dsi_ctrl_version version)
  12. {
  13. /* common functions */
  14. ctrl->ops.host_setup = dsi_ctrl_hw_cmn_host_setup;
  15. ctrl->ops.video_engine_en = dsi_ctrl_hw_cmn_video_engine_en;
  16. ctrl->ops.video_engine_setup = dsi_ctrl_hw_cmn_video_engine_setup;
  17. ctrl->ops.set_video_timing = dsi_ctrl_hw_cmn_set_video_timing;
  18. ctrl->ops.set_timing_db = dsi_ctrl_hw_cmn_set_timing_db;
  19. ctrl->ops.cmd_engine_setup = dsi_ctrl_hw_cmn_cmd_engine_setup;
  20. ctrl->ops.setup_cmd_stream = dsi_ctrl_hw_cmn_setup_cmd_stream;
  21. ctrl->ops.ctrl_en = dsi_ctrl_hw_cmn_ctrl_en;
  22. ctrl->ops.cmd_engine_en = dsi_ctrl_hw_cmn_cmd_engine_en;
  23. ctrl->ops.phy_sw_reset = dsi_ctrl_hw_cmn_phy_sw_reset;
  24. ctrl->ops.soft_reset = dsi_ctrl_hw_cmn_soft_reset;
  25. ctrl->ops.kickoff_command = dsi_ctrl_hw_cmn_kickoff_command;
  26. ctrl->ops.kickoff_fifo_command = dsi_ctrl_hw_cmn_kickoff_fifo_command;
  27. ctrl->ops.reset_cmd_fifo = dsi_ctrl_hw_cmn_reset_cmd_fifo;
  28. ctrl->ops.trigger_command_dma = dsi_ctrl_hw_cmn_trigger_command_dma;
  29. ctrl->ops.get_interrupt_status = dsi_ctrl_hw_cmn_get_interrupt_status;
  30. ctrl->ops.poll_dma_status = dsi_ctrl_hw_cmn_poll_dma_status;
  31. ctrl->ops.get_error_status = dsi_ctrl_hw_cmn_get_error_status;
  32. ctrl->ops.clear_error_status = dsi_ctrl_hw_cmn_clear_error_status;
  33. ctrl->ops.clear_interrupt_status =
  34. dsi_ctrl_hw_cmn_clear_interrupt_status;
  35. ctrl->ops.enable_status_interrupts =
  36. dsi_ctrl_hw_cmn_enable_status_interrupts;
  37. ctrl->ops.enable_error_interrupts =
  38. dsi_ctrl_hw_cmn_enable_error_interrupts;
  39. ctrl->ops.video_test_pattern_setup =
  40. dsi_ctrl_hw_cmn_video_test_pattern_setup;
  41. ctrl->ops.cmd_test_pattern_setup =
  42. dsi_ctrl_hw_cmn_cmd_test_pattern_setup;
  43. ctrl->ops.test_pattern_enable = dsi_ctrl_hw_cmn_test_pattern_enable;
  44. ctrl->ops.trigger_cmd_test_pattern =
  45. dsi_ctrl_hw_cmn_trigger_cmd_test_pattern;
  46. ctrl->ops.clear_phy0_ln_err = dsi_ctrl_hw_dln0_phy_err;
  47. ctrl->ops.phy_reset_config = dsi_ctrl_hw_cmn_phy_reset_config;
  48. ctrl->ops.setup_misr = dsi_ctrl_hw_cmn_setup_misr;
  49. ctrl->ops.collect_misr = dsi_ctrl_hw_cmn_collect_misr;
  50. ctrl->ops.get_cmd_read_data = dsi_ctrl_hw_cmn_get_cmd_read_data;
  51. ctrl->ops.clear_rdbk_register = dsi_ctrl_hw_cmn_clear_rdbk_reg;
  52. ctrl->ops.ctrl_reset = dsi_ctrl_hw_cmn_ctrl_reset;
  53. ctrl->ops.mask_error_intr = dsi_ctrl_hw_cmn_mask_error_intr;
  54. ctrl->ops.error_intr_ctrl = dsi_ctrl_hw_cmn_error_intr_ctrl;
  55. ctrl->ops.get_error_mask = dsi_ctrl_hw_cmn_get_error_mask;
  56. ctrl->ops.get_hw_version = dsi_ctrl_hw_cmn_get_hw_version;
  57. ctrl->ops.wait_for_cmd_mode_mdp_idle =
  58. dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle;
  59. ctrl->ops.setup_avr = dsi_ctrl_hw_cmn_setup_avr;
  60. ctrl->ops.set_continuous_clk = dsi_ctrl_hw_cmn_set_continuous_clk;
  61. ctrl->ops.wait4dynamic_refresh_done =
  62. dsi_ctrl_hw_cmn_wait4dynamic_refresh_done;
  63. ctrl->ops.hs_req_sel = dsi_ctrl_hw_cmn_hs_req_sel;
  64. ctrl->ops.vid_engine_busy = dsi_ctrl_hw_cmn_vid_engine_busy;
  65. switch (version) {
  66. case DSI_CTRL_VERSION_2_2:
  67. case DSI_CTRL_VERSION_2_3:
  68. case DSI_CTRL_VERSION_2_4:
  69. case DSI_CTRL_VERSION_2_5:
  70. case DSI_CTRL_VERSION_2_6:
  71. case DSI_CTRL_VERSION_2_7:
  72. ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config;
  73. ctrl->ops.config_clk_gating = dsi_ctrl_hw_22_config_clk_gating;
  74. ctrl->ops.setup_lane_map = dsi_ctrl_hw_22_setup_lane_map;
  75. ctrl->ops.wait_for_lane_idle =
  76. dsi_ctrl_hw_22_wait_for_lane_idle;
  77. ctrl->ops.reg_dump_to_buffer =
  78. dsi_ctrl_hw_22_reg_dump_to_buffer;
  79. ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_cmn_ulps_request;
  80. ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_cmn_ulps_exit;
  81. ctrl->ops.ulps_ops.get_lanes_in_ulps =
  82. dsi_ctrl_hw_cmn_get_lanes_in_ulps;
  83. ctrl->ops.clamp_enable = NULL;
  84. ctrl->ops.clamp_disable = NULL;
  85. ctrl->ops.schedule_dma_cmd = dsi_ctrl_hw_22_schedule_dma_cmd;
  86. ctrl->ops.kickoff_command_non_embedded_mode =
  87. dsi_ctrl_hw_kickoff_non_embedded_mode;
  88. ctrl->ops.configure_cmddma_window =
  89. dsi_ctrl_hw_22_configure_cmddma_window;
  90. ctrl->ops.reset_trig_ctrl =
  91. dsi_ctrl_hw_22_reset_trigger_controls;
  92. ctrl->ops.log_line_count = dsi_ctrl_hw_22_log_line_count;
  93. ctrl->ops.splitlink_cmd_setup = dsi_ctrl_hw_22_configure_splitlink;
  94. break;
  95. default:
  96. break;
  97. }
  98. }
  99. /**
  100. * dsi_catalog_ctrl_setup() - return catalog info for dsi controller
  101. * @ctrl: Pointer to DSI controller hw object.
  102. * @version: DSI controller version.
  103. * @index: DSI controller instance ID.
  104. * @phy_isolation_enabled: DSI controller works isolated from phy.
  105. * @null_insertion_enabled: DSI controller inserts null packet.
  106. *
  107. * This function setups the catalog information in the dsi_ctrl_hw object.
  108. *
  109. * return: error code for failure and 0 for success.
  110. */
  111. int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
  112. enum dsi_ctrl_version version, u32 index,
  113. bool phy_isolation_enabled, bool null_insertion_enabled)
  114. {
  115. int rc = 0;
  116. if (version == DSI_CTRL_VERSION_UNKNOWN ||
  117. version >= DSI_CTRL_VERSION_MAX) {
  118. DSI_ERR("Unsupported version: %d\n", version);
  119. return -ENOTSUPP;
  120. }
  121. ctrl->index = index;
  122. ctrl->null_insertion_enabled = null_insertion_enabled;
  123. set_bit(DSI_CTRL_VIDEO_TPG, ctrl->feature_map);
  124. set_bit(DSI_CTRL_CMD_TPG, ctrl->feature_map);
  125. set_bit(DSI_CTRL_VARIABLE_REFRESH_RATE, ctrl->feature_map);
  126. set_bit(DSI_CTRL_DYNAMIC_REFRESH, ctrl->feature_map);
  127. set_bit(DSI_CTRL_DESKEW_CALIB, ctrl->feature_map);
  128. set_bit(DSI_CTRL_DPHY, ctrl->feature_map);
  129. switch (version) {
  130. case DSI_CTRL_VERSION_2_2:
  131. case DSI_CTRL_VERSION_2_3:
  132. case DSI_CTRL_VERSION_2_4:
  133. ctrl->phy_isolation_enabled = phy_isolation_enabled;
  134. dsi_catalog_cmn_init(ctrl, version);
  135. break;
  136. case DSI_CTRL_VERSION_2_5:
  137. case DSI_CTRL_VERSION_2_6:
  138. case DSI_CTRL_VERSION_2_7:
  139. ctrl->widebus_support = true;
  140. ctrl->phy_isolation_enabled = phy_isolation_enabled;
  141. dsi_catalog_cmn_init(ctrl, version);
  142. break;
  143. default:
  144. return -ENOTSUPP;
  145. }
  146. return rc;
  147. }
  148. /**
  149. * dsi_catalog_phy_3_0_init() - catalog init for DSI PHY 10nm
  150. */
  151. static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy)
  152. {
  153. phy->ops.regulator_enable = dsi_phy_hw_v3_0_regulator_enable;
  154. phy->ops.regulator_disable = dsi_phy_hw_v3_0_regulator_disable;
  155. phy->ops.enable = dsi_phy_hw_v3_0_enable;
  156. phy->ops.disable = dsi_phy_hw_v3_0_disable;
  157. phy->ops.calculate_timing_params =
  158. dsi_phy_hw_calculate_timing_params;
  159. phy->ops.ulps_ops.wait_for_lane_idle =
  160. dsi_phy_hw_v3_0_wait_for_lane_idle;
  161. phy->ops.ulps_ops.ulps_request =
  162. dsi_phy_hw_v3_0_ulps_request;
  163. phy->ops.ulps_ops.ulps_exit =
  164. dsi_phy_hw_v3_0_ulps_exit;
  165. phy->ops.ulps_ops.get_lanes_in_ulps =
  166. dsi_phy_hw_v3_0_get_lanes_in_ulps;
  167. phy->ops.ulps_ops.is_lanes_in_ulps =
  168. dsi_phy_hw_v3_0_is_lanes_in_ulps;
  169. phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0;
  170. phy->ops.clamp_ctrl = dsi_phy_hw_v3_0_clamp_ctrl;
  171. phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;
  172. phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;
  173. phy->ops.dyn_refresh_ops.dyn_refresh_config =
  174. dsi_phy_hw_v3_0_dyn_refresh_config;
  175. phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay =
  176. dsi_phy_hw_v3_0_dyn_refresh_pipe_delay;
  177. phy->ops.dyn_refresh_ops.dyn_refresh_helper =
  178. dsi_phy_hw_v3_0_dyn_refresh_helper;
  179. phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel = NULL;
  180. phy->ops.dyn_refresh_ops.cache_phy_timings =
  181. dsi_phy_hw_v3_0_cache_phy_timings;
  182. }
  183. /**
  184. * dsi_catalog_phy_4_0_init() - catalog init for DSI PHY 7nm
  185. */
  186. static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
  187. {
  188. phy->ops.regulator_enable = NULL;
  189. phy->ops.regulator_disable = NULL;
  190. phy->ops.enable = dsi_phy_hw_v4_0_enable;
  191. phy->ops.disable = dsi_phy_hw_v4_0_disable;
  192. phy->ops.calculate_timing_params =
  193. dsi_phy_hw_calculate_timing_params;
  194. phy->ops.ulps_ops.wait_for_lane_idle =
  195. dsi_phy_hw_v4_0_wait_for_lane_idle;
  196. phy->ops.ulps_ops.ulps_request =
  197. dsi_phy_hw_v4_0_ulps_request;
  198. phy->ops.ulps_ops.ulps_exit =
  199. dsi_phy_hw_v4_0_ulps_exit;
  200. phy->ops.ulps_ops.get_lanes_in_ulps =
  201. dsi_phy_hw_v4_0_get_lanes_in_ulps;
  202. phy->ops.ulps_ops.is_lanes_in_ulps =
  203. dsi_phy_hw_v4_0_is_lanes_in_ulps;
  204. phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v4_0;
  205. phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;
  206. phy->ops.toggle_resync_fifo = dsi_phy_hw_v4_0_toggle_resync_fifo;
  207. phy->ops.reset_clk_en_sel = dsi_phy_hw_v4_0_reset_clk_en_sel;
  208. phy->ops.dyn_refresh_ops.dyn_refresh_config =
  209. dsi_phy_hw_v4_0_dyn_refresh_config;
  210. phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay =
  211. dsi_phy_hw_v4_0_dyn_refresh_pipe_delay;
  212. phy->ops.dyn_refresh_ops.dyn_refresh_helper =
  213. dsi_phy_hw_v4_0_dyn_refresh_helper;
  214. phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel =
  215. dsi_phy_hw_v4_0_dyn_refresh_trigger_sel;
  216. phy->ops.dyn_refresh_ops.cache_phy_timings =
  217. dsi_phy_hw_v4_0_cache_phy_timings;
  218. phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk;
  219. phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing;
  220. }
  221. /**
  222. * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
  223. * @ctrl: Pointer to DSI PHY hw object.
  224. * @version: DSI PHY version.
  225. * @index: DSI PHY instance ID.
  226. *
  227. * This function setups the catalog information in the dsi_phy_hw object.
  228. *
  229. * return: error code for failure and 0 for success.
  230. */
  231. int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
  232. enum dsi_phy_version version,
  233. u32 index)
  234. {
  235. int rc = 0;
  236. if (version == DSI_PHY_VERSION_UNKNOWN ||
  237. version >= DSI_PHY_VERSION_MAX) {
  238. DSI_ERR("Unsupported version: %d\n", version);
  239. return -ENOTSUPP;
  240. }
  241. phy->index = index;
  242. phy->version = version;
  243. set_bit(DSI_PHY_DPHY, phy->feature_map);
  244. dsi_phy_timing_calc_init(phy, version);
  245. switch (version) {
  246. case DSI_PHY_VERSION_3_0:
  247. dsi_catalog_phy_3_0_init(phy);
  248. break;
  249. case DSI_PHY_VERSION_4_0:
  250. case DSI_PHY_VERSION_4_1:
  251. case DSI_PHY_VERSION_4_2:
  252. case DSI_PHY_VERSION_4_3:
  253. case DSI_PHY_VERSION_5_2:
  254. dsi_catalog_phy_4_0_init(phy);
  255. break;
  256. default:
  257. return -ENOTSUPP;
  258. }
  259. return rc;
  260. }
  261. int dsi_catalog_phy_pll_setup(struct dsi_phy_hw *phy, u32 pll_ver)
  262. {
  263. int rc = 0;
  264. if (pll_ver >= DSI_PLL_VERSION_UNKNOWN) {
  265. DSI_ERR("Unsupported version: %d\n", pll_ver);
  266. return -EOPNOTSUPP;
  267. }
  268. switch (pll_ver) {
  269. case DSI_PLL_VERSION_5NM:
  270. phy->ops.configure = dsi_pll_5nm_configure;
  271. phy->ops.pll_toggle = dsi_pll_5nm_toggle;
  272. break;
  273. default:
  274. phy->ops.configure = NULL;
  275. phy->ops.pll_toggle = NULL;
  276. break;
  277. }
  278. return rc;
  279. }