msm_drv.h 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984
  1. /*
  2. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #ifndef __MSM_DRV_H__
  19. #define __MSM_DRV_H__
  20. #include <linux/kernel.h>
  21. #include <linux/clk.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/module.h>
  24. #include <linux/component.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pm.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/slab.h>
  29. #include <linux/list.h>
  30. #include <linux/iommu.h>
  31. #include <linux/types.h>
  32. #include <linux/of_graph.h>
  33. #include <linux/of_device.h>
  34. #include <linux/sde_io_util.h>
  35. #include <linux/sizes.h>
  36. #include <linux/kthread.h>
  37. #include <drm/drmP.h>
  38. #include <drm/drm_atomic.h>
  39. #include <drm/drm_atomic_helper.h>
  40. #include <drm/drm_plane_helper.h>
  41. #include <drm/drm_fb_helper.h>
  42. #include <drm/msm_drm.h>
  43. #include <drm/sde_drm.h>
  44. #include <drm/drm_gem.h>
  45. #include <drm/drm_dsc.h>
  46. #include "sde_power_handle.h"
  47. #define GET_MAJOR_REV(rev) ((rev) >> 28)
  48. #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF)
  49. #define GET_STEP_REV(rev) ((rev) & 0xFFFF)
  50. struct msm_kms;
  51. struct msm_gpu;
  52. struct msm_mmu;
  53. struct msm_mdss;
  54. struct msm_rd_state;
  55. struct msm_perf_state;
  56. struct msm_gem_submit;
  57. struct msm_fence_context;
  58. struct msm_fence_cb;
  59. struct msm_gem_address_space;
  60. struct msm_gem_vma;
  61. #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */
  62. #define MAX_CRTCS 16
  63. #define MAX_PLANES 20
  64. #define MAX_ENCODERS 16
  65. #define MAX_BRIDGES 16
  66. #define MAX_CONNECTORS 16
  67. #define TEARDOWN_DEADLOCK_RETRY_MAX 5
  68. struct msm_file_private {
  69. rwlock_t queuelock;
  70. struct list_head submitqueues;
  71. int queueid;
  72. /* update the refcount when user driver calls power_ctrl IOCTL */
  73. unsigned short enable_refcnt;
  74. /* protects enable_refcnt */
  75. struct mutex power_lock;
  76. };
  77. enum msm_mdp_plane_property {
  78. /* blob properties, always put these first */
  79. PLANE_PROP_CSC_V1,
  80. PLANE_PROP_CSC_DMA_V1,
  81. PLANE_PROP_INFO,
  82. PLANE_PROP_SCALER_LUT_ED,
  83. PLANE_PROP_SCALER_LUT_CIR,
  84. PLANE_PROP_SCALER_LUT_SEP,
  85. PLANE_PROP_SKIN_COLOR,
  86. PLANE_PROP_SKY_COLOR,
  87. PLANE_PROP_FOLIAGE_COLOR,
  88. PLANE_PROP_VIG_GAMUT,
  89. PLANE_PROP_VIG_IGC,
  90. PLANE_PROP_DMA_IGC,
  91. PLANE_PROP_DMA_GC,
  92. /* # of blob properties */
  93. PLANE_PROP_BLOBCOUNT,
  94. /* range properties */
  95. PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
  96. PLANE_PROP_ALPHA,
  97. PLANE_PROP_COLOR_FILL,
  98. PLANE_PROP_H_DECIMATE,
  99. PLANE_PROP_V_DECIMATE,
  100. PLANE_PROP_INPUT_FENCE,
  101. PLANE_PROP_HUE_ADJUST,
  102. PLANE_PROP_SATURATION_ADJUST,
  103. PLANE_PROP_VALUE_ADJUST,
  104. PLANE_PROP_CONTRAST_ADJUST,
  105. PLANE_PROP_EXCL_RECT_V1,
  106. PLANE_PROP_PREFILL_SIZE,
  107. PLANE_PROP_PREFILL_TIME,
  108. PLANE_PROP_SCALER_V1,
  109. PLANE_PROP_SCALER_V2,
  110. PLANE_PROP_INVERSE_PMA,
  111. /* enum/bitmask properties */
  112. PLANE_PROP_BLEND_OP,
  113. PLANE_PROP_SRC_CONFIG,
  114. PLANE_PROP_FB_TRANSLATION_MODE,
  115. PLANE_PROP_MULTIRECT_MODE,
  116. /* total # of properties */
  117. PLANE_PROP_COUNT
  118. };
  119. enum msm_mdp_crtc_property {
  120. CRTC_PROP_INFO,
  121. CRTC_PROP_DEST_SCALER_LUT_ED,
  122. CRTC_PROP_DEST_SCALER_LUT_CIR,
  123. CRTC_PROP_DEST_SCALER_LUT_SEP,
  124. /* # of blob properties */
  125. CRTC_PROP_BLOBCOUNT,
  126. /* range properties */
  127. CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
  128. CRTC_PROP_OUTPUT_FENCE,
  129. CRTC_PROP_OUTPUT_FENCE_OFFSET,
  130. CRTC_PROP_DIM_LAYER_V1,
  131. CRTC_PROP_CORE_CLK,
  132. CRTC_PROP_CORE_AB,
  133. CRTC_PROP_CORE_IB,
  134. CRTC_PROP_LLCC_AB,
  135. CRTC_PROP_LLCC_IB,
  136. CRTC_PROP_DRAM_AB,
  137. CRTC_PROP_DRAM_IB,
  138. CRTC_PROP_ROT_PREFILL_BW,
  139. CRTC_PROP_ROT_CLK,
  140. CRTC_PROP_ROI_V1,
  141. CRTC_PROP_SECURITY_LEVEL,
  142. CRTC_PROP_IDLE_TIMEOUT,
  143. CRTC_PROP_DEST_SCALER,
  144. CRTC_PROP_CAPTURE_OUTPUT,
  145. CRTC_PROP_IDLE_PC_STATE,
  146. /* total # of properties */
  147. CRTC_PROP_COUNT
  148. };
  149. enum msm_mdp_conn_property {
  150. /* blob properties, always put these first */
  151. CONNECTOR_PROP_SDE_INFO,
  152. CONNECTOR_PROP_MODE_INFO,
  153. CONNECTOR_PROP_HDR_INFO,
  154. CONNECTOR_PROP_EXT_HDR_INFO,
  155. CONNECTOR_PROP_PP_DITHER,
  156. CONNECTOR_PROP_HDR_METADATA,
  157. /* # of blob properties */
  158. CONNECTOR_PROP_BLOBCOUNT,
  159. /* range properties */
  160. CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
  161. CONNECTOR_PROP_RETIRE_FENCE,
  162. CONNECTOR_PROP_DST_X,
  163. CONNECTOR_PROP_DST_Y,
  164. CONNECTOR_PROP_DST_W,
  165. CONNECTOR_PROP_DST_H,
  166. CONNECTOR_PROP_ROI_V1,
  167. CONNECTOR_PROP_BL_SCALE,
  168. CONNECTOR_PROP_SV_BL_SCALE,
  169. CONNECTOR_PROP_SUPPORTED_COLORSPACES,
  170. /* enum/bitmask properties */
  171. CONNECTOR_PROP_TOPOLOGY_NAME,
  172. CONNECTOR_PROP_TOPOLOGY_CONTROL,
  173. CONNECTOR_PROP_AUTOREFRESH,
  174. CONNECTOR_PROP_LP,
  175. CONNECTOR_PROP_FB_TRANSLATION_MODE,
  176. CONNECTOR_PROP_QSYNC_MODE,
  177. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE,
  178. /* total # of properties */
  179. CONNECTOR_PROP_COUNT
  180. };
  181. #define MSM_GPU_MAX_RINGS 4
  182. #define MAX_H_TILES_PER_DISPLAY 2
  183. /**
  184. * enum msm_display_compression_type - compression method used for pixel stream
  185. * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed
  186. * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used
  187. */
  188. enum msm_display_compression_type {
  189. MSM_DISPLAY_COMPRESSION_NONE,
  190. MSM_DISPLAY_COMPRESSION_DSC,
  191. };
  192. /**
  193. * enum msm_display_compression_ratio - compression ratio
  194. * @MSM_DISPLAY_COMPRESSION_NONE: no compression
  195. * @MSM_DISPLAY_COMPRESSION_RATIO_2_TO_1: 2 to 1 compression
  196. * @MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1: 3 to 1 compression
  197. */
  198. enum msm_display_compression_ratio {
  199. MSM_DISPLAY_COMPRESSION_RATIO_NONE,
  200. MSM_DISPLAY_COMPRESSION_RATIO_2_TO_1,
  201. MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1,
  202. MSM_DISPLAY_COMPRESSION_RATIO_MAX,
  203. };
  204. /**
  205. * enum msm_display_caps - features/capabilities supported by displays
  206. * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
  207. * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
  208. * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
  209. * @MSM_DISPLAY_CAP_EDID: EDID supported
  210. * @MSM_DISPLAY_ESD_ENABLED: ESD feature enabled
  211. * @MSM_DISPLAY_CAP_MST_MODE: Display with MST support
  212. * @MSM_DISPLAY_SPLIT_LINK: Split Link enabled
  213. */
  214. enum msm_display_caps {
  215. MSM_DISPLAY_CAP_VID_MODE = BIT(0),
  216. MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
  217. MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
  218. MSM_DISPLAY_CAP_EDID = BIT(3),
  219. MSM_DISPLAY_ESD_ENABLED = BIT(4),
  220. MSM_DISPLAY_CAP_MST_MODE = BIT(5),
  221. MSM_DISPLAY_SPLIT_LINK = BIT(6),
  222. };
  223. /**
  224. * enum panel_mode - panel operation mode
  225. * @MSM_DISPLAY_VIDEO_MODE: video mode panel
  226. * @MSM_DISPLAY_CMD_MODE: Command mode panel
  227. * @MODE_MAX:
  228. */
  229. enum panel_op_mode {
  230. MSM_DISPLAY_VIDEO_MODE = 0,
  231. MSM_DISPLAY_CMD_MODE,
  232. MSM_DISPLAY_MODE_MAX,
  233. };
  234. /**
  235. * enum msm_event_wait - type of HW events to wait for
  236. * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  237. * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
  238. * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  239. * @MSM_ENC_ACTIVE_REGION - wait for the TG to be in active pixel region
  240. */
  241. enum msm_event_wait {
  242. MSM_ENC_COMMIT_DONE = 0,
  243. MSM_ENC_TX_COMPLETE,
  244. MSM_ENC_VBLANK,
  245. MSM_ENC_ACTIVE_REGION,
  246. };
  247. /**
  248. * struct msm_roi_alignment - region of interest alignment restrictions
  249. * @xstart_pix_align: left x offset alignment restriction
  250. * @width_pix_align: width alignment restriction
  251. * @ystart_pix_align: top y offset alignment restriction
  252. * @height_pix_align: height alignment restriction
  253. * @min_width: minimum width restriction
  254. * @min_height: minimum height restriction
  255. */
  256. struct msm_roi_alignment {
  257. uint32_t xstart_pix_align;
  258. uint32_t width_pix_align;
  259. uint32_t ystart_pix_align;
  260. uint32_t height_pix_align;
  261. uint32_t min_width;
  262. uint32_t min_height;
  263. };
  264. /**
  265. * struct msm_roi_caps - display's region of interest capabilities
  266. * @enabled: true if some region of interest is supported
  267. * @merge_rois: merge rois before sending to display
  268. * @num_roi: maximum number of rois supported
  269. * @align: roi alignment restrictions
  270. */
  271. struct msm_roi_caps {
  272. bool enabled;
  273. bool merge_rois;
  274. uint32_t num_roi;
  275. struct msm_roi_alignment align;
  276. };
  277. /**
  278. * struct msm_display_dsc_info - defines dsc configuration
  279. * @config DSC encoder configuration
  280. * @scr_rev: DSC revision.
  281. * @initial_lines: Number of initial lines stored in encoder.
  282. * @pkt_per_line: Number of packets per line.
  283. * @bytes_in_slice: Number of bytes in slice.
  284. * @eol_byte_num: Valid bytes at the end of line.
  285. * @bytes_per_pkt Number of bytes in DSI packet
  286. * @pclk_per_line: Compressed width.
  287. * @slice_last_group_size: Size of last group in pixels.
  288. * @slice_per_pkt: Number of slices per packet.
  289. * @det_thresh_flatness: Flatness threshold.
  290. * @extra_width: Extra width required in timing calculations.
  291. * @pps_delay_ms: Post PPS command delay in milliseconds.
  292. */
  293. struct msm_display_dsc_info {
  294. struct drm_dsc_config config;
  295. u8 scr_rev;
  296. int initial_lines;
  297. int pkt_per_line;
  298. int bytes_in_slice;
  299. int bytes_per_pkt;
  300. int eol_byte_num;
  301. int pclk_per_line;
  302. int slice_last_group_size;
  303. int slice_per_pkt;
  304. int det_thresh_flatness;
  305. u32 extra_width;
  306. u32 pps_delay_ms;
  307. };
  308. /**
  309. * Bits/pixel target >> 4 (removing the fractional bits)
  310. * returns the integer bpp value from the drm_dsc_config struct
  311. */
  312. #define DSC_BPP(config) ((config).bits_per_pixel >> 4)
  313. /**
  314. * struct msm_compression_info - defined panel compression
  315. * @comp_type: type of compression supported
  316. * @comp_ratio: compression ratio
  317. * @dsc_info: dsc configuration if the compression
  318. * supported is DSC
  319. */
  320. struct msm_compression_info {
  321. enum msm_display_compression_type comp_type;
  322. enum msm_display_compression_ratio comp_ratio;
  323. union{
  324. struct msm_display_dsc_info dsc_info;
  325. };
  326. };
  327. /**
  328. * struct msm_display_topology - defines a display topology pipeline
  329. * @num_lm: number of layer mixers used
  330. * @num_enc: number of compression encoder blocks used
  331. * @num_intf: number of interfaces the panel is mounted on
  332. */
  333. struct msm_display_topology {
  334. u32 num_lm;
  335. u32 num_enc;
  336. u32 num_intf;
  337. };
  338. /**
  339. * struct msm_mode_info - defines all msm custom mode info
  340. * @frame_rate: frame_rate of the mode
  341. * @vtotal: vtotal calculated for the mode
  342. * @prefill_lines: prefill lines based on porches.
  343. * @jitter_numer: display panel jitter numerator configuration
  344. * @jitter_denom: display panel jitter denominator configuration
  345. * @clk_rate: DSI bit clock per lane in HZ.
  346. * @topology: supported topology for the mode
  347. * @comp_info: compression info supported
  348. * @roi_caps: panel roi capabilities
  349. * @wide_bus_en: wide-bus mode cfg for interface module
  350. * @mdp_transfer_time_us Specifies the mdp transfer time for command mode
  351. * panels in microseconds.
  352. */
  353. struct msm_mode_info {
  354. uint32_t frame_rate;
  355. uint32_t vtotal;
  356. uint32_t prefill_lines;
  357. uint32_t jitter_numer;
  358. uint32_t jitter_denom;
  359. uint64_t clk_rate;
  360. struct msm_display_topology topology;
  361. struct msm_compression_info comp_info;
  362. struct msm_roi_caps roi_caps;
  363. bool wide_bus_en;
  364. u32 mdp_transfer_time_us;
  365. };
  366. /**
  367. * struct msm_resource_caps_info - defines hw resources
  368. * @num_lm number of layer mixers available
  369. * @num_dsc number of dsc available
  370. * @num_ctl number of ctl available
  371. * @num_3dmux number of 3d mux available
  372. * @max_mixer_width: max width supported by layer mixer
  373. */
  374. struct msm_resource_caps_info {
  375. uint32_t num_lm;
  376. uint32_t num_dsc;
  377. uint32_t num_ctl;
  378. uint32_t num_3dmux;
  379. uint32_t max_mixer_width;
  380. };
  381. /**
  382. * struct msm_display_info - defines display properties
  383. * @intf_type: DRM_MODE_CONNECTOR_ display type
  384. * @capabilities: Bitmask of display flags
  385. * @num_of_h_tiles: Number of horizontal tiles in case of split interface
  386. * @h_tile_instance: Controller instance used per tile. Number of elements is
  387. * based on num_of_h_tiles
  388. * @is_connected: Set to true if display is connected
  389. * @width_mm: Physical width
  390. * @height_mm: Physical height
  391. * @max_width: Max width of display. In case of hot pluggable display
  392. * this is max width supported by controller
  393. * @max_height: Max height of display. In case of hot pluggable display
  394. * this is max height supported by controller
  395. * @clk_rate: DSI bit clock per lane in HZ.
  396. * @display_type: Enum for type of display
  397. * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
  398. * used instead of panel TE in cmd mode panels
  399. * @roi_caps: Region of interest capability info
  400. * @qsync_min_fps Minimum fps supported by Qsync feature
  401. * @te_source vsync source pin information
  402. */
  403. struct msm_display_info {
  404. int intf_type;
  405. uint32_t capabilities;
  406. enum panel_op_mode curr_panel_mode;
  407. uint32_t num_of_h_tiles;
  408. uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
  409. bool is_connected;
  410. unsigned int width_mm;
  411. unsigned int height_mm;
  412. uint32_t max_width;
  413. uint32_t max_height;
  414. uint64_t clk_rate;
  415. uint32_t display_type;
  416. bool is_te_using_watchdog_timer;
  417. struct msm_roi_caps roi_caps;
  418. uint32_t qsync_min_fps;
  419. uint32_t te_source;
  420. };
  421. #define MSM_MAX_ROI 4
  422. /**
  423. * struct msm_roi_list - list of regions of interest for a drm object
  424. * @num_rects: number of valid rectangles in the roi array
  425. * @roi: list of roi rectangles
  426. */
  427. struct msm_roi_list {
  428. uint32_t num_rects;
  429. struct drm_clip_rect roi[MSM_MAX_ROI];
  430. };
  431. /**
  432. * struct - msm_display_kickoff_params - info for display features at kickoff
  433. * @rois: Regions of interest structure for mapping CRTC to Connector output
  434. */
  435. struct msm_display_kickoff_params {
  436. struct msm_roi_list *rois;
  437. struct drm_msm_ext_hdr_metadata *hdr_meta;
  438. };
  439. /**
  440. * struct - msm_display_conn_params - info of dpu display features
  441. * @qsync_mode: Qsync mode, where 0: disabled 1: continuous mode 2: oneshot
  442. * @qsync_update: Qsync settings were changed/updated
  443. */
  444. struct msm_display_conn_params {
  445. uint32_t qsync_mode;
  446. bool qsync_update;
  447. };
  448. /**
  449. * struct msm_drm_event - defines custom event notification struct
  450. * @base: base object required for event notification by DRM framework.
  451. * @event: event object required for event notification by DRM framework.
  452. * @info: contains information of DRM object for which events has been
  453. * requested.
  454. * @data: memory location which contains response payload for event.
  455. */
  456. struct msm_drm_event {
  457. struct drm_pending_event base;
  458. struct drm_event event;
  459. struct drm_msm_event_req info;
  460. u8 data[];
  461. };
  462. /* Commit/Event thread specific structure */
  463. struct msm_drm_thread {
  464. struct drm_device *dev;
  465. struct task_struct *thread;
  466. unsigned int crtc_id;
  467. struct kthread_worker worker;
  468. };
  469. struct msm_drm_private {
  470. struct drm_device *dev;
  471. struct msm_kms *kms;
  472. struct sde_power_handle phandle;
  473. /* subordinate devices, if present: */
  474. struct platform_device *gpu_pdev;
  475. /* top level MDSS wrapper device (for MDP5 only) */
  476. struct msm_mdss *mdss;
  477. /* possibly this should be in the kms component, but it is
  478. * shared by both mdp4 and mdp5..
  479. */
  480. struct hdmi *hdmi;
  481. /* eDP is for mdp5 only, but kms has not been created
  482. * when edp_bind() and edp_init() are called. Here is the only
  483. * place to keep the edp instance.
  484. */
  485. struct msm_edp *edp;
  486. /* DSI is shared by mdp4 and mdp5 */
  487. struct msm_dsi *dsi[2];
  488. /* when we have more than one 'msm_gpu' these need to be an array: */
  489. struct msm_gpu *gpu;
  490. struct msm_file_private *lastctx;
  491. struct drm_fb_helper *fbdev;
  492. struct msm_rd_state *rd; /* debugfs to dump all submits */
  493. struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
  494. struct msm_perf_state *perf;
  495. /* list of GEM objects: */
  496. struct list_head inactive_list;
  497. struct workqueue_struct *wq;
  498. /* crtcs pending async atomic updates: */
  499. uint32_t pending_crtcs;
  500. uint32_t pending_planes;
  501. wait_queue_head_t pending_crtcs_event;
  502. unsigned int num_planes;
  503. struct drm_plane *planes[MAX_PLANES];
  504. unsigned int num_crtcs;
  505. struct drm_crtc *crtcs[MAX_CRTCS];
  506. struct msm_drm_thread disp_thread[MAX_CRTCS];
  507. struct msm_drm_thread event_thread[MAX_CRTCS];
  508. struct task_struct *pp_event_thread;
  509. struct kthread_worker pp_event_worker;
  510. unsigned int num_encoders;
  511. struct drm_encoder *encoders[MAX_ENCODERS];
  512. unsigned int num_bridges;
  513. struct drm_bridge *bridges[MAX_BRIDGES];
  514. unsigned int num_connectors;
  515. struct drm_connector *connectors[MAX_CONNECTORS];
  516. /* Properties */
  517. struct drm_property *plane_property[PLANE_PROP_COUNT];
  518. struct drm_property *crtc_property[CRTC_PROP_COUNT];
  519. struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
  520. /* Color processing properties for the crtc */
  521. struct drm_property **cp_property;
  522. /* VRAM carveout, used when no IOMMU: */
  523. struct {
  524. unsigned long size;
  525. dma_addr_t paddr;
  526. /* NOTE: mm managed at the page level, size is in # of pages
  527. * and position mm_node->start is in # of pages:
  528. */
  529. struct drm_mm mm;
  530. spinlock_t lock; /* Protects drm_mm node allocation/removal */
  531. } vram;
  532. struct notifier_block vmap_notifier;
  533. struct shrinker shrinker;
  534. struct drm_atomic_state *pm_state;
  535. /* task holding struct_mutex.. currently only used in submit path
  536. * to detect and reject faults from copy_from_user() for submit
  537. * ioctl.
  538. */
  539. struct task_struct *struct_mutex_task;
  540. /* list of clients waiting for events */
  541. struct list_head client_event_list;
  542. /* whether registered and drm_dev_unregister should be called */
  543. bool registered;
  544. /* msm drv debug root node */
  545. struct dentry *debug_root;
  546. /* update the flag when msm driver receives shutdown notification */
  547. bool shutdown_in_progress;
  548. };
  549. /* get struct msm_kms * from drm_device * */
  550. #define ddev_to_msm_kms(D) ((D) && (D)->dev_private ? \
  551. ((struct msm_drm_private *)((D)->dev_private))->kms : NULL)
  552. struct msm_format {
  553. uint32_t pixel_format;
  554. };
  555. int msm_atomic_prepare_fb(struct drm_plane *plane,
  556. struct drm_plane_state *new_state);
  557. void msm_atomic_commit_tail(struct drm_atomic_state *state);
  558. int msm_atomic_commit(struct drm_device *dev,
  559. struct drm_atomic_state *state, bool nonblock);
  560. /* callback from wq once fence has passed: */
  561. struct msm_fence_cb {
  562. struct work_struct work;
  563. uint32_t fence;
  564. void (*func)(struct msm_fence_cb *cb);
  565. };
  566. void __msm_fence_worker(struct work_struct *work);
  567. #define INIT_FENCE_CB(_cb, _func) do { \
  568. INIT_WORK(&(_cb)->work, __msm_fence_worker); \
  569. (_cb)->func = _func; \
  570. } while (0)
  571. struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
  572. void msm_atomic_state_clear(struct drm_atomic_state *state);
  573. void msm_atomic_state_free(struct drm_atomic_state *state);
  574. int msm_gem_init_vma(struct msm_gem_address_space *aspace,
  575. struct msm_gem_vma *vma, int npages);
  576. void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
  577. struct msm_gem_vma *vma, struct sg_table *sgt,
  578. unsigned int flags);
  579. int msm_gem_map_vma(struct msm_gem_address_space *aspace,
  580. struct msm_gem_vma *vma, struct sg_table *sgt, int npages,
  581. unsigned int flags);
  582. struct device *msm_gem_get_aspace_device(struct msm_gem_address_space *aspace);
  583. void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
  584. struct msm_gem_address_space *
  585. msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
  586. const char *name);
  587. /* For SDE display */
  588. struct msm_gem_address_space *
  589. msm_gem_smmu_address_space_create(struct drm_device *dev, struct msm_mmu *mmu,
  590. const char *name);
  591. /**
  592. * msm_gem_add_obj_to_aspace_active_list: adds obj to active obj list in aspace
  593. */
  594. void msm_gem_add_obj_to_aspace_active_list(
  595. struct msm_gem_address_space *aspace,
  596. struct drm_gem_object *obj);
  597. /**
  598. * msm_gem_remove_obj_from_aspace_active_list: removes obj from active obj
  599. * list in aspace
  600. */
  601. void msm_gem_remove_obj_from_aspace_active_list(
  602. struct msm_gem_address_space *aspace,
  603. struct drm_gem_object *obj);
  604. /**
  605. * msm_gem_smmu_address_space_get: returns the aspace pointer for the requested
  606. * domain
  607. */
  608. struct msm_gem_address_space *
  609. msm_gem_smmu_address_space_get(struct drm_device *dev,
  610. unsigned int domain);
  611. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  612. void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  613. /**
  614. * msm_gem_aspace_domain_attach_detach: function to inform the attach/detach
  615. * of the domain for this aspace
  616. */
  617. void msm_gem_aspace_domain_attach_detach_update(
  618. struct msm_gem_address_space *aspace,
  619. bool is_detach);
  620. /**
  621. * msm_gem_address_space_register_cb: function to register callback for attach
  622. * and detach of the domain
  623. */
  624. int msm_gem_address_space_register_cb(
  625. struct msm_gem_address_space *aspace,
  626. void (*cb)(void *, bool),
  627. void *cb_data);
  628. /**
  629. * msm_gem_address_space_register_cb: function to unregister callback
  630. */
  631. int msm_gem_address_space_unregister_cb(
  632. struct msm_gem_address_space *aspace,
  633. void (*cb)(void *, bool),
  634. void *cb_data);
  635. void msm_gem_submit_free(struct msm_gem_submit *submit);
  636. int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
  637. struct drm_file *file);
  638. void msm_gem_shrinker_init(struct drm_device *dev);
  639. void msm_gem_shrinker_cleanup(struct drm_device *dev);
  640. void msm_gem_sync(struct drm_gem_object *obj);
  641. int msm_gem_mmap_obj(struct drm_gem_object *obj,
  642. struct vm_area_struct *vma);
  643. int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
  644. vm_fault_t msm_gem_fault(struct vm_fault *vmf);
  645. uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
  646. int msm_gem_get_iova(struct drm_gem_object *obj,
  647. struct msm_gem_address_space *aspace, uint64_t *iova);
  648. int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
  649. struct msm_gem_address_space *aspace, uint64_t *iova);
  650. uint64_t msm_gem_iova(struct drm_gem_object *obj,
  651. struct msm_gem_address_space *aspace);
  652. void msm_gem_unpin_iova(struct drm_gem_object *obj,
  653. struct msm_gem_address_space *aspace);
  654. struct page **msm_gem_get_pages(struct drm_gem_object *obj);
  655. void msm_gem_put_pages(struct drm_gem_object *obj);
  656. void msm_gem_put_iova(struct drm_gem_object *obj,
  657. struct msm_gem_address_space *aspace);
  658. dma_addr_t msm_gem_get_dma_addr(struct drm_gem_object *obj);
  659. int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
  660. struct drm_mode_create_dumb *args);
  661. int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
  662. uint32_t handle, uint64_t *offset);
  663. struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
  664. void *msm_gem_prime_vmap(struct drm_gem_object *obj);
  665. void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  666. int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
  667. struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
  668. struct dma_buf_attachment *attach, struct sg_table *sg);
  669. int msm_gem_prime_pin(struct drm_gem_object *obj);
  670. void msm_gem_prime_unpin(struct drm_gem_object *obj);
  671. struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev,
  672. struct dma_buf *dma_buf);
  673. void *msm_gem_get_vaddr(struct drm_gem_object *obj);
  674. void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
  675. void msm_gem_put_vaddr(struct drm_gem_object *obj);
  676. int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
  677. int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
  678. int msm_gem_cpu_fini(struct drm_gem_object *obj);
  679. void msm_gem_free_object(struct drm_gem_object *obj);
  680. int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
  681. uint32_t size, uint32_t flags, uint32_t *handle, char *name);
  682. struct drm_gem_object *msm_gem_new(struct drm_device *dev,
  683. uint32_t size, uint32_t flags);
  684. struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
  685. uint32_t size, uint32_t flags);
  686. void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
  687. uint32_t flags, struct msm_gem_address_space *aspace,
  688. struct drm_gem_object **bo, uint64_t *iova);
  689. void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
  690. uint32_t flags, struct msm_gem_address_space *aspace,
  691. struct drm_gem_object **bo, uint64_t *iova);
  692. struct drm_gem_object *msm_gem_import(struct drm_device *dev,
  693. struct dma_buf *dmabuf, struct sg_table *sgt);
  694. __printf(2, 3)
  695. void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
  696. int msm_gem_delayed_import(struct drm_gem_object *obj);
  697. void msm_framebuffer_set_kmap(struct drm_framebuffer *fb, bool enable);
  698. void msm_framebuffer_set_keepattrs(struct drm_framebuffer *fb, bool enable);
  699. int msm_framebuffer_prepare(struct drm_framebuffer *fb,
  700. struct msm_gem_address_space *aspace);
  701. void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
  702. struct msm_gem_address_space *aspace);
  703. uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
  704. struct msm_gem_address_space *aspace, int plane);
  705. uint32_t msm_framebuffer_phys(struct drm_framebuffer *fb, int plane);
  706. struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
  707. const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
  708. struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
  709. const struct drm_mode_fb_cmd2 *mode_cmd,
  710. struct drm_gem_object **bos);
  711. struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
  712. struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
  713. struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
  714. int w, int h, int p, uint32_t format);
  715. struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
  716. void msm_fbdev_free(struct drm_device *dev);
  717. struct hdmi;
  718. #ifdef CONFIG_DRM_MSM_HDMI
  719. int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
  720. struct drm_encoder *encoder);
  721. void __init msm_hdmi_register(void);
  722. void __exit msm_hdmi_unregister(void);
  723. #else
  724. static inline void __init msm_hdmi_register(void)
  725. {
  726. }
  727. static inline void __exit msm_hdmi_unregister(void)
  728. {
  729. }
  730. #endif
  731. struct msm_edp;
  732. #ifdef CONFIG_DRM_MSM_EDP
  733. void __init msm_edp_register(void);
  734. void __exit msm_edp_unregister(void);
  735. int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
  736. struct drm_encoder *encoder);
  737. #else
  738. static inline void __init msm_edp_register(void)
  739. {
  740. }
  741. static inline void __exit msm_edp_unregister(void)
  742. {
  743. }
  744. static inline int msm_edp_modeset_init(struct msm_edp *edp,
  745. struct drm_device *dev, struct drm_encoder *encoder)
  746. {
  747. return -EINVAL;
  748. }
  749. #endif
  750. struct msm_dsi;
  751. /* *
  752. * msm_mode_object_event_notify - notify user-space clients of drm object
  753. * events.
  754. * @obj: mode object (crtc/connector) that is generating the event.
  755. * @event: event that needs to be notified.
  756. * @payload: payload for the event.
  757. */
  758. void msm_mode_object_event_notify(struct drm_mode_object *obj,
  759. struct drm_device *dev, struct drm_event *event, u8 *payload);
  760. #ifndef CONFIG_DRM_MSM_DSI
  761. void __init msm_dsi_register(void);
  762. void __exit msm_dsi_unregister(void);
  763. int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
  764. struct drm_encoder *encoder);
  765. #else
  766. static inline void __init msm_dsi_register(void)
  767. {
  768. }
  769. static inline void __exit msm_dsi_unregister(void)
  770. {
  771. }
  772. static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
  773. struct drm_device *dev,
  774. struct drm_encoder *encoder)
  775. {
  776. return -EINVAL;
  777. }
  778. #endif
  779. #ifdef CONFIG_DRM_MSM_MDP5
  780. void __init msm_mdp_register(void);
  781. void __exit msm_mdp_unregister(void);
  782. #else
  783. static inline void __init msm_mdp_register(void)
  784. {
  785. }
  786. static inline void __exit msm_mdp_unregister(void)
  787. {
  788. }
  789. #endif
  790. #ifdef CONFIG_DEBUG_FS
  791. void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
  792. void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
  793. void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
  794. int msm_debugfs_late_init(struct drm_device *dev);
  795. int msm_rd_debugfs_init(struct drm_minor *minor);
  796. void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
  797. __printf(3, 4)
  798. void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  799. const char *fmt, ...);
  800. int msm_perf_debugfs_init(struct drm_minor *minor);
  801. void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
  802. #else
  803. static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
  804. __printf(3, 4)
  805. static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  806. const char *fmt, ...) {}
  807. static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
  808. static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
  809. #endif
  810. struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
  811. int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);
  812. struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
  813. const char *name);
  814. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  815. const char *dbgname);
  816. unsigned long msm_iomap_size(struct platform_device *pdev, const char *name);
  817. void msm_iounmap(struct platform_device *dev, void __iomem *addr);
  818. void msm_writel(u32 data, void __iomem *addr);
  819. u32 msm_readl(const void __iomem *addr);
  820. #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  821. #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  822. static inline int align_pitch(int width, int bpp)
  823. {
  824. int bytespp = (bpp + 7) / 8;
  825. /* adreno needs pitch aligned to 32 pixels: */
  826. return bytespp * ALIGN(width, 32);
  827. }
  828. /* for the generated headers: */
  829. #define INVALID_IDX(idx) ({BUG(); 0;})
  830. #define fui(x) ({BUG(); 0;})
  831. #define util_float_to_half(x) ({BUG(); 0;})
  832. #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
  833. /* for conditionally setting boolean flag(s): */
  834. #define COND(bool, val) ((bool) ? (val) : 0)
  835. static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
  836. {
  837. ktime_t now = ktime_get();
  838. unsigned long remaining_jiffies;
  839. if (ktime_compare(*timeout, now) < 0) {
  840. remaining_jiffies = 0;
  841. } else {
  842. ktime_t rem = ktime_sub(*timeout, now);
  843. struct timespec ts = ktime_to_timespec(rem);
  844. remaining_jiffies = timespec_to_jiffies(&ts);
  845. }
  846. return remaining_jiffies;
  847. }
  848. int msm_get_mixer_count(struct msm_drm_private *priv,
  849. const struct drm_display_mode *mode,
  850. const struct msm_resource_caps_info *res, u32 *num_lm);
  851. #endif /* __MSM_DRV_H__ */