wcd938x.c 114 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. #define NUM_ATTEMPTS 5
  38. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  39. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  40. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  41. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  42. enum {
  43. CODEC_TX = 0,
  44. CODEC_RX,
  45. };
  46. enum {
  47. WCD_ADC1 = 0,
  48. WCD_ADC2,
  49. WCD_ADC3,
  50. WCD_ADC4,
  51. ALLOW_BUCK_DISABLE,
  52. HPH_COMP_DELAY,
  53. HPH_PA_DELAY,
  54. AMIC2_BCS_ENABLE,
  55. };
  56. enum {
  57. ADC_MODE_INVALID = 0,
  58. ADC_MODE_HIFI,
  59. ADC_MODE_LO_HIF,
  60. ADC_MODE_NORMAL,
  61. ADC_MODE_LP,
  62. ADC_MODE_ULP1,
  63. ADC_MODE_ULP2,
  64. };
  65. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  66. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  67. static int wcd938x_handle_post_irq(void *data);
  68. static int wcd938x_reset(struct device *dev);
  69. static int wcd938x_reset_low(struct device *dev);
  70. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  87. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  88. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  89. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  91. };
  92. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  93. .name = "wcd938x",
  94. .irqs = wcd938x_irqs,
  95. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  96. .num_regs = 3,
  97. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  98. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  99. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  100. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  101. .use_ack = 1,
  102. .runtime_pm = false,
  103. .handle_post_irq = wcd938x_handle_post_irq,
  104. .irq_drv_data = NULL,
  105. };
  106. static int wcd938x_handle_post_irq(void *data)
  107. {
  108. struct wcd938x_priv *wcd938x = data;
  109. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  110. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  111. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  112. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  113. wcd938x->tx_swr_dev->slave_irq_pending =
  114. ((sts1 || sts2 || sts3) ? true : false);
  115. return IRQ_HANDLED;
  116. }
  117. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  118. {
  119. int ret = 0;
  120. int bank = 0;
  121. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  122. if (ret)
  123. return -EINVAL;
  124. return ((bank & 0x40) ? 1: 0);
  125. }
  126. static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
  127. u8 devnum, int bank)
  128. {
  129. u8 val = (bank ? 1 : 0);
  130. return (swr_write(dev, devnum,
  131. (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
  132. }
  133. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  134. int mode, int bank)
  135. {
  136. u8 mask = (bank ? 0xF0 : 0x0F);
  137. u8 val = 0;
  138. if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
  139. val = (bank ? 0x60 : 0x06);
  140. else
  141. val = 0x00;
  142. snd_soc_component_update_bits(component,
  143. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  144. mask, val);
  145. return 0;
  146. }
  147. static int wcd938x_init_reg(struct snd_soc_component *component)
  148. {
  149. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  150. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  151. /* 1 msec delay as per HW requirement */
  152. usleep_range(1000, 1010);
  153. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  154. /* 1 msec delay as per HW requirement */
  155. usleep_range(1000, 1010);
  156. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  157. 0x10, 0x00);
  158. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  159. 0xF0, 0x80);
  160. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  161. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  162. /* 10 msec delay as per HW requirement */
  163. usleep_range(10000, 10010);
  164. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  165. snd_soc_component_update_bits(component,
  166. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  167. 0xF0, 0x00);
  168. snd_soc_component_update_bits(component,
  169. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  170. 0x1F, 0x15);
  171. snd_soc_component_update_bits(component,
  172. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  173. 0x1F, 0x15);
  174. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  175. 0xC0, 0x80);
  176. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  177. 0x02, 0x02);
  178. snd_soc_component_update_bits(component,
  179. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  180. 0xFF, 0x14);
  181. snd_soc_component_update_bits(component,
  182. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  183. 0x1F, 0x08);
  184. snd_soc_component_update_bits(component,
  185. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  186. snd_soc_component_update_bits(component,
  187. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  188. snd_soc_component_update_bits(component,
  189. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  192. snd_soc_component_update_bits(component,
  193. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  194. snd_soc_component_update_bits(component,
  195. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  196. snd_soc_component_update_bits(component,
  197. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  198. snd_soc_component_update_bits(component,
  199. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  200. snd_soc_component_update_bits(component,
  201. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  202. snd_soc_component_update_bits(component,
  203. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  204. return 0;
  205. }
  206. static int wcd938x_set_port_params(struct snd_soc_component *component,
  207. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  208. u8 *ch_mask, u32 *ch_rate,
  209. u8 *port_type, u8 path)
  210. {
  211. int i, j;
  212. u8 num_ports = 0;
  213. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  214. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  215. switch (path) {
  216. case CODEC_RX:
  217. map = &wcd938x->rx_port_mapping;
  218. num_ports = wcd938x->num_rx_ports;
  219. break;
  220. case CODEC_TX:
  221. map = &wcd938x->tx_port_mapping;
  222. num_ports = wcd938x->num_tx_ports;
  223. break;
  224. default:
  225. dev_err(component->dev, "%s Invalid path selected %u\n",
  226. __func__, path);
  227. return -EINVAL;
  228. }
  229. for (i = 0; i <= num_ports; i++) {
  230. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  231. if ((*map)[i][j].slave_port_type == slv_prt_type)
  232. goto found;
  233. }
  234. }
  235. found:
  236. if (i > num_ports || j == MAX_CH_PER_PORT) {
  237. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  238. __func__, slv_prt_type);
  239. return -EINVAL;
  240. }
  241. *port_id = i;
  242. *num_ch = (*map)[i][j].num_ch;
  243. *ch_mask = (*map)[i][j].ch_mask;
  244. *ch_rate = (*map)[i][j].ch_rate;
  245. *port_type = (*map)[i][j].master_port_type;
  246. return 0;
  247. }
  248. static int wcd938x_parse_port_mapping(struct device *dev,
  249. char *prop, u8 path)
  250. {
  251. u32 *dt_array, map_size, map_length;
  252. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  253. u32 slave_port_type, master_port_type;
  254. u32 i, ch_iter = 0;
  255. int ret = 0;
  256. u8 *num_ports = NULL;
  257. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  258. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  259. switch (path) {
  260. case CODEC_RX:
  261. map = &wcd938x->rx_port_mapping;
  262. num_ports = &wcd938x->num_rx_ports;
  263. break;
  264. case CODEC_TX:
  265. map = &wcd938x->tx_port_mapping;
  266. num_ports = &wcd938x->num_tx_ports;
  267. break;
  268. default:
  269. dev_err(dev, "%s Invalid path selected %u\n",
  270. __func__, path);
  271. return -EINVAL;
  272. }
  273. if (!of_find_property(dev->of_node, prop,
  274. &map_size)) {
  275. dev_err(dev, "missing port mapping prop %s\n", prop);
  276. ret = -EINVAL;
  277. goto err_port_map;
  278. }
  279. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  280. dt_array = kzalloc(map_size, GFP_KERNEL);
  281. if (!dt_array) {
  282. ret = -ENOMEM;
  283. goto err_alloc;
  284. }
  285. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  286. NUM_SWRS_DT_PARAMS * map_length);
  287. if (ret) {
  288. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  289. __func__, prop);
  290. goto err_pdata_fail;
  291. }
  292. for (i = 0; i < map_length; i++) {
  293. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  294. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  295. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  296. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  297. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  298. if (port_num != old_port_num)
  299. ch_iter = 0;
  300. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  301. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  302. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  303. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  304. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  305. old_port_num = port_num;
  306. }
  307. *num_ports = port_num;
  308. kfree(dt_array);
  309. return 0;
  310. err_pdata_fail:
  311. kfree(dt_array);
  312. err_alloc:
  313. err_port_map:
  314. return ret;
  315. }
  316. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  317. u8 slv_port_type, u8 enable)
  318. {
  319. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  320. u8 port_id, num_ch, ch_mask;
  321. u8 ch_type = 0;
  322. u32 ch_rate;
  323. int slave_ch_idx;
  324. u8 num_port = 1;
  325. int ret = 0;
  326. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  327. &num_ch, &ch_mask, &ch_rate,
  328. &ch_type, CODEC_TX);
  329. if (ret)
  330. return ret;
  331. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  332. if (slave_ch_idx != -EINVAL)
  333. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  334. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  335. __func__, slave_ch_idx, ch_type);
  336. if (enable)
  337. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  338. num_port, &ch_mask, &ch_rate,
  339. &num_ch, &ch_type);
  340. else
  341. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  342. num_port, &ch_mask, &ch_type);
  343. return ret;
  344. }
  345. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  346. u8 slv_port_type, u8 enable)
  347. {
  348. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  349. u8 port_id, num_ch, ch_mask, port_type;
  350. u32 ch_rate;
  351. u8 num_port = 1;
  352. int ret = 0;
  353. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  354. &num_ch, &ch_mask, &ch_rate,
  355. &port_type, CODEC_RX);
  356. if (ret)
  357. return ret;
  358. if (enable)
  359. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  360. num_port, &ch_mask, &ch_rate,
  361. &num_ch, &port_type);
  362. else
  363. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  364. num_port, &ch_mask, &port_type);
  365. return ret;
  366. }
  367. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  368. {
  369. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  370. if (wcd938x->rx_clk_cnt == 0) {
  371. snd_soc_component_update_bits(component,
  372. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  373. snd_soc_component_update_bits(component,
  374. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  375. snd_soc_component_update_bits(component,
  376. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  377. snd_soc_component_update_bits(component,
  378. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  379. snd_soc_component_update_bits(component,
  380. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  381. snd_soc_component_update_bits(component,
  382. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  383. snd_soc_component_update_bits(component,
  384. WCD938X_AUX_AUXPA, 0x10, 0x10);
  385. }
  386. wcd938x->rx_clk_cnt++;
  387. return 0;
  388. }
  389. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  390. {
  391. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  392. wcd938x->rx_clk_cnt--;
  393. if (wcd938x->rx_clk_cnt == 0) {
  394. snd_soc_component_update_bits(component,
  395. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  396. snd_soc_component_update_bits(component,
  397. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  398. snd_soc_component_update_bits(component,
  399. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  400. snd_soc_component_update_bits(component,
  401. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  402. snd_soc_component_update_bits(component,
  403. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  404. }
  405. return 0;
  406. }
  407. /*
  408. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  409. * @component: handle to snd_soc_component *
  410. *
  411. * return wcd938x_mbhc handle or error code in case of failure
  412. */
  413. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  414. {
  415. struct wcd938x_priv *wcd938x;
  416. if (!component) {
  417. pr_err("%s: Invalid params, NULL component\n", __func__);
  418. return NULL;
  419. }
  420. wcd938x = snd_soc_component_get_drvdata(component);
  421. if (!wcd938x) {
  422. pr_err("%s: wcd938x is NULL\n", __func__);
  423. return NULL;
  424. }
  425. return wcd938x->mbhc;
  426. }
  427. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  428. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  429. struct snd_kcontrol *kcontrol,
  430. int event)
  431. {
  432. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  433. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  434. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  435. w->name, event);
  436. switch (event) {
  437. case SND_SOC_DAPM_PRE_PMU:
  438. wcd938x_rx_clk_enable(component);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  441. snd_soc_component_update_bits(component,
  442. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  443. snd_soc_component_update_bits(component,
  444. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  445. break;
  446. case SND_SOC_DAPM_POST_PMU:
  447. snd_soc_component_update_bits(component,
  448. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  449. if (wcd938x->comp1_enable) {
  450. snd_soc_component_update_bits(component,
  451. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  452. /* 5msec compander delay as per HW requirement */
  453. if (!wcd938x->comp2_enable ||
  454. (snd_soc_component_read32(component,
  455. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  456. usleep_range(5000, 5010);
  457. snd_soc_component_update_bits(component,
  458. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  459. } else {
  460. snd_soc_component_update_bits(component,
  461. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  462. 0x02, 0x00);
  463. snd_soc_component_update_bits(component,
  464. WCD938X_HPH_L_EN, 0x20, 0x20);
  465. }
  466. break;
  467. case SND_SOC_DAPM_POST_PMD:
  468. snd_soc_component_update_bits(component,
  469. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  470. 0x0F, 0x01);
  471. break;
  472. }
  473. return 0;
  474. }
  475. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  476. struct snd_kcontrol *kcontrol,
  477. int event)
  478. {
  479. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  480. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  481. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  482. w->name, event);
  483. switch (event) {
  484. case SND_SOC_DAPM_PRE_PMU:
  485. wcd938x_rx_clk_enable(component);
  486. snd_soc_component_update_bits(component,
  487. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  488. snd_soc_component_update_bits(component,
  489. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  490. snd_soc_component_update_bits(component,
  491. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  492. break;
  493. case SND_SOC_DAPM_POST_PMU:
  494. snd_soc_component_update_bits(component,
  495. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  496. if (wcd938x->comp2_enable) {
  497. snd_soc_component_update_bits(component,
  498. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  499. /* 5msec compander delay as per HW requirement */
  500. if (!wcd938x->comp1_enable ||
  501. (snd_soc_component_read32(component,
  502. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  503. usleep_range(5000, 5010);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  506. } else {
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  509. 0x01, 0x00);
  510. snd_soc_component_update_bits(component,
  511. WCD938X_HPH_R_EN, 0x20, 0x20);
  512. }
  513. break;
  514. case SND_SOC_DAPM_POST_PMD:
  515. snd_soc_component_update_bits(component,
  516. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  517. 0x0F, 0x01);
  518. break;
  519. }
  520. return 0;
  521. }
  522. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  523. struct snd_kcontrol *kcontrol,
  524. int event)
  525. {
  526. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  528. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  529. w->name, event);
  530. switch (event) {
  531. case SND_SOC_DAPM_PRE_PMU:
  532. wcd938x_rx_clk_enable(component);
  533. wcd938x->ear_rx_path =
  534. snd_soc_component_read32(
  535. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  536. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  537. snd_soc_component_update_bits(component,
  538. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  539. snd_soc_component_update_bits(component,
  540. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  541. snd_soc_component_update_bits(component,
  542. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  543. snd_soc_component_update_bits(component,
  544. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  545. } else {
  546. snd_soc_component_update_bits(component,
  547. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  548. snd_soc_component_update_bits(component,
  549. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  550. snd_soc_component_update_bits(component,
  551. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  552. }
  553. /* 5 msec delay as per HW requirement */
  554. usleep_range(5000, 5010);
  555. if (wcd938x->flyback_cur_det_disable == 0)
  556. snd_soc_component_update_bits(component,
  557. WCD938X_FLYBACK_EN,
  558. 0x04, 0x00);
  559. wcd938x->flyback_cur_det_disable++;
  560. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  561. WCD_CLSH_EVENT_PRE_DAC,
  562. WCD_CLSH_STATE_EAR,
  563. wcd938x->hph_mode);
  564. break;
  565. case SND_SOC_DAPM_POST_PMD:
  566. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  567. snd_soc_component_update_bits(component,
  568. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  569. }
  570. snd_soc_component_update_bits(component,
  571. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  572. snd_soc_component_update_bits(component,
  573. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  574. break;
  575. };
  576. return 0;
  577. }
  578. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  579. struct snd_kcontrol *kcontrol,
  580. int event)
  581. {
  582. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  583. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  584. int ret = 0;
  585. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  586. w->name, event);
  587. switch (event) {
  588. case SND_SOC_DAPM_PRE_PMU:
  589. wcd938x_rx_clk_enable(component);
  590. snd_soc_component_update_bits(component,
  591. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  592. snd_soc_component_update_bits(component,
  593. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  594. snd_soc_component_update_bits(component,
  595. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  596. if (wcd938x->flyback_cur_det_disable == 0)
  597. snd_soc_component_update_bits(component,
  598. WCD938X_FLYBACK_EN,
  599. 0x04, 0x00);
  600. wcd938x->flyback_cur_det_disable++;
  601. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  602. WCD_CLSH_EVENT_PRE_DAC,
  603. WCD_CLSH_STATE_AUX,
  604. wcd938x->hph_mode);
  605. break;
  606. case SND_SOC_DAPM_POST_PMD:
  607. snd_soc_component_update_bits(component,
  608. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  609. break;
  610. };
  611. return ret;
  612. }
  613. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  614. struct snd_kcontrol *kcontrol,
  615. int event)
  616. {
  617. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  618. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  619. int ret = 0;
  620. int hph_mode = wcd938x->hph_mode;
  621. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  622. w->name, event);
  623. switch (event) {
  624. case SND_SOC_DAPM_PRE_PMU:
  625. if (wcd938x->ldoh)
  626. snd_soc_component_update_bits(component,
  627. WCD938X_LDOH_MODE,
  628. 0x80, 0x80);
  629. if (wcd938x->update_wcd_event)
  630. wcd938x->update_wcd_event(wcd938x->handle,
  631. WCD_BOLERO_EVT_RX_MUTE,
  632. (WCD_RX2 << 0x10 | 0x1));
  633. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  634. wcd938x->rx_swr_dev->dev_num,
  635. true);
  636. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  637. WCD_CLSH_EVENT_PRE_DAC,
  638. WCD_CLSH_STATE_HPHR,
  639. hph_mode);
  640. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  641. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  642. 0x10, 0x10);
  643. wcd_clsh_set_hph_mode(component, hph_mode);
  644. /* 100 usec delay as per HW requirement */
  645. usleep_range(100, 110);
  646. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  647. snd_soc_component_update_bits(component,
  648. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  649. break;
  650. case SND_SOC_DAPM_POST_PMU:
  651. /*
  652. * 7ms sleep is required if compander is enabled as per
  653. * HW requirement. If compander is disabled, then
  654. * 20ms delay is required.
  655. */
  656. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  657. if (!wcd938x->comp2_enable)
  658. usleep_range(20000, 20100);
  659. else
  660. usleep_range(7000, 7100);
  661. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  662. }
  663. snd_soc_component_update_bits(component,
  664. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  665. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  666. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  667. snd_soc_component_update_bits(component,
  668. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  669. if (wcd938x->update_wcd_event)
  670. wcd938x->update_wcd_event(wcd938x->handle,
  671. WCD_BOLERO_EVT_RX_MUTE,
  672. (WCD_RX2 << 0x10));
  673. wcd_enable_irq(&wcd938x->irq_info,
  674. WCD938X_IRQ_HPHR_PDM_WD_INT);
  675. break;
  676. case SND_SOC_DAPM_PRE_PMD:
  677. if (wcd938x->update_wcd_event)
  678. wcd938x->update_wcd_event(wcd938x->handle,
  679. WCD_BOLERO_EVT_RX_MUTE,
  680. (WCD_RX2 << 0x10 | 0x1));
  681. wcd_disable_irq(&wcd938x->irq_info,
  682. WCD938X_IRQ_HPHR_PDM_WD_INT);
  683. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  684. wcd938x->update_wcd_event(wcd938x->handle,
  685. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  686. (WCD_RX2 << 0x10));
  687. /*
  688. * 7ms sleep is required if compander is enabled as per
  689. * HW requirement. If compander is disabled, then
  690. * 20ms delay is required.
  691. */
  692. if (!wcd938x->comp2_enable)
  693. usleep_range(20000, 20100);
  694. else
  695. usleep_range(7000, 7100);
  696. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  697. 0x40, 0x00);
  698. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  699. WCD_EVENT_PRE_HPHR_PA_OFF,
  700. &wcd938x->mbhc->wcd_mbhc);
  701. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  702. break;
  703. case SND_SOC_DAPM_POST_PMD:
  704. /*
  705. * 7ms sleep is required if compander is enabled as per
  706. * HW requirement. If compander is disabled, then
  707. * 20ms delay is required.
  708. */
  709. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  710. if (!wcd938x->comp2_enable)
  711. usleep_range(20000, 20100);
  712. else
  713. usleep_range(7000, 7100);
  714. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  715. }
  716. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  717. WCD_EVENT_POST_HPHR_PA_OFF,
  718. &wcd938x->mbhc->wcd_mbhc);
  719. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  720. 0x10, 0x00);
  721. snd_soc_component_update_bits(component,
  722. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  723. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  724. WCD_CLSH_EVENT_POST_PA,
  725. WCD_CLSH_STATE_HPHR,
  726. hph_mode);
  727. if (wcd938x->ldoh)
  728. snd_soc_component_update_bits(component,
  729. WCD938X_LDOH_MODE,
  730. 0x80, 0x00);
  731. break;
  732. };
  733. return ret;
  734. }
  735. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  736. struct snd_kcontrol *kcontrol,
  737. int event)
  738. {
  739. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  740. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  741. int ret = 0;
  742. int hph_mode = wcd938x->hph_mode;
  743. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  744. w->name, event);
  745. switch (event) {
  746. case SND_SOC_DAPM_PRE_PMU:
  747. if (wcd938x->ldoh)
  748. snd_soc_component_update_bits(component,
  749. WCD938X_LDOH_MODE,
  750. 0x80, 0x80);
  751. if (wcd938x->update_wcd_event)
  752. wcd938x->update_wcd_event(wcd938x->handle,
  753. WCD_BOLERO_EVT_RX_MUTE,
  754. (WCD_RX1 << 0x10 | 0x01));
  755. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  756. wcd938x->rx_swr_dev->dev_num,
  757. true);
  758. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  759. WCD_CLSH_EVENT_PRE_DAC,
  760. WCD_CLSH_STATE_HPHL,
  761. hph_mode);
  762. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  763. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  764. 0x20, 0x20);
  765. wcd_clsh_set_hph_mode(component, hph_mode);
  766. /* 100 usec delay as per HW requirement */
  767. usleep_range(100, 110);
  768. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  769. snd_soc_component_update_bits(component,
  770. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  771. break;
  772. case SND_SOC_DAPM_POST_PMU:
  773. /*
  774. * 7ms sleep is required if compander is enabled as per
  775. * HW requirement. If compander is disabled, then
  776. * 20ms delay is required.
  777. */
  778. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  779. if (!wcd938x->comp1_enable)
  780. usleep_range(20000, 20100);
  781. else
  782. usleep_range(7000, 7100);
  783. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  784. }
  785. snd_soc_component_update_bits(component,
  786. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  787. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  788. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  789. snd_soc_component_update_bits(component,
  790. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  791. if (wcd938x->update_wcd_event)
  792. wcd938x->update_wcd_event(wcd938x->handle,
  793. WCD_BOLERO_EVT_RX_MUTE,
  794. (WCD_RX1 << 0x10));
  795. wcd_enable_irq(&wcd938x->irq_info,
  796. WCD938X_IRQ_HPHL_PDM_WD_INT);
  797. break;
  798. case SND_SOC_DAPM_PRE_PMD:
  799. if (wcd938x->update_wcd_event)
  800. wcd938x->update_wcd_event(wcd938x->handle,
  801. WCD_BOLERO_EVT_RX_MUTE,
  802. (WCD_RX1 << 0x10 | 0x1));
  803. wcd_disable_irq(&wcd938x->irq_info,
  804. WCD938X_IRQ_HPHL_PDM_WD_INT);
  805. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  806. wcd938x->update_wcd_event(wcd938x->handle,
  807. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  808. (WCD_RX1 << 0x10));
  809. /*
  810. * 7ms sleep is required if compander is enabled as per
  811. * HW requirement. If compander is disabled, then
  812. * 20ms delay is required.
  813. */
  814. if (!wcd938x->comp1_enable)
  815. usleep_range(20000, 20100);
  816. else
  817. usleep_range(7000, 7100);
  818. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  819. 0x80, 0x00);
  820. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  821. WCD_EVENT_PRE_HPHL_PA_OFF,
  822. &wcd938x->mbhc->wcd_mbhc);
  823. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  824. break;
  825. case SND_SOC_DAPM_POST_PMD:
  826. /*
  827. * 7ms sleep is required if compander is enabled as per
  828. * HW requirement. If compander is disabled, then
  829. * 20ms delay is required.
  830. */
  831. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  832. if (!wcd938x->comp1_enable)
  833. usleep_range(21000, 21100);
  834. else
  835. usleep_range(7000, 7100);
  836. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  837. }
  838. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  839. WCD_EVENT_POST_HPHL_PA_OFF,
  840. &wcd938x->mbhc->wcd_mbhc);
  841. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  842. 0x20, 0x00);
  843. snd_soc_component_update_bits(component,
  844. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  845. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  846. WCD_CLSH_EVENT_POST_PA,
  847. WCD_CLSH_STATE_HPHL,
  848. hph_mode);
  849. if (wcd938x->ldoh)
  850. snd_soc_component_update_bits(component,
  851. WCD938X_LDOH_MODE,
  852. 0x80, 0x00);
  853. break;
  854. };
  855. return ret;
  856. }
  857. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  858. struct snd_kcontrol *kcontrol,
  859. int event)
  860. {
  861. struct snd_soc_component *component =
  862. snd_soc_dapm_to_component(w->dapm);
  863. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  864. int hph_mode = wcd938x->hph_mode;
  865. int ret = 0;
  866. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  867. w->name, event);
  868. switch (event) {
  869. case SND_SOC_DAPM_PRE_PMU:
  870. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  871. wcd938x->rx_swr_dev->dev_num,
  872. true);
  873. snd_soc_component_update_bits(component,
  874. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  875. break;
  876. case SND_SOC_DAPM_POST_PMU:
  877. /* 1 msec delay as per HW requirement */
  878. usleep_range(1000, 1010);
  879. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  880. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  881. snd_soc_component_update_bits(component,
  882. WCD938X_ANA_RX_SUPPLIES,
  883. 0x02, 0x02);
  884. if (wcd938x->update_wcd_event)
  885. wcd938x->update_wcd_event(wcd938x->handle,
  886. WCD_BOLERO_EVT_RX_MUTE,
  887. (WCD_RX3 << 0x10));
  888. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  889. break;
  890. case SND_SOC_DAPM_PRE_PMD:
  891. wcd_disable_irq(&wcd938x->irq_info,
  892. WCD938X_IRQ_AUX_PDM_WD_INT);
  893. if (wcd938x->update_wcd_event)
  894. wcd938x->update_wcd_event(wcd938x->handle,
  895. WCD_BOLERO_EVT_RX_MUTE,
  896. (WCD_RX3 << 0x10 | 0x1));
  897. break;
  898. case SND_SOC_DAPM_POST_PMD:
  899. /* 1 msec delay as per HW requirement */
  900. usleep_range(1000, 1010);
  901. snd_soc_component_update_bits(component,
  902. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  903. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  904. WCD_CLSH_EVENT_POST_PA,
  905. WCD_CLSH_STATE_AUX,
  906. hph_mode);
  907. wcd938x->flyback_cur_det_disable--;
  908. if (wcd938x->flyback_cur_det_disable == 0)
  909. snd_soc_component_update_bits(component,
  910. WCD938X_FLYBACK_EN,
  911. 0x04, 0x04);
  912. break;
  913. };
  914. return ret;
  915. }
  916. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  917. struct snd_kcontrol *kcontrol,
  918. int event)
  919. {
  920. struct snd_soc_component *component =
  921. snd_soc_dapm_to_component(w->dapm);
  922. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  923. int hph_mode = wcd938x->hph_mode;
  924. int ret = 0;
  925. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  926. w->name, event);
  927. switch (event) {
  928. case SND_SOC_DAPM_PRE_PMU:
  929. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  930. wcd938x->rx_swr_dev->dev_num,
  931. true);
  932. /*
  933. * Enable watchdog interrupt for HPHL or AUX
  934. * depending on mux value
  935. */
  936. wcd938x->ear_rx_path =
  937. snd_soc_component_read32(
  938. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  939. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  940. snd_soc_component_update_bits(component,
  941. WCD938X_DIGITAL_PDM_WD_CTL2,
  942. 0x05, 0x05);
  943. else
  944. snd_soc_component_update_bits(component,
  945. WCD938X_DIGITAL_PDM_WD_CTL0,
  946. 0x17, 0x13);
  947. if (!wcd938x->comp1_enable)
  948. snd_soc_component_update_bits(component,
  949. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  950. break;
  951. case SND_SOC_DAPM_POST_PMU:
  952. /* 6 msec delay as per HW requirement */
  953. usleep_range(6000, 6010);
  954. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  955. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  956. snd_soc_component_update_bits(component,
  957. WCD938X_ANA_RX_SUPPLIES,
  958. 0x02, 0x02);
  959. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  960. if (wcd938x->update_wcd_event)
  961. wcd938x->update_wcd_event(wcd938x->handle,
  962. WCD_BOLERO_EVT_RX_MUTE,
  963. (WCD_RX3 << 0x10));
  964. wcd_enable_irq(&wcd938x->irq_info,
  965. WCD938X_IRQ_AUX_PDM_WD_INT);
  966. } else {
  967. if (wcd938x->update_wcd_event)
  968. wcd938x->update_wcd_event(wcd938x->handle,
  969. WCD_BOLERO_EVT_RX_MUTE,
  970. (WCD_RX1 << 0x10));
  971. wcd_enable_irq(&wcd938x->irq_info,
  972. WCD938X_IRQ_HPHL_PDM_WD_INT);
  973. }
  974. break;
  975. case SND_SOC_DAPM_PRE_PMD:
  976. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  977. wcd_disable_irq(&wcd938x->irq_info,
  978. WCD938X_IRQ_AUX_PDM_WD_INT);
  979. if (wcd938x->update_wcd_event)
  980. wcd938x->update_wcd_event(wcd938x->handle,
  981. WCD_BOLERO_EVT_RX_MUTE,
  982. (WCD_RX3 << 0x10 | 0x1));
  983. } else {
  984. wcd_disable_irq(&wcd938x->irq_info,
  985. WCD938X_IRQ_HPHL_PDM_WD_INT);
  986. if (wcd938x->update_wcd_event)
  987. wcd938x->update_wcd_event(wcd938x->handle,
  988. WCD_BOLERO_EVT_RX_MUTE,
  989. (WCD_RX1 << 0x10 | 0x1));
  990. }
  991. break;
  992. case SND_SOC_DAPM_POST_PMD:
  993. if (!wcd938x->comp1_enable)
  994. snd_soc_component_update_bits(component,
  995. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  996. /* 7 msec delay as per HW requirement */
  997. usleep_range(7000, 7010);
  998. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  999. snd_soc_component_update_bits(component,
  1000. WCD938X_DIGITAL_PDM_WD_CTL2,
  1001. 0x05, 0x00);
  1002. else
  1003. snd_soc_component_update_bits(component,
  1004. WCD938X_DIGITAL_PDM_WD_CTL0,
  1005. 0x17, 0x00);
  1006. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1007. WCD_CLSH_EVENT_POST_PA,
  1008. WCD_CLSH_STATE_EAR,
  1009. hph_mode);
  1010. wcd938x->flyback_cur_det_disable--;
  1011. if (wcd938x->flyback_cur_det_disable == 0)
  1012. snd_soc_component_update_bits(component,
  1013. WCD938X_FLYBACK_EN,
  1014. 0x04, 0x04);
  1015. break;
  1016. };
  1017. return ret;
  1018. }
  1019. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1020. struct snd_kcontrol *kcontrol,
  1021. int event)
  1022. {
  1023. struct snd_soc_component *component =
  1024. snd_soc_dapm_to_component(w->dapm);
  1025. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1026. int mode = wcd938x->hph_mode;
  1027. int ret = 0;
  1028. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1029. w->name, event);
  1030. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1031. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1032. wcd938x_rx_connect_port(component, CLSH,
  1033. SND_SOC_DAPM_EVENT_ON(event));
  1034. }
  1035. if (SND_SOC_DAPM_EVENT_OFF(event))
  1036. ret = swr_slvdev_datapath_control(
  1037. wcd938x->rx_swr_dev,
  1038. wcd938x->rx_swr_dev->dev_num,
  1039. false);
  1040. return ret;
  1041. }
  1042. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1043. struct snd_kcontrol *kcontrol,
  1044. int event)
  1045. {
  1046. struct snd_soc_component *component =
  1047. snd_soc_dapm_to_component(w->dapm);
  1048. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1049. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1050. w->name, event);
  1051. switch (event) {
  1052. case SND_SOC_DAPM_PRE_PMU:
  1053. wcd938x_rx_connect_port(component, HPH_L, true);
  1054. if (wcd938x->comp1_enable)
  1055. wcd938x_rx_connect_port(component, COMP_L, true);
  1056. break;
  1057. case SND_SOC_DAPM_POST_PMD:
  1058. wcd938x_rx_connect_port(component, HPH_L, false);
  1059. if (wcd938x->comp1_enable)
  1060. wcd938x_rx_connect_port(component, COMP_L, false);
  1061. wcd938x_rx_clk_disable(component);
  1062. snd_soc_component_update_bits(component,
  1063. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1064. 0x01, 0x00);
  1065. break;
  1066. };
  1067. return 0;
  1068. }
  1069. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1070. struct snd_kcontrol *kcontrol, int event)
  1071. {
  1072. struct snd_soc_component *component =
  1073. snd_soc_dapm_to_component(w->dapm);
  1074. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1075. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1076. w->name, event);
  1077. switch (event) {
  1078. case SND_SOC_DAPM_PRE_PMU:
  1079. wcd938x_rx_connect_port(component, HPH_R, true);
  1080. if (wcd938x->comp2_enable)
  1081. wcd938x_rx_connect_port(component, COMP_R, true);
  1082. break;
  1083. case SND_SOC_DAPM_POST_PMD:
  1084. wcd938x_rx_connect_port(component, HPH_R, false);
  1085. if (wcd938x->comp2_enable)
  1086. wcd938x_rx_connect_port(component, COMP_R, false);
  1087. wcd938x_rx_clk_disable(component);
  1088. snd_soc_component_update_bits(component,
  1089. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1090. 0x02, 0x00);
  1091. break;
  1092. };
  1093. return 0;
  1094. }
  1095. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1096. struct snd_kcontrol *kcontrol,
  1097. int event)
  1098. {
  1099. struct snd_soc_component *component =
  1100. snd_soc_dapm_to_component(w->dapm);
  1101. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1102. w->name, event);
  1103. switch (event) {
  1104. case SND_SOC_DAPM_PRE_PMU:
  1105. wcd938x_rx_connect_port(component, LO, true);
  1106. break;
  1107. case SND_SOC_DAPM_POST_PMD:
  1108. wcd938x_rx_connect_port(component, LO, false);
  1109. /* 6 msec delay as per HW requirement */
  1110. usleep_range(6000, 6010);
  1111. wcd938x_rx_clk_disable(component);
  1112. snd_soc_component_update_bits(component,
  1113. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1114. break;
  1115. }
  1116. return 0;
  1117. }
  1118. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1119. struct snd_kcontrol *kcontrol,
  1120. int event)
  1121. {
  1122. struct snd_soc_component *component =
  1123. snd_soc_dapm_to_component(w->dapm);
  1124. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1125. u16 dmic_clk_reg, dmic_clk_en_reg;
  1126. s32 *dmic_clk_cnt;
  1127. u8 dmic_ctl_shift = 0;
  1128. u8 dmic_clk_shift = 0;
  1129. u8 dmic_clk_mask = 0;
  1130. u16 dmic2_left_en = 0;
  1131. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1132. w->name, event);
  1133. switch (w->shift) {
  1134. case 0:
  1135. case 1:
  1136. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1137. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1138. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1139. dmic_clk_mask = 0x0F;
  1140. dmic_clk_shift = 0x00;
  1141. dmic_ctl_shift = 0x00;
  1142. break;
  1143. case 2:
  1144. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1145. case 3:
  1146. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1147. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1148. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1149. dmic_clk_mask = 0xF0;
  1150. dmic_clk_shift = 0x04;
  1151. dmic_ctl_shift = 0x01;
  1152. break;
  1153. case 4:
  1154. case 5:
  1155. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1156. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1157. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1158. dmic_clk_mask = 0x0F;
  1159. dmic_clk_shift = 0x00;
  1160. dmic_ctl_shift = 0x02;
  1161. break;
  1162. case 6:
  1163. case 7:
  1164. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1165. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1166. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1167. dmic_clk_mask = 0xF0;
  1168. dmic_clk_shift = 0x04;
  1169. dmic_ctl_shift = 0x03;
  1170. break;
  1171. default:
  1172. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1173. __func__);
  1174. return -EINVAL;
  1175. };
  1176. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1177. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1178. switch (event) {
  1179. case SND_SOC_DAPM_PRE_PMU:
  1180. snd_soc_component_update_bits(component,
  1181. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1182. (0x01 << dmic_ctl_shift), 0x00);
  1183. /* 250us sleep as per HW requirement */
  1184. usleep_range(250, 260);
  1185. if (dmic2_left_en)
  1186. snd_soc_component_update_bits(component,
  1187. dmic2_left_en, 0x80, 0x80);
  1188. /* Setting DMIC clock rate to 2.4MHz */
  1189. snd_soc_component_update_bits(component,
  1190. dmic_clk_reg, dmic_clk_mask,
  1191. (0x03 << dmic_clk_shift));
  1192. snd_soc_component_update_bits(component,
  1193. dmic_clk_en_reg, 0x08, 0x08);
  1194. /* enable clock scaling */
  1195. snd_soc_component_update_bits(component,
  1196. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1197. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1198. break;
  1199. case SND_SOC_DAPM_POST_PMD:
  1200. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1201. snd_soc_component_update_bits(component,
  1202. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1203. (0x01 << dmic_ctl_shift),
  1204. (0x01 << dmic_ctl_shift));
  1205. if (dmic2_left_en)
  1206. snd_soc_component_update_bits(component,
  1207. dmic2_left_en, 0x80, 0x00);
  1208. snd_soc_component_update_bits(component,
  1209. dmic_clk_en_reg, 0x08, 0x00);
  1210. break;
  1211. };
  1212. return 0;
  1213. }
  1214. /*
  1215. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1216. * @micb_mv: micbias in mv
  1217. *
  1218. * return register value converted
  1219. */
  1220. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1221. {
  1222. /* min micbias voltage is 1V and maximum is 2.85V */
  1223. if (micb_mv < 1000 || micb_mv > 2850) {
  1224. pr_err("%s: unsupported micbias voltage\n", __func__);
  1225. return -EINVAL;
  1226. }
  1227. return (micb_mv - 1000) / 50;
  1228. }
  1229. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1230. /*
  1231. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1232. * @component: handle to snd_soc_component *
  1233. * @req_volt: micbias voltage to be set
  1234. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1235. *
  1236. * return 0 if adjustment is success or error code in case of failure
  1237. */
  1238. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1239. int req_volt, int micb_num)
  1240. {
  1241. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1242. int cur_vout_ctl, req_vout_ctl;
  1243. int micb_reg, micb_val, micb_en;
  1244. int ret = 0;
  1245. switch (micb_num) {
  1246. case MIC_BIAS_1:
  1247. micb_reg = WCD938X_ANA_MICB1;
  1248. break;
  1249. case MIC_BIAS_2:
  1250. micb_reg = WCD938X_ANA_MICB2;
  1251. break;
  1252. case MIC_BIAS_3:
  1253. micb_reg = WCD938X_ANA_MICB3;
  1254. break;
  1255. case MIC_BIAS_4:
  1256. micb_reg = WCD938X_ANA_MICB4;
  1257. break;
  1258. default:
  1259. return -EINVAL;
  1260. }
  1261. mutex_lock(&wcd938x->micb_lock);
  1262. /*
  1263. * If requested micbias voltage is same as current micbias
  1264. * voltage, then just return. Otherwise, adjust voltage as
  1265. * per requested value. If micbias is already enabled, then
  1266. * to avoid slow micbias ramp-up or down enable pull-up
  1267. * momentarily, change the micbias value and then re-enable
  1268. * micbias.
  1269. */
  1270. micb_val = snd_soc_component_read32(component, micb_reg);
  1271. micb_en = (micb_val & 0xC0) >> 6;
  1272. cur_vout_ctl = micb_val & 0x3F;
  1273. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1274. if (req_vout_ctl < 0) {
  1275. ret = -EINVAL;
  1276. goto exit;
  1277. }
  1278. if (cur_vout_ctl == req_vout_ctl) {
  1279. ret = 0;
  1280. goto exit;
  1281. }
  1282. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1283. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1284. req_volt, micb_en);
  1285. if (micb_en == 0x1)
  1286. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1287. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1288. if (micb_en == 0x1) {
  1289. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1290. /*
  1291. * Add 2ms delay as per HW requirement after enabling
  1292. * micbias
  1293. */
  1294. usleep_range(2000, 2100);
  1295. }
  1296. exit:
  1297. mutex_unlock(&wcd938x->micb_lock);
  1298. return ret;
  1299. }
  1300. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1301. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1302. struct snd_kcontrol *kcontrol,
  1303. int event)
  1304. {
  1305. struct snd_soc_component *component =
  1306. snd_soc_dapm_to_component(w->dapm);
  1307. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1308. int ret = 0;
  1309. int bank = 0;
  1310. int mode = 0;
  1311. bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1312. wcd938x->tx_swr_dev->dev_num);
  1313. wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
  1314. wcd938x->tx_swr_dev->dev_num, bank);
  1315. switch (event) {
  1316. case SND_SOC_DAPM_PRE_PMU:
  1317. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1318. wcd938x->tx_swr_dev->dev_num,
  1319. true);
  1320. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1321. mode |= wcd938x->tx_mode[WCD_ADC1];
  1322. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1323. mode |= wcd938x->tx_mode[WCD_ADC2];
  1324. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1325. mode |= wcd938x->tx_mode[WCD_ADC3];
  1326. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1327. mode |= wcd938x->tx_mode[WCD_ADC4];
  1328. wcd938x_set_swr_clk_rate(component, mode, bank);
  1329. break;
  1330. case SND_SOC_DAPM_POST_PMD:
  1331. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1332. wcd938x->tx_swr_dev->dev_num,
  1333. false);
  1334. wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
  1335. break;
  1336. };
  1337. return ret;
  1338. }
  1339. static int wcd938x_get_adc_mode(int val)
  1340. {
  1341. int ret = 0;
  1342. switch (val) {
  1343. case ADC_MODE_INVALID:
  1344. ret = ADC_MODE_VAL_NORMAL;
  1345. break;
  1346. case ADC_MODE_HIFI:
  1347. ret = ADC_MODE_VAL_HIFI;
  1348. break;
  1349. case ADC_MODE_LO_HIF:
  1350. ret = ADC_MODE_VAL_LO_HIF;
  1351. break;
  1352. case ADC_MODE_NORMAL:
  1353. ret = ADC_MODE_VAL_NORMAL;
  1354. break;
  1355. case ADC_MODE_LP:
  1356. ret = ADC_MODE_VAL_LP;
  1357. break;
  1358. case ADC_MODE_ULP1:
  1359. ret = ADC_MODE_VAL_ULP1;
  1360. break;
  1361. case ADC_MODE_ULP2:
  1362. ret = ADC_MODE_VAL_ULP2;
  1363. break;
  1364. default:
  1365. ret = -EINVAL;
  1366. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1367. break;
  1368. }
  1369. return ret;
  1370. }
  1371. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1372. struct snd_kcontrol *kcontrol,
  1373. int event){
  1374. struct snd_soc_component *component =
  1375. snd_soc_dapm_to_component(w->dapm);
  1376. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1377. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1378. w->name, event);
  1379. switch (event) {
  1380. case SND_SOC_DAPM_PRE_PMU:
  1381. snd_soc_component_update_bits(component,
  1382. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1383. snd_soc_component_update_bits(component,
  1384. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1385. set_bit(w->shift, &wcd938x->status_mask);
  1386. /* Enable BCS for Headset mic */
  1387. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1388. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1389. wcd938x_tx_connect_port(component, MBHC, true);
  1390. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1391. }
  1392. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1393. break;
  1394. case SND_SOC_DAPM_POST_PMD:
  1395. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1396. if (w->shift == 1 &&
  1397. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1398. wcd938x_tx_connect_port(component, MBHC, false);
  1399. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1400. }
  1401. snd_soc_component_update_bits(component,
  1402. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1403. clear_bit(w->shift, &wcd938x->status_mask);
  1404. break;
  1405. };
  1406. return 0;
  1407. }
  1408. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1409. bool bcs_disable)
  1410. {
  1411. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1412. if (wcd938x->update_wcd_event) {
  1413. if (bcs_disable)
  1414. wcd938x->update_wcd_event(wcd938x->handle,
  1415. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1416. else
  1417. wcd938x->update_wcd_event(wcd938x->handle,
  1418. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1419. }
  1420. }
  1421. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1422. int channel, int mode)
  1423. {
  1424. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1425. int ret = 0;
  1426. switch (channel) {
  1427. case 0:
  1428. reg = WCD938X_ANA_TX_CH2;
  1429. mask = 0x40;
  1430. break;
  1431. case 1:
  1432. reg = WCD938X_ANA_TX_CH2;
  1433. mask = 0x20;
  1434. break;
  1435. case 2:
  1436. reg = WCD938X_ANA_TX_CH4;
  1437. mask = 0x40;
  1438. break;
  1439. case 3:
  1440. reg = WCD938X_ANA_TX_CH4;
  1441. mask = 0x20;
  1442. break;
  1443. default:
  1444. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1445. ret = -EINVAL;
  1446. break;
  1447. }
  1448. if (!mode)
  1449. val = 0x00;
  1450. else
  1451. val = mask;
  1452. if (!ret)
  1453. snd_soc_component_update_bits(component, reg, mask, val);
  1454. return ret;
  1455. }
  1456. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1457. struct snd_kcontrol *kcontrol, int event)
  1458. {
  1459. struct snd_soc_component *component =
  1460. snd_soc_dapm_to_component(w->dapm);
  1461. int mode;
  1462. int ret = 0;
  1463. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1464. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1465. w->name, event);
  1466. switch (event) {
  1467. case SND_SOC_DAPM_PRE_PMU:
  1468. snd_soc_component_update_bits(component,
  1469. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1470. snd_soc_component_update_bits(component,
  1471. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1472. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1473. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1474. if (mode < 0) {
  1475. dev_info(component->dev,
  1476. "%s: invalid mode, setting to normal mode\n",
  1477. __func__);
  1478. mode = ADC_MODE_VAL_NORMAL;
  1479. }
  1480. switch (w->shift) {
  1481. case 0:
  1482. snd_soc_component_update_bits(component,
  1483. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1484. mode);
  1485. snd_soc_component_update_bits(component,
  1486. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1487. break;
  1488. case 1:
  1489. snd_soc_component_update_bits(component,
  1490. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1491. mode << 4);
  1492. snd_soc_component_update_bits(component,
  1493. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1494. break;
  1495. case 2:
  1496. snd_soc_component_update_bits(component,
  1497. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1498. mode);
  1499. snd_soc_component_update_bits(component,
  1500. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1501. break;
  1502. case 3:
  1503. snd_soc_component_update_bits(component,
  1504. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1505. mode << 4);
  1506. snd_soc_component_update_bits(component,
  1507. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1508. break;
  1509. default:
  1510. break;
  1511. }
  1512. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1513. break;
  1514. case SND_SOC_DAPM_POST_PMD:
  1515. switch (w->shift) {
  1516. case 0:
  1517. snd_soc_component_update_bits(component,
  1518. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1519. 0x00);
  1520. snd_soc_component_update_bits(component,
  1521. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1522. break;
  1523. case 1:
  1524. snd_soc_component_update_bits(component,
  1525. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1526. 0x00);
  1527. snd_soc_component_update_bits(component,
  1528. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1529. break;
  1530. case 2:
  1531. snd_soc_component_update_bits(component,
  1532. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1533. 0x00);
  1534. snd_soc_component_update_bits(component,
  1535. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1536. break;
  1537. case 3:
  1538. snd_soc_component_update_bits(component,
  1539. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1540. 0x00);
  1541. snd_soc_component_update_bits(component,
  1542. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1543. break;
  1544. default:
  1545. break;
  1546. }
  1547. snd_soc_component_update_bits(component,
  1548. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1549. break;
  1550. };
  1551. return ret;
  1552. }
  1553. int wcd938x_micbias_control(struct snd_soc_component *component,
  1554. int micb_num, int req, bool is_dapm)
  1555. {
  1556. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1557. int micb_index = micb_num - 1;
  1558. u16 micb_reg;
  1559. int pre_off_event = 0, post_off_event = 0;
  1560. int post_on_event = 0, post_dapm_off = 0;
  1561. int post_dapm_on = 0;
  1562. int ret = 0;
  1563. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1564. dev_err(component->dev,
  1565. "%s: Invalid micbias index, micb_ind:%d\n",
  1566. __func__, micb_index);
  1567. return -EINVAL;
  1568. }
  1569. if (NULL == wcd938x) {
  1570. dev_err(component->dev,
  1571. "%s: wcd938x private data is NULL\n", __func__);
  1572. return -EINVAL;
  1573. }
  1574. switch (micb_num) {
  1575. case MIC_BIAS_1:
  1576. micb_reg = WCD938X_ANA_MICB1;
  1577. break;
  1578. case MIC_BIAS_2:
  1579. micb_reg = WCD938X_ANA_MICB2;
  1580. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1581. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1582. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1583. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1584. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1585. break;
  1586. case MIC_BIAS_3:
  1587. micb_reg = WCD938X_ANA_MICB3;
  1588. break;
  1589. case MIC_BIAS_4:
  1590. micb_reg = WCD938X_ANA_MICB4;
  1591. break;
  1592. default:
  1593. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1594. __func__, micb_num);
  1595. return -EINVAL;
  1596. };
  1597. mutex_lock(&wcd938x->micb_lock);
  1598. switch (req) {
  1599. case MICB_PULLUP_ENABLE:
  1600. if (!wcd938x->dev_up) {
  1601. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1602. __func__, req);
  1603. ret = -ENODEV;
  1604. goto done;
  1605. }
  1606. wcd938x->pullup_ref[micb_index]++;
  1607. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1608. (wcd938x->micb_ref[micb_index] == 0))
  1609. snd_soc_component_update_bits(component, micb_reg,
  1610. 0xC0, 0x80);
  1611. break;
  1612. case MICB_PULLUP_DISABLE:
  1613. if (wcd938x->pullup_ref[micb_index] > 0)
  1614. wcd938x->pullup_ref[micb_index]--;
  1615. if (!wcd938x->dev_up) {
  1616. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1617. __func__, req);
  1618. ret = -ENODEV;
  1619. goto done;
  1620. }
  1621. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1622. (wcd938x->micb_ref[micb_index] == 0))
  1623. snd_soc_component_update_bits(component, micb_reg,
  1624. 0xC0, 0x00);
  1625. break;
  1626. case MICB_ENABLE:
  1627. if (!wcd938x->dev_up) {
  1628. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1629. __func__, req);
  1630. ret = -ENODEV;
  1631. goto done;
  1632. }
  1633. wcd938x->micb_ref[micb_index]++;
  1634. if (wcd938x->micb_ref[micb_index] == 1) {
  1635. snd_soc_component_update_bits(component,
  1636. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1637. snd_soc_component_update_bits(component,
  1638. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1639. snd_soc_component_update_bits(component,
  1640. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1641. snd_soc_component_update_bits(component,
  1642. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1643. snd_soc_component_update_bits(component,
  1644. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1645. snd_soc_component_update_bits(component,
  1646. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1647. snd_soc_component_update_bits(component,
  1648. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1649. snd_soc_component_update_bits(component,
  1650. micb_reg, 0xC0, 0x40);
  1651. if (post_on_event)
  1652. blocking_notifier_call_chain(
  1653. &wcd938x->mbhc->notifier,
  1654. post_on_event,
  1655. &wcd938x->mbhc->wcd_mbhc);
  1656. }
  1657. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1658. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1659. post_dapm_on,
  1660. &wcd938x->mbhc->wcd_mbhc);
  1661. break;
  1662. case MICB_DISABLE:
  1663. if (wcd938x->micb_ref[micb_index] > 0)
  1664. wcd938x->micb_ref[micb_index]--;
  1665. if (!wcd938x->dev_up) {
  1666. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1667. __func__, req);
  1668. ret = -ENODEV;
  1669. goto done;
  1670. }
  1671. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1672. (wcd938x->pullup_ref[micb_index] > 0))
  1673. snd_soc_component_update_bits(component, micb_reg,
  1674. 0xC0, 0x80);
  1675. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1676. (wcd938x->pullup_ref[micb_index] == 0)) {
  1677. if (pre_off_event && wcd938x->mbhc)
  1678. blocking_notifier_call_chain(
  1679. &wcd938x->mbhc->notifier,
  1680. pre_off_event,
  1681. &wcd938x->mbhc->wcd_mbhc);
  1682. snd_soc_component_update_bits(component, micb_reg,
  1683. 0xC0, 0x00);
  1684. if (post_off_event && wcd938x->mbhc)
  1685. blocking_notifier_call_chain(
  1686. &wcd938x->mbhc->notifier,
  1687. post_off_event,
  1688. &wcd938x->mbhc->wcd_mbhc);
  1689. }
  1690. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1691. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1692. post_dapm_off,
  1693. &wcd938x->mbhc->wcd_mbhc);
  1694. break;
  1695. };
  1696. dev_dbg(component->dev,
  1697. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1698. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1699. wcd938x->pullup_ref[micb_index]);
  1700. done:
  1701. mutex_unlock(&wcd938x->micb_lock);
  1702. return ret;
  1703. }
  1704. EXPORT_SYMBOL(wcd938x_micbias_control);
  1705. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1706. {
  1707. int ret = 0;
  1708. uint8_t devnum = 0;
  1709. int num_retry = NUM_ATTEMPTS;
  1710. do {
  1711. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1712. if (ret) {
  1713. dev_err(&swr_dev->dev,
  1714. "%s get devnum %d for dev addr %lx failed\n",
  1715. __func__, devnum, swr_dev->addr);
  1716. /* retry after 1ms */
  1717. usleep_range(1000, 1010);
  1718. }
  1719. } while (ret && --num_retry);
  1720. swr_dev->dev_num = devnum;
  1721. return 0;
  1722. }
  1723. static int wcd938x_event_notify(struct notifier_block *block,
  1724. unsigned long val,
  1725. void *data)
  1726. {
  1727. u16 event = (val & 0xffff);
  1728. int ret = 0;
  1729. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1730. struct snd_soc_component *component = wcd938x->component;
  1731. struct wcd_mbhc *mbhc;
  1732. switch (event) {
  1733. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1734. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1735. snd_soc_component_update_bits(component,
  1736. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1737. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1738. }
  1739. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1740. snd_soc_component_update_bits(component,
  1741. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1742. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1743. }
  1744. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1745. snd_soc_component_update_bits(component,
  1746. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1747. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1748. }
  1749. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1750. snd_soc_component_update_bits(component,
  1751. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1752. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1753. }
  1754. break;
  1755. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1756. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1757. 0xC0, 0x00);
  1758. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1759. 0x80, 0x00);
  1760. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1761. 0x80, 0x00);
  1762. break;
  1763. case BOLERO_WCD_EVT_SSR_DOWN:
  1764. wcd938x->dev_up = false;
  1765. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1766. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1767. wcd938x_reset_low(wcd938x->dev);
  1768. break;
  1769. case BOLERO_WCD_EVT_SSR_UP:
  1770. wcd938x_reset(wcd938x->dev);
  1771. /* allow reset to take effect */
  1772. usleep_range(10000, 10010);
  1773. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1774. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1775. wcd938x_init_reg(component);
  1776. regcache_mark_dirty(wcd938x->regmap);
  1777. regcache_sync(wcd938x->regmap);
  1778. /* Initialize MBHC module */
  1779. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1780. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1781. if (ret) {
  1782. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1783. __func__);
  1784. } else {
  1785. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1786. }
  1787. wcd938x->dev_up = true;
  1788. break;
  1789. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1790. snd_soc_component_update_bits(component,
  1791. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1792. ((val >> 0x10) << 0x01));
  1793. break;
  1794. default:
  1795. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1796. break;
  1797. }
  1798. return 0;
  1799. }
  1800. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1801. int event)
  1802. {
  1803. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1804. int micb_num;
  1805. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1806. __func__, w->name, event);
  1807. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1808. micb_num = MIC_BIAS_1;
  1809. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1810. micb_num = MIC_BIAS_2;
  1811. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1812. micb_num = MIC_BIAS_3;
  1813. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1814. micb_num = MIC_BIAS_4;
  1815. else
  1816. return -EINVAL;
  1817. switch (event) {
  1818. case SND_SOC_DAPM_PRE_PMU:
  1819. wcd938x_micbias_control(component, micb_num,
  1820. MICB_ENABLE, true);
  1821. break;
  1822. case SND_SOC_DAPM_POST_PMU:
  1823. /* 1 msec delay as per HW requirement */
  1824. usleep_range(1000, 1100);
  1825. break;
  1826. case SND_SOC_DAPM_POST_PMD:
  1827. wcd938x_micbias_control(component, micb_num,
  1828. MICB_DISABLE, true);
  1829. break;
  1830. };
  1831. return 0;
  1832. }
  1833. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1834. struct snd_kcontrol *kcontrol,
  1835. int event)
  1836. {
  1837. return __wcd938x_codec_enable_micbias(w, event);
  1838. }
  1839. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1840. int event)
  1841. {
  1842. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1843. int micb_num;
  1844. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1845. __func__, w->name, event);
  1846. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1847. micb_num = MIC_BIAS_1;
  1848. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1849. micb_num = MIC_BIAS_2;
  1850. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1851. micb_num = MIC_BIAS_3;
  1852. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1853. micb_num = MIC_BIAS_4;
  1854. else
  1855. return -EINVAL;
  1856. switch (event) {
  1857. case SND_SOC_DAPM_PRE_PMU:
  1858. wcd938x_micbias_control(component, micb_num,
  1859. MICB_PULLUP_ENABLE, true);
  1860. break;
  1861. case SND_SOC_DAPM_POST_PMU:
  1862. /* 1 msec delay as per HW requirement */
  1863. usleep_range(1000, 1100);
  1864. break;
  1865. case SND_SOC_DAPM_POST_PMD:
  1866. wcd938x_micbias_control(component, micb_num,
  1867. MICB_PULLUP_DISABLE, true);
  1868. break;
  1869. };
  1870. return 0;
  1871. }
  1872. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1873. struct snd_kcontrol *kcontrol,
  1874. int event)
  1875. {
  1876. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1877. }
  1878. static int wcd938x_wakeup(void *handle, bool enable)
  1879. {
  1880. struct wcd938x_priv *priv;
  1881. int ret = 0;
  1882. if (!handle) {
  1883. pr_err("%s: NULL handle\n", __func__);
  1884. return -EINVAL;
  1885. }
  1886. priv = (struct wcd938x_priv *)handle;
  1887. if (!priv->tx_swr_dev) {
  1888. pr_err("%s: tx swr dev is NULL\n", __func__);
  1889. return -EINVAL;
  1890. }
  1891. mutex_lock(&priv->wakeup_lock);
  1892. if (enable)
  1893. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  1894. else
  1895. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  1896. mutex_unlock(&priv->wakeup_lock);
  1897. return ret;
  1898. }
  1899. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  1900. struct snd_kcontrol *kcontrol,
  1901. int event)
  1902. {
  1903. int ret = 0;
  1904. struct snd_soc_component *component =
  1905. snd_soc_dapm_to_component(w->dapm);
  1906. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1907. switch (event) {
  1908. case SND_SOC_DAPM_PRE_PMU:
  1909. wcd938x_wakeup(wcd938x, true);
  1910. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  1911. wcd938x_wakeup(wcd938x, false);
  1912. break;
  1913. case SND_SOC_DAPM_POST_PMD:
  1914. wcd938x_wakeup(wcd938x, true);
  1915. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  1916. wcd938x_wakeup(wcd938x, false);
  1917. break;
  1918. }
  1919. return ret;
  1920. }
  1921. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  1922. int micb_num, int req)
  1923. {
  1924. int micb_index = micb_num - 1;
  1925. u16 micb_reg;
  1926. if (NULL == wcd938x) {
  1927. pr_err("%s: wcd938x private data is NULL\n", __func__);
  1928. return -EINVAL;
  1929. }
  1930. switch (micb_num) {
  1931. case MIC_BIAS_1:
  1932. micb_reg = WCD938X_ANA_MICB1;
  1933. break;
  1934. case MIC_BIAS_2:
  1935. micb_reg = WCD938X_ANA_MICB2;
  1936. break;
  1937. case MIC_BIAS_3:
  1938. micb_reg = WCD938X_ANA_MICB3;
  1939. break;
  1940. case MIC_BIAS_4:
  1941. micb_reg = WCD938X_ANA_MICB4;
  1942. break;
  1943. default:
  1944. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  1945. return -EINVAL;
  1946. };
  1947. mutex_lock(&wcd938x->micb_lock);
  1948. switch (req) {
  1949. case MICB_ENABLE:
  1950. wcd938x->micb_ref[micb_index]++;
  1951. if (wcd938x->micb_ref[micb_index] == 1) {
  1952. regmap_update_bits(wcd938x->regmap,
  1953. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1954. regmap_update_bits(wcd938x->regmap,
  1955. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1956. regmap_update_bits(wcd938x->regmap,
  1957. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1958. regmap_update_bits(wcd938x->regmap,
  1959. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1960. regmap_update_bits(wcd938x->regmap,
  1961. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1962. regmap_update_bits(wcd938x->regmap,
  1963. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1964. regmap_update_bits(wcd938x->regmap,
  1965. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1966. regmap_update_bits(wcd938x->regmap,
  1967. micb_reg, 0xC0, 0x40);
  1968. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  1969. }
  1970. break;
  1971. case MICB_PULLUP_ENABLE:
  1972. wcd938x->pullup_ref[micb_index]++;
  1973. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1974. (wcd938x->micb_ref[micb_index] == 0))
  1975. regmap_update_bits(wcd938x->regmap, micb_reg,
  1976. 0xC0, 0x80);
  1977. break;
  1978. case MICB_PULLUP_DISABLE:
  1979. if (wcd938x->pullup_ref[micb_index] > 0)
  1980. wcd938x->pullup_ref[micb_index]--;
  1981. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1982. (wcd938x->micb_ref[micb_index] == 0))
  1983. regmap_update_bits(wcd938x->regmap, micb_reg,
  1984. 0xC0, 0x00);
  1985. break;
  1986. case MICB_DISABLE:
  1987. if (wcd938x->micb_ref[micb_index] > 0)
  1988. wcd938x->micb_ref[micb_index]--;
  1989. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1990. (wcd938x->pullup_ref[micb_index] > 0))
  1991. regmap_update_bits(wcd938x->regmap, micb_reg,
  1992. 0xC0, 0x80);
  1993. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1994. (wcd938x->pullup_ref[micb_index] == 0))
  1995. regmap_update_bits(wcd938x->regmap, micb_reg,
  1996. 0xC0, 0x00);
  1997. break;
  1998. };
  1999. mutex_unlock(&wcd938x->micb_lock);
  2000. return 0;
  2001. }
  2002. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2003. int event, int micb_num)
  2004. {
  2005. struct wcd938x_priv *wcd938x_priv = NULL;
  2006. if(NULL == component) {
  2007. pr_err("%s: wcd938x component is NULL\n", __func__);
  2008. return -EINVAL;
  2009. }
  2010. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2011. pr_err("%s: invalid event: %d\n", __func__, event);
  2012. return -EINVAL;
  2013. }
  2014. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2015. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2016. return -EINVAL;
  2017. }
  2018. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2019. switch (event) {
  2020. case SND_SOC_DAPM_PRE_PMU:
  2021. wcd938x_wakeup(wcd938x_priv, true);
  2022. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2023. wcd938x_wakeup(wcd938x_priv, false);
  2024. break;
  2025. case SND_SOC_DAPM_POST_PMD:
  2026. wcd938x_wakeup(wcd938x_priv, true);
  2027. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2028. wcd938x_wakeup(wcd938x_priv, false);
  2029. break;
  2030. }
  2031. return 0;
  2032. }
  2033. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2034. static inline int wcd938x_tx_path_get(const char *wname,
  2035. unsigned int *path_num)
  2036. {
  2037. int ret = 0;
  2038. char *widget_name = NULL;
  2039. char *w_name = NULL;
  2040. char *path_num_char = NULL;
  2041. char *path_name = NULL;
  2042. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2043. if (!widget_name)
  2044. return -EINVAL;
  2045. w_name = widget_name;
  2046. path_name = strsep(&widget_name, " ");
  2047. if (!path_name) {
  2048. pr_err("%s: Invalid widget name = %s\n",
  2049. __func__, widget_name);
  2050. ret = -EINVAL;
  2051. goto err;
  2052. }
  2053. path_num_char = strpbrk(path_name, "0123");
  2054. if (!path_num_char) {
  2055. pr_err("%s: tx path index not found\n",
  2056. __func__);
  2057. ret = -EINVAL;
  2058. goto err;
  2059. }
  2060. ret = kstrtouint(path_num_char, 10, path_num);
  2061. if (ret < 0)
  2062. pr_err("%s: Invalid tx path = %s\n",
  2063. __func__, w_name);
  2064. err:
  2065. kfree(w_name);
  2066. return ret;
  2067. }
  2068. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2069. struct snd_ctl_elem_value *ucontrol)
  2070. {
  2071. struct snd_soc_component *component =
  2072. snd_soc_kcontrol_component(kcontrol);
  2073. struct wcd938x_priv *wcd938x = NULL;
  2074. int ret = 0;
  2075. unsigned int path = 0;
  2076. if (!component)
  2077. return -EINVAL;
  2078. wcd938x = snd_soc_component_get_drvdata(component);
  2079. if (!wcd938x)
  2080. return -EINVAL;
  2081. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2082. if (ret < 0)
  2083. return ret;
  2084. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2085. return 0;
  2086. }
  2087. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2088. struct snd_ctl_elem_value *ucontrol)
  2089. {
  2090. struct snd_soc_component *component =
  2091. snd_soc_kcontrol_component(kcontrol);
  2092. struct wcd938x_priv *wcd938x = NULL;
  2093. u32 mode_val;
  2094. unsigned int path = 0;
  2095. int ret = 0;
  2096. if (!component)
  2097. return -EINVAL;
  2098. wcd938x = snd_soc_component_get_drvdata(component);
  2099. if (!wcd938x)
  2100. return -EINVAL;
  2101. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2102. if (ret)
  2103. return ret;
  2104. mode_val = ucontrol->value.enumerated.item[0];
  2105. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2106. wcd938x->tx_mode[path] = mode_val;
  2107. return 0;
  2108. }
  2109. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2110. struct snd_ctl_elem_value *ucontrol)
  2111. {
  2112. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2113. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2114. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2115. return 0;
  2116. }
  2117. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2118. struct snd_ctl_elem_value *ucontrol)
  2119. {
  2120. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2121. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2122. u32 mode_val;
  2123. mode_val = ucontrol->value.enumerated.item[0];
  2124. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2125. if (wcd938x->variant == WCD9380) {
  2126. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2127. dev_info(component->dev,
  2128. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2129. __func__);
  2130. mode_val = CLS_H_ULP;
  2131. }
  2132. }
  2133. if (mode_val == CLS_H_NORMAL) {
  2134. dev_info(component->dev,
  2135. "%s:Invalid HPH Mode, default to class_AB\n",
  2136. __func__);
  2137. mode_val = CLS_H_ULP;
  2138. }
  2139. wcd938x->hph_mode = mode_val;
  2140. return 0;
  2141. }
  2142. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2143. struct snd_ctl_elem_value *ucontrol)
  2144. {
  2145. u8 ear_pa_gain = 0;
  2146. struct snd_soc_component *component =
  2147. snd_soc_kcontrol_component(kcontrol);
  2148. ear_pa_gain = snd_soc_component_read32(component,
  2149. WCD938X_ANA_EAR_COMPANDER_CTL);
  2150. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2151. ucontrol->value.integer.value[0] = ear_pa_gain;
  2152. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2153. ear_pa_gain);
  2154. return 0;
  2155. }
  2156. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2157. struct snd_ctl_elem_value *ucontrol)
  2158. {
  2159. u8 ear_pa_gain = 0;
  2160. struct snd_soc_component *component =
  2161. snd_soc_kcontrol_component(kcontrol);
  2162. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2163. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2164. __func__, ucontrol->value.integer.value[0]);
  2165. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2166. if (!wcd938x->comp1_enable) {
  2167. snd_soc_component_update_bits(component,
  2168. WCD938X_ANA_EAR_COMPANDER_CTL,
  2169. 0x7C, ear_pa_gain);
  2170. }
  2171. return 0;
  2172. }
  2173. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2174. struct snd_ctl_elem_value *ucontrol)
  2175. {
  2176. struct snd_soc_component *component =
  2177. snd_soc_kcontrol_component(kcontrol);
  2178. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2179. bool hphr;
  2180. struct soc_multi_mixer_control *mc;
  2181. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2182. hphr = mc->shift;
  2183. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2184. wcd938x->comp1_enable;
  2185. return 0;
  2186. }
  2187. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2188. struct snd_ctl_elem_value *ucontrol)
  2189. {
  2190. struct snd_soc_component *component =
  2191. snd_soc_kcontrol_component(kcontrol);
  2192. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2193. int value = ucontrol->value.integer.value[0];
  2194. bool hphr;
  2195. struct soc_multi_mixer_control *mc;
  2196. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2197. hphr = mc->shift;
  2198. if (hphr)
  2199. wcd938x->comp2_enable = value;
  2200. else
  2201. wcd938x->comp1_enable = value;
  2202. return 0;
  2203. }
  2204. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2205. struct snd_ctl_elem_value *ucontrol)
  2206. {
  2207. struct snd_soc_component *component =
  2208. snd_soc_kcontrol_component(kcontrol);
  2209. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2210. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2211. return 0;
  2212. }
  2213. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2214. struct snd_ctl_elem_value *ucontrol)
  2215. {
  2216. struct snd_soc_component *component =
  2217. snd_soc_kcontrol_component(kcontrol);
  2218. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2219. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2220. return 0;
  2221. }
  2222. const char * const tx_master_ch_text[] = {
  2223. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2224. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2225. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2226. "SWRM_PCM_IN",
  2227. };
  2228. const struct soc_enum tx_master_ch_enum =
  2229. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2230. tx_master_ch_text);
  2231. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2232. {
  2233. u8 ch_type = 0;
  2234. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2235. ch_type = ADC1;
  2236. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2237. ch_type = ADC2;
  2238. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2239. ch_type = ADC3;
  2240. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2241. ch_type = ADC4;
  2242. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2243. ch_type = DMIC0;
  2244. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2245. ch_type = DMIC1;
  2246. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2247. ch_type = MBHC;
  2248. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2249. ch_type = DMIC2;
  2250. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2251. ch_type = DMIC3;
  2252. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2253. ch_type = DMIC4;
  2254. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2255. ch_type = DMIC5;
  2256. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2257. ch_type = DMIC6;
  2258. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2259. ch_type = DMIC7;
  2260. else
  2261. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2262. if (ch_type)
  2263. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2264. else
  2265. *ch_idx = -EINVAL;
  2266. }
  2267. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2268. struct snd_ctl_elem_value *ucontrol)
  2269. {
  2270. struct snd_soc_component *component =
  2271. snd_soc_kcontrol_component(kcontrol);
  2272. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2273. int slave_ch_idx;
  2274. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2275. if (slave_ch_idx != -EINVAL)
  2276. ucontrol->value.integer.value[0] =
  2277. wcd938x_slave_get_master_ch_val(
  2278. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2279. return 0;
  2280. }
  2281. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2282. struct snd_ctl_elem_value *ucontrol)
  2283. {
  2284. struct snd_soc_component *component =
  2285. snd_soc_kcontrol_component(kcontrol);
  2286. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2287. int slave_ch_idx;
  2288. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2289. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2290. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2291. __func__, ucontrol->value.enumerated.item[0]);
  2292. if (slave_ch_idx != -EINVAL)
  2293. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2294. wcd938x_slave_get_master_ch(
  2295. ucontrol->value.enumerated.item[0]);
  2296. return 0;
  2297. }
  2298. static const char * const tx_mode_mux_text_wcd9380[] = {
  2299. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2300. };
  2301. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2302. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2303. tx_mode_mux_text_wcd9380);
  2304. static const char * const tx_mode_mux_text[] = {
  2305. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2306. "ADC_ULP1", "ADC_ULP2",
  2307. };
  2308. static const struct soc_enum tx_mode_mux_enum =
  2309. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2310. tx_mode_mux_text);
  2311. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2312. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2313. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2314. "CLS_AB_LOHIFI",
  2315. };
  2316. static const char * const wcd938x_ear_pa_gain_text[] = {
  2317. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2318. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2319. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2320. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2321. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2322. };
  2323. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2324. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2325. rx_hph_mode_mux_text_wcd9380);
  2326. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2327. wcd938x_ear_pa_gain_text);
  2328. static const char * const rx_hph_mode_mux_text[] = {
  2329. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2330. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2331. };
  2332. static const struct soc_enum rx_hph_mode_mux_enum =
  2333. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2334. rx_hph_mode_mux_text);
  2335. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2336. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2337. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2338. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2339. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2340. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2341. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2342. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2343. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2344. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2345. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2346. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2347. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2348. };
  2349. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2350. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2351. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2352. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2353. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2354. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2355. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2356. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2357. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2358. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2359. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2360. };
  2361. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2362. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2363. wcd938x_get_compander, wcd938x_set_compander),
  2364. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2365. wcd938x_get_compander, wcd938x_set_compander),
  2366. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2367. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2368. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2369. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2370. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2371. analog_gain),
  2372. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2373. analog_gain),
  2374. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2375. analog_gain),
  2376. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2377. analog_gain),
  2378. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2379. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2380. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2381. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2382. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2383. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2384. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2385. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2386. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2387. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2388. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2389. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2390. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2391. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2392. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2393. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2394. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2395. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2396. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2397. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2398. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2399. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2400. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2401. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2402. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2403. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2404. };
  2405. static const struct snd_kcontrol_new adc1_switch[] = {
  2406. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2407. };
  2408. static const struct snd_kcontrol_new adc2_switch[] = {
  2409. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2410. };
  2411. static const struct snd_kcontrol_new adc3_switch[] = {
  2412. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2413. };
  2414. static const struct snd_kcontrol_new adc4_switch[] = {
  2415. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2416. };
  2417. static const struct snd_kcontrol_new dmic1_switch[] = {
  2418. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2419. };
  2420. static const struct snd_kcontrol_new dmic2_switch[] = {
  2421. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2422. };
  2423. static const struct snd_kcontrol_new dmic3_switch[] = {
  2424. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2425. };
  2426. static const struct snd_kcontrol_new dmic4_switch[] = {
  2427. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2428. };
  2429. static const struct snd_kcontrol_new dmic5_switch[] = {
  2430. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2431. };
  2432. static const struct snd_kcontrol_new dmic6_switch[] = {
  2433. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2434. };
  2435. static const struct snd_kcontrol_new dmic7_switch[] = {
  2436. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2437. };
  2438. static const struct snd_kcontrol_new dmic8_switch[] = {
  2439. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2440. };
  2441. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2442. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2443. };
  2444. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2445. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2446. };
  2447. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2448. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2449. };
  2450. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2451. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2452. };
  2453. static const char * const adc2_mux_text[] = {
  2454. "INP2", "INP3"
  2455. };
  2456. static const struct soc_enum adc2_enum =
  2457. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2458. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2459. static const struct snd_kcontrol_new tx_adc2_mux =
  2460. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2461. static const char * const adc3_mux_text[] = {
  2462. "INP4", "INP6"
  2463. };
  2464. static const struct soc_enum adc3_enum =
  2465. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2466. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2467. static const struct snd_kcontrol_new tx_adc3_mux =
  2468. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2469. static const char * const adc4_mux_text[] = {
  2470. "INP5", "INP7"
  2471. };
  2472. static const struct soc_enum adc4_enum =
  2473. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2474. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2475. static const struct snd_kcontrol_new tx_adc4_mux =
  2476. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2477. static const char * const rdac3_mux_text[] = {
  2478. "RX1", "RX3"
  2479. };
  2480. static const char * const hdr12_mux_text[] = {
  2481. "NO_HDR12", "HDR12"
  2482. };
  2483. static const struct soc_enum hdr12_enum =
  2484. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2485. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2486. static const struct snd_kcontrol_new tx_hdr12_mux =
  2487. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2488. static const char * const hdr34_mux_text[] = {
  2489. "NO_HDR34", "HDR34"
  2490. };
  2491. static const struct soc_enum hdr34_enum =
  2492. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2493. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2494. static const struct snd_kcontrol_new tx_hdr34_mux =
  2495. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2496. static const struct soc_enum rdac3_enum =
  2497. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2498. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2499. static const struct snd_kcontrol_new rx_rdac3_mux =
  2500. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2501. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2502. /*input widgets*/
  2503. SND_SOC_DAPM_INPUT("AMIC1"),
  2504. SND_SOC_DAPM_INPUT("AMIC2"),
  2505. SND_SOC_DAPM_INPUT("AMIC3"),
  2506. SND_SOC_DAPM_INPUT("AMIC4"),
  2507. SND_SOC_DAPM_INPUT("AMIC5"),
  2508. SND_SOC_DAPM_INPUT("AMIC6"),
  2509. SND_SOC_DAPM_INPUT("AMIC7"),
  2510. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2511. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2512. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2513. /*tx widgets*/
  2514. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2515. wcd938x_codec_enable_adc,
  2516. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2517. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2518. wcd938x_codec_enable_adc,
  2519. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2520. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2521. wcd938x_codec_enable_adc,
  2522. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2523. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2524. wcd938x_codec_enable_adc,
  2525. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2526. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2527. wcd938x_codec_enable_dmic,
  2528. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2529. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2530. wcd938x_codec_enable_dmic,
  2531. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2532. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2533. wcd938x_codec_enable_dmic,
  2534. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2535. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2536. wcd938x_codec_enable_dmic,
  2537. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2538. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2539. wcd938x_codec_enable_dmic,
  2540. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2541. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2542. wcd938x_codec_enable_dmic,
  2543. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2544. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2545. wcd938x_codec_enable_dmic,
  2546. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2547. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2548. wcd938x_codec_enable_dmic,
  2549. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2550. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2551. NULL, 0, wcd938x_enable_req,
  2552. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2553. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2554. NULL, 0, wcd938x_enable_req,
  2555. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2556. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2557. NULL, 0, wcd938x_enable_req,
  2558. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2559. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2560. NULL, 0, wcd938x_enable_req,
  2561. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2562. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2563. &tx_adc2_mux),
  2564. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2565. &tx_adc3_mux),
  2566. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2567. &tx_adc4_mux),
  2568. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2569. &tx_hdr12_mux),
  2570. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2571. &tx_hdr34_mux),
  2572. /*tx mixers*/
  2573. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2574. adc1_switch, ARRAY_SIZE(adc1_switch),
  2575. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2576. SND_SOC_DAPM_POST_PMD),
  2577. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2578. adc2_switch, ARRAY_SIZE(adc2_switch),
  2579. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2580. SND_SOC_DAPM_POST_PMD),
  2581. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2582. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2583. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2584. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2585. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2586. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2587. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2588. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2589. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2590. SND_SOC_DAPM_POST_PMD),
  2591. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2592. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2593. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2594. SND_SOC_DAPM_POST_PMD),
  2595. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2596. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2597. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2598. SND_SOC_DAPM_POST_PMD),
  2599. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2600. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2601. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2602. SND_SOC_DAPM_POST_PMD),
  2603. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2604. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2605. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2606. SND_SOC_DAPM_POST_PMD),
  2607. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2608. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2609. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2610. SND_SOC_DAPM_POST_PMD),
  2611. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2612. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2613. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2614. SND_SOC_DAPM_POST_PMD),
  2615. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2616. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2617. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2618. SND_SOC_DAPM_POST_PMD),
  2619. /* micbias widgets*/
  2620. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2621. wcd938x_codec_enable_micbias,
  2622. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2623. SND_SOC_DAPM_POST_PMD),
  2624. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2625. wcd938x_codec_enable_micbias,
  2626. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2627. SND_SOC_DAPM_POST_PMD),
  2628. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2629. wcd938x_codec_enable_micbias,
  2630. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2631. SND_SOC_DAPM_POST_PMD),
  2632. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2633. wcd938x_codec_enable_micbias,
  2634. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2635. SND_SOC_DAPM_POST_PMD),
  2636. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2637. wcd938x_codec_force_enable_micbias,
  2638. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2639. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2640. wcd938x_codec_force_enable_micbias,
  2641. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2642. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2643. wcd938x_codec_force_enable_micbias,
  2644. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2645. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2646. wcd938x_codec_force_enable_micbias,
  2647. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2648. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2649. wcd938x_enable_clsh,
  2650. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2651. /*rx widgets*/
  2652. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2653. wcd938x_codec_enable_ear_pa,
  2654. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2655. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2656. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2657. wcd938x_codec_enable_aux_pa,
  2658. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2659. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2660. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2661. wcd938x_codec_enable_hphl_pa,
  2662. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2663. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2664. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2665. wcd938x_codec_enable_hphr_pa,
  2666. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2667. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2668. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2669. wcd938x_codec_hphl_dac_event,
  2670. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2671. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2672. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2673. wcd938x_codec_hphr_dac_event,
  2674. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2675. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2676. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2677. wcd938x_codec_ear_dac_event,
  2678. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2679. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2680. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2681. wcd938x_codec_aux_dac_event,
  2682. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2683. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2684. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2685. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2686. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2687. SND_SOC_DAPM_POST_PMD),
  2688. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2689. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2690. SND_SOC_DAPM_POST_PMD),
  2691. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2692. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2693. SND_SOC_DAPM_POST_PMD),
  2694. /* rx mixer widgets*/
  2695. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2696. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2697. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2698. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2699. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2700. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2701. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2702. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2703. /*output widgets tx*/
  2704. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2705. /*output widgets rx*/
  2706. SND_SOC_DAPM_OUTPUT("EAR"),
  2707. SND_SOC_DAPM_OUTPUT("AUX"),
  2708. SND_SOC_DAPM_OUTPUT("HPHL"),
  2709. SND_SOC_DAPM_OUTPUT("HPHR"),
  2710. /* micbias pull up widgets*/
  2711. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2712. wcd938x_codec_enable_micbias_pullup,
  2713. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2714. SND_SOC_DAPM_POST_PMD),
  2715. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2716. wcd938x_codec_enable_micbias_pullup,
  2717. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2718. SND_SOC_DAPM_POST_PMD),
  2719. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2720. wcd938x_codec_enable_micbias_pullup,
  2721. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2722. SND_SOC_DAPM_POST_PMD),
  2723. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2724. wcd938x_codec_enable_micbias_pullup,
  2725. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2726. SND_SOC_DAPM_POST_PMD),
  2727. };
  2728. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2729. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2730. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2731. {"ADC1 REQ", NULL, "ADC1"},
  2732. {"ADC1", NULL, "AMIC1"},
  2733. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2734. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2735. {"ADC2 REQ", NULL, "ADC2"},
  2736. {"ADC2", NULL, "HDR12 MUX"},
  2737. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2738. {"HDR12 MUX", "HDR12", "AMIC1"},
  2739. {"ADC2 MUX", "INP3", "AMIC3"},
  2740. {"ADC2 MUX", "INP2", "AMIC2"},
  2741. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2742. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2743. {"ADC3 REQ", NULL, "ADC3"},
  2744. {"ADC3", NULL, "HDR34 MUX"},
  2745. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2746. {"HDR34 MUX", "HDR34", "AMIC5"},
  2747. {"ADC3 MUX", "INP4", "AMIC4"},
  2748. {"ADC3 MUX", "INP6", "AMIC6"},
  2749. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2750. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2751. {"ADC4 REQ", NULL, "ADC4"},
  2752. {"ADC4", NULL, "ADC4 MUX"},
  2753. {"ADC4 MUX", "INP5", "AMIC5"},
  2754. {"ADC4 MUX", "INP7", "AMIC7"},
  2755. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2756. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2757. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2758. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2759. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2760. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2761. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2762. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2763. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2764. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2765. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2766. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2767. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2768. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2769. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2770. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2771. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2772. {"RX1", NULL, "IN1_HPHL"},
  2773. {"RDAC1", NULL, "RX1"},
  2774. {"HPHL_RDAC", "Switch", "RDAC1"},
  2775. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2776. {"HPHL", NULL, "HPHL PGA"},
  2777. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2778. {"RX2", NULL, "IN2_HPHR"},
  2779. {"RDAC2", NULL, "RX2"},
  2780. {"HPHR_RDAC", "Switch", "RDAC2"},
  2781. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2782. {"HPHR", NULL, "HPHR PGA"},
  2783. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2784. {"RX3", NULL, "IN3_AUX"},
  2785. {"RDAC4", NULL, "RX3"},
  2786. {"AUX_RDAC", "Switch", "RDAC4"},
  2787. {"AUX PGA", NULL, "AUX_RDAC"},
  2788. {"AUX", NULL, "AUX PGA"},
  2789. {"RDAC3_MUX", "RX3", "RX3"},
  2790. {"RDAC3_MUX", "RX1", "RX1"},
  2791. {"RDAC3", NULL, "RDAC3_MUX"},
  2792. {"EAR_RDAC", "Switch", "RDAC3"},
  2793. {"EAR PGA", NULL, "EAR_RDAC"},
  2794. {"EAR", NULL, "EAR PGA"},
  2795. };
  2796. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2797. void *file_private_data,
  2798. struct file *file,
  2799. char __user *buf, size_t count,
  2800. loff_t pos)
  2801. {
  2802. struct wcd938x_priv *priv;
  2803. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2804. int len = 0;
  2805. priv = (struct wcd938x_priv *) entry->private_data;
  2806. if (!priv) {
  2807. pr_err("%s: wcd938x priv is null\n", __func__);
  2808. return -EINVAL;
  2809. }
  2810. switch (priv->version) {
  2811. case WCD938X_VERSION_1_0:
  2812. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2813. break;
  2814. default:
  2815. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2816. }
  2817. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2818. }
  2819. static struct snd_info_entry_ops wcd938x_info_ops = {
  2820. .read = wcd938x_version_read,
  2821. };
  2822. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2823. void *file_private_data,
  2824. struct file *file,
  2825. char __user *buf, size_t count,
  2826. loff_t pos)
  2827. {
  2828. struct wcd938x_priv *priv;
  2829. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2830. int len = 0;
  2831. priv = (struct wcd938x_priv *) entry->private_data;
  2832. if (!priv) {
  2833. pr_err("%s: wcd938x priv is null\n", __func__);
  2834. return -EINVAL;
  2835. }
  2836. switch (priv->variant) {
  2837. case WCD9380:
  2838. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2839. break;
  2840. case WCD9385:
  2841. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2842. break;
  2843. default:
  2844. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2845. }
  2846. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2847. }
  2848. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2849. .read = wcd938x_variant_read,
  2850. };
  2851. /*
  2852. * wcd938x_get_codec_variant
  2853. * @component: component instance
  2854. *
  2855. * Return: codec variant or -EINVAL in error.
  2856. */
  2857. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2858. {
  2859. struct wcd938x_priv *priv = NULL;
  2860. if (!component)
  2861. return -EINVAL;
  2862. priv = snd_soc_component_get_drvdata(component);
  2863. if (!priv) {
  2864. dev_err(component->dev,
  2865. "%s:wcd938x not probed\n", __func__);
  2866. return 0;
  2867. }
  2868. return priv->variant;
  2869. }
  2870. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2871. /*
  2872. * wcd938x_info_create_codec_entry - creates wcd938x module
  2873. * @codec_root: The parent directory
  2874. * @component: component instance
  2875. *
  2876. * Creates wcd938x module, variant and version entry under the given
  2877. * parent directory.
  2878. *
  2879. * Return: 0 on success or negative error code on failure.
  2880. */
  2881. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2882. struct snd_soc_component *component)
  2883. {
  2884. struct snd_info_entry *version_entry;
  2885. struct snd_info_entry *variant_entry;
  2886. struct wcd938x_priv *priv;
  2887. struct snd_soc_card *card;
  2888. if (!codec_root || !component)
  2889. return -EINVAL;
  2890. priv = snd_soc_component_get_drvdata(component);
  2891. if (priv->entry) {
  2892. dev_dbg(priv->dev,
  2893. "%s:wcd938x module already created\n", __func__);
  2894. return 0;
  2895. }
  2896. card = component->card;
  2897. priv->entry = snd_info_create_module_entry(codec_root->module,
  2898. "wcd938x", codec_root);
  2899. if (!priv->entry) {
  2900. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2901. __func__);
  2902. return -ENOMEM;
  2903. }
  2904. priv->entry->mode = S_IFDIR | 0555;
  2905. if (snd_info_register(priv->entry) < 0) {
  2906. snd_info_free_entry(priv->entry);
  2907. return -ENOMEM;
  2908. }
  2909. version_entry = snd_info_create_card_entry(card->snd_card,
  2910. "version",
  2911. priv->entry);
  2912. if (!version_entry) {
  2913. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2914. __func__);
  2915. snd_info_free_entry(priv->entry);
  2916. return -ENOMEM;
  2917. }
  2918. version_entry->private_data = priv;
  2919. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2920. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2921. version_entry->c.ops = &wcd938x_info_ops;
  2922. if (snd_info_register(version_entry) < 0) {
  2923. snd_info_free_entry(version_entry);
  2924. snd_info_free_entry(priv->entry);
  2925. return -ENOMEM;
  2926. }
  2927. priv->version_entry = version_entry;
  2928. variant_entry = snd_info_create_card_entry(card->snd_card,
  2929. "variant",
  2930. priv->entry);
  2931. if (!variant_entry) {
  2932. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2933. __func__);
  2934. snd_info_free_entry(version_entry);
  2935. snd_info_free_entry(priv->entry);
  2936. return -ENOMEM;
  2937. }
  2938. variant_entry->private_data = priv;
  2939. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2940. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2941. variant_entry->c.ops = &wcd938x_variant_ops;
  2942. if (snd_info_register(variant_entry) < 0) {
  2943. snd_info_free_entry(variant_entry);
  2944. snd_info_free_entry(version_entry);
  2945. snd_info_free_entry(priv->entry);
  2946. return -ENOMEM;
  2947. }
  2948. priv->variant_entry = variant_entry;
  2949. return 0;
  2950. }
  2951. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2952. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  2953. struct wcd938x_pdata *pdata)
  2954. {
  2955. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  2956. int rc = 0;
  2957. if (!pdata) {
  2958. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  2959. return -ENODEV;
  2960. }
  2961. /* set micbias voltage */
  2962. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2963. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2964. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2965. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  2966. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  2967. vout_ctl_4 < 0) {
  2968. rc = -EINVAL;
  2969. goto done;
  2970. }
  2971. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  2972. vout_ctl_1);
  2973. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  2974. vout_ctl_2);
  2975. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  2976. vout_ctl_3);
  2977. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  2978. vout_ctl_4);
  2979. done:
  2980. return rc;
  2981. }
  2982. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2983. {
  2984. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2985. struct snd_soc_dapm_context *dapm =
  2986. snd_soc_component_get_dapm(component);
  2987. int variant;
  2988. int ret = -EINVAL;
  2989. dev_info(component->dev, "%s()\n", __func__);
  2990. wcd938x = snd_soc_component_get_drvdata(component);
  2991. if (!wcd938x)
  2992. return -EINVAL;
  2993. wcd938x->component = component;
  2994. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2995. variant = (snd_soc_component_read32(component,
  2996. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2997. wcd938x->variant = variant;
  2998. wcd938x->fw_data = devm_kzalloc(component->dev,
  2999. sizeof(*(wcd938x->fw_data)),
  3000. GFP_KERNEL);
  3001. if (!wcd938x->fw_data) {
  3002. dev_err(component->dev, "Failed to allocate fw_data\n");
  3003. ret = -ENOMEM;
  3004. goto err;
  3005. }
  3006. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3007. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3008. WCD9XXX_CODEC_HWDEP_NODE, component);
  3009. if (ret < 0) {
  3010. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3011. goto err_hwdep;
  3012. }
  3013. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3014. if (ret) {
  3015. pr_err("%s: mbhc initialization failed\n", __func__);
  3016. goto err_hwdep;
  3017. }
  3018. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3019. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3020. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3021. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3022. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3023. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3024. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3025. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3026. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3027. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3028. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3029. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3030. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3031. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3032. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3033. snd_soc_dapm_sync(dapm);
  3034. wcd_cls_h_init(&wcd938x->clsh_info);
  3035. wcd938x_init_reg(component);
  3036. if (wcd938x->variant == WCD9380) {
  3037. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3038. ARRAY_SIZE(wcd9380_snd_controls));
  3039. if (ret < 0) {
  3040. dev_err(component->dev,
  3041. "%s: Failed to add snd ctrls for variant: %d\n",
  3042. __func__, wcd938x->variant);
  3043. goto err_hwdep;
  3044. }
  3045. }
  3046. if (wcd938x->variant == WCD9385) {
  3047. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3048. ARRAY_SIZE(wcd9385_snd_controls));
  3049. if (ret < 0) {
  3050. dev_err(component->dev,
  3051. "%s: Failed to add snd ctrls for variant: %d\n",
  3052. __func__, wcd938x->variant);
  3053. goto err_hwdep;
  3054. }
  3055. }
  3056. wcd938x->version = WCD938X_VERSION_1_0;
  3057. /* Register event notifier */
  3058. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3059. if (wcd938x->register_notifier) {
  3060. ret = wcd938x->register_notifier(wcd938x->handle,
  3061. &wcd938x->nblock,
  3062. true);
  3063. if (ret) {
  3064. dev_err(component->dev,
  3065. "%s: Failed to register notifier %d\n",
  3066. __func__, ret);
  3067. return ret;
  3068. }
  3069. }
  3070. wcd938x->dev_up = true;
  3071. return ret;
  3072. err_hwdep:
  3073. wcd938x->fw_data = NULL;
  3074. err:
  3075. return ret;
  3076. }
  3077. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3078. {
  3079. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3080. if (!wcd938x) {
  3081. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3082. __func__);
  3083. return;
  3084. }
  3085. if (wcd938x->register_notifier)
  3086. wcd938x->register_notifier(wcd938x->handle,
  3087. &wcd938x->nblock,
  3088. false);
  3089. }
  3090. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3091. .name = WCD938X_DRV_NAME,
  3092. .probe = wcd938x_soc_codec_probe,
  3093. .remove = wcd938x_soc_codec_remove,
  3094. .controls = wcd938x_snd_controls,
  3095. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3096. .dapm_widgets = wcd938x_dapm_widgets,
  3097. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3098. .dapm_routes = wcd938x_audio_map,
  3099. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3100. };
  3101. static int wcd938x_reset(struct device *dev)
  3102. {
  3103. struct wcd938x_priv *wcd938x = NULL;
  3104. int rc = 0;
  3105. int value = 0;
  3106. if (!dev)
  3107. return -ENODEV;
  3108. wcd938x = dev_get_drvdata(dev);
  3109. if (!wcd938x)
  3110. return -EINVAL;
  3111. if (!wcd938x->rst_np) {
  3112. dev_err(dev, "%s: reset gpio device node not specified\n",
  3113. __func__);
  3114. return -EINVAL;
  3115. }
  3116. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3117. if (value > 0)
  3118. return 0;
  3119. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3120. if (rc) {
  3121. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3122. __func__);
  3123. return rc;
  3124. }
  3125. /* 20us sleep required after pulling the reset gpio to LOW */
  3126. usleep_range(20, 30);
  3127. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3128. if (rc) {
  3129. dev_err(dev, "%s: wcd active state request fail!\n",
  3130. __func__);
  3131. return rc;
  3132. }
  3133. /* 20us sleep required after pulling the reset gpio to HIGH */
  3134. usleep_range(20, 30);
  3135. return rc;
  3136. }
  3137. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3138. u32 *val)
  3139. {
  3140. int rc = 0;
  3141. rc = of_property_read_u32(dev->of_node, name, val);
  3142. if (rc)
  3143. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3144. __func__, name, dev->of_node->full_name);
  3145. return rc;
  3146. }
  3147. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3148. struct wcd938x_micbias_setting *mb)
  3149. {
  3150. u32 prop_val = 0;
  3151. int rc = 0;
  3152. /* MB1 */
  3153. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3154. NULL)) {
  3155. rc = wcd938x_read_of_property_u32(dev,
  3156. "qcom,cdc-micbias1-mv",
  3157. &prop_val);
  3158. if (!rc)
  3159. mb->micb1_mv = prop_val;
  3160. } else {
  3161. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3162. __func__);
  3163. }
  3164. /* MB2 */
  3165. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3166. NULL)) {
  3167. rc = wcd938x_read_of_property_u32(dev,
  3168. "qcom,cdc-micbias2-mv",
  3169. &prop_val);
  3170. if (!rc)
  3171. mb->micb2_mv = prop_val;
  3172. } else {
  3173. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3174. __func__);
  3175. }
  3176. /* MB3 */
  3177. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3178. NULL)) {
  3179. rc = wcd938x_read_of_property_u32(dev,
  3180. "qcom,cdc-micbias3-mv",
  3181. &prop_val);
  3182. if (!rc)
  3183. mb->micb3_mv = prop_val;
  3184. } else {
  3185. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3186. __func__);
  3187. }
  3188. /* MB4 */
  3189. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3190. NULL)) {
  3191. rc = wcd938x_read_of_property_u32(dev,
  3192. "qcom,cdc-micbias4-mv",
  3193. &prop_val);
  3194. if (!rc)
  3195. mb->micb4_mv = prop_val;
  3196. } else {
  3197. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3198. __func__);
  3199. }
  3200. }
  3201. static int wcd938x_reset_low(struct device *dev)
  3202. {
  3203. struct wcd938x_priv *wcd938x = NULL;
  3204. int rc = 0;
  3205. if (!dev)
  3206. return -ENODEV;
  3207. wcd938x = dev_get_drvdata(dev);
  3208. if (!wcd938x)
  3209. return -EINVAL;
  3210. if (!wcd938x->rst_np) {
  3211. dev_err(dev, "%s: reset gpio device node not specified\n",
  3212. __func__);
  3213. return -EINVAL;
  3214. }
  3215. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3216. if (rc) {
  3217. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3218. __func__);
  3219. return rc;
  3220. }
  3221. /* 20us sleep required after pulling the reset gpio to LOW */
  3222. usleep_range(20, 30);
  3223. return rc;
  3224. }
  3225. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3226. {
  3227. struct wcd938x_pdata *pdata = NULL;
  3228. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3229. GFP_KERNEL);
  3230. if (!pdata)
  3231. return NULL;
  3232. pdata->rst_np = of_parse_phandle(dev->of_node,
  3233. "qcom,wcd-rst-gpio-node", 0);
  3234. if (!pdata->rst_np) {
  3235. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3236. __func__, "qcom,wcd-rst-gpio-node",
  3237. dev->of_node->full_name);
  3238. return NULL;
  3239. }
  3240. /* Parse power supplies */
  3241. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3242. &pdata->num_supplies);
  3243. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3244. dev_err(dev, "%s: no power supplies defined for codec\n",
  3245. __func__);
  3246. return NULL;
  3247. }
  3248. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3249. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3250. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3251. return pdata;
  3252. }
  3253. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3254. {
  3255. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3256. __func__, irq);
  3257. return IRQ_HANDLED;
  3258. }
  3259. static int wcd938x_bind(struct device *dev)
  3260. {
  3261. int ret = 0, i = 0;
  3262. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3263. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3264. /*
  3265. * Add 5msec delay to provide sufficient time for
  3266. * soundwire auto enumeration of slave devices as
  3267. * as per HW requirement.
  3268. */
  3269. usleep_range(5000, 5010);
  3270. ret = component_bind_all(dev, wcd938x);
  3271. if (ret) {
  3272. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3273. __func__, ret);
  3274. return ret;
  3275. }
  3276. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3277. if (!wcd938x->rx_swr_dev) {
  3278. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3279. __func__);
  3280. ret = -ENODEV;
  3281. goto err;
  3282. }
  3283. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3284. if (!wcd938x->tx_swr_dev) {
  3285. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3286. __func__);
  3287. ret = -ENODEV;
  3288. goto err;
  3289. }
  3290. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3291. &wcd938x_regmap_config);
  3292. if (!wcd938x->regmap) {
  3293. dev_err(dev, "%s: Regmap init failed\n",
  3294. __func__);
  3295. goto err;
  3296. }
  3297. /* Set all interupts as edge triggered */
  3298. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3299. regmap_write(wcd938x->regmap,
  3300. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3301. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3302. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3303. wcd938x->irq_info.codec_name = "WCD938X";
  3304. wcd938x->irq_info.regmap = wcd938x->regmap;
  3305. wcd938x->irq_info.dev = dev;
  3306. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3307. if (ret) {
  3308. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3309. __func__, ret);
  3310. goto err;
  3311. }
  3312. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3313. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3314. if (ret < 0) {
  3315. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3316. goto err_irq;
  3317. }
  3318. /* Request for watchdog interrupt */
  3319. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3320. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3321. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3322. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3323. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3324. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3325. /* Disable watchdog interrupt for HPH and AUX */
  3326. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3327. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3328. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3329. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3330. NULL, 0);
  3331. if (ret) {
  3332. dev_err(dev, "%s: Codec registration failed\n",
  3333. __func__);
  3334. goto err_irq;
  3335. }
  3336. return ret;
  3337. err_irq:
  3338. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3339. err:
  3340. component_unbind_all(dev, wcd938x);
  3341. return ret;
  3342. }
  3343. static void wcd938x_unbind(struct device *dev)
  3344. {
  3345. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3346. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3347. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3348. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3349. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3350. snd_soc_unregister_component(dev);
  3351. component_unbind_all(dev, wcd938x);
  3352. }
  3353. static const struct of_device_id wcd938x_dt_match[] = {
  3354. { .compatible = "qcom,wcd938x-codec" },
  3355. {}
  3356. };
  3357. static const struct component_master_ops wcd938x_comp_ops = {
  3358. .bind = wcd938x_bind,
  3359. .unbind = wcd938x_unbind,
  3360. };
  3361. static int wcd938x_compare_of(struct device *dev, void *data)
  3362. {
  3363. return dev->of_node == data;
  3364. }
  3365. static void wcd938x_release_of(struct device *dev, void *data)
  3366. {
  3367. of_node_put(data);
  3368. }
  3369. static int wcd938x_add_slave_components(struct device *dev,
  3370. struct component_match **matchptr)
  3371. {
  3372. struct device_node *np, *rx_node, *tx_node;
  3373. np = dev->of_node;
  3374. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3375. if (!rx_node) {
  3376. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3377. return -ENODEV;
  3378. }
  3379. of_node_get(rx_node);
  3380. component_match_add_release(dev, matchptr,
  3381. wcd938x_release_of,
  3382. wcd938x_compare_of,
  3383. rx_node);
  3384. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3385. if (!tx_node) {
  3386. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3387. return -ENODEV;
  3388. }
  3389. of_node_get(tx_node);
  3390. component_match_add_release(dev, matchptr,
  3391. wcd938x_release_of,
  3392. wcd938x_compare_of,
  3393. tx_node);
  3394. return 0;
  3395. }
  3396. static int wcd938x_probe(struct platform_device *pdev)
  3397. {
  3398. struct component_match *match = NULL;
  3399. struct wcd938x_priv *wcd938x = NULL;
  3400. struct wcd938x_pdata *pdata = NULL;
  3401. struct wcd_ctrl_platform_data *plat_data = NULL;
  3402. struct device *dev = &pdev->dev;
  3403. int ret;
  3404. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3405. GFP_KERNEL);
  3406. if (!wcd938x)
  3407. return -ENOMEM;
  3408. dev_set_drvdata(dev, wcd938x);
  3409. wcd938x->dev = dev;
  3410. pdata = wcd938x_populate_dt_data(dev);
  3411. if (!pdata) {
  3412. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3413. return -EINVAL;
  3414. }
  3415. dev->platform_data = pdata;
  3416. wcd938x->rst_np = pdata->rst_np;
  3417. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3418. pdata->regulator, pdata->num_supplies);
  3419. if (!wcd938x->supplies) {
  3420. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3421. __func__);
  3422. return ret;
  3423. }
  3424. plat_data = dev_get_platdata(dev->parent);
  3425. if (!plat_data) {
  3426. dev_err(dev, "%s: platform data from parent is NULL\n",
  3427. __func__);
  3428. return -EINVAL;
  3429. }
  3430. wcd938x->handle = (void *)plat_data->handle;
  3431. if (!wcd938x->handle) {
  3432. dev_err(dev, "%s: handle is NULL\n", __func__);
  3433. return -EINVAL;
  3434. }
  3435. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3436. if (!wcd938x->update_wcd_event) {
  3437. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3438. __func__);
  3439. return -EINVAL;
  3440. }
  3441. wcd938x->register_notifier = plat_data->register_notifier;
  3442. if (!wcd938x->register_notifier) {
  3443. dev_err(dev, "%s: register_notifier api is null!\n",
  3444. __func__);
  3445. return -EINVAL;
  3446. }
  3447. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3448. pdata->regulator,
  3449. pdata->num_supplies);
  3450. if (ret) {
  3451. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3452. __func__);
  3453. return ret;
  3454. }
  3455. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3456. CODEC_RX);
  3457. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3458. CODEC_TX);
  3459. if (ret) {
  3460. dev_err(dev, "Failed to read port mapping\n");
  3461. goto err;
  3462. }
  3463. mutex_init(&wcd938x->wakeup_lock);
  3464. mutex_init(&wcd938x->micb_lock);
  3465. ret = wcd938x_add_slave_components(dev, &match);
  3466. if (ret)
  3467. goto err_lock_init;
  3468. wcd938x_reset(dev);
  3469. wcd938x->wakeup = wcd938x_wakeup;
  3470. return component_master_add_with_match(dev,
  3471. &wcd938x_comp_ops, match);
  3472. err_lock_init:
  3473. mutex_destroy(&wcd938x->micb_lock);
  3474. mutex_destroy(&wcd938x->wakeup_lock);
  3475. err:
  3476. return ret;
  3477. }
  3478. static int wcd938x_remove(struct platform_device *pdev)
  3479. {
  3480. struct wcd938x_priv *wcd938x = NULL;
  3481. wcd938x = platform_get_drvdata(pdev);
  3482. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3483. mutex_destroy(&wcd938x->micb_lock);
  3484. mutex_destroy(&wcd938x->wakeup_lock);
  3485. dev_set_drvdata(&pdev->dev, NULL);
  3486. return 0;
  3487. }
  3488. #ifdef CONFIG_PM_SLEEP
  3489. static int wcd938x_suspend(struct device *dev)
  3490. {
  3491. return 0;
  3492. }
  3493. static int wcd938x_resume(struct device *dev)
  3494. {
  3495. return 0;
  3496. }
  3497. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3498. SET_SYSTEM_SLEEP_PM_OPS(
  3499. wcd938x_suspend,
  3500. wcd938x_resume
  3501. )
  3502. };
  3503. #endif
  3504. static struct platform_driver wcd938x_codec_driver = {
  3505. .probe = wcd938x_probe,
  3506. .remove = wcd938x_remove,
  3507. .driver = {
  3508. .name = "wcd938x_codec",
  3509. .owner = THIS_MODULE,
  3510. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3511. #ifdef CONFIG_PM_SLEEP
  3512. .pm = &wcd938x_dev_pm_ops,
  3513. #endif
  3514. .suppress_bind_attrs = true,
  3515. },
  3516. };
  3517. module_platform_driver(wcd938x_codec_driver);
  3518. MODULE_DESCRIPTION("WCD938X Codec driver");
  3519. MODULE_LICENSE("GPL v2");