sde_hw_intf.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SDE_HW_INTF_H
  6. #define _SDE_HW_INTF_H
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_mdss.h"
  9. #include "sde_hw_util.h"
  10. #include "sde_hw_blk.h"
  11. #include "sde_kms.h"
  12. struct sde_hw_intf;
  13. /* intf timing settings */
  14. struct intf_timing_params {
  15. u32 width; /* active width */
  16. u32 height; /* active height */
  17. u32 xres; /* Display panel width */
  18. u32 yres; /* Display panel height */
  19. u32 h_back_porch;
  20. u32 h_front_porch;
  21. u32 v_back_porch;
  22. u32 v_front_porch;
  23. u32 hsync_pulse_width;
  24. u32 vsync_pulse_width;
  25. u32 hsync_polarity;
  26. u32 vsync_polarity;
  27. u32 border_clr;
  28. u32 underflow_clr;
  29. u32 hsync_skew;
  30. u32 v_front_porch_fixed;
  31. bool wide_bus_en; /* for DP only */
  32. bool compression_en;
  33. u32 extra_dto_cycles; /* for DP only */
  34. bool dsc_4hs_merge; /* DSC 4HS merge */
  35. };
  36. struct intf_prog_fetch {
  37. u8 enable;
  38. /* vsync counter for the front porch pixel line */
  39. u32 fetch_start;
  40. };
  41. struct intf_status {
  42. u8 is_en; /* interface timing engine is enabled or not */
  43. u32 frame_count; /* frame count since timing engine enabled */
  44. u32 line_count; /* current line count including blanking */
  45. };
  46. struct intf_avr_params {
  47. u32 default_fps;
  48. u32 min_fps;
  49. u32 avr_mode; /* 0 - disable, 1 - continuous, 2 - one-shot */
  50. };
  51. /**
  52. * struct sde_hw_intf_ops : Interface to the interface Hw driver functions
  53. * Assumption is these functions will be called after clocks are enabled
  54. * @ setup_timing_gen : programs the timing engine
  55. * @ setup_prog_fetch : enables/disables the programmable fetch logic
  56. * @ setup_rot_start : enables/disables the rotator start trigger
  57. * @ enable_timing: enable/disable timing engine
  58. * @ get_status: returns if timing engine is enabled or not
  59. * @ setup_misr: enables/disables MISR in HW register
  60. * @ collect_misr: reads and stores MISR data from HW register
  61. * @ get_line_count: reads current vertical line counter
  62. * @ get_underrun_line_count: reads current underrun pixel clock count and
  63. * converts it into line count
  64. * @bind_pingpong_blk: enable/disable the connection with pingpong which will
  65. * feed pixels to this interface
  66. */
  67. struct sde_hw_intf_ops {
  68. void (*setup_timing_gen)(struct sde_hw_intf *intf,
  69. const struct intf_timing_params *p,
  70. const struct sde_format *fmt);
  71. void (*setup_prg_fetch)(struct sde_hw_intf *intf,
  72. const struct intf_prog_fetch *fetch);
  73. void (*setup_rot_start)(struct sde_hw_intf *intf,
  74. const struct intf_prog_fetch *fetch);
  75. void (*enable_timing)(struct sde_hw_intf *intf,
  76. u8 enable);
  77. void (*get_status)(struct sde_hw_intf *intf,
  78. struct intf_status *status);
  79. void (*setup_misr)(struct sde_hw_intf *intf,
  80. bool enable, u32 frame_count);
  81. int (*collect_misr)(struct sde_hw_intf *intf,
  82. bool nonblock, u32 *misr_value);
  83. /**
  84. * returns the current scan line count of the display
  85. * video mode panels use get_line_count whereas get_vsync_info
  86. * is used for command mode panels
  87. */
  88. u32 (*get_line_count)(struct sde_hw_intf *intf);
  89. u32 (*get_underrun_line_count)(struct sde_hw_intf *intf);
  90. void (*bind_pingpong_blk)(struct sde_hw_intf *intf,
  91. bool enable,
  92. const enum sde_pingpong pp);
  93. /**
  94. * enables vysnc generation and sets up init value of
  95. * read pointer and programs the tear check cofiguration
  96. */
  97. int (*setup_tearcheck)(struct sde_hw_intf *intf,
  98. struct sde_hw_tear_check *cfg);
  99. /**
  100. * enables tear check block
  101. */
  102. int (*enable_tearcheck)(struct sde_hw_intf *intf,
  103. bool enable);
  104. /**
  105. * updates tearcheck configuration
  106. */
  107. void (*update_tearcheck)(struct sde_hw_intf *intf,
  108. struct sde_hw_tear_check *cfg);
  109. /**
  110. * read, modify, write to either set or clear listening to external TE
  111. * @Return: 1 if TE was originally connected, 0 if not, or -ERROR
  112. */
  113. int (*connect_external_te)(struct sde_hw_intf *intf,
  114. bool enable_external_te);
  115. /**
  116. * provides the programmed and current
  117. * line_count
  118. */
  119. int (*get_vsync_info)(struct sde_hw_intf *intf,
  120. struct sde_hw_pp_vsync_info *info);
  121. /**
  122. * configure and enable the autorefresh config
  123. */
  124. int (*setup_autorefresh)(struct sde_hw_intf *intf,
  125. struct sde_hw_autorefresh *cfg);
  126. /**
  127. * retrieve autorefresh config from hardware
  128. */
  129. int (*get_autorefresh)(struct sde_hw_intf *intf,
  130. struct sde_hw_autorefresh *cfg);
  131. /**
  132. * poll until write pointer transmission starts
  133. * @Return: 0 on success, -ETIMEDOUT on timeout
  134. */
  135. int (*poll_timeout_wr_ptr)(struct sde_hw_intf *intf, u32 timeout_us);
  136. /**
  137. * Select vsync signal for tear-effect configuration
  138. */
  139. void (*vsync_sel)(struct sde_hw_intf *intf, u32 vsync_source);
  140. /**
  141. * Program the AVR_TOTAL for min fps rate
  142. */
  143. int (*avr_setup)(struct sde_hw_intf *intf,
  144. const struct intf_timing_params *params,
  145. const struct intf_avr_params *avr_params);
  146. /**
  147. * Signal the trigger on each commit for AVR
  148. */
  149. void (*avr_trigger)(struct sde_hw_intf *ctx);
  150. /**
  151. * Enable AVR and select the mode
  152. */
  153. void (*avr_ctrl)(struct sde_hw_intf *intf,
  154. const struct intf_avr_params *avr_params);
  155. /**
  156. * Enable/disable 64 bit compressed data input to interface block
  157. */
  158. void (*enable_compressed_input)(struct sde_hw_intf *intf,
  159. bool compression_en, bool dsc_4hs_merge);
  160. };
  161. struct sde_hw_intf {
  162. struct sde_hw_blk base;
  163. struct sde_hw_blk_reg_map hw;
  164. /* intf */
  165. enum sde_intf idx;
  166. const struct sde_intf_cfg *cap;
  167. const struct sde_mdss_cfg *mdss;
  168. struct split_pipe_cfg cfg;
  169. /* ops */
  170. struct sde_hw_intf_ops ops;
  171. };
  172. /**
  173. * to_sde_hw_intf - convert base object sde_hw_base to container
  174. * @hw: Pointer to base hardware block
  175. * return: Pointer to hardware block container
  176. */
  177. static inline struct sde_hw_intf *to_sde_hw_intf(struct sde_hw_blk *hw)
  178. {
  179. return container_of(hw, struct sde_hw_intf, base);
  180. }
  181. /**
  182. * sde_hw_intf_init(): Initializes the intf driver for the passed
  183. * interface idx.
  184. * @idx: interface index for which driver object is required
  185. * @addr: mapped register io address of MDP
  186. * @m : pointer to mdss catalog data
  187. */
  188. struct sde_hw_intf *sde_hw_intf_init(enum sde_intf idx,
  189. void __iomem *addr,
  190. struct sde_mdss_cfg *m);
  191. /**
  192. * sde_hw_intf_destroy(): Destroys INTF driver context
  193. * @intf: Pointer to INTF driver context
  194. */
  195. void sde_hw_intf_destroy(struct sde_hw_intf *intf);
  196. #endif /*_SDE_HW_INTF_H */