sde_hw_intf.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/iopoll.h>
  6. #include "sde_hwio.h"
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_intf.h"
  9. #include "sde_dbg.h"
  10. #define INTF_TIMING_ENGINE_EN 0x000
  11. #define INTF_CONFIG 0x004
  12. #define INTF_HSYNC_CTL 0x008
  13. #define INTF_VSYNC_PERIOD_F0 0x00C
  14. #define INTF_VSYNC_PERIOD_F1 0x010
  15. #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
  16. #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
  17. #define INTF_DISPLAY_V_START_F0 0x01C
  18. #define INTF_DISPLAY_V_START_F1 0x020
  19. #define INTF_DISPLAY_V_END_F0 0x024
  20. #define INTF_DISPLAY_V_END_F1 0x028
  21. #define INTF_ACTIVE_V_START_F0 0x02C
  22. #define INTF_ACTIVE_V_START_F1 0x030
  23. #define INTF_ACTIVE_V_END_F0 0x034
  24. #define INTF_ACTIVE_V_END_F1 0x038
  25. #define INTF_DISPLAY_HCTL 0x03C
  26. #define INTF_ACTIVE_HCTL 0x040
  27. #define INTF_BORDER_COLOR 0x044
  28. #define INTF_UNDERFLOW_COLOR 0x048
  29. #define INTF_HSYNC_SKEW 0x04C
  30. #define INTF_POLARITY_CTL 0x050
  31. #define INTF_TEST_CTL 0x054
  32. #define INTF_TP_COLOR0 0x058
  33. #define INTF_TP_COLOR1 0x05C
  34. #define INTF_CONFIG2 0x060
  35. #define INTF_DISPLAY_DATA_HCTL 0x064
  36. #define INTF_ACTIVE_DATA_HCTL 0x068
  37. #define INTF_FRAME_LINE_COUNT_EN 0x0A8
  38. #define INTF_FRAME_COUNT 0x0AC
  39. #define INTF_LINE_COUNT 0x0B0
  40. #define INTF_DEFLICKER_CONFIG 0x0F0
  41. #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
  42. #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
  43. #define INTF_REG_SPLIT_LINK 0x080
  44. #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
  45. #define INTF_PANEL_FORMAT 0x090
  46. #define INTF_TPG_ENABLE 0x100
  47. #define INTF_TPG_MAIN_CONTROL 0x104
  48. #define INTF_TPG_VIDEO_CONFIG 0x108
  49. #define INTF_TPG_COMPONENT_LIMITS 0x10C
  50. #define INTF_TPG_RECTANGLE 0x110
  51. #define INTF_TPG_INITIAL_VALUE 0x114
  52. #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
  53. #define INTF_TPG_RGB_MAPPING 0x11C
  54. #define INTF_PROG_FETCH_START 0x170
  55. #define INTF_PROG_ROT_START 0x174
  56. #define INTF_MISR_CTRL 0x180
  57. #define INTF_MISR_SIGNATURE 0x184
  58. #define INTF_MUX 0x25C
  59. #define INTF_UNDERRUN_COUNT 0x268
  60. #define INTF_STATUS 0x26C
  61. #define INTF_AVR_CONTROL 0x270
  62. #define INTF_AVR_MODE 0x274
  63. #define INTF_AVR_TRIGGER 0x278
  64. #define INTF_AVR_VTOTAL 0x27C
  65. #define INTF_TEAR_MDP_VSYNC_SEL 0x280
  66. #define INTF_TEAR_TEAR_CHECK_EN 0x284
  67. #define INTF_TEAR_SYNC_CONFIG_VSYNC 0x288
  68. #define INTF_TEAR_SYNC_CONFIG_HEIGHT 0x28C
  69. #define INTF_TEAR_SYNC_WRCOUNT 0x290
  70. #define INTF_TEAR_VSYNC_INIT_VAL 0x294
  71. #define INTF_TEAR_INT_COUNT_VAL 0x298
  72. #define INTF_TEAR_SYNC_THRESH 0x29C
  73. #define INTF_TEAR_START_POS 0x2A0
  74. #define INTF_TEAR_RD_PTR_IRQ 0x2A4
  75. #define INTF_TEAR_WR_PTR_IRQ 0x2A8
  76. #define INTF_TEAR_OUT_LINE_COUNT 0x2AC
  77. #define INTF_TEAR_LINE_COUNT 0x2B0
  78. #define INTF_TEAR_AUTOREFRESH_CONFIG 0x2B4
  79. #define INTF_TEAR_TEAR_DETECT_CTRL 0x2B8
  80. static struct sde_intf_cfg *_intf_offset(enum sde_intf intf,
  81. struct sde_mdss_cfg *m,
  82. void __iomem *addr,
  83. struct sde_hw_blk_reg_map *b)
  84. {
  85. int i;
  86. for (i = 0; i < m->intf_count; i++) {
  87. if ((intf == m->intf[i].id) &&
  88. (m->intf[i].type != INTF_NONE)) {
  89. b->base_off = addr;
  90. b->blk_off = m->intf[i].base;
  91. b->length = m->intf[i].len;
  92. b->hwversion = m->hwversion;
  93. b->log_mask = SDE_DBG_MASK_INTF;
  94. return &m->intf[i];
  95. }
  96. }
  97. return ERR_PTR(-EINVAL);
  98. }
  99. static void sde_hw_intf_avr_trigger(struct sde_hw_intf *ctx)
  100. {
  101. struct sde_hw_blk_reg_map *c;
  102. if (!ctx)
  103. return;
  104. c = &ctx->hw;
  105. SDE_REG_WRITE(c, INTF_AVR_TRIGGER, 0x1);
  106. SDE_DEBUG("AVR Triggered\n");
  107. }
  108. static int sde_hw_intf_avr_setup(struct sde_hw_intf *ctx,
  109. const struct intf_timing_params *params,
  110. const struct intf_avr_params *avr_params)
  111. {
  112. struct sde_hw_blk_reg_map *c;
  113. u32 hsync_period, vsync_period;
  114. u32 min_fps, default_fps, diff_fps;
  115. u32 vsync_period_slow;
  116. u32 avr_vtotal;
  117. u32 add_porches = 0;
  118. if (!ctx || !params || !avr_params) {
  119. SDE_ERROR("invalid input parameter(s)\n");
  120. return -EINVAL;
  121. }
  122. c = &ctx->hw;
  123. min_fps = avr_params->min_fps;
  124. default_fps = avr_params->default_fps;
  125. diff_fps = default_fps - min_fps;
  126. hsync_period = params->hsync_pulse_width +
  127. params->h_back_porch + params->width +
  128. params->h_front_porch;
  129. vsync_period = params->vsync_pulse_width +
  130. params->v_back_porch + params->height +
  131. params->v_front_porch;
  132. if (diff_fps)
  133. add_porches = mult_frac(vsync_period, diff_fps, min_fps);
  134. vsync_period_slow = vsync_period + add_porches;
  135. avr_vtotal = vsync_period_slow * hsync_period;
  136. SDE_REG_WRITE(c, INTF_AVR_VTOTAL, avr_vtotal);
  137. return 0;
  138. }
  139. static void sde_hw_intf_avr_ctrl(struct sde_hw_intf *ctx,
  140. const struct intf_avr_params *avr_params)
  141. {
  142. struct sde_hw_blk_reg_map *c;
  143. u32 avr_mode = 0;
  144. u32 avr_ctrl = 0;
  145. if (!ctx || !avr_params)
  146. return;
  147. c = &ctx->hw;
  148. if (avr_params->avr_mode) {
  149. avr_ctrl = BIT(0);
  150. avr_mode =
  151. (avr_params->avr_mode == SDE_RM_QSYNC_ONE_SHOT_MODE) ?
  152. (BIT(0) | BIT(8)) : 0x0;
  153. }
  154. SDE_REG_WRITE(c, INTF_AVR_CONTROL, avr_ctrl);
  155. SDE_REG_WRITE(c, INTF_AVR_MODE, avr_mode);
  156. }
  157. static inline void _check_and_set_comp_bit(struct sde_hw_intf *ctx,
  158. bool dsc_4hs_merge, bool compression_en, u32 *intf_cfg2)
  159. {
  160. if (((SDE_HW_MAJOR(ctx->mdss->hwversion) >=
  161. SDE_HW_MAJOR(SDE_HW_VER_700)) &&
  162. compression_en) ||
  163. (IS_SDE_MAJOR_SAME(ctx->mdss->hwversion,
  164. SDE_HW_VER_600) && dsc_4hs_merge))
  165. (*intf_cfg2) |= BIT(12);
  166. }
  167. static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
  168. const struct intf_timing_params *p,
  169. const struct sde_format *fmt)
  170. {
  171. struct sde_hw_blk_reg_map *c = &ctx->hw;
  172. u32 hsync_period, vsync_period;
  173. u32 display_v_start, display_v_end;
  174. u32 hsync_start_x, hsync_end_x;
  175. u32 active_h_start, active_h_end;
  176. u32 active_v_start, active_v_end;
  177. u32 active_hctl, display_hctl, hsync_ctl;
  178. u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
  179. u32 panel_format;
  180. u32 intf_cfg, intf_cfg2;
  181. u32 display_data_hctl = 0, active_data_hctl = 0;
  182. bool dp_intf = false;
  183. /* read interface_cfg */
  184. intf_cfg = SDE_REG_READ(c, INTF_CONFIG);
  185. hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
  186. p->h_front_porch;
  187. vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
  188. p->v_front_porch;
  189. display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
  190. hsync_period) + p->hsync_skew;
  191. display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
  192. p->hsync_skew - 1;
  193. hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
  194. hsync_end_x = hsync_period - p->h_front_porch - 1;
  195. if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP)
  196. dp_intf = true;
  197. if (p->width != p->xres) {
  198. active_h_start = hsync_start_x;
  199. active_h_end = active_h_start + p->xres - 1;
  200. } else {
  201. active_h_start = 0;
  202. active_h_end = 0;
  203. }
  204. if (p->height != p->yres) {
  205. active_v_start = display_v_start;
  206. active_v_end = active_v_start + (p->yres * hsync_period) - 1;
  207. } else {
  208. active_v_start = 0;
  209. active_v_end = 0;
  210. }
  211. if (active_h_end) {
  212. active_hctl = (active_h_end << 16) | active_h_start;
  213. intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
  214. } else {
  215. active_hctl = 0;
  216. }
  217. if (active_v_end)
  218. intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
  219. hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
  220. display_hctl = (hsync_end_x << 16) | hsync_start_x;
  221. if (dp_intf) {
  222. active_h_start = hsync_start_x;
  223. active_h_end = active_h_start + p->xres - 1;
  224. active_v_start = display_v_start;
  225. active_v_end = active_v_start + (p->yres * hsync_period) - 1;
  226. display_v_start += p->hsync_pulse_width + p->h_back_porch;
  227. active_hctl = (active_h_end << 16) | active_h_start;
  228. display_hctl = active_hctl;
  229. }
  230. intf_cfg2 = 0;
  231. _check_and_set_comp_bit(ctx, p->dsc_4hs_merge, p->compression_en,
  232. &intf_cfg2);
  233. if (dp_intf && p->compression_en) {
  234. active_data_hctl = (hsync_start_x + p->extra_dto_cycles) << 16;
  235. active_data_hctl += hsync_start_x;
  236. display_data_hctl = active_data_hctl;
  237. intf_cfg2 |= BIT(4);
  238. }
  239. den_polarity = 0;
  240. if (ctx->cap->type == INTF_HDMI) {
  241. hsync_polarity = p->yres >= 720 ? 0 : 1;
  242. vsync_polarity = p->yres >= 720 ? 0 : 1;
  243. } else if (ctx->cap->type == INTF_DP) {
  244. hsync_polarity = p->hsync_polarity;
  245. vsync_polarity = p->vsync_polarity;
  246. } else {
  247. hsync_polarity = 0;
  248. vsync_polarity = 0;
  249. }
  250. polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
  251. (vsync_polarity << 1) | /* VSYNC Polarity */
  252. (hsync_polarity << 0); /* HSYNC Polarity */
  253. if (!SDE_FORMAT_IS_YUV(fmt))
  254. panel_format = (fmt->bits[C0_G_Y] |
  255. (fmt->bits[C1_B_Cb] << 2) |
  256. (fmt->bits[C2_R_Cr] << 4) |
  257. (0x21 << 8));
  258. else
  259. /* Interface treats all the pixel data in RGB888 format */
  260. panel_format = (COLOR_8BIT |
  261. (COLOR_8BIT << 2) |
  262. (COLOR_8BIT << 4) |
  263. (0x21 << 8));
  264. if (p->wide_bus_en)
  265. intf_cfg2 |= BIT(0);
  266. if (ctx->cfg.split_link_en)
  267. SDE_REG_WRITE(c, INTF_REG_SPLIT_LINK, 0x3);
  268. SDE_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
  269. SDE_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
  270. SDE_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
  271. p->vsync_pulse_width * hsync_period);
  272. SDE_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
  273. SDE_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
  274. SDE_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
  275. SDE_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
  276. SDE_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
  277. SDE_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
  278. SDE_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
  279. SDE_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
  280. SDE_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
  281. SDE_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
  282. SDE_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
  283. SDE_REG_WRITE(c, INTF_CONFIG, intf_cfg);
  284. SDE_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
  285. SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
  286. SDE_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
  287. SDE_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);
  288. }
  289. static void sde_hw_intf_enable_timing_engine(
  290. struct sde_hw_intf *intf,
  291. u8 enable)
  292. {
  293. struct sde_hw_blk_reg_map *c = &intf->hw;
  294. /* Note: Display interface select is handled in top block hw layer */
  295. SDE_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
  296. }
  297. static void sde_hw_intf_setup_prg_fetch(
  298. struct sde_hw_intf *intf,
  299. const struct intf_prog_fetch *fetch)
  300. {
  301. struct sde_hw_blk_reg_map *c = &intf->hw;
  302. int fetch_enable;
  303. /*
  304. * Fetch should always be outside the active lines. If the fetching
  305. * is programmed within active region, hardware behavior is unknown.
  306. */
  307. fetch_enable = SDE_REG_READ(c, INTF_CONFIG);
  308. if (fetch->enable) {
  309. fetch_enable |= BIT(31);
  310. SDE_REG_WRITE(c, INTF_PROG_FETCH_START,
  311. fetch->fetch_start);
  312. } else {
  313. fetch_enable &= ~BIT(31);
  314. }
  315. SDE_REG_WRITE(c, INTF_CONFIG, fetch_enable);
  316. }
  317. static void sde_hw_intf_bind_pingpong_blk(
  318. struct sde_hw_intf *intf,
  319. bool enable,
  320. const enum sde_pingpong pp)
  321. {
  322. struct sde_hw_blk_reg_map *c;
  323. u32 mux_cfg;
  324. if (!intf)
  325. return;
  326. c = &intf->hw;
  327. mux_cfg = SDE_REG_READ(c, INTF_MUX);
  328. mux_cfg &= ~0xf;
  329. if (enable) {
  330. mux_cfg |= (pp - PINGPONG_0) & 0x7;
  331. if (intf->cfg.split_link_en)
  332. mux_cfg = 0x60000;
  333. } else {
  334. mux_cfg = 0xf000f;
  335. }
  336. SDE_REG_WRITE(c, INTF_MUX, mux_cfg);
  337. }
  338. static void sde_hw_intf_get_status(
  339. struct sde_hw_intf *intf,
  340. struct intf_status *s)
  341. {
  342. struct sde_hw_blk_reg_map *c = &intf->hw;
  343. s->is_en = SDE_REG_READ(c, INTF_TIMING_ENGINE_EN);
  344. if (s->is_en) {
  345. s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
  346. s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT);
  347. } else {
  348. s->line_count = 0;
  349. s->frame_count = 0;
  350. }
  351. }
  352. static void sde_hw_intf_v1_get_status(
  353. struct sde_hw_intf *intf,
  354. struct intf_status *s)
  355. {
  356. struct sde_hw_blk_reg_map *c = &intf->hw;
  357. s->is_en = SDE_REG_READ(c, INTF_STATUS) & BIT(0);
  358. if (s->is_en) {
  359. s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
  360. s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT);
  361. } else {
  362. s->line_count = 0;
  363. s->frame_count = 0;
  364. }
  365. }
  366. static void sde_hw_intf_setup_misr(struct sde_hw_intf *intf,
  367. bool enable, u32 frame_count)
  368. {
  369. struct sde_hw_blk_reg_map *c = &intf->hw;
  370. u32 config = 0;
  371. SDE_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
  372. /* clear misr data */
  373. wmb();
  374. if (enable)
  375. config = (frame_count & MISR_FRAME_COUNT_MASK) |
  376. MISR_CTRL_ENABLE |
  377. INTF_MISR_CTRL_FREE_RUN_MASK |
  378. INTF_MISR_CTRL_INPUT_SEL_DATA;
  379. SDE_REG_WRITE(c, INTF_MISR_CTRL, config);
  380. }
  381. static int sde_hw_intf_collect_misr(struct sde_hw_intf *intf, bool nonblock,
  382. u32 *misr_value)
  383. {
  384. struct sde_hw_blk_reg_map *c = &intf->hw;
  385. u32 ctrl = 0;
  386. if (!misr_value)
  387. return -EINVAL;
  388. ctrl = SDE_REG_READ(c, INTF_MISR_CTRL);
  389. if (!nonblock) {
  390. if (ctrl & MISR_CTRL_ENABLE) {
  391. int rc;
  392. rc = readl_poll_timeout(c->base_off + c->blk_off +
  393. INTF_MISR_CTRL, ctrl,
  394. (ctrl & MISR_CTRL_STATUS) > 0, 500,
  395. 84000);
  396. if (rc)
  397. return rc;
  398. } else {
  399. return -EINVAL;
  400. }
  401. }
  402. *misr_value = SDE_REG_READ(c, INTF_MISR_SIGNATURE);
  403. return 0;
  404. }
  405. static u32 sde_hw_intf_get_line_count(struct sde_hw_intf *intf)
  406. {
  407. struct sde_hw_blk_reg_map *c;
  408. if (!intf)
  409. return 0;
  410. c = &intf->hw;
  411. return SDE_REG_READ(c, INTF_LINE_COUNT);
  412. }
  413. static u32 sde_hw_intf_get_underrun_line_count(struct sde_hw_intf *intf)
  414. {
  415. struct sde_hw_blk_reg_map *c;
  416. u32 hsync_period;
  417. if (!intf)
  418. return 0;
  419. c = &intf->hw;
  420. hsync_period = SDE_REG_READ(c, INTF_HSYNC_CTL);
  421. hsync_period = ((hsync_period & 0xffff0000) >> 16);
  422. return hsync_period ?
  423. SDE_REG_READ(c, INTF_UNDERRUN_COUNT) / hsync_period :
  424. 0xebadebad;
  425. }
  426. static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
  427. struct sde_hw_tear_check *te)
  428. {
  429. struct sde_hw_blk_reg_map *c;
  430. int cfg;
  431. if (!intf)
  432. return -EINVAL;
  433. c = &intf->hw;
  434. cfg = BIT(19); /* VSYNC_COUNTER_EN */
  435. if (te->hw_vsync_mode)
  436. cfg |= BIT(20);
  437. cfg |= te->vsync_count;
  438. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  439. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
  440. SDE_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);
  441. SDE_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);
  442. SDE_REG_WRITE(c, INTF_TEAR_WR_PTR_IRQ, te->wr_ptr_irq);
  443. SDE_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);
  444. SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH,
  445. ((te->sync_threshold_continue << 16) |
  446. te->sync_threshold_start));
  447. SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
  448. (te->start_pos + te->sync_threshold_start + 1));
  449. return 0;
  450. }
  451. static int sde_hw_intf_setup_autorefresh_config(struct sde_hw_intf *intf,
  452. struct sde_hw_autorefresh *cfg)
  453. {
  454. struct sde_hw_blk_reg_map *c;
  455. u32 refresh_cfg;
  456. if (!intf || !cfg)
  457. return -EINVAL;
  458. c = &intf->hw;
  459. if (cfg->enable)
  460. refresh_cfg = BIT(31) | cfg->frame_count;
  461. else
  462. refresh_cfg = 0;
  463. SDE_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg);
  464. return 0;
  465. }
  466. static int sde_hw_intf_get_autorefresh_config(struct sde_hw_intf *intf,
  467. struct sde_hw_autorefresh *cfg)
  468. {
  469. struct sde_hw_blk_reg_map *c;
  470. u32 val;
  471. if (!intf || !cfg)
  472. return -EINVAL;
  473. c = &intf->hw;
  474. val = SDE_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG);
  475. cfg->enable = (val & BIT(31)) >> 31;
  476. cfg->frame_count = val & 0xffff;
  477. return 0;
  478. }
  479. static int sde_hw_intf_poll_timeout_wr_ptr(struct sde_hw_intf *intf,
  480. u32 timeout_us)
  481. {
  482. struct sde_hw_blk_reg_map *c;
  483. u32 val;
  484. int rc;
  485. if (!intf)
  486. return -EINVAL;
  487. c = &intf->hw;
  488. rc = readl_poll_timeout(c->base_off + c->blk_off + INTF_TEAR_LINE_COUNT,
  489. val, (val & 0xffff) >= 1, 10, timeout_us);
  490. return rc;
  491. }
  492. static int sde_hw_intf_enable_te(struct sde_hw_intf *intf, bool enable)
  493. {
  494. struct sde_hw_blk_reg_map *c;
  495. if (!intf)
  496. return -EINVAL;
  497. c = &intf->hw;
  498. SDE_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, enable);
  499. return 0;
  500. }
  501. static void sde_hw_intf_update_te(struct sde_hw_intf *intf,
  502. struct sde_hw_tear_check *te)
  503. {
  504. struct sde_hw_blk_reg_map *c;
  505. int cfg;
  506. if (!intf || !te)
  507. return;
  508. c = &intf->hw;
  509. cfg = SDE_REG_READ(c, INTF_TEAR_SYNC_THRESH);
  510. cfg &= ~0xFFFF;
  511. cfg |= te->sync_threshold_start;
  512. SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, cfg);
  513. }
  514. static int sde_hw_intf_connect_external_te(struct sde_hw_intf *intf,
  515. bool enable_external_te)
  516. {
  517. struct sde_hw_blk_reg_map *c = &intf->hw;
  518. u32 cfg;
  519. int orig;
  520. if (!intf)
  521. return -EINVAL;
  522. c = &intf->hw;
  523. cfg = SDE_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC);
  524. orig = (bool)(cfg & BIT(20));
  525. if (enable_external_te)
  526. cfg |= BIT(20);
  527. else
  528. cfg &= ~BIT(20);
  529. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  530. return orig;
  531. }
  532. static int sde_hw_intf_get_vsync_info(struct sde_hw_intf *intf,
  533. struct sde_hw_pp_vsync_info *info)
  534. {
  535. struct sde_hw_blk_reg_map *c = &intf->hw;
  536. u32 val;
  537. if (!intf || !info)
  538. return -EINVAL;
  539. c = &intf->hw;
  540. val = SDE_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL);
  541. info->rd_ptr_init_val = val & 0xffff;
  542. val = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);
  543. info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
  544. info->rd_ptr_line_count = val & 0xffff;
  545. val = SDE_REG_READ(c, INTF_TEAR_LINE_COUNT);
  546. info->wr_ptr_line_count = val & 0xffff;
  547. val = SDE_REG_READ(c, INTF_FRAME_COUNT);
  548. info->intf_frame_count = val;
  549. return 0;
  550. }
  551. static void sde_hw_intf_vsync_sel(struct sde_hw_intf *intf,
  552. u32 vsync_source)
  553. {
  554. struct sde_hw_blk_reg_map *c;
  555. if (!intf)
  556. return;
  557. c = &intf->hw;
  558. SDE_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf));
  559. }
  560. static void sde_hw_intf_enable_compressed_input(struct sde_hw_intf *intf,
  561. bool compression_en, bool dsc_4hs_merge)
  562. {
  563. struct sde_hw_blk_reg_map *c;
  564. u32 intf_cfg2;
  565. if (!intf)
  566. return;
  567. /*
  568. * callers can either call this function to enable/disable the 64 bit
  569. * compressed input or this configuration can be applied along
  570. * with timing generation parameters
  571. */
  572. c = &intf->hw;
  573. intf_cfg2 = SDE_REG_READ(c, INTF_CONFIG2);
  574. _check_and_set_comp_bit(intf, dsc_4hs_merge, compression_en,
  575. &intf_cfg2);
  576. SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
  577. }
  578. static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
  579. unsigned long cap)
  580. {
  581. ops->setup_timing_gen = sde_hw_intf_setup_timing_engine;
  582. ops->setup_prg_fetch = sde_hw_intf_setup_prg_fetch;
  583. ops->get_status = sde_hw_intf_get_status;
  584. ops->enable_timing = sde_hw_intf_enable_timing_engine;
  585. ops->setup_misr = sde_hw_intf_setup_misr;
  586. ops->collect_misr = sde_hw_intf_collect_misr;
  587. ops->get_line_count = sde_hw_intf_get_line_count;
  588. ops->get_underrun_line_count = sde_hw_intf_get_underrun_line_count;
  589. ops->avr_setup = sde_hw_intf_avr_setup;
  590. ops->avr_trigger = sde_hw_intf_avr_trigger;
  591. ops->avr_ctrl = sde_hw_intf_avr_ctrl;
  592. ops->enable_compressed_input = sde_hw_intf_enable_compressed_input;
  593. if (cap & BIT(SDE_INTF_INPUT_CTRL))
  594. ops->bind_pingpong_blk = sde_hw_intf_bind_pingpong_blk;
  595. if (cap & BIT(SDE_INTF_TE)) {
  596. ops->setup_tearcheck = sde_hw_intf_setup_te_config;
  597. ops->enable_tearcheck = sde_hw_intf_enable_te;
  598. ops->update_tearcheck = sde_hw_intf_update_te;
  599. ops->connect_external_te = sde_hw_intf_connect_external_te;
  600. ops->get_vsync_info = sde_hw_intf_get_vsync_info;
  601. ops->setup_autorefresh = sde_hw_intf_setup_autorefresh_config;
  602. ops->get_autorefresh = sde_hw_intf_get_autorefresh_config;
  603. ops->poll_timeout_wr_ptr = sde_hw_intf_poll_timeout_wr_ptr;
  604. ops->vsync_sel = sde_hw_intf_vsync_sel;
  605. ops->get_status = sde_hw_intf_v1_get_status;
  606. }
  607. }
  608. static struct sde_hw_blk_ops sde_hw_ops = {
  609. .start = NULL,
  610. .stop = NULL,
  611. };
  612. struct sde_hw_intf *sde_hw_intf_init(enum sde_intf idx,
  613. void __iomem *addr,
  614. struct sde_mdss_cfg *m)
  615. {
  616. struct sde_hw_intf *c;
  617. struct sde_intf_cfg *cfg;
  618. int rc;
  619. c = kzalloc(sizeof(*c), GFP_KERNEL);
  620. if (!c)
  621. return ERR_PTR(-ENOMEM);
  622. cfg = _intf_offset(idx, m, addr, &c->hw);
  623. if (IS_ERR_OR_NULL(cfg)) {
  624. kfree(c);
  625. pr_err("failed to create sde_hw_intf %d\n", idx);
  626. return ERR_PTR(-EINVAL);
  627. }
  628. /*
  629. * Assign ops
  630. */
  631. c->idx = idx;
  632. c->cap = cfg;
  633. c->mdss = m;
  634. _setup_intf_ops(&c->ops, c->cap->features);
  635. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_INTF, idx, &sde_hw_ops);
  636. if (rc) {
  637. SDE_ERROR("failed to init hw blk %d\n", rc);
  638. goto blk_init_error;
  639. }
  640. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  641. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  642. return c;
  643. blk_init_error:
  644. kzfree(c);
  645. return ERR_PTR(rc);
  646. }
  647. void sde_hw_intf_destroy(struct sde_hw_intf *intf)
  648. {
  649. if (intf)
  650. sde_hw_blk_destroy(&intf->base);
  651. kfree(intf);
  652. }