sde_hw_ctl.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SDE_HW_CTL_H
  6. #define _SDE_HW_CTL_H
  7. #include "sde_hw_mdss.h"
  8. #include "sde_hw_util.h"
  9. #include "sde_hw_catalog.h"
  10. #include "sde_hw_sspp.h"
  11. #include "sde_hw_blk.h"
  12. #define INVALID_CTL_STATUS 0xfffff88e
  13. #define CTL_MAX_DSPP_COUNT (DSPP_MAX - DSPP_0)
  14. /**
  15. * sde_ctl_mode_sel: Interface mode selection
  16. * SDE_CTL_MODE_SEL_VID: Video mode interface
  17. * SDE_CTL_MODE_SEL_CMD: Command mode interface
  18. */
  19. enum sde_ctl_mode_sel {
  20. SDE_CTL_MODE_SEL_VID = 0,
  21. SDE_CTL_MODE_SEL_CMD
  22. };
  23. /**
  24. * sde_ctl_rot_op_mode - inline rotation mode
  25. * SDE_CTL_ROT_OP_MODE_OFFLINE: offline rotation
  26. * SDE_CTL_ROT_OP_MODE_RESERVED: reserved
  27. * SDE_CTL_ROT_OP_MODE_INLINE_SYNC: inline rotation synchronous mode
  28. * SDE_CTL_ROT_OP_MODE_INLINE_ASYNC: inline rotation asynchronous mode
  29. */
  30. enum sde_ctl_rot_op_mode {
  31. SDE_CTL_ROT_OP_MODE_OFFLINE,
  32. SDE_CTL_ROT_OP_MODE_RESERVED,
  33. SDE_CTL_ROT_OP_MODE_INLINE_SYNC,
  34. SDE_CTL_ROT_OP_MODE_INLINE_ASYNC,
  35. };
  36. struct sde_hw_ctl;
  37. /**
  38. * struct sde_hw_stage_cfg - blending stage cfg
  39. * @stage : SSPP_ID at each stage
  40. * @multirect_index: index of the rectangle of SSPP.
  41. */
  42. struct sde_hw_stage_cfg {
  43. enum sde_sspp stage[SDE_STAGE_MAX][PIPES_PER_STAGE];
  44. enum sde_sspp_multirect_index multirect_index
  45. [SDE_STAGE_MAX][PIPES_PER_STAGE];
  46. };
  47. /**
  48. * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface
  49. * @intf : Interface id
  50. * @wb: Writeback id
  51. * @mode_3d: 3d mux configuration
  52. * @intf_mode_sel: Interface mode, cmd / vid
  53. * @stream_sel: Stream selection for multi-stream interfaces
  54. */
  55. struct sde_hw_intf_cfg {
  56. enum sde_intf intf;
  57. enum sde_wb wb;
  58. enum sde_3d_blend_mode mode_3d;
  59. enum sde_ctl_mode_sel intf_mode_sel;
  60. int stream_sel;
  61. };
  62. /**
  63. * struct sde_hw_intf_cfg_v1 :Describes the data strcuture to configure the
  64. * output interfaces for a particular display on a
  65. * platform which supports ctl path version 1.
  66. * @intf_count: No. of active interfaces for this display
  67. * @intf : Interface ids of active interfaces
  68. * @intf_mode_sel: Interface mode, cmd / vid
  69. * @intf_master: Master interface for split display
  70. * @wb_count: No. of active writebacks
  71. * @wb: Writeback ids of active writebacks
  72. * @merge_3d_count No. of active merge_3d blocks
  73. * @merge_3d: Id of the active merge 3d blocks
  74. * @cwb_count: No. of active concurrent writebacks
  75. * @cwb: Id of active cwb blocks
  76. * @cdm_count: No. of active chroma down module
  77. * @cdm: Id of active cdm blocks
  78. * @dsc_count: No. of active dsc blocks
  79. * @dsc: Id of active dsc blocks
  80. * @vdc_count: No. of active vdc blocks
  81. * @vdc: Id of active vdc blocks
  82. */
  83. struct sde_hw_intf_cfg_v1 {
  84. uint32_t intf_count;
  85. enum sde_intf intf[MAX_INTF_PER_CTL_V1];
  86. enum sde_ctl_mode_sel intf_mode_sel;
  87. enum sde_intf intf_master;
  88. uint32_t wb_count;
  89. enum sde_wb wb[MAX_WB_PER_CTL_V1];
  90. uint32_t merge_3d_count;
  91. enum sde_merge_3d merge_3d[MAX_MERGE_3D_PER_CTL_V1];
  92. uint32_t cwb_count;
  93. enum sde_cwb cwb[MAX_CWB_PER_CTL_V1];
  94. uint32_t cdm_count;
  95. enum sde_cdm cdm[MAX_CDM_PER_CTL_V1];
  96. uint32_t dsc_count;
  97. enum sde_dsc dsc[MAX_DSC_PER_CTL_V1];
  98. uint32_t vdc_count;
  99. enum sde_vdc vdc[MAX_VDC_PER_CTL_V1];
  100. };
  101. /**
  102. * struct sde_ctl_flush_cfg - struct describing flush configuration managed
  103. * via set, trigger and clear ops.
  104. * set ops corresponding to the hw_block is called, when the block's
  105. * configuration is changed and needs to be committed on Hw. Flush mask caches
  106. * the different bits for the ongoing commit.
  107. * clear ops clears the bitmask and cancels the update to the corresponding
  108. * hw block.
  109. * trigger op will trigger the update on the hw for the blocks cached in the
  110. * pending flush mask.
  111. *
  112. * @pending_flush_mask: pending ctl_flush
  113. * CTL path version SDE_CTL_CFG_VERSION_1_0_0 has * two level flush mechanism
  114. * for lower pipe controls. individual control should be flushed before
  115. * exercising top level flush
  116. * @pending_intf_flush_mask: pending INTF flush
  117. * @pending_cdm_flush_mask: pending CDWN block flush
  118. * @pending_wb_flush_mask: pending writeback flush
  119. * @pending_dsc_flush_mask: pending dsc flush
  120. * @pending_merge_3d_flush_mask: pending 3d merge block flush
  121. * @pending_cwb_flush_mask: pending flush for concurrent writeback
  122. * @pending_periph_flush_mask: pending flush for peripheral module
  123. * @pending_dspp_flush_masks: pending flush masks for sub-blks of each DSPP
  124. */
  125. struct sde_ctl_flush_cfg {
  126. u32 pending_flush_mask;
  127. u32 pending_intf_flush_mask;
  128. u32 pending_cdm_flush_mask;
  129. u32 pending_wb_flush_mask;
  130. u32 pending_dsc_flush_mask;
  131. u32 pending_merge_3d_flush_mask;
  132. u32 pending_cwb_flush_mask;
  133. u32 pending_periph_flush_mask;
  134. u32 pending_dspp_flush_masks[CTL_MAX_DSPP_COUNT];
  135. };
  136. /**
  137. * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions
  138. * Assumption is these functions will be called after clocks are enabled
  139. */
  140. struct sde_hw_ctl_ops {
  141. /**
  142. * kickoff hw operation for Sw controlled interfaces
  143. * DSI cmd mode and WB interface are SW controlled
  144. * @ctx : ctl path ctx pointer
  145. * @Return: error code
  146. */
  147. int (*trigger_start)(struct sde_hw_ctl *ctx);
  148. /**
  149. * kickoff prepare is in progress hw operation for sw
  150. * controlled interfaces: DSI cmd mode and WB interface
  151. * are SW controlled
  152. * @ctx : ctl path ctx pointer
  153. * @Return: error code
  154. */
  155. int (*trigger_pending)(struct sde_hw_ctl *ctx);
  156. /**
  157. * kickoff rotator operation for Sw controlled interfaces
  158. * DSI cmd mode and WB interface are SW controlled
  159. * @ctx : ctl path ctx pointer
  160. * @Return: error code
  161. */
  162. int (*trigger_rot_start)(struct sde_hw_ctl *ctx);
  163. /**
  164. * enable/disable UIDLE feature
  165. * @ctx : ctl path ctx pointer
  166. * @enable: true to enable the feature
  167. */
  168. void (*uidle_enable)(struct sde_hw_ctl *ctx, bool enable);
  169. /**
  170. * Clear the value of the cached pending_flush_mask
  171. * No effect on hardware
  172. * @ctx : ctl path ctx pointer
  173. * @Return: error code
  174. */
  175. int (*clear_pending_flush)(struct sde_hw_ctl *ctx);
  176. /**
  177. * Query the value of the cached pending_flush_mask
  178. * No effect on hardware
  179. * @ctx : ctl path ctx pointer
  180. * @cfg : current flush configuration
  181. * @Return: error code
  182. */
  183. int (*get_pending_flush)(struct sde_hw_ctl *ctx,
  184. struct sde_ctl_flush_cfg *cfg);
  185. /**
  186. * OR in the given flushbits to the flush_cfg
  187. * No effect on hardware
  188. * @ctx : ctl path ctx pointer
  189. * @cfg : flush configuration pointer
  190. * @Return: error code
  191. */
  192. int (*update_pending_flush)(struct sde_hw_ctl *ctx,
  193. struct sde_ctl_flush_cfg *cfg);
  194. /**
  195. * Write the value of the pending_flush_mask to hardware
  196. * @ctx : ctl path ctx pointer
  197. * @Return: error code
  198. */
  199. int (*trigger_flush)(struct sde_hw_ctl *ctx);
  200. /**
  201. * Read the value of the flush register
  202. * @ctx : ctl path ctx pointer
  203. * @Return: value of the ctl flush register.
  204. */
  205. u32 (*get_flush_register)(struct sde_hw_ctl *ctx);
  206. /**
  207. * Setup ctl_path interface config
  208. * @ctx
  209. * @cfg : interface config structure pointer
  210. * @Return: error code
  211. */
  212. int (*setup_intf_cfg)(struct sde_hw_ctl *ctx,
  213. struct sde_hw_intf_cfg *cfg);
  214. /**
  215. * Reset ctl_path interface config
  216. * @ctx : ctl path ctx pointer
  217. * @cfg : interface config structure pointer
  218. * @merge_3d_idx : index of merge3d blk
  219. * @Return: error code
  220. */
  221. int (*reset_post_disable)(struct sde_hw_ctl *ctx,
  222. struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx);
  223. /** update cwb for ctl_path
  224. * @ctx : ctl path ctx pointer
  225. * @cfg : interface config structure pointer
  226. * @enable : enable/disable the dynamic sub-blocks in interface cfg
  227. * @Return: error code
  228. */
  229. int (*update_intf_cfg)(struct sde_hw_ctl *ctx,
  230. struct sde_hw_intf_cfg_v1 *cfg, bool enable);
  231. /**
  232. * Setup ctl_path interface config for SDE_CTL_ACTIVE_CFG
  233. * @ctx : ctl path ctx pointer
  234. * @cfg : interface config structure pointer
  235. * @Return: error code
  236. */
  237. int (*setup_intf_cfg_v1)(struct sde_hw_ctl *ctx,
  238. struct sde_hw_intf_cfg_v1 *cfg);
  239. /**
  240. * Update the interface selection with input WB config
  241. * @ctx : ctl path ctx pointer
  242. * @cfg : pointer to input wb config
  243. * @enable : set if true, clear otherwise
  244. */
  245. void (*update_wb_cfg)(struct sde_hw_ctl *ctx,
  246. struct sde_hw_intf_cfg *cfg, bool enable);
  247. int (*reset)(struct sde_hw_ctl *c);
  248. /**
  249. * get_reset - check ctl reset status bit
  250. * @ctx : ctl path ctx pointer
  251. * Returns: current value of ctl reset status
  252. */
  253. u32 (*get_reset)(struct sde_hw_ctl *ctx);
  254. /**
  255. * get_scheduler_reset - check ctl scheduler status bit
  256. * @ctx : ctl path ctx pointer
  257. * Returns: current value of ctl scheduler and idle status
  258. */
  259. u32 (*get_scheduler_status)(struct sde_hw_ctl *ctx);
  260. /**
  261. * hard_reset - force reset on ctl_path
  262. * @ctx : ctl path ctx pointer
  263. * @enable : whether to enable/disable hard reset
  264. */
  265. void (*hard_reset)(struct sde_hw_ctl *c, bool enable);
  266. /*
  267. * wait_reset_status - checks ctl reset status
  268. * @ctx : ctl path ctx pointer
  269. *
  270. * This function checks the ctl reset status bit.
  271. * If the reset bit is set, it keeps polling the status till the hw
  272. * reset is complete.
  273. * Returns: 0 on success or -error if reset incomplete within interval
  274. */
  275. int (*wait_reset_status)(struct sde_hw_ctl *ctx);
  276. /**
  277. * update_bitmask_sspp: updates mask corresponding to sspp
  278. * @blk : blk id
  279. * @enable : true to enable, 0 to disable
  280. */
  281. int (*update_bitmask_sspp)(struct sde_hw_ctl *ctx,
  282. enum sde_sspp blk, bool enable);
  283. /**
  284. * update_bitmask_sspp: updates mask corresponding to sspp
  285. * @blk : blk id
  286. * @enable : true to enable, 0 to disable
  287. */
  288. int (*update_bitmask_mixer)(struct sde_hw_ctl *ctx,
  289. enum sde_lm blk, bool enable);
  290. /**
  291. * update_bitmask_sspp: updates mask corresponding to sspp
  292. * @blk : blk id
  293. * @enable : true to enable, 0 to disable
  294. */
  295. int (*update_bitmask_dspp)(struct sde_hw_ctl *ctx,
  296. enum sde_dspp blk, bool enable);
  297. /**
  298. * update_bitmask_sspp: updates mask corresponding to sspp
  299. * @blk : blk id
  300. * @enable : true to enable, 0 to disable
  301. */
  302. int (*update_bitmask_dspp_pavlut)(struct sde_hw_ctl *ctx,
  303. enum sde_dspp blk, bool enable);
  304. /**
  305. * Program DSPP sub block specific bit of dspp flush register.
  306. * @ctx : ctl path ctx pointer
  307. * @dspp : HW block ID of dspp block
  308. * @sub_blk : enum of DSPP sub block to flush
  309. * @enable : true to enable, 0 to disable
  310. *
  311. * This API is for CTL with DSPP flush hierarchy registers.
  312. */
  313. int (*update_bitmask_dspp_subblk)(struct sde_hw_ctl *ctx,
  314. enum sde_dspp dspp, u32 sub_blk, bool enable);
  315. /**
  316. * update_bitmask_sspp: updates mask corresponding to sspp
  317. * @blk : blk id
  318. * @enable : true to enable, 0 to disable
  319. */
  320. int (*update_bitmask_intf)(struct sde_hw_ctl *ctx,
  321. enum sde_intf blk, bool enable);
  322. /**
  323. * update_bitmask_sspp: updates mask corresponding to sspp
  324. * @blk : blk id
  325. * @enable : true to enable, 0 to disable
  326. */
  327. int (*update_bitmask_cdm)(struct sde_hw_ctl *ctx,
  328. enum sde_cdm blk, bool enable);
  329. /**
  330. * update_bitmask_sspp: updates mask corresponding to sspp
  331. * @blk : blk id
  332. * @enable : true to enable, 0 to disable
  333. */
  334. int (*update_bitmask_wb)(struct sde_hw_ctl *ctx,
  335. enum sde_wb blk, bool enable);
  336. /**
  337. * update_bitmask_sspp: updates mask corresponding to sspp
  338. * @blk : blk id
  339. * @enable : true to enable, 0 to disable
  340. */
  341. int (*update_bitmask_rot)(struct sde_hw_ctl *ctx,
  342. enum sde_rot blk, bool enable);
  343. /**
  344. * update_bitmask_dsc: updates mask corresponding to dsc
  345. * @blk : blk id
  346. * @enable : true to enable, 0 to disable
  347. */
  348. int (*update_bitmask_dsc)(struct sde_hw_ctl *ctx,
  349. enum sde_dsc blk, bool enable);
  350. /**
  351. * update_bitmask_vdc: updates mask corresponding to vdc
  352. * @blk : blk id
  353. * @enable : true to enable, 0 to disable
  354. */
  355. int (*update_bitmask_vdc)(struct sde_hw_ctl *ctx,
  356. enum sde_vdc blk, bool enable);
  357. /**
  358. * update_bitmask_merge3d: updates mask corresponding to merge_3d
  359. * @blk : blk id
  360. * @enable : true to enable, 0 to disable
  361. */
  362. int (*update_bitmask_merge3d)(struct sde_hw_ctl *ctx,
  363. enum sde_merge_3d blk, bool enable);
  364. /**
  365. * update_bitmask_cwb: updates mask corresponding to cwb
  366. * @blk : blk id
  367. * @enable : true to enable, 0 to disable
  368. */
  369. int (*update_bitmask_cwb)(struct sde_hw_ctl *ctx,
  370. enum sde_cwb blk, bool enable);
  371. /**
  372. * update_bitmask_periph: updates mask corresponding to peripheral
  373. * @blk : blk id
  374. * @enable : true to enable, 0 to disable
  375. */
  376. int (*update_bitmask_periph)(struct sde_hw_ctl *ctx,
  377. enum sde_intf blk, bool enable);
  378. /**
  379. * read CTL_TOP register value and return
  380. * the data.
  381. * @ctx : ctl path ctx pointer
  382. * @return : CTL top register value
  383. */
  384. u32 (*read_ctl_top)(struct sde_hw_ctl *ctx);
  385. /**
  386. * get interfaces for the active CTL .
  387. * @ctx : ctl path ctx pointer
  388. * @return : bit mask with the active interfaces for the CTL
  389. */
  390. u32 (*get_ctl_intf)(struct sde_hw_ctl *ctx);
  391. /**
  392. * read CTL layers register value and return
  393. * the data.
  394. * @ctx : ctl path ctx pointer
  395. * @index : layer index for this ctl path
  396. * @return : CTL layers register value
  397. */
  398. u32 (*read_ctl_layers)(struct sde_hw_ctl *ctx, int index);
  399. /**
  400. * read active register configuration for this block
  401. * @ctx : ctl path ctx pointer
  402. * @blk : hw blk type, supported blocks are DSC, MERGE_3D, INTF,
  403. * CDM, WB
  404. * @index : blk index
  405. * @return : true if blk at idx is active or false
  406. */
  407. bool (*read_active_status)(struct sde_hw_ctl *ctx,
  408. enum sde_hw_blk_type blk, int index);
  409. /**
  410. * Set all blend stages to disabled
  411. * @ctx : ctl path ctx pointer
  412. */
  413. void (*clear_all_blendstages)(struct sde_hw_ctl *ctx);
  414. /**
  415. * Configure layer mixer to pipe configuration
  416. * @ctx : ctl path ctx pointer
  417. * @lm : layer mixer enumeration
  418. * @cfg : blend stage configuration
  419. */
  420. void (*setup_blendstage)(struct sde_hw_ctl *ctx,
  421. enum sde_lm lm, struct sde_hw_stage_cfg *cfg);
  422. /**
  423. * Get all the sspp staged on a layer mixer
  424. * @ctx : ctl path ctx pointer
  425. * @lm : layer mixer enumeration
  426. * @info : array address to populate connected sspp index info
  427. * @info_max_cnt : maximum sspp info elements based on array size
  428. * @Return: count of sspps info elements populated
  429. */
  430. u32 (*get_staged_sspp)(struct sde_hw_ctl *ctx, enum sde_lm lm,
  431. struct sde_sspp_index_info *info, u32 info_max_cnt);
  432. /**
  433. * Flush the reg dma by sending last command.
  434. * @ctx : ctl path ctx pointer
  435. * @blocking : if set to true api will block until flush is done
  436. * @Return: error code
  437. */
  438. int (*reg_dma_flush)(struct sde_hw_ctl *ctx, bool blocking);
  439. /**
  440. * check if ctl start trigger state to confirm the frame pending
  441. * status
  442. * @ctx : ctl path ctx pointer
  443. * @Return: error code
  444. */
  445. int (*get_start_state)(struct sde_hw_ctl *ctx);
  446. };
  447. /**
  448. * struct sde_hw_ctl : CTL PATH driver object
  449. * @base: hardware block base structure
  450. * @hw: block register map object
  451. * @idx: control path index
  452. * @caps: control path capabilities
  453. * @mixer_count: number of mixers
  454. * @mixer_hw_caps: mixer hardware capabilities
  455. * @flush: storage for pending ctl_flush managed via ops
  456. * @ops: operation list
  457. */
  458. struct sde_hw_ctl {
  459. struct sde_hw_blk base;
  460. struct sde_hw_blk_reg_map hw;
  461. /* ctl path */
  462. int idx;
  463. const struct sde_ctl_cfg *caps;
  464. int mixer_count;
  465. const struct sde_lm_cfg *mixer_hw_caps;
  466. struct sde_ctl_flush_cfg flush;
  467. /* ops */
  468. struct sde_hw_ctl_ops ops;
  469. };
  470. /**
  471. * sde_hw_ctl - convert base object sde_hw_base to container
  472. * @hw: Pointer to base hardware block
  473. * return: Pointer to hardware block container
  474. */
  475. static inline struct sde_hw_ctl *to_sde_hw_ctl(struct sde_hw_blk *hw)
  476. {
  477. return container_of(hw, struct sde_hw_ctl, base);
  478. }
  479. /**
  480. * sde_hw_ctl_init(): Initializes the ctl_path hw driver object.
  481. * should be called before accessing every ctl path registers.
  482. * @idx: ctl_path index for which driver object is required
  483. * @addr: mapped register io address of MDP
  484. * @m : pointer to mdss catalog data
  485. */
  486. struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
  487. void __iomem *addr,
  488. struct sde_mdss_cfg *m);
  489. /**
  490. * sde_hw_ctl_destroy(): Destroys ctl driver context
  491. * should be called to free the context
  492. */
  493. void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx);
  494. #endif /*_SDE_HW_CTL_H */