sde_hw_ctl.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include "sde_hwio.h"
  7. #include "sde_hw_ctl.h"
  8. #include "sde_dbg.h"
  9. #include "sde_kms.h"
  10. #include "sde_reg_dma.h"
  11. #define CTL_LAYER(lm) \
  12. (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
  13. #define CTL_LAYER_EXT(lm) \
  14. (0x40 + (((lm) - LM_0) * 0x004))
  15. #define CTL_LAYER_EXT2(lm) \
  16. (0x70 + (((lm) - LM_0) * 0x004))
  17. #define CTL_LAYER_EXT3(lm) \
  18. (0xA0 + (((lm) - LM_0) * 0x004))
  19. #define CTL_TOP 0x014
  20. #define CTL_FLUSH 0x018
  21. #define CTL_START 0x01C
  22. #define CTL_PREPARE 0x0d0
  23. #define CTL_SW_RESET 0x030
  24. #define CTL_SW_RESET_OVERRIDE 0x060
  25. #define CTL_STATUS 0x064
  26. #define CTL_LAYER_EXTN_OFFSET 0x40
  27. #define CTL_ROT_TOP 0x0C0
  28. #define CTL_ROT_FLUSH 0x0C4
  29. #define CTL_ROT_START 0x0CC
  30. #define CTL_MERGE_3D_ACTIVE 0x0E4
  31. #define CTL_DSC_ACTIVE 0x0E8
  32. #define CTL_WB_ACTIVE 0x0EC
  33. #define CTL_CWB_ACTIVE 0x0F0
  34. #define CTL_INTF_ACTIVE 0x0F4
  35. #define CTL_CDM_ACTIVE 0x0F8
  36. #define CTL_FETCH_PIPE_ACTIVE 0x0FC
  37. #define CTL_MERGE_3D_FLUSH 0x100
  38. #define CTL_DSC_FLUSH 0x104
  39. #define CTL_WB_FLUSH 0x108
  40. #define CTL_CWB_FLUSH 0x10C
  41. #define CTL_INTF_FLUSH 0x110
  42. #define CTL_CDM_FLUSH 0x114
  43. #define CTL_PERIPH_FLUSH 0x128
  44. #define CTL_DSPP_0_FLUSH 0x13c
  45. #define CTL_INTF_MASTER 0x134
  46. #define CTL_UIDLE_ACTIVE 0x138
  47. #define CTL_MIXER_BORDER_OUT BIT(24)
  48. #define CTL_FLUSH_MASK_ROT BIT(27)
  49. #define CTL_FLUSH_MASK_CTL BIT(17)
  50. #define CTL_NUM_EXT 4
  51. #define CTL_SSPP_MAX_RECTS 2
  52. #define SDE_REG_RESET_TIMEOUT_US 2000
  53. #define SDE_REG_WAIT_RESET_TIMEOUT_US 100000
  54. #define UPDATE_MASK(m, idx, en) \
  55. ((m) = (en) ? ((m) | BIT((idx))) : ((m) & ~BIT((idx))))
  56. #define CTL_INVALID_BIT 0xffff
  57. #define VDC_IDX(i) ((i) + 16)
  58. #define UPDATE_ACTIVE(r, idx, en) UPDATE_MASK((r), (idx), (en))
  59. /**
  60. * List of SSPP bits in CTL_FLUSH
  61. */
  62. static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 3, 4, 5,
  63. 19, 11, 12, 24, 25, SDE_NONE, SDE_NONE};
  64. /**
  65. * List of layer mixer bits in CTL_FLUSH
  66. */
  67. static const u32 mixer_tbl[LM_MAX] = {SDE_NONE, 6, 7, 8, 9, 10, 20,
  68. SDE_NONE};
  69. /**
  70. * List of DSPP bits in CTL_FLUSH
  71. */
  72. static const u32 dspp_tbl[DSPP_MAX] = {SDE_NONE, 13, 14, 15, 21};
  73. /**
  74. * List of DSPP PA LUT bits in CTL_FLUSH
  75. */
  76. static const u32 dspp_pav_tbl[DSPP_MAX] = {SDE_NONE, 3, 4, 5, 19};
  77. /**
  78. * List of CDM LUT bits in CTL_FLUSH
  79. */
  80. static const u32 cdm_tbl[CDM_MAX] = {SDE_NONE, 26};
  81. /**
  82. * List of WB bits in CTL_FLUSH
  83. */
  84. static const u32 wb_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 16};
  85. /**
  86. * List of ROT bits in CTL_FLUSH
  87. */
  88. static const u32 rot_tbl[ROT_MAX] = {SDE_NONE, 27};
  89. /**
  90. * List of INTF bits in CTL_FLUSH
  91. */
  92. static const u32 intf_tbl[INTF_MAX] = {SDE_NONE, 31, 30, 29, 28};
  93. /**
  94. * Below definitions are for CTL supporting SDE_CTL_ACTIVE_CFG,
  95. * certain blocks have the individual flush control as well,
  96. * for such blocks flush is done by flushing individual control and
  97. * top level control.
  98. */
  99. /**
  100. * List of SSPP bits in CTL_FETCH_PIPE_ACTIVE
  101. */
  102. static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
  103. CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
  104. 1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
  105. /**
  106. * list of WB bits in CTL_WB_FLUSH
  107. */
  108. static const u32 wb_flush_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 2};
  109. /**
  110. * list of INTF bits in CTL_INTF_FLUSH
  111. */
  112. static const u32 intf_flush_tbl[INTF_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  113. /**
  114. * list of DSC bits in CTL_DSC_FLUSH
  115. */
  116. static const u32 dsc_flush_tbl[DSC_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  117. /**
  118. * list of VDC bits in CTL_DSC_FLUSH
  119. */
  120. static const u32 vdc_flush_tbl[DSC_MAX] = {SDE_NONE, 16, 17};
  121. /**
  122. * list of MERGE_3D bits in CTL_MERGE_3D_FLUSH
  123. */
  124. static const u32 merge_3d_tbl[MERGE_3D_MAX] = {SDE_NONE, 0, 1, 2};
  125. /**
  126. * list of CDM bits in CTL_CDM_FLUSH
  127. */
  128. static const u32 cdm_flush_tbl[CDM_MAX] = {SDE_NONE, 0};
  129. /**
  130. * list of CWB bits in CTL_CWB_FLUSH
  131. */
  132. static const u32 cwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 1, 2, 3,
  133. 4, 5};
  134. /**
  135. * list of DSPP sub-blk flush bits in CTL_DSPP_x_FLUSH
  136. */
  137. static const u32 dspp_sub_blk_flush_tbl[SDE_DSPP_MAX] = {
  138. [SDE_DSPP_IGC] = 2,
  139. [SDE_DSPP_PCC] = 4,
  140. [SDE_DSPP_GC] = 5,
  141. [SDE_DSPP_HSIC] = 0,
  142. [SDE_DSPP_MEMCOLOR] = 0,
  143. [SDE_DSPP_SIXZONE] = 0,
  144. [SDE_DSPP_GAMUT] = 3,
  145. [SDE_DSPP_DITHER] = 0,
  146. [SDE_DSPP_HIST] = 0,
  147. [SDE_DSPP_VLUT] = 1,
  148. [SDE_DSPP_AD] = 0,
  149. [SDE_DSPP_LTM] = 7,
  150. [SDE_DSPP_SPR] = 8,
  151. [SDE_DSPP_DEMURA] = 9,
  152. [SDE_DSPP_RC] = 10,
  153. [SDE_DSPP_SB] = 31,
  154. };
  155. /**
  156. * struct ctl_sspp_stage_reg_map: Describes bit layout for a sspp stage cfg
  157. * @ext: Index to indicate LAYER_x_EXT id for given sspp
  158. * @start: Start position of blend stage bits for given sspp
  159. * @bits: Number of bits from @start assigned for given sspp
  160. * @sec_bit_mask: Bitmask to add to LAYER_x_EXT1 for missing bit of sspp
  161. */
  162. struct ctl_sspp_stage_reg_map {
  163. u32 ext;
  164. u32 start;
  165. u32 bits;
  166. u32 sec_bit_mask;
  167. };
  168. /* list of ctl_sspp_stage_reg_map for all the sppp */
  169. static const struct ctl_sspp_stage_reg_map
  170. sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
  171. /* SSPP_NONE */{ {0, 0, 0, 0}, {0, 0, 0, 0} },
  172. /* SSPP_VIG0 */{ {0, 0, 3, BIT(0)}, {3, 0, 4, 0} },
  173. /* SSPP_VIG1 */{ {0, 3, 3, BIT(2)}, {3, 4, 4, 0} },
  174. /* SSPP_VIG2 */{ {0, 6, 3, BIT(4)}, {3, 8, 4, 0} },
  175. /* SSPP_VIG3 */{ {0, 26, 3, BIT(6)}, {3, 12, 4, 0} },
  176. /* SSPP_RGB0 */{ {0, 9, 3, BIT(8)}, {0, 0, 0, 0} },
  177. /* SSPP_RGB1 */{ {0, 12, 3, BIT(10)}, {0, 0, 0, 0} },
  178. /* SSPP_RGB2 */{ {0, 15, 3, BIT(12)}, {0, 0, 0, 0} },
  179. /* SSPP_RGB3 */{ {0, 29, 3, BIT(14)}, {0, 0, 0, 0} },
  180. /* SSPP_DMA0 */{ {0, 18, 3, BIT(16)}, {2, 8, 4, 0} },
  181. /* SSPP_DMA1 */{ {0, 21, 3, BIT(18)}, {2, 12, 4, 0} },
  182. /* SSPP_DMA2 */{ {2, 0, 4, 0}, {2, 16, 4, 0} },
  183. /* SSPP_DMA3 */{ {2, 4, 4, 0}, {2, 20, 4, 0} },
  184. /* SSPP_CURSOR0 */{ {1, 20, 4, 0}, {0, 0, 0, 0} },
  185. /* SSPP_CURSOR1 */{ {0, 26, 4, 0}, {0, 0, 0, 0} }
  186. };
  187. /**
  188. * Individual flush bit in CTL_FLUSH
  189. */
  190. #define WB_IDX 16
  191. #define DSC_IDX 22
  192. #define MERGE_3D_IDX 23
  193. #define CDM_IDX 26
  194. #define CWB_IDX 28
  195. #define DSPP_IDX 29
  196. #define PERIPH_IDX 30
  197. #define INTF_IDX 31
  198. static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
  199. struct sde_mdss_cfg *m,
  200. void __iomem *addr,
  201. struct sde_hw_blk_reg_map *b)
  202. {
  203. int i;
  204. for (i = 0; i < m->ctl_count; i++) {
  205. if (ctl == m->ctl[i].id) {
  206. b->base_off = addr;
  207. b->blk_off = m->ctl[i].base;
  208. b->length = m->ctl[i].len;
  209. b->hwversion = m->hwversion;
  210. b->log_mask = SDE_DBG_MASK_CTL;
  211. return &m->ctl[i];
  212. }
  213. }
  214. return ERR_PTR(-ENOMEM);
  215. }
  216. static int _mixer_stages(const struct sde_lm_cfg *mixer, int count,
  217. enum sde_lm lm)
  218. {
  219. int i;
  220. int stages = -EINVAL;
  221. for (i = 0; i < count; i++) {
  222. if (lm == mixer[i].id) {
  223. stages = mixer[i].sblk->maxblendstages;
  224. break;
  225. }
  226. }
  227. return stages;
  228. }
  229. static inline bool _is_dspp_flush_pending(struct sde_hw_ctl *ctx)
  230. {
  231. int i;
  232. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  233. if (ctx->flush.pending_dspp_flush_masks[i])
  234. return true;
  235. }
  236. return false;
  237. }
  238. static inline int sde_hw_ctl_trigger_start(struct sde_hw_ctl *ctx)
  239. {
  240. if (!ctx)
  241. return -EINVAL;
  242. SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1);
  243. return 0;
  244. }
  245. static inline int sde_hw_ctl_get_start_state(struct sde_hw_ctl *ctx)
  246. {
  247. if (!ctx)
  248. return -EINVAL;
  249. return SDE_REG_READ(&ctx->hw, CTL_START);
  250. }
  251. static inline int sde_hw_ctl_trigger_pending(struct sde_hw_ctl *ctx)
  252. {
  253. if (!ctx)
  254. return -EINVAL;
  255. SDE_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
  256. return 0;
  257. }
  258. static inline int sde_hw_ctl_clear_pending_flush(struct sde_hw_ctl *ctx)
  259. {
  260. if (!ctx)
  261. return -EINVAL;
  262. memset(&ctx->flush, 0, sizeof(ctx->flush));
  263. return 0;
  264. }
  265. static inline int sde_hw_ctl_update_pending_flush(struct sde_hw_ctl *ctx,
  266. struct sde_ctl_flush_cfg *cfg)
  267. {
  268. if (!ctx || !cfg)
  269. return -EINVAL;
  270. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  271. return 0;
  272. }
  273. static int sde_hw_ctl_get_pending_flush(struct sde_hw_ctl *ctx,
  274. struct sde_ctl_flush_cfg *cfg)
  275. {
  276. if (!ctx || !cfg)
  277. return -EINVAL;
  278. memcpy(cfg, &ctx->flush, sizeof(*cfg));
  279. return 0;
  280. }
  281. static inline int sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx)
  282. {
  283. if (!ctx)
  284. return -EINVAL;
  285. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  286. return 0;
  287. }
  288. static inline u32 sde_hw_ctl_get_flush_register(struct sde_hw_ctl *ctx)
  289. {
  290. struct sde_hw_blk_reg_map *c;
  291. u32 rot_op_mode;
  292. if (!ctx)
  293. return 0;
  294. c = &ctx->hw;
  295. rot_op_mode = SDE_REG_READ(c, CTL_ROT_TOP) & 0x3;
  296. /* rotate flush bit is undefined if offline mode, so ignore it */
  297. if (rot_op_mode == SDE_CTL_ROT_OP_MODE_OFFLINE)
  298. return SDE_REG_READ(c, CTL_FLUSH) & ~CTL_FLUSH_MASK_ROT;
  299. return SDE_REG_READ(c, CTL_FLUSH);
  300. }
  301. static inline void sde_hw_ctl_uidle_enable(struct sde_hw_ctl *ctx, bool enable)
  302. {
  303. u32 val;
  304. if (!ctx)
  305. return;
  306. val = SDE_REG_READ(&ctx->hw, CTL_UIDLE_ACTIVE);
  307. val = (val & ~BIT(0)) | (enable ? BIT(0) : 0);
  308. SDE_REG_WRITE(&ctx->hw, CTL_UIDLE_ACTIVE, val);
  309. }
  310. static inline int sde_hw_ctl_update_bitmask_sspp(struct sde_hw_ctl *ctx,
  311. enum sde_sspp sspp,
  312. bool enable)
  313. {
  314. if (!ctx)
  315. return -EINVAL;
  316. if (!(sspp > SSPP_NONE) || !(sspp < SSPP_MAX)) {
  317. SDE_ERROR("Unsupported pipe %d\n", sspp);
  318. return -EINVAL;
  319. }
  320. UPDATE_MASK(ctx->flush.pending_flush_mask, sspp_tbl[sspp], enable);
  321. return 0;
  322. }
  323. static inline int sde_hw_ctl_update_bitmask_mixer(struct sde_hw_ctl *ctx,
  324. enum sde_lm lm,
  325. bool enable)
  326. {
  327. if (!ctx)
  328. return -EINVAL;
  329. if (!(lm > SDE_NONE) || !(lm < LM_MAX)) {
  330. SDE_ERROR("Unsupported mixer %d\n", lm);
  331. return -EINVAL;
  332. }
  333. UPDATE_MASK(ctx->flush.pending_flush_mask, mixer_tbl[lm], enable);
  334. ctx->flush.pending_flush_mask |= CTL_FLUSH_MASK_CTL;
  335. return 0;
  336. }
  337. static inline int sde_hw_ctl_update_bitmask_dspp(struct sde_hw_ctl *ctx,
  338. enum sde_dspp dspp,
  339. bool enable)
  340. {
  341. if (!ctx)
  342. return -EINVAL;
  343. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  344. SDE_ERROR("Unsupported dspp %d\n", dspp);
  345. return -EINVAL;
  346. }
  347. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_tbl[dspp], enable);
  348. return 0;
  349. }
  350. static inline int sde_hw_ctl_update_bitmask_dspp_pavlut(struct sde_hw_ctl *ctx,
  351. enum sde_dspp dspp, bool enable)
  352. {
  353. if (!ctx)
  354. return -EINVAL;
  355. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  356. SDE_ERROR("Unsupported dspp %d\n", dspp);
  357. return -EINVAL;
  358. }
  359. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_pav_tbl[dspp], enable);
  360. return 0;
  361. }
  362. static inline int sde_hw_ctl_update_bitmask_cdm(struct sde_hw_ctl *ctx,
  363. enum sde_cdm cdm,
  364. bool enable)
  365. {
  366. if (!ctx)
  367. return -EINVAL;
  368. if (!(cdm > SDE_NONE) || !(cdm < CDM_MAX) || (cdm == CDM_1)) {
  369. SDE_ERROR("Unsupported cdm %d\n", cdm);
  370. return -EINVAL;
  371. }
  372. UPDATE_MASK(ctx->flush.pending_flush_mask, cdm_tbl[cdm], enable);
  373. return 0;
  374. }
  375. static inline int sde_hw_ctl_update_bitmask_wb(struct sde_hw_ctl *ctx,
  376. enum sde_wb wb, bool enable)
  377. {
  378. if (!ctx)
  379. return -EINVAL;
  380. if (!(wb > SDE_NONE) || !(wb < WB_MAX) ||
  381. (wb == WB_0) || (wb == WB_1)) {
  382. SDE_ERROR("Unsupported wb %d\n", wb);
  383. return -EINVAL;
  384. }
  385. UPDATE_MASK(ctx->flush.pending_flush_mask, wb_tbl[wb], enable);
  386. return 0;
  387. }
  388. static inline int sde_hw_ctl_update_bitmask_intf(struct sde_hw_ctl *ctx,
  389. enum sde_intf intf, bool enable)
  390. {
  391. if (!ctx)
  392. return -EINVAL;
  393. if (!(intf > SDE_NONE) || !(intf < INTF_MAX) || (intf > INTF_4)) {
  394. SDE_ERROR("Unsupported intf %d\n", intf);
  395. return -EINVAL;
  396. }
  397. UPDATE_MASK(ctx->flush.pending_flush_mask, intf_tbl[intf], enable);
  398. return 0;
  399. }
  400. static inline int sde_hw_ctl_update_bitmask_wb_v1(struct sde_hw_ctl *ctx,
  401. enum sde_wb wb, bool enable)
  402. {
  403. if (!ctx)
  404. return -EINVAL;
  405. if (wb != WB_2) {
  406. SDE_ERROR("Unsupported wb %d\n", wb);
  407. return -EINVAL;
  408. }
  409. UPDATE_MASK(ctx->flush.pending_wb_flush_mask, wb_flush_tbl[wb], enable);
  410. if (ctx->flush.pending_wb_flush_mask)
  411. UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
  412. else
  413. UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 0);
  414. return 0;
  415. }
  416. static inline int sde_hw_ctl_update_bitmask_intf_v1(struct sde_hw_ctl *ctx,
  417. enum sde_intf intf, bool enable)
  418. {
  419. if (!ctx)
  420. return -EINVAL;
  421. if (!(intf > SDE_NONE) || !(intf < INTF_MAX)) {
  422. SDE_ERROR("Unsupported intf %d\n", intf);
  423. return -EINVAL;
  424. }
  425. UPDATE_MASK(ctx->flush.pending_intf_flush_mask, intf_flush_tbl[intf],
  426. enable);
  427. if (ctx->flush.pending_intf_flush_mask)
  428. UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
  429. else
  430. UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 0);
  431. return 0;
  432. }
  433. static inline int sde_hw_ctl_update_bitmask_periph_v1(struct sde_hw_ctl *ctx,
  434. enum sde_intf intf, bool enable)
  435. {
  436. if (!ctx)
  437. return -EINVAL;
  438. if (!(intf > SDE_NONE) || !(intf < INTF_MAX)) {
  439. SDE_ERROR("Unsupported intf %d\n", intf);
  440. return -EINVAL;
  441. }
  442. UPDATE_MASK(ctx->flush.pending_periph_flush_mask, intf_flush_tbl[intf],
  443. enable);
  444. if (ctx->flush.pending_periph_flush_mask)
  445. UPDATE_MASK(ctx->flush.pending_flush_mask, PERIPH_IDX, 1);
  446. else
  447. UPDATE_MASK(ctx->flush.pending_flush_mask, PERIPH_IDX, 0);
  448. return 0;
  449. }
  450. static inline int sde_hw_ctl_update_bitmask_dsc_v1(struct sde_hw_ctl *ctx,
  451. enum sde_dsc dsc, bool enable)
  452. {
  453. if (!ctx)
  454. return -EINVAL;
  455. if (!(dsc > SDE_NONE) || !(dsc < DSC_MAX)) {
  456. SDE_ERROR("Unsupported dsc %d\n", dsc);
  457. return -EINVAL;
  458. }
  459. UPDATE_MASK(ctx->flush.pending_dsc_flush_mask, dsc_flush_tbl[dsc],
  460. enable);
  461. if (ctx->flush.pending_dsc_flush_mask)
  462. UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 1);
  463. else
  464. UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 0);
  465. return 0;
  466. }
  467. static inline int sde_hw_ctl_update_bitmask_vdc(struct sde_hw_ctl *ctx,
  468. enum sde_vdc vdc, bool enable)
  469. {
  470. if (!ctx)
  471. return -EINVAL;
  472. if (!(vdc > SDE_NONE) || !(vdc < VDC_MAX)) {
  473. SDE_ERROR("Unsupported vdc %d\n", vdc);
  474. return -EINVAL;
  475. }
  476. UPDATE_MASK(ctx->flush.pending_dsc_flush_mask, vdc_flush_tbl[vdc],
  477. enable);
  478. if (ctx->flush.pending_dsc_flush_mask)
  479. UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 1);
  480. else
  481. UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 0);
  482. return 0;
  483. }
  484. static inline int sde_hw_ctl_update_bitmask_merge3d_v1(struct sde_hw_ctl *ctx,
  485. enum sde_merge_3d merge_3d, bool enable)
  486. {
  487. if (!ctx)
  488. return -EINVAL;
  489. if (!(merge_3d > SDE_NONE) || !(merge_3d < MERGE_3D_MAX)) {
  490. SDE_ERROR("Unsupported merge_3d %d\n", merge_3d);
  491. return -EINVAL;
  492. }
  493. UPDATE_MASK(ctx->flush.pending_merge_3d_flush_mask,
  494. merge_3d_tbl[merge_3d], enable);
  495. if (ctx->flush.pending_merge_3d_flush_mask)
  496. UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
  497. else
  498. UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 0);
  499. return 0;
  500. }
  501. static inline int sde_hw_ctl_update_bitmask_cdm_v1(struct sde_hw_ctl *ctx,
  502. enum sde_cdm cdm, bool enable)
  503. {
  504. if (!ctx)
  505. return -EINVAL;
  506. if (cdm != CDM_0) {
  507. SDE_ERROR("Unsupported cdm %d\n", cdm);
  508. return -EINVAL;
  509. }
  510. UPDATE_MASK(ctx->flush.pending_cdm_flush_mask, cdm_flush_tbl[cdm],
  511. enable);
  512. if (ctx->flush.pending_cdm_flush_mask)
  513. UPDATE_MASK(ctx->flush.pending_flush_mask, CDM_IDX, 1);
  514. else
  515. UPDATE_MASK(ctx->flush.pending_flush_mask, CDM_IDX, 0);
  516. return 0;
  517. }
  518. static inline int sde_hw_ctl_update_bitmask_cwb_v1(struct sde_hw_ctl *ctx,
  519. enum sde_cwb cwb, bool enable)
  520. {
  521. if (!ctx)
  522. return -EINVAL;
  523. if ((cwb < CWB_1) || (cwb >= CWB_MAX)) {
  524. SDE_ERROR("Unsupported cwb %d\n", cwb);
  525. return -EINVAL;
  526. }
  527. UPDATE_MASK(ctx->flush.pending_cwb_flush_mask, cwb_flush_tbl[cwb],
  528. enable);
  529. if (ctx->flush.pending_cwb_flush_mask)
  530. UPDATE_MASK(ctx->flush.pending_flush_mask, CWB_IDX, 1);
  531. else
  532. UPDATE_MASK(ctx->flush.pending_flush_mask, CWB_IDX, 0);
  533. return 0;
  534. }
  535. static inline int sde_hw_ctl_update_pending_flush_v1(
  536. struct sde_hw_ctl *ctx,
  537. struct sde_ctl_flush_cfg *cfg)
  538. {
  539. int i;
  540. if (!ctx || !cfg)
  541. return -EINVAL;
  542. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  543. ctx->flush.pending_intf_flush_mask |= cfg->pending_intf_flush_mask;
  544. ctx->flush.pending_cdm_flush_mask |= cfg->pending_cdm_flush_mask;
  545. ctx->flush.pending_wb_flush_mask |= cfg->pending_wb_flush_mask;
  546. ctx->flush.pending_dsc_flush_mask |= cfg->pending_dsc_flush_mask;
  547. ctx->flush.pending_merge_3d_flush_mask |=
  548. cfg->pending_merge_3d_flush_mask;
  549. ctx->flush.pending_cwb_flush_mask |= cfg->pending_cwb_flush_mask;
  550. ctx->flush.pending_periph_flush_mask |= cfg->pending_periph_flush_mask;
  551. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++)
  552. ctx->flush.pending_dspp_flush_masks[i] |=
  553. cfg->pending_dspp_flush_masks[i];
  554. return 0;
  555. }
  556. static inline int sde_hw_ctl_update_bitmask_dspp_subblk(struct sde_hw_ctl *ctx,
  557. enum sde_dspp dspp, u32 sub_blk, bool enable)
  558. {
  559. if (!ctx || dspp < DSPP_0 || dspp >= DSPP_MAX ||
  560. sub_blk < SDE_DSPP_IGC || sub_blk >= SDE_DSPP_MAX) {
  561. SDE_ERROR("invalid args - ctx %s, dspp %d sub_block %d\n",
  562. ctx ? "valid" : "invalid", dspp, sub_blk);
  563. return -EINVAL;
  564. }
  565. UPDATE_MASK(ctx->flush.pending_dspp_flush_masks[dspp - DSPP_0],
  566. dspp_sub_blk_flush_tbl[sub_blk], enable);
  567. if (_is_dspp_flush_pending(ctx))
  568. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 1);
  569. else
  570. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 0);
  571. return 0;
  572. }
  573. static inline void _sde_hw_ctl_write_dspp_flushes(struct sde_hw_ctl *ctx) {
  574. int i;
  575. bool has_dspp_flushes = ctx->caps->features &
  576. BIT(SDE_CTL_UNIFIED_DSPP_FLUSH);
  577. if (!has_dspp_flushes)
  578. return;
  579. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  580. u32 pending = ctx->flush.pending_dspp_flush_masks[i];
  581. if (pending)
  582. SDE_REG_WRITE(&ctx->hw, CTL_DSPP_0_FLUSH + (i * 4),
  583. pending);
  584. }
  585. }
  586. static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
  587. {
  588. if (!ctx)
  589. return -EINVAL;
  590. if (ctx->flush.pending_flush_mask & BIT(WB_IDX))
  591. SDE_REG_WRITE(&ctx->hw, CTL_WB_FLUSH,
  592. ctx->flush.pending_wb_flush_mask);
  593. if (ctx->flush.pending_flush_mask & BIT(DSC_IDX))
  594. SDE_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,
  595. ctx->flush.pending_dsc_flush_mask);
  596. if (ctx->flush.pending_flush_mask & BIT(MERGE_3D_IDX))
  597. SDE_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
  598. ctx->flush.pending_merge_3d_flush_mask);
  599. if (ctx->flush.pending_flush_mask & BIT(CDM_IDX))
  600. SDE_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH,
  601. ctx->flush.pending_cdm_flush_mask);
  602. if (ctx->flush.pending_flush_mask & BIT(CWB_IDX))
  603. SDE_REG_WRITE(&ctx->hw, CTL_CWB_FLUSH,
  604. ctx->flush.pending_cwb_flush_mask);
  605. if (ctx->flush.pending_flush_mask & BIT(INTF_IDX))
  606. SDE_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
  607. ctx->flush.pending_intf_flush_mask);
  608. if (ctx->flush.pending_flush_mask & BIT(PERIPH_IDX))
  609. SDE_REG_WRITE(&ctx->hw, CTL_PERIPH_FLUSH,
  610. ctx->flush.pending_periph_flush_mask);
  611. if (ctx->flush.pending_flush_mask & BIT(DSPP_IDX))
  612. _sde_hw_ctl_write_dspp_flushes(ctx);
  613. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  614. return 0;
  615. }
  616. static inline u32 sde_hw_ctl_get_intf_v1(struct sde_hw_ctl *ctx)
  617. {
  618. struct sde_hw_blk_reg_map *c;
  619. u32 intf_active;
  620. if (!ctx) {
  621. pr_err("Invalid input argument\n");
  622. return 0;
  623. }
  624. c = &ctx->hw;
  625. intf_active = SDE_REG_READ(c, CTL_INTF_ACTIVE);
  626. return intf_active;
  627. }
  628. static inline u32 sde_hw_ctl_get_intf(struct sde_hw_ctl *ctx)
  629. {
  630. struct sde_hw_blk_reg_map *c;
  631. u32 ctl_top;
  632. u32 intf_active = 0;
  633. if (!ctx) {
  634. pr_err("Invalid input argument\n");
  635. return 0;
  636. }
  637. c = &ctx->hw;
  638. ctl_top = SDE_REG_READ(c, CTL_TOP);
  639. intf_active = (ctl_top > 0) ?
  640. BIT(ctl_top - 1) : 0;
  641. return intf_active;
  642. }
  643. static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us)
  644. {
  645. struct sde_hw_blk_reg_map *c;
  646. ktime_t timeout;
  647. u32 status;
  648. if (!ctx)
  649. return 0;
  650. c = &ctx->hw;
  651. timeout = ktime_add_us(ktime_get(), timeout_us);
  652. /*
  653. * it takes around 30us to have mdp finish resetting its ctl path
  654. * poll every 50us so that reset should be completed at 1st poll
  655. */
  656. do {
  657. status = SDE_REG_READ(c, CTL_SW_RESET);
  658. status &= 0x1;
  659. if (status)
  660. usleep_range(20, 50);
  661. } while (status && ktime_compare_safe(ktime_get(), timeout) < 0);
  662. return status;
  663. }
  664. static u32 sde_hw_ctl_get_reset_status(struct sde_hw_ctl *ctx)
  665. {
  666. if (!ctx)
  667. return 0;
  668. return (u32)SDE_REG_READ(&ctx->hw, CTL_SW_RESET);
  669. }
  670. static u32 sde_hw_ctl_get_scheduler_status(struct sde_hw_ctl *ctx)
  671. {
  672. if (!ctx)
  673. return INVALID_CTL_STATUS;
  674. return (u32)SDE_REG_READ(&ctx->hw, CTL_STATUS);
  675. }
  676. static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx)
  677. {
  678. struct sde_hw_blk_reg_map *c;
  679. if (!ctx)
  680. return 0;
  681. c = &ctx->hw;
  682. pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx);
  683. SDE_REG_WRITE(c, CTL_SW_RESET, 0x1);
  684. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US))
  685. return -EINVAL;
  686. return 0;
  687. }
  688. static void sde_hw_ctl_hard_reset(struct sde_hw_ctl *ctx, bool enable)
  689. {
  690. struct sde_hw_blk_reg_map *c;
  691. if (!ctx)
  692. return;
  693. c = &ctx->hw;
  694. pr_debug("hw ctl hard reset for ctl:%d, %d\n",
  695. ctx->idx - CTL_0, enable);
  696. SDE_REG_WRITE(c, CTL_SW_RESET_OVERRIDE, enable);
  697. }
  698. static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx)
  699. {
  700. struct sde_hw_blk_reg_map *c;
  701. u32 status;
  702. if (!ctx)
  703. return 0;
  704. c = &ctx->hw;
  705. status = SDE_REG_READ(c, CTL_SW_RESET);
  706. status &= 0x01;
  707. if (!status)
  708. return 0;
  709. pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx);
  710. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_WAIT_RESET_TIMEOUT_US)) {
  711. pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx);
  712. return -EINVAL;
  713. }
  714. return 0;
  715. }
  716. static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx)
  717. {
  718. struct sde_hw_blk_reg_map *c;
  719. int i;
  720. if (!ctx)
  721. return;
  722. c = &ctx->hw;
  723. for (i = 0; i < ctx->mixer_count; i++) {
  724. int mixer_id = ctx->mixer_hw_caps[i].id;
  725. SDE_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
  726. SDE_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
  727. SDE_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
  728. SDE_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
  729. }
  730. SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
  731. }
  732. static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
  733. enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg)
  734. {
  735. struct sde_hw_blk_reg_map *c;
  736. u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
  737. u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
  738. u32 active_fetch_pipes = 0;
  739. int i, j;
  740. u8 stages;
  741. int pipes_per_stage;
  742. if (!ctx)
  743. return;
  744. c = &ctx->hw;
  745. stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
  746. if ((int)stages < 0)
  747. return;
  748. if (test_bit(SDE_MIXER_SOURCESPLIT,
  749. &ctx->mixer_hw_caps->features))
  750. pipes_per_stage = PIPES_PER_STAGE;
  751. else
  752. pipes_per_stage = 1;
  753. mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */
  754. if (!stage_cfg)
  755. goto exit;
  756. for (i = 0; i <= stages; i++) {
  757. /* overflow to ext register if 'i + 1 > 7' */
  758. mix = (i + 1) & 0x7;
  759. ext = i >= 7;
  760. for (j = 0 ; j < pipes_per_stage; j++) {
  761. enum sde_sspp pipe = stage_cfg->stage[i][j];
  762. enum sde_sspp_multirect_index rect_index =
  763. stage_cfg->multirect_index[i][j];
  764. switch (pipe) {
  765. case SSPP_VIG0:
  766. if (rect_index == SDE_SSPP_RECT_1) {
  767. mixercfg_ext3 |= ((i + 1) & 0xF) << 0;
  768. } else {
  769. mixercfg |= mix << 0;
  770. mixercfg_ext |= ext << 0;
  771. }
  772. break;
  773. case SSPP_VIG1:
  774. if (rect_index == SDE_SSPP_RECT_1) {
  775. mixercfg_ext3 |= ((i + 1) & 0xF) << 4;
  776. } else {
  777. mixercfg |= mix << 3;
  778. mixercfg_ext |= ext << 2;
  779. }
  780. break;
  781. case SSPP_VIG2:
  782. if (rect_index == SDE_SSPP_RECT_1) {
  783. mixercfg_ext3 |= ((i + 1) & 0xF) << 8;
  784. } else {
  785. mixercfg |= mix << 6;
  786. mixercfg_ext |= ext << 4;
  787. }
  788. break;
  789. case SSPP_VIG3:
  790. if (rect_index == SDE_SSPP_RECT_1) {
  791. mixercfg_ext3 |= ((i + 1) & 0xF) << 12;
  792. } else {
  793. mixercfg |= mix << 26;
  794. mixercfg_ext |= ext << 6;
  795. }
  796. break;
  797. case SSPP_RGB0:
  798. mixercfg |= mix << 9;
  799. mixercfg_ext |= ext << 8;
  800. break;
  801. case SSPP_RGB1:
  802. mixercfg |= mix << 12;
  803. mixercfg_ext |= ext << 10;
  804. break;
  805. case SSPP_RGB2:
  806. mixercfg |= mix << 15;
  807. mixercfg_ext |= ext << 12;
  808. break;
  809. case SSPP_RGB3:
  810. mixercfg |= mix << 29;
  811. mixercfg_ext |= ext << 14;
  812. break;
  813. case SSPP_DMA0:
  814. if (rect_index == SDE_SSPP_RECT_1) {
  815. mixercfg_ext2 |= ((i + 1) & 0xF) << 8;
  816. } else {
  817. mixercfg |= mix << 18;
  818. mixercfg_ext |= ext << 16;
  819. }
  820. break;
  821. case SSPP_DMA1:
  822. if (rect_index == SDE_SSPP_RECT_1) {
  823. mixercfg_ext2 |= ((i + 1) & 0xF) << 12;
  824. } else {
  825. mixercfg |= mix << 21;
  826. mixercfg_ext |= ext << 18;
  827. }
  828. break;
  829. case SSPP_DMA2:
  830. if (rect_index == SDE_SSPP_RECT_1) {
  831. mixercfg_ext2 |= ((i + 1) & 0xF) << 16;
  832. } else {
  833. mix |= (i + 1) & 0xF;
  834. mixercfg_ext2 |= mix << 0;
  835. }
  836. break;
  837. case SSPP_DMA3:
  838. if (rect_index == SDE_SSPP_RECT_1) {
  839. mixercfg_ext2 |= ((i + 1) & 0xF) << 20;
  840. } else {
  841. mix |= (i + 1) & 0xF;
  842. mixercfg_ext2 |= mix << 4;
  843. }
  844. break;
  845. case SSPP_CURSOR0:
  846. mixercfg_ext |= ((i + 1) & 0xF) << 20;
  847. break;
  848. case SSPP_CURSOR1:
  849. mixercfg_ext |= ((i + 1) & 0xF) << 26;
  850. break;
  851. default:
  852. break;
  853. }
  854. if (fetch_tbl[pipe] != CTL_INVALID_BIT)
  855. active_fetch_pipes |= BIT(fetch_tbl[pipe]);
  856. }
  857. }
  858. exit:
  859. SDE_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
  860. SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
  861. SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
  862. SDE_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
  863. SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, active_fetch_pipes);
  864. }
  865. static u32 sde_hw_ctl_get_staged_sspp(struct sde_hw_ctl *ctx, enum sde_lm lm,
  866. struct sde_sspp_index_info *info, u32 info_max_cnt)
  867. {
  868. int i, j;
  869. u32 count = 0;
  870. u32 mask = 0;
  871. bool staged;
  872. u32 mixercfg[CTL_NUM_EXT];
  873. struct sde_hw_blk_reg_map *c;
  874. const struct ctl_sspp_stage_reg_map *sspp_cfg;
  875. if (!ctx || (lm >= LM_MAX) || !info)
  876. return count;
  877. c = &ctx->hw;
  878. mixercfg[0] = SDE_REG_READ(c, CTL_LAYER(lm));
  879. mixercfg[1] = SDE_REG_READ(c, CTL_LAYER_EXT(lm));
  880. mixercfg[2] = SDE_REG_READ(c, CTL_LAYER_EXT2(lm));
  881. mixercfg[3] = SDE_REG_READ(c, CTL_LAYER_EXT3(lm));
  882. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  883. for (j = 0; j < CTL_SSPP_MAX_RECTS; j++) {
  884. if (count >= info_max_cnt)
  885. goto end;
  886. sspp_cfg = &sspp_reg_cfg_tbl[i][j];
  887. if (!sspp_cfg->bits || sspp_cfg->ext >= CTL_NUM_EXT)
  888. continue;
  889. mask = ((0x1 << sspp_cfg->bits) - 1) << sspp_cfg->start;
  890. staged = mixercfg[sspp_cfg->ext] & mask;
  891. if (!staged)
  892. staged = mixercfg[1] & sspp_cfg->sec_bit_mask;
  893. if (staged) {
  894. info[count].sspp = i;
  895. info[count].is_virtual = j;
  896. count++;
  897. }
  898. }
  899. }
  900. end:
  901. return count;
  902. }
  903. static int sde_hw_ctl_intf_cfg_v1(struct sde_hw_ctl *ctx,
  904. struct sde_hw_intf_cfg_v1 *cfg)
  905. {
  906. struct sde_hw_blk_reg_map *c;
  907. u32 intf_active = 0;
  908. u32 wb_active = 0;
  909. u32 merge_3d_active = 0;
  910. u32 cwb_active = 0;
  911. u32 mode_sel = 0xf0000000;
  912. u32 cdm_active = 0;
  913. u32 intf_master = 0;
  914. u32 i;
  915. if (!ctx)
  916. return -EINVAL;
  917. c = &ctx->hw;
  918. for (i = 0; i < cfg->intf_count; i++) {
  919. if (cfg->intf[i])
  920. intf_active |= BIT(cfg->intf[i] - INTF_0);
  921. }
  922. if (cfg->intf_count > 1)
  923. intf_master = BIT(cfg->intf_master - INTF_0);
  924. for (i = 0; i < cfg->wb_count; i++) {
  925. if (cfg->wb[i])
  926. wb_active |= BIT(cfg->wb[i] - WB_0);
  927. }
  928. for (i = 0; i < cfg->merge_3d_count; i++) {
  929. if (cfg->merge_3d[i])
  930. merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
  931. }
  932. for (i = 0; i < cfg->cwb_count; i++) {
  933. if (cfg->cwb[i])
  934. cwb_active |= BIT(cfg->cwb[i] - CWB_0);
  935. }
  936. for (i = 0; i < cfg->cdm_count; i++) {
  937. if (cfg->cdm[i])
  938. cdm_active |= BIT(cfg->cdm[i] - CDM_0);
  939. }
  940. if (cfg->intf_mode_sel == SDE_CTL_MODE_SEL_CMD)
  941. mode_sel |= BIT(17);
  942. SDE_REG_WRITE(c, CTL_TOP, mode_sel);
  943. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  944. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  945. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  946. SDE_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);
  947. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  948. SDE_REG_WRITE(c, CTL_INTF_MASTER, intf_master);
  949. return 0;
  950. }
  951. static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
  952. struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx)
  953. {
  954. struct sde_hw_blk_reg_map *c;
  955. u32 intf_active = 0, wb_active = 0, merge_3d_active = 0;
  956. u32 intf_flush = 0, wb_flush = 0;
  957. u32 i;
  958. if (!ctx || !cfg) {
  959. SDE_ERROR("invalid hw_ctl or hw_intf blk\n");
  960. return -EINVAL;
  961. }
  962. c = &ctx->hw;
  963. for (i = 0; i < cfg->intf_count; i++) {
  964. if (cfg->intf[i]) {
  965. intf_active &= ~BIT(cfg->intf[i] - INTF_0);
  966. intf_flush |= BIT(cfg->intf[i] - INTF_0);
  967. }
  968. }
  969. for (i = 0; i < cfg->wb_count; i++) {
  970. if (cfg->wb[i]) {
  971. wb_active &= ~BIT(cfg->wb[i] - WB_0);
  972. wb_flush |= BIT(cfg->wb[i] - WB_0);
  973. }
  974. }
  975. if (merge_3d_idx) {
  976. /* disable and flush merge3d_blk */
  977. ctx->flush.pending_merge_3d_flush_mask =
  978. BIT(merge_3d_idx - MERGE_3D_0);
  979. merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
  980. UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
  981. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  982. }
  983. sde_hw_ctl_clear_all_blendstages(ctx);
  984. if (cfg->intf_count) {
  985. ctx->flush.pending_intf_flush_mask = intf_flush;
  986. UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
  987. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  988. }
  989. if (cfg->wb_count) {
  990. ctx->flush.pending_wb_flush_mask = wb_flush;
  991. UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
  992. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  993. }
  994. return 0;
  995. }
  996. static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
  997. struct sde_hw_intf_cfg_v1 *cfg, bool enable)
  998. {
  999. int i;
  1000. u32 cwb_active = 0;
  1001. u32 merge_3d_active = 0;
  1002. u32 wb_active = 0;
  1003. u32 dsc_active = 0;
  1004. u32 vdc_active = 0;
  1005. struct sde_hw_blk_reg_map *c;
  1006. if (!ctx)
  1007. return -EINVAL;
  1008. c = &ctx->hw;
  1009. if (cfg->cwb_count) {
  1010. cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
  1011. for (i = 0; i < cfg->cwb_count; i++) {
  1012. if (cfg->cwb[i])
  1013. UPDATE_ACTIVE(cwb_active,
  1014. (cfg->cwb[i] - CWB_0),
  1015. enable);
  1016. }
  1017. wb_active = enable ? BIT(2) : 0;
  1018. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  1019. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  1020. }
  1021. if (cfg->merge_3d_count) {
  1022. merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
  1023. for (i = 0; i < cfg->merge_3d_count; i++) {
  1024. if (cfg->merge_3d[i])
  1025. UPDATE_ACTIVE(merge_3d_active,
  1026. (cfg->merge_3d[i] - MERGE_3D_0),
  1027. enable);
  1028. }
  1029. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  1030. }
  1031. if (cfg->dsc_count) {
  1032. dsc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  1033. for (i = 0; i < cfg->dsc_count; i++) {
  1034. if (cfg->dsc[i])
  1035. UPDATE_ACTIVE(dsc_active,
  1036. (cfg->dsc[i] - DSC_0), enable);
  1037. }
  1038. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
  1039. }
  1040. if (cfg->vdc_count) {
  1041. vdc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  1042. for (i = 0; i < cfg->vdc_count; i++) {
  1043. if (cfg->vdc[i])
  1044. UPDATE_ACTIVE(vdc_active,
  1045. VDC_IDX(cfg->vdc[i] - VDC_0), enable);
  1046. }
  1047. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, vdc_active);
  1048. }
  1049. return 0;
  1050. }
  1051. static int sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx,
  1052. struct sde_hw_intf_cfg *cfg)
  1053. {
  1054. struct sde_hw_blk_reg_map *c;
  1055. u32 intf_cfg = 0;
  1056. if (!ctx)
  1057. return -EINVAL;
  1058. c = &ctx->hw;
  1059. intf_cfg |= (cfg->intf & 0xF) << 4;
  1060. if (cfg->wb)
  1061. intf_cfg |= (cfg->wb & 0x3) + 2;
  1062. if (cfg->mode_3d) {
  1063. intf_cfg |= BIT(19);
  1064. intf_cfg |= (cfg->mode_3d - 0x1) << 20;
  1065. }
  1066. switch (cfg->intf_mode_sel) {
  1067. case SDE_CTL_MODE_SEL_VID:
  1068. intf_cfg &= ~BIT(17);
  1069. intf_cfg &= ~(0x3 << 15);
  1070. break;
  1071. case SDE_CTL_MODE_SEL_CMD:
  1072. intf_cfg |= BIT(17);
  1073. intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
  1074. break;
  1075. default:
  1076. pr_err("unknown interface type %d\n", cfg->intf_mode_sel);
  1077. return -EINVAL;
  1078. }
  1079. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  1080. return 0;
  1081. }
  1082. static void sde_hw_ctl_update_wb_cfg(struct sde_hw_ctl *ctx,
  1083. struct sde_hw_intf_cfg *cfg, bool enable)
  1084. {
  1085. struct sde_hw_blk_reg_map *c = &ctx->hw;
  1086. u32 intf_cfg = 0;
  1087. if (!cfg->wb)
  1088. return;
  1089. intf_cfg = SDE_REG_READ(c, CTL_TOP);
  1090. if (enable)
  1091. intf_cfg |= (cfg->wb & 0x3) + 2;
  1092. else
  1093. intf_cfg &= ~((cfg->wb & 0x3) + 2);
  1094. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  1095. }
  1096. static inline u32 sde_hw_ctl_read_ctl_top(struct sde_hw_ctl *ctx)
  1097. {
  1098. struct sde_hw_blk_reg_map *c;
  1099. u32 ctl_top;
  1100. if (!ctx) {
  1101. pr_err("Invalid input argument\n");
  1102. return 0;
  1103. }
  1104. c = &ctx->hw;
  1105. ctl_top = SDE_REG_READ(c, CTL_TOP);
  1106. return ctl_top;
  1107. }
  1108. static inline u32 sde_hw_ctl_read_ctl_layers(struct sde_hw_ctl *ctx, int index)
  1109. {
  1110. struct sde_hw_blk_reg_map *c;
  1111. u32 ctl_top;
  1112. if (!ctx) {
  1113. pr_err("Invalid input argument\n");
  1114. return 0;
  1115. }
  1116. c = &ctx->hw;
  1117. ctl_top = SDE_REG_READ(c, CTL_LAYER(index));
  1118. pr_debug("Ctl_layer value = 0x%x\n", ctl_top);
  1119. return ctl_top;
  1120. }
  1121. static inline bool sde_hw_ctl_read_active_status(struct sde_hw_ctl *ctx,
  1122. enum sde_hw_blk_type blk, int index)
  1123. {
  1124. struct sde_hw_blk_reg_map *c;
  1125. if (!ctx) {
  1126. pr_err("Invalid input argument\n");
  1127. return 0;
  1128. }
  1129. c = &ctx->hw;
  1130. switch (blk) {
  1131. case SDE_HW_BLK_MERGE_3D:
  1132. return (SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE) &
  1133. BIT(index - MERGE_3D_0)) ? true : false;
  1134. case SDE_HW_BLK_DSC:
  1135. return (SDE_REG_READ(c, CTL_DSC_ACTIVE) &
  1136. BIT(index - DSC_0)) ? true : false;
  1137. case SDE_HW_BLK_WB:
  1138. return (SDE_REG_READ(c, CTL_WB_ACTIVE) &
  1139. BIT(index - WB_0)) ? true : false;
  1140. case SDE_HW_BLK_CDM:
  1141. return (SDE_REG_READ(c, CTL_CDM_ACTIVE) &
  1142. BIT(index - CDM_0)) ? true : false;
  1143. case SDE_HW_BLK_INTF:
  1144. return (SDE_REG_READ(c, CTL_INTF_ACTIVE) &
  1145. BIT(index - INTF_0)) ? true : false;
  1146. default:
  1147. pr_err("unsupported blk %d\n", blk);
  1148. return false;
  1149. };
  1150. return false;
  1151. }
  1152. static int sde_hw_reg_dma_flush(struct sde_hw_ctl *ctx, bool blocking)
  1153. {
  1154. struct sde_hw_reg_dma_ops *ops = sde_reg_dma_get_ops();
  1155. if (!ctx)
  1156. return -EINVAL;
  1157. if (ops && ops->last_command)
  1158. return ops->last_command(ctx, DMA_CTL_QUEUE0,
  1159. (blocking ? REG_DMA_WAIT4_COMP : REG_DMA_NOWAIT));
  1160. return 0;
  1161. }
  1162. static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
  1163. unsigned long cap)
  1164. {
  1165. if (cap & BIT(SDE_CTL_ACTIVE_CFG)) {
  1166. ops->update_pending_flush =
  1167. sde_hw_ctl_update_pending_flush_v1;
  1168. ops->trigger_flush = sde_hw_ctl_trigger_flush_v1;
  1169. ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
  1170. ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
  1171. ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm_v1;
  1172. ops->update_bitmask_wb = sde_hw_ctl_update_bitmask_wb_v1;
  1173. ops->update_bitmask_intf = sde_hw_ctl_update_bitmask_intf_v1;
  1174. ops->update_bitmask_dsc = sde_hw_ctl_update_bitmask_dsc_v1;
  1175. ops->update_bitmask_vdc = sde_hw_ctl_update_bitmask_vdc;
  1176. ops->update_bitmask_merge3d =
  1177. sde_hw_ctl_update_bitmask_merge3d_v1;
  1178. ops->update_bitmask_cwb = sde_hw_ctl_update_bitmask_cwb_v1;
  1179. ops->update_bitmask_periph =
  1180. sde_hw_ctl_update_bitmask_periph_v1;
  1181. ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;
  1182. ops->reset_post_disable = sde_hw_ctl_reset_post_disable;
  1183. ops->get_scheduler_status = sde_hw_ctl_get_scheduler_status;
  1184. ops->read_active_status = sde_hw_ctl_read_active_status;
  1185. } else {
  1186. ops->update_pending_flush = sde_hw_ctl_update_pending_flush;
  1187. ops->trigger_flush = sde_hw_ctl_trigger_flush;
  1188. ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
  1189. ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm;
  1190. ops->update_bitmask_wb = sde_hw_ctl_update_bitmask_wb;
  1191. ops->update_bitmask_intf = sde_hw_ctl_update_bitmask_intf;
  1192. ops->get_ctl_intf = sde_hw_ctl_get_intf;
  1193. }
  1194. ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;
  1195. ops->get_pending_flush = sde_hw_ctl_get_pending_flush;
  1196. ops->get_flush_register = sde_hw_ctl_get_flush_register;
  1197. ops->trigger_start = sde_hw_ctl_trigger_start;
  1198. ops->trigger_pending = sde_hw_ctl_trigger_pending;
  1199. ops->read_ctl_top = sde_hw_ctl_read_ctl_top;
  1200. ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers;
  1201. ops->update_wb_cfg = sde_hw_ctl_update_wb_cfg;
  1202. ops->reset = sde_hw_ctl_reset_control;
  1203. ops->get_reset = sde_hw_ctl_get_reset_status;
  1204. ops->hard_reset = sde_hw_ctl_hard_reset;
  1205. ops->wait_reset_status = sde_hw_ctl_wait_reset_status;
  1206. ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages;
  1207. ops->setup_blendstage = sde_hw_ctl_setup_blendstage;
  1208. ops->get_staged_sspp = sde_hw_ctl_get_staged_sspp;
  1209. ops->update_bitmask_sspp = sde_hw_ctl_update_bitmask_sspp;
  1210. ops->update_bitmask_mixer = sde_hw_ctl_update_bitmask_mixer;
  1211. ops->reg_dma_flush = sde_hw_reg_dma_flush;
  1212. ops->get_start_state = sde_hw_ctl_get_start_state;
  1213. if (cap & BIT(SDE_CTL_UNIFIED_DSPP_FLUSH)) {
  1214. ops->update_bitmask_dspp_subblk =
  1215. sde_hw_ctl_update_bitmask_dspp_subblk;
  1216. } else {
  1217. ops->update_bitmask_dspp = sde_hw_ctl_update_bitmask_dspp;
  1218. ops->update_bitmask_dspp_pavlut =
  1219. sde_hw_ctl_update_bitmask_dspp_pavlut;
  1220. }
  1221. if (cap & BIT(SDE_CTL_UIDLE))
  1222. ops->uidle_enable = sde_hw_ctl_uidle_enable;
  1223. };
  1224. static struct sde_hw_blk_ops sde_hw_ops = {
  1225. .start = NULL,
  1226. .stop = NULL,
  1227. };
  1228. struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
  1229. void __iomem *addr,
  1230. struct sde_mdss_cfg *m)
  1231. {
  1232. struct sde_hw_ctl *c;
  1233. struct sde_ctl_cfg *cfg;
  1234. int rc;
  1235. c = kzalloc(sizeof(*c), GFP_KERNEL);
  1236. if (!c)
  1237. return ERR_PTR(-ENOMEM);
  1238. cfg = _ctl_offset(idx, m, addr, &c->hw);
  1239. if (IS_ERR_OR_NULL(cfg)) {
  1240. kfree(c);
  1241. pr_err("failed to create sde_hw_ctl %d\n", idx);
  1242. return ERR_PTR(-EINVAL);
  1243. }
  1244. c->caps = cfg;
  1245. _setup_ctl_ops(&c->ops, c->caps->features);
  1246. c->idx = idx;
  1247. c->mixer_count = m->mixer_count;
  1248. c->mixer_hw_caps = m->mixer;
  1249. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_CTL, idx, &sde_hw_ops);
  1250. if (rc) {
  1251. SDE_ERROR("failed to init hw blk %d\n", rc);
  1252. goto blk_init_error;
  1253. }
  1254. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  1255. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  1256. return c;
  1257. blk_init_error:
  1258. kzfree(c);
  1259. return ERR_PTR(rc);
  1260. }
  1261. void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx)
  1262. {
  1263. if (ctx)
  1264. sde_hw_blk_destroy(&ctx->base);
  1265. kfree(ctx);
  1266. }