sde_encoder_phys_vid.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include "sde_encoder_phys.h"
  7. #include "sde_hw_interrupts.h"
  8. #include "sde_core_irq.h"
  9. #include "sde_formats.h"
  10. #include "dsi_display.h"
  11. #include "sde_trace.h"
  12. #define SDE_DEBUG_VIDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
  13. (e) && (e)->base.parent ? \
  14. (e)->base.parent->base.id : -1, \
  15. (e) && (e)->base.hw_intf ? \
  16. (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  17. #define SDE_ERROR_VIDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
  18. (e) && (e)->base.parent ? \
  19. (e)->base.parent->base.id : -1, \
  20. (e) && (e)->base.hw_intf ? \
  21. (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  22. #define to_sde_encoder_phys_vid(x) \
  23. container_of(x, struct sde_encoder_phys_vid, base)
  24. /* maximum number of consecutive kickoff errors */
  25. #define KICKOFF_MAX_ERRORS 2
  26. /* Poll time to do recovery during active region */
  27. #define POLL_TIME_USEC_FOR_LN_CNT 500
  28. #define MAX_POLL_CNT 10
  29. static bool sde_encoder_phys_vid_is_master(
  30. struct sde_encoder_phys *phys_enc)
  31. {
  32. bool ret = false;
  33. if (phys_enc->split_role != ENC_ROLE_SLAVE)
  34. ret = true;
  35. return ret;
  36. }
  37. static void drm_mode_to_intf_timing_params(
  38. const struct sde_encoder_phys_vid *vid_enc,
  39. const struct drm_display_mode *mode,
  40. struct intf_timing_params *timing)
  41. {
  42. const struct sde_encoder_phys *phys_enc = &vid_enc->base;
  43. memset(timing, 0, sizeof(*timing));
  44. if ((mode->htotal < mode->hsync_end)
  45. || (mode->hsync_start < mode->hdisplay)
  46. || (mode->vtotal < mode->vsync_end)
  47. || (mode->vsync_start < mode->vdisplay)
  48. || (mode->hsync_end < mode->hsync_start)
  49. || (mode->vsync_end < mode->vsync_start)) {
  50. SDE_ERROR(
  51. "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
  52. mode->hsync_start, mode->hsync_end,
  53. mode->htotal, mode->hdisplay);
  54. SDE_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
  55. mode->vsync_start, mode->vsync_end,
  56. mode->vtotal, mode->vdisplay);
  57. return;
  58. }
  59. /*
  60. * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
  61. * Active Region Front Porch Sync Back Porch
  62. * <-----------------><------------><-----><----------->
  63. * <- [hv]display --->
  64. * <--------- [hv]sync_start ------>
  65. * <----------------- [hv]sync_end ------->
  66. * <---------------------------- [hv]total ------------->
  67. */
  68. timing->width = mode->hdisplay; /* active width */
  69. if (phys_enc->hw_intf->cap->type != INTF_DP) {
  70. if ((vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC) ||
  71. (vid_enc->base.comp_type ==
  72. MSM_DISPLAY_COMPRESSION_VDC))
  73. timing->width = DIV_ROUND_UP(timing->width,
  74. vid_enc->base.comp_ratio);
  75. }
  76. timing->height = mode->vdisplay; /* active height */
  77. timing->xres = timing->width;
  78. timing->yres = timing->height;
  79. timing->h_back_porch = mode->htotal - mode->hsync_end;
  80. timing->h_front_porch = mode->hsync_start - mode->hdisplay;
  81. timing->v_back_porch = mode->vtotal - mode->vsync_end;
  82. timing->v_front_porch = mode->vsync_start - mode->vdisplay;
  83. timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
  84. timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
  85. timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
  86. timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
  87. timing->border_clr = 0;
  88. timing->underflow_clr = 0xff;
  89. timing->hsync_skew = mode->hskew;
  90. timing->v_front_porch_fixed = vid_enc->base.vfp_cached;
  91. if (vid_enc->base.comp_type != MSM_DISPLAY_COMPRESSION_NONE)
  92. timing->compression_en = true;
  93. /* DSI controller cannot handle active-low sync signals. */
  94. if (phys_enc->hw_intf->cap->type == INTF_DSI) {
  95. timing->hsync_polarity = 0;
  96. timing->vsync_polarity = 0;
  97. }
  98. /* for DP/EDP, Shift timings to align it to bottom right */
  99. if ((phys_enc->hw_intf->cap->type == INTF_DP) ||
  100. (phys_enc->hw_intf->cap->type == INTF_EDP)) {
  101. timing->h_back_porch += timing->h_front_porch;
  102. timing->h_front_porch = 0;
  103. timing->v_back_porch += timing->v_front_porch;
  104. timing->v_front_porch = 0;
  105. }
  106. timing->wide_bus_en = vid_enc->base.wide_bus_en;
  107. /*
  108. * for DP, divide the horizonal parameters by 2 when
  109. * widebus or compression is enabled, irrespective of
  110. * compression ratio
  111. */
  112. if (phys_enc->hw_intf->cap->type == INTF_DP &&
  113. (timing->wide_bus_en ||
  114. (vid_enc->base.comp_ratio > 1))) {
  115. timing->width = timing->width >> 1;
  116. timing->xres = timing->xres >> 1;
  117. timing->h_back_porch = timing->h_back_porch >> 1;
  118. timing->h_front_porch = timing->h_front_porch >> 1;
  119. timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
  120. if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  121. (vid_enc->base.comp_ratio > 1)) {
  122. timing->extra_dto_cycles =
  123. vid_enc->base.dsc_extra_pclk_cycle_cnt;
  124. timing->width += vid_enc->base.dsc_extra_disp_width;
  125. timing->h_back_porch +=
  126. vid_enc->base.dsc_extra_disp_width;
  127. }
  128. }
  129. /*
  130. * For edp only:
  131. * DISPLAY_V_START = (VBP * HCYCLE) + HBP
  132. * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
  133. */
  134. /*
  135. * if (vid_enc->hw->cap->type == INTF_EDP) {
  136. * display_v_start += mode->htotal - mode->hsync_start;
  137. * display_v_end -= mode->hsync_start - mode->hdisplay;
  138. * }
  139. */
  140. }
  141. static inline u32 get_horizontal_total(const struct intf_timing_params *timing)
  142. {
  143. u32 active = timing->xres;
  144. u32 inactive =
  145. timing->h_back_porch + timing->h_front_porch +
  146. timing->hsync_pulse_width;
  147. return active + inactive;
  148. }
  149. static inline u32 get_vertical_total(const struct intf_timing_params *timing,
  150. bool use_fixed_vfp)
  151. {
  152. u32 inactive;
  153. u32 active = timing->yres;
  154. u32 v_front_porch = use_fixed_vfp ?
  155. timing->v_front_porch_fixed : timing->v_front_porch;
  156. inactive = timing->v_back_porch + v_front_porch +
  157. timing->vsync_pulse_width;
  158. return active + inactive;
  159. }
  160. /*
  161. * programmable_fetch_get_num_lines:
  162. * Number of fetch lines in vertical front porch
  163. * @timing: Pointer to the intf timing information for the requested mode
  164. *
  165. * Returns the number of fetch lines in vertical front porch at which mdp
  166. * can start fetching the next frame.
  167. *
  168. * Number of needed prefetch lines is anything that cannot be absorbed in the
  169. * start of frame time (back porch + vsync pulse width).
  170. *
  171. * Some panels have very large VFP, however we only need a total number of
  172. * lines based on the chip worst case latencies.
  173. */
  174. static u32 programmable_fetch_get_num_lines(
  175. struct sde_encoder_phys_vid *vid_enc,
  176. const struct intf_timing_params *timing,
  177. bool use_fixed_vfp)
  178. {
  179. struct sde_encoder_phys *phys_enc = &vid_enc->base;
  180. u32 worst_case_needed_lines =
  181. phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
  182. u32 start_of_frame_lines =
  183. timing->v_back_porch + timing->vsync_pulse_width;
  184. u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
  185. u32 actual_vfp_lines = 0;
  186. u32 v_front_porch = use_fixed_vfp ?
  187. timing->v_front_porch_fixed : timing->v_front_porch;
  188. /* Fetch must be outside active lines, otherwise undefined. */
  189. if (start_of_frame_lines >= worst_case_needed_lines) {
  190. SDE_DEBUG_VIDENC(vid_enc,
  191. "prog fetch is not needed, large vbp+vsw\n");
  192. actual_vfp_lines = 0;
  193. } else if (v_front_porch < needed_vfp_lines) {
  194. /* Warn fetch needed, but not enough porch in panel config */
  195. pr_warn_once
  196. ("low vbp+vfp may lead to perf issues in some cases\n");
  197. SDE_DEBUG_VIDENC(vid_enc,
  198. "less vfp than fetch req, using entire vfp\n");
  199. actual_vfp_lines = v_front_porch;
  200. } else {
  201. SDE_DEBUG_VIDENC(vid_enc, "room in vfp for needed prefetch\n");
  202. actual_vfp_lines = needed_vfp_lines;
  203. }
  204. SDE_DEBUG_VIDENC(vid_enc,
  205. "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
  206. v_front_porch, timing->v_back_porch,
  207. timing->vsync_pulse_width);
  208. SDE_DEBUG_VIDENC(vid_enc,
  209. "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
  210. worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
  211. return actual_vfp_lines;
  212. }
  213. /*
  214. * programmable_fetch_config: Programs HW to prefetch lines by offsetting
  215. * the start of fetch into the vertical front porch for cases where the
  216. * vsync pulse width and vertical back porch time is insufficient
  217. *
  218. * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
  219. * HW layer requires VSYNC counter of first pixel of tgt VFP line.
  220. *
  221. * @timing: Pointer to the intf timing information for the requested mode
  222. */
  223. static void programmable_fetch_config(struct sde_encoder_phys *phys_enc,
  224. const struct intf_timing_params *timing)
  225. {
  226. struct sde_encoder_phys_vid *vid_enc =
  227. to_sde_encoder_phys_vid(phys_enc);
  228. struct intf_prog_fetch f = { 0 };
  229. u32 vfp_fetch_lines = 0;
  230. u32 horiz_total = 0;
  231. u32 vert_total = 0;
  232. u32 vfp_fetch_start_vsync_counter = 0;
  233. unsigned long lock_flags;
  234. struct sde_mdss_cfg *m;
  235. if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
  236. return;
  237. m = phys_enc->sde_kms->catalog;
  238. vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc,
  239. timing, true);
  240. if (vfp_fetch_lines) {
  241. vert_total = get_vertical_total(timing, true);
  242. horiz_total = get_horizontal_total(timing);
  243. vfp_fetch_start_vsync_counter =
  244. (vert_total - vfp_fetch_lines) * horiz_total + 1;
  245. /**
  246. * Check if we need to throttle the fetch to start
  247. * from second line after the active region.
  248. */
  249. if (m->delay_prg_fetch_start)
  250. vfp_fetch_start_vsync_counter += horiz_total;
  251. f.enable = 1;
  252. f.fetch_start = vfp_fetch_start_vsync_counter;
  253. }
  254. SDE_DEBUG_VIDENC(vid_enc,
  255. "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
  256. vfp_fetch_lines, vfp_fetch_start_vsync_counter);
  257. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  258. phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
  259. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  260. }
  261. static bool sde_encoder_phys_vid_mode_fixup(
  262. struct sde_encoder_phys *phys_enc,
  263. const struct drm_display_mode *mode,
  264. struct drm_display_mode *adj_mode)
  265. {
  266. if (phys_enc)
  267. SDE_DEBUG_VIDENC(to_sde_encoder_phys_vid(phys_enc), "\n");
  268. /*
  269. * Modifying mode has consequences when the mode comes back to us
  270. */
  271. return true;
  272. }
  273. /* vid_enc timing_params must be configured before calling this function */
  274. static void _sde_encoder_phys_vid_setup_avr(
  275. struct sde_encoder_phys *phys_enc, u32 qsync_min_fps)
  276. {
  277. struct sde_encoder_phys_vid *vid_enc;
  278. struct drm_display_mode mode;
  279. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  280. mode = phys_enc->cached_mode;
  281. if (vid_enc->base.hw_intf->ops.avr_setup) {
  282. struct intf_avr_params avr_params = {0};
  283. u32 default_fps = mode.vrefresh;
  284. int ret;
  285. if (!default_fps) {
  286. SDE_ERROR_VIDENC(vid_enc,
  287. "invalid default fps %d\n",
  288. default_fps);
  289. return;
  290. }
  291. if (qsync_min_fps > default_fps) {
  292. SDE_ERROR_VIDENC(vid_enc,
  293. "qsync fps %d must be less than default %d\n",
  294. qsync_min_fps, default_fps);
  295. return;
  296. }
  297. avr_params.default_fps = default_fps;
  298. avr_params.min_fps = qsync_min_fps;
  299. ret = vid_enc->base.hw_intf->ops.avr_setup(
  300. vid_enc->base.hw_intf,
  301. &vid_enc->timing_params, &avr_params);
  302. if (ret)
  303. SDE_ERROR_VIDENC(vid_enc,
  304. "bad settings, can't configure AVR\n");
  305. SDE_EVT32(DRMID(phys_enc->parent), default_fps,
  306. qsync_min_fps, ret);
  307. }
  308. }
  309. static void _sde_encoder_phys_vid_avr_ctrl(struct sde_encoder_phys *phys_enc)
  310. {
  311. struct intf_avr_params avr_params;
  312. struct sde_encoder_phys_vid *vid_enc =
  313. to_sde_encoder_phys_vid(phys_enc);
  314. avr_params.avr_mode = sde_connector_get_qsync_mode(
  315. phys_enc->connector);
  316. if (vid_enc->base.hw_intf->ops.avr_ctrl) {
  317. vid_enc->base.hw_intf->ops.avr_ctrl(
  318. vid_enc->base.hw_intf,
  319. &avr_params);
  320. }
  321. SDE_EVT32(DRMID(phys_enc->parent),
  322. phys_enc->hw_intf->idx - INTF_0,
  323. avr_params.avr_mode);
  324. }
  325. static void sde_encoder_phys_vid_setup_timing_engine(
  326. struct sde_encoder_phys *phys_enc)
  327. {
  328. struct sde_encoder_phys_vid *vid_enc;
  329. struct drm_display_mode mode;
  330. struct intf_timing_params timing_params = { 0 };
  331. const struct sde_format *fmt = NULL;
  332. u32 fmt_fourcc = DRM_FORMAT_RGB888;
  333. u32 qsync_min_fps = 0;
  334. unsigned long lock_flags;
  335. struct sde_hw_intf_cfg intf_cfg = { 0 };
  336. bool is_split_link = false;
  337. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->hw_ctl ||
  338. !phys_enc->hw_intf) {
  339. SDE_ERROR("invalid encoder %d\n", !phys_enc);
  340. return;
  341. }
  342. mode = phys_enc->cached_mode;
  343. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  344. if (!phys_enc->hw_intf->ops.setup_timing_gen) {
  345. SDE_ERROR("timing engine setup is not supported\n");
  346. return;
  347. }
  348. SDE_DEBUG_VIDENC(vid_enc, "enabling mode:\n");
  349. drm_mode_debug_printmodeline(&mode);
  350. is_split_link = phys_enc->hw_intf->cfg.split_link_en;
  351. if (phys_enc->split_role != ENC_ROLE_SOLO || is_split_link) {
  352. mode.hdisplay >>= 1;
  353. mode.htotal >>= 1;
  354. mode.hsync_start >>= 1;
  355. mode.hsync_end >>= 1;
  356. SDE_DEBUG_VIDENC(vid_enc,
  357. "split_role %d, halve horizontal %d %d %d %d\n",
  358. phys_enc->split_role,
  359. mode.hdisplay, mode.htotal,
  360. mode.hsync_start, mode.hsync_end);
  361. }
  362. if (!phys_enc->vfp_cached) {
  363. phys_enc->vfp_cached =
  364. sde_connector_get_panel_vfp(phys_enc->connector, &mode);
  365. if (phys_enc->vfp_cached <= 0)
  366. phys_enc->vfp_cached = mode.vsync_start - mode.vdisplay;
  367. }
  368. drm_mode_to_intf_timing_params(vid_enc, &mode, &timing_params);
  369. vid_enc->timing_params = timing_params;
  370. if (phys_enc->cont_splash_enabled) {
  371. SDE_DEBUG_VIDENC(vid_enc,
  372. "skipping intf programming since cont splash is enabled\n");
  373. goto exit;
  374. }
  375. fmt = sde_get_sde_format(fmt_fourcc);
  376. SDE_DEBUG_VIDENC(vid_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
  377. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  378. phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
  379. &timing_params, fmt);
  380. if (test_bit(SDE_CTL_ACTIVE_CFG,
  381. &phys_enc->hw_ctl->caps->features)) {
  382. sde_encoder_helper_update_intf_cfg(phys_enc);
  383. } else if (phys_enc->hw_ctl->ops.setup_intf_cfg) {
  384. intf_cfg.intf = phys_enc->hw_intf->idx;
  385. intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  386. intf_cfg.stream_sel = 0; /* Don't care value for video mode */
  387. intf_cfg.mode_3d =
  388. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  389. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  390. &intf_cfg);
  391. }
  392. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  393. if (phys_enc->hw_intf->cap->type == INTF_DSI)
  394. programmable_fetch_config(phys_enc, &timing_params);
  395. exit:
  396. if (phys_enc->parent_ops.get_qsync_fps)
  397. phys_enc->parent_ops.get_qsync_fps(
  398. phys_enc->parent, &qsync_min_fps);
  399. /* only panels which support qsync will have a non-zero min fps */
  400. if (qsync_min_fps) {
  401. _sde_encoder_phys_vid_setup_avr(phys_enc, qsync_min_fps);
  402. _sde_encoder_phys_vid_avr_ctrl(phys_enc);
  403. }
  404. }
  405. static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
  406. {
  407. struct sde_encoder_phys *phys_enc = arg;
  408. struct sde_hw_ctl *hw_ctl;
  409. struct intf_status intf_status = {0};
  410. unsigned long lock_flags;
  411. u32 flush_register = ~0;
  412. u32 reset_status = 0;
  413. int new_cnt = -1, old_cnt = -1;
  414. u32 event = 0;
  415. int pend_ret_fence_cnt = 0;
  416. if (!phys_enc)
  417. return;
  418. hw_ctl = phys_enc->hw_ctl;
  419. if (!hw_ctl)
  420. return;
  421. SDE_ATRACE_BEGIN("vblank_irq");
  422. /*
  423. * only decrement the pending flush count if we've actually flushed
  424. * hardware. due to sw irq latency, vblank may have already happened
  425. * so we need to double-check with hw that it accepted the flush bits
  426. */
  427. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  428. old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt);
  429. if (hw_ctl && hw_ctl->ops.get_flush_register)
  430. flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
  431. if (flush_register)
  432. goto not_flushed;
  433. new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
  434. pend_ret_fence_cnt = atomic_read(&phys_enc->pending_retire_fence_cnt);
  435. /* signal only for master, where there is a pending kickoff */
  436. if (sde_encoder_phys_vid_is_master(phys_enc) &&
  437. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  438. event = SDE_ENCODER_FRAME_EVENT_DONE |
  439. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE |
  440. SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  441. }
  442. not_flushed:
  443. if (hw_ctl && hw_ctl->ops.get_reset)
  444. reset_status = hw_ctl->ops.get_reset(hw_ctl);
  445. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  446. if (event && phys_enc->parent_ops.handle_frame_done)
  447. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  448. phys_enc, event);
  449. if (phys_enc->parent_ops.handle_vblank_virt)
  450. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  451. phys_enc);
  452. if (phys_enc->hw_intf->ops.get_status)
  453. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  454. &intf_status);
  455. SDE_EVT32_IRQ(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
  456. old_cnt, atomic_read(&phys_enc->pending_kickoff_cnt),
  457. reset_status ? SDE_EVTLOG_ERROR : 0,
  458. flush_register, event,
  459. atomic_read(&phys_enc->pending_retire_fence_cnt),
  460. intf_status.frame_count);
  461. /* Signal any waiting atomic commit thread */
  462. wake_up_all(&phys_enc->pending_kickoff_wq);
  463. SDE_ATRACE_END("vblank_irq");
  464. }
  465. static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
  466. {
  467. struct sde_encoder_phys *phys_enc = arg;
  468. if (!phys_enc)
  469. return;
  470. if (phys_enc->parent_ops.handle_underrun_virt)
  471. phys_enc->parent_ops.handle_underrun_virt(phys_enc->parent,
  472. phys_enc);
  473. }
  474. static void _sde_encoder_phys_vid_setup_irq_hw_idx(
  475. struct sde_encoder_phys *phys_enc)
  476. {
  477. struct sde_encoder_irq *irq;
  478. /*
  479. * Initialize irq->hw_idx only when irq is not registered.
  480. * Prevent invalidating irq->irq_idx as modeset may be
  481. * called many times during dfps.
  482. */
  483. irq = &phys_enc->irq[INTR_IDX_VSYNC];
  484. if (irq->irq_idx < 0)
  485. irq->hw_idx = phys_enc->intf_idx;
  486. irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
  487. if (irq->irq_idx < 0)
  488. irq->hw_idx = phys_enc->intf_idx;
  489. }
  490. static void sde_encoder_phys_vid_cont_splash_mode_set(
  491. struct sde_encoder_phys *phys_enc,
  492. struct drm_display_mode *adj_mode)
  493. {
  494. if (!phys_enc || !adj_mode) {
  495. SDE_ERROR("invalid args\n");
  496. return;
  497. }
  498. phys_enc->cached_mode = *adj_mode;
  499. phys_enc->enable_state = SDE_ENC_ENABLED;
  500. _sde_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
  501. }
  502. static void sde_encoder_phys_vid_mode_set(
  503. struct sde_encoder_phys *phys_enc,
  504. struct drm_display_mode *mode,
  505. struct drm_display_mode *adj_mode)
  506. {
  507. struct sde_rm *rm;
  508. struct sde_rm_hw_iter iter;
  509. int i, instance;
  510. struct sde_encoder_phys_vid *vid_enc;
  511. if (!phys_enc || !phys_enc->sde_kms) {
  512. SDE_ERROR("invalid encoder/kms\n");
  513. return;
  514. }
  515. rm = &phys_enc->sde_kms->rm;
  516. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  517. if (adj_mode) {
  518. phys_enc->cached_mode = *adj_mode;
  519. drm_mode_debug_printmodeline(adj_mode);
  520. SDE_DEBUG_VIDENC(vid_enc, "caching mode:\n");
  521. }
  522. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  523. /* Retrieve previously allocated HW Resources. Shouldn't fail */
  524. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  525. for (i = 0; i <= instance; i++) {
  526. if (sde_rm_get_hw(rm, &iter))
  527. phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
  528. }
  529. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  530. SDE_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
  531. PTR_ERR(phys_enc->hw_ctl));
  532. phys_enc->hw_ctl = NULL;
  533. return;
  534. }
  535. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_INTF);
  536. for (i = 0; i <= instance; i++) {
  537. if (sde_rm_get_hw(rm, &iter))
  538. phys_enc->hw_intf = (struct sde_hw_intf *)iter.hw;
  539. }
  540. if (IS_ERR_OR_NULL(phys_enc->hw_intf)) {
  541. SDE_ERROR_VIDENC(vid_enc, "failed to init intf: %ld\n",
  542. PTR_ERR(phys_enc->hw_intf));
  543. phys_enc->hw_intf = NULL;
  544. return;
  545. }
  546. _sde_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
  547. }
  548. static int sde_encoder_phys_vid_control_vblank_irq(
  549. struct sde_encoder_phys *phys_enc,
  550. bool enable)
  551. {
  552. int ret = 0;
  553. struct sde_encoder_phys_vid *vid_enc;
  554. int refcount;
  555. if (!phys_enc) {
  556. SDE_ERROR("invalid encoder\n");
  557. return -EINVAL;
  558. }
  559. mutex_lock(phys_enc->vblank_ctl_lock);
  560. refcount = atomic_read(&phys_enc->vblank_refcount);
  561. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  562. /* Slave encoders don't report vblank */
  563. if (!sde_encoder_phys_vid_is_master(phys_enc))
  564. goto end;
  565. /* protect against negative */
  566. if (!enable && refcount == 0) {
  567. ret = -EINVAL;
  568. goto end;
  569. }
  570. SDE_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
  571. __builtin_return_address(0),
  572. enable, atomic_read(&phys_enc->vblank_refcount));
  573. SDE_EVT32(DRMID(phys_enc->parent), enable,
  574. atomic_read(&phys_enc->vblank_refcount));
  575. if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) {
  576. ret = sde_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
  577. if (ret)
  578. atomic_dec_return(&phys_enc->vblank_refcount);
  579. } else if (!enable &&
  580. atomic_dec_return(&phys_enc->vblank_refcount) == 0) {
  581. ret = sde_encoder_helper_unregister_irq(phys_enc,
  582. INTR_IDX_VSYNC);
  583. if (ret)
  584. atomic_inc_return(&phys_enc->vblank_refcount);
  585. }
  586. end:
  587. if (ret) {
  588. SDE_ERROR_VIDENC(vid_enc,
  589. "control vblank irq error %d, enable %d\n",
  590. ret, enable);
  591. SDE_EVT32(DRMID(phys_enc->parent),
  592. phys_enc->hw_intf->idx - INTF_0,
  593. enable, refcount, SDE_EVTLOG_ERROR);
  594. }
  595. mutex_unlock(phys_enc->vblank_ctl_lock);
  596. return ret;
  597. }
  598. static bool sde_encoder_phys_vid_wait_dma_trigger(
  599. struct sde_encoder_phys *phys_enc)
  600. {
  601. struct sde_encoder_phys_vid *vid_enc;
  602. struct sde_hw_intf *intf;
  603. struct sde_hw_ctl *ctl;
  604. struct intf_status status;
  605. if (!phys_enc) {
  606. SDE_ERROR("invalid encoder\n");
  607. return false;
  608. }
  609. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  610. intf = phys_enc->hw_intf;
  611. ctl = phys_enc->hw_ctl;
  612. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  613. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  614. phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
  615. return false;
  616. }
  617. if (!intf->ops.get_status)
  618. return false;
  619. intf->ops.get_status(intf, &status);
  620. /* if interface is not enabled, return true to wait for dma trigger */
  621. return status.is_en ? false : true;
  622. }
  623. static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
  624. {
  625. struct msm_drm_private *priv;
  626. struct sde_encoder_phys_vid *vid_enc;
  627. struct sde_hw_intf *intf;
  628. struct sde_hw_ctl *ctl;
  629. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
  630. !phys_enc->parent->dev->dev_private ||
  631. !phys_enc->sde_kms) {
  632. SDE_ERROR("invalid encoder/device\n");
  633. return;
  634. }
  635. priv = phys_enc->parent->dev->dev_private;
  636. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  637. intf = phys_enc->hw_intf;
  638. ctl = phys_enc->hw_ctl;
  639. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  640. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  641. !phys_enc->hw_intf, !phys_enc->hw_ctl);
  642. return;
  643. }
  644. if (!ctl->ops.update_bitmask_intf ||
  645. (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  646. !ctl->ops.update_bitmask_merge3d)) {
  647. SDE_ERROR("invalid hw_ctl ops %d\n", ctl->idx);
  648. return;
  649. }
  650. SDE_DEBUG_VIDENC(vid_enc, "\n");
  651. if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
  652. return;
  653. if (!phys_enc->cont_splash_enabled)
  654. sde_encoder_helper_split_config(phys_enc,
  655. phys_enc->hw_intf->idx);
  656. sde_encoder_phys_vid_setup_timing_engine(phys_enc);
  657. /*
  658. * For cases where both the interfaces are connected to same ctl,
  659. * set the flush bit for both master and slave.
  660. * For single flush cases (dual-ctl or pp-split), skip setting the
  661. * flush bit for the slave intf, since both intfs use same ctl
  662. * and HW will only flush the master.
  663. */
  664. if (!test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  665. sde_encoder_phys_needs_single_flush(phys_enc) &&
  666. !sde_encoder_phys_vid_is_master(phys_enc))
  667. goto skip_flush;
  668. /**
  669. * skip flushing intf during cont. splash handoff since bootloader
  670. * has already enabled the hardware and is single buffered.
  671. */
  672. if (phys_enc->cont_splash_enabled) {
  673. SDE_DEBUG_VIDENC(vid_enc,
  674. "skipping intf flush bit set as cont. splash is enabled\n");
  675. goto skip_flush;
  676. }
  677. ctl->ops.update_bitmask_intf(ctl, intf->idx, 1);
  678. if (ctl->ops.update_bitmask_merge3d && phys_enc->hw_pp->merge_3d)
  679. ctl->ops.update_bitmask_merge3d(ctl,
  680. phys_enc->hw_pp->merge_3d->idx, 1);
  681. if (phys_enc->hw_intf->cap->type == INTF_DP &&
  682. phys_enc->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  683. phys_enc->comp_ratio && ctl->ops.update_bitmask_periph)
  684. ctl->ops.update_bitmask_periph(ctl, intf->idx, 1);
  685. skip_flush:
  686. SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d intf %d\n",
  687. ctl->idx - CTL_0, intf->idx);
  688. SDE_EVT32(DRMID(phys_enc->parent),
  689. atomic_read(&phys_enc->pending_retire_fence_cnt));
  690. /* ctl_flush & timing engine enable will be triggered by framework */
  691. if (phys_enc->enable_state == SDE_ENC_DISABLED)
  692. phys_enc->enable_state = SDE_ENC_ENABLING;
  693. }
  694. static void sde_encoder_phys_vid_destroy(struct sde_encoder_phys *phys_enc)
  695. {
  696. struct sde_encoder_phys_vid *vid_enc;
  697. if (!phys_enc) {
  698. SDE_ERROR("invalid encoder\n");
  699. return;
  700. }
  701. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  702. SDE_DEBUG_VIDENC(vid_enc, "\n");
  703. kfree(vid_enc);
  704. }
  705. static void sde_encoder_phys_vid_get_hw_resources(
  706. struct sde_encoder_phys *phys_enc,
  707. struct sde_encoder_hw_resources *hw_res,
  708. struct drm_connector_state *conn_state)
  709. {
  710. struct sde_encoder_phys_vid *vid_enc;
  711. if (!phys_enc || !hw_res) {
  712. SDE_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
  713. !phys_enc, !hw_res, !conn_state);
  714. return;
  715. }
  716. if ((phys_enc->intf_idx - INTF_0) >= INTF_MAX) {
  717. SDE_ERROR("invalid intf idx:%d\n", phys_enc->intf_idx);
  718. return;
  719. }
  720. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  721. SDE_DEBUG_VIDENC(vid_enc, "\n");
  722. hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
  723. }
  724. static int _sde_encoder_phys_vid_wait_for_vblank(
  725. struct sde_encoder_phys *phys_enc, bool notify)
  726. {
  727. struct sde_encoder_wait_info wait_info = {0};
  728. int ret = 0;
  729. u32 event = SDE_ENCODER_FRAME_EVENT_ERROR |
  730. SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE |
  731. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  732. if (!phys_enc) {
  733. pr_err("invalid encoder\n");
  734. return -EINVAL;
  735. }
  736. wait_info.wq = &phys_enc->pending_kickoff_wq;
  737. wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
  738. wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
  739. /* Wait for kickoff to complete */
  740. ret = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
  741. &wait_info);
  742. if (notify && (ret == -ETIMEDOUT) &&
  743. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0) &&
  744. phys_enc->parent_ops.handle_frame_done)
  745. phys_enc->parent_ops.handle_frame_done(
  746. phys_enc->parent, phys_enc, event);
  747. SDE_EVT32(DRMID(phys_enc->parent), event, notify, ret,
  748. ret ? SDE_EVTLOG_FATAL : 0);
  749. return ret;
  750. }
  751. static int sde_encoder_phys_vid_wait_for_vblank(
  752. struct sde_encoder_phys *phys_enc)
  753. {
  754. return _sde_encoder_phys_vid_wait_for_vblank(phys_enc, true);
  755. }
  756. static int sde_encoder_phys_vid_wait_for_vblank_no_notify(
  757. struct sde_encoder_phys *phys_enc)
  758. {
  759. return _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
  760. }
  761. static int sde_encoder_phys_vid_prepare_for_kickoff(
  762. struct sde_encoder_phys *phys_enc,
  763. struct sde_encoder_kickoff_params *params)
  764. {
  765. struct sde_encoder_phys_vid *vid_enc;
  766. struct sde_hw_ctl *ctl;
  767. bool recovery_events;
  768. struct drm_connector *conn;
  769. int event;
  770. int rc;
  771. if (!phys_enc || !params || !phys_enc->hw_ctl) {
  772. SDE_ERROR("invalid encoder/parameters\n");
  773. return -EINVAL;
  774. }
  775. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  776. ctl = phys_enc->hw_ctl;
  777. if (!ctl->ops.wait_reset_status)
  778. return 0;
  779. conn = phys_enc->connector;
  780. recovery_events = sde_encoder_recovery_events_enabled(
  781. phys_enc->parent);
  782. /*
  783. * hw supports hardware initiated ctl reset, so before we kickoff a new
  784. * frame, need to check and wait for hw initiated ctl reset completion
  785. */
  786. rc = ctl->ops.wait_reset_status(ctl);
  787. if (rc) {
  788. SDE_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
  789. ctl->idx, rc);
  790. ++vid_enc->error_count;
  791. /* to avoid flooding, only log first time, and "dead" time */
  792. if (vid_enc->error_count == 1) {
  793. SDE_EVT32(DRMID(phys_enc->parent), SDE_EVTLOG_FATAL);
  794. sde_encoder_helper_unregister_irq(
  795. phys_enc, INTR_IDX_VSYNC);
  796. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus");
  797. sde_encoder_helper_register_irq(
  798. phys_enc, INTR_IDX_VSYNC);
  799. }
  800. /*
  801. * if the recovery event is registered by user, don't panic
  802. * trigger panic on first timeout if no listener registered
  803. */
  804. if (recovery_events) {
  805. event = vid_enc->error_count > KICKOFF_MAX_ERRORS ?
  806. SDE_RECOVERY_HARD_RESET : SDE_RECOVERY_CAPTURE;
  807. sde_connector_event_notify(conn,
  808. DRM_EVENT_SDE_HW_RECOVERY,
  809. sizeof(uint8_t), event);
  810. } else {
  811. SDE_DBG_DUMP("panic");
  812. }
  813. /* request a ctl reset before the next flush */
  814. phys_enc->enable_state = SDE_ENC_ERR_NEEDS_HW_RESET;
  815. } else {
  816. if (recovery_events && vid_enc->error_count)
  817. sde_connector_event_notify(conn,
  818. DRM_EVENT_SDE_HW_RECOVERY,
  819. sizeof(uint8_t),
  820. SDE_RECOVERY_SUCCESS);
  821. vid_enc->error_count = 0;
  822. }
  823. return rc;
  824. }
  825. static void sde_encoder_phys_vid_single_vblank_wait(
  826. struct sde_encoder_phys *phys_enc)
  827. {
  828. int ret;
  829. struct sde_encoder_phys_vid *vid_enc
  830. = to_sde_encoder_phys_vid(phys_enc);
  831. /*
  832. * Wait for a vsync so we know the ENABLE=0 latched before
  833. * the (connector) source of the vsync's gets disabled,
  834. * otherwise we end up in a funny state if we re-enable
  835. * before the disable latches, which results that some of
  836. * the settings changes for the new modeset (like new
  837. * scanout buffer) don't latch properly..
  838. */
  839. ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
  840. if (ret) {
  841. SDE_ERROR_VIDENC(vid_enc,
  842. "failed to enable vblank irq: %d\n",
  843. ret);
  844. SDE_EVT32(DRMID(phys_enc->parent),
  845. phys_enc->hw_intf->idx - INTF_0, ret,
  846. SDE_EVTLOG_FUNC_CASE1,
  847. SDE_EVTLOG_ERROR);
  848. } else {
  849. ret = _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
  850. if (ret) {
  851. atomic_set(&phys_enc->pending_kickoff_cnt, 0);
  852. SDE_ERROR_VIDENC(vid_enc,
  853. "failure waiting for disable: %d\n",
  854. ret);
  855. SDE_EVT32(DRMID(phys_enc->parent),
  856. phys_enc->hw_intf->idx - INTF_0, ret,
  857. SDE_EVTLOG_FUNC_CASE2,
  858. SDE_EVTLOG_ERROR);
  859. }
  860. sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
  861. }
  862. }
  863. static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
  864. {
  865. struct msm_drm_private *priv;
  866. struct sde_encoder_phys_vid *vid_enc;
  867. unsigned long lock_flags;
  868. struct intf_status intf_status = {0};
  869. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
  870. !phys_enc->parent->dev->dev_private) {
  871. SDE_ERROR("invalid encoder/device\n");
  872. return;
  873. }
  874. priv = phys_enc->parent->dev->dev_private;
  875. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  876. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  877. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  878. !phys_enc->hw_intf, !phys_enc->hw_ctl);
  879. return;
  880. }
  881. SDE_DEBUG_VIDENC(vid_enc, "\n");
  882. if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
  883. return;
  884. else if (!sde_encoder_phys_vid_is_master(phys_enc))
  885. goto exit;
  886. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  887. SDE_ERROR("already disabled\n");
  888. return;
  889. }
  890. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  891. phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
  892. sde_encoder_phys_inc_pending(phys_enc);
  893. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  894. sde_encoder_phys_vid_single_vblank_wait(phys_enc);
  895. if (phys_enc->hw_intf->ops.get_status)
  896. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  897. &intf_status);
  898. if (intf_status.is_en) {
  899. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  900. sde_encoder_phys_inc_pending(phys_enc);
  901. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  902. sde_encoder_phys_vid_single_vblank_wait(phys_enc);
  903. }
  904. sde_encoder_helper_phys_disable(phys_enc, NULL);
  905. exit:
  906. SDE_EVT32(DRMID(phys_enc->parent),
  907. atomic_read(&phys_enc->pending_retire_fence_cnt));
  908. phys_enc->vfp_cached = 0;
  909. phys_enc->enable_state = SDE_ENC_DISABLED;
  910. }
  911. static void sde_encoder_phys_vid_handle_post_kickoff(
  912. struct sde_encoder_phys *phys_enc)
  913. {
  914. unsigned long lock_flags;
  915. struct sde_encoder_phys_vid *vid_enc;
  916. u32 avr_mode;
  917. if (!phys_enc) {
  918. SDE_ERROR("invalid encoder\n");
  919. return;
  920. }
  921. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  922. SDE_DEBUG_VIDENC(vid_enc, "enable_state %d\n", phys_enc->enable_state);
  923. /*
  924. * Video mode must flush CTL before enabling timing engine
  925. * Video encoders need to turn on their interfaces now
  926. */
  927. if (phys_enc->enable_state == SDE_ENC_ENABLING) {
  928. if (sde_encoder_phys_vid_is_master(phys_enc)) {
  929. SDE_EVT32(DRMID(phys_enc->parent),
  930. phys_enc->hw_intf->idx - INTF_0);
  931. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  932. phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf,
  933. 1);
  934. spin_unlock_irqrestore(phys_enc->enc_spinlock,
  935. lock_flags);
  936. }
  937. phys_enc->enable_state = SDE_ENC_ENABLED;
  938. }
  939. avr_mode = sde_connector_get_qsync_mode(phys_enc->connector);
  940. if (avr_mode && vid_enc->base.hw_intf->ops.avr_trigger) {
  941. vid_enc->base.hw_intf->ops.avr_trigger(vid_enc->base.hw_intf);
  942. SDE_EVT32(DRMID(phys_enc->parent),
  943. phys_enc->hw_intf->idx - INTF_0,
  944. SDE_EVTLOG_FUNC_CASE9);
  945. }
  946. }
  947. static void sde_encoder_phys_vid_prepare_for_commit(
  948. struct sde_encoder_phys *phys_enc)
  949. {
  950. if (!phys_enc) {
  951. SDE_ERROR("invalid encoder parameters\n");
  952. return;
  953. }
  954. if (sde_connector_is_qsync_updated(phys_enc->connector))
  955. _sde_encoder_phys_vid_avr_ctrl(phys_enc);
  956. }
  957. static void sde_encoder_phys_vid_irq_control(struct sde_encoder_phys *phys_enc,
  958. bool enable)
  959. {
  960. struct sde_encoder_phys_vid *vid_enc;
  961. int ret;
  962. if (!phys_enc)
  963. return;
  964. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  965. SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
  966. enable, atomic_read(&phys_enc->vblank_refcount));
  967. if (enable) {
  968. ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
  969. if (ret)
  970. return;
  971. sde_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
  972. } else {
  973. sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
  974. sde_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
  975. }
  976. }
  977. static int sde_encoder_phys_vid_get_line_count(
  978. struct sde_encoder_phys *phys_enc)
  979. {
  980. if (!phys_enc)
  981. return -EINVAL;
  982. if (!sde_encoder_phys_vid_is_master(phys_enc))
  983. return -EINVAL;
  984. if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
  985. return -EINVAL;
  986. return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
  987. }
  988. static u32 sde_encoder_phys_vid_get_underrun_line_count(
  989. struct sde_encoder_phys *phys_enc)
  990. {
  991. u32 underrun_linecount = 0xebadebad;
  992. struct intf_status intf_status = {0};
  993. if (!phys_enc)
  994. return -EINVAL;
  995. if (!sde_encoder_phys_vid_is_master(phys_enc) || !phys_enc->hw_intf)
  996. return -EINVAL;
  997. if (phys_enc->hw_intf->ops.get_status)
  998. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  999. &intf_status);
  1000. if (phys_enc->hw_intf->ops.get_underrun_line_count)
  1001. underrun_linecount =
  1002. phys_enc->hw_intf->ops.get_underrun_line_count(
  1003. phys_enc->hw_intf);
  1004. SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount,
  1005. intf_status.frame_count, intf_status.line_count);
  1006. return underrun_linecount;
  1007. }
  1008. static int sde_encoder_phys_vid_wait_for_active(
  1009. struct sde_encoder_phys *phys_enc)
  1010. {
  1011. struct drm_display_mode mode;
  1012. struct sde_encoder_phys_vid *vid_enc;
  1013. u32 ln_cnt, min_ln_cnt, active_lns_cnt;
  1014. u32 clk_period, time_of_line;
  1015. u32 delay, retry = MAX_POLL_CNT;
  1016. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1017. if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) {
  1018. SDE_ERROR_VIDENC(vid_enc, "invalid vid_enc params\n");
  1019. return -EINVAL;
  1020. }
  1021. mode = phys_enc->cached_mode;
  1022. /*
  1023. * calculate clk_period as pico second to maintain good
  1024. * accuracy with high pclk rate and this number is in 17 bit
  1025. * range.
  1026. */
  1027. clk_period = DIV_ROUND_UP_ULL(1000000000, mode.clock);
  1028. if (!clk_period) {
  1029. SDE_ERROR_VIDENC(vid_enc, "Unable to calculate clock period\n");
  1030. return -EINVAL;
  1031. }
  1032. min_ln_cnt = (mode.vtotal - mode.vsync_start) +
  1033. (mode.vsync_end - mode.vsync_start);
  1034. active_lns_cnt = mode.vdisplay;
  1035. time_of_line = mode.htotal * clk_period;
  1036. /* delay in micro seconds */
  1037. delay = (time_of_line * (min_ln_cnt +
  1038. (mode.vsync_start - mode.vdisplay))) / 1000000;
  1039. /*
  1040. * Wait for max delay before
  1041. * polling to check active region
  1042. */
  1043. if (delay > POLL_TIME_USEC_FOR_LN_CNT)
  1044. delay = POLL_TIME_USEC_FOR_LN_CNT;
  1045. while (retry) {
  1046. ln_cnt = phys_enc->hw_intf->ops.get_line_count(
  1047. phys_enc->hw_intf);
  1048. if ((ln_cnt >= min_ln_cnt) &&
  1049. (ln_cnt < (active_lns_cnt + min_ln_cnt))) {
  1050. SDE_DEBUG_VIDENC(vid_enc,
  1051. "Needed lines left line_cnt=%d\n",
  1052. ln_cnt);
  1053. return 0;
  1054. }
  1055. SDE_ERROR_VIDENC(vid_enc, "line count is less. line_cnt = %d\n",
  1056. ln_cnt);
  1057. /* Add delay so that line count is in active region */
  1058. udelay(delay);
  1059. retry--;
  1060. }
  1061. return -EINVAL;
  1062. }
  1063. static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops)
  1064. {
  1065. ops->is_master = sde_encoder_phys_vid_is_master;
  1066. ops->mode_set = sde_encoder_phys_vid_mode_set;
  1067. ops->cont_splash_mode_set = sde_encoder_phys_vid_cont_splash_mode_set;
  1068. ops->mode_fixup = sde_encoder_phys_vid_mode_fixup;
  1069. ops->enable = sde_encoder_phys_vid_enable;
  1070. ops->disable = sde_encoder_phys_vid_disable;
  1071. ops->destroy = sde_encoder_phys_vid_destroy;
  1072. ops->get_hw_resources = sde_encoder_phys_vid_get_hw_resources;
  1073. ops->control_vblank_irq = sde_encoder_phys_vid_control_vblank_irq;
  1074. ops->wait_for_commit_done = sde_encoder_phys_vid_wait_for_vblank;
  1075. ops->wait_for_vblank = sde_encoder_phys_vid_wait_for_vblank_no_notify;
  1076. ops->wait_for_tx_complete = sde_encoder_phys_vid_wait_for_vblank;
  1077. ops->irq_control = sde_encoder_phys_vid_irq_control;
  1078. ops->prepare_for_kickoff = sde_encoder_phys_vid_prepare_for_kickoff;
  1079. ops->handle_post_kickoff = sde_encoder_phys_vid_handle_post_kickoff;
  1080. ops->needs_single_flush = sde_encoder_phys_needs_single_flush;
  1081. ops->setup_misr = sde_encoder_helper_setup_misr;
  1082. ops->collect_misr = sde_encoder_helper_collect_misr;
  1083. ops->trigger_flush = sde_encoder_helper_trigger_flush;
  1084. ops->hw_reset = sde_encoder_helper_hw_reset;
  1085. ops->get_line_count = sde_encoder_phys_vid_get_line_count;
  1086. ops->get_wr_line_count = sde_encoder_phys_vid_get_line_count;
  1087. ops->wait_dma_trigger = sde_encoder_phys_vid_wait_dma_trigger;
  1088. ops->wait_for_active = sde_encoder_phys_vid_wait_for_active;
  1089. ops->prepare_commit = sde_encoder_phys_vid_prepare_for_commit;
  1090. ops->get_underrun_line_count =
  1091. sde_encoder_phys_vid_get_underrun_line_count;
  1092. }
  1093. struct sde_encoder_phys *sde_encoder_phys_vid_init(
  1094. struct sde_enc_phys_init_params *p)
  1095. {
  1096. struct sde_encoder_phys *phys_enc = NULL;
  1097. struct sde_encoder_phys_vid *vid_enc = NULL;
  1098. struct sde_hw_mdp *hw_mdp;
  1099. struct sde_encoder_irq *irq;
  1100. int i, ret = 0;
  1101. if (!p) {
  1102. ret = -EINVAL;
  1103. goto fail;
  1104. }
  1105. vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL);
  1106. if (!vid_enc) {
  1107. ret = -ENOMEM;
  1108. goto fail;
  1109. }
  1110. phys_enc = &vid_enc->base;
  1111. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1112. if (IS_ERR_OR_NULL(hw_mdp)) {
  1113. ret = PTR_ERR(hw_mdp);
  1114. SDE_ERROR("failed to get mdptop\n");
  1115. goto fail;
  1116. }
  1117. phys_enc->hw_mdptop = hw_mdp;
  1118. phys_enc->intf_idx = p->intf_idx;
  1119. SDE_DEBUG_VIDENC(vid_enc, "\n");
  1120. sde_encoder_phys_vid_init_ops(&phys_enc->ops);
  1121. phys_enc->parent = p->parent;
  1122. phys_enc->parent_ops = p->parent_ops;
  1123. phys_enc->sde_kms = p->sde_kms;
  1124. phys_enc->split_role = p->split_role;
  1125. phys_enc->intf_mode = INTF_MODE_VIDEO;
  1126. phys_enc->enc_spinlock = p->enc_spinlock;
  1127. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1128. phys_enc->comp_type = p->comp_type;
  1129. for (i = 0; i < INTR_IDX_MAX; i++) {
  1130. irq = &phys_enc->irq[i];
  1131. INIT_LIST_HEAD(&irq->cb.list);
  1132. irq->irq_idx = -EINVAL;
  1133. irq->hw_idx = -EINVAL;
  1134. irq->cb.arg = phys_enc;
  1135. }
  1136. irq = &phys_enc->irq[INTR_IDX_VSYNC];
  1137. irq->name = "vsync_irq";
  1138. irq->intr_type = SDE_IRQ_TYPE_INTF_VSYNC;
  1139. irq->intr_idx = INTR_IDX_VSYNC;
  1140. irq->cb.func = sde_encoder_phys_vid_vblank_irq;
  1141. irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
  1142. irq->name = "underrun";
  1143. irq->intr_type = SDE_IRQ_TYPE_INTF_UNDER_RUN;
  1144. irq->intr_idx = INTR_IDX_UNDERRUN;
  1145. irq->cb.func = sde_encoder_phys_vid_underrun_irq;
  1146. atomic_set(&phys_enc->vblank_refcount, 0);
  1147. atomic_set(&phys_enc->pending_kickoff_cnt, 0);
  1148. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1149. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1150. phys_enc->enable_state = SDE_ENC_DISABLED;
  1151. SDE_DEBUG_VIDENC(vid_enc, "created intf idx:%d\n", p->intf_idx);
  1152. return phys_enc;
  1153. fail:
  1154. SDE_ERROR("failed to create encoder\n");
  1155. if (vid_enc)
  1156. sde_encoder_phys_vid_destroy(phys_enc);
  1157. return ERR_PTR(ret);
  1158. }