dsi_defs.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DSI_DEFS_H_
  6. #define _DSI_DEFS_H_
  7. #include <linux/types.h>
  8. #include <drm/drm_mipi_dsi.h>
  9. #include "msm_drv.h"
  10. #define DSI_H_TOTAL(t) (((t)->h_active) + ((t)->h_back_porch) + \
  11. ((t)->h_sync_width) + ((t)->h_front_porch))
  12. #define DSI_V_TOTAL(t) (((t)->v_active) + ((t)->v_back_porch) + \
  13. ((t)->v_sync_width) + ((t)->v_front_porch))
  14. #define DSI_DEBUG_NAME_LEN 32
  15. #define display_for_each_ctrl(index, display) \
  16. for (index = 0; (index < (display)->ctrl_count) &&\
  17. (index < MAX_DSI_CTRLS_PER_DISPLAY); index++)
  18. #define DSI_WARN(fmt, ...) DRM_WARN("[msm-dsi-warn]: "fmt, ##__VA_ARGS__)
  19. #define DSI_ERR(fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: " fmt, \
  20. ##__VA_ARGS__)
  21. #define DSI_INFO(fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: "fmt, \
  22. ##__VA_ARGS__)
  23. #define DSI_DEBUG(fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: "fmt, \
  24. ##__VA_ARGS__)
  25. /**
  26. * enum dsi_pixel_format - DSI pixel formats
  27. * @DSI_PIXEL_FORMAT_RGB565:
  28. * @DSI_PIXEL_FORMAT_RGB666:
  29. * @DSI_PIXEL_FORMAT_RGB666_LOOSE:
  30. * @DSI_PIXEL_FORMAT_RGB888:
  31. * @DSI_PIXEL_FORMAT_RGB111:
  32. * @DSI_PIXEL_FORMAT_RGB332:
  33. * @DSI_PIXEL_FORMAT_RGB444:
  34. * @DSI_PIXEL_FORMAT_MAX:
  35. */
  36. enum dsi_pixel_format {
  37. DSI_PIXEL_FORMAT_RGB565 = 0,
  38. DSI_PIXEL_FORMAT_RGB666,
  39. DSI_PIXEL_FORMAT_RGB666_LOOSE,
  40. DSI_PIXEL_FORMAT_RGB888,
  41. DSI_PIXEL_FORMAT_RGB111,
  42. DSI_PIXEL_FORMAT_RGB332,
  43. DSI_PIXEL_FORMAT_RGB444,
  44. DSI_PIXEL_FORMAT_MAX
  45. };
  46. /**
  47. * enum dsi_op_mode - dsi operation mode
  48. * @DSI_OP_VIDEO_MODE: DSI video mode operation
  49. * @DSI_OP_CMD_MODE: DSI Command mode operation
  50. * @DSI_OP_MODE_MAX:
  51. */
  52. enum dsi_op_mode {
  53. DSI_OP_VIDEO_MODE = 0,
  54. DSI_OP_CMD_MODE,
  55. DSI_OP_MODE_MAX
  56. };
  57. /**
  58. * enum dsi_mode_flags - flags to signal other drm components via private flags
  59. * @DSI_MODE_FLAG_SEAMLESS: Seamless transition requested by user
  60. * @DSI_MODE_FLAG_DFPS: Seamless transition is DynamicFPS
  61. * @DSI_MODE_FLAG_VBLANK_PRE_MODESET: Transition needs VBLANK before Modeset
  62. * @DSI_MODE_FLAG_DMS: Seamless transition is dynamic mode switch
  63. * @DSI_MODE_FLAG_VRR: Seamless transition is DynamicFPS.
  64. * New timing values are sent from DAL.
  65. * @DSI_MODE_FLAG_POMS:
  66. * Seamless transition is dynamic panel operating mode switch
  67. * @DSI_MODE_FLAG_DYN_CLK: Seamless transition is dynamic clock change
  68. * @DSI_MODE_FLAG_DMS_FPS: Seamless fps only transition in Dynamic Mode Switch
  69. */
  70. enum dsi_mode_flags {
  71. DSI_MODE_FLAG_SEAMLESS = BIT(0),
  72. DSI_MODE_FLAG_DFPS = BIT(1),
  73. DSI_MODE_FLAG_VBLANK_PRE_MODESET = BIT(2),
  74. DSI_MODE_FLAG_DMS = BIT(3),
  75. DSI_MODE_FLAG_VRR = BIT(4),
  76. DSI_MODE_FLAG_POMS = BIT(5),
  77. DSI_MODE_FLAG_DYN_CLK = BIT(6),
  78. DSI_MODE_FLAG_DMS_FPS = BIT(7),
  79. };
  80. /**
  81. * enum dsi_logical_lane - dsi logical lanes
  82. * @DSI_LOGICAL_LANE_0: Logical lane 0
  83. * @DSI_LOGICAL_LANE_1: Logical lane 1
  84. * @DSI_LOGICAL_LANE_2: Logical lane 2
  85. * @DSI_LOGICAL_LANE_3: Logical lane 3
  86. * @DSI_LOGICAL_CLOCK_LANE: Clock lane
  87. * @DSI_LANE_MAX: Maximum lanes supported
  88. */
  89. enum dsi_logical_lane {
  90. DSI_LOGICAL_LANE_0 = 0,
  91. DSI_LOGICAL_LANE_1,
  92. DSI_LOGICAL_LANE_2,
  93. DSI_LOGICAL_LANE_3,
  94. DSI_LOGICAL_CLOCK_LANE,
  95. DSI_LANE_MAX
  96. };
  97. /**
  98. * enum dsi_data_lanes - BIT map for DSI data lanes
  99. * This is used to identify the active DSI data lanes for
  100. * various operations like DSI data lane enable/ULPS/clamp
  101. * configurations.
  102. * @DSI_DATA_LANE_0: BIT(DSI_LOGICAL_LANE_0)
  103. * @DSI_DATA_LANE_1: BIT(DSI_LOGICAL_LANE_1)
  104. * @DSI_DATA_LANE_2: BIT(DSI_LOGICAL_LANE_2)
  105. * @DSI_DATA_LANE_3: BIT(DSI_LOGICAL_LANE_3)
  106. * @DSI_CLOCK_LANE: BIT(DSI_LOGICAL_CLOCK_LANE)
  107. */
  108. enum dsi_data_lanes {
  109. DSI_DATA_LANE_0 = BIT(DSI_LOGICAL_LANE_0),
  110. DSI_DATA_LANE_1 = BIT(DSI_LOGICAL_LANE_1),
  111. DSI_DATA_LANE_2 = BIT(DSI_LOGICAL_LANE_2),
  112. DSI_DATA_LANE_3 = BIT(DSI_LOGICAL_LANE_3),
  113. DSI_CLOCK_LANE = BIT(DSI_LOGICAL_CLOCK_LANE)
  114. };
  115. /**
  116. * enum dsi_phy_data_lanes - dsi physical lanes
  117. * used for DSI logical to physical lane mapping
  118. * @DSI_PHYSICAL_LANE_INVALID: Physical lane valid/invalid
  119. * @DSI_PHYSICAL_LANE_0: Physical lane 0
  120. * @DSI_PHYSICAL_LANE_1: Physical lane 1
  121. * @DSI_PHYSICAL_LANE_2: Physical lane 2
  122. * @DSI_PHYSICAL_LANE_3: Physical lane 3
  123. */
  124. enum dsi_phy_data_lanes {
  125. DSI_PHYSICAL_LANE_INVALID = 0,
  126. DSI_PHYSICAL_LANE_0 = BIT(0),
  127. DSI_PHYSICAL_LANE_1 = BIT(1),
  128. DSI_PHYSICAL_LANE_2 = BIT(2),
  129. DSI_PHYSICAL_LANE_3 = BIT(3)
  130. };
  131. enum dsi_lane_map_type_v1 {
  132. DSI_LANE_MAP_0123,
  133. DSI_LANE_MAP_3012,
  134. DSI_LANE_MAP_2301,
  135. DSI_LANE_MAP_1230,
  136. DSI_LANE_MAP_0321,
  137. DSI_LANE_MAP_1032,
  138. DSI_LANE_MAP_2103,
  139. DSI_LANE_MAP_3210,
  140. };
  141. /**
  142. * lane_map: DSI logical <-> physical lane mapping
  143. * lane_map_v1: Lane mapping for DSI controllers < v2.0
  144. * lane_map_v2: Lane mapping for DSI controllers >= 2.0
  145. */
  146. struct dsi_lane_map {
  147. enum dsi_lane_map_type_v1 lane_map_v1;
  148. u8 lane_map_v2[DSI_LANE_MAX - 1];
  149. };
  150. /**
  151. * enum dsi_trigger_type - dsi trigger type
  152. * @DSI_TRIGGER_NONE: No trigger.
  153. * @DSI_TRIGGER_TE: TE trigger.
  154. * @DSI_TRIGGER_SEOF: Start or End of frame.
  155. * @DSI_TRIGGER_SW: Software trigger.
  156. * @DSI_TRIGGER_SW_SEOF: Software trigger and start/end of frame.
  157. * @DSI_TRIGGER_SW_TE: Software and TE triggers.
  158. * @DSI_TRIGGER_MAX: Max trigger values.
  159. */
  160. enum dsi_trigger_type {
  161. DSI_TRIGGER_NONE = 0,
  162. DSI_TRIGGER_TE,
  163. DSI_TRIGGER_SEOF,
  164. DSI_TRIGGER_SW,
  165. DSI_TRIGGER_SW_SEOF,
  166. DSI_TRIGGER_SW_TE,
  167. DSI_TRIGGER_MAX
  168. };
  169. /**
  170. * enum dsi_color_swap_mode - color swap mode
  171. * @DSI_COLOR_SWAP_RGB:
  172. * @DSI_COLOR_SWAP_RBG:
  173. * @DSI_COLOR_SWAP_BGR:
  174. * @DSI_COLOR_SWAP_BRG:
  175. * @DSI_COLOR_SWAP_GRB:
  176. * @DSI_COLOR_SWAP_GBR:
  177. */
  178. enum dsi_color_swap_mode {
  179. DSI_COLOR_SWAP_RGB = 0,
  180. DSI_COLOR_SWAP_RBG,
  181. DSI_COLOR_SWAP_BGR,
  182. DSI_COLOR_SWAP_BRG,
  183. DSI_COLOR_SWAP_GRB,
  184. DSI_COLOR_SWAP_GBR
  185. };
  186. /**
  187. * enum dsi_dfps_type - Dynamic FPS support type
  188. * @DSI_DFPS_NONE: Dynamic FPS is not supported.
  189. * @DSI_DFPS_SUSPEND_RESUME:
  190. * @DSI_DFPS_IMMEDIATE_CLK:
  191. * @DSI_DFPS_IMMEDIATE_HFP:
  192. * @DSI_DFPS_IMMEDIATE_VFP:
  193. * @DSI_DPFS_MAX:
  194. */
  195. enum dsi_dfps_type {
  196. DSI_DFPS_NONE = 0,
  197. DSI_DFPS_SUSPEND_RESUME,
  198. DSI_DFPS_IMMEDIATE_CLK,
  199. DSI_DFPS_IMMEDIATE_HFP,
  200. DSI_DFPS_IMMEDIATE_VFP,
  201. DSI_DFPS_MAX
  202. };
  203. /**
  204. * enum dsi_cmd_set_type - DSI command set type
  205. * @DSI_CMD_SET_PRE_ON: Panel pre on
  206. * @DSI_CMD_SET_ON: Panel on
  207. * @DSI_CMD_SET_POST_ON: Panel post on
  208. * @DSI_CMD_SET_PRE_OFF: Panel pre off
  209. * @DSI_CMD_SET_OFF: Panel off
  210. * @DSI_CMD_SET_POST_OFF: Panel post off
  211. * @DSI_CMD_SET_PRE_RES_SWITCH: Pre resolution switch
  212. * @DSI_CMD_SET_RES_SWITCH: Resolution switch
  213. * @DSI_CMD_SET_POST_RES_SWITCH: Post resolution switch
  214. * @DSI_CMD_SET_CMD_TO_VID_SWITCH: Cmd to video mode switch
  215. * @DSI_CMD_SET_POST_CMD_TO_VID_SWITCH: Post cmd to vid switch
  216. * @DSI_CMD_SET_VID_TO_CMD_SWITCH: Video to cmd mode switch
  217. * @DSI_CMD_SET_POST_VID_TO_CMD_SWITCH: Post vid to cmd switch
  218. * @DSI_CMD_SET_PANEL_STATUS: Panel status
  219. * @DSI_CMD_SET_LP1: Low power mode 1
  220. * @DSI_CMD_SET_LP2: Low power mode 2
  221. * @DSI_CMD_SET_NOLP: Low power mode disable
  222. * @DSI_CMD_SET_PPS: DSC PPS command
  223. * @DSI_CMD_SET_ROI: Panel ROI update
  224. * @DSI_CMD_SET_TIMING_SWITCH: Timing switch
  225. * @DSI_CMD_SET_POST_TIMING_SWITCH: Post timing switch
  226. * @DSI_CMD_SET_QSYNC_ON Enable qsync mode
  227. * @DSI_CMD_SET_QSYNC_OFF Disable qsync mode
  228. * @DSI_CMD_SET_MAX
  229. */
  230. enum dsi_cmd_set_type {
  231. DSI_CMD_SET_PRE_ON = 0,
  232. DSI_CMD_SET_ON,
  233. DSI_CMD_SET_POST_ON,
  234. DSI_CMD_SET_PRE_OFF,
  235. DSI_CMD_SET_OFF,
  236. DSI_CMD_SET_POST_OFF,
  237. DSI_CMD_SET_PRE_RES_SWITCH,
  238. DSI_CMD_SET_RES_SWITCH,
  239. DSI_CMD_SET_POST_RES_SWITCH,
  240. DSI_CMD_SET_CMD_TO_VID_SWITCH,
  241. DSI_CMD_SET_POST_CMD_TO_VID_SWITCH,
  242. DSI_CMD_SET_VID_TO_CMD_SWITCH,
  243. DSI_CMD_SET_POST_VID_TO_CMD_SWITCH,
  244. DSI_CMD_SET_PANEL_STATUS,
  245. DSI_CMD_SET_LP1,
  246. DSI_CMD_SET_LP2,
  247. DSI_CMD_SET_NOLP,
  248. DSI_CMD_SET_PPS,
  249. DSI_CMD_SET_ROI,
  250. DSI_CMD_SET_TIMING_SWITCH,
  251. DSI_CMD_SET_POST_TIMING_SWITCH,
  252. DSI_CMD_SET_QSYNC_ON,
  253. DSI_CMD_SET_QSYNC_OFF,
  254. DSI_CMD_SET_MAX
  255. };
  256. /**
  257. * enum dsi_cmd_set_state - command set state
  258. * @DSI_CMD_SET_STATE_LP: dsi low power mode
  259. * @DSI_CMD_SET_STATE_HS: dsi high speed mode
  260. * @DSI_CMD_SET_STATE_MAX
  261. */
  262. enum dsi_cmd_set_state {
  263. DSI_CMD_SET_STATE_LP = 0,
  264. DSI_CMD_SET_STATE_HS,
  265. DSI_CMD_SET_STATE_MAX
  266. };
  267. /**
  268. * enum dsi_clk_gate_type - Type of clock to be gated.
  269. * @PIXEL_CLK: DSI pixel clock.
  270. * @BYTE_CLK: DSI byte clock.
  271. * @DSI_PHY: DSI PHY.
  272. * @DSI_CLK_ALL: All available DSI clocks
  273. * @DSI_CLK_NONE: None of the clocks should be gated
  274. */
  275. enum dsi_clk_gate_type {
  276. PIXEL_CLK = 1,
  277. BYTE_CLK = 2,
  278. DSI_PHY = 4,
  279. DSI_CLK_ALL = (PIXEL_CLK | BYTE_CLK | DSI_PHY),
  280. DSI_CLK_NONE = 8,
  281. };
  282. /**
  283. * enum dsi_phy_type - DSI phy types
  284. * @DSI_PHY_TYPE_DPHY:
  285. * @DSI_PHY_TYPE_CPHY:
  286. */
  287. enum dsi_phy_type {
  288. DSI_PHY_TYPE_DPHY,
  289. DSI_PHY_TYPE_CPHY
  290. };
  291. /**
  292. * enum dsi_te_mode - dsi te source
  293. * @DSI_TE_ON_DATA_LINK: TE read from DSI link
  294. * @DSI_TE_ON_EXT_PIN: TE signal on an external GPIO
  295. */
  296. enum dsi_te_mode {
  297. DSI_TE_ON_DATA_LINK = 0,
  298. DSI_TE_ON_EXT_PIN,
  299. };
  300. /**
  301. * enum dsi_video_traffic_mode - video mode pixel transmission type
  302. * @DSI_VIDEO_TRAFFIC_SYNC_PULSES: Non-burst mode with sync pulses.
  303. * @DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS: Non-burst mode with sync start events.
  304. * @DSI_VIDEO_TRAFFIC_BURST_MODE: Burst mode using sync start events.
  305. */
  306. enum dsi_video_traffic_mode {
  307. DSI_VIDEO_TRAFFIC_SYNC_PULSES = 0,
  308. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS,
  309. DSI_VIDEO_TRAFFIC_BURST_MODE,
  310. };
  311. /**
  312. * struct dsi_cmd_desc - description of a dsi command
  313. * @msg: dsi mipi msg packet
  314. * @last_command: indicates whether the cmd is the last one to send
  315. * @post_wait_ms: post wait duration
  316. */
  317. struct dsi_cmd_desc {
  318. struct mipi_dsi_msg msg;
  319. bool last_command;
  320. u32 post_wait_ms;
  321. };
  322. /**
  323. * struct dsi_panel_cmd_set - command set of the panel
  324. * @type: type of the command
  325. * @state: state of the command
  326. * @count: number of cmds
  327. * @ctrl_idx: index of the dsi control
  328. * @cmds: arry of cmds
  329. */
  330. struct dsi_panel_cmd_set {
  331. enum dsi_cmd_set_type type;
  332. enum dsi_cmd_set_state state;
  333. u32 count;
  334. u32 ctrl_idx;
  335. struct dsi_cmd_desc *cmds;
  336. };
  337. /**
  338. * struct dsi_mode_info - video mode information dsi frame
  339. * @h_active: Active width of one frame in pixels.
  340. * @h_back_porch: Horizontal back porch in pixels.
  341. * @h_sync_width: HSYNC width in pixels.
  342. * @h_front_porch: Horizontal fron porch in pixels.
  343. * @h_skew:
  344. * @h_sync_polarity: Polarity of HSYNC (false is active low).
  345. * @v_active: Active height of one frame in lines.
  346. * @v_back_porch: Vertical back porch in lines.
  347. * @v_sync_width: VSYNC width in lines.
  348. * @v_front_porch: Vertical front porch in lines.
  349. * @v_sync_polarity: Polarity of VSYNC (false is active low).
  350. * @refresh_rate: Refresh rate in Hz.
  351. * @clk_rate_hz: DSI bit clock rate per lane in Hz.
  352. * @min_dsi_clk_hz: Min DSI bit clock to transfer in vsync time.
  353. * @mdp_transfer_time_us: Specifies the mdp transfer time for command mode
  354. * panels in microseconds.
  355. * @dsi_transfer_time_us: Specifies dsi transfer time for command mode.
  356. * @dsc_enabled: DSC compression enabled.
  357. * @vdc_enabled: VDC compression enabled.
  358. * @dsc: DSC compression configuration.
  359. * @vdc: VDC compression configuration.
  360. * @roi_caps: Panel ROI capabilities.
  361. */
  362. struct dsi_mode_info {
  363. u32 h_active;
  364. u32 h_back_porch;
  365. u32 h_sync_width;
  366. u32 h_front_porch;
  367. u32 h_skew;
  368. bool h_sync_polarity;
  369. u32 v_active;
  370. u32 v_back_porch;
  371. u32 v_sync_width;
  372. u32 v_front_porch;
  373. bool v_sync_polarity;
  374. u32 refresh_rate;
  375. u64 clk_rate_hz;
  376. u64 min_dsi_clk_hz;
  377. u32 mdp_transfer_time_us;
  378. u32 dsi_transfer_time_us;
  379. bool dsc_enabled;
  380. bool vdc_enabled;
  381. struct msm_display_dsc_info *dsc;
  382. struct msm_display_vdc_info *vdc;
  383. struct msm_roi_caps roi_caps;
  384. };
  385. /**
  386. * struct dsi_split_link_config - Split Link Configuration
  387. * @split_link_enabled: Split Link Enabled.
  388. * @num_sublinks: Number of sublinks.
  389. * @lanes_per_sublink: Number of lanes per sublink.
  390. */
  391. struct dsi_split_link_config {
  392. bool split_link_enabled;
  393. u32 num_sublinks;
  394. u32 lanes_per_sublink;
  395. };
  396. /**
  397. * struct dsi_host_common_cfg - Host configuration common to video and cmd mode
  398. * @dst_format: Destination pixel format.
  399. * @data_lanes: Physical data lanes to be enabled.
  400. * @num_data_lanes: Number of physical data lanes.
  401. * @bpp: Number of bits per pixel.
  402. * @en_crc_check: Enable CRC checks.
  403. * @en_ecc_check: Enable ECC checks.
  404. * @te_mode: Source for TE signalling.
  405. * @mdp_cmd_trigger: MDP frame update trigger for command mode.
  406. * @dma_cmd_trigger: Command DMA trigger.
  407. * @cmd_trigger_stream: Command mode stream to trigger.
  408. * @swap_mode: DSI color swap mode.
  409. * @bit_swap_read: Is red color bit swapped.
  410. * @bit_swap_green: Is green color bit swapped.
  411. * @bit_swap_blue: Is blue color bit swapped.
  412. * @t_clk_post: Number of byte clock cycles that the transmitter shall
  413. * continue sending after last data lane has transitioned
  414. * to LP mode.
  415. * @t_clk_pre: Number of byte clock cycles that the high spped clock
  416. * shall be driven prior to data lane transitions from LP
  417. * to HS mode.
  418. * @ignore_rx_eot: Ignore Rx EOT packets if set to true.
  419. * @append_tx_eot: Append EOT packets for forward transmissions if set to
  420. * true.
  421. * @ext_bridge_mode: External bridge is connected.
  422. * @force_hs_clk_lane: Send continuous clock to the panel.
  423. * @dsi_split_link_config: Split Link Configuration.
  424. */
  425. struct dsi_host_common_cfg {
  426. enum dsi_pixel_format dst_format;
  427. enum dsi_data_lanes data_lanes;
  428. u8 num_data_lanes;
  429. u8 bpp;
  430. bool en_crc_check;
  431. bool en_ecc_check;
  432. enum dsi_te_mode te_mode;
  433. enum dsi_trigger_type mdp_cmd_trigger;
  434. enum dsi_trigger_type dma_cmd_trigger;
  435. u32 cmd_trigger_stream;
  436. enum dsi_color_swap_mode swap_mode;
  437. bool bit_swap_red;
  438. bool bit_swap_green;
  439. bool bit_swap_blue;
  440. u32 t_clk_post;
  441. u32 t_clk_pre;
  442. bool ignore_rx_eot;
  443. bool append_tx_eot;
  444. bool ext_bridge_mode;
  445. bool force_hs_clk_lane;
  446. struct dsi_split_link_config split_link;
  447. };
  448. /**
  449. * struct dsi_video_engine_cfg - DSI video engine configuration
  450. * @last_line_interleave_en: Allow command mode op interleaved on last line of
  451. * video stream.
  452. * @pulse_mode_hsa_he: Send HSA and HE following VS/VE packet if set to
  453. * true.
  454. * @hfp_lp11_en: Enter low power stop mode (LP-11) during HFP.
  455. * @hbp_lp11_en: Enter low power stop mode (LP-11) during HBP.
  456. * @hsa_lp11_en: Enter low power stop mode (LP-11) during HSA.
  457. * @eof_bllp_lp11_en: Enter low power stop mode (LP-11) during BLLP of
  458. * last line of a frame.
  459. * @bllp_lp11_en: Enter low power stop mode (LP-11) during BLLP.
  460. * @traffic_mode: Traffic mode for video stream.
  461. * @vc_id: Virtual channel identifier.
  462. * @dma_sched_line: Line number, after vactive end, at which command dma
  463. * needs to be triggered.
  464. */
  465. struct dsi_video_engine_cfg {
  466. bool last_line_interleave_en;
  467. bool pulse_mode_hsa_he;
  468. bool hfp_lp11_en;
  469. bool hbp_lp11_en;
  470. bool hsa_lp11_en;
  471. bool eof_bllp_lp11_en;
  472. bool bllp_lp11_en;
  473. bool force_clk_lane_hs;
  474. enum dsi_video_traffic_mode traffic_mode;
  475. u32 vc_id;
  476. u32 dma_sched_line;
  477. };
  478. /**
  479. * struct dsi_cmd_engine_cfg - DSI command engine configuration
  480. * @max_cmd_packets_interleave Maximum number of command mode RGB packets to
  481. * send with in one horizontal blanking period
  482. * of the video mode frame.
  483. * @wr_mem_start: DCS command for write_memory_start.
  484. * @wr_mem_continue: DCS command for write_memory_continue.
  485. * @insert_dcs_command: Insert DCS command as first byte of payload
  486. * of the pixel data.
  487. */
  488. struct dsi_cmd_engine_cfg {
  489. u32 max_cmd_packets_interleave;
  490. u32 wr_mem_start;
  491. u32 wr_mem_continue;
  492. bool insert_dcs_command;
  493. };
  494. /**
  495. * struct dsi_host_config - DSI host configuration parameters.
  496. * @panel_mode: Operation mode for panel (video or cmd mode).
  497. * @common_config: Host configuration common to both Video and Cmd mode.
  498. * @video_engine: Video engine configuration if panel is in video mode.
  499. * @cmd_engine: Cmd engine configuration if panel is in cmd mode.
  500. * @esc_clk_rate_khz: Esc clock frequency in Hz.
  501. * @bit_clk_rate_hz: Bit clock frequency in Hz.
  502. * @bit_clk_rate_hz_override: DSI bit clk rate override from dt/sysfs.
  503. * @video_timing: Video timing information of a frame.
  504. * @lane_map: Mapping between logical and physical lanes.
  505. */
  506. struct dsi_host_config {
  507. enum dsi_op_mode panel_mode;
  508. struct dsi_host_common_cfg common_config;
  509. union {
  510. struct dsi_video_engine_cfg video_engine;
  511. struct dsi_cmd_engine_cfg cmd_engine;
  512. } u;
  513. u64 esc_clk_rate_hz;
  514. u64 bit_clk_rate_hz;
  515. u64 bit_clk_rate_hz_override;
  516. struct dsi_mode_info video_timing;
  517. struct dsi_lane_map lane_map;
  518. };
  519. /**
  520. * struct dsi_display_mode_priv_info - private mode info that will be attached
  521. * with each drm mode
  522. * @cmd_sets: Command sets of the mode
  523. * @phy_timing_val: Phy timing values
  524. * @phy_timing_len: Phy timing array length
  525. * @panel_jitter: Panel jitter for RSC backoff
  526. * @panel_prefill_lines: Panel prefill lines for RSC
  527. * @mdp_transfer_time_us: Specifies the mdp transfer time for command mode
  528. * panels in microseconds.
  529. * @dsi_transfer_time_us: Specifies the dsi transfer time for cmd panels.
  530. * @clk_rate_hz: DSI bit clock per lane in hz.
  531. * @min_dsi_clk_hz: Min dsi clk per lane to transfer frame in vsync time.
  532. * @topology: Topology selected for the panel
  533. * @dsc: DSC compression info
  534. * @vdc: VDC compression info
  535. * @dsc_enabled: DSC compression enabled
  536. * @vdc_enabled: VDC compression enabled
  537. * @roi_caps: Panel ROI capabilities
  538. */
  539. struct dsi_display_mode_priv_info {
  540. struct dsi_panel_cmd_set cmd_sets[DSI_CMD_SET_MAX];
  541. u32 *phy_timing_val;
  542. u32 phy_timing_len;
  543. u32 panel_jitter_numer;
  544. u32 panel_jitter_denom;
  545. u32 panel_prefill_lines;
  546. u32 mdp_transfer_time_us;
  547. u32 dsi_transfer_time_us;
  548. u64 clk_rate_hz;
  549. u64 min_dsi_clk_hz;
  550. struct msm_display_topology topology;
  551. struct msm_display_dsc_info dsc;
  552. struct msm_display_vdc_info vdc;
  553. bool dsc_enabled;
  554. bool vdc_enabled;
  555. struct msm_roi_caps roi_caps;
  556. };
  557. /**
  558. * struct dsi_display_mode - specifies mode for dsi display
  559. * @timing: Timing parameters for the panel.
  560. * @pixel_clk_khz: Pixel clock in Khz.
  561. * @dsi_mode_flags: Flags to signal other drm components via private flags
  562. * @panel_mode: Panel mode
  563. * @priv_info: Mode private info
  564. */
  565. struct dsi_display_mode {
  566. struct dsi_mode_info timing;
  567. u32 pixel_clk_khz;
  568. u32 dsi_mode_flags;
  569. enum dsi_op_mode panel_mode;
  570. struct dsi_display_mode_priv_info *priv_info;
  571. };
  572. /**
  573. * struct dsi_rect - dsi rectangle representation
  574. * Note: sde_rect is also using u16, this must be maintained for memcpy
  575. */
  576. struct dsi_rect {
  577. u16 x;
  578. u16 y;
  579. u16 w;
  580. u16 h;
  581. };
  582. /**
  583. * dsi_rect_intersect - intersect two rectangles
  584. * @r1: first rectangle
  585. * @r2: scissor rectangle
  586. * @result: result rectangle, all 0's on no intersection found
  587. */
  588. void dsi_rect_intersect(const struct dsi_rect *r1,
  589. const struct dsi_rect *r2,
  590. struct dsi_rect *result);
  591. /**
  592. * dsi_rect_is_equal - compares two rects
  593. * @r1: rect value to compare
  594. * @r2: rect value to compare
  595. *
  596. * Returns true if the rects are same
  597. */
  598. static inline bool dsi_rect_is_equal(struct dsi_rect *r1,
  599. struct dsi_rect *r2)
  600. {
  601. return r1->x == r2->x && r1->y == r2->y && r1->w == r2->w &&
  602. r1->h == r2->h;
  603. }
  604. struct dsi_event_cb_info {
  605. uint32_t event_idx;
  606. void *event_usr_ptr;
  607. int (*event_cb)(void *event_usr_ptr,
  608. uint32_t event_idx, uint32_t instance_idx,
  609. uint32_t data0, uint32_t data1,
  610. uint32_t data2, uint32_t data3);
  611. };
  612. /**
  613. * enum dsi_error_status - various dsi errors
  614. * @DSI_FIFO_OVERFLOW: DSI FIFO Overflow error
  615. * @DSI_FIFO_UNDERFLOW: DSI FIFO Underflow error
  616. * @DSI_LP_Rx_TIMEOUT: DSI LP/RX Timeout error
  617. * @DSI_PLL_UNLOCK_ERR: DSI PLL unlock error
  618. */
  619. enum dsi_error_status {
  620. DSI_FIFO_OVERFLOW = 1,
  621. DSI_FIFO_UNDERFLOW,
  622. DSI_LP_Rx_TIMEOUT,
  623. DSI_PLL_UNLOCK_ERR,
  624. DSI_ERR_INTR_ALL,
  625. };
  626. /* structure containing the delays required for dynamic clk */
  627. struct dsi_dyn_clk_delay {
  628. u32 pipe_delay;
  629. u32 pipe_delay2;
  630. u32 pll_delay;
  631. };
  632. /* dynamic refresh control bits */
  633. enum dsi_dyn_clk_control_bits {
  634. DYN_REFRESH_INTF_SEL = 1,
  635. DYN_REFRESH_SYNC_MODE,
  636. DYN_REFRESH_SW_TRIGGER,
  637. DYN_REFRESH_SWI_CTRL,
  638. };
  639. /* convert dsi pixel format into bits per pixel */
  640. static inline int dsi_pixel_format_to_bpp(enum dsi_pixel_format fmt)
  641. {
  642. switch (fmt) {
  643. case DSI_PIXEL_FORMAT_RGB888:
  644. case DSI_PIXEL_FORMAT_MAX:
  645. return 24;
  646. case DSI_PIXEL_FORMAT_RGB666:
  647. case DSI_PIXEL_FORMAT_RGB666_LOOSE:
  648. return 18;
  649. case DSI_PIXEL_FORMAT_RGB565:
  650. return 16;
  651. case DSI_PIXEL_FORMAT_RGB111:
  652. return 3;
  653. case DSI_PIXEL_FORMAT_RGB332:
  654. return 8;
  655. case DSI_PIXEL_FORMAT_RGB444:
  656. return 12;
  657. }
  658. return 24;
  659. }
  660. static inline u64 dsi_h_active_dce(struct dsi_mode_info *mode)
  661. {
  662. u64 h_active = 0;
  663. if (mode->dsc_enabled && mode->dsc)
  664. h_active = mode->dsc->pclk_per_line;
  665. else if (mode->vdc_enabled && mode->vdc)
  666. h_active = mode->vdc->pclk_per_line;
  667. else
  668. h_active = mode->h_active;
  669. return h_active;
  670. }
  671. static inline u64 dsi_h_total_dce(struct dsi_mode_info *mode)
  672. {
  673. return dsi_h_active_dce(mode) + mode->h_back_porch +
  674. mode->h_sync_width + mode->h_front_porch;
  675. }
  676. #endif /* _DSI_DEFS_H_ */