443ca7a00e
Add support for BT Soundwire port configurations. Add support for flow control modes for fractional channel rates. Configure slave side data ports for flow controls modes. Fix the direction adn offset1 fields for Tx ports on BT Soundwire. When the flow control mode is not required, update the slave configuration accordingly. Sample Interval HIGH field in slave port controls needs to be reset to zero when Sample Interval value is less than 255. Avoid clock stop mode for bt swr slave during runtime suspend call. In case of fractional sampling rates, additional offset bits need to be added between samples to carry flow control information. Change-Id: If023946f62c5157119836cf43e8542cfd6e0ce16 Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
77 lines
4.9 KiB
C
77 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, 2018-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _SWR_SLAVE_REGISTERS_H
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#define _SWR_SLAVE_REGISTERS_H
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#define SWRS_BASE 0x00
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#define SWRS_SCP_INT_STATUS_1 (SWRS_BASE+0x0040)
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#define SWRS_SCP_INT_CLEAR_1 (SWRS_BASE+0x0040)
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#define SWRS_SCP_INT_MASK_1 (SWRS_BASE+0x0041)
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#define SWRS_SCP_INT_STATUS_2 (SWRS_BASE+0x0042)
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#define SWRS_SCP_INT_STATUS_3 (SWRS_BASE+0x0043)
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#define SWRS_SCP_CONTROL (SWRS_BASE+0x0044)
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#define SWRS_SCP_STATUS (SWRS_BASE+0x0044)
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#define SWRS_SCP_CLOCK_STOP_CONTROL (SWRS_BASE+0x0045)
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#define SWRS_SCP_DEV_NUMBER (SWRS_BASE+0x0046)
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#define SWRS_SCP_KEEPER_EN (SWRS_BASE+0x004A)
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#define SWRS_SCP_DEVICE_ID_0 (SWRS_BASE+0x0050)
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#define SWRS_SCP_DEVICE_ID_1 (SWRS_BASE+0x0051)
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#define SWRS_SCP_DEVICE_ID_2 (SWRS_BASE+0x0052)
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#define SWRS_SCP_DEVICE_ID_3 (SWRS_BASE+0x0053)
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#define SWRS_SCP_DEVICE_ID_4 (SWRS_BASE+0x0054)
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#define SWRS_SCP_DEVICE_ID_5 (SWRS_BASE+0x0055)
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#define SWRS_SCP_FRAME_CTRL_BANK(m) (SWRS_BASE+0x0060+0x10*m)
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#define SWRS_SCP_IMPDEF_SWR_INTERRUPT_DETECT_TYPE (SWRS_BASE+0x00C8)
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#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (SWRS_BASE+0x00E0+0x10*m)
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#define SWRS_DP_INT_STATUS(n) (SWRS_BASE+0x100+0x0100*n)
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#define SWRS_DP_INT_STATUS_MASK(n) (SWRS_BASE+0x101+0x100*n)
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#define SWRS_DP_PORT_CONTROL(n) (SWRS_BASE+0x102+0x100*n)
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#define SWRS_DP_BLOCK_CONTROL_1(n) (SWRS_BASE+0x103+0x100*n)
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#define SWRS_DP_PREPARE_STATUS(n) (SWRS_BASE+0x104+0x100*n)
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#define SWRS_DP_PREPARE_CONTROL(n) (SWRS_BASE+0x105+0x100*n)
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#define SWRS_DP_CHANNEL_ENABLE_BANK(n, m) (SWRS_BASE+0x120+0x100*n+0x10*m)
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#define SWRS_DP_BLOCK_CONTROL_2_BANK(n, m) (SWRS_BASE+0x121+0x100*n+0x10*m)
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#define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE+0x122+0x100*n+0x10*m)
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#define SWRS_DP_SAMPLE_CONTROL_2_BANK(n, m) (SWRS_BASE+0x123+0x100*n+0x10*m)
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#define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE+0x124+0x100*n+0x10*m)
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#define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE+0x125+0x100*n+0x10*m)
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#define SWRS_DP_HCONTROL_BANK(n, m) (SWRS_BASE+0x126+0x100*n+0x10*m)
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#define SWRS_DP_BLOCK_CONTROL_3_BANK(n, m) (SWRS_BASE+0x127+0x100*n+0x10*m)
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#define SWRS_DP_LANE_CONTROL_BANK(n, m) (SWRS_BASE+0x128+0x100*n+0x10*m)
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#define SWRS_DP_ALL_INT_STATUS (SWRS_BASE+0x0F00)
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#define SWRS_DP_ALL_INT_STATUS_MASK (SWRS_BASE+0x0F01)
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#define SWRS_DP_ALL_PORT_CONTROL (SWRS_BASE+0x0F02)
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#define SWRS_DP_ALL_BLOCK_CONTROL_1 (SWRS_BASE+0x0F03)
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#define SWRS_DP_ALL_PREPARE_STATUS (SWRS_BASE+0x0F04)
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#define SWRS_DP_ALL_PREPARE_CONTROL (SWRS_BASE+0x0F05)
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#define SWRS_DP_ALL_CHANNEL_ENABLE_BANK(m) (SWRS_BASE+0x0F20+0x10*m)
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#define SWRS_DP_ALL_BLOCK_CONTROL_2_BANK(m) (SWRS_BASE+0x0F21+0x10*m)
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#define SWRS_DP_ALL_SAMPLE_CONTROL_1_BANK(m) (SWRS_BASE+0x0F22+0x10*m)
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#define SWRS_DP_ALL_SAMPLE_CONTROL_2_BANK(m) (SWRS_BASE+0x0F23+0x10*m)
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#define SWRS_DP_ALL_OFFSET_CONTROL_1_BANK(m) (SWRS_BASE+0x0F24+0x10*m)
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#define SWRS_DP_ALL_OFFSET_CONTROL_2_BANK(m) (SWRS_BASE+0x0F25+0x10*m)
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#define SWRS_DP_ALL_HCONTROL_BANK(m) (SWRS_BASE+0x0F26+0x10*m)
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#define SWRS_DP_ALL_BLOCK_CONTROL_3_BANK(m) (SWRS_BASE+0x0F27+0x10*m)
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#define SWRS_DP_ALL_LANE_CONTROL_BANK(m) (SWRS_BASE+0x0F28+0x10*m)
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#define SWRS_COMP_HW_VERSION_MAJOR (SWRS_BASE+0x2000)
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#define SWRS_COMP_HW_VERSION_MINOR (SWRS_BASE+0x2001)
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#define SWRS_COMP_HW_VERSION_STEP (SWRS_BASE+0x2002)
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#define SWRS_COMP_STATUS (SWRS_BASE+0x2003)
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#define SWRS_COMP_POWER_CFG (SWRS_BASE+0x2004)
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#define SWRS_COMP_FEATURE_CFG (SWRS_BASE+0x2005)
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#define SWRS_COMP_PARAMS (SWRS_BASE+0x2006)
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#define SWRS_TEST_BUS_CTL (SWRS_BASE+0x2007)
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#define SWRS_TEST_BUS_STATUS_LOW (SWRS_BASE+0x200A)
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#define SWRS_TEST_BUS_STATUS_HIGH (SWRS_BASE+0x200B)
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#define SWRS_LOOPBACK_CTL (SWRS_BASE+0x2009)
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#define SWRS_DPn_FEATURE_EN(n) (SWRS_BASE+0x000001D4+0x100*n)
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#define SWRS_DPn_FLOW_CTRL_N_REPEAT_PERIOD(n) (SWRS_BASE+0x000001CC+0x100*n)
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#define SWRS_DPn_FLOW_CTRL_M_VALID_SAMPLE(n) (SWRS_BASE+0x000001C4+0x100*n)
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#endif /* _SWR_SLAVE_REGISTERS_H */
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