wsa884x.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/printk.h>
  11. #include <linux/bitops.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/delay.h>
  15. #include <linux/kernel.h>
  16. #include <linux/gpio.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/regmap.h>
  20. #include <linux/debugfs.h>
  21. #include <soc/soundwire.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/tlv.h>
  27. #include <asoc/msm-cdc-pinctrl.h>
  28. #include <asoc/msm-cdc-supply.h>
  29. #include "wsa884x.h"
  30. #include "internal.h"
  31. #include "asoc/bolero-slave-internal.h"
  32. #include <linux/qti-regmap-debugfs.h>
  33. #define T1_TEMP -10
  34. #define T2_TEMP 150
  35. #define LOW_TEMP_THRESHOLD 5
  36. #define HIGH_TEMP_THRESHOLD 45
  37. #define TEMP_INVALID 0xFFFF
  38. #define WSA884X_TEMP_RETRY 3
  39. #define MAX_NAME_LEN 40
  40. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  41. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  42. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  43. SNDRV_PCM_RATE_384000)
  44. /* Fractional Rates */
  45. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  46. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  47. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  48. SNDRV_PCM_FMTBIT_S24_LE |\
  49. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  50. #define REG_FIELD_VALUE(register_name, field_name, value) \
  51. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  52. value << FIELD_SHIFT(register_name, field_name)
  53. struct wsa_temp_register {
  54. u8 d1_msb;
  55. u8 d1_lsb;
  56. u8 d2_msb;
  57. u8 d2_lsb;
  58. u8 dmeas_msb;
  59. u8 dmeas_lsb;
  60. };
  61. enum {
  62. COMP_OFFSET0,
  63. COMP_OFFSET1,
  64. COMP_OFFSET2,
  65. COMP_OFFSET3,
  66. COMP_OFFSET4,
  67. };
  68. enum {
  69. EXT_ABOVE_3S,
  70. CONFIG_1S,
  71. CONFIG_2S,
  72. CONFIG_3S,
  73. EXT_1S,
  74. EXT_2S,
  75. EXT_3S,
  76. };
  77. enum {
  78. WSA_4OHMS = 0,
  79. WSA_6OHMS,
  80. WSA_8OHMS,
  81. WSA_32OHMS,
  82. WSA_MAXOHMS,
  83. };
  84. /* Aux gain from system gain */
  85. static const u8 pa_aux_no_comp[G_MAX_DB] = {
  86. PA_AUX_18_DB, /* G_21_DB */
  87. PA_AUX_18_DB, /* G_19P5_DB */
  88. PA_AUX_18_DB, /* G_18_DB */
  89. PA_AUX_18_DB, /* G_16P5_DB */
  90. PA_AUX_18_DB, /* G_15_DB */
  91. PA_AUX_12_DB, /* G_13P5_DB */
  92. PA_AUX_12_DB, /* G_12_DB */
  93. PA_AUX_12_DB, /* G_10P5_DB */
  94. PA_AUX_7P5_DB, /* G_9_DB */
  95. PA_AUX_7P5_DB, /* G_7P5_DB */
  96. PA_AUX_7P5_DB, /* G_6_DB */
  97. PA_AUX_7P5_DB, /* G_4P5_DB */
  98. PA_AUX_0_DB, /* G_3_DB */
  99. PA_AUX_0_DB, /* G_1P5_DB */
  100. PA_AUX_0_DB, /* G_0_DB */
  101. PA_AUX_M1P5_DB,/* G_M1P5_DB */
  102. PA_AUX_M3_DB, /* G_M3_DB */
  103. PA_AUX_M4P5_DB,/* G_M4P5_DB */
  104. PA_AUX_M6_DB /* G_M6_DB */
  105. };
  106. /*
  107. * Isense data indexed by system_gain and rload
  108. * WSA_4OHMS, WSA_6OHMS, WSA_8OHMS, WSA_32OHMS
  109. */
  110. static const u8 isense_gain_data[G_MAX_DB][WSA_MAXOHMS] = {
  111. {ISENSE_6_DB, ISENSE_6_DB, ISENSE_12_DB, ISENSE_18_DB}, /*G_21_DB */
  112. {ISENSE_6_DB, ISENSE_6_DB, ISENSE_12_DB, ISENSE_18_DB}, /*G_19P5_DB */
  113. {ISENSE_6_DB, ISENSE_6_DB, ISENSE_15_DB, ISENSE_18_DB}, /*G_18_DB */
  114. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_15_DB, ISENSE_18_DB}, /*G_16P5_DB */
  115. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_15_DB */
  116. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_13P5_DB */
  117. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_12_DB */
  118. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_10P5_DB */
  119. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_9_DB */
  120. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_7P5_DB */
  121. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_6_DB */
  122. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_4P5_DB */
  123. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_3_DB */
  124. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_1P5_DB */
  125. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_0_DB */
  126. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M1P5_DB */
  127. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M3_DB */
  128. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M4P5_DB */
  129. {ISENSE_12_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M6_DB */
  130. };
  131. /* Vsense gain from system gain */
  132. static const u8 vsense_gain_data[G_MAX_DB] = {
  133. VSENSE_M24_DB, /* G_21_DB */
  134. VSENSE_M24_DB, /* G_19P5_DB */
  135. VSENSE_M21_DB, /* G_18_DB */
  136. VSENSE_M21_DB, /* G_16P5_DB */
  137. VSENSE_M18_DB, /* G_15_DB */
  138. VSENSE_M18_DB, /* G_13P5_DB */
  139. VSENSE_M15_DB, /* G_12_DB */
  140. VSENSE_M15_DB, /* G_10P5_DB */
  141. VSENSE_M12_DB, /* G_9_DB */
  142. VSENSE_M12_DB, /* G_7P5_DB */
  143. VSENSE_M12_DB, /* G_6_DB */
  144. VSENSE_M12_DB, /* G_4P5_DB */
  145. VSENSE_M12_DB, /* G_3_DB */
  146. VSENSE_M12_DB, /* G_1P5_DB */
  147. VSENSE_M12_DB, /* G_0_DB */
  148. VSENSE_M12_DB, /* G_M1P5_DB */
  149. VSENSE_M12_DB, /* G_M3_DB */
  150. VSENSE_M12_DB, /* G_M4P5_DB */
  151. VSENSE_M12_DB /* G_M6_DB */
  152. };
  153. struct wsa_reg_mask_val {
  154. u16 reg;
  155. u8 mask;
  156. u8 val;
  157. };
  158. static const struct wsa_reg_mask_val reg_init[] = {
  159. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  160. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  161. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  162. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  163. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  164. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  165. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  166. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  167. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  168. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  169. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  170. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  171. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  172. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  173. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  174. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  175. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  176. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  177. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  178. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  179. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  180. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  181. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  182. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  183. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  184. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  185. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  186. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  187. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  188. };
  189. static int wsa884x_handle_post_irq(void *data);
  190. static int wsa884x_get_temperature(struct snd_soc_component *component,
  191. int *temp);
  192. enum {
  193. WSA8840 = 0,
  194. WSA8845 = 5,
  195. WSA8845H = 0xC,
  196. };
  197. enum {
  198. SPKR_STATUS = 0,
  199. WSA_SUPPLIES_LPM_MODE,
  200. SPKR_ADIE_LB,
  201. };
  202. enum {
  203. WSA884X_IRQ_INT_SAF2WAR = 0,
  204. WSA884X_IRQ_INT_WAR2SAF,
  205. WSA884X_IRQ_INT_DISABLE,
  206. WSA884X_IRQ_INT_OCP,
  207. WSA884X_IRQ_INT_CLIP,
  208. WSA884X_IRQ_INT_PDM_WD,
  209. WSA884X_IRQ_INT_CLK_WD,
  210. WSA884X_IRQ_INT_INTR_PIN,
  211. WSA884X_IRQ_INT_UVLO,
  212. WSA884X_IRQ_INT_PA_ON_ERR,
  213. WSA884X_NUM_IRQS,
  214. };
  215. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  216. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  217. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  218. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  219. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  220. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  221. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  222. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  223. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  224. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  225. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  226. };
  227. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  228. .name = "wsa884x",
  229. .irqs = wsa884x_irqs,
  230. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  231. .num_regs = 2,
  232. .status_base = WSA884X_INTR_STATUS0,
  233. .mask_base = WSA884X_INTR_MASK0,
  234. .type_base = WSA884X_INTR_LEVEL0,
  235. .ack_base = WSA884X_INTR_CLEAR0,
  236. .use_ack = 1,
  237. .runtime_pm = false,
  238. .handle_post_irq = wsa884x_handle_post_irq,
  239. .irq_drv_data = NULL,
  240. };
  241. static int wsa884x_handle_post_irq(void *data)
  242. {
  243. struct wsa884x_priv *wsa884x = data;
  244. u32 sts1 = 0, sts2 = 0;
  245. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  246. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  247. wsa884x->swr_slave->slave_irq_pending =
  248. ((sts1 || sts2) ? true : false);
  249. return IRQ_HANDLED;
  250. }
  251. #ifdef CONFIG_DEBUG_FS
  252. static int codec_debug_open(struct inode *inode, struct file *file)
  253. {
  254. file->private_data = inode->i_private;
  255. return 0;
  256. }
  257. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  258. {
  259. char *token;
  260. int base, cnt;
  261. token = strsep(&buf, " ");
  262. for (cnt = 0; cnt < num_of_par; cnt++) {
  263. if (token) {
  264. if ((token[1] == 'x') || (token[1] == 'X'))
  265. base = 16;
  266. else
  267. base = 10;
  268. if (kstrtou32(token, base, &param1[cnt]) != 0)
  269. return -EINVAL;
  270. token = strsep(&buf, " ");
  271. } else {
  272. return -EINVAL;
  273. }
  274. }
  275. return 0;
  276. }
  277. static bool is_swr_slave_reg_readable(int reg)
  278. {
  279. int ret = true;
  280. if (((reg > 0x46) && (reg < 0x4A)) ||
  281. ((reg > 0x4A) && (reg < 0x50)) ||
  282. ((reg > 0x55) && (reg < 0xD0)) ||
  283. ((reg > 0xD0) && (reg < 0xE0)) ||
  284. ((reg > 0xE0) && (reg < 0xF0)) ||
  285. ((reg > 0xF0) && (reg < 0x100)) ||
  286. ((reg > 0x105) && (reg < 0x120)) ||
  287. ((reg > 0x205) && (reg < 0x220)) ||
  288. ((reg > 0x305) && (reg < 0x320)) ||
  289. ((reg > 0x405) && (reg < 0x420)) ||
  290. ((reg > 0x128) && (reg < 0x130)) ||
  291. ((reg > 0x228) && (reg < 0x230)) ||
  292. ((reg > 0x328) && (reg < 0x330)) ||
  293. ((reg > 0x428) && (reg < 0x430)) ||
  294. ((reg > 0x138) && (reg < 0x205)) ||
  295. ((reg > 0x238) && (reg < 0x305)) ||
  296. ((reg > 0x338) && (reg < 0x405)) ||
  297. ((reg > 0x405) && (reg < 0xF00)) ||
  298. ((reg > 0xF05) && (reg < 0xF20)) ||
  299. ((reg > 0xF25) && (reg < 0xF30)) ||
  300. ((reg > 0xF35) && (reg < 0x2000)))
  301. ret = false;
  302. return ret;
  303. }
  304. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  305. size_t count, loff_t *ppos)
  306. {
  307. int i, reg_val, len;
  308. ssize_t total = 0;
  309. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  310. if (!ubuf || !ppos)
  311. return 0;
  312. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  313. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  314. if (!is_swr_slave_reg_readable(i))
  315. continue;
  316. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  317. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  318. (reg_val & 0xFF));
  319. if (len < 0) {
  320. pr_err("%s: fail to fill the buffer\n", __func__);
  321. total = -EFAULT;
  322. goto copy_err;
  323. }
  324. if ((total + len) >= count - 1)
  325. break;
  326. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  327. pr_err("%s: fail to copy reg dump\n", __func__);
  328. total = -EFAULT;
  329. goto copy_err;
  330. }
  331. total += len;
  332. *ppos += len;
  333. }
  334. copy_err:
  335. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  336. return total;
  337. }
  338. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  339. size_t count, loff_t *ppos)
  340. {
  341. struct swr_device *pdev;
  342. if (!count || !file || !ppos || !ubuf)
  343. return -EINVAL;
  344. pdev = file->private_data;
  345. if (!pdev)
  346. return -EINVAL;
  347. if (*ppos < 0)
  348. return -EINVAL;
  349. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  350. }
  351. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  352. size_t count, loff_t *ppos)
  353. {
  354. char lbuf[SWR_SLV_RD_BUF_LEN];
  355. struct swr_device *pdev = NULL;
  356. struct wsa884x_priv *wsa884x = NULL;
  357. if (!count || !file || !ppos || !ubuf)
  358. return -EINVAL;
  359. pdev = file->private_data;
  360. if (!pdev)
  361. return -EINVAL;
  362. wsa884x = swr_get_dev_data(pdev);
  363. if (!wsa884x)
  364. return -EINVAL;
  365. if (*ppos < 0)
  366. return -EINVAL;
  367. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  368. (wsa884x->read_data & 0xFF));
  369. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  370. strnlen(lbuf, 7));
  371. }
  372. static ssize_t codec_debug_peek_write(struct file *file,
  373. const char __user *ubuf, size_t cnt, loff_t *ppos)
  374. {
  375. char lbuf[SWR_SLV_WR_BUF_LEN];
  376. int rc = 0;
  377. u32 param[5];
  378. struct swr_device *pdev = NULL;
  379. struct wsa884x_priv *wsa884x = NULL;
  380. if (!cnt || !file || !ppos || !ubuf)
  381. return -EINVAL;
  382. pdev = file->private_data;
  383. if (!pdev)
  384. return -EINVAL;
  385. wsa884x = swr_get_dev_data(pdev);
  386. if (!wsa884x)
  387. return -EINVAL;
  388. if (*ppos < 0)
  389. return -EINVAL;
  390. if (cnt > sizeof(lbuf) - 1)
  391. return -EINVAL;
  392. rc = copy_from_user(lbuf, ubuf, cnt);
  393. if (rc)
  394. return -EFAULT;
  395. lbuf[cnt] = '\0';
  396. rc = get_parameters(lbuf, param, 1);
  397. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  398. return -EINVAL;
  399. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  400. if (rc == 0)
  401. rc = cnt;
  402. else
  403. pr_err("%s: rc = %d\n", __func__, rc);
  404. return rc;
  405. }
  406. static ssize_t codec_debug_write(struct file *file,
  407. const char __user *ubuf, size_t cnt, loff_t *ppos)
  408. {
  409. char lbuf[SWR_SLV_WR_BUF_LEN];
  410. int rc = 0;
  411. u32 param[5];
  412. struct swr_device *pdev;
  413. if (!file || !ppos || !ubuf)
  414. return -EINVAL;
  415. pdev = file->private_data;
  416. if (!pdev)
  417. return -EINVAL;
  418. if (cnt > sizeof(lbuf) - 1)
  419. return -EINVAL;
  420. rc = copy_from_user(lbuf, ubuf, cnt);
  421. if (rc)
  422. return -EFAULT;
  423. lbuf[cnt] = '\0';
  424. rc = get_parameters(lbuf, param, 2);
  425. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  426. (param[1] <= 0xFF) && (rc == 0)))
  427. return -EINVAL;
  428. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  429. if (rc == 0)
  430. rc = cnt;
  431. else
  432. pr_err("%s: rc = %d\n", __func__, rc);
  433. return rc;
  434. }
  435. static const struct file_operations codec_debug_write_ops = {
  436. .open = codec_debug_open,
  437. .write = codec_debug_write,
  438. };
  439. static const struct file_operations codec_debug_read_ops = {
  440. .open = codec_debug_open,
  441. .read = codec_debug_read,
  442. .write = codec_debug_peek_write,
  443. };
  444. static const struct file_operations codec_debug_dump_ops = {
  445. .open = codec_debug_open,
  446. .read = codec_debug_dump,
  447. };
  448. #endif
  449. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  450. {
  451. mutex_lock(&wsa884x->res_lock);
  452. regcache_mark_dirty(wsa884x->regmap);
  453. regcache_sync(wsa884x->regmap);
  454. mutex_unlock(&wsa884x->res_lock);
  455. }
  456. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  457. {
  458. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  459. __func__, irq);
  460. return IRQ_HANDLED;
  461. }
  462. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  463. {
  464. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  465. __func__, irq);
  466. return IRQ_HANDLED;
  467. }
  468. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  469. {
  470. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  471. __func__, irq);
  472. return IRQ_HANDLED;
  473. }
  474. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  475. {
  476. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  477. __func__, irq);
  478. return IRQ_HANDLED;
  479. }
  480. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  481. {
  482. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  483. __func__, irq);
  484. return IRQ_HANDLED;
  485. }
  486. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  487. {
  488. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  489. __func__, irq);
  490. return IRQ_HANDLED;
  491. }
  492. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  493. {
  494. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  495. __func__, irq);
  496. return IRQ_HANDLED;
  497. }
  498. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  499. {
  500. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  501. __func__, irq);
  502. return IRQ_HANDLED;
  503. }
  504. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  505. {
  506. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  507. __func__, irq);
  508. return IRQ_HANDLED;
  509. }
  510. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  511. {
  512. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  513. struct wsa884x_priv *wsa884x = data;
  514. struct snd_soc_component *component = NULL;
  515. if (!wsa884x)
  516. return IRQ_NONE;
  517. component = wsa884x->component;
  518. if (!component)
  519. return IRQ_NONE;
  520. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  521. & 0x1F);
  522. if (pa_fsm_sta)
  523. pa_fsm_err = snd_soc_component_read(component,
  524. WSA884X_PA_FSM_ERR_COND0);
  525. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  526. __func__, irq);
  527. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  528. 0x10, 0x00);
  529. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  530. 0x10, 0x10);
  531. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  532. 0x10, 0x00);
  533. return IRQ_HANDLED;
  534. }
  535. static const char * const wsa_dev_mode_text[] = {
  536. "speaker", "receiver"
  537. };
  538. enum {
  539. SPEAKER,
  540. RECEIVER,
  541. };
  542. static const struct soc_enum wsa_dev_mode_enum =
  543. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
  544. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  545. struct snd_ctl_elem_value *ucontrol)
  546. {
  547. struct snd_soc_component *component =
  548. snd_soc_kcontrol_component(kcontrol);
  549. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  550. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  551. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  552. wsa884x->dev_mode);
  553. return 0;
  554. }
  555. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  556. struct snd_ctl_elem_value *ucontrol)
  557. {
  558. struct snd_soc_component *component =
  559. snd_soc_kcontrol_component(kcontrol);
  560. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  561. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  562. __func__, ucontrol->value.integer.value[0]);
  563. wsa884x->dev_mode = ucontrol->value.integer.value[0];
  564. return 0;
  565. }
  566. static const char * const wsa_pa_gain_text[] = {
  567. "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB", "G_12_DB", "G_10P5_DB",
  568. "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB",
  569. "G_0_DB"
  570. };
  571. static const struct soc_enum wsa_pa_gain_enum =
  572. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  573. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  574. struct snd_ctl_elem_value *ucontrol)
  575. {
  576. struct snd_soc_component *component =
  577. snd_soc_kcontrol_component(kcontrol);
  578. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  579. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  580. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  581. wsa884x->pa_gain);
  582. return 0;
  583. }
  584. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  585. struct snd_ctl_elem_value *ucontrol)
  586. {
  587. struct snd_soc_component *component =
  588. snd_soc_kcontrol_component(kcontrol);
  589. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  590. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  591. __func__, ucontrol->value.integer.value[0]);
  592. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  593. return 0;
  594. }
  595. static int wsa884x_get_mute(struct snd_kcontrol *kcontrol,
  596. struct snd_ctl_elem_value *ucontrol)
  597. {
  598. struct snd_soc_component *component =
  599. snd_soc_kcontrol_component(kcontrol);
  600. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  601. ucontrol->value.integer.value[0] = wsa884x->pa_mute;
  602. return 0;
  603. }
  604. static int wsa884x_set_mute(struct snd_kcontrol *kcontrol,
  605. struct snd_ctl_elem_value *ucontrol)
  606. {
  607. struct snd_soc_component *component =
  608. snd_soc_kcontrol_component(kcontrol);
  609. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  610. int value = ucontrol->value.integer.value[0];
  611. dev_dbg(component->dev, "%s: mute current %d, new %d\n",
  612. __func__, wsa884x->pa_mute, value);
  613. wsa884x->pa_mute = value;
  614. return 0;
  615. }
  616. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  617. struct snd_ctl_elem_value *ucontrol)
  618. {
  619. struct snd_soc_component *component =
  620. snd_soc_kcontrol_component(kcontrol);
  621. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  622. int temp = 0;
  623. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  624. temp = wsa884x->curr_temp;
  625. else
  626. wsa884x_get_temperature(component, &temp);
  627. ucontrol->value.integer.value[0] = temp;
  628. return 0;
  629. }
  630. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  631. void *file_private_data, struct file *file,
  632. char __user *buf, size_t count, loff_t pos)
  633. {
  634. struct wsa884x_priv *wsa884x;
  635. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  636. int len = 0;
  637. wsa884x = (struct wsa884x_priv *) entry->private_data;
  638. if (!wsa884x) {
  639. pr_err("%s: wsa884x priv is null\n", __func__);
  640. return -EINVAL;
  641. }
  642. switch (wsa884x->version) {
  643. case WSA884X_VERSION_1_0:
  644. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  645. break;
  646. default:
  647. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  648. break;
  649. }
  650. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  651. }
  652. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  653. .read = wsa884x_codec_version_read,
  654. };
  655. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  656. void *file_private_data,
  657. struct file *file,
  658. char __user *buf, size_t count,
  659. loff_t pos)
  660. {
  661. struct wsa884x_priv *wsa884x;
  662. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  663. int len = 0;
  664. wsa884x = (struct wsa884x_priv *) entry->private_data;
  665. if (!wsa884x) {
  666. pr_err("%s: wsa884x priv is null\n", __func__);
  667. return -EINVAL;
  668. }
  669. switch (wsa884x->variant) {
  670. case WSA8840:
  671. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  672. break;
  673. case WSA8845:
  674. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  675. break;
  676. case WSA8845H:
  677. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  678. break;
  679. default:
  680. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  681. break;
  682. }
  683. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  684. }
  685. static struct snd_info_entry_ops wsa884x_variant_ops = {
  686. .read = wsa884x_variant_read,
  687. };
  688. /*
  689. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  690. * @codec_root: The parent directory
  691. * @component: Codec instance
  692. *
  693. * Creates wsa884x module and version entry under the given
  694. * parent directory.
  695. *
  696. * Return: 0 on success or negative error code on failure.
  697. */
  698. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  699. struct snd_soc_component *component)
  700. {
  701. struct snd_info_entry *version_entry;
  702. struct snd_info_entry *variant_entry;
  703. struct wsa884x_priv *wsa884x;
  704. struct snd_soc_card *card;
  705. char name[80];
  706. if (!codec_root || !component)
  707. return -EINVAL;
  708. wsa884x = snd_soc_component_get_drvdata(component);
  709. if (wsa884x->entry) {
  710. dev_dbg(wsa884x->dev,
  711. "%s:wsa884x module already created\n", __func__);
  712. return 0;
  713. }
  714. card = component->card;
  715. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  716. wsa884x->swr_slave->addr);
  717. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  718. (const char *)name,
  719. codec_root);
  720. if (!wsa884x->entry) {
  721. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  722. __func__);
  723. return -ENOMEM;
  724. }
  725. wsa884x->entry->mode = S_IFDIR | 0555;
  726. if (snd_info_register(wsa884x->entry) < 0) {
  727. snd_info_free_entry(wsa884x->entry);
  728. return -ENOMEM;
  729. }
  730. version_entry = snd_info_create_card_entry(card->snd_card,
  731. "version",
  732. wsa884x->entry);
  733. if (!version_entry) {
  734. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  735. __func__);
  736. snd_info_free_entry(wsa884x->entry);
  737. return -ENOMEM;
  738. }
  739. version_entry->private_data = wsa884x;
  740. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  741. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  742. version_entry->c.ops = &wsa884x_codec_info_ops;
  743. if (snd_info_register(version_entry) < 0) {
  744. snd_info_free_entry(version_entry);
  745. snd_info_free_entry(wsa884x->entry);
  746. return -ENOMEM;
  747. }
  748. wsa884x->version_entry = version_entry;
  749. variant_entry = snd_info_create_card_entry(card->snd_card,
  750. "variant",
  751. wsa884x->entry);
  752. if (!variant_entry) {
  753. dev_dbg(component->dev,
  754. "%s: failed to create wsa884x variant entry\n",
  755. __func__);
  756. snd_info_free_entry(version_entry);
  757. snd_info_free_entry(wsa884x->entry);
  758. return -ENOMEM;
  759. }
  760. variant_entry->private_data = wsa884x;
  761. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  762. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  763. variant_entry->c.ops = &wsa884x_variant_ops;
  764. if (snd_info_register(variant_entry) < 0) {
  765. snd_info_free_entry(variant_entry);
  766. snd_info_free_entry(version_entry);
  767. snd_info_free_entry(wsa884x->entry);
  768. return -ENOMEM;
  769. }
  770. wsa884x->variant_entry = variant_entry;
  771. return 0;
  772. }
  773. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  774. int wsa884x_set_configuration(struct snd_soc_component *component,
  775. u8 rload, u8 bat_cfg, u8 system_gain)
  776. {
  777. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  778. wsa884x->rload = rload;
  779. wsa884x->bat_cfg = bat_cfg;
  780. wsa884x->system_gain = system_gain;
  781. return 0;
  782. }
  783. EXPORT_SYMBOL(wsa884x_set_configuration);
  784. /*
  785. * wsa884x_codec_get_dev_num - returns swr device number
  786. * @component: Codec instance
  787. *
  788. * Return: swr device number on success or negative error
  789. * code on failure.
  790. */
  791. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  792. {
  793. struct wsa884x_priv *wsa884x;
  794. if (!component)
  795. return -EINVAL;
  796. wsa884x = snd_soc_component_get_drvdata(component);
  797. if (!wsa884x) {
  798. pr_err("%s: wsa884x component is NULL\n", __func__);
  799. return -EINVAL;
  800. }
  801. return wsa884x->swr_slave->dev_num;
  802. }
  803. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  804. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  805. struct snd_ctl_elem_value *ucontrol)
  806. {
  807. struct snd_soc_component *component =
  808. snd_soc_kcontrol_component(kcontrol);
  809. struct wsa884x_priv *wsa884x;
  810. if (!component)
  811. return -EINVAL;
  812. wsa884x = snd_soc_component_get_drvdata(component);
  813. if (!wsa884x) {
  814. pr_err("%s: wsa884x component is NULL\n", __func__);
  815. return -EINVAL;
  816. }
  817. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  818. return 0;
  819. }
  820. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  821. struct snd_ctl_elem_value *ucontrol)
  822. {
  823. struct snd_soc_component *component =
  824. snd_soc_kcontrol_component(kcontrol);
  825. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  826. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  827. return 0;
  828. }
  829. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_value *ucontrol)
  831. {
  832. struct snd_soc_component *component =
  833. snd_soc_kcontrol_component(kcontrol);
  834. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  835. int value = ucontrol->value.integer.value[0];
  836. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  837. __func__, wsa884x->comp_enable, value);
  838. wsa884x->comp_enable = value;
  839. return 0;
  840. }
  841. static int wsa884x_get_comp_offset(struct snd_kcontrol *kcontrol,
  842. struct snd_ctl_elem_value *ucontrol)
  843. {
  844. struct snd_soc_component *component =
  845. snd_soc_kcontrol_component(kcontrol);
  846. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  847. ucontrol->value.integer.value[0] = wsa884x->comp_offset;
  848. return 0;
  849. }
  850. static int wsa884x_set_comp_offset(struct snd_kcontrol *kcontrol,
  851. struct snd_ctl_elem_value *ucontrol)
  852. {
  853. struct snd_soc_component *component =
  854. snd_soc_kcontrol_component(kcontrol);
  855. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  856. int value = ucontrol->value.integer.value[0];
  857. dev_dbg(component->dev, "%s: comp_offset %d\n",
  858. __func__, wsa884x->comp_offset);
  859. wsa884x->comp_offset = value;
  860. return 0;
  861. }
  862. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  863. struct snd_ctl_elem_value *ucontrol)
  864. {
  865. struct snd_soc_component *component =
  866. snd_soc_kcontrol_component(kcontrol);
  867. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  868. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  869. return 0;
  870. }
  871. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  872. struct snd_ctl_elem_value *ucontrol)
  873. {
  874. struct snd_soc_component *component =
  875. snd_soc_kcontrol_component(kcontrol);
  876. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  877. int value = ucontrol->value.integer.value[0];
  878. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  879. __func__, wsa884x->visense_enable, value);
  880. wsa884x->visense_enable = value;
  881. return 0;
  882. }
  883. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  884. struct snd_ctl_elem_value *ucontrol)
  885. {
  886. struct snd_soc_component *component =
  887. snd_soc_kcontrol_component(kcontrol);
  888. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  889. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  890. return 0;
  891. }
  892. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  893. struct snd_ctl_elem_value *ucontrol)
  894. {
  895. struct snd_soc_component *component =
  896. snd_soc_kcontrol_component(kcontrol);
  897. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  898. int value = ucontrol->value.integer.value[0];
  899. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  900. __func__, wsa884x->pbr_enable, value);
  901. wsa884x->pbr_enable = value;
  902. if (value) {
  903. snd_soc_component_update_bits(component,
  904. WSA884X_CLSH_VTH1,
  905. 0xFF, 0xFF);
  906. }
  907. return 0;
  908. }
  909. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  910. struct snd_ctl_elem_value *ucontrol)
  911. {
  912. struct snd_soc_component *component =
  913. snd_soc_kcontrol_component(kcontrol);
  914. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  915. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  916. return 0;
  917. }
  918. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  919. struct snd_ctl_elem_value *ucontrol)
  920. {
  921. struct snd_soc_component *component =
  922. snd_soc_kcontrol_component(kcontrol);
  923. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  924. int value = ucontrol->value.integer.value[0];
  925. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  926. __func__, wsa884x->cps_enable, value);
  927. wsa884x->cps_enable = value;
  928. return 0;
  929. }
  930. static int wsa884x_get_ext_vdd_spk(struct snd_kcontrol *kcontrol,
  931. struct snd_ctl_elem_value *ucontrol)
  932. {
  933. struct snd_soc_component *component =
  934. snd_soc_kcontrol_component(kcontrol);
  935. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  936. ucontrol->value.integer.value[0] = wsa884x->ext_vdd_spk;
  937. return 0;
  938. }
  939. static int wsa884x_put_ext_vdd_spk(struct snd_kcontrol *kcontrol,
  940. struct snd_ctl_elem_value *ucontrol)
  941. {
  942. struct snd_soc_component *component =
  943. snd_soc_kcontrol_component(kcontrol);
  944. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  945. int value = ucontrol->value.integer.value[0];
  946. dev_dbg(component->dev, "%s: Ext VDD SPK enable current %d, new %d\n",
  947. __func__, wsa884x->ext_vdd_spk, value);
  948. wsa884x->ext_vdd_spk = value;
  949. return 0;
  950. }
  951. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  952. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  953. wsa_pa_gain_get, wsa_pa_gain_put),
  954. SOC_SINGLE_EXT("WSA PA Mute", SND_SOC_NOPM, 0, 1, 0,
  955. wsa884x_get_mute, wsa884x_set_mute),
  956. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  957. wsa_get_temp, NULL),
  958. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  959. wsa884x_get_dev_num, NULL),
  960. SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
  961. wsa_dev_mode_get, wsa_dev_mode_put),
  962. SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
  963. wsa884x_get_comp_offset, wsa884x_set_comp_offset),
  964. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  965. wsa884x_get_compander, wsa884x_set_compander),
  966. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  967. wsa884x_get_visense, wsa884x_set_visense),
  968. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  969. wsa884x_get_pbr, wsa884x_set_pbr),
  970. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  971. wsa884x_get_cps, wsa884x_set_cps),
  972. SOC_SINGLE_EXT("External VDD_SPK", SND_SOC_NOPM, 0, 1, 0,
  973. wsa884x_get_ext_vdd_spk, wsa884x_put_ext_vdd_spk),
  974. };
  975. static const struct snd_kcontrol_new swr_dac_port[] = {
  976. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  977. };
  978. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  979. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  980. u8 *port_type)
  981. {
  982. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  983. *port_id = wsa884x->port[port_idx].port_id;
  984. *num_ch = wsa884x->port[port_idx].num_ch;
  985. *ch_mask = wsa884x->port[port_idx].ch_mask;
  986. *ch_rate = wsa884x->port[port_idx].ch_rate;
  987. *port_type = wsa884x->port[port_idx].port_type;
  988. return 0;
  989. }
  990. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  991. struct snd_kcontrol *kcontrol, int event)
  992. {
  993. struct snd_soc_component *component =
  994. snd_soc_dapm_to_component(w->dapm);
  995. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  996. u8 port_id[WSA884X_MAX_SWR_PORTS];
  997. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  998. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  999. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1000. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1001. u8 num_port = 0;
  1002. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1003. event, w->name);
  1004. if (wsa884x == NULL)
  1005. return -EINVAL;
  1006. switch (event) {
  1007. case SND_SOC_DAPM_PRE_PMU:
  1008. wsa884x_set_port(component, SWR_DAC_PORT,
  1009. &port_id[num_port], &num_ch[num_port],
  1010. &ch_mask[num_port], &ch_rate[num_port],
  1011. &port_type[num_port]);
  1012. ++num_port;
  1013. if (wsa884x->comp_enable) {
  1014. wsa884x_set_port(component, SWR_COMP_PORT,
  1015. &port_id[num_port], &num_ch[num_port],
  1016. &ch_mask[num_port], &ch_rate[num_port],
  1017. &port_type[num_port]);
  1018. ++num_port;
  1019. }
  1020. if (wsa884x->pbr_enable) {
  1021. wsa884x_set_port(component, SWR_PBR_PORT,
  1022. &port_id[num_port], &num_ch[num_port],
  1023. &ch_mask[num_port], &ch_rate[num_port],
  1024. &port_type[num_port]);
  1025. ++num_port;
  1026. }
  1027. if (wsa884x->visense_enable) {
  1028. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1029. &port_id[num_port], &num_ch[num_port],
  1030. &ch_mask[num_port], &ch_rate[num_port],
  1031. &port_type[num_port]);
  1032. ++num_port;
  1033. }
  1034. if (wsa884x->cps_enable) {
  1035. wsa884x_set_port(component, SWR_CPS_PORT,
  1036. &port_id[num_port], &num_ch[num_port],
  1037. &ch_mask[num_port], &ch_rate[num_port],
  1038. &port_type[num_port]);
  1039. ++num_port;
  1040. }
  1041. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1042. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1043. &port_type[0]);
  1044. break;
  1045. case SND_SOC_DAPM_POST_PMU:
  1046. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1047. break;
  1048. case SND_SOC_DAPM_PRE_PMD:
  1049. wsa884x_set_port(component, SWR_DAC_PORT,
  1050. &port_id[num_port], &num_ch[num_port],
  1051. &ch_mask[num_port], &ch_rate[num_port],
  1052. &port_type[num_port]);
  1053. ++num_port;
  1054. if (wsa884x->comp_enable) {
  1055. wsa884x_set_port(component, SWR_COMP_PORT,
  1056. &port_id[num_port], &num_ch[num_port],
  1057. &ch_mask[num_port], &ch_rate[num_port],
  1058. &port_type[num_port]);
  1059. ++num_port;
  1060. }
  1061. if (wsa884x->pbr_enable) {
  1062. wsa884x_set_port(component, SWR_PBR_PORT,
  1063. &port_id[num_port], &num_ch[num_port],
  1064. &ch_mask[num_port], &ch_rate[num_port],
  1065. &port_type[num_port]);
  1066. ++num_port;
  1067. }
  1068. if (wsa884x->visense_enable) {
  1069. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1070. &port_id[num_port], &num_ch[num_port],
  1071. &ch_mask[num_port], &ch_rate[num_port],
  1072. &port_type[num_port]);
  1073. ++num_port;
  1074. }
  1075. if (wsa884x->cps_enable) {
  1076. wsa884x_set_port(component, SWR_CPS_PORT,
  1077. &port_id[num_port], &num_ch[num_port],
  1078. &ch_mask[num_port], &ch_rate[num_port],
  1079. &port_type[num_port]);
  1080. ++num_port;
  1081. }
  1082. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1083. &ch_mask[0], &port_type[0]);
  1084. break;
  1085. case SND_SOC_DAPM_POST_PMD:
  1086. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1087. dev_err(component->dev,
  1088. "%s: set num ch failed\n", __func__);
  1089. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1090. wsa884x->swr_slave->dev_num,
  1091. false);
  1092. break;
  1093. default:
  1094. break;
  1095. }
  1096. return 0;
  1097. }
  1098. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  1099. {
  1100. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1101. switch (wsa884x->bat_cfg) {
  1102. case CONFIG_1S:
  1103. case EXT_1S:
  1104. switch (wsa884x->system_gain) {
  1105. case G_21_DB:
  1106. wsa884x->comp_offset = COMP_OFFSET0;
  1107. wsa884x->min_gain = G_0_DB;
  1108. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  1109. break;
  1110. case G_19P5_DB:
  1111. wsa884x->comp_offset = COMP_OFFSET1;
  1112. wsa884x->min_gain = G_M1P5_DB;
  1113. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  1114. break;
  1115. case G_18_DB:
  1116. wsa884x->comp_offset = COMP_OFFSET2;
  1117. wsa884x->min_gain = G_M3_DB;
  1118. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  1119. break;
  1120. case G_16P5_DB:
  1121. wsa884x->comp_offset = COMP_OFFSET3;
  1122. wsa884x->min_gain = G_M4P5_DB;
  1123. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  1124. break;
  1125. default:
  1126. wsa884x->comp_offset = COMP_OFFSET4;
  1127. wsa884x->min_gain = G_M6_DB;
  1128. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  1129. break;
  1130. }
  1131. break;
  1132. case CONFIG_3S:
  1133. case EXT_3S:
  1134. wsa884x->comp_offset = COMP_OFFSET0;
  1135. wsa884x->min_gain = G_7P5_DB;
  1136. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  1137. break;
  1138. case EXT_ABOVE_3S:
  1139. wsa884x->comp_offset = COMP_OFFSET0;
  1140. wsa884x->min_gain = G_12_DB;
  1141. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  1142. break;
  1143. default:
  1144. wsa884x->comp_offset = COMP_OFFSET0;
  1145. wsa884x->min_gain = G_0_DB;
  1146. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  1147. break;
  1148. }
  1149. if (!wsa884x->comp_enable)
  1150. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->system_gain];
  1151. snd_soc_component_update_bits(component,
  1152. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  1153. if (wsa884x->comp_enable)
  1154. snd_soc_component_update_bits(component,
  1155. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  1156. wsa884x->comp_offset));
  1157. return 0;
  1158. }
  1159. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1160. struct snd_kcontrol *kcontrol, int event)
  1161. {
  1162. struct snd_soc_component *component =
  1163. snd_soc_dapm_to_component(w->dapm);
  1164. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1165. u8 igain;
  1166. u8 vgain;
  1167. u8 ana_wo_ctl_0_value;
  1168. u8 pa_aux_shift = 0x02;
  1169. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1170. switch (event) {
  1171. case SND_SOC_DAPM_POST_PMU:
  1172. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1173. wsa884x->swr_slave->dev_num,
  1174. true);
  1175. wsa884x_set_gain_parameters(component);
  1176. /* Must write WO registers in a single write */
  1177. ana_wo_ctl_0_value = (0xC |
  1178. (wsa884x->pa_aux_gain << pa_aux_shift) |
  1179. !wsa884x->dev_mode);
  1180. snd_soc_component_update_bits(component,
  1181. WSA884X_ANA_WO_CTL_0, 0xFF, ana_wo_ctl_0_value);
  1182. snd_soc_component_update_bits(component,
  1183. WSA884X_ANA_WO_CTL_1, 0xFF, 0);
  1184. if (wsa884x->rload == WSA_4OHMS ||
  1185. wsa884x->rload == WSA_6OHMS)
  1186. snd_soc_component_update_bits(component,
  1187. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1188. if (wsa884x->dev_mode == SPEAKER) {
  1189. snd_soc_component_update_bits(component,
  1190. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1191. } else {
  1192. snd_soc_component_update_bits(component,
  1193. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1194. snd_soc_component_update_bits(component,
  1195. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1196. snd_soc_component_update_bits(component,
  1197. REG_FIELD_VALUE(PWM_CLK_CTL,
  1198. PWM_CLK_FREQ_SEL, 0x01));
  1199. }
  1200. if (!wsa884x->pbr_enable) {
  1201. snd_soc_component_update_bits(component,
  1202. REG_FIELD_VALUE(CURRENT_LIMIT,
  1203. CURRENT_LIMIT_OVRD_EN, 0x01));
  1204. snd_soc_component_update_bits(component,
  1205. REG_FIELD_VALUE(CURRENT_LIMIT,
  1206. CURRENT_LIMIT, 0x09));
  1207. }
  1208. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  1209. vgain = vsense_gain_data[wsa884x->system_gain];
  1210. snd_soc_component_update_bits(component,
  1211. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  1212. snd_soc_component_update_bits(component,
  1213. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  1214. wcd_enable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR);
  1215. wcd_enable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO);
  1216. /* Force remove group */
  1217. swr_remove_from_group(wsa884x->swr_slave,
  1218. wsa884x->swr_slave->dev_num);
  1219. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask))
  1220. snd_soc_component_update_bits(component,
  1221. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1222. break;
  1223. case SND_SOC_DAPM_PRE_PMD:
  1224. if (!test_bit(SPKR_ADIE_LB, &wsa884x->status_mask))
  1225. wcd_disable_irq(&wsa884x->irq_info,
  1226. WSA884X_IRQ_INT_PDM_WD);
  1227. snd_soc_component_update_bits(component,
  1228. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1229. snd_soc_component_update_bits(component,
  1230. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1231. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO);
  1232. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR);
  1233. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1234. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1235. break;
  1236. }
  1237. return 0;
  1238. }
  1239. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1240. SND_SOC_DAPM_INPUT("IN"),
  1241. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1242. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1243. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1244. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1245. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1246. };
  1247. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1248. {"SWR DAC_Port", "Switch", "IN"},
  1249. {"SPKR", NULL, "SWR DAC_Port"},
  1250. };
  1251. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1252. u8 num_port, unsigned int *ch_mask,
  1253. unsigned int *ch_rate, u8 *port_type)
  1254. {
  1255. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1256. int i;
  1257. if (!port || !ch_mask || !ch_rate ||
  1258. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1259. dev_err(component->dev,
  1260. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1261. __func__, port, ch_mask, ch_rate);
  1262. return -EINVAL;
  1263. }
  1264. for (i = 0; i < num_port; i++) {
  1265. wsa884x->port[i].port_id = port[i];
  1266. wsa884x->port[i].ch_mask = ch_mask[i];
  1267. wsa884x->port[i].ch_rate = ch_rate[i];
  1268. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1269. if (port_type)
  1270. wsa884x->port[i].port_type = port_type[i];
  1271. }
  1272. return 0;
  1273. }
  1274. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1275. static void wsa884x_codec_init(struct snd_soc_component *component)
  1276. {
  1277. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1278. int i;
  1279. if (!wsa884x)
  1280. return;
  1281. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1282. snd_soc_component_update_bits(component, reg_init[i].reg,
  1283. reg_init[i].mask, reg_init[i].val);
  1284. if (wsa884x->variant == WSA8845H)
  1285. snd_soc_component_update_bits(wsa884x->component,
  1286. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  1287. }
  1288. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1289. struct wsa_temp_register *wsa_temp_reg)
  1290. {
  1291. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1292. if (!wsa884x) {
  1293. dev_err(component->dev, "%s: wsa884x is NULL\n", __func__);
  1294. return -EINVAL;
  1295. }
  1296. mutex_lock(&wsa884x->res_lock);
  1297. snd_soc_component_update_bits(component,
  1298. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1299. snd_soc_component_update_bits(component,
  1300. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1301. snd_soc_component_update_bits(component,
  1302. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1303. snd_soc_component_update_bits(component,
  1304. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1305. snd_soc_component_update_bits(component,
  1306. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1307. snd_soc_component_update_bits(component,
  1308. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1309. snd_soc_component_update_bits(component,
  1310. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1311. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1312. WSA884X_TEMP_DIN_MSB);
  1313. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1314. WSA884X_TEMP_DIN_LSB);
  1315. snd_soc_component_update_bits(component,
  1316. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1317. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1318. WSA884X_OTP_REG_1);
  1319. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1320. WSA884X_OTP_REG_2);
  1321. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1322. WSA884X_OTP_REG_3);
  1323. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1324. WSA884X_OTP_REG_4);
  1325. snd_soc_component_update_bits(component,
  1326. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1327. mutex_unlock(&wsa884x->res_lock);
  1328. return 0;
  1329. }
  1330. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1331. int *temp)
  1332. {
  1333. struct wsa_temp_register reg;
  1334. int dmeas, d1, d2;
  1335. int ret = 0;
  1336. int temp_val = 0;
  1337. int t1 = T1_TEMP;
  1338. int t2 = T2_TEMP;
  1339. u8 retry = WSA884X_TEMP_RETRY;
  1340. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1341. if (!wsa884x)
  1342. return -EINVAL;
  1343. do {
  1344. ret = wsa884x_temp_reg_read(component, &reg);
  1345. if (ret) {
  1346. pr_err("%s: temp read failed: %d, current temp: %d\n",
  1347. __func__, ret, wsa884x->curr_temp);
  1348. if (temp)
  1349. *temp = wsa884x->curr_temp;
  1350. return 0;
  1351. }
  1352. /*
  1353. * Temperature register values are expected to be in the
  1354. * following range.
  1355. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1356. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1357. */
  1358. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1359. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1360. reg.d1_lsb == 192)) ||
  1361. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1362. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1363. reg.d2_lsb == 192))) {
  1364. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1365. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1366. reg.d2_lsb);
  1367. }
  1368. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1369. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1370. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1371. if (d1 == d2)
  1372. temp_val = TEMP_INVALID;
  1373. else
  1374. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1375. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1376. temp_val >= HIGH_TEMP_THRESHOLD) {
  1377. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1378. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1379. if (retry--)
  1380. msleep(10);
  1381. } else {
  1382. break;
  1383. }
  1384. } while (retry);
  1385. wsa884x->curr_temp = temp_val;
  1386. if (temp)
  1387. *temp = temp_val;
  1388. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1389. __func__, temp_val, dmeas, d1, d2);
  1390. return ret;
  1391. }
  1392. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1393. {
  1394. char w_name[MAX_NAME_LEN];
  1395. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1396. struct swr_device *dev;
  1397. int variant = 0, version = 0;
  1398. struct snd_soc_dapm_context *dapm =
  1399. snd_soc_component_get_dapm(component);
  1400. if (!wsa884x)
  1401. return -EINVAL;
  1402. if (!component->name_prefix)
  1403. return -EINVAL;
  1404. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1405. dev = wsa884x->swr_slave;
  1406. wsa884x->component = component;
  1407. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1408. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1409. wsa884x->variant = variant;
  1410. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1411. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1412. wsa884x->version = version;
  1413. wsa884x->comp_offset = COMP_OFFSET2;
  1414. wsa884x->bat_cfg = CONFIG_1S;
  1415. wsa884x->rload = WSA_8OHMS;
  1416. wsa884x->system_gain = G_19P5_DB;
  1417. wsa884x_codec_init(component);
  1418. wsa884x->global_pa_cnt = 0;
  1419. memset(w_name, 0, sizeof(w_name));
  1420. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1421. strlcat(w_name, " ", sizeof(w_name));
  1422. strlcat(w_name, wsa884x->dai_driver->playback.stream_name,
  1423. sizeof(w_name));
  1424. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1425. memset(w_name, 0, sizeof(w_name));
  1426. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1427. strlcat(w_name, " IN", sizeof(w_name));
  1428. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1429. memset(w_name, 0, sizeof(w_name));
  1430. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1431. strlcat(w_name, " SWR DAC_Port", sizeof(w_name));
  1432. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1433. memset(w_name, 0, sizeof(w_name));
  1434. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1435. strlcat(w_name, " SPKR", sizeof(w_name));
  1436. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1437. snd_soc_dapm_sync(dapm);
  1438. return 0;
  1439. }
  1440. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1441. {
  1442. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1443. if (!wsa884x)
  1444. return;
  1445. snd_soc_component_exit_regmap(component);
  1446. return;
  1447. }
  1448. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1449. {
  1450. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1451. if (!wsa884x)
  1452. return 0;
  1453. wsa884x->dapm_bias_off = true;
  1454. return 0;
  1455. }
  1456. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1457. {
  1458. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1459. if (!wsa884x)
  1460. return 0;
  1461. wsa884x->dapm_bias_off = false;
  1462. return 0;
  1463. }
  1464. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1465. .name = "",
  1466. .probe = wsa884x_codec_probe,
  1467. .remove = wsa884x_codec_remove,
  1468. .controls = wsa884x_snd_controls,
  1469. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1470. .dapm_widgets = wsa884x_dapm_widgets,
  1471. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1472. .dapm_routes = wsa884x_audio_map,
  1473. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1474. .suspend = wsa884x_soc_codec_suspend,
  1475. .resume = wsa884x_soc_codec_resume,
  1476. };
  1477. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1478. {
  1479. int ret = 0;
  1480. if (enable)
  1481. ret = msm_cdc_pinctrl_select_active_state(
  1482. wsa884x->wsa_rst_np);
  1483. else
  1484. ret = msm_cdc_pinctrl_select_sleep_state(
  1485. wsa884x->wsa_rst_np);
  1486. if (ret != 0)
  1487. dev_err(wsa884x->dev,
  1488. "%s: Failed to turn state %d; ret=%d\n",
  1489. __func__, enable, ret);
  1490. return ret;
  1491. }
  1492. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1493. {
  1494. int ret;
  1495. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1496. if (ret)
  1497. dev_err(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1498. return ret;
  1499. }
  1500. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1501. {
  1502. int ret;
  1503. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1504. if (ret)
  1505. dev_err(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1506. return ret;
  1507. }
  1508. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1509. {
  1510. u8 retry = WSA884X_NUM_RETRY;
  1511. u8 devnum = 0;
  1512. struct swr_device *pdev;
  1513. pdev = wsa884x->swr_slave;
  1514. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1515. /* Retry after 1 msec delay */
  1516. usleep_range(1000, 1100);
  1517. }
  1518. pdev->dev_num = devnum;
  1519. wsa884x_regcache_sync(wsa884x);
  1520. return 0;
  1521. }
  1522. static int wsa884x_event_notify(struct notifier_block *nb,
  1523. unsigned long val, void *ptr)
  1524. {
  1525. u16 event = (val & 0xffff);
  1526. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1527. parent_nblock);
  1528. if (!wsa884x)
  1529. return -EINVAL;
  1530. switch (event) {
  1531. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1532. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1533. snd_soc_component_update_bits(wsa884x->component,
  1534. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1535. wsa884x_swr_down(wsa884x);
  1536. break;
  1537. case BOLERO_SLV_EVT_SSR_UP:
  1538. wsa884x_swr_up(wsa884x);
  1539. /* Add delay to allow enumerate */
  1540. usleep_range(20000, 20010);
  1541. wsa884x_swr_reset(wsa884x);
  1542. break;
  1543. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1544. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1545. snd_soc_component_update_bits(wsa884x->component,
  1546. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1547. snd_soc_component_update_bits(wsa884x->component,
  1548. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1549. wcd_enable_irq(&wsa884x->irq_info,
  1550. WSA884X_IRQ_INT_PDM_WD);
  1551. /* Added delay as per HW sequence */
  1552. usleep_range(3000, 3100);
  1553. snd_soc_component_update_bits(wsa884x->component,
  1554. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  1555. /* Added delay as per HW sequence */
  1556. usleep_range(5000, 5050);
  1557. }
  1558. break;
  1559. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1560. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1561. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1562. break;
  1563. default:
  1564. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1565. __func__, event);
  1566. break;
  1567. }
  1568. return 0;
  1569. }
  1570. static int wsa884x_enable_supplies(struct device *dev,
  1571. struct wsa884x_priv *priv)
  1572. {
  1573. int ret = 0;
  1574. /* Parse power supplies */
  1575. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1576. &priv->num_supplies);
  1577. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1578. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1579. return -EINVAL;
  1580. }
  1581. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1582. priv->regulator, priv->num_supplies);
  1583. if (!priv->supplies) {
  1584. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1585. __func__);
  1586. return ret;
  1587. }
  1588. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1589. priv->regulator,
  1590. priv->num_supplies);
  1591. if (ret)
  1592. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1593. __func__);
  1594. return ret;
  1595. }
  1596. static struct snd_soc_dai_driver wsa_dai[] = {
  1597. {
  1598. .name = "",
  1599. .playback = {
  1600. .stream_name = "",
  1601. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1602. .formats = WSA884X_FORMATS,
  1603. .rate_max = 192000,
  1604. .rate_min = 8000,
  1605. .channels_min = 1,
  1606. .channels_max = 2,
  1607. },
  1608. },
  1609. };
  1610. static int wsa884x_swr_probe(struct swr_device *pdev)
  1611. {
  1612. int ret = 0, i = 0;
  1613. struct wsa884x_priv *wsa884x;
  1614. u8 devnum = 0;
  1615. bool pin_state_current = false;
  1616. struct wsa_ctrl_platform_data *plat_data = NULL;
  1617. struct snd_soc_component *component;
  1618. char buffer[MAX_NAME_LEN];
  1619. int dev_index = 0;
  1620. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1621. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1622. GFP_KERNEL);
  1623. if (!wsa884x)
  1624. return -ENOMEM;
  1625. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1626. GFP_KERNEL);
  1627. if (!wsa884x_sub_regmap_irq_chip)
  1628. return -ENOMEM;
  1629. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1630. sizeof(struct regmap_irq_chip));
  1631. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1632. if (ret) {
  1633. ret = -EPROBE_DEFER;
  1634. goto err;
  1635. }
  1636. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1637. "qcom,spkr-sd-n-node", 0);
  1638. if (!wsa884x->wsa_rst_np) {
  1639. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1640. goto err_supply;
  1641. }
  1642. swr_set_dev_data(pdev, wsa884x);
  1643. wsa884x->swr_slave = pdev;
  1644. wsa884x->dev = &pdev->dev;
  1645. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1646. wsa884x_gpio_ctrl(wsa884x, true);
  1647. /*
  1648. * Add 5msec delay to provide sufficient time for
  1649. * soundwire auto enumeration of slave devices as
  1650. * per HW requirement.
  1651. */
  1652. usleep_range(5000, 5010);
  1653. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1654. if (ret) {
  1655. dev_dbg(&pdev->dev,
  1656. "%s get devnum %d for dev addr %lx failed\n",
  1657. __func__, devnum, pdev->addr);
  1658. ret = -EPROBE_DEFER;
  1659. goto err_supply;
  1660. }
  1661. pdev->dev_num = devnum;
  1662. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1663. &wsa884x_regmap_config);
  1664. if (IS_ERR(wsa884x->regmap)) {
  1665. ret = PTR_ERR(wsa884x->regmap);
  1666. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1667. __func__, ret);
  1668. goto dev_err;
  1669. }
  1670. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1671. /* Set all interrupts as edge triggered */
  1672. for (i = 0; i < wsa884x_sub_regmap_irq_chip->num_regs; i++)
  1673. regmap_write(wsa884x->regmap, (WSA884X_INTR_LEVEL0 + i), 0);
  1674. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1675. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1676. wsa884x->irq_info.codec_name = "WSA884X";
  1677. wsa884x->irq_info.regmap = wsa884x->regmap;
  1678. wsa884x->irq_info.dev = &pdev->dev;
  1679. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1680. if (ret) {
  1681. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1682. __func__, ret);
  1683. goto dev_err;
  1684. }
  1685. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1686. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1687. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1688. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR);
  1689. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1690. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1691. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF);
  1692. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1693. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1694. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE);
  1695. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1696. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1697. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP);
  1698. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1699. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1700. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1701. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1702. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1703. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD);
  1704. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1705. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1706. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD);
  1707. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1708. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1709. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1710. /* Under Voltage Lock out (UVLO) interrupt handle */
  1711. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1712. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1713. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO);
  1714. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1715. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1716. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR);
  1717. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1718. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1719. if (!wsa884x->driver) {
  1720. ret = -ENOMEM;
  1721. goto err_irq;
  1722. }
  1723. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1724. sizeof(struct snd_soc_component_driver));
  1725. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1726. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1727. if (!wsa884x->dai_driver) {
  1728. ret = -ENOMEM;
  1729. goto err_mem;
  1730. }
  1731. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1732. /* Get last digit from HEX format */
  1733. dev_index = (int)((char)(pdev->addr & 0xF));
  1734. dev_index += 1;
  1735. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1736. dev_index += 2;
  1737. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1738. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1739. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1740. wsa884x->dai_driver->name =
  1741. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1742. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1743. wsa884x->dai_driver->playback.stream_name =
  1744. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1745. /* Number of DAI's used is 1 */
  1746. ret = snd_soc_register_component(&pdev->dev,
  1747. wsa884x->driver, wsa884x->dai_driver, 1);
  1748. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1749. if (!component) {
  1750. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1751. ret = -EINVAL;
  1752. goto err_mem;
  1753. }
  1754. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1755. "qcom,bolero-handle", 0);
  1756. if (!wsa884x->parent_np)
  1757. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1758. "qcom,lpass-cdc-handle", 0);
  1759. if (wsa884x->parent_np) {
  1760. wsa884x->parent_dev =
  1761. of_find_device_by_node(wsa884x->parent_np);
  1762. if (wsa884x->parent_dev) {
  1763. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1764. if (plat_data) {
  1765. wsa884x->parent_nblock.notifier_call =
  1766. wsa884x_event_notify;
  1767. if (plat_data->register_notifier)
  1768. plat_data->register_notifier(
  1769. plat_data->handle,
  1770. &wsa884x->parent_nblock,
  1771. true);
  1772. wsa884x->register_notifier =
  1773. plat_data->register_notifier;
  1774. wsa884x->handle = plat_data->handle;
  1775. } else {
  1776. dev_err(&pdev->dev, "%s: plat data not found\n",
  1777. __func__);
  1778. }
  1779. } else {
  1780. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1781. __func__);
  1782. }
  1783. } else {
  1784. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1785. }
  1786. mutex_init(&wsa884x->res_lock);
  1787. #ifdef CONFIG_DEBUG_FS
  1788. if (!wsa884x->debugfs_dent) {
  1789. wsa884x->debugfs_dent = debugfs_create_dir(
  1790. dev_name(&pdev->dev), 0);
  1791. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1792. wsa884x->debugfs_peek =
  1793. debugfs_create_file("swrslave_peek",
  1794. S_IFREG | 0444,
  1795. wsa884x->debugfs_dent,
  1796. (void *) pdev,
  1797. &codec_debug_read_ops);
  1798. wsa884x->debugfs_poke =
  1799. debugfs_create_file("swrslave_poke",
  1800. S_IFREG | 0444,
  1801. wsa884x->debugfs_dent,
  1802. (void *) pdev,
  1803. &codec_debug_write_ops);
  1804. wsa884x->debugfs_reg_dump =
  1805. debugfs_create_file(
  1806. "swrslave_reg_dump",
  1807. S_IFREG | 0444,
  1808. wsa884x->debugfs_dent,
  1809. (void *) pdev,
  1810. &codec_debug_dump_ops);
  1811. }
  1812. }
  1813. #endif
  1814. return 0;
  1815. err_mem:
  1816. if (wsa884x->dai_driver) {
  1817. kfree(wsa884x->dai_driver->name);
  1818. kfree(wsa884x->dai_driver->playback.stream_name);
  1819. kfree(wsa884x->dai_driver);
  1820. }
  1821. if (wsa884x->driver) {
  1822. kfree(wsa884x->driver->name);
  1823. kfree(wsa884x->driver);
  1824. }
  1825. err_irq:
  1826. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1827. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1828. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1829. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1830. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1831. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1832. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1833. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1834. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1835. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1836. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  1837. dev_err:
  1838. if (pin_state_current == false)
  1839. wsa884x_gpio_ctrl(wsa884x, false);
  1840. swr_remove_device(pdev);
  1841. err_supply:
  1842. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1843. wsa884x->regulator,
  1844. wsa884x->num_supplies);
  1845. err:
  1846. swr_set_dev_data(pdev, NULL);
  1847. return ret;
  1848. }
  1849. static int wsa884x_swr_remove(struct swr_device *pdev)
  1850. {
  1851. struct wsa884x_priv *wsa884x;
  1852. wsa884x = swr_get_dev_data(pdev);
  1853. if (!wsa884x) {
  1854. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  1855. return -EINVAL;
  1856. }
  1857. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1858. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1859. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1860. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1861. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1862. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1863. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1864. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1865. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1866. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1867. if (wsa884x->register_notifier)
  1868. wsa884x->register_notifier(wsa884x->handle,
  1869. &wsa884x->parent_nblock, false);
  1870. #ifdef CONFIG_DEBUG_FS
  1871. debugfs_remove_recursive(wsa884x->debugfs_dent);
  1872. wsa884x->debugfs_dent = NULL;
  1873. #endif
  1874. mutex_destroy(&wsa884x->res_lock);
  1875. snd_soc_unregister_component(&pdev->dev);
  1876. if (wsa884x->dai_driver) {
  1877. kfree(wsa884x->dai_driver->name);
  1878. kfree(wsa884x->dai_driver->playback.stream_name);
  1879. kfree(wsa884x->dai_driver);
  1880. }
  1881. if (wsa884x->driver) {
  1882. kfree(wsa884x->driver->name);
  1883. kfree(wsa884x->driver);
  1884. }
  1885. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1886. wsa884x->regulator,
  1887. wsa884x->num_supplies);
  1888. swr_set_dev_data(pdev, NULL);
  1889. return 0;
  1890. }
  1891. #ifdef CONFIG_PM_SLEEP
  1892. static int wsa884x_swr_suspend(struct device *dev)
  1893. {
  1894. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  1895. if (!wsa884x) {
  1896. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  1897. return -EINVAL;
  1898. }
  1899. dev_dbg(dev, "%s: system suspend\n", __func__);
  1900. if (wsa884x->dapm_bias_off) {
  1901. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  1902. wsa884x->regulator,
  1903. wsa884x->num_supplies,
  1904. true);
  1905. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  1906. }
  1907. return 0;
  1908. }
  1909. static int wsa884x_swr_resume(struct device *dev)
  1910. {
  1911. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  1912. if (!wsa884x) {
  1913. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  1914. return -EINVAL;
  1915. }
  1916. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  1917. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  1918. wsa884x->regulator,
  1919. wsa884x->num_supplies,
  1920. false);
  1921. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  1922. }
  1923. dev_dbg(dev, "%s: system resume\n", __func__);
  1924. return 0;
  1925. }
  1926. #endif /* CONFIG_PM_SLEEP */
  1927. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  1928. .suspend_late = wsa884x_swr_suspend,
  1929. .resume_early = wsa884x_swr_resume,
  1930. };
  1931. static const struct swr_device_id wsa884x_swr_id[] = {
  1932. {"wsa884x", 0},
  1933. {"wsa884x_2", 0},
  1934. {}
  1935. };
  1936. static const struct of_device_id wsa884x_swr_dt_match[] = {
  1937. {
  1938. .compatible = "qcom,wsa884x",
  1939. },
  1940. {
  1941. .compatible = "qcom,wsa884x_2",
  1942. },
  1943. {}
  1944. };
  1945. static struct swr_driver wsa884x_swr_driver = {
  1946. .driver = {
  1947. .name = "wsa884x",
  1948. .owner = THIS_MODULE,
  1949. .pm = &wsa884x_swr_pm_ops,
  1950. .of_match_table = wsa884x_swr_dt_match,
  1951. },
  1952. .probe = wsa884x_swr_probe,
  1953. .remove = wsa884x_swr_remove,
  1954. .id_table = wsa884x_swr_id,
  1955. };
  1956. static int __init wsa884x_swr_init(void)
  1957. {
  1958. return swr_driver_register(&wsa884x_swr_driver);
  1959. }
  1960. static void __exit wsa884x_swr_exit(void)
  1961. {
  1962. swr_driver_unregister(&wsa884x_swr_driver);
  1963. }
  1964. module_init(wsa884x_swr_init);
  1965. module_exit(wsa884x_swr_exit);
  1966. MODULE_DESCRIPTION("WSA884x codec driver");
  1967. MODULE_LICENSE("GPL v2");