dp_be_tx.c 56 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "hal_tx.h"
  25. #include <hal_be_api.h>
  26. #include <hal_be_tx.h>
  27. #include <dp_htt.h>
  28. #include "dp_internal.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  33. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_mutex_create(lock)
  34. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_mutex_destroy(lock)
  35. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_mutex_acquire(lock)
  36. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_mutex_release(lock)
  37. #else
  38. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_spinlock_create(lock)
  39. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_spinlock_destroy(lock)
  40. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_spin_lock_bh(lock)
  41. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_spin_unlock_bh(lock)
  42. #endif
  43. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  44. #ifdef WLAN_MCAST_MLO
  45. /* MLO peer id for reinject*/
  46. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  47. #define MAX_GSN_NUM 0x0FFF
  48. #ifdef QCA_MULTIPASS_SUPPORT
  49. #define INVALID_VLAN_ID 0xFFFF
  50. #define MULTIPASS_WITH_VLAN_ID 0xFFFE
  51. /**
  52. * struct dp_mlo_mpass_buf - Multipass buffer
  53. * @vlan_id: vlan_id of frame
  54. * @nbuf: pointer to skb buf
  55. */
  56. struct dp_mlo_mpass_buf {
  57. uint16_t vlan_id;
  58. qdf_nbuf_t nbuf;
  59. };
  60. #endif
  61. #endif
  62. #endif
  63. #define DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(_var) \
  64. HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var)
  65. #define DP_TX_WBM_COMPLETION_V3_VALID_GET(_var) \
  66. HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var)
  67. #define DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(_var) \
  68. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var)
  69. #define DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(_var) \
  70. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var)
  71. #define DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(_var) \
  72. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var)
  73. #define DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(_var) \
  74. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var)
  75. #define DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(_var) \
  76. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var)
  77. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  78. #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK
  79. /*
  80. * Value to mark ring desc is invalidated by buffer_virt_addr_63_32 field
  81. * of WBM2SW ring Desc.
  82. */
  83. #define DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE 0x12121212
  84. /**
  85. * dp_tx_comp_desc_check_and_invalidate() - sanity check for ring desc and
  86. * invalidate it after each reaping
  87. * @tx_comp_hal_desc: ring desc virtual address
  88. * @r_tx_desc: pointer to current dp TX Desc pointer
  89. * @tx_desc_va: the original 64 bits Desc VA got from ring Desc
  90. * @hw_cc_done: HW cookie conversion done or not
  91. *
  92. * If HW CC is done, check the buffer_virt_addr_63_32 value to know if
  93. * ring Desc is stale or not. if HW CC is not done, then compare PA between
  94. * ring Desc and current TX desc.
  95. *
  96. * Return: None.
  97. */
  98. static inline
  99. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  100. struct dp_tx_desc_s **r_tx_desc,
  101. uint64_t tx_desc_va,
  102. bool hw_cc_done)
  103. {
  104. qdf_dma_addr_t desc_dma_addr;
  105. if (qdf_likely(hw_cc_done)) {
  106. /* Check upper 32 bits */
  107. if (DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE ==
  108. (tx_desc_va >> 32))
  109. *r_tx_desc = NULL;
  110. /* Invalidate the ring desc for 32 ~ 63 bits of VA */
  111. hal_tx_comp_set_desc_va_63_32(
  112. tx_comp_hal_desc,
  113. DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE);
  114. } else {
  115. /* Compare PA between ring desc and current TX desc stored */
  116. desc_dma_addr = hal_tx_comp_get_paddr(tx_comp_hal_desc);
  117. if (desc_dma_addr != (*r_tx_desc)->dma_addr)
  118. *r_tx_desc = NULL;
  119. }
  120. }
  121. #else
  122. static inline
  123. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  124. struct dp_tx_desc_s **r_tx_desc,
  125. uint64_t tx_desc_va,
  126. bool hw_cc_done)
  127. {
  128. }
  129. #endif
  130. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  131. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  132. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  133. void *tx_comp_hal_desc,
  134. struct dp_tx_desc_s **r_tx_desc)
  135. {
  136. uint32_t tx_desc_id;
  137. uint64_t tx_desc_va = 0;
  138. bool hw_cc_done =
  139. hal_tx_comp_get_cookie_convert_done(tx_comp_hal_desc);
  140. if (qdf_likely(hw_cc_done)) {
  141. /* HW cookie conversion done */
  142. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  143. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  144. } else {
  145. /* SW do cookie conversion to VA */
  146. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  147. *r_tx_desc =
  148. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  149. }
  150. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  151. r_tx_desc, tx_desc_va,
  152. hw_cc_done);
  153. if (*r_tx_desc)
  154. (*r_tx_desc)->peer_id =
  155. dp_tx_comp_get_peer_id_be(soc,
  156. tx_comp_hal_desc);
  157. }
  158. #else
  159. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  160. void *tx_comp_hal_desc,
  161. struct dp_tx_desc_s **r_tx_desc)
  162. {
  163. uint64_t tx_desc_va;
  164. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  165. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  166. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  167. r_tx_desc,
  168. tx_desc_va,
  169. true);
  170. if (*r_tx_desc)
  171. (*r_tx_desc)->peer_id =
  172. dp_tx_comp_get_peer_id_be(soc,
  173. tx_comp_hal_desc);
  174. }
  175. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  176. #else
  177. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  178. void *tx_comp_hal_desc,
  179. struct dp_tx_desc_s **r_tx_desc)
  180. {
  181. uint32_t tx_desc_id;
  182. /* SW do cookie conversion to VA */
  183. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  184. *r_tx_desc =
  185. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  186. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  187. r_tx_desc, 0,
  188. false);
  189. if (*r_tx_desc)
  190. (*r_tx_desc)->peer_id =
  191. dp_tx_comp_get_peer_id_be(soc,
  192. tx_comp_hal_desc);
  193. }
  194. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  195. static inline
  196. void dp_tx_process_mec_notify_be(struct dp_soc *soc, uint8_t *status)
  197. {
  198. struct dp_vdev *vdev;
  199. uint8_t vdev_id;
  200. uint32_t *htt_desc = (uint32_t *)status;
  201. dp_assert_always_internal(soc->mec_fw_offload);
  202. /*
  203. * Get vdev id from HTT status word in case of MEC
  204. * notification
  205. */
  206. vdev_id = DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(htt_desc[4]);
  207. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  208. return;
  209. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  210. DP_MOD_ID_HTT_COMP);
  211. if (!vdev)
  212. return;
  213. dp_tx_mec_handler(vdev, status);
  214. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  215. }
  216. void dp_tx_process_htt_completion_be(struct dp_soc *soc,
  217. struct dp_tx_desc_s *tx_desc,
  218. uint8_t *status,
  219. uint8_t ring_id)
  220. {
  221. uint8_t tx_status;
  222. struct dp_pdev *pdev;
  223. struct dp_vdev *vdev = NULL;
  224. struct hal_tx_completion_status ts = {0};
  225. uint32_t *htt_desc = (uint32_t *)status;
  226. struct dp_txrx_peer *txrx_peer;
  227. dp_txrx_ref_handle txrx_ref_handle = NULL;
  228. struct cdp_tid_tx_stats *tid_stats = NULL;
  229. struct htt_soc *htt_handle;
  230. uint8_t vdev_id;
  231. uint16_t peer_id;
  232. uint8_t xmit_type;
  233. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  234. htt_handle = (struct htt_soc *)soc->htt_handle;
  235. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  236. /*
  237. * There can be scenario where WBM consuming descriptor enqueued
  238. * from TQM2WBM first and TQM completion can happen before MEC
  239. * notification comes from FW2WBM. Avoid access any field of tx
  240. * descriptor in case of MEC notify.
  241. */
  242. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  243. return dp_tx_process_mec_notify_be(soc, status);
  244. /*
  245. * If the descriptor is already freed in vdev_detach,
  246. * continue to next descriptor
  247. */
  248. if (qdf_unlikely(!tx_desc->flags)) {
  249. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  250. tx_desc->id);
  251. return;
  252. }
  253. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  254. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  255. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  256. goto release_tx_desc;
  257. }
  258. pdev = tx_desc->pdev;
  259. if (qdf_unlikely(!pdev)) {
  260. dp_tx_comp_warn("The pdev in TX desc is NULL, dropped.");
  261. dp_tx_comp_warn("tx_status: %u", tx_status);
  262. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  263. goto release_tx_desc;
  264. }
  265. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  266. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  267. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  268. goto release_tx_desc;
  269. }
  270. qdf_assert(tx_desc->pdev);
  271. vdev_id = tx_desc->vdev_id;
  272. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  273. DP_MOD_ID_HTT_COMP);
  274. if (qdf_unlikely(!vdev)) {
  275. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  276. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  277. goto release_tx_desc;
  278. }
  279. switch (tx_status) {
  280. case HTT_TX_FW2WBM_TX_STATUS_OK:
  281. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  282. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  283. {
  284. uint8_t tid;
  285. uint8_t transmit_cnt_valid = 0;
  286. if (DP_TX_WBM_COMPLETION_V3_VALID_GET(htt_desc[3])) {
  287. ts.peer_id =
  288. DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(
  289. htt_desc[3]);
  290. ts.tid =
  291. DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(
  292. htt_desc[3]);
  293. } else {
  294. ts.peer_id = HTT_INVALID_PEER;
  295. ts.tid = HTT_INVALID_TID;
  296. }
  297. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  298. ts.ppdu_id =
  299. DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(
  300. htt_desc[2]);
  301. ts.ack_frame_rssi =
  302. DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(
  303. htt_desc[2]);
  304. transmit_cnt_valid =
  305. DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(
  306. htt_desc[3]);
  307. if (transmit_cnt_valid)
  308. ts.transmit_cnt =
  309. HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(
  310. htt_desc[1]);
  311. ts.tsf = htt_desc[4];
  312. ts.first_msdu = 1;
  313. ts.last_msdu = 1;
  314. switch (tx_status) {
  315. case HTT_TX_FW2WBM_TX_STATUS_OK:
  316. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  317. break;
  318. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  319. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  320. break;
  321. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  322. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  323. break;
  324. }
  325. tid = ts.tid;
  326. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  327. tid = CDP_MAX_DATA_TIDS - 1;
  328. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  329. if (qdf_unlikely(pdev->delay_stats_flag) ||
  330. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  331. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  332. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  333. tid_stats->htt_status_cnt[tx_status]++;
  334. peer_id = dp_tx_comp_adjust_peer_id_be(soc, ts.peer_id);
  335. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  336. &txrx_ref_handle,
  337. DP_MOD_ID_HTT_COMP);
  338. if (qdf_likely(txrx_peer))
  339. dp_tx_update_peer_basic_stats(
  340. txrx_peer,
  341. qdf_nbuf_len(tx_desc->nbuf),
  342. tx_status,
  343. pdev->enhanced_stats_en);
  344. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  345. ring_id);
  346. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  347. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  348. if (qdf_likely(txrx_peer))
  349. dp_txrx_peer_unref_delete(txrx_ref_handle,
  350. DP_MOD_ID_HTT_COMP);
  351. break;
  352. }
  353. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  354. {
  355. uint8_t reinject_reason;
  356. reinject_reason =
  357. HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(
  358. htt_desc[1]);
  359. dp_tx_reinject_handler(soc, vdev, tx_desc,
  360. status, reinject_reason);
  361. break;
  362. }
  363. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  364. {
  365. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  366. break;
  367. }
  368. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  369. {
  370. xmit_type = qdf_nbuf_get_vdev_xmit_type(tx_desc->nbuf);
  371. DP_STATS_INC(vdev,
  372. tx_i[xmit_type].dropped.fail_per_pkt_vdev_id_check,
  373. 1);
  374. goto release_tx_desc;
  375. }
  376. default:
  377. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  378. tx_status);
  379. goto release_tx_desc;
  380. }
  381. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  382. return;
  383. release_tx_desc:
  384. dp_tx_comp_free_buf(soc, tx_desc, false);
  385. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  386. if (vdev)
  387. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  388. }
  389. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  390. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  391. /**
  392. * dp_tx_get_rbm_id_be() - Get the RBM ID for data transmission completion.
  393. * @soc: DP soc structure pointer
  394. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  395. *
  396. * Return: RBM ID corresponding to TCL ring_id
  397. */
  398. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  399. uint8_t ring_id)
  400. {
  401. return 0;
  402. }
  403. #else
  404. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  405. uint8_t ring_id)
  406. {
  407. return (ring_id ? soc->wbm_sw0_bm_id + (ring_id - 1) :
  408. HAL_WBM_SW2_BM_ID(soc->wbm_sw0_bm_id));
  409. }
  410. #endif /*DP_TX_IMPLICIT_RBM_MAPPING*/
  411. #else
  412. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  413. uint8_t tcl_index)
  414. {
  415. uint8_t rbm;
  416. rbm = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_index);
  417. dp_verbose_debug("tcl_id %u rbm %u", tcl_index, rbm);
  418. return rbm;
  419. }
  420. #endif
  421. #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES
  422. /**
  423. * dp_tx_set_min_rates_for_critical_frames()- sets min-rates for critical pkts
  424. * @soc: DP soc structure pointer
  425. * @hal_tx_desc: HAL descriptor where fields are set
  426. * @nbuf: skb to be considered for min rates
  427. *
  428. * The function relies on upper layers to set QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL
  429. * and uses it to determine if the frame is critical. For a critical frame,
  430. * flow override bits are set to classify the frame into HW's high priority
  431. * queue. The HW will pick pre-configured min rates for such packets.
  432. *
  433. * Return: None
  434. */
  435. static void
  436. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  437. uint32_t *hal_tx_desc,
  438. qdf_nbuf_t nbuf)
  439. {
  440. /*
  441. * Critical frames should be queued to the high priority queue for the TID on
  442. * on which they are sent out (for the concerned peer).
  443. * FW is using HTT_MSDU_Q_IDX 2 for HOL (high priority) queue.
  444. * htt_msdu_idx = (2 * who_classify_info_sel) + flow_override
  445. * Hence, using who_classify_info_sel = 1, flow_override = 0 to select
  446. * HOL queue.
  447. */
  448. if (QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL(nbuf)) {
  449. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  450. hal_tx_desc_set_flow_override(hal_tx_desc, 0);
  451. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  452. hal_tx_desc_set_tx_notify_frame(hal_tx_desc,
  453. TX_SEMI_HARD_NOTIFY_E);
  454. }
  455. }
  456. #else
  457. static inline void
  458. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  459. uint32_t *hal_tx_desc_cached,
  460. qdf_nbuf_t nbuf)
  461. {
  462. }
  463. #endif
  464. #ifdef DP_TX_PACKET_INSPECT_FOR_ILP
  465. /**
  466. * dp_tx_set_particular_tx_queue() - set particular TX TQM flow queue 3 for
  467. * TX packets, currently TCP ACK only
  468. * @soc: DP soc structure pointer
  469. * @hal_tx_desc: HAL descriptor where fields are set
  470. * @nbuf: skb to be considered for particular TX queue
  471. *
  472. * Return: None
  473. */
  474. static inline
  475. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  476. uint32_t *hal_tx_desc,
  477. qdf_nbuf_t nbuf)
  478. {
  479. if (!soc->tx_ilp_enable)
  480. return;
  481. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  482. QDF_NBUF_CB_PACKET_TYPE_TCP_ACK)) {
  483. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  484. hal_tx_desc_set_flow_override(hal_tx_desc, 1);
  485. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  486. }
  487. }
  488. #else
  489. static inline
  490. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  491. uint32_t *hal_tx_desc,
  492. qdf_nbuf_t nbuf)
  493. {
  494. }
  495. #endif
  496. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  497. defined(WLAN_MCAST_MLO)
  498. #ifdef QCA_MULTIPASS_SUPPORT
  499. /**
  500. * dp_tx_mlo_mcast_multipass_lookup() - lookup vlan_id in mpass peer list
  501. * @be_vdev: Handle to DP be_vdev structure
  502. * @ptnr_vdev: DP ptnr_vdev handle
  503. * @arg: pointer to dp_mlo_mpass_ buf
  504. *
  505. * Return: None
  506. */
  507. static void
  508. dp_tx_mlo_mcast_multipass_lookup(struct dp_vdev_be *be_vdev,
  509. struct dp_vdev *ptnr_vdev,
  510. void *arg)
  511. {
  512. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  513. struct dp_txrx_peer *txrx_peer = NULL;
  514. struct vlan_ethhdr *veh = NULL;
  515. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(ptr->nbuf);
  516. uint16_t vlan_id = 0;
  517. bool not_vlan = ((ptnr_vdev->tx_encap_type == htt_cmn_pkt_type_raw) ||
  518. (htons(eh->ether_type) != ETH_P_8021Q));
  519. if (qdf_unlikely(not_vlan))
  520. return;
  521. veh = (struct vlan_ethhdr *)eh;
  522. vlan_id = (ntohs(veh->h_vlan_TCI) & VLAN_VID_MASK);
  523. qdf_spin_lock_bh(&ptnr_vdev->mpass_peer_mutex);
  524. TAILQ_FOREACH(txrx_peer, &ptnr_vdev->mpass_peer_list,
  525. mpass_peer_list_elem) {
  526. if (vlan_id == txrx_peer->vlan_id) {
  527. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  528. ptr->vlan_id = vlan_id;
  529. return;
  530. }
  531. }
  532. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  533. }
  534. /**
  535. * dp_tx_mlo_mcast_multipass_send() - send multipass MLO Mcast packets
  536. * @be_vdev: Handle to DP be_vdev structure
  537. * @ptnr_vdev: DP ptnr_vdev handle
  538. * @arg: pointer to dp_mlo_mpass_ buf
  539. *
  540. * Return: None
  541. */
  542. static void
  543. dp_tx_mlo_mcast_multipass_send(struct dp_vdev_be *be_vdev,
  544. struct dp_vdev *ptnr_vdev,
  545. void *arg)
  546. {
  547. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  548. struct dp_tx_msdu_info_s msdu_info;
  549. struct dp_vdev_be *be_ptnr_vdev = NULL;
  550. qdf_nbuf_t nbuf_clone;
  551. uint16_t group_key = 0;
  552. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  553. if (be_vdev != be_ptnr_vdev) {
  554. nbuf_clone = qdf_nbuf_clone(ptr->nbuf);
  555. if (qdf_unlikely(!nbuf_clone)) {
  556. dp_tx_debug("nbuf clone failed");
  557. return;
  558. }
  559. } else {
  560. nbuf_clone = ptr->nbuf;
  561. }
  562. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  563. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  564. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  565. msdu_info.xmit_type = qdf_nbuf_get_vdev_xmit_type(ptr->nbuf);
  566. if (ptr->vlan_id == MULTIPASS_WITH_VLAN_ID) {
  567. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  568. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(
  569. msdu_info.meta_data[0], 1);
  570. } else {
  571. /* return when vlan map is not initialized */
  572. if (!ptnr_vdev->iv_vlan_map)
  573. return;
  574. group_key = ptnr_vdev->iv_vlan_map[ptr->vlan_id];
  575. /*
  576. * If group key is not installed, drop the frame.
  577. */
  578. if (!group_key)
  579. return;
  580. dp_tx_remove_vlan_tag(ptnr_vdev, nbuf_clone);
  581. dp_tx_add_groupkey_metadata(ptnr_vdev, &msdu_info, group_key);
  582. msdu_info.exception_fw = 1;
  583. }
  584. nbuf_clone = dp_tx_send_msdu_single(
  585. ptnr_vdev,
  586. nbuf_clone,
  587. &msdu_info,
  588. DP_MLO_MCAST_REINJECT_PEER_ID,
  589. NULL);
  590. if (qdf_unlikely(nbuf_clone)) {
  591. dp_info("pkt send failed");
  592. qdf_nbuf_free(nbuf_clone);
  593. return;
  594. }
  595. }
  596. /**
  597. * dp_tx_mlo_mcast_multipass_handler - If frame needs multipass processing
  598. * @soc: DP soc handle
  599. * @vdev: DP vdev handle
  600. * @nbuf: nbuf to be enqueued
  601. *
  602. * Return: true if handling is done else false
  603. */
  604. static bool
  605. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc,
  606. struct dp_vdev *vdev,
  607. qdf_nbuf_t nbuf)
  608. {
  609. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  610. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  611. qdf_nbuf_t nbuf_copy = NULL;
  612. struct dp_mlo_mpass_buf mpass_buf;
  613. memset(&mpass_buf, 0, sizeof(struct dp_mlo_mpass_buf));
  614. mpass_buf.vlan_id = INVALID_VLAN_ID;
  615. mpass_buf.nbuf = nbuf;
  616. dp_tx_mlo_mcast_multipass_lookup(be_vdev, vdev, &mpass_buf);
  617. if (mpass_buf.vlan_id == INVALID_VLAN_ID) {
  618. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  619. dp_tx_mlo_mcast_multipass_lookup,
  620. &mpass_buf, DP_MOD_ID_TX,
  621. DP_ALL_VDEV_ITER,
  622. DP_VDEV_ITERATE_SKIP_SELF);
  623. /*
  624. * Do not drop the frame when vlan_id doesn't match.
  625. * Send the frame as it is.
  626. */
  627. if (mpass_buf.vlan_id == INVALID_VLAN_ID)
  628. return false;
  629. }
  630. /* AP can have classic clients, special clients &
  631. * classic repeaters.
  632. * 1. Classic clients & special client:
  633. * Remove vlan header, find corresponding group key
  634. * index, fill in metaheader and enqueue multicast
  635. * frame to TCL.
  636. * 2. Classic repeater:
  637. * Pass through to classic repeater with vlan tag
  638. * intact without any group key index. Hardware
  639. * will know which key to use to send frame to
  640. * repeater.
  641. */
  642. nbuf_copy = qdf_nbuf_copy(nbuf);
  643. /*
  644. * Send multicast frame to special peers even
  645. * if pass through to classic repeater fails.
  646. */
  647. if (nbuf_copy) {
  648. struct dp_mlo_mpass_buf mpass_buf_copy = {0};
  649. mpass_buf_copy.vlan_id = MULTIPASS_WITH_VLAN_ID;
  650. mpass_buf_copy.nbuf = nbuf_copy;
  651. /* send frame on partner vdevs */
  652. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  653. dp_tx_mlo_mcast_multipass_send,
  654. &mpass_buf_copy, DP_MOD_ID_TX,
  655. DP_LINK_VDEV_ITER,
  656. DP_VDEV_ITERATE_SKIP_SELF);
  657. /* send frame on mcast primary vdev */
  658. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf_copy);
  659. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  660. be_vdev->mlo_dev_ctxt->seq_num = 0;
  661. else
  662. be_vdev->mlo_dev_ctxt->seq_num++;
  663. }
  664. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  665. dp_tx_mlo_mcast_multipass_send,
  666. &mpass_buf, DP_MOD_ID_TX, DP_LINK_VDEV_ITER,
  667. DP_VDEV_ITERATE_SKIP_SELF);
  668. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf);
  669. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  670. be_vdev->mlo_dev_ctxt->seq_num = 0;
  671. else
  672. be_vdev->mlo_dev_ctxt->seq_num++;
  673. return true;
  674. }
  675. #else
  676. static bool
  677. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  678. qdf_nbuf_t nbuf)
  679. {
  680. return false;
  681. }
  682. #endif
  683. void
  684. dp_tx_mlo_mcast_pkt_send(struct dp_vdev_be *be_vdev,
  685. struct dp_vdev *ptnr_vdev,
  686. void *arg)
  687. {
  688. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  689. qdf_nbuf_t nbuf_clone;
  690. struct dp_vdev_be *be_ptnr_vdev = NULL;
  691. struct dp_tx_msdu_info_s msdu_info;
  692. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  693. if (be_vdev != be_ptnr_vdev) {
  694. nbuf_clone = qdf_nbuf_clone(nbuf);
  695. if (qdf_unlikely(!nbuf_clone)) {
  696. dp_tx_debug("nbuf clone failed");
  697. return;
  698. }
  699. } else {
  700. nbuf_clone = nbuf;
  701. }
  702. /* NAWDS clients will accepts on 4 addr format MCAST packets
  703. * This will ensure to send packets in 4 addr format to NAWDS clients.
  704. */
  705. if (qdf_unlikely(ptnr_vdev->nawds_enabled)) {
  706. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  707. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  708. dp_tx_nawds_handler(ptnr_vdev->pdev->soc, ptnr_vdev,
  709. &msdu_info, nbuf_clone, DP_INVALID_PEER);
  710. }
  711. if (qdf_unlikely(dp_tx_proxy_arp(ptnr_vdev, nbuf_clone) !=
  712. QDF_STATUS_SUCCESS)) {
  713. qdf_nbuf_free(nbuf_clone);
  714. return;
  715. }
  716. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  717. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  718. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  719. msdu_info.xmit_type = qdf_nbuf_get_vdev_xmit_type(nbuf_clone);
  720. DP_STATS_INC(ptnr_vdev,
  721. tx_i[msdu_info.xmit_type].mlo_mcast.send_pkt_count, 1);
  722. nbuf_clone = dp_tx_send_msdu_single(
  723. ptnr_vdev,
  724. nbuf_clone,
  725. &msdu_info,
  726. DP_MLO_MCAST_REINJECT_PEER_ID,
  727. NULL);
  728. if (qdf_unlikely(nbuf_clone)) {
  729. DP_STATS_INC(ptnr_vdev,
  730. tx_i[msdu_info.xmit_type].mlo_mcast.fail_pkt_count,
  731. 1);
  732. dp_info("pkt send failed");
  733. qdf_nbuf_free(nbuf_clone);
  734. return;
  735. }
  736. }
  737. static inline void
  738. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  739. struct dp_vdev *vdev,
  740. struct dp_tx_msdu_info_s *msdu_info)
  741. {
  742. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, msdu_info->vdev_id);
  743. }
  744. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  745. struct dp_vdev *vdev,
  746. qdf_nbuf_t nbuf)
  747. {
  748. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  749. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  750. if (qdf_unlikely(vdev->multipass_en) &&
  751. dp_tx_mlo_mcast_multipass_handler(soc, vdev, nbuf))
  752. return;
  753. /* send frame on partner vdevs */
  754. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  755. dp_tx_mlo_mcast_pkt_send,
  756. nbuf, DP_MOD_ID_REINJECT, DP_LINK_VDEV_ITER,
  757. DP_VDEV_ITERATE_SKIP_SELF);
  758. /* send frame on mcast primary vdev */
  759. dp_tx_mlo_mcast_pkt_send(be_vdev, vdev, nbuf);
  760. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  761. be_vdev->mlo_dev_ctxt->seq_num = 0;
  762. else
  763. be_vdev->mlo_dev_ctxt->seq_num++;
  764. }
  765. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  766. struct dp_vdev *vdev)
  767. {
  768. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  769. if (be_vdev->mcast_primary)
  770. return true;
  771. return false;
  772. }
  773. #if defined(CONFIG_MLO_SINGLE_DEV)
  774. static void
  775. dp_tx_mlo_mcast_enhance_be(struct dp_vdev_be *be_vdev,
  776. struct dp_vdev *ptnr_vdev,
  777. void *arg)
  778. {
  779. struct dp_vdev *vdev = (struct dp_vdev *)be_vdev;
  780. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  781. if (vdev == ptnr_vdev)
  782. return;
  783. /*
  784. * Hold the reference to avoid free of nbuf in
  785. * dp_tx_mcast_enhance() in case of successful
  786. * conversion
  787. */
  788. qdf_nbuf_ref(nbuf);
  789. if (qdf_unlikely(!dp_tx_mcast_enhance(ptnr_vdev, nbuf)))
  790. return;
  791. qdf_nbuf_free(nbuf);
  792. }
  793. qdf_nbuf_t
  794. dp_tx_mlo_mcast_send_be(struct dp_soc *soc, struct dp_vdev *vdev,
  795. qdf_nbuf_t nbuf,
  796. struct cdp_tx_exception_metadata *tx_exc_metadata)
  797. {
  798. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  799. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  800. if (!tx_exc_metadata->is_mlo_mcast)
  801. return nbuf;
  802. if (!be_vdev->mcast_primary) {
  803. qdf_nbuf_free(nbuf);
  804. return NULL;
  805. }
  806. /*
  807. * In the single netdev model avoid reinjection path as mcast
  808. * packet is identified in upper layers while peer search to find
  809. * primary TQM based on dest mac addr
  810. *
  811. * New bonding interface added into the bridge so MCSD will update
  812. * snooping table and wifi driver populates the entries in appropriate
  813. * child net devices.
  814. */
  815. if (vdev->mcast_enhancement_en) {
  816. /*
  817. * As dp_tx_mcast_enhance() can consume the nbuf incase of
  818. * successful conversion hold the reference of nbuf.
  819. *
  820. * Hold the reference to tx on partner links
  821. */
  822. qdf_nbuf_ref(nbuf);
  823. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf))) {
  824. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  825. dp_tx_mlo_mcast_enhance_be,
  826. nbuf, DP_MOD_ID_TX,
  827. DP_ALL_VDEV_ITER,
  828. DP_VDEV_ITERATE_SKIP_SELF);
  829. qdf_nbuf_free(nbuf);
  830. return NULL;
  831. }
  832. /* release reference taken above */
  833. qdf_nbuf_free(nbuf);
  834. }
  835. dp_tx_mlo_mcast_handler_be(soc, vdev, nbuf);
  836. return NULL;
  837. }
  838. #endif
  839. #else
  840. static inline void
  841. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  842. struct dp_vdev *vdev,
  843. struct dp_tx_msdu_info_s *msdu_info)
  844. {
  845. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, vdev->vdev_id);
  846. }
  847. #endif
  848. #if defined(WLAN_FEATURE_11BE_MLO) && !defined(WLAN_MLO_MULTI_CHIP) && \
  849. !defined(WLAN_MCAST_MLO)
  850. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  851. struct dp_vdev *vdev,
  852. qdf_nbuf_t nbuf)
  853. {
  854. }
  855. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  856. struct dp_vdev *vdev)
  857. {
  858. return false;
  859. }
  860. #endif
  861. #ifdef CONFIG_SAWF
  862. /**
  863. * dp_sawf_config_be - Configure sawf specific fields in tcl
  864. *
  865. * @soc: DP soc handle
  866. * @hal_tx_desc_cached: tx descriptor
  867. * @fw_metadata: firmware metadata
  868. * @nbuf: skb buffer
  869. * @msdu_info: msdu info
  870. *
  871. * Return: void
  872. */
  873. void dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  874. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  875. struct dp_tx_msdu_info_s *msdu_info)
  876. {
  877. uint8_t q_id = 0;
  878. q_id = dp_sawf_queue_id_get(nbuf);
  879. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  880. return;
  881. msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
  882. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  883. (q_id & (CDP_DATA_TID_MAX - 1)));
  884. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  885. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  886. return;
  887. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  888. return;
  889. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  890. hal_tx_desc_set_flow_override_enable(hal_tx_desc_cached,
  891. DP_TX_FLOW_OVERRIDE_ENABLE);
  892. hal_tx_desc_set_flow_override(hal_tx_desc_cached,
  893. DP_TX_FLOW_OVERRIDE_GET(q_id));
  894. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc_cached,
  895. DP_TX_WHO_CLFY_INF_SEL_GET(q_id));
  896. }
  897. #else
  898. static inline
  899. void dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  900. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  901. struct dp_tx_msdu_info_s *msdu_info)
  902. {
  903. }
  904. static inline
  905. QDF_STATUS dp_sawf_tx_enqueue_peer_stats(struct dp_soc *soc,
  906. struct dp_tx_desc_s *tx_desc)
  907. {
  908. return QDF_STATUS_SUCCESS;
  909. }
  910. static inline
  911. QDF_STATUS dp_sawf_tx_enqueue_fail_peer_stats(struct dp_soc *soc,
  912. struct dp_tx_desc_s *tx_desc)
  913. {
  914. return QDF_STATUS_SUCCESS;
  915. }
  916. #endif
  917. #ifdef WLAN_SUPPORT_PPEDS
  918. /**
  919. * dp_ppeds_stats() - Accounting fw2wbm_tx_drop drops in Tx path
  920. * @soc: Handle to DP Soc structure
  921. * @peer_id: Peer ID in the descriptor
  922. *
  923. * Return: NONE
  924. */
  925. static inline
  926. void dp_ppeds_stats(struct dp_soc *soc, uint16_t peer_id)
  927. {
  928. struct dp_vdev *vdev = NULL;
  929. struct dp_txrx_peer *txrx_peer = NULL;
  930. dp_txrx_ref_handle txrx_ref_handle = NULL;
  931. DP_STATS_INC(soc, tx.fw2wbm_tx_drop, 1);
  932. txrx_peer = dp_txrx_peer_get_ref_by_id(soc,
  933. peer_id,
  934. &txrx_ref_handle,
  935. DP_MOD_ID_TX_COMP);
  936. if (txrx_peer) {
  937. vdev = txrx_peer->vdev;
  938. DP_STATS_INC(vdev, tx_i[DP_XMIT_LINK].dropped.fw2wbm_tx_drop, 1);
  939. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  940. }
  941. }
  942. int dp_ppeds_tx_comp_handler(struct dp_soc_be *be_soc, uint32_t quota)
  943. {
  944. uint32_t num_avail_for_reap = 0;
  945. void *tx_comp_hal_desc;
  946. uint8_t buf_src, status = 0;
  947. uint32_t count = 0;
  948. struct dp_tx_desc_s *tx_desc = NULL;
  949. struct dp_tx_desc_s *head_desc = NULL;
  950. struct dp_tx_desc_s *tail_desc = NULL;
  951. struct dp_soc *soc = &be_soc->soc;
  952. void *last_prefetch_hw_desc = NULL;
  953. struct dp_tx_desc_s *last_prefetch_sw_desc = NULL;
  954. qdf_nbuf_t nbuf;
  955. hal_soc_handle_t hal_soc = soc->hal_soc;
  956. hal_ring_handle_t hal_ring_hdl =
  957. be_soc->ppeds_wbm_release_ring.hal_srng;
  958. struct dp_txrx_peer *txrx_peer = NULL;
  959. uint16_t peer_id = CDP_INVALID_PEER;
  960. dp_txrx_ref_handle txrx_ref_handle = NULL;
  961. struct dp_vdev *vdev = NULL;
  962. struct dp_pdev *pdev = NULL;
  963. struct dp_srng *srng;
  964. if (qdf_unlikely(dp_srng_access_start(NULL, soc, hal_ring_hdl))) {
  965. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  966. return 0;
  967. }
  968. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  969. if (num_avail_for_reap >= quota)
  970. num_avail_for_reap = quota;
  971. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  972. last_prefetch_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  973. num_avail_for_reap);
  974. srng = &be_soc->ppeds_wbm_release_ring;
  975. if (srng) {
  976. hal_update_ring_util(soc->hal_soc, srng->hal_srng,
  977. WBM2SW_RELEASE,
  978. &be_soc->ppeds_wbm_release_ring.stats);
  979. }
  980. while (qdf_likely(num_avail_for_reap--)) {
  981. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  982. if (qdf_unlikely(!tx_comp_hal_desc))
  983. break;
  984. buf_src = hal_tx_comp_get_buffer_source(hal_soc,
  985. tx_comp_hal_desc);
  986. if (qdf_unlikely(buf_src != HAL_TX_COMP_RELEASE_SOURCE_TQM &&
  987. buf_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  988. dp_err("Tx comp release_src != TQM | FW but from %d",
  989. buf_src);
  990. dp_assert_always_internal_ds_stat(0, be_soc,
  991. tx.tx_comp_buf_src);
  992. continue;
  993. }
  994. dp_tx_comp_get_params_from_hal_desc_be(soc, tx_comp_hal_desc,
  995. &tx_desc);
  996. if (!tx_desc) {
  997. dp_err("unable to retrieve tx_desc!");
  998. dp_assert_always_internal_ds_stat(0, be_soc,
  999. tx.tx_comp_desc_null);
  1000. continue;
  1001. }
  1002. if (qdf_unlikely(!(tx_desc->flags &
  1003. DP_TX_DESC_FLAG_ALLOCATED) ||
  1004. !(tx_desc->flags & DP_TX_DESC_FLAG_PPEDS))) {
  1005. dp_assert_always_internal_ds_stat(0, be_soc,
  1006. tx.tx_comp_invalid_flag);
  1007. continue;
  1008. }
  1009. tx_desc->buffer_src = buf_src;
  1010. if (qdf_unlikely(buf_src == HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1011. status = hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1012. if (status != HTT_TX_FW2WBM_TX_STATUS_OK)
  1013. dp_ppeds_stats(soc, tx_desc->peer_id);
  1014. nbuf = dp_ppeds_tx_desc_free(soc, tx_desc);
  1015. qdf_nbuf_free(nbuf);
  1016. } else {
  1017. tx_desc->tx_status =
  1018. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1019. /*
  1020. * Add desc sync to account for extended statistics
  1021. * during Tx completion.
  1022. */
  1023. if (peer_id != tx_desc->peer_id) {
  1024. if (txrx_peer) {
  1025. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1026. DP_MOD_ID_TX_COMP);
  1027. txrx_peer = NULL;
  1028. vdev = NULL;
  1029. pdev = NULL;
  1030. }
  1031. peer_id = tx_desc->peer_id;
  1032. txrx_peer =
  1033. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  1034. &txrx_ref_handle,
  1035. DP_MOD_ID_TX_COMP);
  1036. if (txrx_peer) {
  1037. vdev = txrx_peer->vdev;
  1038. if (!vdev)
  1039. goto next_desc;
  1040. pdev = vdev->pdev;
  1041. if (!pdev)
  1042. goto next_desc;
  1043. dp_tx_desc_update_fast_comp_flag(soc,
  1044. tx_desc,
  1045. !pdev->enhanced_stats_en);
  1046. if (pdev->enhanced_stats_en) {
  1047. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1048. &tx_desc->comp, 1);
  1049. }
  1050. }
  1051. } else if (txrx_peer && vdev && pdev) {
  1052. dp_tx_desc_update_fast_comp_flag(soc,
  1053. tx_desc,
  1054. !pdev->enhanced_stats_en);
  1055. if (pdev->enhanced_stats_en) {
  1056. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1057. &tx_desc->comp, 1);
  1058. }
  1059. }
  1060. next_desc:
  1061. if (!head_desc) {
  1062. head_desc = tx_desc;
  1063. tail_desc = tx_desc;
  1064. }
  1065. tail_desc->next = tx_desc;
  1066. tx_desc->next = NULL;
  1067. tail_desc = tx_desc;
  1068. count++;
  1069. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  1070. num_avail_for_reap,
  1071. hal_ring_hdl,
  1072. &last_prefetch_hw_desc,
  1073. &last_prefetch_sw_desc);
  1074. }
  1075. }
  1076. dp_srng_access_end(NULL, soc, hal_ring_hdl);
  1077. if (txrx_peer)
  1078. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1079. DP_MOD_ID_TX_COMP);
  1080. if (head_desc)
  1081. dp_tx_comp_process_desc_list(soc, head_desc,
  1082. CDP_MAX_TX_COMP_PPE_RING);
  1083. return count;
  1084. }
  1085. #endif
  1086. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  1087. static inline void
  1088. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1089. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1090. uint16_t *ast_idx, uint16_t *ast_hash)
  1091. {
  1092. struct dp_peer *peer = NULL;
  1093. if (tx_exc_metadata->is_wds_extended) {
  1094. peer = dp_peer_get_ref_by_id(soc, tx_exc_metadata->peer_id,
  1095. DP_MOD_ID_TX);
  1096. if (peer) {
  1097. *ast_idx = peer->ast_idx;
  1098. *ast_hash = peer->ast_hash;
  1099. hal_tx_desc_set_index_lookup_override
  1100. (soc->hal_soc,
  1101. hal_tx_desc_cached,
  1102. 0x1);
  1103. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  1104. }
  1105. } else {
  1106. return;
  1107. }
  1108. }
  1109. #else
  1110. static inline void
  1111. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1112. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1113. uint16_t *ast_idx, uint16_t *ast_hash)
  1114. {
  1115. }
  1116. #endif
  1117. QDF_STATUS
  1118. dp_tx_hw_enqueue_be(struct dp_soc *soc, struct dp_vdev *vdev,
  1119. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1120. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1121. struct dp_tx_msdu_info_s *msdu_info)
  1122. {
  1123. void *hal_tx_desc;
  1124. uint32_t *hal_tx_desc_cached;
  1125. int coalesce = 0;
  1126. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1127. uint8_t ring_id = tx_q->ring_id;
  1128. uint8_t tid;
  1129. struct dp_vdev_be *be_vdev;
  1130. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1131. uint8_t bm_id = dp_tx_get_rbm_id_be(soc, ring_id);
  1132. hal_ring_handle_t hal_ring_hdl = NULL;
  1133. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1134. uint8_t num_desc_bytes = HAL_TX_DESC_LEN_BYTES;
  1135. uint16_t ast_idx = vdev->bss_ast_idx;
  1136. uint16_t ast_hash = vdev->bss_ast_hash;
  1137. be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1138. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1139. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1140. return QDF_STATUS_E_RESOURCES;
  1141. }
  1142. if (qdf_unlikely(tx_exc_metadata)) {
  1143. qdf_assert_always((tx_exc_metadata->tx_encap_type ==
  1144. CDP_INVALID_TX_ENCAP_TYPE) ||
  1145. (tx_exc_metadata->tx_encap_type ==
  1146. vdev->tx_encap_type));
  1147. if (tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)
  1148. qdf_assert_always((tx_exc_metadata->sec_type ==
  1149. CDP_INVALID_SEC_TYPE) ||
  1150. tx_exc_metadata->sec_type ==
  1151. vdev->sec_type);
  1152. dp_get_peer_from_tx_exc_meta(soc, (void *)cached_desc,
  1153. tx_exc_metadata,
  1154. &ast_idx, &ast_hash);
  1155. }
  1156. hal_tx_desc_cached = (void *)cached_desc;
  1157. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  1158. dp_sawf_config_be(soc, hal_tx_desc_cached,
  1159. &fw_metadata, tx_desc->nbuf, msdu_info);
  1160. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  1161. }
  1162. hal_tx_desc_set_buf_addr_be(soc->hal_soc, hal_tx_desc_cached,
  1163. tx_desc->dma_addr, bm_id, tx_desc->id,
  1164. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1165. hal_tx_desc_set_lmac_id_be(soc->hal_soc, hal_tx_desc_cached,
  1166. vdev->lmac_id);
  1167. hal_tx_desc_set_search_index_be(soc->hal_soc, hal_tx_desc_cached,
  1168. ast_idx);
  1169. /*
  1170. * Bank_ID is used as DSCP_TABLE number in beryllium
  1171. * So there is no explicit field used for DSCP_TID_TABLE_NUM.
  1172. */
  1173. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1174. (ast_hash & 0xF));
  1175. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1176. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1177. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1178. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1179. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1180. /* verify checksum offload configuration*/
  1181. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  1182. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  1183. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  1184. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1185. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1186. }
  1187. hal_tx_desc_set_bank_id(hal_tx_desc_cached, vdev->bank_id);
  1188. dp_tx_vdev_id_set_hal_tx_desc(hal_tx_desc_cached, vdev, msdu_info);
  1189. tid = msdu_info->tid;
  1190. if (tid != HTT_TX_EXT_TID_INVALID)
  1191. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1192. dp_tx_set_min_rates_for_critical_frames(soc, hal_tx_desc_cached,
  1193. tx_desc->nbuf);
  1194. dp_tx_set_particular_tx_queue(soc, hal_tx_desc_cached,
  1195. tx_desc->nbuf);
  1196. dp_tx_desc_set_ktimestamp(vdev, tx_desc);
  1197. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1198. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1199. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1200. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1201. DP_STATS_INC(vdev,
  1202. tx_i[msdu_info->xmit_type].dropped.enqueue_fail,
  1203. 1);
  1204. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1205. return status;
  1206. }
  1207. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1208. if (qdf_unlikely(!hal_tx_desc)) {
  1209. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1210. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1211. DP_STATS_INC(vdev,
  1212. tx_i[msdu_info->xmit_type].dropped.enqueue_fail,
  1213. 1);
  1214. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1215. goto ring_access_fail;
  1216. }
  1217. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1218. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1219. /* Sync cached descriptor with HW */
  1220. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc, num_desc_bytes);
  1221. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  1222. msdu_info, ring_id);
  1223. DP_STATS_INC_PKT(vdev, tx_i[msdu_info->xmit_type].processed, 1,
  1224. dp_tx_get_pkt_len(tx_desc));
  1225. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  1226. dp_tx_update_stats(soc, tx_desc, ring_id);
  1227. status = QDF_STATUS_SUCCESS;
  1228. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  1229. hal_ring_hdl, soc, ring_id);
  1230. ring_access_fail:
  1231. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1232. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  1233. qdf_get_log_timestamp(), tx_desc->nbuf);
  1234. return status;
  1235. }
  1236. #ifdef IPA_OFFLOAD
  1237. static void
  1238. dp_tx_get_ipa_bank_config(struct dp_soc_be *be_soc,
  1239. union hal_tx_bank_config *bank_config)
  1240. {
  1241. bank_config->epd = 0;
  1242. bank_config->encap_type = wlan_cfg_pkt_type(be_soc->soc.wlan_cfg_ctx);
  1243. bank_config->encrypt_type = 0;
  1244. bank_config->src_buffer_swap = 0;
  1245. bank_config->link_meta_swap = 0;
  1246. bank_config->index_lookup_enable = 0;
  1247. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1248. bank_config->addrx_en = 1;
  1249. bank_config->addry_en = 1;
  1250. bank_config->mesh_enable = 0;
  1251. bank_config->dscp_tid_map_id = 0;
  1252. bank_config->vdev_id_check_en = 0;
  1253. bank_config->pmac_id = 0;
  1254. }
  1255. static void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1256. {
  1257. union hal_tx_bank_config ipa_config = {0};
  1258. int bid;
  1259. if (!wlan_cfg_is_ipa_enabled(be_soc->soc.wlan_cfg_ctx)) {
  1260. be_soc->ipa_bank_id = DP_BE_INVALID_BANK_ID;
  1261. return;
  1262. }
  1263. dp_tx_get_ipa_bank_config(be_soc, &ipa_config);
  1264. /* Let IPA use last HOST owned bank */
  1265. bid = be_soc->num_bank_profiles - 1;
  1266. be_soc->bank_profiles[bid].is_configured = true;
  1267. be_soc->bank_profiles[bid].bank_config.val = ipa_config.val;
  1268. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1269. &be_soc->bank_profiles[bid].bank_config,
  1270. bid);
  1271. qdf_atomic_inc(&be_soc->bank_profiles[bid].ref_count);
  1272. dp_info("IPA bank at slot %d config:0x%x", bid,
  1273. be_soc->bank_profiles[bid].bank_config.val);
  1274. be_soc->ipa_bank_id = bid;
  1275. }
  1276. #else /* !IPA_OFFLOAD */
  1277. static inline void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1278. {
  1279. }
  1280. #endif /* IPA_OFFLOAD */
  1281. QDF_STATUS dp_tx_init_bank_profiles(struct dp_soc_be *be_soc)
  1282. {
  1283. int i, num_tcl_banks;
  1284. num_tcl_banks = hal_tx_get_num_tcl_banks(be_soc->soc.hal_soc);
  1285. dp_assert_always_internal(num_tcl_banks);
  1286. be_soc->num_bank_profiles = num_tcl_banks;
  1287. be_soc->bank_profiles = qdf_mem_malloc(num_tcl_banks *
  1288. sizeof(*be_soc->bank_profiles));
  1289. if (!be_soc->bank_profiles) {
  1290. dp_err("unable to allocate memory for DP TX Profiles!");
  1291. return QDF_STATUS_E_NOMEM;
  1292. }
  1293. DP_TX_BANK_LOCK_CREATE(&be_soc->tx_bank_lock);
  1294. for (i = 0; i < num_tcl_banks; i++) {
  1295. be_soc->bank_profiles[i].is_configured = false;
  1296. qdf_atomic_init(&be_soc->bank_profiles[i].ref_count);
  1297. }
  1298. dp_info("initialized %u bank profiles", be_soc->num_bank_profiles);
  1299. dp_tx_init_ipa_bank_profile(be_soc);
  1300. return QDF_STATUS_SUCCESS;
  1301. }
  1302. void dp_tx_deinit_bank_profiles(struct dp_soc_be *be_soc)
  1303. {
  1304. qdf_mem_free(be_soc->bank_profiles);
  1305. DP_TX_BANK_LOCK_DESTROY(&be_soc->tx_bank_lock);
  1306. }
  1307. static
  1308. void dp_tx_get_vdev_bank_config(struct dp_vdev_be *be_vdev,
  1309. union hal_tx_bank_config *bank_config)
  1310. {
  1311. struct dp_vdev *vdev = &be_vdev->vdev;
  1312. bank_config->epd = 0;
  1313. bank_config->encap_type = vdev->tx_encap_type;
  1314. /* Only valid for raw frames. Needs work for RAW mode */
  1315. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) {
  1316. bank_config->encrypt_type = sec_type_map[vdev->sec_type];
  1317. } else {
  1318. bank_config->encrypt_type = 0;
  1319. }
  1320. bank_config->src_buffer_swap = 0;
  1321. bank_config->link_meta_swap = 0;
  1322. if ((vdev->search_type == HAL_TX_ADDR_INDEX_SEARCH) &&
  1323. vdev->opmode == wlan_op_mode_sta) {
  1324. bank_config->index_lookup_enable = 1;
  1325. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_MEC_NOTIFY;
  1326. bank_config->addrx_en = 0;
  1327. bank_config->addry_en = 0;
  1328. } else {
  1329. bank_config->index_lookup_enable = 0;
  1330. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1331. bank_config->addrx_en =
  1332. (vdev->hal_desc_addr_search_flags &
  1333. HAL_TX_DESC_ADDRX_EN) ? 1 : 0;
  1334. bank_config->addry_en =
  1335. (vdev->hal_desc_addr_search_flags &
  1336. HAL_TX_DESC_ADDRY_EN) ? 1 : 0;
  1337. }
  1338. bank_config->mesh_enable = vdev->mesh_vdev ? 1 : 0;
  1339. bank_config->dscp_tid_map_id = vdev->dscp_tid_map_id;
  1340. /* Disabling vdev id check for now. Needs revist. */
  1341. bank_config->vdev_id_check_en = be_vdev->vdev_id_check_en;
  1342. bank_config->pmac_id = vdev->lmac_id;
  1343. }
  1344. int dp_tx_get_bank_profile(struct dp_soc_be *be_soc,
  1345. struct dp_vdev_be *be_vdev)
  1346. {
  1347. char *temp_str = "";
  1348. bool found_match = false;
  1349. int bank_id = DP_BE_INVALID_BANK_ID;
  1350. int i;
  1351. int unconfigured_slot = DP_BE_INVALID_BANK_ID;
  1352. int zero_ref_count_slot = DP_BE_INVALID_BANK_ID;
  1353. union hal_tx_bank_config vdev_config = {0};
  1354. /* convert vdev params into hal_tx_bank_config */
  1355. dp_tx_get_vdev_bank_config(be_vdev, &vdev_config);
  1356. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1357. /* go over all banks and find a matching/unconfigured/unused bank */
  1358. for (i = 0; i < be_soc->num_bank_profiles; i++) {
  1359. if (be_soc->bank_profiles[i].is_configured &&
  1360. (be_soc->bank_profiles[i].bank_config.val ^
  1361. vdev_config.val) == 0) {
  1362. found_match = true;
  1363. break;
  1364. }
  1365. if (unconfigured_slot == DP_BE_INVALID_BANK_ID &&
  1366. !be_soc->bank_profiles[i].is_configured)
  1367. unconfigured_slot = i;
  1368. else if (zero_ref_count_slot == DP_BE_INVALID_BANK_ID &&
  1369. !qdf_atomic_read(&be_soc->bank_profiles[i].ref_count))
  1370. zero_ref_count_slot = i;
  1371. }
  1372. if (found_match) {
  1373. temp_str = "matching";
  1374. bank_id = i;
  1375. goto inc_ref_and_return;
  1376. }
  1377. if (unconfigured_slot != DP_BE_INVALID_BANK_ID) {
  1378. temp_str = "unconfigured";
  1379. bank_id = unconfigured_slot;
  1380. goto configure_and_return;
  1381. }
  1382. if (zero_ref_count_slot != DP_BE_INVALID_BANK_ID) {
  1383. temp_str = "zero_ref_count";
  1384. bank_id = zero_ref_count_slot;
  1385. }
  1386. if (bank_id == DP_BE_INVALID_BANK_ID) {
  1387. dp_alert("unable to find TX bank!");
  1388. QDF_BUG(0);
  1389. return bank_id;
  1390. }
  1391. configure_and_return:
  1392. be_soc->bank_profiles[bank_id].is_configured = true;
  1393. be_soc->bank_profiles[bank_id].bank_config.val = vdev_config.val;
  1394. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1395. &be_soc->bank_profiles[bank_id].bank_config,
  1396. bank_id);
  1397. inc_ref_and_return:
  1398. qdf_atomic_inc(&be_soc->bank_profiles[bank_id].ref_count);
  1399. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1400. dp_info("found %s slot at index %d, input:0x%x match:0x%x ref_count %u",
  1401. temp_str, bank_id, vdev_config.val,
  1402. be_soc->bank_profiles[bank_id].bank_config.val,
  1403. qdf_atomic_read(&be_soc->bank_profiles[bank_id].ref_count));
  1404. dp_info("epd:%x encap:%x encryp:%x src_buf_swap:%x link_meta_swap:%x addrx_en:%x addry_en:%x mesh_en:%x vdev_id_check:%x pmac_id:%x mcast_pkt_ctrl:%x",
  1405. be_soc->bank_profiles[bank_id].bank_config.epd,
  1406. be_soc->bank_profiles[bank_id].bank_config.encap_type,
  1407. be_soc->bank_profiles[bank_id].bank_config.encrypt_type,
  1408. be_soc->bank_profiles[bank_id].bank_config.src_buffer_swap,
  1409. be_soc->bank_profiles[bank_id].bank_config.link_meta_swap,
  1410. be_soc->bank_profiles[bank_id].bank_config.addrx_en,
  1411. be_soc->bank_profiles[bank_id].bank_config.addry_en,
  1412. be_soc->bank_profiles[bank_id].bank_config.mesh_enable,
  1413. be_soc->bank_profiles[bank_id].bank_config.vdev_id_check_en,
  1414. be_soc->bank_profiles[bank_id].bank_config.pmac_id,
  1415. be_soc->bank_profiles[bank_id].bank_config.mcast_pkt_ctrl);
  1416. return bank_id;
  1417. }
  1418. void dp_tx_put_bank_profile(struct dp_soc_be *be_soc,
  1419. struct dp_vdev_be *be_vdev)
  1420. {
  1421. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1422. qdf_atomic_dec(&be_soc->bank_profiles[be_vdev->bank_id].ref_count);
  1423. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1424. }
  1425. void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
  1426. struct dp_vdev_be *be_vdev)
  1427. {
  1428. dp_tx_put_bank_profile(be_soc, be_vdev);
  1429. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  1430. be_vdev->vdev.bank_id = be_vdev->bank_id;
  1431. }
  1432. QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
  1433. uint32_t num_elem,
  1434. uint8_t pool_id,
  1435. bool spcl_tx_desc)
  1436. {
  1437. struct dp_tx_desc_pool_s *tx_desc_pool;
  1438. struct dp_hw_cookie_conversion_t *cc_ctx;
  1439. struct dp_spt_page_desc *page_desc;
  1440. struct dp_tx_desc_s *tx_desc;
  1441. uint32_t ppt_idx = 0;
  1442. uint32_t avail_entry_index = 0;
  1443. if (!num_elem) {
  1444. dp_err("desc_num 0 !!");
  1445. return QDF_STATUS_E_FAILURE;
  1446. }
  1447. if (spcl_tx_desc) {
  1448. tx_desc_pool = dp_get_spcl_tx_desc_pool(soc, pool_id);
  1449. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1450. } else {
  1451. tx_desc_pool = dp_get_tx_desc_pool(soc, pool_id);;
  1452. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1453. }
  1454. tx_desc = tx_desc_pool->freelist;
  1455. page_desc = &cc_ctx->page_desc_base[0];
  1456. while (tx_desc) {
  1457. if (avail_entry_index == 0) {
  1458. if (ppt_idx >= cc_ctx->total_page_num) {
  1459. dp_alert("insufficient secondary page tables");
  1460. qdf_assert_always(0);
  1461. }
  1462. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  1463. }
  1464. /* put each TX Desc VA to SPT pages and
  1465. * get corresponding ID
  1466. */
  1467. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  1468. avail_entry_index,
  1469. tx_desc);
  1470. tx_desc->id =
  1471. dp_cc_desc_id_generate(page_desc->ppt_index,
  1472. avail_entry_index);
  1473. tx_desc->pool_id = pool_id;
  1474. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  1475. tx_desc = tx_desc->next;
  1476. avail_entry_index = (avail_entry_index + 1) &
  1477. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  1478. }
  1479. return QDF_STATUS_SUCCESS;
  1480. }
  1481. void dp_tx_desc_pool_deinit_be(struct dp_soc *soc,
  1482. struct dp_tx_desc_pool_s *tx_desc_pool,
  1483. uint8_t pool_id, bool spcl_tx_desc)
  1484. {
  1485. struct dp_spt_page_desc *page_desc;
  1486. int i = 0;
  1487. struct dp_hw_cookie_conversion_t *cc_ctx;
  1488. if (spcl_tx_desc)
  1489. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1490. else
  1491. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1492. for (i = 0; i < cc_ctx->total_page_num; i++) {
  1493. page_desc = &cc_ctx->page_desc_base[i];
  1494. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  1495. }
  1496. }
  1497. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1498. uint32_t dp_tx_comp_nf_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  1499. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  1500. uint32_t quota)
  1501. {
  1502. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  1503. uint32_t work_done = 0;
  1504. if (dp_srng_get_near_full_level(soc, tx_comp_ring) <
  1505. DP_SRNG_THRESH_NEAR_FULL)
  1506. return 0;
  1507. qdf_atomic_set(&tx_comp_ring->near_full, 1);
  1508. work_done++;
  1509. return work_done;
  1510. }
  1511. #endif
  1512. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1513. defined(WLAN_CONFIG_TX_DELAY)
  1514. #define PPDUID_GET_HW_LINK_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  1515. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  1516. #define HW_TX_DELAY_MAX 0x1000000
  1517. #define TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US 10
  1518. #define HW_TX_DELAY_MASK 0x1FFFFFFF
  1519. #define TX_COMPL_BUFFER_TSTAMP_US(TSTAMP) \
  1520. (((TSTAMP) << TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US) & \
  1521. HW_TX_DELAY_MASK)
  1522. static inline
  1523. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1524. struct dp_vdev *vdev,
  1525. struct hal_tx_completion_status *ts,
  1526. uint32_t *delay_us)
  1527. {
  1528. uint32_t ppdu_id;
  1529. uint8_t link_id_offset, link_id_bits;
  1530. uint8_t hw_link_id;
  1531. uint32_t msdu_tqm_enqueue_tstamp_us, final_msdu_tqm_enqueue_tstamp_us;
  1532. uint32_t msdu_compl_tsf_tstamp_us, final_msdu_compl_tsf_tstamp_us;
  1533. uint32_t delay;
  1534. int32_t delta_tsf2, delta_tqm;
  1535. if (!ts->valid)
  1536. return QDF_STATUS_E_INVAL;
  1537. link_id_offset = soc->link_id_offset;
  1538. link_id_bits = soc->link_id_bits;
  1539. ppdu_id = ts->ppdu_id;
  1540. hw_link_id = PPDUID_GET_HW_LINK_ID(ppdu_id, link_id_offset,
  1541. link_id_bits);
  1542. msdu_tqm_enqueue_tstamp_us =
  1543. TX_COMPL_BUFFER_TSTAMP_US(ts->buffer_timestamp);
  1544. msdu_compl_tsf_tstamp_us = ts->tsf;
  1545. delta_tsf2 = dp_mlo_get_delta_tsf2_wrt_mlo_offset(soc, hw_link_id);
  1546. delta_tqm = dp_mlo_get_delta_tqm_wrt_mlo_offset(soc);
  1547. final_msdu_tqm_enqueue_tstamp_us = (msdu_tqm_enqueue_tstamp_us +
  1548. delta_tqm) & HW_TX_DELAY_MASK;
  1549. final_msdu_compl_tsf_tstamp_us = (msdu_compl_tsf_tstamp_us +
  1550. delta_tsf2) & HW_TX_DELAY_MASK;
  1551. delay = (final_msdu_compl_tsf_tstamp_us -
  1552. final_msdu_tqm_enqueue_tstamp_us) & HW_TX_DELAY_MASK;
  1553. if (delay > HW_TX_DELAY_MAX)
  1554. return QDF_STATUS_E_FAILURE;
  1555. if (delay_us)
  1556. *delay_us = delay;
  1557. return QDF_STATUS_SUCCESS;
  1558. }
  1559. #else
  1560. static inline
  1561. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1562. struct dp_vdev *vdev,
  1563. struct hal_tx_completion_status *ts,
  1564. uint32_t *delay_us)
  1565. {
  1566. return QDF_STATUS_SUCCESS;
  1567. }
  1568. #endif
  1569. QDF_STATUS dp_tx_compute_tx_delay_be(struct dp_soc *soc,
  1570. struct dp_vdev *vdev,
  1571. struct hal_tx_completion_status *ts,
  1572. uint32_t *delay_us)
  1573. {
  1574. return dp_mlo_compute_hw_delay_us(soc, vdev, ts, delay_us);
  1575. }
  1576. static inline
  1577. qdf_dma_addr_t dp_tx_nbuf_map_be(struct dp_vdev *vdev,
  1578. struct dp_tx_desc_s *tx_desc,
  1579. qdf_nbuf_t nbuf)
  1580. {
  1581. qdf_nbuf_dma_clean_range_no_dsb((void *)nbuf->data,
  1582. (void *)(nbuf->data + 256));
  1583. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1584. }
  1585. static inline
  1586. void dp_tx_nbuf_unmap_be(struct dp_soc *soc,
  1587. struct dp_tx_desc_s *desc)
  1588. {
  1589. }
  1590. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  1591. qdf_nbuf_t dp_tx_fast_send_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1592. qdf_nbuf_t nbuf)
  1593. {
  1594. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1595. struct dp_vdev *vdev = NULL;
  1596. struct dp_pdev *pdev = NULL;
  1597. struct dp_tx_desc_s *tx_desc;
  1598. uint16_t desc_pool_id;
  1599. uint16_t pkt_len;
  1600. qdf_dma_addr_t paddr;
  1601. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1602. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1603. hal_ring_handle_t hal_ring_hdl = NULL;
  1604. uint32_t *hal_tx_desc_cached;
  1605. void *hal_tx_desc;
  1606. uint8_t tid = HTT_TX_EXT_TID_INVALID;
  1607. uint8_t xmit_type = qdf_nbuf_get_vdev_xmit_type(nbuf);
  1608. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  1609. return nbuf;
  1610. vdev = soc->vdev_id_map[vdev_id];
  1611. if (qdf_unlikely(!vdev))
  1612. return nbuf;
  1613. desc_pool_id = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  1614. pkt_len = qdf_nbuf_headlen(nbuf);
  1615. DP_STATS_INC_PKT(vdev, tx_i[xmit_type].rcvd, 1, pkt_len);
  1616. DP_STATS_INC(vdev, tx_i[xmit_type].rcvd_in_fast_xmit_flow, 1);
  1617. DP_STATS_INC(vdev, tx_i[xmit_type].rcvd_per_core[desc_pool_id], 1);
  1618. pdev = vdev->pdev;
  1619. if (dp_tx_limit_check(vdev, nbuf))
  1620. return nbuf;
  1621. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1622. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1623. tid = qdf_nbuf_get_priority(nbuf);
  1624. if (tid == DP_TX_INVALID_QOS_TAG)
  1625. tid = HTT_TX_EXT_TID_INVALID;
  1626. }
  1627. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1628. if (qdf_unlikely(!tx_desc)) {
  1629. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.desc_na.num, 1);
  1630. DP_STATS_INC(vdev,
  1631. tx_i[xmit_type].dropped.desc_na_exc_alloc_fail.num,
  1632. 1);
  1633. return nbuf;
  1634. }
  1635. dp_tx_outstanding_inc(pdev);
  1636. /* Initialize the SW tx descriptor */
  1637. tx_desc->nbuf = nbuf;
  1638. tx_desc->frm_type = dp_tx_frm_std;
  1639. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1640. tx_desc->vdev_id = vdev_id;
  1641. tx_desc->pdev = pdev;
  1642. tx_desc->pkt_offset = 0;
  1643. tx_desc->length = pkt_len;
  1644. tx_desc->flags |= pdev->tx_fast_flag;
  1645. tx_desc->nbuf->fast_recycled = 1;
  1646. if (nbuf->is_from_recycler && nbuf->fast_xmit)
  1647. tx_desc->flags |= DP_TX_DESC_FLAG_FAST;
  1648. paddr = dp_tx_nbuf_map_be(vdev, tx_desc, nbuf);
  1649. if (!paddr) {
  1650. /* Handle failure */
  1651. dp_err("qdf_nbuf_map failed");
  1652. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.dma_error, 1);
  1653. goto release_desc;
  1654. }
  1655. tx_desc->dma_addr = paddr;
  1656. hal_tx_desc_cached = (void *)cached_desc;
  1657. hal_tx_desc_cached[0] = (uint32_t)tx_desc->dma_addr;
  1658. hal_tx_desc_cached[1] = tx_desc->id <<
  1659. TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  1660. /* bank_id */
  1661. hal_tx_desc_cached[2] = vdev->bank_id << TCL_DATA_CMD_BANK_ID_LSB;
  1662. hal_tx_desc_cached[3] = vdev->htt_tcl_metadata <<
  1663. TCL_DATA_CMD_TCL_CMD_NUMBER_LSB;
  1664. hal_tx_desc_cached[4] = tx_desc->length;
  1665. /* l3 and l4 checksum enable */
  1666. hal_tx_desc_cached[4] |= DP_TX_L3_L4_CSUM_ENABLE <<
  1667. TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB;
  1668. hal_tx_desc_cached[5] = vdev->lmac_id << TCL_DATA_CMD_PMAC_ID_LSB;
  1669. hal_tx_desc_cached[5] |= vdev->vdev_id << TCL_DATA_CMD_VDEV_ID_LSB;
  1670. if (tid != HTT_TX_EXT_TID_INVALID) {
  1671. hal_tx_desc_cached[5] |= tid << TCL_DATA_CMD_HLOS_TID_LSB;
  1672. hal_tx_desc_cached[5] |= tid << TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB;
  1673. }
  1674. if (vdev->opmode == wlan_op_mode_sta)
  1675. hal_tx_desc_cached[6] = vdev->bss_ast_idx |
  1676. ((vdev->bss_ast_hash & 0xF) <<
  1677. TCL_DATA_CMD_CACHE_SET_NUM_LSB);
  1678. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, desc_pool_id);
  1679. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1680. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1681. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1682. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.enqueue_fail, 1);
  1683. goto ring_access_fail2;
  1684. }
  1685. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1686. if (qdf_unlikely(!hal_tx_desc)) {
  1687. dp_verbose_debug("TCL ring full ring_id:%d", desc_pool_id);
  1688. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1689. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.enqueue_fail, 1);
  1690. goto ring_access_fail;
  1691. }
  1692. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1693. /* Sync cached descriptor with HW */
  1694. qdf_mem_copy(hal_tx_desc, hal_tx_desc_cached, DP_TX_FAST_DESC_SIZE);
  1695. qdf_dsb();
  1696. DP_STATS_INC_PKT(vdev, tx_i[xmit_type].processed, 1, tx_desc->length);
  1697. DP_STATS_INC(soc, tx.tcl_enq[desc_pool_id], 1);
  1698. status = QDF_STATUS_SUCCESS;
  1699. ring_access_fail:
  1700. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1701. ring_access_fail2:
  1702. if (status != QDF_STATUS_SUCCESS) {
  1703. dp_tx_nbuf_unmap_be(soc, tx_desc);
  1704. goto release_desc;
  1705. }
  1706. return NULL;
  1707. release_desc:
  1708. dp_tx_desc_release(soc, tx_desc, desc_pool_id);
  1709. return nbuf;
  1710. }
  1711. #endif
  1712. QDF_STATUS dp_tx_desc_pool_alloc_be(struct dp_soc *soc, uint32_t num_elem,
  1713. uint8_t pool_id)
  1714. {
  1715. return QDF_STATUS_SUCCESS;
  1716. }
  1717. void dp_tx_desc_pool_free_be(struct dp_soc *soc, uint8_t pool_id)
  1718. {
  1719. }