dp_be.c 47 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  26. #include "dp_mon_2.0.h"
  27. #endif
  28. #include <hal_be_api.h>
  29. /* Generic AST entry aging timer value */
  30. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  31. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  32. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  33. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  34. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  35. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  36. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  37. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  38. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  39. };
  40. #else
  41. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  42. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  43. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  44. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  45. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  46. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  47. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  48. };
  49. #endif
  50. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  51. {
  52. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  53. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  54. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  55. /* this is used only when dmac mode is enabled */
  56. soc->num_rx_refill_buf_rings = 1;
  57. }
  58. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  59. {
  60. switch (context_type) {
  61. case DP_CONTEXT_TYPE_SOC:
  62. return sizeof(struct dp_soc_be);
  63. case DP_CONTEXT_TYPE_PDEV:
  64. return sizeof(struct dp_pdev_be);
  65. case DP_CONTEXT_TYPE_VDEV:
  66. return sizeof(struct dp_vdev_be);
  67. case DP_CONTEXT_TYPE_PEER:
  68. return sizeof(struct dp_peer_be);
  69. default:
  70. return 0;
  71. }
  72. }
  73. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  74. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  75. {
  76. switch (context_type) {
  77. case DP_CONTEXT_TYPE_MON_SOC:
  78. return sizeof(struct dp_mon_soc_be);
  79. case DP_CONTEXT_TYPE_MON_PDEV:
  80. return sizeof(struct dp_mon_pdev_be);
  81. default:
  82. return 0;
  83. }
  84. }
  85. #else
  86. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  87. {
  88. switch (context_type) {
  89. case DP_CONTEXT_TYPE_MON_SOC:
  90. return sizeof(struct dp_mon_soc);
  91. case DP_CONTEXT_TYPE_MON_PDEV:
  92. return sizeof(struct dp_mon_pdev);
  93. default:
  94. return 0;
  95. }
  96. }
  97. #endif
  98. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  99. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  100. /**
  101. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  102. per wbm2sw ring
  103. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  104. *
  105. * Return: None
  106. */
  107. static inline
  108. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  109. {
  110. cc_cfg->wbm2sw6_cc_en = 1;
  111. cc_cfg->wbm2sw5_cc_en = 1;
  112. cc_cfg->wbm2sw4_cc_en = 1;
  113. cc_cfg->wbm2sw3_cc_en = 1;
  114. cc_cfg->wbm2sw2_cc_en = 1;
  115. /* disable wbm2sw1 hw cc as it's for FW */
  116. cc_cfg->wbm2sw1_cc_en = 0;
  117. cc_cfg->wbm2sw0_cc_en = 1;
  118. cc_cfg->wbm2fw_cc_en = 0;
  119. }
  120. #else
  121. static inline
  122. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  123. {
  124. cc_cfg->wbm2sw6_cc_en = 1;
  125. cc_cfg->wbm2sw5_cc_en = 1;
  126. cc_cfg->wbm2sw4_cc_en = 1;
  127. cc_cfg->wbm2sw3_cc_en = 1;
  128. cc_cfg->wbm2sw2_cc_en = 1;
  129. cc_cfg->wbm2sw1_cc_en = 1;
  130. cc_cfg->wbm2sw0_cc_en = 1;
  131. cc_cfg->wbm2fw_cc_en = 0;
  132. }
  133. #endif
  134. /**
  135. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  136. conversion register
  137. * @soc: SOC handle
  138. * @is_4k_align: page address 4k alignd
  139. *
  140. * Return: None
  141. */
  142. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  143. bool is_4k_align)
  144. {
  145. struct hal_hw_cc_config cc_cfg = { 0 };
  146. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  147. if (soc->cdp_soc.ol_ops->get_con_mode &&
  148. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  149. return;
  150. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  151. dp_info("INI skip HW CC register setting");
  152. return;
  153. }
  154. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  155. cc_cfg.cc_global_en = true;
  156. cc_cfg.page_4k_align = is_4k_align;
  157. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  158. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  159. /* 36th bit should be 1 then HW know this is CMEM address */
  160. cc_cfg.lut_base_addr_39_32 = 0x10;
  161. cc_cfg.error_path_cookie_conv_en = true;
  162. cc_cfg.release_path_cookie_conv_en = true;
  163. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  164. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  165. }
  166. /**
  167. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  168. * @hal_soc_hdl: HAL SOC handle
  169. * @offset: CMEM address
  170. * @value: value to write
  171. *
  172. * Return: None.
  173. */
  174. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  175. uint32_t offset,
  176. uint32_t value)
  177. {
  178. hal_cmem_write(hal_soc_hdl, offset, value);
  179. }
  180. /**
  181. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  182. HW cookie conversion
  183. * @soc: SOC handle
  184. * @cc_ctx: cookie conversion context pointer
  185. *
  186. * Return: 0 in case of success, else error value
  187. */
  188. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  189. {
  190. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  191. dp_info("cmem base 0x%llx, size 0x%llx",
  192. soc->cmem_base, soc->cmem_size);
  193. /* get CMEM for cookie conversion */
  194. if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
  195. dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
  196. return QDF_STATUS_E_RESOURCES;
  197. }
  198. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  199. DP_CC_MEM_OFFSET_IN_CMEM);
  200. return QDF_STATUS_SUCCESS;
  201. }
  202. #else
  203. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  204. bool is_4k_align) {}
  205. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  206. uint32_t offset,
  207. uint32_t value)
  208. { }
  209. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  210. {
  211. return QDF_STATUS_SUCCESS;
  212. }
  213. #endif
  214. QDF_STATUS
  215. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  216. struct dp_hw_cookie_conversion_t *cc_ctx,
  217. uint32_t num_descs,
  218. enum dp_desc_type desc_type,
  219. uint8_t desc_pool_id)
  220. {
  221. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  222. uint32_t num_spt_pages, i = 0;
  223. struct dp_spt_page_desc *spt_desc;
  224. struct qdf_mem_dma_page_t *dma_page;
  225. uint8_t chip_id;
  226. /* estimate how many SPT DDR pages needed */
  227. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  228. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  229. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  230. dp_info("num_spt_pages needed %d", num_spt_pages);
  231. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  232. &cc_ctx->page_pool, qdf_page_size,
  233. num_spt_pages, 0, false);
  234. if (!cc_ctx->page_pool.dma_pages) {
  235. dp_err("spt ddr pages allocation failed");
  236. return QDF_STATUS_E_RESOURCES;
  237. }
  238. cc_ctx->page_desc_base = qdf_mem_malloc(
  239. num_spt_pages * sizeof(struct dp_spt_page_desc));
  240. if (!cc_ctx->page_desc_base) {
  241. dp_err("spt page descs allocation failed");
  242. goto fail_0;
  243. }
  244. chip_id = dp_mlo_get_chip_id(soc);
  245. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  246. desc_type);
  247. /* initial page desc */
  248. spt_desc = cc_ctx->page_desc_base;
  249. dma_page = cc_ctx->page_pool.dma_pages;
  250. while (i < num_spt_pages) {
  251. /* check if page address 4K aligned */
  252. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  253. dp_err("non-4k aligned pages addr %pK",
  254. (void *)dma_page[i].page_p_addr);
  255. goto fail_1;
  256. }
  257. spt_desc[i].page_v_addr =
  258. dma_page[i].page_v_addr_start;
  259. spt_desc[i].page_p_addr =
  260. dma_page[i].page_p_addr;
  261. i++;
  262. }
  263. cc_ctx->total_page_num = num_spt_pages;
  264. qdf_spinlock_create(&cc_ctx->cc_lock);
  265. return QDF_STATUS_SUCCESS;
  266. fail_1:
  267. qdf_mem_free(cc_ctx->page_desc_base);
  268. fail_0:
  269. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  270. &cc_ctx->page_pool, 0, false);
  271. return QDF_STATUS_E_FAILURE;
  272. }
  273. QDF_STATUS
  274. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  275. struct dp_hw_cookie_conversion_t *cc_ctx)
  276. {
  277. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  278. qdf_mem_free(cc_ctx->page_desc_base);
  279. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  280. &cc_ctx->page_pool, 0, false);
  281. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  282. return QDF_STATUS_SUCCESS;
  283. }
  284. QDF_STATUS
  285. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  286. struct dp_hw_cookie_conversion_t *cc_ctx)
  287. {
  288. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  289. uint32_t i = 0;
  290. struct dp_spt_page_desc *spt_desc;
  291. uint32_t ppt_index;
  292. uint32_t ppt_id_start;
  293. if (!cc_ctx->total_page_num) {
  294. dp_err("total page num is 0");
  295. return QDF_STATUS_E_INVAL;
  296. }
  297. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  298. spt_desc = cc_ctx->page_desc_base;
  299. while (i < cc_ctx->total_page_num) {
  300. /* write page PA to CMEM */
  301. dp_hw_cc_cmem_write(soc->hal_soc,
  302. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  303. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  304. (spt_desc[i].page_p_addr >>
  305. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  306. ppt_index = ppt_id_start + i;
  307. spt_desc[i].ppt_index = ppt_index;
  308. be_soc->page_desc_base[ppt_index].page_v_addr =
  309. spt_desc[i].page_v_addr;
  310. i++;
  311. }
  312. return QDF_STATUS_SUCCESS;
  313. }
  314. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  315. QDF_STATUS
  316. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  317. struct dp_hw_cookie_conversion_t *cc_ctx)
  318. {
  319. uint32_t ppt_index;
  320. struct dp_spt_page_desc *spt_desc;
  321. int i = 0;
  322. spt_desc = cc_ctx->page_desc_base;
  323. while (i < cc_ctx->total_page_num) {
  324. ppt_index = spt_desc[i].ppt_index;
  325. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  326. i++;
  327. }
  328. return QDF_STATUS_SUCCESS;
  329. }
  330. #else
  331. QDF_STATUS
  332. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  333. struct dp_hw_cookie_conversion_t *cc_ctx)
  334. {
  335. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  336. uint32_t ppt_index;
  337. struct dp_spt_page_desc *spt_desc;
  338. int i = 0;
  339. spt_desc = cc_ctx->page_desc_base;
  340. while (i < cc_ctx->total_page_num) {
  341. /* reset PA in CMEM to NULL */
  342. dp_hw_cc_cmem_write(soc->hal_soc,
  343. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  344. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  345. 0);
  346. ppt_index = spt_desc[i].ppt_index;
  347. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  348. i++;
  349. }
  350. return QDF_STATUS_SUCCESS;
  351. }
  352. #endif
  353. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  354. {
  355. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  356. int i = 0;
  357. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  358. dp_hw_cookie_conversion_detach(be_soc,
  359. &be_soc->tx_cc_ctx[i]);
  360. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  361. dp_hw_cookie_conversion_detach(be_soc,
  362. &be_soc->rx_cc_ctx[i]);
  363. qdf_mem_free(be_soc->page_desc_base);
  364. be_soc->page_desc_base = NULL;
  365. return QDF_STATUS_SUCCESS;
  366. }
  367. #ifdef WLAN_MLO_MULTI_CHIP
  368. #ifdef WLAN_MCAST_MLO
  369. static inline void
  370. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  371. {
  372. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  373. be_vdev->mcast_primary = false;
  374. be_vdev->seq_num = 0;
  375. if (vdev->mlo_vdev)
  376. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  377. vdev->vdev_id,
  378. HAL_TX_MCAST_CTRL_DROP);
  379. }
  380. static inline void
  381. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  382. {
  383. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  384. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  385. be_vdev->vdev.pdev->soc);
  386. be_vdev->seq_num = 0;
  387. if (vdev->mlo_vdev) {
  388. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  389. vdev->vdev_id,
  390. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  391. vdev->mlo_vdev = false;
  392. }
  393. if (be_vdev->mcast_primary) {
  394. be_vdev->mcast_primary = false;
  395. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  396. dp_tx_mcast_mlo_reinject_routing_set,
  397. (void *)&be_vdev->mcast_primary);
  398. }
  399. }
  400. #else
  401. static inline void
  402. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  403. {
  404. }
  405. static inline void
  406. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  407. {
  408. }
  409. #endif
  410. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  411. {
  412. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  413. qdf_mem_set(be_vdev->partner_vdev_list,
  414. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  415. CDP_INVALID_VDEV_ID);
  416. }
  417. #else
  418. static inline void
  419. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  420. {
  421. }
  422. static inline void
  423. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  424. {
  425. }
  426. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  427. {
  428. }
  429. #endif
  430. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  431. struct cdp_soc_attach_params *params)
  432. {
  433. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  434. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  435. uint32_t max_tx_rx_desc_num, num_spt_pages;
  436. uint32_t num_entries;
  437. int i = 0;
  438. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  439. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  440. /* estimate how many SPT DDR pages needed */
  441. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  442. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  443. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  444. be_soc->page_desc_base = qdf_mem_malloc(
  445. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  446. if (!be_soc->page_desc_base) {
  447. dp_err("spt page descs allocation failed");
  448. return QDF_STATUS_E_NOMEM;
  449. }
  450. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  451. qdf_status = dp_hw_cc_cmem_addr_init(soc);
  452. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  453. goto fail;
  454. dp_soc_mlo_fill_params(soc, params);
  455. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  456. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  457. qdf_status =
  458. dp_hw_cookie_conversion_attach(be_soc,
  459. &be_soc->tx_cc_ctx[i],
  460. num_entries,
  461. DP_TX_DESC_TYPE, i);
  462. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  463. goto fail;
  464. }
  465. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  466. num_entries =
  467. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  468. qdf_status =
  469. dp_hw_cookie_conversion_attach(be_soc,
  470. &be_soc->rx_cc_ctx[i],
  471. num_entries,
  472. DP_RX_DESC_BUF_TYPE, i);
  473. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  474. goto fail;
  475. }
  476. return qdf_status;
  477. fail:
  478. dp_soc_detach_be(soc);
  479. return qdf_status;
  480. }
  481. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  482. {
  483. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  484. int i = 0;
  485. dp_tx_deinit_bank_profiles(be_soc);
  486. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  487. dp_hw_cookie_conversion_deinit(be_soc,
  488. &be_soc->tx_cc_ctx[i]);
  489. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  490. dp_hw_cookie_conversion_deinit(be_soc,
  491. &be_soc->rx_cc_ctx[i]);
  492. return QDF_STATUS_SUCCESS;
  493. }
  494. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  495. {
  496. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  497. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  498. int i = 0;
  499. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  500. qdf_status =
  501. dp_hw_cookie_conversion_init(be_soc,
  502. &be_soc->tx_cc_ctx[i]);
  503. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  504. goto fail;
  505. }
  506. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  507. qdf_status =
  508. dp_hw_cookie_conversion_init(be_soc,
  509. &be_soc->rx_cc_ctx[i]);
  510. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  511. goto fail;
  512. }
  513. /* route vdev_id mismatch notification via FW completion */
  514. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  515. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  516. qdf_status = dp_tx_init_bank_profiles(be_soc);
  517. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  518. goto fail;
  519. /* write WBM/REO cookie conversion CFG register */
  520. dp_cc_reg_cfg_init(soc, true);
  521. return qdf_status;
  522. fail:
  523. dp_soc_deinit_be(soc);
  524. return qdf_status;
  525. }
  526. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  527. struct cdp_pdev_attach_params *params)
  528. {
  529. dp_pdev_mlo_fill_params(pdev, params);
  530. return QDF_STATUS_SUCCESS;
  531. }
  532. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  533. {
  534. return QDF_STATUS_SUCCESS;
  535. }
  536. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  537. {
  538. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  539. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  540. struct dp_pdev *pdev = vdev->pdev;
  541. if (vdev->opmode == wlan_op_mode_monitor)
  542. return QDF_STATUS_SUCCESS;
  543. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  544. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  545. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  546. QDF_BUG(0);
  547. return QDF_STATUS_E_FAULT;
  548. }
  549. if (vdev->opmode == wlan_op_mode_sta) {
  550. if (soc->cdp_soc.ol_ops->set_mec_timer)
  551. soc->cdp_soc.ol_ops->set_mec_timer(
  552. soc->ctrl_psoc,
  553. vdev->vdev_id,
  554. DP_AST_AGING_TIMER_DEFAULT_MS);
  555. if (pdev->isolation)
  556. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  557. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  558. else
  559. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  560. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  561. }
  562. if (vdev->opmode == wlan_op_mode_ap)
  563. dp_mlo_mcast_init(soc, vdev);
  564. dp_mlo_init_ptnr_list(vdev);
  565. return QDF_STATUS_SUCCESS;
  566. }
  567. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  568. {
  569. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  570. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  571. if (vdev->opmode == wlan_op_mode_monitor)
  572. return QDF_STATUS_SUCCESS;
  573. if (vdev->opmode == wlan_op_mode_ap)
  574. dp_mlo_mcast_deinit(soc, vdev);
  575. dp_tx_put_bank_profile(be_soc, be_vdev);
  576. dp_clr_mlo_ptnr_list(soc, vdev);
  577. return QDF_STATUS_SUCCESS;
  578. }
  579. qdf_size_t dp_get_soc_context_size_be(void)
  580. {
  581. return sizeof(struct dp_soc_be);
  582. }
  583. #ifdef NO_RX_PKT_HDR_TLV
  584. /**
  585. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  586. * @soc: Common DP soc handle
  587. *
  588. * Return: QDF_STATUS
  589. */
  590. static QDF_STATUS
  591. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  592. {
  593. int i;
  594. int mac_id;
  595. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  596. struct dp_srng *rx_mac_srng;
  597. QDF_STATUS status = QDF_STATUS_SUCCESS;
  598. /*
  599. * In Beryllium chipset msdu_start, mpdu_end
  600. * and rx_attn are part of msdu_end/mpdu_start
  601. */
  602. htt_tlv_filter.msdu_start = 0;
  603. htt_tlv_filter.mpdu_end = 0;
  604. htt_tlv_filter.attention = 0;
  605. htt_tlv_filter.mpdu_start = 1;
  606. htt_tlv_filter.msdu_end = 1;
  607. htt_tlv_filter.packet = 1;
  608. htt_tlv_filter.packet_header = 1;
  609. htt_tlv_filter.ppdu_start = 0;
  610. htt_tlv_filter.ppdu_end = 0;
  611. htt_tlv_filter.ppdu_end_user_stats = 0;
  612. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  613. htt_tlv_filter.ppdu_end_status_done = 0;
  614. htt_tlv_filter.enable_fp = 1;
  615. htt_tlv_filter.enable_md = 0;
  616. htt_tlv_filter.enable_md = 0;
  617. htt_tlv_filter.enable_mo = 0;
  618. htt_tlv_filter.fp_mgmt_filter = 0;
  619. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  620. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  621. FILTER_DATA_MCAST |
  622. FILTER_DATA_DATA);
  623. htt_tlv_filter.mo_mgmt_filter = 0;
  624. htt_tlv_filter.mo_ctrl_filter = 0;
  625. htt_tlv_filter.mo_data_filter = 0;
  626. htt_tlv_filter.md_data_filter = 0;
  627. htt_tlv_filter.offset_valid = true;
  628. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  629. htt_tlv_filter.rx_mpdu_end_offset = 0;
  630. htt_tlv_filter.rx_msdu_start_offset = 0;
  631. htt_tlv_filter.rx_attn_offset = 0;
  632. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  633. /*Not subscribing rx_pkt_header*/
  634. htt_tlv_filter.rx_header_offset = 0;
  635. htt_tlv_filter.rx_mpdu_start_offset =
  636. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  637. htt_tlv_filter.rx_msdu_end_offset =
  638. hal_rx_msdu_end_offset_get(soc->hal_soc);
  639. for (i = 0; i < MAX_PDEV_CNT; i++) {
  640. struct dp_pdev *pdev = soc->pdev_list[i];
  641. if (!pdev)
  642. continue;
  643. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  644. int mac_for_pdev =
  645. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  646. /*
  647. * Obtain lmac id from pdev to access the LMAC ring
  648. * in soc context
  649. */
  650. int lmac_id =
  651. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  652. pdev->pdev_id);
  653. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  654. if (!rx_mac_srng->hal_srng)
  655. continue;
  656. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  657. rx_mac_srng->hal_srng,
  658. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  659. &htt_tlv_filter);
  660. }
  661. }
  662. return status;
  663. }
  664. #else
  665. /**
  666. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  667. * @soc: Common DP soc handle
  668. *
  669. * Return: QDF_STATUS
  670. */
  671. static QDF_STATUS
  672. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  673. {
  674. int i;
  675. int mac_id;
  676. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  677. struct dp_srng *rx_mac_srng;
  678. QDF_STATUS status = QDF_STATUS_SUCCESS;
  679. /*
  680. * In Beryllium chipset msdu_start, mpdu_end
  681. * and rx_attn are part of msdu_end/mpdu_start
  682. */
  683. htt_tlv_filter.msdu_start = 0;
  684. htt_tlv_filter.mpdu_end = 0;
  685. htt_tlv_filter.attention = 0;
  686. htt_tlv_filter.mpdu_start = 1;
  687. htt_tlv_filter.msdu_end = 1;
  688. htt_tlv_filter.packet = 1;
  689. htt_tlv_filter.packet_header = 1;
  690. htt_tlv_filter.ppdu_start = 0;
  691. htt_tlv_filter.ppdu_end = 0;
  692. htt_tlv_filter.ppdu_end_user_stats = 0;
  693. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  694. htt_tlv_filter.ppdu_end_status_done = 0;
  695. htt_tlv_filter.enable_fp = 1;
  696. htt_tlv_filter.enable_md = 0;
  697. htt_tlv_filter.enable_md = 0;
  698. htt_tlv_filter.enable_mo = 0;
  699. htt_tlv_filter.fp_mgmt_filter = 0;
  700. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  701. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  702. FILTER_DATA_MCAST |
  703. FILTER_DATA_DATA);
  704. htt_tlv_filter.mo_mgmt_filter = 0;
  705. htt_tlv_filter.mo_ctrl_filter = 0;
  706. htt_tlv_filter.mo_data_filter = 0;
  707. htt_tlv_filter.md_data_filter = 0;
  708. htt_tlv_filter.offset_valid = true;
  709. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  710. htt_tlv_filter.rx_mpdu_end_offset = 0;
  711. htt_tlv_filter.rx_msdu_start_offset = 0;
  712. htt_tlv_filter.rx_attn_offset = 0;
  713. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  714. htt_tlv_filter.rx_header_offset =
  715. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  716. htt_tlv_filter.rx_mpdu_start_offset =
  717. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  718. htt_tlv_filter.rx_msdu_end_offset =
  719. hal_rx_msdu_end_offset_get(soc->hal_soc);
  720. dp_info("TLV subscription\n"
  721. "msdu_start %d, mpdu_end %d, attention %d"
  722. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  723. "TLV offsets\n"
  724. "msdu_start %d, mpdu_end %d, attention %d"
  725. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  726. htt_tlv_filter.msdu_start,
  727. htt_tlv_filter.mpdu_end,
  728. htt_tlv_filter.attention,
  729. htt_tlv_filter.mpdu_start,
  730. htt_tlv_filter.msdu_end,
  731. htt_tlv_filter.packet_header,
  732. htt_tlv_filter.packet,
  733. htt_tlv_filter.rx_msdu_start_offset,
  734. htt_tlv_filter.rx_mpdu_end_offset,
  735. htt_tlv_filter.rx_attn_offset,
  736. htt_tlv_filter.rx_mpdu_start_offset,
  737. htt_tlv_filter.rx_msdu_end_offset,
  738. htt_tlv_filter.rx_header_offset,
  739. htt_tlv_filter.rx_packet_offset);
  740. for (i = 0; i < MAX_PDEV_CNT; i++) {
  741. struct dp_pdev *pdev = soc->pdev_list[i];
  742. if (!pdev)
  743. continue;
  744. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  745. int mac_for_pdev =
  746. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  747. /*
  748. * Obtain lmac id from pdev to access the LMAC ring
  749. * in soc context
  750. */
  751. int lmac_id =
  752. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  753. pdev->pdev_id);
  754. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  755. if (!rx_mac_srng->hal_srng)
  756. continue;
  757. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  758. rx_mac_srng->hal_srng,
  759. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  760. &htt_tlv_filter);
  761. }
  762. }
  763. return status;
  764. }
  765. #endif
  766. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  767. /**
  768. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  769. * near-full IRQs.
  770. * @soc: Datapath SoC handle
  771. * @int_ctx: Interrupt context
  772. * @dp_budget: Budget of the work that can be done in the bottom half
  773. *
  774. * Return: work done in the handler
  775. */
  776. static uint32_t
  777. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  778. uint32_t dp_budget)
  779. {
  780. int ring = 0;
  781. int budget = dp_budget;
  782. uint32_t work_done = 0;
  783. uint32_t remaining_quota = dp_budget;
  784. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  785. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  786. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  787. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  788. int rx_near_full_mask = rx_near_full_grp_1_mask |
  789. rx_near_full_grp_2_mask;
  790. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  791. rx_near_full_mask,
  792. tx_ring_near_full_mask);
  793. if (rx_near_full_mask) {
  794. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  795. if (!(rx_near_full_mask & (1 << ring)))
  796. continue;
  797. work_done = dp_rx_nf_process(int_ctx,
  798. soc->reo_dest_ring[ring].hal_srng,
  799. ring, remaining_quota);
  800. if (work_done) {
  801. intr_stats->num_rx_ring_near_full_masks[ring]++;
  802. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  803. rx_near_full_mask, ring,
  804. work_done,
  805. budget);
  806. budget -= work_done;
  807. if (budget <= 0)
  808. goto budget_done;
  809. remaining_quota = budget;
  810. }
  811. }
  812. }
  813. if (tx_ring_near_full_mask) {
  814. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  815. if (!(tx_ring_near_full_mask & (1 << ring)))
  816. continue;
  817. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  818. soc->tx_comp_ring[ring].hal_srng,
  819. ring, remaining_quota);
  820. if (work_done) {
  821. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  822. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  823. tx_ring_near_full_mask, ring,
  824. work_done, budget);
  825. budget -= work_done;
  826. if (budget <= 0)
  827. break;
  828. remaining_quota = budget;
  829. }
  830. }
  831. }
  832. intr_stats->num_near_full_masks++;
  833. budget_done:
  834. return dp_budget - budget;
  835. }
  836. /**
  837. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  838. * state and set the reap_limit appropriately
  839. * as per the near full state
  840. * @soc: Datapath soc handle
  841. * @dp_srng: Datapath handle for SRNG
  842. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  843. * the srng near-full state
  844. *
  845. * Return: 1, if the srng is in near-full state
  846. * 0, if the srng is not in near-full state
  847. */
  848. static int
  849. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  850. struct dp_srng *dp_srng,
  851. int *max_reap_limit)
  852. {
  853. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  854. }
  855. /**
  856. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  857. * near full IRQ handling operations.
  858. * @arch_ops: arch ops handle
  859. *
  860. * Return: none
  861. */
  862. static inline void
  863. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  864. {
  865. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  866. arch_ops->dp_srng_test_and_update_nf_params =
  867. dp_srng_test_and_update_nf_params_be;
  868. }
  869. #else
  870. static inline void
  871. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  872. {
  873. }
  874. #endif
  875. #ifdef WLAN_SUPPORT_PPEDS
  876. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  877. {
  878. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  879. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  880. soc_cfg_ctx = soc->wlan_cfg_ctx;
  881. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  882. return;
  883. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  884. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  885. be_soc->ppe_release_ring.alloc_size,
  886. soc->ctrl_psoc,
  887. WLAN_MD_DP_SRNG_PPE_RELEASE,
  888. "ppe_release_ring");
  889. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  890. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  891. be_soc->ppe2tcl_ring.alloc_size,
  892. soc->ctrl_psoc,
  893. WLAN_MD_DP_SRNG_PPE2TCL,
  894. "ppe2tcl_ring");
  895. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  896. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  897. be_soc->reo2ppe_ring.alloc_size,
  898. soc->ctrl_psoc,
  899. WLAN_MD_DP_SRNG_REO2PPE,
  900. "reo2ppe_ring");
  901. }
  902. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  903. {
  904. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  905. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  906. soc_cfg_ctx = soc->wlan_cfg_ctx;
  907. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  908. return;
  909. dp_srng_free(soc, &be_soc->ppe_release_ring);
  910. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  911. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  912. }
  913. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  914. {
  915. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  916. uint32_t entries;
  917. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  918. soc_cfg_ctx = soc->wlan_cfg_ctx;
  919. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  920. return QDF_STATUS_SUCCESS;
  921. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  922. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  923. entries, 0)) {
  924. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  925. goto fail;
  926. }
  927. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  928. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  929. entries, 0)) {
  930. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  931. goto fail;
  932. }
  933. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  934. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  935. entries, 0)) {
  936. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  937. goto fail;
  938. }
  939. return QDF_STATUS_SUCCESS;
  940. fail:
  941. dp_soc_ppe_srng_free(soc);
  942. return QDF_STATUS_E_NOMEM;
  943. }
  944. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  945. {
  946. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  947. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  948. soc_cfg_ctx = soc->wlan_cfg_ctx;
  949. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  950. return QDF_STATUS_SUCCESS;
  951. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  952. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  953. goto fail;
  954. }
  955. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  956. be_soc->reo2ppe_ring.alloc_size,
  957. soc->ctrl_psoc,
  958. WLAN_MD_DP_SRNG_REO2PPE,
  959. "reo2ppe_ring");
  960. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  961. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  962. goto fail;
  963. }
  964. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  965. be_soc->ppe2tcl_ring.alloc_size,
  966. soc->ctrl_psoc,
  967. WLAN_MD_DP_SRNG_PPE2TCL,
  968. "ppe2tcl_ring");
  969. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  970. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  971. goto fail;
  972. }
  973. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  974. be_soc->ppe_release_ring.alloc_size,
  975. soc->ctrl_psoc,
  976. WLAN_MD_DP_SRNG_PPE_RELEASE,
  977. "ppe_release_ring");
  978. return QDF_STATUS_SUCCESS;
  979. fail:
  980. dp_soc_ppe_srng_deinit(soc);
  981. return QDF_STATUS_E_NOMEM;
  982. }
  983. #else
  984. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  985. {
  986. }
  987. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  988. {
  989. }
  990. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  991. {
  992. return QDF_STATUS_SUCCESS;
  993. }
  994. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  995. {
  996. return QDF_STATUS_SUCCESS;
  997. }
  998. #endif
  999. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1000. {
  1001. uint32_t i;
  1002. dp_soc_ppe_srng_deinit(soc);
  1003. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1004. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1005. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1006. RXDMA_BUF, 0);
  1007. }
  1008. }
  1009. }
  1010. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1011. {
  1012. uint32_t i;
  1013. dp_soc_ppe_srng_free(soc);
  1014. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1015. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1016. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1017. }
  1018. }
  1019. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1020. {
  1021. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1022. uint32_t ring_size;
  1023. uint32_t i;
  1024. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1025. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1026. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1027. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1028. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1029. RXDMA_BUF, ring_size, 0)) {
  1030. dp_err("%pK: dp_srng_alloc failed refill ring",
  1031. soc);
  1032. goto fail;
  1033. }
  1034. }
  1035. }
  1036. if (dp_soc_ppe_srng_alloc(soc)) {
  1037. dp_err("%pK: ppe rings alloc failed",
  1038. soc);
  1039. goto fail;
  1040. }
  1041. return QDF_STATUS_SUCCESS;
  1042. fail:
  1043. dp_soc_srng_free_be(soc);
  1044. return QDF_STATUS_E_NOMEM;
  1045. }
  1046. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1047. {
  1048. int i = 0;
  1049. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1050. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1051. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1052. RXDMA_BUF, 0, 0)) {
  1053. dp_err("%pK: dp_srng_init failed refill ring",
  1054. soc);
  1055. goto fail;
  1056. }
  1057. }
  1058. }
  1059. if (dp_soc_ppe_srng_init(soc)) {
  1060. dp_err("%pK: ppe rings init failed",
  1061. soc);
  1062. goto fail;
  1063. }
  1064. return QDF_STATUS_SUCCESS;
  1065. fail:
  1066. dp_soc_srng_deinit_be(soc);
  1067. return QDF_STATUS_E_NOMEM;
  1068. }
  1069. #ifdef WLAN_FEATURE_11BE_MLO
  1070. static inline unsigned
  1071. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1072. union dp_align_mac_addr *mac_addr)
  1073. {
  1074. uint32_t index;
  1075. index =
  1076. mac_addr->align2.bytes_ab ^
  1077. mac_addr->align2.bytes_cd ^
  1078. mac_addr->align2.bytes_ef;
  1079. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1080. index &= mld_hash_obj->mld_peer_hash.mask;
  1081. return index;
  1082. }
  1083. QDF_STATUS
  1084. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1085. int hash_elems)
  1086. {
  1087. int i, log2;
  1088. if (!mld_hash_obj)
  1089. return QDF_STATUS_E_FAILURE;
  1090. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1091. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1092. log2 = dp_log2_ceil(hash_elems);
  1093. hash_elems = 1 << log2;
  1094. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1095. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1096. /* allocate an array of TAILQ peer object lists */
  1097. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1098. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1099. if (!mld_hash_obj->mld_peer_hash.bins)
  1100. return QDF_STATUS_E_NOMEM;
  1101. for (i = 0; i < hash_elems; i++)
  1102. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1103. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1104. return QDF_STATUS_SUCCESS;
  1105. }
  1106. void
  1107. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1108. {
  1109. if (!mld_hash_obj)
  1110. return;
  1111. if (mld_hash_obj->mld_peer_hash.bins) {
  1112. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1113. mld_hash_obj->mld_peer_hash.bins = NULL;
  1114. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1115. }
  1116. }
  1117. #ifdef WLAN_MLO_MULTI_CHIP
  1118. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1119. {
  1120. /* In case of MULTI chip MLO peer hash table when MLO global object
  1121. * is created, avoid from SOC attach path
  1122. */
  1123. return QDF_STATUS_SUCCESS;
  1124. }
  1125. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1126. {
  1127. }
  1128. #else
  1129. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1130. {
  1131. dp_mld_peer_hash_obj_t mld_hash_obj;
  1132. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1133. if (!mld_hash_obj)
  1134. return QDF_STATUS_E_FAILURE;
  1135. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1136. }
  1137. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1138. {
  1139. dp_mld_peer_hash_obj_t mld_hash_obj;
  1140. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1141. if (!mld_hash_obj)
  1142. return;
  1143. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1144. }
  1145. #endif
  1146. static struct dp_peer *
  1147. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1148. uint8_t *peer_mac_addr,
  1149. int mac_addr_is_aligned,
  1150. enum dp_mod_id mod_id,
  1151. uint8_t vdev_id)
  1152. {
  1153. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1154. uint32_t index;
  1155. struct dp_peer *peer;
  1156. struct dp_vdev *vdev;
  1157. dp_mld_peer_hash_obj_t mld_hash_obj;
  1158. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1159. if (!mld_hash_obj)
  1160. return NULL;
  1161. if (!mld_hash_obj->mld_peer_hash.bins)
  1162. return NULL;
  1163. if (mac_addr_is_aligned) {
  1164. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1165. } else {
  1166. qdf_mem_copy(
  1167. &local_mac_addr_aligned.raw[0],
  1168. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1169. mac_addr = &local_mac_addr_aligned;
  1170. }
  1171. if (vdev_id != DP_VDEV_ALL) {
  1172. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1173. if (!vdev) {
  1174. dp_err("vdev is null\n");
  1175. return NULL;
  1176. }
  1177. } else {
  1178. vdev = NULL;
  1179. }
  1180. /* search mld peer table if no link peer for given mac address */
  1181. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1182. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1183. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1184. hash_list_elem) {
  1185. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1186. if ((vdev_id == DP_VDEV_ALL) || (
  1187. dp_peer_find_mac_addr_cmp(
  1188. &peer->vdev->mld_mac_addr,
  1189. &vdev->mld_mac_addr) == 0)) {
  1190. /* take peer reference before returning */
  1191. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1192. QDF_STATUS_SUCCESS)
  1193. peer = NULL;
  1194. if (vdev)
  1195. dp_vdev_unref_delete(soc, vdev, mod_id);
  1196. qdf_spin_unlock_bh(
  1197. &mld_hash_obj->mld_peer_hash_lock);
  1198. return peer;
  1199. }
  1200. }
  1201. }
  1202. if (vdev)
  1203. dp_vdev_unref_delete(soc, vdev, mod_id);
  1204. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1205. return NULL; /* failure */
  1206. }
  1207. static void
  1208. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1209. {
  1210. uint32_t index;
  1211. struct dp_peer *tmppeer = NULL;
  1212. int found = 0;
  1213. dp_mld_peer_hash_obj_t mld_hash_obj;
  1214. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1215. if (!mld_hash_obj)
  1216. return;
  1217. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1218. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1219. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1220. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1221. hash_list_elem) {
  1222. if (tmppeer == peer) {
  1223. found = 1;
  1224. break;
  1225. }
  1226. }
  1227. QDF_ASSERT(found);
  1228. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1229. hash_list_elem);
  1230. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1231. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1232. }
  1233. static void
  1234. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1235. {
  1236. uint32_t index;
  1237. dp_mld_peer_hash_obj_t mld_hash_obj;
  1238. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1239. if (!mld_hash_obj)
  1240. return;
  1241. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1242. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1243. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1244. DP_MOD_ID_CONFIG))) {
  1245. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1246. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1247. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1248. return;
  1249. }
  1250. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1251. hash_list_elem);
  1252. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1253. }
  1254. #endif
  1255. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1256. defined(WLAN_MCAST_MLO)
  1257. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1258. struct dp_vdev_be *be_vdev,
  1259. cdp_config_param_type val)
  1260. {
  1261. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1262. be_vdev->vdev.pdev->soc);
  1263. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1264. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1265. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1266. if (be_vdev->mcast_primary) {
  1267. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1268. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1269. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1270. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1271. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1272. dp_tx_mcast_mlo_reinject_routing_set,
  1273. (void *)&be_vdev->mcast_primary);
  1274. } else {
  1275. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1276. HAL_TX_MCAST_CTRL_DROP);
  1277. }
  1278. }
  1279. #else
  1280. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1281. struct dp_vdev_be *be_vdev,
  1282. cdp_config_param_type val)
  1283. {
  1284. }
  1285. #endif
  1286. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1287. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1288. uint8_t tx_ring_id,
  1289. uint8_t bm_id)
  1290. {
  1291. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1292. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1293. bm_id);
  1294. }
  1295. #else
  1296. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1297. uint8_t tx_ring_id,
  1298. uint8_t bm_id)
  1299. {
  1300. }
  1301. #endif
  1302. #ifdef WLAN_MLO_MULTI_CHIP
  1303. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1304. struct cdp_peer_setup_info *setup_info,
  1305. enum cdp_host_reo_dest_ring *reo_dest,
  1306. bool *hash_based,
  1307. uint8_t *lmac_peer_id_msb)
  1308. {
  1309. struct dp_soc *soc = vdev->pdev->soc;
  1310. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1311. uint8_t default_rx_ring_id;
  1312. uint8_t chip_id;
  1313. if (!be_soc->mlo_enabled)
  1314. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1315. hash_based);
  1316. chip_id = be_soc->mlo_chip_id;
  1317. default_rx_ring_id =
  1318. wlan_cfg_mlo_default_rx_ring_get_by_chip_id(soc->wlan_cfg_ctx,
  1319. chip_id);
  1320. *reo_dest = hal_reo_ring_remap_value_get_be(default_rx_ring_id);
  1321. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1322. *lmac_peer_id_msb =
  1323. wlan_cfg_mlo_lmac_peer_id_msb_get_by_chip_id(soc->wlan_cfg_ctx,
  1324. chip_id);
  1325. }
  1326. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1327. uint32_t *remap0,
  1328. uint32_t *remap1,
  1329. uint32_t *remap2)
  1330. {
  1331. uint8_t rx_ring_mask;
  1332. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1333. if (!be_soc->mlo_enabled)
  1334. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1335. rx_ring_mask =
  1336. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 0);
  1337. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1338. rx_ring_mask =
  1339. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 1);
  1340. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1341. rx_ring_mask =
  1342. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 2);
  1343. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1344. return true;
  1345. }
  1346. #else
  1347. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1348. struct cdp_peer_setup_info *setup_info,
  1349. enum cdp_host_reo_dest_ring *reo_dest,
  1350. bool *hash_based,
  1351. uint8_t *lmac_peer_id_msb)
  1352. {
  1353. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1354. }
  1355. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1356. uint32_t *remap0,
  1357. uint32_t *remap1,
  1358. uint32_t *remap2)
  1359. {
  1360. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1361. }
  1362. #endif
  1363. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1364. struct dp_vdev *vdev,
  1365. enum cdp_vdev_param_type param,
  1366. cdp_config_param_type val)
  1367. {
  1368. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1369. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1370. switch (param) {
  1371. case CDP_TX_ENCAP_TYPE:
  1372. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1373. case CDP_UPDATE_TDLS_FLAGS:
  1374. dp_tx_update_bank_profile(be_soc, be_vdev);
  1375. break;
  1376. case CDP_ENABLE_CIPHER:
  1377. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1378. dp_tx_update_bank_profile(be_soc, be_vdev);
  1379. break;
  1380. case CDP_SET_MCAST_VDEV:
  1381. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1382. break;
  1383. default:
  1384. dp_warn("invalid param %d", param);
  1385. break;
  1386. }
  1387. return QDF_STATUS_SUCCESS;
  1388. }
  1389. #ifdef WLAN_FEATURE_11BE_MLO
  1390. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1391. static inline void
  1392. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1393. {
  1394. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1395. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1396. /*
  1397. * Double the peers since we use ML indication bit
  1398. * alongwith peer_id to find peers.
  1399. */
  1400. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1401. }
  1402. #else
  1403. static inline void
  1404. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1405. {
  1406. soc->max_peer_id =
  1407. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1408. }
  1409. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1410. #else
  1411. static inline void
  1412. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1413. {
  1414. soc->max_peer_id = soc->max_peers;
  1415. }
  1416. #endif /* WLAN_FEATURE_11BE_MLO */
  1417. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1418. {
  1419. }
  1420. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1421. {
  1422. dp_soc_max_peer_id_set(soc);
  1423. return QDF_STATUS_SUCCESS;
  1424. }
  1425. #ifdef WLAN_FEATURE_11BE_MLO
  1426. #ifdef WLAN_MCAST_MLO
  1427. static inline void
  1428. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1429. {
  1430. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1431. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1432. }
  1433. #else /* WLAN_MCAST_MLO */
  1434. static inline void
  1435. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1436. {
  1437. }
  1438. #endif /* WLAN_MCAST_MLO */
  1439. static inline void
  1440. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1441. {
  1442. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1443. arch_ops->mlo_peer_find_hash_detach =
  1444. dp_mlo_peer_find_hash_detach_wrapper;
  1445. arch_ops->mlo_peer_find_hash_attach =
  1446. dp_mlo_peer_find_hash_attach_wrapper;
  1447. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1448. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1449. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1450. }
  1451. #else /* WLAN_FEATURE_11BE_MLO */
  1452. static inline void
  1453. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1454. {
  1455. }
  1456. #endif /* WLAN_FEATURE_11BE_MLO */
  1457. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1458. {
  1459. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1460. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1461. arch_ops->dp_rx_process = dp_rx_process_be;
  1462. arch_ops->tx_comp_get_params_from_hal_desc =
  1463. dp_tx_comp_get_params_from_hal_desc_be;
  1464. arch_ops->dp_tx_process_htt_completion =
  1465. dp_tx_process_htt_completion_be;
  1466. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1467. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1468. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1469. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1470. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1471. dp_wbm_get_rx_desc_from_hal_desc_be;
  1472. #endif
  1473. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1474. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1475. arch_ops->dp_rx_desc_cookie_2_va =
  1476. dp_rx_desc_cookie_2_va_be;
  1477. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1478. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1479. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1480. arch_ops->txrx_soc_init = dp_soc_init_be;
  1481. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1482. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1483. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1484. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1485. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1486. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1487. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1488. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1489. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1490. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1491. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1492. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1493. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1494. dp_rx_peer_metadata_peer_id_get_be;
  1495. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1496. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1497. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1498. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1499. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1500. dp_initialize_arch_ops_be_mlo(arch_ops);
  1501. arch_ops->dp_peer_rx_reorder_queue_setup =
  1502. dp_peer_rx_reorder_queue_setup_be;
  1503. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1504. dp_init_near_full_arch_ops_be(arch_ops);
  1505. }