cam_mem_mgr.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  13. #include <linux/mem-buf.h>
  14. #include <soc/qcom/secure_buffer.h>
  15. #endif
  16. #include "cam_compat.h"
  17. #include "cam_req_mgr_util.h"
  18. #include "cam_mem_mgr.h"
  19. #include "cam_smmu_api.h"
  20. #include "cam_debug_util.h"
  21. #include "cam_trace.h"
  22. #include "cam_common_util.h"
  23. #define CAM_MEM_SHARED_BUFFER_PAD_4K (4 * 1024)
  24. static struct cam_mem_table tbl;
  25. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  26. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  27. static void cam_mem_mgr_put_dma_heaps(void);
  28. static int cam_mem_mgr_get_dma_heaps(void);
  29. #endif
  30. static void cam_mem_mgr_print_tbl(void)
  31. {
  32. int i;
  33. uint64_t ms, tmp, hrs, min, sec;
  34. struct timespec64 *ts = NULL;
  35. struct timespec64 current_ts;
  36. ktime_get_real_ts64(&(current_ts));
  37. tmp = current_ts.tv_sec;
  38. ms = (current_ts.tv_nsec) / 1000000;
  39. sec = do_div(tmp, 60);
  40. min = do_div(tmp, 60);
  41. hrs = do_div(tmp, 24);
  42. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  43. hrs, min, sec, ms);
  44. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  45. if (tbl.bufq[i].active) {
  46. ts = &tbl.bufq[i].timestamp;
  47. tmp = ts->tv_sec;
  48. ms = (ts->tv_nsec) / 1000000;
  49. sec = do_div(tmp, 60);
  50. min = do_div(tmp, 60);
  51. hrs = do_div(tmp, 24);
  52. CAM_INFO(CAM_MEM,
  53. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  54. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  55. tbl.bufq[i].len);
  56. }
  57. }
  58. }
  59. static int cam_mem_util_get_dma_dir(uint32_t flags)
  60. {
  61. int rc = -EINVAL;
  62. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  63. rc = DMA_TO_DEVICE;
  64. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  65. rc = DMA_FROM_DEVICE;
  66. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  67. rc = DMA_BIDIRECTIONAL;
  68. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  69. rc = DMA_BIDIRECTIONAL;
  70. return rc;
  71. }
  72. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  73. uintptr_t *vaddr,
  74. size_t *len)
  75. {
  76. int rc = 0;
  77. void *addr;
  78. /*
  79. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  80. * need to be called in pair to avoid stability issue.
  81. */
  82. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  83. if (rc) {
  84. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  85. return rc;
  86. }
  87. addr = dma_buf_vmap(dmabuf);
  88. if (!addr) {
  89. CAM_ERR(CAM_MEM, "kernel map fail");
  90. *vaddr = 0;
  91. *len = 0;
  92. rc = -ENOSPC;
  93. goto fail;
  94. }
  95. *vaddr = (uint64_t)addr;
  96. *len = dmabuf->size;
  97. return 0;
  98. fail:
  99. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  100. return rc;
  101. }
  102. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  103. uint64_t vaddr)
  104. {
  105. int rc = 0;
  106. if (!dmabuf || !vaddr) {
  107. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  108. return -EINVAL;
  109. }
  110. dma_buf_vunmap(dmabuf, (void *)vaddr);
  111. /*
  112. * dma_buf_begin_cpu_access() and
  113. * dma_buf_end_cpu_access() need to be called in pair
  114. * to avoid stability issue.
  115. */
  116. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  117. if (rc) {
  118. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  119. dmabuf);
  120. return rc;
  121. }
  122. return rc;
  123. }
  124. static int cam_mem_mgr_create_debug_fs(void)
  125. {
  126. int rc = 0;
  127. struct dentry *dbgfileptr = NULL;
  128. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  129. if (!dbgfileptr) {
  130. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  131. rc = -ENOENT;
  132. goto end;
  133. }
  134. /* Store parent inode for cleanup in caller */
  135. tbl.dentry = dbgfileptr;
  136. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  137. tbl.dentry, &tbl.alloc_profile_enable);
  138. if (IS_ERR(dbgfileptr)) {
  139. if (PTR_ERR(dbgfileptr) == -ENODEV)
  140. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  141. else
  142. rc = PTR_ERR(dbgfileptr);
  143. }
  144. end:
  145. return rc;
  146. }
  147. int cam_mem_mgr_init(void)
  148. {
  149. int i;
  150. int bitmap_size;
  151. int rc = 0;
  152. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  153. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  154. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  155. return -EINVAL;
  156. }
  157. tbl.need_shared_buffer_padding = cam_smmu_need_shared_buffer_padding();
  158. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  159. rc = cam_mem_mgr_get_dma_heaps();
  160. if (rc) {
  161. CAM_ERR(CAM_MEM, "Failed in getting dma heaps rc=%d", rc);
  162. return rc;
  163. }
  164. #endif
  165. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  166. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  167. if (!tbl.bitmap) {
  168. rc = -ENOMEM;
  169. goto put_heaps;
  170. }
  171. tbl.bits = bitmap_size * BITS_PER_BYTE;
  172. bitmap_zero(tbl.bitmap, tbl.bits);
  173. /* We need to reserve slot 0 because 0 is invalid */
  174. set_bit(0, tbl.bitmap);
  175. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  176. tbl.bufq[i].fd = -1;
  177. tbl.bufq[i].buf_handle = -1;
  178. }
  179. mutex_init(&tbl.m_lock);
  180. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  181. cam_mem_mgr_create_debug_fs();
  182. return 0;
  183. put_heaps:
  184. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  185. cam_mem_mgr_put_dma_heaps();
  186. #endif
  187. return rc;
  188. }
  189. static int32_t cam_mem_get_slot(void)
  190. {
  191. int32_t idx;
  192. mutex_lock(&tbl.m_lock);
  193. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  194. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  195. mutex_unlock(&tbl.m_lock);
  196. return -ENOMEM;
  197. }
  198. set_bit(idx, tbl.bitmap);
  199. tbl.bufq[idx].active = true;
  200. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  201. mutex_init(&tbl.bufq[idx].q_lock);
  202. mutex_unlock(&tbl.m_lock);
  203. return idx;
  204. }
  205. static void cam_mem_put_slot(int32_t idx)
  206. {
  207. mutex_lock(&tbl.m_lock);
  208. mutex_lock(&tbl.bufq[idx].q_lock);
  209. tbl.bufq[idx].active = false;
  210. tbl.bufq[idx].is_internal = false;
  211. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  212. mutex_unlock(&tbl.bufq[idx].q_lock);
  213. mutex_destroy(&tbl.bufq[idx].q_lock);
  214. clear_bit(idx, tbl.bitmap);
  215. mutex_unlock(&tbl.m_lock);
  216. }
  217. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  218. dma_addr_t *iova_ptr, size_t *len_ptr)
  219. {
  220. int rc = 0, idx;
  221. *len_ptr = 0;
  222. if (!atomic_read(&cam_mem_mgr_state)) {
  223. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  224. return -EINVAL;
  225. }
  226. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  227. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  228. return -ENOENT;
  229. if (!tbl.bufq[idx].active) {
  230. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  231. idx);
  232. return -EAGAIN;
  233. }
  234. mutex_lock(&tbl.bufq[idx].q_lock);
  235. if (buf_handle != tbl.bufq[idx].buf_handle) {
  236. rc = -EINVAL;
  237. goto handle_mismatch;
  238. }
  239. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  240. rc = cam_smmu_get_stage2_iova(mmu_handle,
  241. tbl.bufq[idx].fd,
  242. iova_ptr,
  243. len_ptr);
  244. else
  245. rc = cam_smmu_get_iova(mmu_handle,
  246. tbl.bufq[idx].fd,
  247. iova_ptr,
  248. len_ptr);
  249. if (rc) {
  250. CAM_ERR(CAM_MEM,
  251. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  252. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  253. goto handle_mismatch;
  254. }
  255. CAM_DBG(CAM_MEM,
  256. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  257. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  258. handle_mismatch:
  259. mutex_unlock(&tbl.bufq[idx].q_lock);
  260. return rc;
  261. }
  262. EXPORT_SYMBOL(cam_mem_get_io_buf);
  263. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  264. {
  265. int idx;
  266. if (!atomic_read(&cam_mem_mgr_state)) {
  267. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  268. return -EINVAL;
  269. }
  270. if (!atomic_read(&cam_mem_mgr_state)) {
  271. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  272. return -EINVAL;
  273. }
  274. if (!buf_handle || !vaddr_ptr || !len)
  275. return -EINVAL;
  276. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  277. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  278. return -EINVAL;
  279. if (!tbl.bufq[idx].active) {
  280. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  281. idx);
  282. return -EPERM;
  283. }
  284. if (buf_handle != tbl.bufq[idx].buf_handle)
  285. return -EINVAL;
  286. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  287. return -EINVAL;
  288. if (tbl.bufq[idx].kmdvaddr) {
  289. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  290. *len = tbl.bufq[idx].len;
  291. } else {
  292. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  293. buf_handle);
  294. return -EINVAL;
  295. }
  296. return 0;
  297. }
  298. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  299. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  300. {
  301. int rc = 0, idx;
  302. uint32_t cache_dir;
  303. unsigned long dmabuf_flag = 0;
  304. if (!atomic_read(&cam_mem_mgr_state)) {
  305. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  306. return -EINVAL;
  307. }
  308. if (!cmd)
  309. return -EINVAL;
  310. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  311. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  312. return -EINVAL;
  313. mutex_lock(&tbl.bufq[idx].q_lock);
  314. if (!tbl.bufq[idx].active) {
  315. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  316. idx);
  317. rc = -EINVAL;
  318. goto end;
  319. }
  320. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  321. rc = -EINVAL;
  322. goto end;
  323. }
  324. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  325. if (rc) {
  326. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  327. goto end;
  328. }
  329. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  330. CAM_DBG(CAM_MEM, "Calling dmap buf APIs for cache operations");
  331. cache_dir = DMA_BIDIRECTIONAL;
  332. #else
  333. if (dmabuf_flag & ION_FLAG_CACHED) {
  334. switch (cmd->mem_cache_ops) {
  335. case CAM_MEM_CLEAN_CACHE:
  336. cache_dir = DMA_TO_DEVICE;
  337. break;
  338. case CAM_MEM_INV_CACHE:
  339. cache_dir = DMA_FROM_DEVICE;
  340. break;
  341. case CAM_MEM_CLEAN_INV_CACHE:
  342. cache_dir = DMA_BIDIRECTIONAL;
  343. break;
  344. default:
  345. CAM_ERR(CAM_MEM,
  346. "invalid cache ops :%d", cmd->mem_cache_ops);
  347. rc = -EINVAL;
  348. goto end;
  349. }
  350. } else {
  351. CAM_DBG(CAM_MEM, "BUF is not cached");
  352. goto end;
  353. }
  354. #endif
  355. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  356. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  357. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  358. if (rc) {
  359. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  360. goto end;
  361. }
  362. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  363. cache_dir);
  364. if (rc) {
  365. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  366. goto end;
  367. }
  368. end:
  369. mutex_unlock(&tbl.bufq[idx].q_lock);
  370. return rc;
  371. }
  372. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  373. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  374. #define CAM_MAX_VMIDS 4
  375. static void cam_mem_mgr_put_dma_heaps(void)
  376. {
  377. CAM_DBG(CAM_MEM, "Releasing DMA Buf heaps usage");
  378. }
  379. static int cam_mem_mgr_get_dma_heaps(void)
  380. {
  381. int rc = 0;
  382. tbl.system_heap = NULL;
  383. tbl.system_uncached_heap = NULL;
  384. tbl.camera_heap = NULL;
  385. tbl.camera_uncached_heap = NULL;
  386. tbl.secure_display_heap = NULL;
  387. tbl.system_heap = dma_heap_find("qcom,system");
  388. if (IS_ERR_OR_NULL(tbl.system_heap)) {
  389. rc = PTR_ERR(tbl.system_heap);
  390. CAM_ERR(CAM_MEM, "qcom system heap not found, rc=%d", rc);
  391. tbl.system_heap = NULL;
  392. goto put_heaps;
  393. }
  394. tbl.system_uncached_heap = dma_heap_find("qcom,system-uncached");
  395. if (IS_ERR_OR_NULL(tbl.system_uncached_heap)) {
  396. if (tbl.force_cache_allocs) {
  397. /* optional, we anyway do not use uncached */
  398. CAM_DBG(CAM_MEM,
  399. "qcom system-uncached heap not found, err=%d",
  400. PTR_ERR(tbl.system_uncached_heap));
  401. tbl.system_uncached_heap = NULL;
  402. } else {
  403. /* fatal, must need uncached heaps */
  404. rc = PTR_ERR(tbl.system_uncached_heap);
  405. CAM_ERR(CAM_MEM,
  406. "qcom system-uncached heap not found, rc=%d",
  407. rc);
  408. tbl.system_uncached_heap = NULL;
  409. goto put_heaps;
  410. }
  411. }
  412. tbl.secure_display_heap = dma_heap_find("qcom,display");
  413. if (IS_ERR_OR_NULL(tbl.secure_display_heap)) {
  414. rc = PTR_ERR(tbl.secure_display_heap);
  415. CAM_ERR(CAM_MEM, "qcom,display heap not found, rc=%d",
  416. rc);
  417. tbl.secure_display_heap = NULL;
  418. goto put_heaps;
  419. }
  420. tbl.camera_heap = dma_heap_find("qcom,camera");
  421. if (IS_ERR_OR_NULL(tbl.camera_heap)) {
  422. /* optional heap, not a fatal error */
  423. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  424. PTR_ERR(tbl.camera_heap));
  425. tbl.camera_heap = NULL;
  426. }
  427. tbl.camera_uncached_heap = dma_heap_find("qcom,camera-uncached");
  428. if (IS_ERR_OR_NULL(tbl.camera_uncached_heap)) {
  429. /* optional heap, not a fatal error */
  430. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  431. PTR_ERR(tbl.camera_uncached_heap));
  432. tbl.camera_uncached_heap = NULL;
  433. }
  434. CAM_INFO(CAM_MEM,
  435. "Heaps : system=%pK, system_uncached=%pK, camera=%pK, camera-uncached=%pK, secure_display=%pK",
  436. tbl.system_heap, tbl.system_uncached_heap,
  437. tbl.camera_heap, tbl.camera_uncached_heap,
  438. tbl.secure_display_heap);
  439. return 0;
  440. put_heaps:
  441. cam_mem_mgr_put_dma_heaps();
  442. return rc;
  443. }
  444. static int cam_mem_util_get_dma_buf(size_t len,
  445. unsigned int cam_flags,
  446. struct dma_buf **buf)
  447. {
  448. int rc = 0;
  449. struct dma_heap *heap;
  450. struct dma_heap *try_heap = NULL;
  451. struct timespec64 ts1, ts2;
  452. long microsec = 0;
  453. bool use_cached_heap = false;
  454. struct mem_buf_lend_kernel_arg arg;
  455. int vmids[CAM_MAX_VMIDS];
  456. int perms[CAM_MAX_VMIDS];
  457. int num_vmids = 0;
  458. if (!buf) {
  459. CAM_ERR(CAM_MEM, "Invalid params");
  460. return -EINVAL;
  461. }
  462. if (tbl.alloc_profile_enable)
  463. CAM_GET_TIMESTAMP(ts1);
  464. if ((cam_flags & CAM_MEM_FLAG_CACHE) ||
  465. (tbl.force_cache_allocs &&
  466. (!(cam_flags & CAM_MEM_FLAG_PROTECTED_MODE)))) {
  467. CAM_DBG(CAM_MEM,
  468. "Using CACHED heap, cam_flags=0x%x, force_cache_allocs=%d",
  469. cam_flags, tbl.force_cache_allocs);
  470. use_cached_heap = true;
  471. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  472. use_cached_heap = true;
  473. CAM_DBG(CAM_MEM,
  474. "Using CACHED heap for secure, cam_flags=0x%x, force_cache_allocs=%d",
  475. cam_flags, tbl.force_cache_allocs);
  476. } else {
  477. use_cached_heap = false;
  478. CAM_ERR(CAM_MEM,
  479. "Using UNCACHED heap not supported, cam_flags=0x%x, force_cache_allocs=%d",
  480. cam_flags, tbl.force_cache_allocs);
  481. /*
  482. * Need a better handling based on whether dma-buf-heaps support
  483. * uncached heaps or not. For now, assume not supported.
  484. */
  485. return -EINVAL;
  486. }
  487. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  488. heap = tbl.secure_display_heap;
  489. vmids[num_vmids] = VMID_CP_CAMERA;
  490. perms[num_vmids] = PERM_READ | PERM_WRITE;
  491. num_vmids++;
  492. if (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT) {
  493. CAM_DBG(CAM_MEM, "Secure mode CDSP flags");
  494. vmids[num_vmids] = VMID_CP_CDSP;
  495. perms[num_vmids] = PERM_READ | PERM_WRITE;
  496. num_vmids++;
  497. }
  498. } else if (use_cached_heap) {
  499. try_heap = tbl.camera_heap;
  500. heap = tbl.system_heap;
  501. } else {
  502. try_heap = tbl.camera_uncached_heap;
  503. heap = tbl.system_uncached_heap;
  504. }
  505. CAM_DBG(CAM_MEM, "Using heaps : try=%pK, heap=%pK", try_heap, heap);
  506. *buf = NULL;
  507. if (!try_heap && !heap) {
  508. CAM_ERR(CAM_MEM,
  509. "No heap available for allocation, cant allocate");
  510. return -EINVAL;
  511. }
  512. if (try_heap) {
  513. *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0);
  514. if (IS_ERR(*buf)) {
  515. CAM_WARN(CAM_MEM,
  516. "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d",
  517. try_heap, len, PTR_ERR(*buf));
  518. *buf = NULL;
  519. }
  520. }
  521. if (*buf == NULL) {
  522. *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0);
  523. if (IS_ERR(*buf)) {
  524. rc = PTR_ERR(*buf);
  525. CAM_ERR(CAM_MEM,
  526. "Failed in allocating from heap, heap=%pK, len=%zu, err=%d",
  527. heap, len, rc);
  528. *buf = NULL;
  529. return rc;
  530. }
  531. }
  532. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  533. if (num_vmids >= CAM_MAX_VMIDS) {
  534. CAM_ERR(CAM_MEM, "Insufficient array size for vmids %d", num_vmids);
  535. rc = -EINVAL;
  536. goto end;
  537. }
  538. arg.nr_acl_entries = num_vmids;
  539. arg.vmids = vmids;
  540. arg.perms = perms;
  541. rc = mem_buf_lend(*buf, &arg);
  542. if (rc) {
  543. CAM_ERR(CAM_MEM,
  544. "Failed in buf lend rc=%d, buf=%pK, vmids [0]=0x%x, [1]=0x%x, [2]=0x%x",
  545. rc, *buf, vmids[0], vmids[1], vmids[2]);
  546. goto end;
  547. }
  548. }
  549. CAM_DBG(CAM_MEM, "Allocate success, len=%zu, *buf=%pK", len, *buf);
  550. if (tbl.alloc_profile_enable) {
  551. CAM_GET_TIMESTAMP(ts2);
  552. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  553. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  554. len, microsec);
  555. }
  556. return rc;
  557. end:
  558. dma_buf_put(*buf);
  559. return rc;
  560. }
  561. #else
  562. static int cam_mem_util_get_dma_buf(size_t len,
  563. unsigned int cam_flags,
  564. struct dma_buf **buf)
  565. {
  566. int rc = 0;
  567. unsigned int heap_id;
  568. int32_t ion_flag = 0;
  569. struct timespec64 ts1, ts2;
  570. long microsec = 0;
  571. if (!buf) {
  572. CAM_ERR(CAM_MEM, "Invalid params");
  573. return -EINVAL;
  574. }
  575. if (tbl.alloc_profile_enable)
  576. CAM_GET_TIMESTAMP(ts1);
  577. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  578. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  579. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  580. ion_flag |=
  581. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  582. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  583. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  584. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  585. } else {
  586. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  587. ION_HEAP(ION_CAMERA_HEAP_ID);
  588. }
  589. if (cam_flags & CAM_MEM_FLAG_CACHE)
  590. ion_flag |= ION_FLAG_CACHED;
  591. else
  592. ion_flag &= ~ION_FLAG_CACHED;
  593. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  594. ion_flag |= ION_FLAG_CACHED;
  595. *buf = ion_alloc(len, heap_id, ion_flag);
  596. if (IS_ERR_OR_NULL(*buf))
  597. return -ENOMEM;
  598. if (tbl.alloc_profile_enable) {
  599. CAM_GET_TIMESTAMP(ts2);
  600. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  601. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  602. len, microsec);
  603. }
  604. return rc;
  605. }
  606. #endif
  607. static int cam_mem_util_buffer_alloc(size_t len, uint32_t flags,
  608. struct dma_buf **dmabuf,
  609. int *fd)
  610. {
  611. int rc;
  612. struct dma_buf *temp_dmabuf = NULL;
  613. rc = cam_mem_util_get_dma_buf(len, flags, dmabuf);
  614. if (rc) {
  615. CAM_ERR(CAM_MEM,
  616. "Error allocating dma buf : len=%llu, flags=0x%x",
  617. len, flags);
  618. return rc;
  619. }
  620. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  621. if (*fd < 0) {
  622. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  623. rc = -EINVAL;
  624. goto put_buf;
  625. }
  626. CAM_DBG(CAM_MEM, "Alloc success : len=%zu, *dmabuf=%pK, fd=%d",
  627. len, *dmabuf, *fd);
  628. /*
  629. * increment the ref count so that ref count becomes 2 here
  630. * when we close fd, refcount becomes 1 and when we do
  631. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  632. */
  633. temp_dmabuf = dma_buf_get(*fd);
  634. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  635. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  636. rc = -EINVAL;
  637. goto put_buf;
  638. }
  639. return rc;
  640. put_buf:
  641. dma_buf_put(*dmabuf);
  642. return rc;
  643. }
  644. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  645. {
  646. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  647. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  648. CAM_MEM_MMU_MAX_HANDLE);
  649. return -EINVAL;
  650. }
  651. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  652. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  653. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  654. return -EINVAL;
  655. }
  656. return 0;
  657. }
  658. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  659. {
  660. if (!cmd->flags) {
  661. CAM_ERR(CAM_MEM, "Invalid flags");
  662. return -EINVAL;
  663. }
  664. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  665. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  666. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  667. return -EINVAL;
  668. }
  669. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  670. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  671. CAM_ERR(CAM_MEM,
  672. "Kernel mapping in secure mode not allowed, flags=0x%x",
  673. cmd->flags);
  674. return -EINVAL;
  675. }
  676. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  677. CAM_ERR(CAM_MEM,
  678. "Shared memory buffers are not allowed to be mapped");
  679. return -EINVAL;
  680. }
  681. return 0;
  682. }
  683. static int cam_mem_util_map_hw_va(uint32_t flags,
  684. int32_t *mmu_hdls,
  685. int32_t num_hdls,
  686. int fd,
  687. dma_addr_t *hw_vaddr,
  688. size_t *len,
  689. enum cam_smmu_region_id region,
  690. bool is_internal)
  691. {
  692. int i;
  693. int rc = -1;
  694. int dir = cam_mem_util_get_dma_dir(flags);
  695. bool dis_delayed_unmap = false;
  696. if (dir < 0) {
  697. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  698. return dir;
  699. }
  700. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  701. dis_delayed_unmap = true;
  702. CAM_DBG(CAM_MEM,
  703. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  704. fd, flags, dir, num_hdls);
  705. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  706. for (i = 0; i < num_hdls; i++) {
  707. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  708. fd,
  709. dir,
  710. hw_vaddr,
  711. len);
  712. if (rc < 0) {
  713. CAM_ERR(CAM_MEM,
  714. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  715. i, fd, dir, mmu_hdls[i], rc);
  716. goto multi_map_fail;
  717. }
  718. }
  719. } else {
  720. for (i = 0; i < num_hdls; i++) {
  721. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  722. fd,
  723. dis_delayed_unmap,
  724. dir,
  725. (dma_addr_t *)hw_vaddr,
  726. len,
  727. region,
  728. is_internal);
  729. if (rc < 0) {
  730. CAM_ERR(CAM_MEM,
  731. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  732. i, fd, dir, mmu_hdls[i], region, rc);
  733. goto multi_map_fail;
  734. }
  735. }
  736. }
  737. return rc;
  738. multi_map_fail:
  739. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  740. for (--i; i >= 0; i--)
  741. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  742. else
  743. for (--i; i >= 0; i--)
  744. cam_smmu_unmap_user_iova(mmu_hdls[i],
  745. fd,
  746. CAM_SMMU_REGION_IO);
  747. return rc;
  748. }
  749. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  750. {
  751. int rc;
  752. int32_t idx;
  753. struct dma_buf *dmabuf = NULL;
  754. int fd = -1;
  755. dma_addr_t hw_vaddr = 0;
  756. size_t len;
  757. uintptr_t kvaddr = 0;
  758. size_t klen;
  759. if (!atomic_read(&cam_mem_mgr_state)) {
  760. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  761. return -EINVAL;
  762. }
  763. if (!cmd) {
  764. CAM_ERR(CAM_MEM, " Invalid argument");
  765. return -EINVAL;
  766. }
  767. len = cmd->len;
  768. if (tbl.need_shared_buffer_padding &&
  769. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)) {
  770. len += CAM_MEM_SHARED_BUFFER_PAD_4K;
  771. CAM_DBG(CAM_MEM, "Pad 4k size, actual %llu, allocating %zu",
  772. cmd->len, len);
  773. }
  774. rc = cam_mem_util_check_alloc_flags(cmd);
  775. if (rc) {
  776. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  777. cmd->flags, rc);
  778. return rc;
  779. }
  780. rc = cam_mem_util_buffer_alloc(len, cmd->flags, &dmabuf, &fd);
  781. if (rc) {
  782. CAM_ERR(CAM_MEM,
  783. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  784. len, cmd->align, cmd->flags, cmd->num_hdl);
  785. cam_mem_mgr_print_tbl();
  786. return rc;
  787. }
  788. if (!dmabuf) {
  789. CAM_ERR(CAM_MEM,
  790. "Ion Alloc return NULL dmabuf! fd=%d, len=%d", fd, len);
  791. cam_mem_mgr_print_tbl();
  792. return rc;
  793. }
  794. idx = cam_mem_get_slot();
  795. if (idx < 0) {
  796. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  797. rc = -ENOMEM;
  798. goto slot_fail;
  799. }
  800. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  801. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  802. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  803. enum cam_smmu_region_id region;
  804. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  805. region = CAM_SMMU_REGION_IO;
  806. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  807. region = CAM_SMMU_REGION_SHARED;
  808. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  809. region = CAM_SMMU_REGION_IO;
  810. rc = cam_mem_util_map_hw_va(cmd->flags,
  811. cmd->mmu_hdls,
  812. cmd->num_hdl,
  813. fd,
  814. &hw_vaddr,
  815. &len,
  816. region,
  817. true);
  818. if (rc) {
  819. CAM_ERR(CAM_MEM,
  820. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  821. len, cmd->flags,
  822. fd, region, cmd->num_hdl, rc);
  823. if (rc == -EALREADY) {
  824. if ((size_t)dmabuf->size != len)
  825. rc = -EBADR;
  826. cam_mem_mgr_print_tbl();
  827. }
  828. goto map_hw_fail;
  829. }
  830. }
  831. mutex_lock(&tbl.bufq[idx].q_lock);
  832. tbl.bufq[idx].fd = fd;
  833. tbl.bufq[idx].dma_buf = NULL;
  834. tbl.bufq[idx].flags = cmd->flags;
  835. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  836. tbl.bufq[idx].is_internal = true;
  837. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  838. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  839. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  840. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  841. if (rc) {
  842. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  843. dmabuf, rc);
  844. goto map_kernel_fail;
  845. }
  846. }
  847. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  848. tbl.dbg_buf_idx = idx;
  849. tbl.bufq[idx].kmdvaddr = kvaddr;
  850. tbl.bufq[idx].vaddr = hw_vaddr;
  851. tbl.bufq[idx].dma_buf = dmabuf;
  852. tbl.bufq[idx].len = len;
  853. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  854. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  855. sizeof(int32_t) * cmd->num_hdl);
  856. tbl.bufq[idx].is_imported = false;
  857. mutex_unlock(&tbl.bufq[idx].q_lock);
  858. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  859. cmd->out.fd = tbl.bufq[idx].fd;
  860. cmd->out.vaddr = 0;
  861. CAM_DBG(CAM_MEM,
  862. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  863. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  864. tbl.bufq[idx].len);
  865. return rc;
  866. map_kernel_fail:
  867. mutex_unlock(&tbl.bufq[idx].q_lock);
  868. map_hw_fail:
  869. cam_mem_put_slot(idx);
  870. slot_fail:
  871. dma_buf_put(dmabuf);
  872. return rc;
  873. }
  874. static bool cam_mem_util_is_map_internal(int32_t fd)
  875. {
  876. uint32_t i;
  877. bool is_internal = false;
  878. mutex_lock(&tbl.m_lock);
  879. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  880. if (tbl.bufq[i].fd == fd) {
  881. is_internal = tbl.bufq[i].is_internal;
  882. break;
  883. }
  884. }
  885. mutex_unlock(&tbl.m_lock);
  886. return is_internal;
  887. }
  888. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  889. {
  890. int32_t idx;
  891. int rc;
  892. struct dma_buf *dmabuf;
  893. dma_addr_t hw_vaddr = 0;
  894. size_t len = 0;
  895. bool is_internal = false;
  896. if (!atomic_read(&cam_mem_mgr_state)) {
  897. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  898. return -EINVAL;
  899. }
  900. if (!cmd || (cmd->fd < 0)) {
  901. CAM_ERR(CAM_MEM, "Invalid argument");
  902. return -EINVAL;
  903. }
  904. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  905. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  906. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  907. return -EINVAL;
  908. }
  909. rc = cam_mem_util_check_map_flags(cmd);
  910. if (rc) {
  911. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  912. return rc;
  913. }
  914. dmabuf = dma_buf_get(cmd->fd);
  915. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  916. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  917. return -EINVAL;
  918. }
  919. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  920. idx = cam_mem_get_slot();
  921. if (idx < 0) {
  922. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  923. idx, cmd->fd);
  924. rc = -ENOMEM;
  925. goto slot_fail;
  926. }
  927. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  928. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  929. rc = cam_mem_util_map_hw_va(cmd->flags,
  930. cmd->mmu_hdls,
  931. cmd->num_hdl,
  932. cmd->fd,
  933. &hw_vaddr,
  934. &len,
  935. CAM_SMMU_REGION_IO,
  936. is_internal);
  937. if (rc) {
  938. CAM_ERR(CAM_MEM,
  939. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  940. cmd->flags, cmd->fd, len,
  941. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  942. if (rc == -EALREADY) {
  943. if ((size_t)dmabuf->size != len) {
  944. rc = -EBADR;
  945. cam_mem_mgr_print_tbl();
  946. }
  947. }
  948. goto map_fail;
  949. }
  950. }
  951. mutex_lock(&tbl.bufq[idx].q_lock);
  952. tbl.bufq[idx].fd = cmd->fd;
  953. tbl.bufq[idx].dma_buf = NULL;
  954. tbl.bufq[idx].flags = cmd->flags;
  955. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  956. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  957. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  958. tbl.bufq[idx].kmdvaddr = 0;
  959. if (cmd->num_hdl > 0)
  960. tbl.bufq[idx].vaddr = hw_vaddr;
  961. else
  962. tbl.bufq[idx].vaddr = 0;
  963. tbl.bufq[idx].dma_buf = dmabuf;
  964. tbl.bufq[idx].len = len;
  965. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  966. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  967. sizeof(int32_t) * cmd->num_hdl);
  968. tbl.bufq[idx].is_imported = true;
  969. tbl.bufq[idx].is_internal = is_internal;
  970. mutex_unlock(&tbl.bufq[idx].q_lock);
  971. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  972. cmd->out.vaddr = 0;
  973. cmd->out.size = (uint32_t)len;
  974. CAM_DBG(CAM_MEM,
  975. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  976. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  977. tbl.bufq[idx].len);
  978. return rc;
  979. map_fail:
  980. cam_mem_put_slot(idx);
  981. slot_fail:
  982. dma_buf_put(dmabuf);
  983. return rc;
  984. }
  985. static int cam_mem_util_unmap_hw_va(int32_t idx,
  986. enum cam_smmu_region_id region,
  987. enum cam_smmu_mapping_client client)
  988. {
  989. int i;
  990. uint32_t flags;
  991. int32_t *mmu_hdls;
  992. int num_hdls;
  993. int fd;
  994. int rc = 0;
  995. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  996. CAM_ERR(CAM_MEM, "Incorrect index");
  997. return -EINVAL;
  998. }
  999. flags = tbl.bufq[idx].flags;
  1000. mmu_hdls = tbl.bufq[idx].hdls;
  1001. num_hdls = tbl.bufq[idx].num_hdl;
  1002. fd = tbl.bufq[idx].fd;
  1003. CAM_DBG(CAM_MEM,
  1004. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  1005. idx, fd, flags, num_hdls, client);
  1006. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  1007. for (i = 0; i < num_hdls; i++) {
  1008. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  1009. if (rc < 0) {
  1010. CAM_ERR(CAM_MEM,
  1011. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  1012. i, fd, mmu_hdls[i], rc);
  1013. goto unmap_end;
  1014. }
  1015. }
  1016. } else {
  1017. for (i = 0; i < num_hdls; i++) {
  1018. if (client == CAM_SMMU_MAPPING_USER) {
  1019. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  1020. fd, region);
  1021. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  1022. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  1023. tbl.bufq[idx].dma_buf, region);
  1024. } else {
  1025. CAM_ERR(CAM_MEM,
  1026. "invalid caller for unmapping : %d",
  1027. client);
  1028. rc = -EINVAL;
  1029. }
  1030. if (rc < 0) {
  1031. CAM_ERR(CAM_MEM,
  1032. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  1033. i, fd, mmu_hdls[i], region, rc);
  1034. goto unmap_end;
  1035. }
  1036. }
  1037. }
  1038. return rc;
  1039. unmap_end:
  1040. CAM_ERR(CAM_MEM, "unmapping failed");
  1041. return rc;
  1042. }
  1043. static void cam_mem_mgr_unmap_active_buf(int idx)
  1044. {
  1045. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1046. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  1047. region = CAM_SMMU_REGION_SHARED;
  1048. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1049. region = CAM_SMMU_REGION_IO;
  1050. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  1051. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  1052. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1053. tbl.bufq[idx].kmdvaddr);
  1054. }
  1055. static int cam_mem_mgr_cleanup_table(void)
  1056. {
  1057. int i;
  1058. mutex_lock(&tbl.m_lock);
  1059. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  1060. if (!tbl.bufq[i].active) {
  1061. CAM_DBG(CAM_MEM,
  1062. "Buffer inactive at idx=%d, continuing", i);
  1063. continue;
  1064. } else {
  1065. CAM_DBG(CAM_MEM,
  1066. "Active buffer at idx=%d, possible leak needs unmapping",
  1067. i);
  1068. cam_mem_mgr_unmap_active_buf(i);
  1069. }
  1070. mutex_lock(&tbl.bufq[i].q_lock);
  1071. if (tbl.bufq[i].dma_buf) {
  1072. dma_buf_put(tbl.bufq[i].dma_buf);
  1073. tbl.bufq[i].dma_buf = NULL;
  1074. }
  1075. tbl.bufq[i].fd = -1;
  1076. tbl.bufq[i].flags = 0;
  1077. tbl.bufq[i].buf_handle = -1;
  1078. tbl.bufq[i].vaddr = 0;
  1079. tbl.bufq[i].len = 0;
  1080. memset(tbl.bufq[i].hdls, 0,
  1081. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  1082. tbl.bufq[i].num_hdl = 0;
  1083. tbl.bufq[i].dma_buf = NULL;
  1084. tbl.bufq[i].active = false;
  1085. tbl.bufq[i].is_internal = false;
  1086. mutex_unlock(&tbl.bufq[i].q_lock);
  1087. mutex_destroy(&tbl.bufq[i].q_lock);
  1088. }
  1089. bitmap_zero(tbl.bitmap, tbl.bits);
  1090. /* We need to reserve slot 0 because 0 is invalid */
  1091. set_bit(0, tbl.bitmap);
  1092. mutex_unlock(&tbl.m_lock);
  1093. return 0;
  1094. }
  1095. void cam_mem_mgr_deinit(void)
  1096. {
  1097. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  1098. cam_mem_mgr_cleanup_table();
  1099. debugfs_remove_recursive(tbl.dentry);
  1100. mutex_lock(&tbl.m_lock);
  1101. bitmap_zero(tbl.bitmap, tbl.bits);
  1102. kfree(tbl.bitmap);
  1103. tbl.bitmap = NULL;
  1104. tbl.dbg_buf_idx = -1;
  1105. mutex_unlock(&tbl.m_lock);
  1106. mutex_destroy(&tbl.m_lock);
  1107. }
  1108. static int cam_mem_util_unmap(int32_t idx,
  1109. enum cam_smmu_mapping_client client)
  1110. {
  1111. int rc = 0;
  1112. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1113. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1114. CAM_ERR(CAM_MEM, "Incorrect index");
  1115. return -EINVAL;
  1116. }
  1117. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  1118. mutex_lock(&tbl.m_lock);
  1119. if ((!tbl.bufq[idx].active) &&
  1120. (tbl.bufq[idx].vaddr) == 0) {
  1121. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  1122. idx);
  1123. mutex_unlock(&tbl.m_lock);
  1124. return 0;
  1125. }
  1126. /* Deactivate the buffer queue to prevent multiple unmap */
  1127. mutex_lock(&tbl.bufq[idx].q_lock);
  1128. tbl.bufq[idx].active = false;
  1129. tbl.bufq[idx].vaddr = 0;
  1130. mutex_unlock(&tbl.bufq[idx].q_lock);
  1131. mutex_unlock(&tbl.m_lock);
  1132. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1133. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  1134. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1135. tbl.bufq[idx].kmdvaddr);
  1136. if (rc)
  1137. CAM_ERR(CAM_MEM,
  1138. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  1139. tbl.bufq[idx].dma_buf,
  1140. (void *) tbl.bufq[idx].kmdvaddr);
  1141. }
  1142. }
  1143. /* SHARED flag gets precedence, all other flags after it */
  1144. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1145. region = CAM_SMMU_REGION_SHARED;
  1146. } else {
  1147. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1148. region = CAM_SMMU_REGION_IO;
  1149. }
  1150. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  1151. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  1152. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  1153. if (cam_mem_util_unmap_hw_va(idx, region, client))
  1154. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  1155. tbl.bufq[idx].dma_buf);
  1156. if (client == CAM_SMMU_MAPPING_KERNEL)
  1157. tbl.bufq[idx].dma_buf = NULL;
  1158. }
  1159. mutex_lock(&tbl.m_lock);
  1160. mutex_lock(&tbl.bufq[idx].q_lock);
  1161. tbl.bufq[idx].flags = 0;
  1162. tbl.bufq[idx].buf_handle = -1;
  1163. memset(tbl.bufq[idx].hdls, 0,
  1164. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  1165. CAM_DBG(CAM_MEM,
  1166. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  1167. idx, tbl.bufq[idx].fd,
  1168. tbl.bufq[idx].is_imported,
  1169. tbl.bufq[idx].dma_buf);
  1170. if (tbl.bufq[idx].dma_buf)
  1171. dma_buf_put(tbl.bufq[idx].dma_buf);
  1172. tbl.bufq[idx].fd = -1;
  1173. tbl.bufq[idx].dma_buf = NULL;
  1174. tbl.bufq[idx].is_imported = false;
  1175. tbl.bufq[idx].is_internal = false;
  1176. tbl.bufq[idx].len = 0;
  1177. tbl.bufq[idx].num_hdl = 0;
  1178. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  1179. mutex_unlock(&tbl.bufq[idx].q_lock);
  1180. mutex_destroy(&tbl.bufq[idx].q_lock);
  1181. clear_bit(idx, tbl.bitmap);
  1182. mutex_unlock(&tbl.m_lock);
  1183. return rc;
  1184. }
  1185. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  1186. {
  1187. int idx;
  1188. int rc;
  1189. if (!atomic_read(&cam_mem_mgr_state)) {
  1190. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1191. return -EINVAL;
  1192. }
  1193. if (!cmd) {
  1194. CAM_ERR(CAM_MEM, "Invalid argument");
  1195. return -EINVAL;
  1196. }
  1197. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  1198. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1199. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  1200. idx);
  1201. return -EINVAL;
  1202. }
  1203. if (!tbl.bufq[idx].active) {
  1204. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1205. return -EINVAL;
  1206. }
  1207. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  1208. CAM_ERR(CAM_MEM,
  1209. "Released buf handle %d not matching within table %d, idx=%d",
  1210. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  1211. return -EINVAL;
  1212. }
  1213. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  1214. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  1215. return rc;
  1216. }
  1217. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  1218. struct cam_mem_mgr_memory_desc *out)
  1219. {
  1220. struct dma_buf *buf = NULL;
  1221. int ion_fd = -1;
  1222. int rc = 0;
  1223. uintptr_t kvaddr;
  1224. dma_addr_t iova = 0;
  1225. size_t request_len = 0;
  1226. uint32_t mem_handle;
  1227. int32_t idx;
  1228. int32_t smmu_hdl = 0;
  1229. int32_t num_hdl = 0;
  1230. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1231. if (!atomic_read(&cam_mem_mgr_state)) {
  1232. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1233. return -EINVAL;
  1234. }
  1235. if (!inp || !out) {
  1236. CAM_ERR(CAM_MEM, "Invalid params");
  1237. return -EINVAL;
  1238. }
  1239. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1240. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1241. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1242. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1243. return -EINVAL;
  1244. }
  1245. rc = cam_mem_util_get_dma_buf(inp->size, inp->flags, &buf);
  1246. if (rc) {
  1247. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1248. goto ion_fail;
  1249. } else if (!buf) {
  1250. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1251. goto ion_fail;
  1252. } else {
  1253. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1254. }
  1255. /*
  1256. * we are mapping kva always here,
  1257. * update flags so that we do unmap properly
  1258. */
  1259. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1260. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1261. if (rc) {
  1262. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1263. goto map_fail;
  1264. }
  1265. if (!inp->smmu_hdl) {
  1266. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1267. rc = -EINVAL;
  1268. goto smmu_fail;
  1269. }
  1270. /* SHARED flag gets precedence, all other flags after it */
  1271. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1272. region = CAM_SMMU_REGION_SHARED;
  1273. } else {
  1274. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1275. region = CAM_SMMU_REGION_IO;
  1276. }
  1277. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1278. buf,
  1279. CAM_SMMU_MAP_RW,
  1280. &iova,
  1281. &request_len,
  1282. region);
  1283. if (rc < 0) {
  1284. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1285. goto smmu_fail;
  1286. }
  1287. smmu_hdl = inp->smmu_hdl;
  1288. num_hdl = 1;
  1289. idx = cam_mem_get_slot();
  1290. if (idx < 0) {
  1291. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1292. rc = -ENOMEM;
  1293. goto slot_fail;
  1294. }
  1295. mutex_lock(&tbl.bufq[idx].q_lock);
  1296. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1297. tbl.bufq[idx].dma_buf = buf;
  1298. tbl.bufq[idx].fd = -1;
  1299. tbl.bufq[idx].flags = inp->flags;
  1300. tbl.bufq[idx].buf_handle = mem_handle;
  1301. tbl.bufq[idx].kmdvaddr = kvaddr;
  1302. tbl.bufq[idx].vaddr = iova;
  1303. tbl.bufq[idx].len = inp->size;
  1304. tbl.bufq[idx].num_hdl = num_hdl;
  1305. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1306. sizeof(int32_t));
  1307. tbl.bufq[idx].is_imported = false;
  1308. mutex_unlock(&tbl.bufq[idx].q_lock);
  1309. out->kva = kvaddr;
  1310. out->iova = (uint32_t)iova;
  1311. out->smmu_hdl = smmu_hdl;
  1312. out->mem_handle = mem_handle;
  1313. out->len = inp->size;
  1314. out->region = region;
  1315. return rc;
  1316. slot_fail:
  1317. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1318. buf, region);
  1319. smmu_fail:
  1320. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1321. map_fail:
  1322. dma_buf_put(buf);
  1323. ion_fail:
  1324. return rc;
  1325. }
  1326. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1327. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1328. {
  1329. int32_t idx;
  1330. int rc;
  1331. if (!atomic_read(&cam_mem_mgr_state)) {
  1332. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1333. return -EINVAL;
  1334. }
  1335. if (!inp) {
  1336. CAM_ERR(CAM_MEM, "Invalid argument");
  1337. return -EINVAL;
  1338. }
  1339. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1340. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1341. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1342. return -EINVAL;
  1343. }
  1344. if (!tbl.bufq[idx].active) {
  1345. if (tbl.bufq[idx].vaddr == 0) {
  1346. CAM_ERR(CAM_MEM, "buffer is released already");
  1347. return 0;
  1348. }
  1349. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1350. return -EINVAL;
  1351. }
  1352. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1353. CAM_ERR(CAM_MEM,
  1354. "Released buf handle not matching within table");
  1355. return -EINVAL;
  1356. }
  1357. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1358. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1359. return rc;
  1360. }
  1361. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1362. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1363. enum cam_smmu_region_id region,
  1364. struct cam_mem_mgr_memory_desc *out)
  1365. {
  1366. struct dma_buf *buf = NULL;
  1367. int rc = 0;
  1368. int ion_fd = -1;
  1369. dma_addr_t iova = 0;
  1370. size_t request_len = 0;
  1371. uint32_t mem_handle;
  1372. int32_t idx;
  1373. int32_t smmu_hdl = 0;
  1374. int32_t num_hdl = 0;
  1375. uintptr_t kvaddr = 0;
  1376. if (!atomic_read(&cam_mem_mgr_state)) {
  1377. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1378. return -EINVAL;
  1379. }
  1380. if (!inp || !out) {
  1381. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1382. return -EINVAL;
  1383. }
  1384. if (!inp->smmu_hdl) {
  1385. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1386. return -EINVAL;
  1387. }
  1388. if ((region != CAM_SMMU_REGION_SECHEAP) &&
  1389. (region != CAM_SMMU_REGION_FWUNCACHED)) {
  1390. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1391. return -EINVAL;
  1392. }
  1393. rc = cam_mem_util_get_dma_buf(inp->size, 0, &buf);
  1394. if (rc) {
  1395. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1396. goto ion_fail;
  1397. } else if (!buf) {
  1398. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1399. goto ion_fail;
  1400. } else {
  1401. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1402. }
  1403. if (inp->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1404. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1405. if (rc) {
  1406. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1407. goto kmap_fail;
  1408. }
  1409. }
  1410. rc = cam_smmu_reserve_buf_region(region,
  1411. inp->smmu_hdl, buf, &iova, &request_len);
  1412. if (rc) {
  1413. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1414. goto smmu_fail;
  1415. }
  1416. smmu_hdl = inp->smmu_hdl;
  1417. num_hdl = 1;
  1418. idx = cam_mem_get_slot();
  1419. if (idx < 0) {
  1420. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1421. rc = -ENOMEM;
  1422. goto slot_fail;
  1423. }
  1424. mutex_lock(&tbl.bufq[idx].q_lock);
  1425. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1426. tbl.bufq[idx].fd = -1;
  1427. tbl.bufq[idx].dma_buf = buf;
  1428. tbl.bufq[idx].flags = inp->flags;
  1429. tbl.bufq[idx].buf_handle = mem_handle;
  1430. tbl.bufq[idx].kmdvaddr = kvaddr;
  1431. tbl.bufq[idx].vaddr = iova;
  1432. tbl.bufq[idx].len = request_len;
  1433. tbl.bufq[idx].num_hdl = num_hdl;
  1434. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1435. sizeof(int32_t));
  1436. tbl.bufq[idx].is_imported = false;
  1437. mutex_unlock(&tbl.bufq[idx].q_lock);
  1438. out->kva = kvaddr;
  1439. out->iova = (uint32_t)iova;
  1440. out->smmu_hdl = smmu_hdl;
  1441. out->mem_handle = mem_handle;
  1442. out->len = request_len;
  1443. out->region = region;
  1444. return rc;
  1445. slot_fail:
  1446. cam_smmu_release_buf_region(region, smmu_hdl);
  1447. smmu_fail:
  1448. if (region == CAM_SMMU_REGION_FWUNCACHED)
  1449. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1450. kmap_fail:
  1451. dma_buf_put(buf);
  1452. ion_fail:
  1453. return rc;
  1454. }
  1455. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1456. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1457. {
  1458. int32_t idx;
  1459. int rc;
  1460. int32_t smmu_hdl;
  1461. if (!atomic_read(&cam_mem_mgr_state)) {
  1462. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1463. return -EINVAL;
  1464. }
  1465. if (!inp) {
  1466. CAM_ERR(CAM_MEM, "Invalid argument");
  1467. return -EINVAL;
  1468. }
  1469. if ((inp->region != CAM_SMMU_REGION_SECHEAP) &&
  1470. (inp->region != CAM_SMMU_REGION_FWUNCACHED)) {
  1471. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1472. return -EINVAL;
  1473. }
  1474. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1475. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1476. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1477. return -EINVAL;
  1478. }
  1479. if (!tbl.bufq[idx].active) {
  1480. if (tbl.bufq[idx].vaddr == 0) {
  1481. CAM_ERR(CAM_MEM, "buffer is released already");
  1482. return 0;
  1483. }
  1484. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1485. return -EINVAL;
  1486. }
  1487. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1488. CAM_ERR(CAM_MEM,
  1489. "Released buf handle not matching within table");
  1490. return -EINVAL;
  1491. }
  1492. if (tbl.bufq[idx].num_hdl != 1) {
  1493. CAM_ERR(CAM_MEM,
  1494. "Sec heap region should have only one smmu hdl");
  1495. return -ENODEV;
  1496. }
  1497. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1498. sizeof(int32_t));
  1499. if (inp->smmu_hdl != smmu_hdl) {
  1500. CAM_ERR(CAM_MEM,
  1501. "Passed SMMU handle doesn't match with internal hdl");
  1502. return -ENODEV;
  1503. }
  1504. rc = cam_smmu_release_buf_region(inp->region, inp->smmu_hdl);
  1505. if (rc) {
  1506. CAM_ERR(CAM_MEM,
  1507. "Sec heap region release failed");
  1508. return -ENODEV;
  1509. }
  1510. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1511. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1512. if (rc)
  1513. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1514. return rc;
  1515. }
  1516. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);
  1517. #ifndef CONFIG_CAM_PRESIL
  1518. struct dma_buf * cam_mem_mgr_get_dma_buf(int fd)
  1519. {
  1520. return NULL;
  1521. }
  1522. int cam_mem_mgr_send_all_buffers_to_presil(int32_t iommu_hdl)
  1523. {
  1524. return 0;
  1525. }
  1526. int cam_mem_mgr_send_buffer_to_presil(int32_t iommu_hdl, int32_t buf_handle)
  1527. {
  1528. return 0;
  1529. }
  1530. int cam_mem_mgr_retrieve_buffer_from_presil(int32_t buf_handle,
  1531. uint32_t buf_size,
  1532. uint32_t offset,
  1533. int32_t iommu_hdl)
  1534. {
  1535. return 0;
  1536. }
  1537. #endif