sde_kms.c 116 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660
  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  171. {
  172. int ret;
  173. if (!kms || !crtc)
  174. return -EINVAL;
  175. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  176. ret = sde_crtc_vblank(crtc, true);
  177. SDE_ATRACE_END("sde_kms_enable_vblank");
  178. return ret;
  179. }
  180. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  181. {
  182. if (!kms || !crtc)
  183. return;
  184. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  185. sde_crtc_vblank(crtc, false);
  186. SDE_ATRACE_END("sde_kms_disable_vblank");
  187. }
  188. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  189. struct drm_crtc *crtc)
  190. {
  191. struct drm_encoder *encoder;
  192. struct drm_device *dev;
  193. int ret;
  194. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  195. SDE_ERROR("invalid params\n");
  196. return;
  197. }
  198. if (!crtc->state->enable) {
  199. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  200. return;
  201. }
  202. if (!crtc->state->active) {
  203. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  204. return;
  205. }
  206. dev = crtc->dev;
  207. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  208. if (encoder->crtc != crtc)
  209. continue;
  210. /*
  211. * Video Mode - Wait for VSYNC
  212. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  213. * complete
  214. */
  215. SDE_EVT32_VERBOSE(DRMID(crtc));
  216. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  217. if (ret && ret != -EWOULDBLOCK) {
  218. SDE_ERROR(
  219. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  220. crtc->base.id, encoder->base.id, ret);
  221. break;
  222. }
  223. }
  224. }
  225. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  226. struct drm_crtc *crtc, bool enable)
  227. {
  228. struct drm_device *dev;
  229. struct msm_drm_private *priv;
  230. struct sde_mdss_cfg *sde_cfg;
  231. struct drm_plane *plane;
  232. int i, ret;
  233. dev = sde_kms->dev;
  234. priv = dev->dev_private;
  235. sde_cfg = sde_kms->catalog;
  236. ret = sde_vbif_halt_xin_mask(sde_kms,
  237. sde_cfg->sui_block_xin_mask, enable);
  238. if (ret) {
  239. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  240. return ret;
  241. }
  242. if (enable) {
  243. for (i = 0; i < priv->num_planes; i++) {
  244. plane = priv->planes[i];
  245. sde_plane_secure_ctrl_xin_client(plane, crtc);
  246. }
  247. }
  248. return 0;
  249. }
  250. /**
  251. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  252. * @sde_kms: Pointer to sde_kms struct
  253. * @vimd: switch the stage 2 translation to this VMID
  254. */
  255. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  256. {
  257. struct device dummy = {};
  258. dma_addr_t dma_handle;
  259. uint32_t num_sids;
  260. uint32_t *sec_sid;
  261. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  262. int ret = 0, i;
  263. struct qtee_shm shm;
  264. bool qtee_en = qtee_shmbridge_is_enabled();
  265. phys_addr_t mem_addr;
  266. u64 mem_size;
  267. num_sids = sde_cfg->sec_sid_mask_count;
  268. if (!num_sids) {
  269. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  270. return -EINVAL;
  271. }
  272. if (qtee_en) {
  273. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  274. &shm);
  275. if (ret)
  276. return -ENOMEM;
  277. sec_sid = (uint32_t *) shm.vaddr;
  278. mem_addr = shm.paddr;
  279. /**
  280. * SMMUSecureModeSwitch requires the size to be number of SID's
  281. * but shm allocates size in pages. Modify the args as per
  282. * client requirement.
  283. */
  284. mem_size = sizeof(uint32_t) * num_sids;
  285. } else {
  286. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  287. if (!sec_sid)
  288. return -ENOMEM;
  289. mem_addr = virt_to_phys(sec_sid);
  290. mem_size = sizeof(uint32_t) * num_sids;
  291. }
  292. for (i = 0; i < num_sids; i++) {
  293. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  294. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  295. }
  296. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  297. if (ret) {
  298. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  299. goto map_error;
  300. }
  301. set_dma_ops(&dummy, NULL);
  302. dma_handle = dma_map_single(&dummy, sec_sid,
  303. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  304. if (dma_mapping_error(&dummy, dma_handle)) {
  305. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  306. vmid);
  307. goto map_error;
  308. }
  309. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  310. vmid, num_sids, qtee_en);
  311. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  312. mem_size, vmid);
  313. if (ret)
  314. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  315. vmid, ret);
  316. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  317. vmid, qtee_en, num_sids, ret);
  318. dma_unmap_single(&dummy, dma_handle,
  319. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  320. map_error:
  321. if (qtee_en)
  322. qtee_shmbridge_free_shm(&shm);
  323. else
  324. kfree(sec_sid);
  325. return ret;
  326. }
  327. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  328. {
  329. u32 ret;
  330. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  331. return 0;
  332. /* detach_all_contexts */
  333. ret = sde_kms_mmu_detach(sde_kms, false);
  334. if (ret) {
  335. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  336. goto mmu_error;
  337. }
  338. ret = _sde_kms_scm_call(sde_kms, vmid);
  339. if (ret) {
  340. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  341. goto scm_error;
  342. }
  343. return 0;
  344. scm_error:
  345. sde_kms_mmu_attach(sde_kms, false);
  346. mmu_error:
  347. atomic_dec(&sde_kms->detach_all_cb);
  348. return ret;
  349. }
  350. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  351. u32 old_vmid)
  352. {
  353. u32 ret;
  354. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  355. return 0;
  356. ret = _sde_kms_scm_call(sde_kms, vmid);
  357. if (ret) {
  358. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  359. goto scm_error;
  360. }
  361. /* attach_all_contexts */
  362. ret = sde_kms_mmu_attach(sde_kms, false);
  363. if (ret) {
  364. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  365. goto mmu_error;
  366. }
  367. return 0;
  368. mmu_error:
  369. _sde_kms_scm_call(sde_kms, old_vmid);
  370. scm_error:
  371. atomic_inc(&sde_kms->detach_all_cb);
  372. return ret;
  373. }
  374. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  375. {
  376. u32 ret;
  377. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  378. return 0;
  379. /* detach secure_context */
  380. ret = sde_kms_mmu_detach(sde_kms, true);
  381. if (ret) {
  382. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  383. goto mmu_error;
  384. }
  385. ret = _sde_kms_scm_call(sde_kms, vmid);
  386. if (ret) {
  387. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  388. goto scm_error;
  389. }
  390. return 0;
  391. scm_error:
  392. sde_kms_mmu_attach(sde_kms, true);
  393. mmu_error:
  394. atomic_dec(&sde_kms->detach_sec_cb);
  395. return ret;
  396. }
  397. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  398. u32 old_vmid)
  399. {
  400. u32 ret;
  401. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  402. return 0;
  403. ret = _sde_kms_scm_call(sde_kms, vmid);
  404. if (ret) {
  405. goto scm_error;
  406. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  407. }
  408. ret = sde_kms_mmu_attach(sde_kms, true);
  409. if (ret) {
  410. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  411. goto mmu_error;
  412. }
  413. return 0;
  414. mmu_error:
  415. _sde_kms_scm_call(sde_kms, old_vmid);
  416. scm_error:
  417. atomic_inc(&sde_kms->detach_sec_cb);
  418. return ret;
  419. }
  420. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  421. struct drm_crtc *crtc, bool enable)
  422. {
  423. int ret;
  424. if (enable) {
  425. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  426. if (ret < 0) {
  427. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  428. return ret;
  429. }
  430. sde_crtc_misr_setup(crtc, true, 1);
  431. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  432. if (ret) {
  433. sde_crtc_misr_setup(crtc, false, 0);
  434. pm_runtime_put_sync(sde_kms->dev->dev);
  435. return ret;
  436. }
  437. } else {
  438. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  439. sde_crtc_misr_setup(crtc, false, 0);
  440. pm_runtime_put_sync(sde_kms->dev->dev);
  441. }
  442. return 0;
  443. }
  444. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  445. bool post_commit)
  446. {
  447. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  448. int old_smmu_state = smmu_state->state;
  449. int ret = 0;
  450. u32 vmid;
  451. if (!sde_kms || !crtc) {
  452. SDE_ERROR("invalid argument(s)\n");
  453. return -EINVAL;
  454. }
  455. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  456. post_commit, smmu_state->sui_misr_state,
  457. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  458. if ((!smmu_state->transition_type) ||
  459. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  460. /* Bail out */
  461. return 0;
  462. /* enable sui misr if requested, before the transition */
  463. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  464. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  465. if (ret) {
  466. smmu_state->sui_misr_state = NONE;
  467. goto end;
  468. }
  469. }
  470. mutex_lock(&sde_kms->secure_transition_lock);
  471. switch (smmu_state->state) {
  472. case DETACH_ALL_REQ:
  473. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  474. if (!ret)
  475. smmu_state->state = DETACHED;
  476. break;
  477. case ATTACH_ALL_REQ:
  478. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  479. VMID_CP_SEC_DISPLAY);
  480. if (!ret) {
  481. smmu_state->state = ATTACHED;
  482. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  483. }
  484. break;
  485. case DETACH_SEC_REQ:
  486. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  487. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  488. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  489. if (!ret)
  490. smmu_state->state = DETACHED_SEC;
  491. break;
  492. case ATTACH_SEC_REQ:
  493. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  494. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  495. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  496. if (!ret) {
  497. smmu_state->state = ATTACHED;
  498. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  499. }
  500. break;
  501. default:
  502. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  503. DRMID(crtc), smmu_state->state,
  504. smmu_state->transition_type);
  505. ret = -EINVAL;
  506. break;
  507. }
  508. mutex_unlock(&sde_kms->secure_transition_lock);
  509. /* disable sui misr if requested, after the transition */
  510. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  511. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  512. if (ret)
  513. goto end;
  514. }
  515. end:
  516. smmu_state->transition_error = false;
  517. if (ret) {
  518. smmu_state->transition_error = true;
  519. SDE_ERROR(
  520. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  521. DRMID(crtc), old_smmu_state, smmu_state->state,
  522. smmu_state->secure_level, ret);
  523. smmu_state->state = smmu_state->prev_state;
  524. smmu_state->secure_level = smmu_state->prev_secure_level;
  525. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  526. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  527. }
  528. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  529. DRMID(crtc), old_smmu_state, smmu_state->state,
  530. smmu_state->secure_level, ret);
  531. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  532. smmu_state->transition_type,
  533. smmu_state->transition_error,
  534. smmu_state->secure_level, smmu_state->prev_secure_level,
  535. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  536. smmu_state->sui_misr_state = NONE;
  537. smmu_state->transition_type = NONE;
  538. return ret;
  539. }
  540. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  541. struct drm_atomic_state *state)
  542. {
  543. struct drm_crtc *crtc;
  544. struct drm_crtc_state *old_crtc_state;
  545. struct drm_plane_state *old_plane_state, *new_plane_state;
  546. struct drm_plane *plane;
  547. struct drm_plane_state *plane_state;
  548. struct sde_kms *sde_kms = to_sde_kms(kms);
  549. struct drm_device *dev = sde_kms->dev;
  550. int i, ops = 0, ret = 0;
  551. bool old_valid_fb = false;
  552. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  553. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  554. if (!crtc->state || !crtc->state->active)
  555. continue;
  556. /*
  557. * It is safe to assume only one active crtc,
  558. * and compatible translation modes on the
  559. * planes staged on this crtc.
  560. * otherwise validation would have failed.
  561. * For this CRTC,
  562. */
  563. /*
  564. * 1. Check if old state on the CRTC has planes
  565. * staged with valid fbs
  566. */
  567. for_each_old_plane_in_state(state, plane, plane_state, i) {
  568. if (!plane_state->crtc)
  569. continue;
  570. if (plane_state->fb) {
  571. old_valid_fb = true;
  572. break;
  573. }
  574. }
  575. /*
  576. * 2.Get the operations needed to be performed before
  577. * secure transition can be initiated.
  578. */
  579. ops = sde_crtc_get_secure_transition_ops(crtc,
  580. old_crtc_state, old_valid_fb);
  581. if (ops < 0) {
  582. SDE_ERROR("invalid secure operations %x\n", ops);
  583. return ops;
  584. }
  585. if (!ops) {
  586. smmu_state->transition_error = false;
  587. goto no_ops;
  588. }
  589. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  590. crtc->base.id, ops, crtc->state);
  591. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  592. /* 3. Perform operations needed for secure transition */
  593. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  594. SDE_DEBUG("wait_for_transfer_done\n");
  595. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  596. }
  597. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  598. SDE_DEBUG("cleanup planes\n");
  599. drm_atomic_helper_cleanup_planes(dev, state);
  600. for_each_oldnew_plane_in_state(state, plane,
  601. old_plane_state, new_plane_state, i)
  602. sde_plane_destroy_fb(old_plane_state);
  603. }
  604. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  605. SDE_DEBUG("secure ctrl\n");
  606. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  607. }
  608. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  609. SDE_DEBUG("prepare planes %d",
  610. crtc->state->plane_mask);
  611. drm_atomic_crtc_for_each_plane(plane,
  612. crtc) {
  613. const struct drm_plane_helper_funcs *funcs;
  614. plane_state = plane->state;
  615. funcs = plane->helper_private;
  616. SDE_DEBUG("psde:%d FB[%u]\n",
  617. plane->base.id,
  618. plane->fb->base.id);
  619. if (!funcs)
  620. continue;
  621. if (funcs->prepare_fb(plane, plane_state)) {
  622. ret = funcs->prepare_fb(plane,
  623. plane_state);
  624. if (ret)
  625. return ret;
  626. }
  627. }
  628. }
  629. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  630. SDE_DEBUG("secure operations completed\n");
  631. }
  632. no_ops:
  633. return 0;
  634. }
  635. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  636. unsigned int splash_buffer_size,
  637. unsigned int ramdump_base,
  638. unsigned int ramdump_buffer_size)
  639. {
  640. unsigned long pfn_start, pfn_end, pfn_idx;
  641. int ret = 0;
  642. if (!mem_addr || !splash_buffer_size) {
  643. SDE_ERROR("invalid params\n");
  644. return -EINVAL;
  645. }
  646. /* leave ramdump memory only if base address matches */
  647. if (ramdump_base == mem_addr &&
  648. ramdump_buffer_size <= splash_buffer_size) {
  649. mem_addr += ramdump_buffer_size;
  650. splash_buffer_size -= ramdump_buffer_size;
  651. }
  652. pfn_start = mem_addr >> PAGE_SHIFT;
  653. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  654. ret = memblock_free(mem_addr, splash_buffer_size);
  655. if (ret) {
  656. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  657. return ret;
  658. }
  659. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  660. free_reserved_page(pfn_to_page(pfn_idx));
  661. return ret;
  662. }
  663. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  664. struct sde_splash_mem *splash)
  665. {
  666. struct msm_mmu *mmu = NULL;
  667. int ret = 0;
  668. if (!sde_kms->aspace[0]) {
  669. SDE_ERROR("aspace not found for sde kms node\n");
  670. return -EINVAL;
  671. }
  672. mmu = sde_kms->aspace[0]->mmu;
  673. if (!mmu) {
  674. SDE_ERROR("mmu not found for aspace\n");
  675. return -EINVAL;
  676. }
  677. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  678. SDE_ERROR("invalid input params for map\n");
  679. return -EINVAL;
  680. }
  681. if (!splash->ref_cnt) {
  682. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  683. splash->splash_buf_base,
  684. splash->splash_buf_size,
  685. IOMMU_READ | IOMMU_NOEXEC);
  686. if (ret)
  687. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  688. }
  689. splash->ref_cnt++;
  690. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  691. splash->splash_buf_base,
  692. splash->splash_buf_size,
  693. splash->ref_cnt);
  694. return ret;
  695. }
  696. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  697. {
  698. int i = 0;
  699. int ret = 0;
  700. if (!sde_kms)
  701. return -EINVAL;
  702. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  703. ret = _sde_kms_splash_mem_get(sde_kms,
  704. sde_kms->splash_data.splash_display[i].splash);
  705. if (ret)
  706. return ret;
  707. }
  708. return ret;
  709. }
  710. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  711. struct sde_splash_mem *splash)
  712. {
  713. struct msm_mmu *mmu = NULL;
  714. int rc = 0;
  715. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  716. SDE_ERROR("invalid params\n");
  717. return -EINVAL;
  718. }
  719. mmu = sde_kms->aspace[0]->mmu;
  720. if (!splash || !splash->ref_cnt ||
  721. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  722. return -EINVAL;
  723. splash->ref_cnt--;
  724. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  725. splash->splash_buf_base, splash->ref_cnt);
  726. if (!splash->ref_cnt) {
  727. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  728. splash->splash_buf_size);
  729. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  730. splash->splash_buf_size, splash->ramdump_base,
  731. splash->ramdump_size);
  732. splash->splash_buf_base = 0;
  733. splash->splash_buf_size = 0;
  734. }
  735. return rc;
  736. }
  737. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  738. {
  739. int i = 0;
  740. int ret = 0;
  741. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  742. return -EINVAL;
  743. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  744. ret = _sde_kms_splash_mem_put(sde_kms,
  745. sde_kms->splash_data.splash_display[i].splash);
  746. if (ret)
  747. return ret;
  748. }
  749. return ret;
  750. }
  751. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  752. struct drm_connector_state *conn_state)
  753. {
  754. int lp_mode, blank;
  755. if (crtc_state->active)
  756. lp_mode = sde_connector_get_property(conn_state,
  757. CONNECTOR_PROP_LP);
  758. else
  759. lp_mode = SDE_MODE_DPMS_OFF;
  760. switch (lp_mode) {
  761. case SDE_MODE_DPMS_ON:
  762. blank = DRM_PANEL_BLANK_UNBLANK;
  763. break;
  764. case SDE_MODE_DPMS_LP1:
  765. case SDE_MODE_DPMS_LP2:
  766. blank = DRM_PANEL_BLANK_LP;
  767. break;
  768. case SDE_MODE_DPMS_OFF:
  769. default:
  770. blank = DRM_PANEL_BLANK_POWERDOWN;
  771. break;
  772. }
  773. return blank;
  774. }
  775. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  776. unsigned long event)
  777. {
  778. struct drm_connector *connector;
  779. struct drm_connector_state *old_conn_state;
  780. struct drm_crtc_state *old_crtc_state;
  781. struct drm_crtc *crtc;
  782. int i, old_mode, new_mode, old_fps, new_fps;
  783. for_each_old_connector_in_state(old_state, connector,
  784. old_conn_state, i) {
  785. crtc = connector->state->crtc ? connector->state->crtc :
  786. old_conn_state->crtc;
  787. if (!crtc)
  788. continue;
  789. new_fps = crtc->state->mode.vrefresh;
  790. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  791. if (old_conn_state->crtc) {
  792. old_crtc_state = drm_atomic_get_existing_crtc_state(
  793. old_state, old_conn_state->crtc);
  794. old_fps = old_crtc_state->mode.vrefresh;
  795. old_mode = _sde_kms_get_blank(old_crtc_state,
  796. old_conn_state);
  797. } else {
  798. old_fps = 0;
  799. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  800. }
  801. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  802. struct drm_panel_notifier notifier_data;
  803. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  804. connector->panel, crtc->state->active,
  805. old_conn_state->crtc, event);
  806. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  807. old_mode, new_mode, old_fps, new_fps);
  808. /* If suspend resume and fps change are happening
  809. * at the same time, give preference to power mode
  810. * changes rather than fps change.
  811. */
  812. if ((old_mode == new_mode) && (old_fps != new_fps))
  813. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  814. notifier_data.data = &new_mode;
  815. notifier_data.refresh_rate = new_fps;
  816. notifier_data.id = connector->base.id;
  817. if (connector->panel)
  818. drm_panel_notifier_call_chain(connector->panel,
  819. event, &notifier_data);
  820. }
  821. }
  822. }
  823. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  824. struct drm_atomic_state *state)
  825. {
  826. struct drm_device *ddev;
  827. struct drm_crtc *crtc;
  828. struct drm_encoder *encoder;
  829. struct drm_connector *connector;
  830. struct sde_vm_ops *vm_ops;
  831. struct sde_crtc_state *cstate;
  832. enum sde_crtc_vm_req vm_req;
  833. int rc = 0;
  834. ddev = sde_kms->dev;
  835. vm_ops = sde_vm_get_ops(sde_kms);
  836. if (!vm_ops)
  837. return -EINVAL;
  838. crtc = state->crtcs[0].ptr;
  839. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  840. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  841. if (vm_req != VM_REQ_ACQUIRE)
  842. return 0;
  843. /* enable MDSS irq line */
  844. sde_irq_update(&sde_kms->base, true);
  845. /* clear the stale IRQ status bits */
  846. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  847. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  848. /* enable the display path IRQ's */
  849. drm_for_each_encoder_mask(encoder, crtc->dev,
  850. crtc->state->encoder_mask) {
  851. if (sde_encoder_in_clone_mode(encoder))
  852. continue;
  853. sde_encoder_irq_control(encoder, true);
  854. }
  855. /* Schedule ESD work */
  856. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  857. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  858. sde_connector_schedule_status_work(connector, true);
  859. /* enable vblank events */
  860. drm_crtc_vblank_on(crtc);
  861. /* handle non-SDE pre_acquire */
  862. if (vm_ops->vm_client_post_acquire)
  863. rc = vm_ops->vm_client_post_acquire(sde_kms);
  864. return rc;
  865. }
  866. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  867. struct drm_atomic_state *state)
  868. {
  869. struct drm_device *ddev;
  870. struct drm_plane *plane;
  871. struct sde_crtc_state *cstate;
  872. enum sde_crtc_vm_req vm_req;
  873. ddev = sde_kms->dev;
  874. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  875. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  876. if (vm_req != VM_REQ_ACQUIRE)
  877. return 0;
  878. /* Clear the stale IRQ status bits */
  879. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  880. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  881. /* Program the SID's for the trusted VM */
  882. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  883. sde_plane_set_sid(plane, 1);
  884. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  885. return 0;
  886. }
  887. static void sde_kms_prepare_commit(struct msm_kms *kms,
  888. struct drm_atomic_state *state)
  889. {
  890. struct sde_kms *sde_kms;
  891. struct msm_drm_private *priv;
  892. struct drm_device *dev;
  893. struct drm_encoder *encoder;
  894. struct drm_crtc *crtc;
  895. struct drm_crtc_state *crtc_state;
  896. struct sde_vm_ops *vm_ops;
  897. int i, rc;
  898. if (!kms)
  899. return;
  900. sde_kms = to_sde_kms(kms);
  901. dev = sde_kms->dev;
  902. if (!dev || !dev->dev_private)
  903. return;
  904. priv = dev->dev_private;
  905. SDE_ATRACE_BEGIN("prepare_commit");
  906. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  907. if (rc < 0) {
  908. SDE_ERROR("failed to enable power resources %d\n", rc);
  909. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  910. goto end;
  911. }
  912. if (sde_kms->first_kickoff) {
  913. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  914. sde_kms->first_kickoff = false;
  915. }
  916. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  917. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  918. head) {
  919. if (encoder->crtc != crtc)
  920. continue;
  921. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  922. SDE_ERROR("crtc:%d, initiating hw reset\n",
  923. DRMID(crtc));
  924. sde_encoder_needs_hw_reset(encoder);
  925. sde_crtc_set_needs_hw_reset(crtc);
  926. }
  927. }
  928. }
  929. /*
  930. * NOTE: for secure use cases we want to apply the new HW
  931. * configuration only after completing preparation for secure
  932. * transitions prepare below if any transtions is required.
  933. */
  934. sde_kms_prepare_secure_transition(kms, state);
  935. vm_ops = sde_vm_get_ops(sde_kms);
  936. if (!vm_ops)
  937. goto end_vm;
  938. if (vm_ops->vm_prepare_commit)
  939. vm_ops->vm_prepare_commit(sde_kms, state);
  940. end_vm:
  941. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  942. end:
  943. SDE_ATRACE_END("prepare_commit");
  944. }
  945. static void sde_kms_commit(struct msm_kms *kms,
  946. struct drm_atomic_state *old_state)
  947. {
  948. struct sde_kms *sde_kms;
  949. struct drm_crtc *crtc;
  950. struct drm_crtc_state *old_crtc_state;
  951. int i;
  952. if (!kms || !old_state)
  953. return;
  954. sde_kms = to_sde_kms(kms);
  955. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  956. SDE_ERROR("power resource is not enabled\n");
  957. return;
  958. }
  959. SDE_ATRACE_BEGIN("sde_kms_commit");
  960. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  961. if (crtc->state->active) {
  962. SDE_EVT32(DRMID(crtc), old_state);
  963. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  964. }
  965. }
  966. SDE_ATRACE_END("sde_kms_commit");
  967. }
  968. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  969. struct sde_splash_display *splash_display)
  970. {
  971. if (!sde_kms || !splash_display ||
  972. !sde_kms->splash_data.num_splash_displays)
  973. return;
  974. if (sde_kms->splash_data.num_splash_regions)
  975. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  976. sde_kms->splash_data.num_splash_displays--;
  977. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  978. sde_kms->splash_data.num_splash_displays);
  979. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  980. }
  981. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  982. struct drm_crtc *crtc)
  983. {
  984. struct msm_drm_private *priv;
  985. struct sde_splash_display *splash_display;
  986. int i;
  987. if (!sde_kms || !crtc)
  988. return;
  989. priv = sde_kms->dev->dev_private;
  990. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  991. return;
  992. SDE_EVT32(DRMID(crtc), crtc->state->active,
  993. sde_kms->splash_data.num_splash_displays);
  994. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  995. splash_display = &sde_kms->splash_data.splash_display[i];
  996. if (splash_display->encoder &&
  997. crtc == splash_display->encoder->crtc)
  998. break;
  999. }
  1000. if (i >= MAX_DSI_DISPLAYS)
  1001. return;
  1002. if (splash_display->cont_splash_enabled) {
  1003. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1004. splash_display, false);
  1005. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1006. }
  1007. /* remove the votes if all displays are done with splash */
  1008. if (!sde_kms->splash_data.num_splash_displays) {
  1009. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1010. sde_power_data_bus_set_quota(&priv->phandle, i,
  1011. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1012. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1013. pm_runtime_put_sync(sde_kms->dev->dev);
  1014. }
  1015. }
  1016. void _sde_kms_program_mode_info(struct sde_kms *sde_kms)
  1017. {
  1018. struct drm_encoder *encoder;
  1019. struct drm_crtc *crtc;
  1020. struct drm_connector *connector;
  1021. struct drm_connector_list_iter conn_iter;
  1022. struct dsi_display *dsi_display;
  1023. struct drm_display_mode *drm_mode;
  1024. int i;
  1025. struct drm_device *dev;
  1026. u32 mode_index = 0;
  1027. if (!sde_kms->dev || !sde_kms->hw_mdp)
  1028. return;
  1029. dev = sde_kms->dev;
  1030. sde_kms->hw_mdp->ops.clear_mode_index(sde_kms->hw_mdp);
  1031. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  1032. dsi_display = (struct dsi_display *)sde_kms->dsi_displays[i];
  1033. if (dsi_display->bridge->base.encoder) {
  1034. encoder = dsi_display->bridge->base.encoder;
  1035. crtc = encoder->crtc;
  1036. if (!crtc->state->active)
  1037. continue;
  1038. mutex_lock(&dev->mode_config.mutex);
  1039. drm_connector_list_iter_begin(dev, &conn_iter);
  1040. drm_for_each_connector_iter(connector, &conn_iter) {
  1041. if (connector->encoder_ids[0]
  1042. == encoder->base.id)
  1043. break;
  1044. }
  1045. drm_connector_list_iter_end(&conn_iter);
  1046. mutex_unlock(&dev->mode_config.mutex);
  1047. list_for_each_entry(drm_mode, &connector->modes, head) {
  1048. if (drm_mode_equal(
  1049. &crtc->state->mode, drm_mode))
  1050. break;
  1051. mode_index++;
  1052. }
  1053. sde_kms->hw_mdp->ops.set_mode_index(
  1054. sde_kms->hw_mdp, i, mode_index);
  1055. SDE_DEBUG("crtc:%d, display_idx:%d, mode_index:%d\n",
  1056. DRMID(crtc), i, mode_index);
  1057. }
  1058. }
  1059. }
  1060. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1061. struct drm_atomic_state *state)
  1062. {
  1063. struct sde_vm_ops *vm_ops;
  1064. struct drm_device *ddev;
  1065. struct drm_crtc *crtc;
  1066. struct drm_plane *plane;
  1067. struct drm_encoder *encoder;
  1068. struct sde_crtc_state *cstate;
  1069. struct drm_crtc_state *new_cstate;
  1070. enum sde_crtc_vm_req vm_req;
  1071. int rc = 0;
  1072. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1073. return -EINVAL;
  1074. vm_ops = sde_vm_get_ops(sde_kms);
  1075. ddev = sde_kms->dev;
  1076. crtc = state->crtcs[0].ptr;
  1077. new_cstate = state->crtcs[0].new_state;
  1078. cstate = to_sde_crtc_state(new_cstate);
  1079. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1080. if (vm_req != VM_REQ_RELEASE)
  1081. return rc;
  1082. if (!new_cstate->active && !new_cstate->active_changed)
  1083. return rc;
  1084. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1085. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1086. drm_for_each_encoder_mask(encoder, crtc->dev,
  1087. crtc->state->encoder_mask) {
  1088. if (sde_encoder_in_clone_mode(encoder))
  1089. continue;
  1090. sde_encoder_irq_control(encoder, false);
  1091. }
  1092. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1093. sde_plane_set_sid(plane, 0);
  1094. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1095. sde_vm_lock(sde_kms);
  1096. if (vm_ops->vm_release)
  1097. rc = vm_ops->vm_release(sde_kms);
  1098. sde_vm_unlock(sde_kms);
  1099. return rc;
  1100. }
  1101. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1102. struct drm_atomic_state *state)
  1103. {
  1104. struct drm_device *ddev;
  1105. struct drm_crtc *crtc;
  1106. struct drm_encoder *encoder;
  1107. struct drm_connector *connector;
  1108. int rc = 0;
  1109. ddev = sde_kms->dev;
  1110. crtc = state->crtcs[0].ptr;
  1111. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1112. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1113. /* disable ESD work */
  1114. list_for_each_entry(connector,
  1115. &ddev->mode_config.connector_list, head) {
  1116. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1117. sde_connector_schedule_status_work(connector, false);
  1118. }
  1119. /* disable SDE irq's */
  1120. drm_for_each_encoder_mask(encoder, crtc->dev,
  1121. crtc->state->encoder_mask) {
  1122. if (sde_encoder_in_clone_mode(encoder))
  1123. continue;
  1124. sde_encoder_irq_control(encoder, false);
  1125. }
  1126. /* disable IRQ line */
  1127. sde_irq_update(&sde_kms->base, false);
  1128. /* disable vblank events */
  1129. drm_crtc_vblank_off(crtc);
  1130. return rc;
  1131. }
  1132. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1133. struct drm_atomic_state *state)
  1134. {
  1135. struct sde_vm_ops *vm_ops;
  1136. struct sde_crtc_state *cstate;
  1137. struct drm_crtc *crtc;
  1138. enum sde_crtc_vm_req vm_req;
  1139. int rc = 0;
  1140. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1141. return -EINVAL;
  1142. vm_ops = sde_vm_get_ops(sde_kms);
  1143. crtc = state->crtcs[0].ptr;
  1144. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1145. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1146. if (vm_req != VM_REQ_RELEASE)
  1147. goto exit;
  1148. /* handle SDE pre-release */
  1149. rc = sde_kms_vm_pre_release(sde_kms, state);
  1150. if (rc) {
  1151. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1152. goto exit;
  1153. }
  1154. /* properly handoff color processing features */
  1155. sde_cp_crtc_vm_primary_handoff(crtc);
  1156. /* program the current drm mode info to scratch reg */
  1157. _sde_kms_program_mode_info(sde_kms);
  1158. /* handle non-SDE clients pre-release */
  1159. if (vm_ops->vm_client_pre_release) {
  1160. rc = vm_ops->vm_client_pre_release(sde_kms);
  1161. if (rc) {
  1162. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1163. rc);
  1164. goto exit;
  1165. }
  1166. }
  1167. sde_vm_lock(sde_kms);
  1168. /* release HW */
  1169. if (vm_ops->vm_release) {
  1170. rc = vm_ops->vm_release(sde_kms);
  1171. if (rc)
  1172. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1173. }
  1174. sde_vm_unlock(sde_kms);
  1175. exit:
  1176. return rc;
  1177. }
  1178. static void sde_kms_complete_commit(struct msm_kms *kms,
  1179. struct drm_atomic_state *old_state)
  1180. {
  1181. struct sde_kms *sde_kms;
  1182. struct msm_drm_private *priv;
  1183. struct drm_crtc *crtc;
  1184. struct drm_crtc_state *old_crtc_state;
  1185. struct drm_connector *connector;
  1186. struct drm_connector_state *old_conn_state;
  1187. struct msm_display_conn_params params;
  1188. struct sde_vm_ops *vm_ops;
  1189. int i, rc = 0;
  1190. if (!kms || !old_state)
  1191. return;
  1192. sde_kms = to_sde_kms(kms);
  1193. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1194. return;
  1195. priv = sde_kms->dev->dev_private;
  1196. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1197. SDE_ERROR("power resource is not enabled\n");
  1198. return;
  1199. }
  1200. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1201. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1202. sde_crtc_complete_commit(crtc, old_crtc_state);
  1203. /* complete secure transitions if any */
  1204. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1205. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1206. }
  1207. for_each_old_connector_in_state(old_state, connector,
  1208. old_conn_state, i) {
  1209. struct sde_connector *c_conn;
  1210. c_conn = to_sde_connector(connector);
  1211. if (!c_conn->ops.post_kickoff)
  1212. continue;
  1213. memset(&params, 0, sizeof(params));
  1214. sde_connector_complete_qsync_commit(connector, &params);
  1215. rc = c_conn->ops.post_kickoff(connector, &params);
  1216. if (rc) {
  1217. pr_err("Connector Post kickoff failed rc=%d\n",
  1218. rc);
  1219. }
  1220. }
  1221. vm_ops = sde_vm_get_ops(sde_kms);
  1222. if (vm_ops && vm_ops->vm_post_commit) {
  1223. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1224. if (rc)
  1225. SDE_ERROR("vm post commit failed, rc = %d\n",
  1226. rc);
  1227. }
  1228. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1229. pm_runtime_put_sync(sde_kms->dev->dev);
  1230. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1231. _sde_kms_release_splash_resource(sde_kms, crtc);
  1232. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1233. SDE_ATRACE_END("sde_kms_complete_commit");
  1234. }
  1235. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1236. struct drm_crtc *crtc)
  1237. {
  1238. struct drm_encoder *encoder;
  1239. struct drm_device *dev;
  1240. int ret;
  1241. bool cwb_disabling;
  1242. if (!kms || !crtc || !crtc->state) {
  1243. SDE_ERROR("invalid params\n");
  1244. return;
  1245. }
  1246. dev = crtc->dev;
  1247. if (!crtc->state->enable) {
  1248. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1249. return;
  1250. }
  1251. if (!crtc->state->active) {
  1252. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1253. return;
  1254. }
  1255. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1256. SDE_ERROR("power resource is not enabled\n");
  1257. return;
  1258. }
  1259. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1260. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1261. cwb_disabling = false;
  1262. if (encoder->crtc != crtc) {
  1263. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1264. crtc);
  1265. if (!cwb_disabling)
  1266. continue;
  1267. }
  1268. /*
  1269. * Wait for post-flush if necessary to delay before
  1270. * plane_cleanup. For example, wait for vsync in case of video
  1271. * mode panels. This may be a no-op for command mode panels.
  1272. */
  1273. SDE_EVT32_VERBOSE(DRMID(crtc));
  1274. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1275. if (ret && ret != -EWOULDBLOCK) {
  1276. SDE_ERROR("wait for commit done returned %d\n", ret);
  1277. sde_crtc_request_frame_reset(crtc);
  1278. break;
  1279. }
  1280. sde_crtc_complete_flip(crtc, NULL);
  1281. if (cwb_disabling)
  1282. sde_encoder_virt_reset(encoder);
  1283. }
  1284. sde_crtc_static_cache_read_kickoff(crtc);
  1285. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1286. }
  1287. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1288. struct drm_atomic_state *old_state)
  1289. {
  1290. struct drm_crtc *crtc;
  1291. struct drm_crtc_state *old_crtc_state;
  1292. int i, rc;
  1293. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1294. SDE_ERROR("invalid argument(s)\n");
  1295. return;
  1296. }
  1297. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1298. retry:
  1299. /* attempt to acquire ww mutex for connection */
  1300. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1301. old_state->acquire_ctx);
  1302. if (rc == -EDEADLK) {
  1303. drm_modeset_backoff(old_state->acquire_ctx);
  1304. goto retry;
  1305. }
  1306. /* old_state actually contains updated crtc pointers */
  1307. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1308. if (crtc->state->active || crtc->state->active_changed)
  1309. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1310. }
  1311. SDE_ATRACE_END("sde_kms_prepare_fence");
  1312. }
  1313. /**
  1314. * _sde_kms_get_displays - query for underlying display handles and cache them
  1315. * @sde_kms: Pointer to sde kms structure
  1316. * Returns: Zero on success
  1317. */
  1318. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1319. {
  1320. int rc = -ENOMEM;
  1321. if (!sde_kms) {
  1322. SDE_ERROR("invalid sde kms\n");
  1323. return -EINVAL;
  1324. }
  1325. /* dsi */
  1326. sde_kms->dsi_displays = NULL;
  1327. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1328. if (sde_kms->dsi_display_count) {
  1329. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1330. sizeof(void *),
  1331. GFP_KERNEL);
  1332. if (!sde_kms->dsi_displays) {
  1333. SDE_ERROR("failed to allocate dsi displays\n");
  1334. goto exit_deinit_dsi;
  1335. }
  1336. sde_kms->dsi_display_count =
  1337. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1338. sde_kms->dsi_display_count);
  1339. }
  1340. /* wb */
  1341. sde_kms->wb_displays = NULL;
  1342. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1343. if (sde_kms->wb_display_count) {
  1344. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1345. sizeof(void *),
  1346. GFP_KERNEL);
  1347. if (!sde_kms->wb_displays) {
  1348. SDE_ERROR("failed to allocate wb displays\n");
  1349. goto exit_deinit_wb;
  1350. }
  1351. sde_kms->wb_display_count =
  1352. wb_display_get_displays(sde_kms->wb_displays,
  1353. sde_kms->wb_display_count);
  1354. }
  1355. /* dp */
  1356. sde_kms->dp_displays = NULL;
  1357. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1358. if (sde_kms->dp_display_count) {
  1359. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1360. sizeof(void *), GFP_KERNEL);
  1361. if (!sde_kms->dp_displays) {
  1362. SDE_ERROR("failed to allocate dp displays\n");
  1363. goto exit_deinit_dp;
  1364. }
  1365. sde_kms->dp_display_count =
  1366. dp_display_get_displays(sde_kms->dp_displays,
  1367. sde_kms->dp_display_count);
  1368. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1369. }
  1370. return 0;
  1371. exit_deinit_dp:
  1372. kfree(sde_kms->dp_displays);
  1373. sde_kms->dp_stream_count = 0;
  1374. sde_kms->dp_display_count = 0;
  1375. sde_kms->dp_displays = NULL;
  1376. exit_deinit_wb:
  1377. kfree(sde_kms->wb_displays);
  1378. sde_kms->wb_display_count = 0;
  1379. sde_kms->wb_displays = NULL;
  1380. exit_deinit_dsi:
  1381. kfree(sde_kms->dsi_displays);
  1382. sde_kms->dsi_display_count = 0;
  1383. sde_kms->dsi_displays = NULL;
  1384. return rc;
  1385. }
  1386. /**
  1387. * _sde_kms_release_displays - release cache of underlying display handles
  1388. * @sde_kms: Pointer to sde kms structure
  1389. */
  1390. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1391. {
  1392. if (!sde_kms) {
  1393. SDE_ERROR("invalid sde kms\n");
  1394. return;
  1395. }
  1396. kfree(sde_kms->wb_displays);
  1397. sde_kms->wb_displays = NULL;
  1398. sde_kms->wb_display_count = 0;
  1399. kfree(sde_kms->dsi_displays);
  1400. sde_kms->dsi_displays = NULL;
  1401. sde_kms->dsi_display_count = 0;
  1402. }
  1403. /**
  1404. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1405. * for underlying displays
  1406. * @dev: Pointer to drm device structure
  1407. * @priv: Pointer to private drm device data
  1408. * @sde_kms: Pointer to sde kms structure
  1409. * Returns: Zero on success
  1410. */
  1411. static int _sde_kms_setup_displays(struct drm_device *dev,
  1412. struct msm_drm_private *priv,
  1413. struct sde_kms *sde_kms)
  1414. {
  1415. static const struct sde_connector_ops dsi_ops = {
  1416. .set_info_blob = dsi_conn_set_info_blob,
  1417. .detect = dsi_conn_detect,
  1418. .get_modes = dsi_connector_get_modes,
  1419. .pre_destroy = dsi_connector_put_modes,
  1420. .mode_valid = dsi_conn_mode_valid,
  1421. .get_info = dsi_display_get_info,
  1422. .set_backlight = dsi_display_set_backlight,
  1423. .soft_reset = dsi_display_soft_reset,
  1424. .pre_kickoff = dsi_conn_pre_kickoff,
  1425. .clk_ctrl = dsi_display_clk_ctrl,
  1426. .set_power = dsi_display_set_power,
  1427. .get_mode_info = dsi_conn_get_mode_info,
  1428. .get_dst_format = dsi_display_get_dst_format,
  1429. .post_kickoff = dsi_conn_post_kickoff,
  1430. .check_status = dsi_display_check_status,
  1431. .enable_event = dsi_conn_enable_event,
  1432. .cmd_transfer = dsi_display_cmd_transfer,
  1433. .cont_splash_config = dsi_display_cont_splash_config,
  1434. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1435. .get_panel_vfp = dsi_display_get_panel_vfp,
  1436. .get_default_lms = dsi_display_get_default_lms,
  1437. .cmd_receive = dsi_display_cmd_receive,
  1438. .install_properties = NULL,
  1439. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1440. .get_qsync_min_fps = dsi_display_get_qsync_min_fps,
  1441. };
  1442. static const struct sde_connector_ops wb_ops = {
  1443. .post_init = sde_wb_connector_post_init,
  1444. .set_info_blob = sde_wb_connector_set_info_blob,
  1445. .detect = sde_wb_connector_detect,
  1446. .get_modes = sde_wb_connector_get_modes,
  1447. .set_property = sde_wb_connector_set_property,
  1448. .get_info = sde_wb_get_info,
  1449. .soft_reset = NULL,
  1450. .get_mode_info = sde_wb_get_mode_info,
  1451. .get_dst_format = NULL,
  1452. .check_status = NULL,
  1453. .cmd_transfer = NULL,
  1454. .cont_splash_config = NULL,
  1455. .cont_splash_res_disable = NULL,
  1456. .get_panel_vfp = NULL,
  1457. .cmd_receive = NULL,
  1458. .install_properties = NULL,
  1459. .set_allowed_mode_switch = NULL,
  1460. };
  1461. static const struct sde_connector_ops dp_ops = {
  1462. .post_init = dp_connector_post_init,
  1463. .detect = dp_connector_detect,
  1464. .get_modes = dp_connector_get_modes,
  1465. .atomic_check = dp_connector_atomic_check,
  1466. .mode_valid = dp_connector_mode_valid,
  1467. .get_info = dp_connector_get_info,
  1468. .get_mode_info = dp_connector_get_mode_info,
  1469. .post_open = dp_connector_post_open,
  1470. .check_status = NULL,
  1471. .set_colorspace = dp_connector_set_colorspace,
  1472. .config_hdr = dp_connector_config_hdr,
  1473. .cmd_transfer = NULL,
  1474. .cont_splash_config = NULL,
  1475. .cont_splash_res_disable = NULL,
  1476. .get_panel_vfp = NULL,
  1477. .update_pps = dp_connector_update_pps,
  1478. .cmd_receive = NULL,
  1479. .install_properties = dp_connector_install_properties,
  1480. .set_allowed_mode_switch = NULL,
  1481. };
  1482. struct msm_display_info info;
  1483. struct drm_encoder *encoder;
  1484. void *display, *connector;
  1485. int i, max_encoders;
  1486. int rc = 0;
  1487. u32 dsc_count = 0, mixer_count = 0;
  1488. u32 max_dp_dsc_count, max_dp_mixer_count;
  1489. if (!dev || !priv || !sde_kms) {
  1490. SDE_ERROR("invalid argument(s)\n");
  1491. return -EINVAL;
  1492. }
  1493. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1494. sde_kms->dp_display_count +
  1495. sde_kms->dp_stream_count;
  1496. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1497. max_encoders = ARRAY_SIZE(priv->encoders);
  1498. SDE_ERROR("capping number of displays to %d", max_encoders);
  1499. }
  1500. /* wb */
  1501. for (i = 0; i < sde_kms->wb_display_count &&
  1502. priv->num_encoders < max_encoders; ++i) {
  1503. display = sde_kms->wb_displays[i];
  1504. encoder = NULL;
  1505. memset(&info, 0x0, sizeof(info));
  1506. rc = sde_wb_get_info(NULL, &info, display);
  1507. if (rc) {
  1508. SDE_ERROR("wb get_info %d failed\n", i);
  1509. continue;
  1510. }
  1511. encoder = sde_encoder_init(dev, &info);
  1512. if (IS_ERR_OR_NULL(encoder)) {
  1513. SDE_ERROR("encoder init failed for wb %d\n", i);
  1514. continue;
  1515. }
  1516. rc = sde_wb_drm_init(display, encoder);
  1517. if (rc) {
  1518. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1519. sde_encoder_destroy(encoder);
  1520. continue;
  1521. }
  1522. connector = sde_connector_init(dev,
  1523. encoder,
  1524. 0,
  1525. display,
  1526. &wb_ops,
  1527. DRM_CONNECTOR_POLL_HPD,
  1528. DRM_MODE_CONNECTOR_VIRTUAL);
  1529. if (connector) {
  1530. priv->encoders[priv->num_encoders++] = encoder;
  1531. priv->connectors[priv->num_connectors++] = connector;
  1532. } else {
  1533. SDE_ERROR("wb %d connector init failed\n", i);
  1534. sde_wb_drm_deinit(display);
  1535. sde_encoder_destroy(encoder);
  1536. }
  1537. }
  1538. /* dsi */
  1539. for (i = 0; i < sde_kms->dsi_display_count &&
  1540. priv->num_encoders < max_encoders; ++i) {
  1541. display = sde_kms->dsi_displays[i];
  1542. encoder = NULL;
  1543. memset(&info, 0x0, sizeof(info));
  1544. rc = dsi_display_get_info(NULL, &info, display);
  1545. if (rc) {
  1546. SDE_ERROR("dsi get_info %d failed\n", i);
  1547. continue;
  1548. }
  1549. encoder = sde_encoder_init(dev, &info);
  1550. if (IS_ERR_OR_NULL(encoder)) {
  1551. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1552. continue;
  1553. }
  1554. rc = dsi_display_drm_bridge_init(display, encoder);
  1555. if (rc) {
  1556. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1557. sde_encoder_destroy(encoder);
  1558. continue;
  1559. }
  1560. connector = sde_connector_init(dev,
  1561. encoder,
  1562. dsi_display_get_drm_panel(display),
  1563. display,
  1564. &dsi_ops,
  1565. DRM_CONNECTOR_POLL_HPD,
  1566. DRM_MODE_CONNECTOR_DSI);
  1567. if (connector) {
  1568. priv->encoders[priv->num_encoders++] = encoder;
  1569. priv->connectors[priv->num_connectors++] = connector;
  1570. } else {
  1571. SDE_ERROR("dsi %d connector init failed\n", i);
  1572. dsi_display_drm_bridge_deinit(display);
  1573. sde_encoder_destroy(encoder);
  1574. continue;
  1575. }
  1576. rc = dsi_display_drm_ext_bridge_init(display,
  1577. encoder, connector);
  1578. if (rc) {
  1579. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1580. dsi_display_drm_bridge_deinit(display);
  1581. sde_connector_destroy(connector);
  1582. sde_encoder_destroy(encoder);
  1583. }
  1584. dsc_count += info.dsc_count;
  1585. mixer_count += info.lm_count;
  1586. }
  1587. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1588. sde_kms->catalog->mixer_count - mixer_count : 0;
  1589. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1590. sde_kms->catalog->dsc_count - dsc_count : 0;
  1591. /* dp */
  1592. for (i = 0; i < sde_kms->dp_display_count &&
  1593. priv->num_encoders < max_encoders; ++i) {
  1594. int idx;
  1595. display = sde_kms->dp_displays[i];
  1596. encoder = NULL;
  1597. memset(&info, 0x0, sizeof(info));
  1598. rc = dp_connector_get_info(NULL, &info, display);
  1599. if (rc) {
  1600. SDE_ERROR("dp get_info %d failed\n", i);
  1601. continue;
  1602. }
  1603. encoder = sde_encoder_init(dev, &info);
  1604. if (IS_ERR_OR_NULL(encoder)) {
  1605. SDE_ERROR("dp encoder init failed %d\n", i);
  1606. continue;
  1607. }
  1608. rc = dp_drm_bridge_init(display, encoder,
  1609. max_dp_mixer_count, max_dp_dsc_count);
  1610. if (rc) {
  1611. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1612. sde_encoder_destroy(encoder);
  1613. continue;
  1614. }
  1615. connector = sde_connector_init(dev,
  1616. encoder,
  1617. NULL,
  1618. display,
  1619. &dp_ops,
  1620. DRM_CONNECTOR_POLL_HPD,
  1621. DRM_MODE_CONNECTOR_DisplayPort);
  1622. if (connector) {
  1623. priv->encoders[priv->num_encoders++] = encoder;
  1624. priv->connectors[priv->num_connectors++] = connector;
  1625. } else {
  1626. SDE_ERROR("dp %d connector init failed\n", i);
  1627. dp_drm_bridge_deinit(display);
  1628. sde_encoder_destroy(encoder);
  1629. }
  1630. /* update display cap to MST_MODE for DP MST encoders */
  1631. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1632. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1633. priv->num_encoders < max_encoders; idx++) {
  1634. info.h_tile_instance[0] = idx;
  1635. encoder = sde_encoder_init(dev, &info);
  1636. if (IS_ERR_OR_NULL(encoder)) {
  1637. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1638. continue;
  1639. }
  1640. rc = dp_mst_drm_bridge_init(display, encoder);
  1641. if (rc) {
  1642. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1643. i, rc);
  1644. sde_encoder_destroy(encoder);
  1645. continue;
  1646. }
  1647. priv->encoders[priv->num_encoders++] = encoder;
  1648. }
  1649. }
  1650. return 0;
  1651. }
  1652. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1653. {
  1654. struct msm_drm_private *priv;
  1655. int i;
  1656. if (!sde_kms) {
  1657. SDE_ERROR("invalid sde_kms\n");
  1658. return;
  1659. } else if (!sde_kms->dev) {
  1660. SDE_ERROR("invalid dev\n");
  1661. return;
  1662. } else if (!sde_kms->dev->dev_private) {
  1663. SDE_ERROR("invalid dev_private\n");
  1664. return;
  1665. }
  1666. priv = sde_kms->dev->dev_private;
  1667. for (i = 0; i < priv->num_crtcs; i++)
  1668. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1669. priv->num_crtcs = 0;
  1670. for (i = 0; i < priv->num_planes; i++)
  1671. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1672. priv->num_planes = 0;
  1673. for (i = 0; i < priv->num_connectors; i++)
  1674. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1675. priv->num_connectors = 0;
  1676. for (i = 0; i < priv->num_encoders; i++)
  1677. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1678. priv->num_encoders = 0;
  1679. _sde_kms_release_displays(sde_kms);
  1680. }
  1681. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1682. {
  1683. struct drm_device *dev;
  1684. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1685. struct drm_crtc *crtc;
  1686. struct msm_drm_private *priv;
  1687. struct sde_mdss_cfg *catalog;
  1688. int primary_planes_idx = 0, i, ret;
  1689. int max_crtc_count;
  1690. u32 sspp_id[MAX_PLANES];
  1691. u32 master_plane_id[MAX_PLANES];
  1692. u32 num_virt_planes = 0;
  1693. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1694. SDE_ERROR("invalid sde_kms\n");
  1695. return -EINVAL;
  1696. }
  1697. dev = sde_kms->dev;
  1698. priv = dev->dev_private;
  1699. catalog = sde_kms->catalog;
  1700. ret = sde_core_irq_domain_add(sde_kms);
  1701. if (ret)
  1702. goto fail_irq;
  1703. /*
  1704. * Query for underlying display drivers, and create connectors,
  1705. * bridges and encoders for them.
  1706. */
  1707. if (!_sde_kms_get_displays(sde_kms))
  1708. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1709. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1710. /* Create the planes */
  1711. for (i = 0; i < catalog->sspp_count; i++) {
  1712. bool primary = true;
  1713. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1714. || primary_planes_idx >= max_crtc_count)
  1715. primary = false;
  1716. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1717. (1UL << max_crtc_count) - 1, 0);
  1718. if (IS_ERR(plane)) {
  1719. SDE_ERROR("sde_plane_init failed\n");
  1720. ret = PTR_ERR(plane);
  1721. goto fail;
  1722. }
  1723. priv->planes[priv->num_planes++] = plane;
  1724. if (primary)
  1725. primary_planes[primary_planes_idx++] = plane;
  1726. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1727. sde_is_custom_client()) {
  1728. int priority =
  1729. catalog->sspp[i].sblk->smart_dma_priority;
  1730. sspp_id[priority - 1] = catalog->sspp[i].id;
  1731. master_plane_id[priority - 1] = plane->base.id;
  1732. num_virt_planes++;
  1733. }
  1734. }
  1735. /* Initialize smart DMA virtual planes */
  1736. for (i = 0; i < num_virt_planes; i++) {
  1737. plane = sde_plane_init(dev, sspp_id[i], false,
  1738. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1739. if (IS_ERR(plane)) {
  1740. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1741. ret = PTR_ERR(plane);
  1742. goto fail;
  1743. }
  1744. priv->planes[priv->num_planes++] = plane;
  1745. }
  1746. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1747. /* Create one CRTC per encoder */
  1748. for (i = 0; i < max_crtc_count; i++) {
  1749. crtc = sde_crtc_init(dev, primary_planes[i]);
  1750. if (IS_ERR(crtc)) {
  1751. ret = PTR_ERR(crtc);
  1752. goto fail;
  1753. }
  1754. priv->crtcs[priv->num_crtcs++] = crtc;
  1755. }
  1756. if (sde_is_custom_client()) {
  1757. /* All CRTCs are compatible with all planes */
  1758. for (i = 0; i < priv->num_planes; i++)
  1759. priv->planes[i]->possible_crtcs =
  1760. (1 << priv->num_crtcs) - 1;
  1761. }
  1762. /* All CRTCs are compatible with all encoders */
  1763. for (i = 0; i < priv->num_encoders; i++)
  1764. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1765. return 0;
  1766. fail:
  1767. _sde_kms_drm_obj_destroy(sde_kms);
  1768. fail_irq:
  1769. sde_core_irq_domain_fini(sde_kms);
  1770. return ret;
  1771. }
  1772. /**
  1773. * sde_kms_timeline_status - provides current timeline status
  1774. * This API should be called without mode config lock.
  1775. * @dev: Pointer to drm device
  1776. */
  1777. void sde_kms_timeline_status(struct drm_device *dev)
  1778. {
  1779. struct drm_crtc *crtc;
  1780. struct drm_connector *conn;
  1781. struct drm_connector_list_iter conn_iter;
  1782. if (!dev) {
  1783. SDE_ERROR("invalid drm device node\n");
  1784. return;
  1785. }
  1786. drm_for_each_crtc(crtc, dev)
  1787. sde_crtc_timeline_status(crtc);
  1788. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1789. /*
  1790. *Probably locked from last close dumping status anyway
  1791. */
  1792. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1793. drm_connector_list_iter_begin(dev, &conn_iter);
  1794. drm_for_each_connector_iter(conn, &conn_iter)
  1795. sde_conn_timeline_status(conn);
  1796. drm_connector_list_iter_end(&conn_iter);
  1797. return;
  1798. }
  1799. mutex_lock(&dev->mode_config.mutex);
  1800. drm_connector_list_iter_begin(dev, &conn_iter);
  1801. drm_for_each_connector_iter(conn, &conn_iter)
  1802. sde_conn_timeline_status(conn);
  1803. drm_connector_list_iter_end(&conn_iter);
  1804. mutex_unlock(&dev->mode_config.mutex);
  1805. }
  1806. static int sde_kms_postinit(struct msm_kms *kms)
  1807. {
  1808. struct sde_kms *sde_kms = to_sde_kms(kms);
  1809. struct drm_device *dev;
  1810. struct drm_crtc *crtc;
  1811. int rc;
  1812. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1813. SDE_ERROR("invalid sde_kms\n");
  1814. return -EINVAL;
  1815. }
  1816. dev = sde_kms->dev;
  1817. rc = _sde_debugfs_init(sde_kms);
  1818. if (rc)
  1819. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1820. drm_for_each_crtc(crtc, dev)
  1821. sde_crtc_post_init(dev, crtc);
  1822. return rc;
  1823. }
  1824. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1825. struct drm_encoder *encoder)
  1826. {
  1827. return rate;
  1828. }
  1829. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1830. struct platform_device *pdev)
  1831. {
  1832. struct drm_device *dev;
  1833. struct msm_drm_private *priv;
  1834. struct sde_vm_ops *vm_ops;
  1835. int i;
  1836. if (!sde_kms || !pdev)
  1837. return;
  1838. dev = sde_kms->dev;
  1839. if (!dev)
  1840. return;
  1841. priv = dev->dev_private;
  1842. if (!priv)
  1843. return;
  1844. if (sde_kms->genpd_init) {
  1845. sde_kms->genpd_init = false;
  1846. pm_genpd_remove(&sde_kms->genpd);
  1847. of_genpd_del_provider(pdev->dev.of_node);
  1848. }
  1849. vm_ops = sde_vm_get_ops(sde_kms);
  1850. if (vm_ops && vm_ops->vm_deinit)
  1851. vm_ops->vm_deinit(sde_kms, vm_ops);
  1852. if (sde_kms->hw_intr)
  1853. sde_hw_intr_destroy(sde_kms->hw_intr);
  1854. sde_kms->hw_intr = NULL;
  1855. if (sde_kms->power_event)
  1856. sde_power_handle_unregister_event(
  1857. &priv->phandle, sde_kms->power_event);
  1858. _sde_kms_release_displays(sde_kms);
  1859. _sde_kms_unmap_all_splash_regions(sde_kms);
  1860. if (sde_kms->catalog) {
  1861. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1862. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1863. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1864. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1865. }
  1866. }
  1867. if (sde_kms->rm_init)
  1868. sde_rm_destroy(&sde_kms->rm);
  1869. sde_kms->rm_init = false;
  1870. if (sde_kms->catalog)
  1871. sde_hw_catalog_deinit(sde_kms->catalog);
  1872. sde_kms->catalog = NULL;
  1873. if (sde_kms->sid)
  1874. msm_iounmap(pdev, sde_kms->sid);
  1875. sde_kms->sid = NULL;
  1876. if (sde_kms->reg_dma)
  1877. msm_iounmap(pdev, sde_kms->reg_dma);
  1878. sde_kms->reg_dma = NULL;
  1879. if (sde_kms->vbif[VBIF_NRT])
  1880. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1881. sde_kms->vbif[VBIF_NRT] = NULL;
  1882. if (sde_kms->vbif[VBIF_RT])
  1883. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1884. sde_kms->vbif[VBIF_RT] = NULL;
  1885. if (sde_kms->mmio)
  1886. msm_iounmap(pdev, sde_kms->mmio);
  1887. sde_kms->mmio = NULL;
  1888. sde_reg_dma_deinit();
  1889. _sde_kms_mmu_destroy(sde_kms);
  1890. }
  1891. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1892. {
  1893. int i;
  1894. if (!sde_kms)
  1895. return -EINVAL;
  1896. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1897. struct msm_mmu *mmu;
  1898. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1899. if (!aspace)
  1900. continue;
  1901. mmu = sde_kms->aspace[i]->mmu;
  1902. if (secure_only &&
  1903. !aspace->mmu->funcs->is_domain_secure(mmu))
  1904. continue;
  1905. /* cleanup aspace before detaching */
  1906. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1907. SDE_DEBUG("Detaching domain:%d\n", i);
  1908. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1909. ARRAY_SIZE(iommu_ports));
  1910. aspace->domain_attached = false;
  1911. }
  1912. return 0;
  1913. }
  1914. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1915. {
  1916. int i;
  1917. if (!sde_kms)
  1918. return -EINVAL;
  1919. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1920. struct msm_mmu *mmu;
  1921. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1922. if (!aspace)
  1923. continue;
  1924. mmu = sde_kms->aspace[i]->mmu;
  1925. if (secure_only &&
  1926. !aspace->mmu->funcs->is_domain_secure(mmu))
  1927. continue;
  1928. SDE_DEBUG("Attaching domain:%d\n", i);
  1929. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1930. ARRAY_SIZE(iommu_ports));
  1931. aspace->domain_attached = true;
  1932. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1933. }
  1934. return 0;
  1935. }
  1936. static void sde_kms_destroy(struct msm_kms *kms)
  1937. {
  1938. struct sde_kms *sde_kms;
  1939. struct drm_device *dev;
  1940. if (!kms) {
  1941. SDE_ERROR("invalid kms\n");
  1942. return;
  1943. }
  1944. sde_kms = to_sde_kms(kms);
  1945. dev = sde_kms->dev;
  1946. if (!dev || !dev->dev) {
  1947. SDE_ERROR("invalid device\n");
  1948. return;
  1949. }
  1950. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1951. kfree(sde_kms);
  1952. }
  1953. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1954. struct drm_atomic_state *state)
  1955. {
  1956. struct drm_device *dev = sde_kms->dev;
  1957. struct drm_plane *plane;
  1958. struct drm_plane_state *plane_state;
  1959. struct drm_crtc *crtc;
  1960. struct drm_crtc_state *crtc_state;
  1961. struct drm_connector *conn;
  1962. struct drm_connector_state *conn_state;
  1963. struct drm_connector_list_iter conn_iter;
  1964. int ret = 0;
  1965. drm_for_each_plane(plane, dev) {
  1966. plane_state = drm_atomic_get_plane_state(state, plane);
  1967. if (IS_ERR(plane_state)) {
  1968. ret = PTR_ERR(plane_state);
  1969. SDE_ERROR("error %d getting plane %d state\n",
  1970. ret, DRMID(plane));
  1971. return ret;
  1972. }
  1973. ret = sde_plane_helper_reset_custom_properties(plane,
  1974. plane_state);
  1975. if (ret) {
  1976. SDE_ERROR("error %d resetting plane props %d\n",
  1977. ret, DRMID(plane));
  1978. return ret;
  1979. }
  1980. }
  1981. drm_for_each_crtc(crtc, dev) {
  1982. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1983. if (IS_ERR(crtc_state)) {
  1984. ret = PTR_ERR(crtc_state);
  1985. SDE_ERROR("error %d getting crtc %d state\n",
  1986. ret, DRMID(crtc));
  1987. return ret;
  1988. }
  1989. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1990. if (ret) {
  1991. SDE_ERROR("error %d resetting crtc props %d\n",
  1992. ret, DRMID(crtc));
  1993. return ret;
  1994. }
  1995. }
  1996. drm_connector_list_iter_begin(dev, &conn_iter);
  1997. drm_for_each_connector_iter(conn, &conn_iter) {
  1998. conn_state = drm_atomic_get_connector_state(state, conn);
  1999. if (IS_ERR(conn_state)) {
  2000. ret = PTR_ERR(conn_state);
  2001. SDE_ERROR("error %d getting connector %d state\n",
  2002. ret, DRMID(conn));
  2003. return ret;
  2004. }
  2005. ret = sde_connector_helper_reset_custom_properties(conn,
  2006. conn_state);
  2007. if (ret) {
  2008. SDE_ERROR("error %d resetting connector props %d\n",
  2009. ret, DRMID(conn));
  2010. return ret;
  2011. }
  2012. }
  2013. drm_connector_list_iter_end(&conn_iter);
  2014. return ret;
  2015. }
  2016. static void sde_kms_lastclose(struct msm_kms *kms)
  2017. {
  2018. struct sde_kms *sde_kms;
  2019. struct drm_device *dev;
  2020. struct drm_atomic_state *state;
  2021. struct drm_modeset_acquire_ctx ctx;
  2022. int ret;
  2023. if (!kms) {
  2024. SDE_ERROR("invalid argument\n");
  2025. return;
  2026. }
  2027. sde_kms = to_sde_kms(kms);
  2028. dev = sde_kms->dev;
  2029. drm_modeset_acquire_init(&ctx, 0);
  2030. state = drm_atomic_state_alloc(dev);
  2031. if (!state) {
  2032. ret = -ENOMEM;
  2033. goto out_ctx;
  2034. }
  2035. state->acquire_ctx = &ctx;
  2036. retry:
  2037. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2038. if (ret)
  2039. goto out_state;
  2040. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2041. if (ret)
  2042. goto out_state;
  2043. ret = drm_atomic_commit(state);
  2044. out_state:
  2045. if (ret == -EDEADLK)
  2046. goto backoff;
  2047. drm_atomic_state_put(state);
  2048. out_ctx:
  2049. drm_modeset_drop_locks(&ctx);
  2050. drm_modeset_acquire_fini(&ctx);
  2051. if (ret)
  2052. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2053. return;
  2054. backoff:
  2055. drm_atomic_state_clear(state);
  2056. drm_modeset_backoff(&ctx);
  2057. goto retry;
  2058. }
  2059. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2060. struct drm_atomic_state *state)
  2061. {
  2062. struct sde_kms *sde_kms;
  2063. struct drm_device *dev;
  2064. struct drm_crtc *crtc;
  2065. struct drm_encoder *encoder;
  2066. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2067. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2068. uint32_t crtc_encoder_cnt = 0;
  2069. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2070. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2071. struct sde_vm_ops *vm_ops;
  2072. bool vm_req_active = false;
  2073. enum sde_crtc_idle_pc_state idle_pc_state;
  2074. struct sde_mdss_cfg *catalog;
  2075. int rc = 0;
  2076. struct sde_connector *sde_conn;
  2077. struct dsi_display *dsi_display;
  2078. struct drm_connector *connector;
  2079. struct drm_connector_state *new_connstate;
  2080. if (!kms || !state)
  2081. return -EINVAL;
  2082. sde_kms = to_sde_kms(kms);
  2083. dev = sde_kms->dev;
  2084. catalog = sde_kms->catalog;
  2085. vm_ops = sde_vm_get_ops(sde_kms);
  2086. if (!vm_ops)
  2087. return 0;
  2088. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw ||
  2089. !vm_ops->vm_acquire)
  2090. return -EINVAL;
  2091. sde_vm_lock(sde_kms);
  2092. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2093. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2094. if (!new_cstate->active && !old_cstate->active)
  2095. continue;
  2096. new_state = to_sde_crtc_state(new_cstate);
  2097. new_vm_req = sde_crtc_get_property(new_state,
  2098. CRTC_PROP_VM_REQ_STATE);
  2099. old_state = to_sde_crtc_state(old_cstate);
  2100. old_vm_req = sde_crtc_get_property(old_state,
  2101. CRTC_PROP_VM_REQ_STATE);
  2102. /*
  2103. * No active request if the transition is from
  2104. * VM_REQ_NONE to VM_REQ_NONE
  2105. */
  2106. if (old_vm_req || new_vm_req) {
  2107. rc = vm_ops->vm_request_valid(sde_kms,
  2108. old_vm_req, new_vm_req);
  2109. if (rc) {
  2110. SDE_ERROR(
  2111. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2112. old_vm_req, new_vm_req,
  2113. vm_ops->vm_owns_hw(sde_kms), rc);
  2114. goto end;
  2115. } else if (old_vm_req == VM_REQ_ACQUIRE &&
  2116. new_vm_req == VM_REQ_NONE) {
  2117. SDE_DEBUG(
  2118. "VM transition valid; ignore further checks\n");
  2119. } else {
  2120. vm_req_active = true;
  2121. }
  2122. }
  2123. idle_pc_state = sde_crtc_get_property(new_state,
  2124. CRTC_PROP_IDLE_PC_STATE);
  2125. active_crtc = crtc;
  2126. active_cstate = new_cstate;
  2127. commit_crtc_cnt++;
  2128. }
  2129. /* return early if no active vm request */
  2130. if (!vm_req_active)
  2131. goto end;
  2132. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2133. if (!crtc->state->active)
  2134. continue;
  2135. global_crtc_cnt++;
  2136. global_active_crtc = crtc;
  2137. }
  2138. if (active_crtc) {
  2139. drm_for_each_encoder_mask(encoder, active_crtc->dev,
  2140. active_cstate->encoder_mask)
  2141. crtc_encoder_cnt++;
  2142. }
  2143. SDE_EVT32(old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2144. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d\n", old_vm_req,
  2145. new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2146. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2147. int conn_mask = active_cstate->connector_mask;
  2148. if (drm_connector_mask(connector) & conn_mask) {
  2149. sde_conn = to_sde_connector(connector);
  2150. dsi_display = (struct dsi_display *) sde_conn->display;
  2151. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i,
  2152. dsi_display->type,
  2153. dsi_display->trusted_vm_env);
  2154. SDE_DEBUG(
  2155. "VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d,",
  2156. dsi_display->name, DRMID(connector),
  2157. DRMID(active_crtc), dsi_display->type,
  2158. dsi_display->trusted_vm_env);
  2159. break;
  2160. }
  2161. }
  2162. /* Check for single crtc commits only on valid VM requests */
  2163. if (active_crtc && global_active_crtc &&
  2164. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2165. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2166. active_crtc != global_active_crtc)) {
  2167. SDE_ERROR(
  2168. "VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2169. catalog->max_trusted_vm_displays,
  2170. commit_crtc_cnt, global_crtc_cnt, DRMID(active_crtc),
  2171. DRMID(global_active_crtc));
  2172. rc = -E2BIG;
  2173. goto end;
  2174. } else if ((new_vm_req == VM_REQ_RELEASE) &&
  2175. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2176. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2177. /*
  2178. * disable idle-pc before releasing the HW
  2179. * allow only specified number of encoders on a given crtc
  2180. */
  2181. SDE_ERROR(
  2182. "VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2183. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC,
  2184. crtc_encoder_cnt);
  2185. rc = -EINVAL;
  2186. goto end;
  2187. }
  2188. if ((new_vm_req == VM_REQ_ACQUIRE) && !vm_ops->vm_owns_hw(sde_kms)) {
  2189. rc = vm_ops->vm_acquire(sde_kms);
  2190. if (rc) {
  2191. SDE_ERROR(
  2192. "VM acquire failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2193. old_vm_req, new_vm_req,
  2194. vm_ops->vm_owns_hw(sde_kms), rc);
  2195. goto end;
  2196. }
  2197. }
  2198. end:
  2199. sde_vm_unlock(sde_kms);
  2200. return rc;
  2201. }
  2202. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2203. struct drm_atomic_state *state)
  2204. {
  2205. struct sde_kms *sde_kms;
  2206. struct drm_device *dev;
  2207. struct drm_crtc *crtc;
  2208. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2209. struct drm_crtc_state *crtc_state;
  2210. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2211. bool sec_session = false, global_sec_session = false;
  2212. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2213. int i;
  2214. if (!kms || !state) {
  2215. return -EINVAL;
  2216. SDE_ERROR("invalid arguments\n");
  2217. }
  2218. sde_kms = to_sde_kms(kms);
  2219. dev = sde_kms->dev;
  2220. /* iterate state object for active secure/non-secure crtc */
  2221. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2222. if (!crtc_state->active)
  2223. continue;
  2224. active_crtc_cnt++;
  2225. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2226. &fb_sec, &fb_sec_dir);
  2227. if (fb_sec_dir)
  2228. sec_session = true;
  2229. cur_crtc = crtc;
  2230. }
  2231. /* iterate global list for active and secure/non-secure crtc */
  2232. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2233. if (!crtc->state->active)
  2234. continue;
  2235. global_active_crtc_cnt++;
  2236. /* update only when crtc is not the same as current crtc */
  2237. if (crtc != cur_crtc) {
  2238. fb_ns = fb_sec = fb_sec_dir = 0;
  2239. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2240. &fb_sec, &fb_sec_dir);
  2241. if (fb_sec_dir)
  2242. global_sec_session = true;
  2243. global_crtc = crtc;
  2244. }
  2245. }
  2246. if (!global_sec_session && !sec_session)
  2247. return 0;
  2248. /*
  2249. * - fail crtc commit, if secure-camera/secure-ui session is
  2250. * in-progress in any other display
  2251. * - fail secure-camera/secure-ui crtc commit, if any other display
  2252. * session is in-progress
  2253. */
  2254. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2255. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2256. SDE_ERROR(
  2257. "crtc%d secure check failed global_active:%d active:%d\n",
  2258. cur_crtc ? cur_crtc->base.id : -1,
  2259. global_active_crtc_cnt, active_crtc_cnt);
  2260. return -EPERM;
  2261. /*
  2262. * As only one crtc is allowed during secure session, the crtc
  2263. * in this commit should match with the global crtc
  2264. */
  2265. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2266. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2267. cur_crtc->base.id, sec_session,
  2268. global_crtc->base.id, global_sec_session);
  2269. return -EPERM;
  2270. }
  2271. return 0;
  2272. }
  2273. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2274. struct drm_atomic_state *state)
  2275. {
  2276. struct drm_crtc *crtc;
  2277. struct drm_crtc_state *new_cstate, *old_cstate;
  2278. struct sde_vm_ops *vm_ops;
  2279. enum sde_crtc_vm_req vm_req;
  2280. struct sde_kms *sde_kms = to_sde_kms(kms);
  2281. int i;
  2282. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2283. struct sde_crtc_state *new_state;
  2284. if (!new_cstate->active && !old_cstate->active)
  2285. continue;
  2286. new_state = to_sde_crtc_state(new_cstate);
  2287. vm_req = sde_crtc_get_property(new_state,
  2288. CRTC_PROP_VM_REQ_STATE);
  2289. if (vm_req != VM_REQ_ACQUIRE)
  2290. return;
  2291. }
  2292. vm_ops = sde_vm_get_ops(sde_kms);
  2293. if (!vm_ops)
  2294. return;
  2295. sde_vm_lock(sde_kms);
  2296. if (vm_ops->vm_acquire_fail_handler)
  2297. vm_ops->vm_acquire_fail_handler(sde_kms);
  2298. sde_vm_unlock(sde_kms);
  2299. }
  2300. static int sde_kms_atomic_check(struct msm_kms *kms,
  2301. struct drm_atomic_state *state)
  2302. {
  2303. struct sde_kms *sde_kms;
  2304. struct drm_device *dev;
  2305. int ret;
  2306. if (!kms || !state)
  2307. return -EINVAL;
  2308. sde_kms = to_sde_kms(kms);
  2309. dev = sde_kms->dev;
  2310. SDE_ATRACE_BEGIN("atomic_check");
  2311. if (sde_kms_is_suspend_blocked(dev)) {
  2312. SDE_DEBUG("suspended, skip atomic_check\n");
  2313. ret = -EBUSY;
  2314. goto end;
  2315. }
  2316. ret = sde_kms_check_vm_request(kms, state);
  2317. if (ret) {
  2318. SDE_ERROR("vm switch request checks failed\n");
  2319. goto end;
  2320. }
  2321. ret = drm_atomic_helper_check(dev, state);
  2322. if (ret)
  2323. goto vm_clean_up;
  2324. /*
  2325. * Check if any secure transition(moving CRTC between secure and
  2326. * non-secure state and vice-versa) is allowed or not. when moving
  2327. * to secure state, planes with fb_mode set to dir_translated only can
  2328. * be staged on the CRTC, and only one CRTC can be active during
  2329. * Secure state
  2330. */
  2331. ret = sde_kms_check_secure_transition(kms, state);
  2332. if (ret)
  2333. goto vm_clean_up;
  2334. goto end;
  2335. vm_clean_up:
  2336. sde_kms_vm_res_release(kms, state);
  2337. end:
  2338. SDE_ATRACE_END("atomic_check");
  2339. return ret;
  2340. }
  2341. static struct msm_gem_address_space*
  2342. _sde_kms_get_address_space(struct msm_kms *kms,
  2343. unsigned int domain)
  2344. {
  2345. struct sde_kms *sde_kms;
  2346. if (!kms) {
  2347. SDE_ERROR("invalid kms\n");
  2348. return NULL;
  2349. }
  2350. sde_kms = to_sde_kms(kms);
  2351. if (!sde_kms) {
  2352. SDE_ERROR("invalid sde_kms\n");
  2353. return NULL;
  2354. }
  2355. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2356. return NULL;
  2357. return (sde_kms->aspace[domain] &&
  2358. sde_kms->aspace[domain]->domain_attached) ?
  2359. sde_kms->aspace[domain] : NULL;
  2360. }
  2361. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2362. unsigned int domain)
  2363. {
  2364. struct sde_kms *sde_kms;
  2365. struct msm_gem_address_space *aspace;
  2366. if (!kms) {
  2367. SDE_ERROR("invalid kms\n");
  2368. return NULL;
  2369. }
  2370. sde_kms = to_sde_kms(kms);
  2371. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2372. SDE_ERROR("invalid params\n");
  2373. return NULL;
  2374. }
  2375. aspace = _sde_kms_get_address_space(kms, domain);
  2376. return (aspace && aspace->domain_attached) ?
  2377. msm_gem_get_aspace_device(aspace) : NULL;
  2378. }
  2379. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2380. {
  2381. struct drm_device *dev = NULL;
  2382. struct sde_kms *sde_kms = NULL;
  2383. struct drm_connector *connector = NULL;
  2384. struct drm_connector_list_iter conn_iter;
  2385. struct sde_connector *sde_conn = NULL;
  2386. if (!kms) {
  2387. SDE_ERROR("invalid kms\n");
  2388. return;
  2389. }
  2390. sde_kms = to_sde_kms(kms);
  2391. dev = sde_kms->dev;
  2392. if (!dev) {
  2393. SDE_ERROR("invalid device\n");
  2394. return;
  2395. }
  2396. if (!dev->mode_config.poll_enabled)
  2397. return;
  2398. mutex_lock(&dev->mode_config.mutex);
  2399. drm_connector_list_iter_begin(dev, &conn_iter);
  2400. drm_for_each_connector_iter(connector, &conn_iter) {
  2401. /* Only handle HPD capable connectors. */
  2402. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2403. continue;
  2404. sde_conn = to_sde_connector(connector);
  2405. if (sde_conn->ops.post_open)
  2406. sde_conn->ops.post_open(&sde_conn->base,
  2407. sde_conn->display);
  2408. }
  2409. drm_connector_list_iter_end(&conn_iter);
  2410. mutex_unlock(&dev->mode_config.mutex);
  2411. }
  2412. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2413. struct sde_splash_display *splash_display,
  2414. struct drm_crtc *crtc)
  2415. {
  2416. struct msm_drm_private *priv;
  2417. struct drm_plane *plane;
  2418. struct sde_splash_mem *splash;
  2419. enum sde_sspp plane_id;
  2420. bool is_virtual;
  2421. int i, j;
  2422. if (!sde_kms || !splash_display || !crtc) {
  2423. SDE_ERROR("invalid input args\n");
  2424. return -EINVAL;
  2425. }
  2426. priv = sde_kms->dev->dev_private;
  2427. for (i = 0; i < priv->num_planes; i++) {
  2428. plane = priv->planes[i];
  2429. plane_id = sde_plane_pipe(plane);
  2430. is_virtual = is_sde_plane_virtual(plane);
  2431. splash = splash_display->splash;
  2432. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2433. if ((plane_id != splash_display->pipes[j].sspp) ||
  2434. (splash_display->pipes[j].is_virtual
  2435. != is_virtual))
  2436. continue;
  2437. if (splash && sde_plane_validate_src_addr(plane,
  2438. splash->splash_buf_base,
  2439. splash->splash_buf_size)) {
  2440. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2441. plane_id, crtc->base.id);
  2442. }
  2443. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2444. crtc->base.id, plane_id, is_virtual);
  2445. }
  2446. }
  2447. return 0;
  2448. }
  2449. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2450. struct sde_kms *sde_kms, struct drm_connector *connector,
  2451. u32 display_idx)
  2452. {
  2453. struct drm_display_mode *drm_mode = NULL, *curr_mode = NULL;
  2454. u32 i = 0, mode_index;
  2455. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2456. /* currently consider modes[0] as the preferred mode */
  2457. curr_mode = list_first_entry(&connector->modes,
  2458. struct drm_display_mode, head);
  2459. } else if (sde_kms->hw_mdp && sde_kms->hw_mdp->ops.get_mode_index) {
  2460. mode_index = sde_kms->hw_mdp->ops.get_mode_index(
  2461. sde_kms->hw_mdp, display_idx);
  2462. list_for_each_entry(drm_mode, &connector->modes, head) {
  2463. if (mode_index == i) {
  2464. curr_mode = drm_mode;
  2465. break;
  2466. }
  2467. i++;
  2468. }
  2469. }
  2470. return curr_mode;
  2471. }
  2472. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2473. struct dsi_display *dsi_display)
  2474. {
  2475. void *display;
  2476. struct drm_encoder *encoder = NULL;
  2477. struct msm_display_info info;
  2478. struct drm_device *dev;
  2479. struct sde_kms *sde_kms;
  2480. struct drm_connector_list_iter conn_iter;
  2481. struct drm_connector *connector = NULL;
  2482. struct sde_connector *sde_conn = NULL;
  2483. int rc = 0;
  2484. sde_kms = to_sde_kms(kms);
  2485. dev = sde_kms->dev;
  2486. display = dsi_display;
  2487. if (dsi_display) {
  2488. if (dsi_display->bridge->base.encoder) {
  2489. encoder = dsi_display->bridge->base.encoder;
  2490. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2491. }
  2492. memset(&info, 0x0, sizeof(info));
  2493. rc = dsi_display_get_info(NULL, &info, display);
  2494. if (rc) {
  2495. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2496. rc, __func__);
  2497. encoder = NULL;
  2498. }
  2499. }
  2500. drm_connector_list_iter_begin(dev, &conn_iter);
  2501. drm_for_each_connector_iter(connector, &conn_iter) {
  2502. /**
  2503. * Inform cont_splash is disabled to each interface/connector.
  2504. * This is currently supported for DSI interface.
  2505. */
  2506. sde_conn = to_sde_connector(connector);
  2507. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2508. if (!dsi_display || !encoder) {
  2509. sde_conn->ops.cont_splash_res_disable
  2510. (sde_conn->display);
  2511. } else if (connector->encoder_ids[0]
  2512. == encoder->base.id) {
  2513. /**
  2514. * This handles dual DSI
  2515. * configuration where one DSI
  2516. * interface has cont_splash
  2517. * enabled and the other doesn't.
  2518. */
  2519. sde_conn->ops.cont_splash_res_disable
  2520. (sde_conn->display);
  2521. break;
  2522. }
  2523. }
  2524. }
  2525. drm_connector_list_iter_end(&conn_iter);
  2526. return 0;
  2527. }
  2528. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2529. {
  2530. void *display;
  2531. struct dsi_display *dsi_display;
  2532. struct msm_display_info info;
  2533. struct drm_encoder *encoder = NULL;
  2534. struct drm_crtc *crtc = NULL;
  2535. int i, rc = 0;
  2536. struct drm_display_mode *drm_mode = NULL;
  2537. struct drm_device *dev;
  2538. struct msm_drm_private *priv;
  2539. struct sde_kms *sde_kms;
  2540. struct drm_connector_list_iter conn_iter;
  2541. struct drm_connector *connector = NULL;
  2542. struct sde_connector *sde_conn = NULL;
  2543. struct sde_splash_display *splash_display;
  2544. if (!kms) {
  2545. SDE_ERROR("invalid kms\n");
  2546. return -EINVAL;
  2547. }
  2548. sde_kms = to_sde_kms(kms);
  2549. dev = sde_kms->dev;
  2550. if (!dev) {
  2551. SDE_ERROR("invalid device\n");
  2552. return -EINVAL;
  2553. }
  2554. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2555. && (!sde_kms->splash_data.num_splash_regions)) ||
  2556. !sde_kms->splash_data.num_splash_displays) {
  2557. DRM_INFO("cont_splash feature not enabled\n");
  2558. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2559. return rc;
  2560. }
  2561. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2562. sde_kms->splash_data.num_splash_displays,
  2563. sde_kms->dsi_display_count);
  2564. /* dsi */
  2565. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2566. display = sde_kms->dsi_displays[i];
  2567. dsi_display = (struct dsi_display *)display;
  2568. splash_display = &sde_kms->splash_data.splash_display[i];
  2569. if (!splash_display->cont_splash_enabled) {
  2570. SDE_DEBUG("display->name = %s splash not enabled\n",
  2571. dsi_display->name);
  2572. sde_kms_inform_cont_splash_res_disable(kms,
  2573. dsi_display);
  2574. continue;
  2575. }
  2576. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2577. if (dsi_display->bridge->base.encoder) {
  2578. encoder = dsi_display->bridge->base.encoder;
  2579. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2580. }
  2581. memset(&info, 0x0, sizeof(info));
  2582. rc = dsi_display_get_info(NULL, &info, display);
  2583. if (rc) {
  2584. SDE_ERROR("dsi get_info %d failed\n", i);
  2585. encoder = NULL;
  2586. continue;
  2587. }
  2588. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2589. ((info.is_connected) ? "true" : "false"),
  2590. info.display_type);
  2591. if (!encoder) {
  2592. SDE_ERROR("encoder not initialized\n");
  2593. return -EINVAL;
  2594. }
  2595. priv = sde_kms->dev->dev_private;
  2596. encoder->crtc = priv->crtcs[i];
  2597. crtc = encoder->crtc;
  2598. splash_display->encoder = encoder;
  2599. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2600. i, crtc->base.id, encoder->base.id);
  2601. mutex_lock(&dev->mode_config.mutex);
  2602. drm_connector_list_iter_begin(dev, &conn_iter);
  2603. drm_for_each_connector_iter(connector, &conn_iter) {
  2604. /**
  2605. * SDE_KMS doesn't attach more than one encoder to
  2606. * a DSI connector. So it is safe to check only with
  2607. * the first encoder entry. Revisit this logic if we
  2608. * ever have to support continuous splash for
  2609. * external displays in MST configuration.
  2610. */
  2611. if (connector->encoder_ids[0] == encoder->base.id)
  2612. break;
  2613. }
  2614. drm_connector_list_iter_end(&conn_iter);
  2615. if (!connector) {
  2616. SDE_ERROR("connector not initialized\n");
  2617. mutex_unlock(&dev->mode_config.mutex);
  2618. return -EINVAL;
  2619. }
  2620. mutex_unlock(&dev->mode_config.mutex);
  2621. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2622. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, i);
  2623. if (!drm_mode) {
  2624. SDE_ERROR("invalid drm-mode type:%d, index:%d\n",
  2625. sde_kms->splash_data.type, i);
  2626. return -EINVAL;
  2627. }
  2628. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2629. drm_mode->name, drm_mode->type,
  2630. drm_mode->flags);
  2631. /* Update CRTC drm structure */
  2632. crtc->state->active = true;
  2633. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2634. if (rc) {
  2635. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2636. return rc;
  2637. }
  2638. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2639. drm_mode_copy(&crtc->mode, drm_mode);
  2640. /* Update encoder structure */
  2641. sde_encoder_update_caps_for_cont_splash(encoder,
  2642. splash_display, true);
  2643. sde_crtc_update_cont_splash_settings(crtc);
  2644. sde_conn = to_sde_connector(connector);
  2645. if (sde_conn && sde_conn->ops.cont_splash_config)
  2646. sde_conn->ops.cont_splash_config(sde_conn->display);
  2647. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2648. splash_display, crtc);
  2649. if (rc) {
  2650. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2651. return rc;
  2652. }
  2653. }
  2654. return rc;
  2655. }
  2656. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2657. {
  2658. struct sde_kms *sde_kms;
  2659. if (!kms) {
  2660. SDE_ERROR("invalid kms\n");
  2661. return false;
  2662. }
  2663. sde_kms = to_sde_kms(kms);
  2664. return sde_kms->splash_data.num_splash_displays;
  2665. }
  2666. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2667. const struct drm_display_mode *mode,
  2668. const struct msm_resource_caps_info *res, u32 *num_lm)
  2669. {
  2670. struct sde_kms *sde_kms;
  2671. s64 mode_clock_hz = 0;
  2672. s64 max_mdp_clock_hz = 0;
  2673. s64 max_lm_width = 0;
  2674. s64 hdisplay_fp = 0;
  2675. s64 htotal_fp = 0;
  2676. s64 vtotal_fp = 0;
  2677. s64 vrefresh_fp = 0;
  2678. s64 mdp_fudge_factor = 0;
  2679. s64 num_lm_fp = 0;
  2680. s64 lm_clk_fp = 0;
  2681. s64 lm_width_fp = 0;
  2682. int rc = 0;
  2683. if (!num_lm) {
  2684. SDE_ERROR("invalid num_lm pointer\n");
  2685. return -EINVAL;
  2686. }
  2687. /* default to 1 layer mixer */
  2688. *num_lm = 1;
  2689. if (!kms || !mode || !res) {
  2690. SDE_ERROR("invalid input args\n");
  2691. return -EINVAL;
  2692. }
  2693. sde_kms = to_sde_kms(kms);
  2694. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2695. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2696. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2697. htotal_fp = drm_int2fixp(mode->htotal);
  2698. vtotal_fp = drm_int2fixp(mode->vtotal);
  2699. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2700. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2701. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2702. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2703. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2704. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2705. if (mode_clock_hz > max_mdp_clock_hz ||
  2706. hdisplay_fp > max_lm_width) {
  2707. *num_lm = 0;
  2708. do {
  2709. *num_lm += 2;
  2710. num_lm_fp = drm_int2fixp(*num_lm);
  2711. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2712. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2713. if (*num_lm > 4) {
  2714. rc = -EINVAL;
  2715. goto error;
  2716. }
  2717. } while (lm_clk_fp > max_mdp_clock_hz ||
  2718. lm_width_fp > max_lm_width);
  2719. mode_clock_hz = lm_clk_fp;
  2720. }
  2721. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2722. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2723. *num_lm, drm_fixp2int(mode_clock_hz),
  2724. sde_kms->perf.max_core_clk_rate);
  2725. return 0;
  2726. error:
  2727. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2728. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2729. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2730. *num_lm, drm_fixp2int(mode_clock_hz),
  2731. sde_kms->perf.max_core_clk_rate);
  2732. return rc;
  2733. }
  2734. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2735. u32 hdisplay, u32 *num_dsc)
  2736. {
  2737. struct sde_kms *sde_kms;
  2738. uint32_t max_dsc_width;
  2739. if (!num_dsc) {
  2740. SDE_ERROR("invalid num_dsc pointer\n");
  2741. return -EINVAL;
  2742. }
  2743. *num_dsc = 0;
  2744. if (!kms || !hdisplay) {
  2745. SDE_ERROR("invalid input args\n");
  2746. return -EINVAL;
  2747. }
  2748. sde_kms = to_sde_kms(kms);
  2749. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2750. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2751. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2752. hdisplay, max_dsc_width,
  2753. *num_dsc);
  2754. return 0;
  2755. }
  2756. static void _sde_kms_null_commit(struct drm_device *dev,
  2757. struct drm_encoder *enc)
  2758. {
  2759. struct drm_modeset_acquire_ctx ctx;
  2760. struct drm_connector *conn = NULL;
  2761. struct drm_connector *tmp_conn = NULL;
  2762. struct drm_connector_list_iter conn_iter;
  2763. struct drm_atomic_state *state = NULL;
  2764. struct drm_crtc_state *crtc_state = NULL;
  2765. struct drm_connector_state *conn_state = NULL;
  2766. int retry_cnt = 0;
  2767. int ret = 0;
  2768. drm_modeset_acquire_init(&ctx, 0);
  2769. retry:
  2770. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2771. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2772. drm_modeset_backoff(&ctx);
  2773. retry_cnt++;
  2774. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2775. goto retry;
  2776. } else if (WARN_ON(ret)) {
  2777. goto end;
  2778. }
  2779. state = drm_atomic_state_alloc(dev);
  2780. if (!state) {
  2781. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2782. goto end;
  2783. }
  2784. state->acquire_ctx = &ctx;
  2785. drm_connector_list_iter_begin(dev, &conn_iter);
  2786. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2787. if (enc == tmp_conn->state->best_encoder) {
  2788. conn = tmp_conn;
  2789. break;
  2790. }
  2791. }
  2792. drm_connector_list_iter_end(&conn_iter);
  2793. if (!conn) {
  2794. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2795. goto end;
  2796. }
  2797. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2798. conn_state = drm_atomic_get_connector_state(state, conn);
  2799. if (IS_ERR(conn_state)) {
  2800. SDE_ERROR("error %d getting connector %d state\n",
  2801. ret, DRMID(conn));
  2802. goto end;
  2803. }
  2804. crtc_state->active = true;
  2805. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2806. if (ret)
  2807. SDE_ERROR("error %d setting the crtc\n", ret);
  2808. ret = drm_atomic_commit(state);
  2809. if (ret)
  2810. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2811. end:
  2812. if (state)
  2813. drm_atomic_state_put(state);
  2814. drm_modeset_drop_locks(&ctx);
  2815. drm_modeset_acquire_fini(&ctx);
  2816. }
  2817. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2818. const int32_t connector_id)
  2819. {
  2820. struct drm_connector_list_iter conn_iter;
  2821. struct drm_connector *conn;
  2822. struct drm_encoder *drm_enc;
  2823. drm_connector_list_iter_begin(dev, &conn_iter);
  2824. drm_for_each_connector_iter(conn, &conn_iter) {
  2825. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2826. connector_id != conn->base.id)
  2827. continue;
  2828. if (conn->state && conn->state->best_encoder)
  2829. drm_enc = conn->state->best_encoder;
  2830. else
  2831. drm_enc = conn->encoder;
  2832. if (drm_enc)
  2833. sde_encoder_early_wakeup(drm_enc);
  2834. }
  2835. drm_connector_list_iter_end(&conn_iter);
  2836. }
  2837. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2838. struct device *dev)
  2839. {
  2840. int i, ret, crtc_id = 0;
  2841. struct drm_device *ddev = dev_get_drvdata(dev);
  2842. struct drm_connector *conn;
  2843. struct drm_connector_list_iter conn_iter;
  2844. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2845. drm_connector_list_iter_begin(ddev, &conn_iter);
  2846. drm_for_each_connector_iter(conn, &conn_iter) {
  2847. uint64_t lp;
  2848. lp = sde_connector_get_lp(conn);
  2849. if (lp != SDE_MODE_DPMS_LP2)
  2850. continue;
  2851. if (sde_encoder_in_clone_mode(conn->encoder))
  2852. continue;
  2853. ret = sde_encoder_wait_for_event(conn->encoder,
  2854. MSM_ENC_TX_COMPLETE);
  2855. if (ret && ret != -EWOULDBLOCK) {
  2856. SDE_ERROR(
  2857. "[conn: %d] wait for commit done returned %d\n",
  2858. conn->base.id, ret);
  2859. } else if (!ret) {
  2860. crtc_id = drm_crtc_index(conn->state->crtc);
  2861. if (priv->event_thread[crtc_id].thread)
  2862. kthread_flush_worker(
  2863. &priv->event_thread[crtc_id].worker);
  2864. sde_encoder_idle_request(conn->encoder);
  2865. }
  2866. }
  2867. drm_connector_list_iter_end(&conn_iter);
  2868. for (i = 0; i < priv->num_crtcs; i++) {
  2869. if (priv->disp_thread[i].thread)
  2870. kthread_flush_worker(
  2871. &priv->disp_thread[i].worker);
  2872. if (priv->event_thread[i].thread)
  2873. kthread_flush_worker(
  2874. &priv->event_thread[i].worker);
  2875. }
  2876. kthread_flush_worker(&priv->pp_event_worker);
  2877. }
  2878. static int sde_kms_pm_suspend(struct device *dev)
  2879. {
  2880. struct drm_device *ddev;
  2881. struct drm_modeset_acquire_ctx ctx;
  2882. struct drm_connector *conn;
  2883. struct drm_encoder *enc;
  2884. struct drm_connector_list_iter conn_iter;
  2885. struct drm_atomic_state *state = NULL;
  2886. struct sde_kms *sde_kms;
  2887. int ret = 0, num_crtcs = 0;
  2888. if (!dev)
  2889. return -EINVAL;
  2890. ddev = dev_get_drvdata(dev);
  2891. if (!ddev || !ddev_to_msm_kms(ddev))
  2892. return -EINVAL;
  2893. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2894. SDE_EVT32(0);
  2895. /* disable hot-plug polling */
  2896. drm_kms_helper_poll_disable(ddev);
  2897. /* if a display stuck in CS trigger a null commit to complete handoff */
  2898. drm_for_each_encoder(enc, ddev) {
  2899. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2900. _sde_kms_null_commit(ddev, enc);
  2901. }
  2902. /* acquire modeset lock(s) */
  2903. drm_modeset_acquire_init(&ctx, 0);
  2904. retry:
  2905. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2906. if (ret)
  2907. goto unlock;
  2908. /* save current state for resume */
  2909. if (sde_kms->suspend_state)
  2910. drm_atomic_state_put(sde_kms->suspend_state);
  2911. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2912. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2913. ret = PTR_ERR(sde_kms->suspend_state);
  2914. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2915. sde_kms->suspend_state = NULL;
  2916. goto unlock;
  2917. }
  2918. /* create atomic state to disable all CRTCs */
  2919. state = drm_atomic_state_alloc(ddev);
  2920. if (!state) {
  2921. ret = -ENOMEM;
  2922. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2923. goto unlock;
  2924. }
  2925. state->acquire_ctx = &ctx;
  2926. drm_connector_list_iter_begin(ddev, &conn_iter);
  2927. drm_for_each_connector_iter(conn, &conn_iter) {
  2928. struct drm_crtc_state *crtc_state;
  2929. uint64_t lp;
  2930. if (!conn->state || !conn->state->crtc ||
  2931. conn->dpms != DRM_MODE_DPMS_ON ||
  2932. sde_encoder_in_clone_mode(conn->encoder))
  2933. continue;
  2934. lp = sde_connector_get_lp(conn);
  2935. if (lp == SDE_MODE_DPMS_LP1) {
  2936. /* transition LP1->LP2 on pm suspend */
  2937. ret = sde_connector_set_property_for_commit(conn, state,
  2938. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2939. if (ret) {
  2940. DRM_ERROR("failed to set lp2 for conn %d\n",
  2941. conn->base.id);
  2942. drm_connector_list_iter_end(&conn_iter);
  2943. goto unlock;
  2944. }
  2945. }
  2946. if (lp != SDE_MODE_DPMS_LP2) {
  2947. /* force CRTC to be inactive */
  2948. crtc_state = drm_atomic_get_crtc_state(state,
  2949. conn->state->crtc);
  2950. if (IS_ERR_OR_NULL(crtc_state)) {
  2951. DRM_ERROR("failed to get crtc %d state\n",
  2952. conn->state->crtc->base.id);
  2953. drm_connector_list_iter_end(&conn_iter);
  2954. goto unlock;
  2955. }
  2956. if (lp != SDE_MODE_DPMS_LP1)
  2957. crtc_state->active = false;
  2958. ++num_crtcs;
  2959. }
  2960. }
  2961. drm_connector_list_iter_end(&conn_iter);
  2962. /* check for nothing to do */
  2963. if (num_crtcs == 0) {
  2964. DRM_DEBUG("all crtcs are already in the off state\n");
  2965. sde_kms->suspend_block = true;
  2966. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2967. goto unlock;
  2968. }
  2969. /* commit the "disable all" state */
  2970. ret = drm_atomic_commit(state);
  2971. if (ret < 0) {
  2972. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2973. goto unlock;
  2974. }
  2975. sde_kms->suspend_block = true;
  2976. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2977. unlock:
  2978. if (state) {
  2979. drm_atomic_state_put(state);
  2980. state = NULL;
  2981. }
  2982. if (ret == -EDEADLK) {
  2983. drm_modeset_backoff(&ctx);
  2984. goto retry;
  2985. }
  2986. drm_modeset_drop_locks(&ctx);
  2987. drm_modeset_acquire_fini(&ctx);
  2988. /*
  2989. * pm runtime driver avoids multiple runtime_suspend API call by
  2990. * checking runtime_status. However, this call helps when there is a
  2991. * race condition between pm_suspend call and doze_suspend/power_off
  2992. * commit. It removes the extra vote from suspend and adds it back
  2993. * later to allow power collapse during pm_suspend call
  2994. */
  2995. pm_runtime_put_sync(dev);
  2996. pm_runtime_get_noresume(dev);
  2997. /* dump clock state before entering suspend */
  2998. if (sde_kms->pm_suspend_clk_dump)
  2999. _sde_kms_dump_clks_state(sde_kms);
  3000. return ret;
  3001. }
  3002. static int sde_kms_pm_resume(struct device *dev)
  3003. {
  3004. struct drm_device *ddev;
  3005. struct sde_kms *sde_kms;
  3006. struct drm_modeset_acquire_ctx ctx;
  3007. int ret, i;
  3008. if (!dev)
  3009. return -EINVAL;
  3010. ddev = dev_get_drvdata(dev);
  3011. if (!ddev || !ddev_to_msm_kms(ddev))
  3012. return -EINVAL;
  3013. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3014. SDE_EVT32(sde_kms->suspend_state != NULL);
  3015. drm_mode_config_reset(ddev);
  3016. drm_modeset_acquire_init(&ctx, 0);
  3017. retry:
  3018. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3019. if (ret == -EDEADLK) {
  3020. drm_modeset_backoff(&ctx);
  3021. goto retry;
  3022. } else if (WARN_ON(ret)) {
  3023. goto end;
  3024. }
  3025. sde_kms->suspend_block = false;
  3026. if (sde_kms->suspend_state) {
  3027. sde_kms->suspend_state->acquire_ctx = &ctx;
  3028. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3029. ret = drm_atomic_helper_commit_duplicated_state(
  3030. sde_kms->suspend_state, &ctx);
  3031. if (ret != -EDEADLK)
  3032. break;
  3033. drm_modeset_backoff(&ctx);
  3034. }
  3035. if (ret < 0)
  3036. DRM_ERROR("failed to restore state, %d\n", ret);
  3037. drm_atomic_state_put(sde_kms->suspend_state);
  3038. sde_kms->suspend_state = NULL;
  3039. }
  3040. end:
  3041. drm_modeset_drop_locks(&ctx);
  3042. drm_modeset_acquire_fini(&ctx);
  3043. /* enable hot-plug polling */
  3044. drm_kms_helper_poll_enable(ddev);
  3045. return 0;
  3046. }
  3047. static const struct msm_kms_funcs kms_funcs = {
  3048. .hw_init = sde_kms_hw_init,
  3049. .postinit = sde_kms_postinit,
  3050. .irq_preinstall = sde_irq_preinstall,
  3051. .irq_postinstall = sde_irq_postinstall,
  3052. .irq_uninstall = sde_irq_uninstall,
  3053. .irq = sde_irq,
  3054. .lastclose = sde_kms_lastclose,
  3055. .prepare_fence = sde_kms_prepare_fence,
  3056. .prepare_commit = sde_kms_prepare_commit,
  3057. .commit = sde_kms_commit,
  3058. .complete_commit = sde_kms_complete_commit,
  3059. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3060. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3061. .enable_vblank = sde_kms_enable_vblank,
  3062. .disable_vblank = sde_kms_disable_vblank,
  3063. .check_modified_format = sde_format_check_modified_format,
  3064. .atomic_check = sde_kms_atomic_check,
  3065. .get_format = sde_get_msm_format,
  3066. .round_pixclk = sde_kms_round_pixclk,
  3067. .display_early_wakeup = sde_kms_display_early_wakeup,
  3068. .pm_suspend = sde_kms_pm_suspend,
  3069. .pm_resume = sde_kms_pm_resume,
  3070. .destroy = sde_kms_destroy,
  3071. .debugfs_destroy = sde_kms_debugfs_destroy,
  3072. .cont_splash_config = sde_kms_cont_splash_config,
  3073. .register_events = _sde_kms_register_events,
  3074. .get_address_space = _sde_kms_get_address_space,
  3075. .get_address_space_device = _sde_kms_get_address_space_device,
  3076. .postopen = _sde_kms_post_open,
  3077. .check_for_splash = sde_kms_check_for_splash,
  3078. .get_mixer_count = sde_kms_get_mixer_count,
  3079. .get_dsc_count = sde_kms_get_dsc_count,
  3080. };
  3081. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3082. {
  3083. int i;
  3084. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3085. if (!sde_kms->aspace[i])
  3086. continue;
  3087. msm_gem_address_space_put(sde_kms->aspace[i]);
  3088. sde_kms->aspace[i] = NULL;
  3089. }
  3090. return 0;
  3091. }
  3092. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3093. {
  3094. struct msm_mmu *mmu;
  3095. int i, ret;
  3096. int early_map = 0;
  3097. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3098. return -EINVAL;
  3099. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3100. struct msm_gem_address_space *aspace;
  3101. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3102. if (IS_ERR(mmu)) {
  3103. ret = PTR_ERR(mmu);
  3104. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3105. i, ret);
  3106. continue;
  3107. }
  3108. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3109. mmu, "sde");
  3110. if (IS_ERR(aspace)) {
  3111. ret = PTR_ERR(aspace);
  3112. mmu->funcs->destroy(mmu);
  3113. goto fail;
  3114. }
  3115. sde_kms->aspace[i] = aspace;
  3116. aspace->domain_attached = true;
  3117. /* Mapping splash memory block */
  3118. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3119. sde_kms->splash_data.num_splash_regions) {
  3120. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3121. if (ret) {
  3122. SDE_ERROR("failed to map ret:%d\n", ret);
  3123. goto fail;
  3124. }
  3125. }
  3126. /*
  3127. * disable early-map which would have been enabled during
  3128. * bootup by smmu through the device-tree hint for cont-spash
  3129. */
  3130. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3131. &early_map);
  3132. if (ret) {
  3133. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3134. ret, early_map);
  3135. goto early_map_fail;
  3136. }
  3137. }
  3138. sde_kms->base.aspace = sde_kms->aspace[0];
  3139. return 0;
  3140. early_map_fail:
  3141. _sde_kms_unmap_all_splash_regions(sde_kms);
  3142. fail:
  3143. _sde_kms_mmu_destroy(sde_kms);
  3144. return ret;
  3145. }
  3146. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3147. {
  3148. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3149. return;
  3150. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3151. }
  3152. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3153. {
  3154. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3155. return;
  3156. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3157. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3158. sde_kms->catalog);
  3159. }
  3160. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3161. {
  3162. struct sde_vbif_set_qos_params qos_params;
  3163. struct sde_mdss_cfg *catalog;
  3164. if (!sde_kms->catalog)
  3165. return;
  3166. catalog = sde_kms->catalog;
  3167. memset(&qos_params, 0, sizeof(qos_params));
  3168. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3169. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3170. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3171. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3172. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3173. }
  3174. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3175. {
  3176. struct sde_hw_uidle *uidle;
  3177. if (!sde_kms) {
  3178. SDE_ERROR("invalid kms\n");
  3179. return -EINVAL;
  3180. }
  3181. uidle = sde_kms->hw_uidle;
  3182. if (uidle && uidle->ops.active_override_enable)
  3183. uidle->ops.active_override_enable(uidle, enable);
  3184. return 0;
  3185. }
  3186. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3187. {
  3188. struct device *cpu_dev;
  3189. int cpu = 0;
  3190. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3191. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3192. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3193. return;
  3194. }
  3195. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3196. cpu_dev = get_cpu_device(cpu);
  3197. if (!cpu_dev) {
  3198. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3199. cpu);
  3200. continue;
  3201. }
  3202. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3203. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3204. cpu_irq_latency);
  3205. else
  3206. dev_pm_qos_add_request(cpu_dev,
  3207. &sde_kms->pm_qos_irq_req[cpu],
  3208. DEV_PM_QOS_RESUME_LATENCY,
  3209. cpu_irq_latency);
  3210. }
  3211. }
  3212. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3213. {
  3214. struct device *cpu_dev;
  3215. int cpu = 0;
  3216. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3217. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3218. return;
  3219. }
  3220. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3221. cpu_dev = get_cpu_device(cpu);
  3222. if (!cpu_dev) {
  3223. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3224. cpu);
  3225. continue;
  3226. }
  3227. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3228. dev_pm_qos_remove_request(
  3229. &sde_kms->pm_qos_irq_req[cpu]);
  3230. }
  3231. }
  3232. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3233. {
  3234. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3235. mutex_lock(&priv->phandle.phandle_lock);
  3236. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3237. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3238. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3239. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3240. mutex_unlock(&priv->phandle.phandle_lock);
  3241. }
  3242. static void sde_kms_irq_affinity_notify(
  3243. struct irq_affinity_notify *affinity_notify,
  3244. const cpumask_t *mask)
  3245. {
  3246. struct msm_drm_private *priv;
  3247. struct sde_kms *sde_kms = container_of(affinity_notify,
  3248. struct sde_kms, affinity_notify);
  3249. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3250. return;
  3251. priv = sde_kms->dev->dev_private;
  3252. mutex_lock(&priv->phandle.phandle_lock);
  3253. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3254. // save irq cpu mask
  3255. sde_kms->irq_cpu_mask = *mask;
  3256. // request vote with updated irq cpu mask
  3257. if (atomic_read(&sde_kms->irq_vote_count))
  3258. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3259. mutex_unlock(&priv->phandle.phandle_lock);
  3260. }
  3261. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3262. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3263. {
  3264. struct sde_kms *sde_kms = usr;
  3265. struct msm_kms *msm_kms;
  3266. msm_kms = &sde_kms->base;
  3267. if (!sde_kms)
  3268. return;
  3269. SDE_DEBUG("event_type:%d\n", event_type);
  3270. SDE_EVT32_VERBOSE(event_type);
  3271. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3272. sde_irq_update(msm_kms, true);
  3273. sde_kms->first_kickoff = true;
  3274. /**
  3275. * Rotator sid needs to be programmed since uefi doesn't
  3276. * configure it during continuous splash
  3277. */
  3278. sde_kms_init_rot_sid_hw(sde_kms);
  3279. if (sde_kms->splash_data.num_splash_displays ||
  3280. sde_in_trusted_vm(sde_kms))
  3281. return;
  3282. sde_vbif_init_memtypes(sde_kms);
  3283. sde_kms_init_shared_hw(sde_kms);
  3284. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3285. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3286. sde_irq_update(msm_kms, false);
  3287. sde_kms->first_kickoff = false;
  3288. if (sde_in_trusted_vm(sde_kms))
  3289. return;
  3290. _sde_kms_active_override(sde_kms, true);
  3291. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3292. sde_vbif_axi_halt_request(sde_kms);
  3293. }
  3294. }
  3295. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3296. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3297. {
  3298. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3299. int rc = -EINVAL;
  3300. SDE_DEBUG("\n");
  3301. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3302. if (rc > 0)
  3303. rc = 0;
  3304. SDE_EVT32(rc, genpd->device_count);
  3305. return rc;
  3306. }
  3307. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3308. {
  3309. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3310. SDE_DEBUG("\n");
  3311. pm_runtime_put_sync(sde_kms->dev->dev);
  3312. SDE_EVT32(genpd->device_count);
  3313. return 0;
  3314. }
  3315. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3316. struct sde_splash_data *data)
  3317. {
  3318. int i = 0;
  3319. int ret = 0;
  3320. struct device_node *parent, *node, *node1;
  3321. struct resource r, r1;
  3322. const char *node_name = "splash_region";
  3323. struct sde_splash_mem *mem;
  3324. bool share_splash_mem = false;
  3325. int num_displays, num_regions;
  3326. struct sde_splash_display *splash_display;
  3327. if (!data)
  3328. return -EINVAL;
  3329. memset(data, 0, sizeof(*data));
  3330. parent = of_find_node_by_path("/reserved-memory");
  3331. if (!parent) {
  3332. SDE_ERROR("failed to find reserved-memory node\n");
  3333. return -EINVAL;
  3334. }
  3335. node = of_find_node_by_name(parent, node_name);
  3336. if (!node) {
  3337. SDE_DEBUG("failed to find node %s\n", node_name);
  3338. return -EINVAL;
  3339. }
  3340. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3341. if (!node1)
  3342. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3343. /**
  3344. * Support sharing a single splash memory for all the built in displays
  3345. * and also independent splash region per displays. Incase of
  3346. * independent splash region for each connected display, dtsi node of
  3347. * cont_splash_region should be collection of all memory regions
  3348. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3349. */
  3350. num_displays = dsi_display_get_num_of_displays();
  3351. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3352. data->num_splash_displays = num_displays;
  3353. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3354. if (num_displays > num_regions) {
  3355. share_splash_mem = true;
  3356. pr_info(":%d displays share same splash buf\n", num_displays);
  3357. }
  3358. for (i = 0; i < num_displays; i++) {
  3359. splash_display = &data->splash_display[i];
  3360. if (!i || !share_splash_mem) {
  3361. if (of_address_to_resource(node, i, &r)) {
  3362. SDE_ERROR("invalid data for:%s\n", node_name);
  3363. return -EINVAL;
  3364. }
  3365. mem = &data->splash_mem[i];
  3366. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3367. SDE_DEBUG("failed to find ramdump memory\n");
  3368. mem->ramdump_base = 0;
  3369. mem->ramdump_size = 0;
  3370. } else {
  3371. mem->ramdump_base = (unsigned long)r1.start;
  3372. mem->ramdump_size = (r1.end - r1.start) + 1;
  3373. }
  3374. mem->splash_buf_base = (unsigned long)r.start;
  3375. mem->splash_buf_size = (r.end - r.start) + 1;
  3376. mem->ref_cnt = 0;
  3377. splash_display->splash = mem;
  3378. data->num_splash_regions++;
  3379. } else {
  3380. data->splash_display[i].splash = &data->splash_mem[0];
  3381. }
  3382. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3383. splash_display->splash->splash_buf_base,
  3384. splash_display->splash->splash_buf_size);
  3385. }
  3386. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3387. return ret;
  3388. }
  3389. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3390. struct platform_device *platformdev)
  3391. {
  3392. int rc = -EINVAL;
  3393. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3394. if (IS_ERR(sde_kms->mmio)) {
  3395. rc = PTR_ERR(sde_kms->mmio);
  3396. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3397. sde_kms->mmio = NULL;
  3398. goto error;
  3399. }
  3400. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3401. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3402. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3403. sde_kms->mmio_len);
  3404. if (rc)
  3405. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3406. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3407. "vbif_phys");
  3408. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3409. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3410. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3411. sde_kms->vbif[VBIF_RT] = NULL;
  3412. goto error;
  3413. }
  3414. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3415. "vbif_phys");
  3416. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3417. sde_kms->vbif_len[VBIF_RT]);
  3418. if (rc)
  3419. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3420. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3421. "vbif_nrt_phys");
  3422. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3423. sde_kms->vbif[VBIF_NRT] = NULL;
  3424. SDE_DEBUG("VBIF NRT is not defined");
  3425. } else {
  3426. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3427. "vbif_nrt_phys");
  3428. rc = sde_dbg_reg_register_base("vbif_nrt",
  3429. sde_kms->vbif[VBIF_NRT],
  3430. sde_kms->vbif_len[VBIF_NRT]);
  3431. if (rc)
  3432. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3433. rc);
  3434. }
  3435. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3436. "regdma_phys");
  3437. if (IS_ERR(sde_kms->reg_dma)) {
  3438. sde_kms->reg_dma = NULL;
  3439. SDE_DEBUG("REG_DMA is not defined");
  3440. } else {
  3441. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3442. "regdma_phys");
  3443. rc = sde_dbg_reg_register_base("reg_dma",
  3444. sde_kms->reg_dma,
  3445. sde_kms->reg_dma_len);
  3446. if (rc)
  3447. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3448. rc);
  3449. }
  3450. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3451. "sid_phys");
  3452. if (IS_ERR(sde_kms->sid)) {
  3453. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3454. sde_kms->sid = NULL;
  3455. } else {
  3456. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3457. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3458. sde_kms->sid_len);
  3459. if (rc)
  3460. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3461. }
  3462. error:
  3463. return rc;
  3464. }
  3465. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3466. struct sde_kms *sde_kms)
  3467. {
  3468. int rc = 0;
  3469. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3470. sde_kms->genpd.name = dev->unique;
  3471. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3472. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3473. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3474. if (rc < 0) {
  3475. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3476. sde_kms->genpd.name, rc);
  3477. return rc;
  3478. }
  3479. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3480. &sde_kms->genpd);
  3481. if (rc < 0) {
  3482. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3483. sde_kms->genpd.name, rc);
  3484. pm_genpd_remove(&sde_kms->genpd);
  3485. return rc;
  3486. }
  3487. sde_kms->genpd_init = true;
  3488. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3489. }
  3490. return rc;
  3491. }
  3492. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3493. struct drm_device *dev,
  3494. struct msm_drm_private *priv)
  3495. {
  3496. struct sde_rm *rm = NULL;
  3497. int i, rc = -EINVAL;
  3498. sde_kms->catalog = sde_hw_catalog_init(dev);
  3499. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3500. rc = PTR_ERR(sde_kms->catalog);
  3501. if (!sde_kms->catalog)
  3502. rc = -EINVAL;
  3503. SDE_ERROR("catalog init failed: %d\n", rc);
  3504. sde_kms->catalog = NULL;
  3505. goto power_error;
  3506. }
  3507. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3508. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3509. /* initialize power domain if defined */
  3510. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3511. if (rc) {
  3512. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3513. goto genpd_err;
  3514. }
  3515. rc = _sde_kms_mmu_init(sde_kms);
  3516. if (rc) {
  3517. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3518. goto power_error;
  3519. }
  3520. /* Initialize reg dma block which is a singleton */
  3521. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3522. sde_kms->dev);
  3523. if (rc) {
  3524. SDE_ERROR("failed: reg dma init failed\n");
  3525. goto power_error;
  3526. }
  3527. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3528. rm = &sde_kms->rm;
  3529. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3530. sde_kms->dev);
  3531. if (rc) {
  3532. SDE_ERROR("rm init failed: %d\n", rc);
  3533. goto power_error;
  3534. }
  3535. sde_kms->rm_init = true;
  3536. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3537. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3538. rc = PTR_ERR(sde_kms->hw_intr);
  3539. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3540. sde_kms->hw_intr = NULL;
  3541. goto hw_intr_init_err;
  3542. }
  3543. /*
  3544. * Attempt continuous splash handoff only if reserved
  3545. * splash memory is found & release resources on any error
  3546. * in finding display hw config in splash
  3547. */
  3548. if (sde_kms->splash_data.num_splash_regions) {
  3549. struct sde_splash_display *display;
  3550. int ret, display_count =
  3551. sde_kms->splash_data.num_splash_displays;
  3552. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3553. &sde_kms->splash_data, sde_kms->catalog);
  3554. for (i = 0; i < display_count; i++) {
  3555. display = &sde_kms->splash_data.splash_display[i];
  3556. /*
  3557. * free splash region on resource init failure and
  3558. * cont-splash disabled case
  3559. */
  3560. if (!display->cont_splash_enabled || ret)
  3561. _sde_kms_free_splash_display_data(
  3562. sde_kms, display);
  3563. }
  3564. }
  3565. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3566. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3567. rc = PTR_ERR(sde_kms->hw_mdp);
  3568. if (!sde_kms->hw_mdp)
  3569. rc = -EINVAL;
  3570. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3571. sde_kms->hw_mdp = NULL;
  3572. goto power_error;
  3573. }
  3574. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3575. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3576. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3577. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3578. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3579. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3580. if (!sde_kms->hw_vbif[vbif_idx])
  3581. rc = -EINVAL;
  3582. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3583. sde_kms->hw_vbif[vbif_idx] = NULL;
  3584. goto power_error;
  3585. }
  3586. }
  3587. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3588. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3589. sde_kms->mmio_len, sde_kms->catalog);
  3590. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3591. rc = PTR_ERR(sde_kms->hw_uidle);
  3592. if (!sde_kms->hw_uidle)
  3593. rc = -EINVAL;
  3594. /* uidle is optional, so do not make it a fatal error */
  3595. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3596. sde_kms->hw_uidle = NULL;
  3597. rc = 0;
  3598. }
  3599. } else {
  3600. sde_kms->hw_uidle = NULL;
  3601. }
  3602. if (sde_kms->sid) {
  3603. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3604. sde_kms->sid_len, sde_kms->catalog);
  3605. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3606. rc = PTR_ERR(sde_kms->hw_sid);
  3607. SDE_ERROR("failed to init sid %ld\n", rc);
  3608. sde_kms->hw_sid = NULL;
  3609. goto power_error;
  3610. }
  3611. }
  3612. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3613. &priv->phandle, "core_clk");
  3614. if (rc) {
  3615. SDE_ERROR("failed to init perf %d\n", rc);
  3616. goto perf_err;
  3617. }
  3618. /*
  3619. * _sde_kms_drm_obj_init should create the DRM related objects
  3620. * i.e. CRTCs, planes, encoders, connectors and so forth
  3621. */
  3622. rc = _sde_kms_drm_obj_init(sde_kms);
  3623. if (rc) {
  3624. SDE_ERROR("modeset init failed: %d\n", rc);
  3625. goto drm_obj_init_err;
  3626. }
  3627. return 0;
  3628. genpd_err:
  3629. drm_obj_init_err:
  3630. sde_core_perf_destroy(&sde_kms->perf);
  3631. hw_intr_init_err:
  3632. perf_err:
  3633. power_error:
  3634. return rc;
  3635. }
  3636. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3637. {
  3638. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3639. int rc = 0;
  3640. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3641. if (rc) {
  3642. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3643. return rc;
  3644. }
  3645. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3646. if (rc) {
  3647. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3648. return rc;
  3649. }
  3650. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3651. if (rc) {
  3652. SDE_ERROR("failed to get io irq for KMS");
  3653. return rc;
  3654. }
  3655. return rc;
  3656. }
  3657. static int sde_kms_hw_init(struct msm_kms *kms)
  3658. {
  3659. struct sde_kms *sde_kms;
  3660. struct drm_device *dev;
  3661. struct msm_drm_private *priv;
  3662. struct platform_device *platformdev;
  3663. int i, irq_num, rc = -EINVAL;
  3664. if (!kms) {
  3665. SDE_ERROR("invalid kms\n");
  3666. goto end;
  3667. }
  3668. sde_kms = to_sde_kms(kms);
  3669. dev = sde_kms->dev;
  3670. if (!dev || !dev->dev) {
  3671. SDE_ERROR("invalid device\n");
  3672. goto end;
  3673. }
  3674. platformdev = to_platform_device(dev->dev);
  3675. priv = dev->dev_private;
  3676. if (!priv) {
  3677. SDE_ERROR("invalid private data\n");
  3678. goto end;
  3679. }
  3680. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3681. if (rc)
  3682. goto error;
  3683. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3684. if (rc)
  3685. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3686. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3687. if (rc)
  3688. goto error;
  3689. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3690. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3691. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3692. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3693. mutex_init(&sde_kms->secure_transition_lock);
  3694. atomic_set(&sde_kms->detach_sec_cb, 0);
  3695. atomic_set(&sde_kms->detach_all_cb, 0);
  3696. atomic_set(&sde_kms->irq_vote_count, 0);
  3697. /*
  3698. * Support format modifiers for compression etc.
  3699. */
  3700. dev->mode_config.allow_fb_modifiers = true;
  3701. /*
  3702. * Handle (re)initializations during power enable
  3703. */
  3704. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3705. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3706. SDE_POWER_EVENT_POST_ENABLE |
  3707. SDE_POWER_EVENT_PRE_DISABLE,
  3708. sde_kms_handle_power_event, sde_kms, "kms");
  3709. if (sde_kms->splash_data.num_splash_displays) {
  3710. SDE_DEBUG("Skipping MDP Resources disable\n");
  3711. } else {
  3712. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3713. sde_power_data_bus_set_quota(&priv->phandle, i,
  3714. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3715. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3716. pm_runtime_put_sync(sde_kms->dev->dev);
  3717. }
  3718. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3719. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3720. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3721. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3722. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3723. if (sde_in_trusted_vm(sde_kms))
  3724. rc = sde_vm_trusted_init(sde_kms);
  3725. else
  3726. rc = sde_vm_primary_init(sde_kms);
  3727. if (rc) {
  3728. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3729. goto error;
  3730. }
  3731. return 0;
  3732. error:
  3733. _sde_kms_hw_destroy(sde_kms, platformdev);
  3734. end:
  3735. return rc;
  3736. }
  3737. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3738. {
  3739. struct msm_drm_private *priv;
  3740. struct sde_kms *sde_kms;
  3741. if (!dev || !dev->dev_private) {
  3742. SDE_ERROR("drm device node invalid\n");
  3743. return ERR_PTR(-EINVAL);
  3744. }
  3745. priv = dev->dev_private;
  3746. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3747. if (!sde_kms) {
  3748. SDE_ERROR("failed to allocate sde kms\n");
  3749. return ERR_PTR(-ENOMEM);
  3750. }
  3751. msm_kms_init(&sde_kms->base, &kms_funcs);
  3752. sde_kms->dev = dev;
  3753. return &sde_kms->base;
  3754. }
  3755. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3756. {
  3757. struct dsi_display *display;
  3758. struct sde_splash_display *handoff_display;
  3759. int i;
  3760. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3761. handoff_display = &sde_kms->splash_data.splash_display[i];
  3762. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3763. if (handoff_display->cont_splash_enabled)
  3764. _sde_kms_free_splash_display_data(sde_kms,
  3765. handoff_display);
  3766. dsi_display_set_active_state(display, false);
  3767. }
  3768. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3769. }
  3770. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms)
  3771. {
  3772. struct drm_device *dev;
  3773. struct msm_drm_private *priv;
  3774. struct sde_splash_display *handoff_display;
  3775. struct dsi_display *display;
  3776. int ret, i;
  3777. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3778. SDE_ERROR("invalid params\n");
  3779. return -EINVAL;
  3780. }
  3781. if (sde_kms->dsi_display_count != 1) {
  3782. SDE_ERROR("no. of displays not supported:%d\n",
  3783. sde_kms->dsi_display_count);
  3784. return -EINVAL;
  3785. }
  3786. dev = sde_kms->dev;
  3787. priv = dev->dev_private;
  3788. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3789. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3790. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3791. &sde_kms->splash_data, sde_kms->catalog);
  3792. if (ret) {
  3793. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  3794. return -EINVAL;
  3795. }
  3796. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3797. handoff_display = &sde_kms->splash_data.splash_display[i];
  3798. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3799. if (!handoff_display->cont_splash_enabled || ret)
  3800. _sde_kms_free_splash_display_data(sde_kms,
  3801. handoff_display);
  3802. else
  3803. dsi_display_set_active_state(display, true);
  3804. }
  3805. ret = sde_kms_cont_splash_config(&sde_kms->base);
  3806. if (ret) {
  3807. SDE_ERROR("error in setting handoff configs\n");
  3808. goto error;
  3809. }
  3810. /**
  3811. * fill-in vote for the continuous splash hanodff path, which will be
  3812. * removed on the successful first commit.
  3813. */
  3814. pm_runtime_get_sync(sde_kms->dev->dev);
  3815. return 0;
  3816. error:
  3817. sde_kms_vm_trusted_resource_deinit(sde_kms);
  3818. return ret;
  3819. }
  3820. static int _sde_kms_register_events(struct msm_kms *kms,
  3821. struct drm_mode_object *obj, u32 event, bool en)
  3822. {
  3823. int ret = 0;
  3824. struct drm_crtc *crtc = NULL;
  3825. struct drm_connector *conn = NULL;
  3826. struct sde_kms *sde_kms = NULL;
  3827. struct sde_vm_ops *vm_ops;
  3828. if (!kms || !obj) {
  3829. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3830. return -EINVAL;
  3831. }
  3832. sde_kms = to_sde_kms(kms);
  3833. vm_ops = sde_vm_get_ops(sde_kms);
  3834. sde_vm_lock(sde_kms);
  3835. if (vm_ops && vm_ops->vm_owns_hw && !vm_ops->vm_owns_hw(sde_kms)) {
  3836. sde_vm_unlock(sde_kms);
  3837. DRM_INFO("HW is owned by other VM\n");
  3838. return -EACCES;
  3839. }
  3840. switch (obj->type) {
  3841. case DRM_MODE_OBJECT_CRTC:
  3842. crtc = obj_to_crtc(obj);
  3843. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3844. break;
  3845. case DRM_MODE_OBJECT_CONNECTOR:
  3846. conn = obj_to_connector(obj);
  3847. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3848. en);
  3849. break;
  3850. }
  3851. sde_vm_unlock(sde_kms);
  3852. return ret;
  3853. }
  3854. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3855. {
  3856. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3857. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3858. }