sde_plane.c 137 KB

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  1. /*
  2. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  52. /**
  53. * enum sde_plane_qos - Different qos configurations for each pipe
  54. *
  55. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  56. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  57. * this configuration is mutually exclusive from VBLANK_CTRL.
  58. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  59. */
  60. enum sde_plane_qos {
  61. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  62. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  63. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  64. };
  65. /*
  66. * struct sde_plane - local sde plane structure
  67. * @aspace: address space pointer
  68. * @csc_cfg: Decoded user configuration for csc
  69. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  70. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  71. * @mplane_list: List of multirect planes of the same pipe
  72. * @catalog: Points to sde catalog structure
  73. * @revalidate: force revalidation of all the plane properties
  74. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  75. * @blob_rot_caps: Pointer to rotator capability blob
  76. */
  77. struct sde_plane {
  78. struct drm_plane base;
  79. struct mutex lock;
  80. enum sde_sspp pipe;
  81. uint64_t features; /* capabilities from catalog */
  82. uint32_t perf_features; /* perf capabilities from catalog */
  83. uint32_t nformats;
  84. uint32_t formats[64];
  85. struct sde_hw_pipe *pipe_hw;
  86. struct sde_hw_pipe_cfg pipe_cfg;
  87. struct sde_hw_sharp_cfg sharp_cfg;
  88. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  89. uint32_t color_fill;
  90. bool is_error;
  91. bool is_rt_pipe;
  92. bool is_virtual;
  93. struct list_head mplane_list;
  94. struct sde_mdss_cfg *catalog;
  95. bool revalidate;
  96. bool xin_halt_forced_clk;
  97. struct sde_csc_cfg csc_cfg;
  98. struct sde_csc_cfg *csc_usr_ptr;
  99. struct sde_csc_cfg *csc_ptr;
  100. struct sde_hw_scaler3_cfg scaler3_cfg;
  101. struct sde_hw_pixel_ext pixel_ext;
  102. const struct sde_sspp_sub_blks *pipe_sblk;
  103. char pipe_name[SDE_NAME_SIZE];
  104. struct msm_property_info property_info;
  105. struct msm_property_data property_data[PLANE_PROP_COUNT];
  106. struct drm_property_blob *blob_info;
  107. struct drm_property_blob *blob_rot_caps;
  108. /* debugfs related stuff */
  109. struct dentry *debugfs_root;
  110. bool debugfs_default_scale;
  111. };
  112. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  113. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  114. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  115. {
  116. struct msm_drm_private *priv;
  117. if (!plane || !plane->dev)
  118. return NULL;
  119. priv = plane->dev->dev_private;
  120. if (!priv)
  121. return NULL;
  122. return to_sde_kms(priv->kms);
  123. }
  124. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  125. {
  126. struct drm_plane_state *pstate = NULL;
  127. struct drm_crtc *drm_crtc = NULL;
  128. struct sde_crtc *sde_crtc = NULL;
  129. struct sde_crtc_mixer *mixer = NULL;
  130. struct sde_hw_ctl *ctl = NULL;
  131. if (!plane) {
  132. DRM_ERROR("Invalid plane %pK\n", plane);
  133. return NULL;
  134. }
  135. pstate = plane->state;
  136. if (!pstate) {
  137. DRM_ERROR("Invalid plane state %pK\n", pstate);
  138. return NULL;
  139. }
  140. drm_crtc = pstate->crtc;
  141. if (!drm_crtc) {
  142. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  143. return NULL;
  144. }
  145. sde_crtc = to_sde_crtc(drm_crtc);
  146. if (!sde_crtc) {
  147. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  148. return NULL;
  149. }
  150. /* it will always return the first mixer and single CTL */
  151. mixer = sde_crtc->mixers;
  152. if (!mixer) {
  153. DRM_ERROR("invalid mixer %pK\n", mixer);
  154. return NULL;
  155. }
  156. ctl = mixer->hw_ctl;
  157. if (!mixer) {
  158. DRM_ERROR("invalid ctl %pK\n", ctl);
  159. return NULL;
  160. }
  161. return ctl;
  162. }
  163. static bool sde_plane_enabled(const struct drm_plane_state *state)
  164. {
  165. return state && state->fb && state->crtc;
  166. }
  167. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  168. {
  169. struct sde_plane *psde;
  170. if (!plane)
  171. return false;
  172. psde = to_sde_plane(plane);
  173. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  174. }
  175. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  176. enum sde_sspp_multirect_index rect_mode, bool enable)
  177. {
  178. struct sde_plane *psde;
  179. if (!plane)
  180. return;
  181. psde = to_sde_plane(plane);
  182. if (psde->pipe_hw->ops.set_src_split_order)
  183. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  184. rect_mode, enable);
  185. }
  186. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  187. {
  188. struct sde_plane *psde;
  189. struct sde_kms *sde_kms;
  190. struct msm_drm_private *priv;
  191. if (!plane || !plane->dev) {
  192. SDE_ERROR("invalid plane\n");
  193. return;
  194. }
  195. priv = plane->dev->dev_private;
  196. if (!priv || !priv->kms) {
  197. SDE_ERROR("invalid KMS reference\n");
  198. return;
  199. }
  200. sde_kms = to_sde_kms(priv->kms);
  201. psde = to_sde_plane(plane);
  202. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  203. }
  204. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  205. struct drm_crtc *crtc,
  206. struct drm_framebuffer *fb)
  207. {
  208. struct sde_plane *psde;
  209. const struct sde_format *fmt = NULL;
  210. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, index;
  211. struct sde_perf_cfg *perf;
  212. struct sde_plane_state *pstate;
  213. bool inline_rot = false;
  214. if (!plane || !fb) {
  215. SDE_ERROR("invalid arguments\n");
  216. return;
  217. }
  218. psde = to_sde_plane(plane);
  219. pstate = to_sde_plane_state(plane->state);
  220. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  221. SDE_ERROR("invalid arguments\n");
  222. return;
  223. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  224. return;
  225. }
  226. frame_rate = drm_mode_vrefresh(&crtc->mode);
  227. perf = &psde->catalog->perf;
  228. qos_count = perf->qos_refresh_count;
  229. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  230. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  231. (fps_index == qos_count - 1))
  232. break;
  233. fps_index++;
  234. }
  235. if (psde->is_rt_pipe) {
  236. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  237. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  238. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  239. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  240. else if (inline_rot)
  241. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  242. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  243. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  244. else
  245. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  246. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  247. if (psde->scaler3_cfg.enable)
  248. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  249. } else {
  250. lut_index = SDE_QOS_LUT_USAGE_NRT;
  251. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  252. }
  253. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  254. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  255. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  256. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  257. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  258. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  259. (fmt) ? fmt->base.pixel_format : 0,
  260. (fmt) ? fmt->fetch_mode : 0,
  261. psde->pipe_qos_cfg.danger_lut,
  262. psde->pipe_qos_cfg.safe_lut,
  263. psde->pipe_qos_cfg.creq_lut);
  264. SDE_DEBUG(
  265. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  266. plane->base.id,
  267. psde->pipe - SSPP_VIG0,
  268. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  269. fmt ? fmt->fetch_mode : -1,
  270. psde->pipe_qos_cfg.danger_lut,
  271. psde->pipe_qos_cfg.safe_lut,
  272. psde->pipe_qos_cfg.creq_lut);
  273. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  274. }
  275. /**
  276. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  277. * @plane: Pointer to drm plane
  278. * @enable: true to enable QoS control
  279. * @flags: QoS control mode (enum sde_plane_qos)
  280. */
  281. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  282. bool enable, u32 flags)
  283. {
  284. struct sde_plane *psde;
  285. if (!plane) {
  286. SDE_ERROR("invalid arguments\n");
  287. return;
  288. }
  289. psde = to_sde_plane(plane);
  290. if (!psde->pipe_hw || !psde->pipe_sblk) {
  291. SDE_ERROR("invalid arguments\n");
  292. return;
  293. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  294. return;
  295. }
  296. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  297. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  298. psde->pipe_qos_cfg.danger_vblank =
  299. psde->pipe_sblk->danger_vblank;
  300. psde->pipe_qos_cfg.vblank_en = enable;
  301. }
  302. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  303. /* this feature overrules previous VBLANK_CTRL */
  304. psde->pipe_qos_cfg.vblank_en = false;
  305. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  306. }
  307. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  308. psde->pipe_qos_cfg.danger_safe_en = enable;
  309. if (!psde->is_rt_pipe) {
  310. psde->pipe_qos_cfg.vblank_en = false;
  311. psde->pipe_qos_cfg.danger_safe_en = false;
  312. }
  313. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  314. plane->base.id,
  315. psde->pipe - SSPP_VIG0,
  316. psde->pipe_qos_cfg.danger_safe_en,
  317. psde->pipe_qos_cfg.vblank_en,
  318. psde->pipe_qos_cfg.creq_vblank,
  319. psde->pipe_qos_cfg.danger_vblank,
  320. psde->is_rt_pipe);
  321. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  322. &psde->pipe_qos_cfg);
  323. }
  324. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  325. {
  326. struct sde_plane *psde;
  327. if (!plane)
  328. return;
  329. psde = to_sde_plane(plane);
  330. psde->revalidate = enable;
  331. }
  332. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  333. {
  334. struct sde_plane *psde;
  335. int rc;
  336. if (!plane) {
  337. SDE_ERROR("invalid arguments\n");
  338. return -EINVAL;
  339. }
  340. psde = to_sde_plane(plane);
  341. if (!psde->is_rt_pipe)
  342. goto end;
  343. rc = pm_runtime_get_sync(plane->dev->dev);
  344. if (rc < 0) {
  345. SDE_ERROR("failed to enable power resource %d\n", rc);
  346. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  347. return rc;
  348. }
  349. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  350. pm_runtime_put_sync(plane->dev->dev);
  351. end:
  352. return 0;
  353. }
  354. /**
  355. * _sde_plane_set_ot_limit - set OT limit for the given plane
  356. * @plane: Pointer to drm plane
  357. * @crtc: Pointer to drm crtc
  358. */
  359. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  360. struct drm_crtc *crtc)
  361. {
  362. struct sde_plane *psde;
  363. struct sde_vbif_set_ot_params ot_params;
  364. struct msm_drm_private *priv;
  365. struct sde_kms *sde_kms;
  366. if (!plane || !plane->dev || !crtc) {
  367. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  368. !plane, !crtc);
  369. return;
  370. }
  371. priv = plane->dev->dev_private;
  372. if (!priv || !priv->kms) {
  373. SDE_ERROR("invalid KMS reference\n");
  374. return;
  375. }
  376. sde_kms = to_sde_kms(priv->kms);
  377. psde = to_sde_plane(plane);
  378. if (!psde->pipe_hw) {
  379. SDE_ERROR("invalid pipe reference\n");
  380. return;
  381. }
  382. memset(&ot_params, 0, sizeof(ot_params));
  383. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  384. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  385. ot_params.width = psde->pipe_cfg.src_rect.w;
  386. ot_params.height = psde->pipe_cfg.src_rect.h;
  387. ot_params.is_wfd = !psde->is_rt_pipe;
  388. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  389. ot_params.vbif_idx = VBIF_RT;
  390. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  391. ot_params.rd = true;
  392. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  393. }
  394. /**
  395. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  396. * @plane: Pointer to drm plane
  397. */
  398. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  399. {
  400. struct sde_plane *psde;
  401. struct sde_vbif_set_qos_params qos_params;
  402. struct msm_drm_private *priv;
  403. struct sde_kms *sde_kms;
  404. if (!plane || !plane->dev) {
  405. SDE_ERROR("invalid arguments\n");
  406. return;
  407. }
  408. priv = plane->dev->dev_private;
  409. if (!priv || !priv->kms) {
  410. SDE_ERROR("invalid KMS reference\n");
  411. return;
  412. }
  413. sde_kms = to_sde_kms(priv->kms);
  414. psde = to_sde_plane(plane);
  415. if (!psde->pipe_hw) {
  416. SDE_ERROR("invalid pipe reference\n");
  417. return;
  418. }
  419. memset(&qos_params, 0, sizeof(qos_params));
  420. qos_params.vbif_idx = VBIF_RT;
  421. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  422. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  423. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  424. qos_params.client_type = psde->is_rt_pipe ?
  425. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  426. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  427. plane->base.id, qos_params.num,
  428. qos_params.vbif_idx,
  429. qos_params.xin_id, qos_params.client_type,
  430. qos_params.clk_ctrl);
  431. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  432. }
  433. /**
  434. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  435. * @plane: Pointer to drm plane
  436. * @pstate: Pointer to sde plane state
  437. */
  438. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  439. struct sde_plane_state *pstate)
  440. {
  441. struct sde_plane *psde;
  442. struct sde_hw_pipe_ts_cfg cfg;
  443. struct msm_drm_private *priv;
  444. struct sde_kms *sde_kms;
  445. if (!plane || !plane->dev) {
  446. SDE_ERROR("invalid arguments");
  447. return;
  448. }
  449. priv = plane->dev->dev_private;
  450. if (!priv || !priv->kms) {
  451. SDE_ERROR("invalid KMS reference\n");
  452. return;
  453. }
  454. sde_kms = to_sde_kms(priv->kms);
  455. psde = to_sde_plane(plane);
  456. if (!psde->pipe_hw) {
  457. SDE_ERROR("invalid pipe reference\n");
  458. return;
  459. }
  460. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  461. return;
  462. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  463. memset(&cfg, 0, sizeof(cfg));
  464. cfg.size = sde_plane_get_property(pstate,
  465. PLANE_PROP_PREFILL_SIZE);
  466. cfg.time = sde_plane_get_property(pstate,
  467. PLANE_PROP_PREFILL_TIME);
  468. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  469. plane->base.id, cfg.size, cfg.time);
  470. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  471. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  472. pstate->multirect_index);
  473. }
  474. /* helper to update a state's input fence pointer from the property */
  475. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  476. struct sde_plane_state *pstate, uint64_t fd)
  477. {
  478. if (!psde || !pstate) {
  479. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  480. !psde, !pstate);
  481. return;
  482. }
  483. /* clear previous reference */
  484. if (pstate->input_fence)
  485. sde_sync_put(pstate->input_fence);
  486. /* get fence pointer for later */
  487. if (fd == 0)
  488. pstate->input_fence = NULL;
  489. else
  490. pstate->input_fence = sde_sync_get(fd);
  491. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  492. }
  493. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  494. {
  495. struct sde_plane *psde;
  496. struct sde_plane_state *pstate;
  497. uint32_t prefix;
  498. void *input_fence;
  499. int ret = -EINVAL;
  500. signed long rc;
  501. if (!plane) {
  502. SDE_ERROR("invalid plane\n");
  503. } else if (!plane->state) {
  504. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  505. } else {
  506. psde = to_sde_plane(plane);
  507. pstate = to_sde_plane_state(plane->state);
  508. input_fence = pstate->input_fence;
  509. if (input_fence) {
  510. prefix = sde_sync_get_name_prefix(input_fence);
  511. rc = sde_sync_wait(input_fence, wait_ms);
  512. switch (rc) {
  513. case 0:
  514. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  515. wait_ms, prefix, sde_plane_get_property(pstate,
  516. PLANE_PROP_INPUT_FENCE));
  517. psde->is_error = true;
  518. sde_kms_timeline_status(plane->dev);
  519. ret = -ETIMEDOUT;
  520. break;
  521. case -ERESTARTSYS:
  522. SDE_ERROR_PLANE(psde,
  523. "%ums wait interrupted on %08X\n",
  524. wait_ms, prefix);
  525. psde->is_error = true;
  526. ret = -ERESTARTSYS;
  527. break;
  528. case -EINVAL:
  529. SDE_ERROR_PLANE(psde,
  530. "invalid fence param for %08X\n",
  531. prefix);
  532. psde->is_error = true;
  533. ret = -EINVAL;
  534. break;
  535. case -EBADF:
  536. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  537. plane->base.id,
  538. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  539. psde->is_error = true;
  540. ret = 0;
  541. break;
  542. default:
  543. SDE_DEBUG_PLANE(psde, "signaled\n");
  544. ret = 0;
  545. break;
  546. }
  547. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  548. } else {
  549. ret = 0;
  550. }
  551. }
  552. return ret;
  553. }
  554. /**
  555. * _sde_plane_get_aspace: gets the address space based on the
  556. * fb_translation mode property
  557. */
  558. static int _sde_plane_get_aspace(
  559. struct sde_plane *psde,
  560. struct sde_plane_state *pstate,
  561. struct msm_gem_address_space **aspace)
  562. {
  563. struct sde_kms *kms;
  564. int mode;
  565. if (!psde || !pstate || !aspace) {
  566. SDE_ERROR("invalid parameters\n");
  567. return -EINVAL;
  568. }
  569. kms = _sde_plane_get_kms(&psde->base);
  570. if (!kms) {
  571. SDE_ERROR("invalid kms\n");
  572. return -EINVAL;
  573. }
  574. mode = sde_plane_get_property(pstate,
  575. PLANE_PROP_FB_TRANSLATION_MODE);
  576. switch (mode) {
  577. case SDE_DRM_FB_NON_SEC:
  578. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  579. if (!aspace)
  580. return -EINVAL;
  581. break;
  582. case SDE_DRM_FB_SEC:
  583. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  584. if (!aspace)
  585. return -EINVAL;
  586. break;
  587. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  588. case SDE_DRM_FB_SEC_DIR_TRANS:
  589. *aspace = NULL;
  590. break;
  591. default:
  592. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  593. return -EFAULT;
  594. }
  595. return 0;
  596. }
  597. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  598. struct sde_plane_state *pstate,
  599. struct sde_hw_pipe_cfg *pipe_cfg,
  600. struct drm_framebuffer *fb)
  601. {
  602. struct sde_plane *psde;
  603. struct msm_gem_address_space *aspace = NULL;
  604. int ret, mode;
  605. bool secure = false;
  606. if (!plane || !pstate || !pipe_cfg || !fb) {
  607. SDE_ERROR(
  608. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  609. !plane, !pstate, !pipe_cfg, !fb);
  610. return;
  611. }
  612. psde = to_sde_plane(plane);
  613. if (!psde->pipe_hw) {
  614. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  615. return;
  616. }
  617. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  618. if (ret) {
  619. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  620. return;
  621. }
  622. /*
  623. * framebuffer prepare is deferred for prepare_fb calls that
  624. * happen during the transition from secure to non-secure.
  625. * Handle the prepare at this point for such cases. This can be
  626. * expected for one or two frames during the transition.
  627. */
  628. if (aspace && pstate->defer_prepare_fb) {
  629. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  630. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  631. if (ret) {
  632. SDE_ERROR_PLANE(psde,
  633. "failed to prepare framebuffer %d\n", ret);
  634. return;
  635. }
  636. pstate->defer_prepare_fb = false;
  637. }
  638. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  639. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  640. secure = true;
  641. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  642. if (ret == -EAGAIN)
  643. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  644. else if (ret) {
  645. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  646. /*
  647. * Force solid fill color on error. This is to prevent
  648. * smmu faults during secure session transition.
  649. */
  650. psde->is_error = true;
  651. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  652. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  653. pipe_cfg->layout.width,
  654. pipe_cfg->layout.height,
  655. pipe_cfg->layout.plane_addr[0],
  656. pipe_cfg->layout.plane_size[0],
  657. pipe_cfg->layout.plane_addr[1],
  658. pipe_cfg->layout.plane_size[1],
  659. pipe_cfg->layout.plane_addr[2],
  660. pipe_cfg->layout.plane_size[2],
  661. pipe_cfg->layout.plane_addr[3],
  662. pipe_cfg->layout.plane_size[3],
  663. pstate->multirect_index,
  664. secure);
  665. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  666. pstate->multirect_index);
  667. }
  668. }
  669. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  670. struct sde_plane_state *pstate)
  671. {
  672. struct sde_hw_scaler3_cfg *cfg;
  673. int ret = 0;
  674. if (!psde || !pstate) {
  675. SDE_ERROR("invalid args\n");
  676. return -EINVAL;
  677. }
  678. cfg = &psde->scaler3_cfg;
  679. cfg->dir_lut = msm_property_get_blob(
  680. &psde->property_info,
  681. &pstate->property_state, &cfg->dir_len,
  682. PLANE_PROP_SCALER_LUT_ED);
  683. cfg->cir_lut = msm_property_get_blob(
  684. &psde->property_info,
  685. &pstate->property_state, &cfg->cir_len,
  686. PLANE_PROP_SCALER_LUT_CIR);
  687. cfg->sep_lut = msm_property_get_blob(
  688. &psde->property_info,
  689. &pstate->property_state, &cfg->sep_len,
  690. PLANE_PROP_SCALER_LUT_SEP);
  691. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  692. ret = -ENODATA;
  693. return ret;
  694. }
  695. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  696. struct sde_plane_state *pstate)
  697. {
  698. struct sde_hw_scaler3_cfg *cfg;
  699. cfg = &psde->scaler3_cfg;
  700. cfg->sep_lut = msm_property_get_blob(
  701. &psde->property_info,
  702. &pstate->property_state, &cfg->sep_len,
  703. PLANE_PROP_SCALER_LUT_SEP);
  704. return cfg->sep_lut ? 0 : -ENODATA;
  705. }
  706. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  707. struct sde_plane_state *pstate, const struct sde_format *fmt,
  708. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  709. {
  710. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  711. struct sde_hw_scaler3_cfg *scale_cfg;
  712. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  713. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  714. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  715. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  716. chroma_subsmpl_h, chroma_subsmpl_v);
  717. return;
  718. }
  719. scale_cfg = &psde->scaler3_cfg;
  720. src_w = psde->pipe_cfg.src_rect.w;
  721. src_h = psde->pipe_cfg.src_rect.h;
  722. dst_w = psde->pipe_cfg.dst_rect.w;
  723. dst_h = psde->pipe_cfg.dst_rect.h;
  724. memset(scale_cfg, 0, sizeof(*scale_cfg));
  725. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  726. /*
  727. * For inline rotation cases, scaler config is post-rotation,
  728. * so swap the dimensions here. However, pixel extension will
  729. * need pre-rotation settings, this will be corrected below
  730. * when calculating pixel extension settings.
  731. */
  732. if (inline_rotation)
  733. swap(src_w, src_h);
  734. decimated = DECIMATED_DIMENSION(src_w,
  735. psde->pipe_cfg.horz_decimation);
  736. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  737. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  738. decimated = DECIMATED_DIMENSION(src_h,
  739. psde->pipe_cfg.vert_decimation);
  740. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  741. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  742. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  744. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  745. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  746. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  748. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  749. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  751. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  753. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  754. for (i = 0; i < SDE_MAX_PLANES; i++) {
  755. /*
  756. * For inline rotation cases with pre-downscaling enabled
  757. * set x pre-downscale value if required. Only x direction
  758. * is currently supported. Use src_h as values have been swapped
  759. * and x direction corresponds to height value.
  760. */
  761. src_h_pre_down = src_h;
  762. if (pre_down_supported && inline_rotation) {
  763. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  764. src_h_pre_down = src_h / 2;
  765. }
  766. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  767. psde->pipe_cfg.horz_decimation);
  768. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  769. psde->pipe_cfg.vert_decimation);
  770. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  771. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  772. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  773. }
  774. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  775. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  776. /* For pixel extension we need the pre-rotated orientation */
  777. if (inline_rotation) {
  778. psde->pixel_ext.num_ext_pxls_top[i] =
  779. scale_cfg->src_width[i];
  780. psde->pixel_ext.num_ext_pxls_left[i] =
  781. scale_cfg->src_height[i];
  782. } else {
  783. psde->pixel_ext.num_ext_pxls_top[i] =
  784. scale_cfg->src_height[i];
  785. psde->pixel_ext.num_ext_pxls_left[i] =
  786. scale_cfg->src_width[i];
  787. }
  788. }
  789. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  790. && (src_w == dst_w) && !inline_rotation) ||
  791. pstate->multirect_mode)
  792. return;
  793. SDE_DEBUG_PLANE(psde,
  794. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  795. src_w, src_h, dst_w, dst_h,
  796. chroma_subsmpl_v, chroma_subsmpl_h,
  797. fmt->base.pixel_format);
  798. scale_cfg->dst_width = dst_w;
  799. scale_cfg->dst_height = dst_h;
  800. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  801. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  802. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  803. scale_cfg->lut_flag = 0;
  804. scale_cfg->blend_cfg = 1;
  805. scale_cfg->enable = 1;
  806. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  807. }
  808. /**
  809. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  810. * @psde: Pointer to SDE plane object
  811. * @src: Source size
  812. * @dst: Destination size
  813. * @phase_steps: Pointer to output array for phase steps
  814. * @filter: Pointer to output array for filter type
  815. * @fmt: Pointer to format definition
  816. * @chroma_subsampling: Subsampling amount for chroma channel
  817. *
  818. * Returns: 0 on success
  819. */
  820. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  821. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  822. enum sde_hw_filter *filter, const struct sde_format *fmt,
  823. uint32_t chroma_subsampling)
  824. {
  825. if (!psde || !phase_steps || !filter || !fmt) {
  826. SDE_ERROR(
  827. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  828. !psde, !phase_steps, !filter, !fmt);
  829. return -EINVAL;
  830. }
  831. /* calculate phase steps, leave init phase as zero */
  832. phase_steps[SDE_SSPP_COMP_0] =
  833. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  834. phase_steps[SDE_SSPP_COMP_1_2] =
  835. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  836. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  837. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  838. /* calculate scaler config, if necessary */
  839. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  840. filter[SDE_SSPP_COMP_3] =
  841. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  842. SDE_SCALE_FILTER_PCMN;
  843. if (SDE_FORMAT_IS_YUV(fmt)) {
  844. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  845. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  846. } else {
  847. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  848. filter[SDE_SSPP_COMP_1_2] =
  849. SDE_SCALE_FILTER_NEAREST;
  850. }
  851. } else {
  852. /* disable scaler */
  853. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  854. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  855. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  856. }
  857. return 0;
  858. }
  859. /**
  860. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  861. * @psde: Pointer to SDE plane object
  862. * @src: Source size
  863. * @dst: Destination size
  864. * @decimated_src: Source size after decimation, if any
  865. * @phase_steps: Pointer to output array for phase steps
  866. * @out_src: Output array for pixel extension values
  867. * @out_edge1: Output array for pixel extension first edge
  868. * @out_edge2: Output array for pixel extension second edge
  869. * @filter: Pointer to array for filter type
  870. * @fmt: Pointer to format definition
  871. * @chroma_subsampling: Subsampling amount for chroma channel
  872. * @post_compare: Whether to chroma subsampled source size for comparisions
  873. */
  874. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  875. uint32_t src, uint32_t dst, uint32_t decimated_src,
  876. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  877. int *out_edge2, enum sde_hw_filter *filter,
  878. const struct sde_format *fmt, uint32_t chroma_subsampling,
  879. bool post_compare)
  880. {
  881. int64_t edge1, edge2, caf;
  882. uint32_t src_work;
  883. int i, tmp;
  884. if (psde && phase_steps && out_src && out_edge1 &&
  885. out_edge2 && filter && fmt) {
  886. /* handle CAF for YUV formats */
  887. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  888. caf = PHASE_STEP_UNIT_SCALE;
  889. else
  890. caf = 0;
  891. for (i = 0; i < SDE_MAX_PLANES; i++) {
  892. src_work = decimated_src;
  893. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  894. src_work /= chroma_subsampling;
  895. if (post_compare)
  896. src = src_work;
  897. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  898. /* unity */
  899. edge1 = 0;
  900. edge2 = 0;
  901. } else if (dst >= src) {
  902. /* upscale */
  903. edge1 = (1 << PHASE_RESIDUAL);
  904. edge1 -= caf;
  905. edge2 = (1 << PHASE_RESIDUAL);
  906. edge2 += (dst - 1) * *(phase_steps + i);
  907. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  908. edge2 += caf;
  909. edge2 = -(edge2);
  910. } else {
  911. /* downscale */
  912. edge1 = 0;
  913. edge2 = (dst - 1) * *(phase_steps + i);
  914. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  915. edge2 += *(phase_steps + i);
  916. edge2 = -(edge2);
  917. }
  918. /* only enable CAF for luma plane */
  919. caf = 0;
  920. /* populate output arrays */
  921. *(out_src + i) = src_work;
  922. /* edge updates taken from __pxl_extn_helper */
  923. if (edge1 >= 0) {
  924. tmp = (uint32_t)edge1;
  925. tmp >>= PHASE_STEP_SHIFT;
  926. *(out_edge1 + i) = -tmp;
  927. } else {
  928. tmp = (uint32_t)(-edge1);
  929. *(out_edge1 + i) =
  930. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  931. PHASE_STEP_SHIFT;
  932. }
  933. if (edge2 >= 0) {
  934. tmp = (uint32_t)edge2;
  935. tmp >>= PHASE_STEP_SHIFT;
  936. *(out_edge2 + i) = -tmp;
  937. } else {
  938. tmp = (uint32_t)(-edge2);
  939. *(out_edge2 + i) =
  940. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  941. PHASE_STEP_SHIFT;
  942. }
  943. }
  944. }
  945. }
  946. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  947. {
  948. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  949. {
  950. /* S15.16 format */
  951. 0x00012A00, 0x00000000, 0x00019880,
  952. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  953. 0x00012A00, 0x00020480, 0x00000000,
  954. },
  955. /* signed bias */
  956. { 0xfff0, 0xff80, 0xff80,},
  957. { 0x0, 0x0, 0x0,},
  958. /* unsigned clamp */
  959. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  960. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  961. };
  962. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  963. {
  964. /* S15.16 format */
  965. 0x00012A00, 0x00000000, 0x00019880,
  966. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  967. 0x00012A00, 0x00020480, 0x00000000,
  968. },
  969. /* signed bias */
  970. { 0xffc0, 0xfe00, 0xfe00,},
  971. { 0x0, 0x0, 0x0,},
  972. /* unsigned clamp */
  973. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  974. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  975. };
  976. if (!psde) {
  977. SDE_ERROR("invalid plane\n");
  978. return;
  979. }
  980. /* revert to kernel default if override not available */
  981. if (psde->csc_usr_ptr)
  982. psde->csc_ptr = psde->csc_usr_ptr;
  983. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  984. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  985. else
  986. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  987. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  988. psde->csc_ptr->csc_mv[0],
  989. psde->csc_ptr->csc_mv[1],
  990. psde->csc_ptr->csc_mv[2]);
  991. }
  992. static void sde_color_process_plane_setup(struct drm_plane *plane)
  993. {
  994. struct sde_plane *psde;
  995. struct sde_plane_state *pstate;
  996. uint32_t hue, saturation, value, contrast;
  997. struct drm_msm_memcol *memcol = NULL;
  998. struct drm_msm_3d_gamut *vig_gamut = NULL;
  999. struct drm_msm_igc_lut *igc = NULL;
  1000. struct drm_msm_pgc_lut *gc = NULL;
  1001. size_t memcol_sz = 0, size = 0;
  1002. struct sde_hw_cp_cfg hw_cfg = {};
  1003. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1004. bool fp16_igc, fp16_unmult;
  1005. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1006. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1007. psde = to_sde_plane(plane);
  1008. pstate = to_sde_plane_state(plane->state);
  1009. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1010. if (psde->pipe_hw->ops.setup_pa_hue)
  1011. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1012. saturation = (uint32_t) sde_plane_get_property(pstate,
  1013. PLANE_PROP_SATURATION_ADJUST);
  1014. if (psde->pipe_hw->ops.setup_pa_sat)
  1015. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1016. value = (uint32_t) sde_plane_get_property(pstate,
  1017. PLANE_PROP_VALUE_ADJUST);
  1018. if (psde->pipe_hw->ops.setup_pa_val)
  1019. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1020. contrast = (uint32_t) sde_plane_get_property(pstate,
  1021. PLANE_PROP_CONTRAST_ADJUST);
  1022. if (psde->pipe_hw->ops.setup_pa_cont)
  1023. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1024. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1025. /* Skin memory color setup */
  1026. memcol = msm_property_get_blob(&psde->property_info,
  1027. &pstate->property_state,
  1028. &memcol_sz,
  1029. PLANE_PROP_SKIN_COLOR);
  1030. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1031. MEMCOLOR_SKIN, memcol);
  1032. /* Sky memory color setup */
  1033. memcol = msm_property_get_blob(&psde->property_info,
  1034. &pstate->property_state,
  1035. &memcol_sz,
  1036. PLANE_PROP_SKY_COLOR);
  1037. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1038. MEMCOLOR_SKY, memcol);
  1039. /* Foliage memory color setup */
  1040. memcol = msm_property_get_blob(&psde->property_info,
  1041. &pstate->property_state,
  1042. &memcol_sz,
  1043. PLANE_PROP_FOLIAGE_COLOR);
  1044. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1045. MEMCOLOR_FOLIAGE, memcol);
  1046. }
  1047. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1048. psde->pipe_hw->ops.setup_vig_gamut) {
  1049. vig_gamut = msm_property_get_blob(&psde->property_info,
  1050. &pstate->property_state,
  1051. &size,
  1052. PLANE_PROP_VIG_GAMUT);
  1053. hw_cfg.last_feature = 0;
  1054. hw_cfg.ctl = ctl;
  1055. hw_cfg.len = size;
  1056. hw_cfg.payload = vig_gamut;
  1057. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1058. }
  1059. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1060. psde->pipe_hw->ops.setup_vig_igc) {
  1061. igc = msm_property_get_blob(&psde->property_info,
  1062. &pstate->property_state,
  1063. &size,
  1064. PLANE_PROP_VIG_IGC);
  1065. hw_cfg.last_feature = 0;
  1066. hw_cfg.ctl = ctl;
  1067. hw_cfg.len = size;
  1068. hw_cfg.payload = igc;
  1069. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1070. }
  1071. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1072. psde->pipe_hw->ops.setup_dma_igc) {
  1073. igc = msm_property_get_blob(&psde->property_info,
  1074. &pstate->property_state,
  1075. &size,
  1076. PLANE_PROP_DMA_IGC);
  1077. hw_cfg.last_feature = 0;
  1078. hw_cfg.ctl = ctl;
  1079. hw_cfg.len = size;
  1080. hw_cfg.payload = igc;
  1081. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1082. pstate->multirect_index);
  1083. }
  1084. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1085. psde->pipe_hw->ops.setup_dma_gc) {
  1086. gc = msm_property_get_blob(&psde->property_info,
  1087. &pstate->property_state,
  1088. &size,
  1089. PLANE_PROP_DMA_GC);
  1090. hw_cfg.last_feature = 0;
  1091. hw_cfg.ctl = ctl;
  1092. hw_cfg.len = size;
  1093. hw_cfg.payload = gc;
  1094. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1095. pstate->multirect_index);
  1096. }
  1097. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1098. psde->pipe_hw->ops.setup_fp16_igc) {
  1099. fp16_igc = !!sde_plane_get_property(pstate,
  1100. PLANE_PROP_FP16_IGC);
  1101. hw_cfg.last_feature = 0;
  1102. hw_cfg.ctl = ctl;
  1103. hw_cfg.len = sizeof(bool);
  1104. hw_cfg.payload = &fp16_igc;
  1105. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1106. pstate->multirect_index, &hw_cfg);
  1107. }
  1108. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1109. psde->pipe_hw->ops.setup_fp16_gc) {
  1110. fp16_gc = msm_property_get_blob(&psde->property_info,
  1111. &pstate->property_state,
  1112. &size,
  1113. PLANE_PROP_FP16_GC);
  1114. hw_cfg.last_feature = 0;
  1115. hw_cfg.ctl = ctl;
  1116. hw_cfg.len = size;
  1117. hw_cfg.payload = fp16_gc;
  1118. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1119. pstate->multirect_index, &hw_cfg);
  1120. }
  1121. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1122. psde->pipe_hw->ops.setup_fp16_csc) {
  1123. fp16_csc = msm_property_get_blob(&psde->property_info,
  1124. &pstate->property_state,
  1125. &size,
  1126. PLANE_PROP_FP16_CSC);
  1127. hw_cfg.last_feature = 0;
  1128. hw_cfg.ctl = ctl;
  1129. hw_cfg.len = size;
  1130. hw_cfg.payload = fp16_csc;
  1131. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1132. pstate->multirect_index, &hw_cfg);
  1133. }
  1134. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1135. psde->pipe_hw->ops.setup_fp16_unmult) {
  1136. fp16_unmult = !!sde_plane_get_property(pstate,
  1137. PLANE_PROP_FP16_UNMULT);
  1138. hw_cfg.last_feature = 0;
  1139. hw_cfg.ctl = ctl;
  1140. hw_cfg.len = sizeof(bool);
  1141. hw_cfg.payload = &fp16_unmult;
  1142. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1143. pstate->multirect_index, &hw_cfg);
  1144. }
  1145. }
  1146. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1147. struct sde_plane_state *pstate,
  1148. const struct sde_format *fmt, bool color_fill)
  1149. {
  1150. struct sde_hw_pixel_ext *pe;
  1151. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1152. const struct drm_format_info *info = NULL;
  1153. if (!psde || !fmt || !pstate) {
  1154. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1155. !psde, !fmt, !pstate);
  1156. return;
  1157. }
  1158. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1159. sizeof(psde->scaler3_cfg));
  1160. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1161. sizeof(psde->pixel_ext));
  1162. info = drm_format_info(fmt->base.pixel_format);
  1163. pe = &psde->pixel_ext;
  1164. psde->pipe_cfg.horz_decimation =
  1165. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1166. psde->pipe_cfg.vert_decimation =
  1167. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1168. /* don't chroma subsample if decimating */
  1169. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1170. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1171. /* update scaler */
  1172. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1173. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1174. int rc = -EINVAL;
  1175. if (!color_fill && !psde->debugfs_default_scale)
  1176. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1177. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1178. _sde_plane_setup_scaler3_lut(psde, pstate);
  1179. if (rc || pstate->scaler_check_state !=
  1180. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1181. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1182. pstate->scaler_check_state,
  1183. psde->debugfs_default_scale, rc,
  1184. psde->pipe_cfg.src_rect.w,
  1185. psde->pipe_cfg.src_rect.h,
  1186. psde->pipe_cfg.dst_rect.w,
  1187. psde->pipe_cfg.dst_rect.h,
  1188. pstate->multirect_mode);
  1189. /* calculate default config for QSEED3 */
  1190. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1191. chroma_subsmpl_h, chroma_subsmpl_v);
  1192. }
  1193. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1194. color_fill || psde->debugfs_default_scale) {
  1195. uint32_t deci_dim, i;
  1196. /* calculate default configuration for QSEED2 */
  1197. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1198. SDE_DEBUG_PLANE(psde, "default config\n");
  1199. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1200. psde->pipe_cfg.horz_decimation);
  1201. _sde_plane_setup_scaler2(psde,
  1202. deci_dim,
  1203. psde->pipe_cfg.dst_rect.w,
  1204. pe->phase_step_x,
  1205. pe->horz_filter, fmt, chroma_subsmpl_h);
  1206. if (SDE_FORMAT_IS_YUV(fmt))
  1207. deci_dim &= ~0x1;
  1208. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1209. psde->pipe_cfg.dst_rect.w, deci_dim,
  1210. pe->phase_step_x,
  1211. pe->roi_w,
  1212. pe->num_ext_pxls_left,
  1213. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1214. chroma_subsmpl_h, 0);
  1215. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1216. psde->pipe_cfg.vert_decimation);
  1217. _sde_plane_setup_scaler2(psde,
  1218. deci_dim,
  1219. psde->pipe_cfg.dst_rect.h,
  1220. pe->phase_step_y,
  1221. pe->vert_filter, fmt, chroma_subsmpl_v);
  1222. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1223. psde->pipe_cfg.dst_rect.h, deci_dim,
  1224. pe->phase_step_y,
  1225. pe->roi_h,
  1226. pe->num_ext_pxls_top,
  1227. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1228. chroma_subsmpl_v, 1);
  1229. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1230. if (pe->num_ext_pxls_left[i] >= 0)
  1231. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1232. else
  1233. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1234. if (pe->num_ext_pxls_right[i] >= 0)
  1235. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1236. else
  1237. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1238. if (pe->num_ext_pxls_top[i] >= 0)
  1239. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1240. else
  1241. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1242. if (pe->num_ext_pxls_btm[i] >= 0)
  1243. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1244. else
  1245. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1246. }
  1247. }
  1248. if (psde->pipe_hw->ops.setup_pre_downscale)
  1249. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1250. &pstate->pre_down);
  1251. }
  1252. /**
  1253. * _sde_plane_color_fill - enables color fill on plane
  1254. * @psde: Pointer to SDE plane object
  1255. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1256. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1257. * Returns: 0 on success
  1258. */
  1259. static int _sde_plane_color_fill(struct sde_plane *psde,
  1260. uint32_t color, uint32_t alpha)
  1261. {
  1262. const struct sde_format *fmt;
  1263. const struct drm_plane *plane;
  1264. struct sde_plane_state *pstate;
  1265. bool blend_enable = true;
  1266. if (!psde || !psde->base.state) {
  1267. SDE_ERROR("invalid plane\n");
  1268. return -EINVAL;
  1269. }
  1270. if (!psde->pipe_hw) {
  1271. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1272. return -EINVAL;
  1273. }
  1274. plane = &psde->base;
  1275. pstate = to_sde_plane_state(plane->state);
  1276. SDE_DEBUG_PLANE(psde, "\n");
  1277. /*
  1278. * select fill format to match user property expectation,
  1279. * h/w only supports RGB variants
  1280. */
  1281. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1282. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1283. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1284. /* update sspp */
  1285. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1286. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1287. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1288. pstate->multirect_index);
  1289. /* override scaler/decimation if solid fill */
  1290. psde->pipe_cfg.src_rect.x = 0;
  1291. psde->pipe_cfg.src_rect.y = 0;
  1292. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1293. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1294. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1295. if (psde->pipe_hw->ops.setup_format)
  1296. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1297. fmt, blend_enable,
  1298. SDE_SSPP_SOLID_FILL,
  1299. pstate->multirect_index);
  1300. if (psde->pipe_hw->ops.setup_rects)
  1301. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1302. &psde->pipe_cfg,
  1303. pstate->multirect_index);
  1304. if (psde->pipe_hw->ops.setup_pe)
  1305. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1306. &psde->pixel_ext);
  1307. if (psde->pipe_hw->ops.setup_scaler &&
  1308. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1309. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1310. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1311. &psde->pipe_cfg, &psde->pixel_ext,
  1312. &psde->scaler3_cfg);
  1313. }
  1314. }
  1315. return 0;
  1316. }
  1317. /**
  1318. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1319. * @plane: Pointer to drm plane
  1320. * @state: Pointer to drm plane state to be validated
  1321. * return: 0 if success; error code otherwise
  1322. */
  1323. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1324. struct drm_plane_state *state)
  1325. {
  1326. struct sde_plane *psde;
  1327. struct sde_plane_state *pstate, *old_pstate;
  1328. int ret = 0;
  1329. u32 rotation;
  1330. if (!plane || !state) {
  1331. SDE_ERROR("invalid plane/state\n");
  1332. return -EINVAL;
  1333. }
  1334. psde = to_sde_plane(plane);
  1335. pstate = to_sde_plane_state(state);
  1336. old_pstate = to_sde_plane_state(plane->state);
  1337. /* check inline rotation and simplify the transform */
  1338. rotation = drm_rotation_simplify(
  1339. state->rotation,
  1340. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1341. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1342. if ((rotation & DRM_MODE_ROTATE_180) ||
  1343. (rotation & DRM_MODE_ROTATE_270)) {
  1344. SDE_ERROR_PLANE(psde,
  1345. "invalid rotation transform must be simplified 0x%x\n",
  1346. rotation);
  1347. ret = -EINVAL;
  1348. goto exit;
  1349. }
  1350. if (rotation & DRM_MODE_ROTATE_90) {
  1351. struct msm_drm_private *priv = plane->dev->dev_private;
  1352. struct sde_kms *sde_kms;
  1353. const struct msm_format *msm_fmt;
  1354. const struct sde_format *fmt;
  1355. struct sde_rect src;
  1356. bool q16_data = true;
  1357. POPULATE_RECT(&src, state->src_x, state->src_y,
  1358. state->src_w, state->src_h, q16_data);
  1359. /*
  1360. * DRM framework expects rotation flag in counter-clockwise
  1361. * direction and the HW expects in clockwise direction.
  1362. * Flip the flags to match with HW.
  1363. */
  1364. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1365. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1366. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1367. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1368. !psde->pipe_sblk->in_rot_maxheight ||
  1369. !psde->pipe_sblk->in_rot_format_list ||
  1370. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1371. SDE_ERROR_PLANE(psde,
  1372. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1373. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1374. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1375. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1376. !psde->pipe_sblk->in_rot_format_list,
  1377. !psde->pipe_sblk->in_rot_maxheight,
  1378. psde->features);
  1379. ret = -EINVAL;
  1380. goto exit;
  1381. }
  1382. /* check for valid height */
  1383. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1384. SDE_ERROR_PLANE(psde,
  1385. "invalid height for inline rot:%d max:%d\n",
  1386. src.h, psde->pipe_sblk->in_rot_maxheight);
  1387. ret = -EINVAL;
  1388. goto exit;
  1389. }
  1390. if (!sde_plane_enabled(state))
  1391. goto exit;
  1392. /* check for valid formats supported by inline rot */
  1393. sde_kms = to_sde_kms(priv->kms);
  1394. msm_fmt = msm_framebuffer_format(state->fb);
  1395. fmt = to_sde_format(msm_fmt);
  1396. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1397. psde->pipe_sblk->in_rot_format_list);
  1398. }
  1399. exit:
  1400. pstate->rotation = rotation;
  1401. return ret;
  1402. }
  1403. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1404. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1405. {
  1406. struct sde_plane *psde;
  1407. struct msm_drm_private *priv;
  1408. struct sde_vbif_set_xin_halt_params halt_params;
  1409. if (!plane || !plane->dev) {
  1410. SDE_ERROR("invalid arguments\n");
  1411. return false;
  1412. }
  1413. psde = to_sde_plane(plane);
  1414. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1415. SDE_ERROR("invalid pipe reference\n");
  1416. return false;
  1417. }
  1418. priv = plane->dev->dev_private;
  1419. if (!priv || !priv->kms) {
  1420. SDE_ERROR("invalid KMS reference\n");
  1421. return false;
  1422. }
  1423. memset(&halt_params, 0, sizeof(halt_params));
  1424. halt_params.vbif_idx = VBIF_RT;
  1425. halt_params.xin_id = xin_id;
  1426. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1427. halt_params.forced_on = halt_forced_clk;
  1428. halt_params.enable = enable;
  1429. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1430. }
  1431. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1432. {
  1433. struct sde_plane *psde;
  1434. if (!plane) {
  1435. SDE_ERROR("invalid plane\n");
  1436. return;
  1437. }
  1438. psde = to_sde_plane(plane);
  1439. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1440. SDE_ERROR("invalid pipe reference\n");
  1441. return;
  1442. }
  1443. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1444. psde->xin_halt_forced_clk =
  1445. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1446. psde->xin_halt_forced_clk, enable);
  1447. }
  1448. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1449. struct drm_crtc *crtc)
  1450. {
  1451. struct sde_plane *psde;
  1452. if (!plane || !crtc) {
  1453. SDE_ERROR("invalid plane/crtc\n");
  1454. return;
  1455. }
  1456. psde = to_sde_plane(plane);
  1457. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1458. return;
  1459. /* do all VBIF programming for the sec-ui allowed SSPP */
  1460. _sde_plane_set_qos_remap(plane);
  1461. _sde_plane_set_ot_limit(plane, crtc);
  1462. }
  1463. /**
  1464. * sde_plane_rot_install_properties - install plane rotator properties
  1465. * @plane: Pointer to drm plane
  1466. * @catalog: Pointer to mdss configuration
  1467. * return: none
  1468. */
  1469. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1470. struct sde_mdss_cfg *catalog)
  1471. {
  1472. struct sde_plane *psde = to_sde_plane(plane);
  1473. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1474. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1475. int ret = 0;
  1476. if (!plane || !psde) {
  1477. SDE_ERROR("invalid plane\n");
  1478. return;
  1479. } else if (!catalog) {
  1480. SDE_ERROR("invalid catalog\n");
  1481. return;
  1482. }
  1483. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1484. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1485. ret = drm_plane_create_rotation_property(plane,
  1486. DRM_MODE_ROTATE_0, supported_rotations);
  1487. if (ret) {
  1488. DRM_ERROR("create rotation property failed: %d\n", ret);
  1489. return;
  1490. }
  1491. }
  1492. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1493. {
  1494. struct sde_plane_state *pstate;
  1495. if (!drm_state)
  1496. return;
  1497. pstate = to_sde_plane_state(drm_state);
  1498. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1499. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1500. }
  1501. /**
  1502. * multi_rect validate API allows to validate only R0 and R1 RECT
  1503. * passing for each plane. Client of this API must not pass multiple
  1504. * plane which are not sharing same XIN client. Such calls will fail
  1505. * even though kernel client is passing valid multirect configuration.
  1506. */
  1507. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1508. {
  1509. struct sde_plane_state *pstate[R_MAX];
  1510. const struct drm_plane_state *drm_state[R_MAX];
  1511. struct sde_rect src[R_MAX], dst[R_MAX];
  1512. struct sde_plane *sde_plane[R_MAX];
  1513. const struct sde_format *fmt[R_MAX];
  1514. int xin_id[R_MAX];
  1515. bool q16_data = true;
  1516. int i, j, buffer_lines, width_threshold[R_MAX];
  1517. unsigned int max_tile_height = 1;
  1518. bool parallel_fetch_qualified = true;
  1519. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1520. const struct msm_format *msm_fmt;
  1521. bool const_alpha_enable = true;
  1522. for (i = 0; i < R_MAX; i++) {
  1523. drm_state[i] = i ? plane->r1 : plane->r0;
  1524. if (!drm_state[i]) {
  1525. SDE_ERROR("drm plane state is NULL\n");
  1526. return -EINVAL;
  1527. }
  1528. pstate[i] = to_sde_plane_state(drm_state[i]);
  1529. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1530. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1531. for (j = 0; j < i; j++) {
  1532. if (xin_id[i] != xin_id[j]) {
  1533. SDE_ERROR_PLANE(sde_plane[i],
  1534. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1535. j, xin_id[j], i, xin_id[i]);
  1536. return -EINVAL;
  1537. }
  1538. }
  1539. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1540. if (!msm_fmt) {
  1541. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1542. return -EINVAL;
  1543. }
  1544. fmt[i] = to_sde_format(msm_fmt);
  1545. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1546. (fmt[i]->tile_height > max_tile_height))
  1547. max_tile_height = fmt[i]->tile_height;
  1548. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1549. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1550. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1551. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1552. drm_state[i]->crtc_h, !q16_data);
  1553. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1554. SDE_ERROR_PLANE(sde_plane[i],
  1555. "scaling is not supported in multirect mode\n");
  1556. return -EINVAL;
  1557. }
  1558. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1559. SDE_ERROR_PLANE(sde_plane[i],
  1560. "inline rotation is not supported in mulirect mode\n");
  1561. return -EINVAL;
  1562. }
  1563. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1564. SDE_ERROR_PLANE(sde_plane[i],
  1565. "Unsupported format for multirect mode\n");
  1566. return -EINVAL;
  1567. }
  1568. /**
  1569. * SSPP PD_MEM is split half - one for each RECT.
  1570. * Tiled formats need 5 lines of buffering while fetching
  1571. * whereas linear formats need only 2 lines.
  1572. * So we cannot support more than half of the supported SSPP
  1573. * width for tiled formats.
  1574. */
  1575. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1576. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1577. width_threshold[i] /= 2;
  1578. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1579. parallel_fetch_qualified = false;
  1580. if (sde_plane[i]->is_virtual)
  1581. mode = sde_plane_get_property(pstate[i],
  1582. PLANE_PROP_MULTIRECT_MODE);
  1583. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1584. const_alpha_enable = false;
  1585. }
  1586. buffer_lines = 2 * max_tile_height;
  1587. /**
  1588. * fallback to driver mode selection logic if client is using
  1589. * multirect plane without setting property.
  1590. *
  1591. * validate multirect mode configuration based on rectangle
  1592. */
  1593. switch (mode) {
  1594. case SDE_SSPP_MULTIRECT_NONE:
  1595. if (parallel_fetch_qualified)
  1596. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1597. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1598. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1599. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1600. else
  1601. SDE_ERROR(
  1602. "planes(%d - %d) multirect mode selection fail\n",
  1603. drm_state[R0]->plane->base.id,
  1604. drm_state[R1]->plane->base.id);
  1605. break;
  1606. case SDE_SSPP_MULTIRECT_PARALLEL:
  1607. if (!parallel_fetch_qualified) {
  1608. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1609. drm_state[R0]->plane->base.id,
  1610. width_threshold[R0], src[R0].w);
  1611. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1612. drm_state[R1]->plane->base.id,
  1613. width_threshold[R1], src[R1].w);
  1614. SDE_ERROR("parallel fetch not qualified\n");
  1615. mode = SDE_SSPP_MULTIRECT_NONE;
  1616. }
  1617. break;
  1618. case SDE_SSPP_MULTIRECT_TIME_MX:
  1619. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1620. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1621. SDE_ERROR(
  1622. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1623. buffer_lines, drm_state[R0]->plane->base.id,
  1624. dst[R0].y, dst[R0].h);
  1625. SDE_ERROR(
  1626. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1627. buffer_lines, drm_state[R1]->plane->base.id,
  1628. dst[R1].y, dst[R1].h);
  1629. SDE_ERROR("time multiplexed fetch not qualified\n");
  1630. mode = SDE_SSPP_MULTIRECT_NONE;
  1631. }
  1632. break;
  1633. default:
  1634. SDE_ERROR("bad mode:%d selection\n", mode);
  1635. mode = SDE_SSPP_MULTIRECT_NONE;
  1636. break;
  1637. }
  1638. for (i = 0; i < R_MAX; i++) {
  1639. pstate[i]->multirect_mode = mode;
  1640. pstate[i]->const_alpha_en = const_alpha_enable;
  1641. }
  1642. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1643. return -EINVAL;
  1644. if (sde_plane[R0]->is_virtual) {
  1645. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1646. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1647. } else {
  1648. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1649. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1650. }
  1651. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1652. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1653. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1654. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1655. return 0;
  1656. }
  1657. /**
  1658. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1659. * @plane: Pointer to drm plane structure
  1660. * @ctl: Pointer to hardware control driver
  1661. * @set: set if true else clear
  1662. */
  1663. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1664. bool set)
  1665. {
  1666. if (!plane || !ctl) {
  1667. SDE_ERROR("invalid parameters\n");
  1668. return;
  1669. }
  1670. if (!ctl->ops.update_bitmask_sspp) {
  1671. SDE_ERROR("invalid ops\n");
  1672. return;
  1673. }
  1674. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1675. }
  1676. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1677. struct drm_plane_state *new_state)
  1678. {
  1679. struct drm_framebuffer *fb = new_state->fb;
  1680. struct sde_plane *psde = to_sde_plane(plane);
  1681. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1682. struct sde_hw_fmt_layout layout;
  1683. struct msm_gem_address_space *aspace;
  1684. int ret;
  1685. if (!fb)
  1686. return 0;
  1687. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1688. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1689. if (ret) {
  1690. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1691. return ret;
  1692. }
  1693. /* cache aspace */
  1694. pstate->aspace = aspace;
  1695. /*
  1696. * when transitioning from secure to non-secure,
  1697. * plane->prepare_fb happens before the commit. In such case,
  1698. * defer the prepare_fb and handled it late, during the commit
  1699. * after attaching the domains as part of the transition
  1700. */
  1701. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1702. true : false;
  1703. if (pstate->defer_prepare_fb) {
  1704. SDE_EVT32(DRMID(plane), psde->pipe);
  1705. SDE_DEBUG_PLANE(psde,
  1706. "domain not attached, prepare_fb handled later\n");
  1707. return 0;
  1708. }
  1709. if (pstate->aspace && fb) {
  1710. ret = msm_framebuffer_prepare(fb,
  1711. pstate->aspace);
  1712. if (ret) {
  1713. SDE_ERROR("failed to prepare framebuffer\n");
  1714. return ret;
  1715. }
  1716. }
  1717. /* validate framebuffer layout before commit */
  1718. ret = sde_format_populate_layout(pstate->aspace,
  1719. fb, &layout);
  1720. if (ret) {
  1721. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1722. return ret;
  1723. }
  1724. return 0;
  1725. }
  1726. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1727. struct drm_plane_state *old_state)
  1728. {
  1729. struct sde_plane *psde = to_sde_plane(plane);
  1730. struct sde_plane_state *old_pstate;
  1731. if (!old_state || !old_state->fb || !plane)
  1732. return;
  1733. old_pstate = to_sde_plane_state(old_state);
  1734. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1735. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1736. }
  1737. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1738. struct drm_plane_state *state,
  1739. struct drm_plane_state *old_state)
  1740. {
  1741. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1742. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1743. struct drm_framebuffer *fb, *old_fb;
  1744. /* no need to check it again */
  1745. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1746. return;
  1747. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1748. || psde->is_error) {
  1749. SDE_DEBUG_PLANE(psde,
  1750. "enabling/disabling full modeset required\n");
  1751. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1752. } else if (to_sde_plane_state(old_state)->pending) {
  1753. SDE_DEBUG_PLANE(psde, "still pending\n");
  1754. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1755. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1756. pstate->multirect_mode != old_pstate->multirect_mode) {
  1757. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1758. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1759. } else if (state->src_w != old_state->src_w ||
  1760. state->src_h != old_state->src_h ||
  1761. state->src_x != old_state->src_x ||
  1762. state->src_y != old_state->src_y) {
  1763. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1764. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1765. } else if (state->crtc_w != old_state->crtc_w ||
  1766. state->crtc_h != old_state->crtc_h ||
  1767. state->crtc_x != old_state->crtc_x ||
  1768. state->crtc_y != old_state->crtc_y) {
  1769. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1770. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1771. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1772. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1773. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1774. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1775. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1776. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1777. } else if (pstate->rotation != old_pstate->rotation) {
  1778. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1779. pstate->rotation, old_pstate->rotation);
  1780. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1781. }
  1782. fb = state->fb;
  1783. old_fb = old_state->fb;
  1784. if (!fb || !old_fb) {
  1785. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1786. } else if ((fb->format->format != old_fb->format->format) ||
  1787. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1788. SDE_DEBUG_PLANE(psde, "format change\n");
  1789. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1790. } else {
  1791. uint64_t new_mod = fb->modifier;
  1792. uint64_t old_mod = old_fb->modifier;
  1793. uint32_t *new_pitches = fb->pitches;
  1794. uint32_t *old_pitches = old_fb->pitches;
  1795. uint32_t *new_offset = fb->offsets;
  1796. uint32_t *old_offset = old_fb->offsets;
  1797. int i;
  1798. if (new_mod != old_mod) {
  1799. SDE_DEBUG_PLANE(psde,
  1800. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1801. new_mod, old_mod);
  1802. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1803. SDE_PLANE_DIRTY_RECTS;
  1804. }
  1805. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1806. if (new_pitches[i] != old_pitches[i]) {
  1807. SDE_DEBUG_PLANE(psde,
  1808. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1809. i, old_pitches[i], new_pitches[i]);
  1810. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1811. break;
  1812. }
  1813. }
  1814. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1815. if (new_offset[i] != old_offset[i]) {
  1816. SDE_DEBUG_PLANE(psde,
  1817. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1818. i, old_offset[i], new_offset[i]);
  1819. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1820. SDE_PLANE_DIRTY_RECTS;
  1821. break;
  1822. }
  1823. }
  1824. }
  1825. }
  1826. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1827. unsigned long base_addr, u32 size)
  1828. {
  1829. int ret = -EINVAL;
  1830. u32 addr;
  1831. struct sde_plane *psde = to_sde_plane(plane);
  1832. if (!psde || !base_addr || !size) {
  1833. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1834. return ret;
  1835. }
  1836. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1837. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1838. is_sde_plane_virtual(plane));
  1839. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1840. ret = 0;
  1841. }
  1842. return ret;
  1843. }
  1844. static inline bool _sde_plane_is_pre_downscale_enabled(
  1845. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1846. {
  1847. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1848. }
  1849. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1850. struct sde_plane_state *pstate,
  1851. const struct sde_format *fmt,
  1852. uint32_t img_w, uint32_t img_h,
  1853. uint32_t src_w, uint32_t src_h,
  1854. uint32_t deci_w, uint32_t deci_h)
  1855. {
  1856. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1857. bool pre_down_en;
  1858. int i;
  1859. if (!psde || !pstate || !fmt) {
  1860. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1861. return -EINVAL;
  1862. }
  1863. if (psde->debugfs_default_scale ||
  1864. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1865. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1866. return 0;
  1867. pd_cfg = &pstate->pre_down;
  1868. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1869. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1870. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1871. uint32_t hor_req_pixels, hor_fetch_pixels;
  1872. uint32_t vert_req_pixels, vert_fetch_pixels;
  1873. uint32_t src_w_tmp, src_h_tmp;
  1874. uint32_t scaler_w, scaler_h;
  1875. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1876. bool rot;
  1877. /* re-use color plane 1's config for plane 2 */
  1878. if (i == 2)
  1879. continue;
  1880. if (pre_down_en) {
  1881. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1882. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1883. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1884. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1885. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1886. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1887. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1888. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1889. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1890. i, pre_down_ratio_x, pre_down_ratio_y);
  1891. }
  1892. src_w_tmp = src_w;
  1893. src_h_tmp = src_h;
  1894. /*
  1895. * For chroma plane, width is half for the following sub sampled
  1896. * formats. Except in case of decimation, where hardware avoids
  1897. * 1 line of decimation instead of downsampling.
  1898. */
  1899. if (i == 1) {
  1900. if (!deci_w &&
  1901. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1902. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1903. src_w_tmp >>= 1;
  1904. if (!deci_h &&
  1905. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1906. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1907. src_h_tmp >>= 1;
  1908. }
  1909. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1910. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1911. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1912. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1913. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1914. deci_w);
  1915. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1916. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1917. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1918. deci_h);
  1919. if ((hor_req_pixels != hor_fetch_pixels) ||
  1920. (hor_fetch_pixels > img_w) ||
  1921. (vert_req_pixels != vert_fetch_pixels) ||
  1922. (vert_fetch_pixels > img_h)) {
  1923. SDE_ERROR_PLANE(psde,
  1924. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1925. hor_req_pixels, vert_req_pixels,
  1926. hor_fetch_pixels, vert_fetch_pixels,
  1927. img_w, img_h);
  1928. return -EINVAL;
  1929. }
  1930. /*
  1931. * swap the scaler src width & height for inline-rotation 90
  1932. * comparison with Pixel-Extension, as PE is based on
  1933. * pre-rotation and QSEED is based on post-rotation
  1934. */
  1935. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1936. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1937. : pstate->scaler3_cfg.src_width[i];
  1938. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1939. : pstate->scaler3_cfg.src_height[i];
  1940. /*
  1941. * Alpha plane can only be scaled using bilinear or pixel
  1942. * repeat/drop, src_width and src_height are only specified
  1943. * for Y and UV plane
  1944. */
  1945. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1946. vert_req_pixels / pre_down_ratio_y !=
  1947. scaler_h)) {
  1948. SDE_ERROR_PLANE(psde,
  1949. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1950. i, pstate->pixel_ext.roi_w[i],
  1951. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1952. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1953. return -EINVAL;
  1954. }
  1955. /*
  1956. * SSPP fetch , unpack output and QSEED3 input lines need
  1957. * to match for Y plane
  1958. */
  1959. if (i == 0 &&
  1960. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1961. BIT(SDE_DRM_DEINTERLACE)) &&
  1962. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1963. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1964. SDE_ERROR_PLANE(psde,
  1965. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1966. i, pstate->pixel_ext.roi_w[i],
  1967. pstate->pixel_ext.roi_h[i],
  1968. pstate->scaler3_cfg.src_width[i],
  1969. pstate->scaler3_cfg.src_height[i],
  1970. src_w, src_h);
  1971. return -EINVAL;
  1972. }
  1973. }
  1974. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1975. return 0;
  1976. }
  1977. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1978. {
  1979. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1980. }
  1981. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1982. struct sde_plane_state *pstate, struct sde_rect *dst,
  1983. u32 src_w, u32 src_h)
  1984. {
  1985. int ret = 0;
  1986. u32 min_ratio_numer, min_ratio_denom;
  1987. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1988. bool pd_x;
  1989. bool pd_y;
  1990. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1991. return ret;
  1992. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1993. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1994. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1995. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1996. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1997. SDE_ERROR_PLANE(psde,
  1998. "hw does not support pre-downscale X: 0x%x\n",
  1999. psde->features);
  2000. ret = -EINVAL;
  2001. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2002. SDE_ERROR_PLANE(psde,
  2003. "hw does not support pre-downscale Y: 0x%x\n",
  2004. psde->features);
  2005. ret = -EINVAL;
  2006. } else if (!min_ratio_numer || !min_ratio_denom) {
  2007. SDE_ERROR_PLANE(psde,
  2008. "min downscale ratio not set! %u / %u\n",
  2009. min_ratio_numer, min_ratio_denom);
  2010. ret = -EINVAL;
  2011. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2012. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2013. min_ratio_denom))) {
  2014. SDE_ERROR_PLANE(psde,
  2015. "failed min downscale-x check %u->%u, %u/%u\n",
  2016. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2017. ret = -EINVAL;
  2018. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2019. min_ratio_denom))) {
  2020. SDE_ERROR_PLANE(psde,
  2021. "failed min downscale-y check %u->%u, %u/%u\n",
  2022. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2023. ret = -EINVAL;
  2024. }
  2025. return ret;
  2026. }
  2027. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2028. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2029. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2030. u32 *max_numer_h, u32 *max_denom_h)
  2031. {
  2032. bool rotated, has_predown, default_scale;
  2033. const struct sde_sspp_sub_blks *sblk;
  2034. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2035. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2036. sblk = psde->pipe_sblk;
  2037. *max_numer_w = sblk->maxdwnscale;
  2038. *max_denom_w = 1;
  2039. *max_numer_h = sblk->maxdwnscale;
  2040. *max_denom_h = 1;
  2041. has_predown = _sde_plane_has_pre_downscale(psde);
  2042. if (has_predown)
  2043. pd = &pstate->pre_down;
  2044. default_scale = psde->debugfs_default_scale ||
  2045. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2046. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2047. /**
  2048. * Inline rotation has different max vertical downscaling limits since
  2049. * the source-width becomes the scaler's pre-downscaled source-height.
  2050. **/
  2051. if (rotated) {
  2052. if (pd != NULL && rt_client && has_predown) {
  2053. if (default_scale)
  2054. pd->pre_downscale_x_0 = (src_h >
  2055. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2056. *max_numer_h = pd->pre_downscale_x_0 ?
  2057. sblk->in_rot_maxdwnscale_rt_num :
  2058. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2059. *max_denom_h = pd->pre_downscale_x_0 ?
  2060. sblk->in_rot_maxdwnscale_rt_denom :
  2061. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2062. } else if (rt_client) {
  2063. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2064. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2065. } else {
  2066. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2067. }
  2068. }
  2069. }
  2070. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2071. struct sde_plane *psde, const struct sde_format *fmt,
  2072. struct sde_plane_state *pstate, struct sde_rect *src,
  2073. struct sde_rect *dst, u32 width, u32 height)
  2074. {
  2075. int ret = 0;
  2076. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2077. uint32_t scaler_src_w, scaler_src_h;
  2078. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2079. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2080. uint32_t max_upscale, max_linewidth;
  2081. bool inline_rotation, rt_client;
  2082. struct drm_crtc *crtc;
  2083. struct drm_crtc_state *new_cstate;
  2084. const struct sde_sspp_sub_blks *sblk;
  2085. if (!state || !state->state || !state->crtc) {
  2086. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2087. return -EINVAL;
  2088. }
  2089. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2090. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2091. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2092. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2093. /* with inline rotator, the source of the scaler is post-rotated */
  2094. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2095. if (inline_rotation) {
  2096. scaler_src_w = src_deci_h;
  2097. scaler_src_h = src_deci_w;
  2098. } else {
  2099. scaler_src_w = src_deci_w;
  2100. scaler_src_h = src_deci_h;
  2101. }
  2102. sblk = psde->pipe_sblk;
  2103. max_upscale = sblk->maxupscale;
  2104. if (inline_rotation)
  2105. max_linewidth = sblk->in_rot_maxheight;
  2106. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2107. max_linewidth = sblk->scaling_linewidth;
  2108. else
  2109. max_linewidth = sblk->maxlinewidth;
  2110. crtc = state->crtc;
  2111. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2112. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2113. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2114. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2115. &max_downscale_num_h, &max_downscale_denom_h);
  2116. /* decimation validation */
  2117. if ((deci_w || deci_h)
  2118. && ((deci_w > sblk->maxhdeciexp)
  2119. || (deci_h > sblk->maxvdeciexp))) {
  2120. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2121. ret = -EINVAL;
  2122. } else if ((deci_w || deci_h)
  2123. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2124. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2125. ret = -EINVAL;
  2126. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2127. ((src->w != dst->w) || (src->h != dst->h))) {
  2128. SDE_ERROR_PLANE(psde,
  2129. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2130. src->w, src->h, dst->w, dst->h);
  2131. ret = -EINVAL;
  2132. /* check scaler source width */
  2133. } else if (scaler_src_w > max_linewidth) {
  2134. SDE_ERROR_PLANE(psde,
  2135. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2136. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2137. ret = -E2BIG;
  2138. /* check max scaler capability */
  2139. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2140. ((scaler_src_h * max_upscale) < dst->h) ||
  2141. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2142. < scaler_src_w) ||
  2143. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2144. < scaler_src_h)) {
  2145. SDE_ERROR_PLANE(psde,
  2146. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2147. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2148. inline_rotation, max_downscale_num_w,
  2149. max_downscale_denom_w, max_downscale_num_h,
  2150. max_downscale_denom_h);
  2151. ret = -E2BIG;
  2152. /* check inline pre-downscale support */
  2153. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2154. pstate, dst, src_deci_w, src_deci_h)) {
  2155. ret = -EINVAL;
  2156. /* QSEED validation */
  2157. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2158. width, height, src->w, src->h,
  2159. deci_w, deci_h)) {
  2160. ret = -EINVAL;
  2161. }
  2162. return ret;
  2163. }
  2164. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2165. struct sde_plane_state *pstate, struct sde_rect *src,
  2166. const struct sde_format *fmt, int ret)
  2167. {
  2168. /* check excl rect configs */
  2169. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2170. struct sde_rect intersect;
  2171. /*
  2172. * Check exclusion rect against src rect.
  2173. * it must intersect with source rect.
  2174. */
  2175. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2176. if (intersect.w != pstate->excl_rect.w ||
  2177. intersect.h != pstate->excl_rect.h ||
  2178. SDE_FORMAT_IS_YUV(fmt)) {
  2179. SDE_ERROR_PLANE(psde,
  2180. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2181. pstate->excl_rect.x, pstate->excl_rect.y,
  2182. pstate->excl_rect.w, pstate->excl_rect.h,
  2183. src->x, src->y, src->w, src->h,
  2184. (char *)&fmt->base.pixel_format);
  2185. ret = -EINVAL;
  2186. }
  2187. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2188. pstate->excl_rect.x, pstate->excl_rect.y,
  2189. pstate->excl_rect.w, pstate->excl_rect.h);
  2190. }
  2191. return ret;
  2192. }
  2193. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2194. struct drm_plane_state *state)
  2195. {
  2196. struct sde_kms *sde_kms;
  2197. struct sde_splash_display *splash_display;
  2198. int i;
  2199. sde_kms = _sde_plane_get_kms(&psde->base);
  2200. if (!sde_kms || !state->crtc)
  2201. return 0;
  2202. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2203. splash_display = &sde_kms->splash_data.splash_display[i];
  2204. if (splash_display && splash_display->cont_splash_enabled &&
  2205. splash_display->encoder &&
  2206. state->crtc != splash_display->encoder->crtc) {
  2207. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2208. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2209. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2210. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2211. psde->pipe,
  2212. splash_display->encoder->crtc->base.id);
  2213. return -EINVAL;
  2214. }
  2215. }
  2216. }
  2217. return 0;
  2218. }
  2219. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2220. const struct sde_format *fmt,
  2221. struct sde_rect src, struct sde_rect dst,
  2222. u32 width, u32 height)
  2223. {
  2224. int ret = 0;
  2225. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2226. if (SDE_FORMAT_IS_YUV(fmt) &&
  2227. (!(psde->features & SDE_SSPP_SCALER) ||
  2228. !(psde->features & (BIT(SDE_SSPP_CSC)
  2229. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2230. SDE_ERROR_PLANE(psde,
  2231. "plane doesn't have scaler/csc for yuv\n");
  2232. ret = -EINVAL;
  2233. /* check src bounds */
  2234. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2235. src.w < min_src_size || src.h < min_src_size ||
  2236. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2237. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2238. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2239. src.x, src.y, src.w, src.h);
  2240. ret = -E2BIG;
  2241. /* valid yuv image */
  2242. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2243. (src.w & 0x1) || (src.h & 0x1))) {
  2244. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2245. src.x, src.y, src.w, src.h);
  2246. ret = -EINVAL;
  2247. /* min dst support */
  2248. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2249. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2250. dst.x, dst.y, dst.w, dst.h);
  2251. ret = -EINVAL;
  2252. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2253. !psde->catalog->ubwc_rev) {
  2254. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2255. ret = -EINVAL;
  2256. }
  2257. return ret;
  2258. }
  2259. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2260. struct drm_plane_state *state)
  2261. {
  2262. int ret = 0;
  2263. struct sde_plane *psde;
  2264. struct sde_plane_state *pstate;
  2265. const struct msm_format *msm_fmt;
  2266. const struct sde_format *fmt;
  2267. struct sde_rect src, dst;
  2268. bool q16_data = true;
  2269. struct drm_framebuffer *fb;
  2270. u32 width;
  2271. u32 height;
  2272. psde = to_sde_plane(plane);
  2273. pstate = to_sde_plane_state(state);
  2274. if (!psde->pipe_sblk) {
  2275. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2276. return -EINVAL;
  2277. }
  2278. /* src values are in Q16 fixed point, convert to integer */
  2279. POPULATE_RECT(&src, state->src_x, state->src_y,
  2280. state->src_w, state->src_h, q16_data);
  2281. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2282. state->crtc_h, !q16_data);
  2283. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2284. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2285. if (!sde_plane_enabled(state))
  2286. goto modeset_update;
  2287. fb = state->fb;
  2288. width = fb ? state->fb->width : 0x0;
  2289. height = fb ? state->fb->height : 0x0;
  2290. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2291. plane->base.id,
  2292. pstate->rotation,
  2293. width, height,
  2294. fb ? (char *) &state->fb->format->format : 0x0,
  2295. fb ? state->fb->modifier : 0x0);
  2296. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2297. state->src_w >> 16, state->src_h >> 16,
  2298. state->src_x >> 16, state->src_y >> 16,
  2299. state->crtc_w, state->crtc_h,
  2300. state->crtc_x, state->crtc_y);
  2301. msm_fmt = msm_framebuffer_format(fb);
  2302. fmt = to_sde_format(msm_fmt);
  2303. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2304. height);
  2305. if (ret)
  2306. return ret;
  2307. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2308. &src, &dst, width, height);
  2309. if (ret)
  2310. return ret;
  2311. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2312. &src, fmt, ret);
  2313. if (ret)
  2314. return ret;
  2315. ret = _sde_plane_validate_shared_crtc(psde, state);
  2316. if (ret)
  2317. return ret;
  2318. pstate->const_alpha_en = fmt->alpha_enable &&
  2319. (SDE_DRM_BLEND_OP_OPAQUE !=
  2320. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2321. (pstate->stage != SDE_STAGE_0);
  2322. modeset_update:
  2323. if (!ret)
  2324. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2325. state, plane->state);
  2326. return ret;
  2327. }
  2328. static int sde_plane_atomic_check(struct drm_plane *plane,
  2329. struct drm_atomic_state *atomic_state)
  2330. {
  2331. int ret = 0;
  2332. struct sde_plane *psde;
  2333. struct sde_plane_state *pstate;
  2334. struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2335. if (!plane || !state) {
  2336. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2337. !plane, !state);
  2338. ret = -EINVAL;
  2339. goto exit;
  2340. }
  2341. psde = to_sde_plane(plane);
  2342. pstate = to_sde_plane_state(state);
  2343. SDE_DEBUG_PLANE(psde, "\n");
  2344. ret = sde_plane_rot_atomic_check(plane, state);
  2345. if (ret)
  2346. goto exit;
  2347. ret = sde_plane_sspp_atomic_check(plane, state);
  2348. exit:
  2349. return ret;
  2350. }
  2351. void sde_plane_flush(struct drm_plane *plane)
  2352. {
  2353. struct sde_plane *psde;
  2354. struct sde_plane_state *pstate;
  2355. if (!plane || !plane->state) {
  2356. SDE_ERROR("invalid plane\n");
  2357. return;
  2358. }
  2359. psde = to_sde_plane(plane);
  2360. pstate = to_sde_plane_state(plane->state);
  2361. /*
  2362. * These updates have to be done immediately before the plane flush
  2363. * timing, and may not be moved to the atomic_update/mode_set functions.
  2364. */
  2365. if (psde->is_error)
  2366. /* force white frame with 100% alpha pipe output on error */
  2367. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2368. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2369. /* force 100% alpha */
  2370. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2371. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2372. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2373. /* flag h/w flush complete */
  2374. if (plane->state)
  2375. pstate->pending = false;
  2376. }
  2377. /**
  2378. * sde_plane_set_error: enable/disable error condition
  2379. * @plane: pointer to drm_plane structure
  2380. */
  2381. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2382. {
  2383. struct sde_plane *psde;
  2384. if (!plane)
  2385. return;
  2386. psde = to_sde_plane(plane);
  2387. psde->is_error = error;
  2388. }
  2389. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2390. struct sde_plane_state *pstate)
  2391. {
  2392. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2393. bool prev_rd_en;
  2394. /* Only display system cache is currently supported */
  2395. if (!sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
  2396. return;
  2397. prev_rd_en = pstate->sc_cfg.rd_en;
  2398. SDE_DEBUG_PLANE(psde, "features:0x%x\n", psde->features);
  2399. pstate->sc_cfg.rd_en = false;
  2400. pstate->sc_cfg.rd_scid = 0x0;
  2401. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2402. SSPP_SYS_CACHE_SCID;
  2403. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2404. if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE) {
  2405. pstate->sc_cfg.rd_en = true;
  2406. pstate->sc_cfg.rd_scid =
  2407. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2408. pstate->sc_cfg.rd_noallocate = false;
  2409. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2410. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2411. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2412. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ) {
  2413. pstate->sc_cfg.rd_en = true;
  2414. pstate->sc_cfg.rd_scid =
  2415. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2416. pstate->sc_cfg.rd_noallocate = true;
  2417. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2418. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2419. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2420. }
  2421. if (!pstate->sc_cfg.rd_en && !prev_rd_en)
  2422. return;
  2423. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2424. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2425. psde->pipe_hw->ops.setup_sys_cache(
  2426. psde->pipe_hw, &pstate->sc_cfg);
  2427. }
  2428. void sde_plane_static_img_control(struct drm_plane *plane,
  2429. enum sde_crtc_cache_state state)
  2430. {
  2431. struct sde_plane *psde;
  2432. struct sde_plane_state *pstate;
  2433. if (!plane || !plane->state) {
  2434. SDE_ERROR("invalid plane\n");
  2435. return;
  2436. }
  2437. psde = to_sde_plane(plane);
  2438. pstate = to_sde_plane_state(plane->state);
  2439. pstate->static_cache_state = state;
  2440. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2441. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2442. }
  2443. static void _sde_plane_map_prop_to_dirty_bits(void)
  2444. {
  2445. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2446. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2447. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2448. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2449. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2450. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2451. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2452. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2453. plane_prop_array[PLANE_PROP_ZPOS] =
  2454. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2455. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2456. SDE_PLANE_DIRTY_RECTS;
  2457. plane_prop_array[PLANE_PROP_CSC_V1] =
  2458. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2459. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2460. SDE_PLANE_DIRTY_FORMAT;
  2461. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2462. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2463. SDE_PLANE_DIRTY_ALL;
  2464. /* no special action required */
  2465. plane_prop_array[PLANE_PROP_INFO] =
  2466. plane_prop_array[PLANE_PROP_ALPHA] =
  2467. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2468. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2469. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2470. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2471. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2472. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2473. SDE_PLANE_DIRTY_PERF;
  2474. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2475. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2476. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2477. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2478. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2479. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2480. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2481. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2482. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2483. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2484. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2485. SDE_PLANE_DIRTY_ALL;
  2486. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2487. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2488. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2489. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2490. }
  2491. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2492. struct sde_rect *src, struct sde_rect *dst)
  2493. {
  2494. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2495. u32 downscale = (src->h * 1000)/dst->h;
  2496. return (downscale > max_downscale) ? false : true;
  2497. }
  2498. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2499. struct sde_plane *psde, struct sde_plane_state *pstate,
  2500. struct sde_rect *src, struct sde_rect *dst)
  2501. {
  2502. struct sde_hw_pipe_uidle_cfg cfg;
  2503. u32 line_time = sde_crtc_get_line_time(crtc);
  2504. u32 fal1_target_idle_time_ns =
  2505. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2506. u32 fal10_target_idle_time_ns =
  2507. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2508. u32 fal10_threshold =
  2509. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2510. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2511. fal1_target_idle_time_ns) {
  2512. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2513. cfg.fal10_threshold = fal10_threshold;
  2514. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2515. cfg.fal1_threshold = min(1 +
  2516. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2517. psde->catalog->uidle_cfg.fal1_max_threshold);
  2518. cfg.fal_allowed_threshold = fal10_threshold +
  2519. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2520. } else {
  2521. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2522. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2523. fal1_target_idle_time_ns);
  2524. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2525. }
  2526. SDE_DEBUG_PLANE(psde,
  2527. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2528. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2529. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2530. SDE_DEBUG_PLANE(psde,
  2531. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2532. line_time, fal1_target_idle_time_ns,
  2533. fal10_target_idle_time_ns,
  2534. psde->catalog->uidle_cfg.max_dwnscale);
  2535. SDE_EVT32_VERBOSE(cfg.enable,
  2536. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2537. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2538. psde->catalog->uidle_cfg.max_dwnscale);
  2539. psde->pipe_hw->ops.setup_uidle(
  2540. psde->pipe_hw, &cfg,
  2541. pstate->multirect_index);
  2542. }
  2543. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2544. struct sde_plane_state *pstate)
  2545. {
  2546. bool enable = false;
  2547. int mode = sde_plane_get_property(pstate,
  2548. PLANE_PROP_FB_TRANSLATION_MODE);
  2549. if ((mode == SDE_DRM_FB_SEC) ||
  2550. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2551. enable = true;
  2552. /* update secure session flag */
  2553. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2554. pstate->multirect_index,
  2555. enable);
  2556. }
  2557. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2558. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2559. {
  2560. const struct sde_format *fmt;
  2561. const struct msm_format *msm_fmt;
  2562. struct sde_plane *psde;
  2563. struct drm_plane_state *state;
  2564. struct sde_plane_state *pstate;
  2565. struct sde_rect src, dst;
  2566. const struct sde_rect *crtc_roi;
  2567. bool q16_data = true;
  2568. int idx;
  2569. psde = to_sde_plane(plane);
  2570. state = plane->state;
  2571. pstate = to_sde_plane_state(state);
  2572. msm_fmt = msm_framebuffer_format(fb);
  2573. if (!msm_fmt) {
  2574. SDE_ERROR("crtc%d plane%d: null format\n",
  2575. DRMID(crtc), DRMID(plane));
  2576. return;
  2577. }
  2578. fmt = to_sde_format(msm_fmt);
  2579. POPULATE_RECT(&src, state->src_x, state->src_y,
  2580. state->src_w, state->src_h, q16_data);
  2581. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2582. state->crtc_w, state->crtc_h, !q16_data);
  2583. SDE_DEBUG_PLANE(psde,
  2584. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2585. fb->base.id, src.x, src.y, src.w, src.h,
  2586. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2587. (char *)&fmt->base.pixel_format,
  2588. SDE_FORMAT_IS_UBWC(fmt));
  2589. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2590. BIT(SDE_DRM_DEINTERLACE)) {
  2591. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2592. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2593. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2594. src.h /= 2;
  2595. src.y = DIV_ROUND_UP(src.y, 2);
  2596. src.y &= ~0x1;
  2597. }
  2598. /*
  2599. * adjust layer mixer position of the sspp in the presence
  2600. * of a partial update to the active lm origin
  2601. */
  2602. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2603. dst.x -= crtc_roi->x;
  2604. dst.y -= crtc_roi->y;
  2605. /* check for UIDLE */
  2606. if (psde->pipe_hw->ops.setup_uidle)
  2607. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2608. psde->pipe_cfg.src_rect = src;
  2609. psde->pipe_cfg.dst_rect = dst;
  2610. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2611. /* check for color fill */
  2612. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2613. PLANE_PROP_COLOR_FILL);
  2614. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2615. /* skip remaining processing on color fill */
  2616. pstate->dirty = 0x0;
  2617. } else if (psde->pipe_hw->ops.setup_rects) {
  2618. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2619. &psde->pipe_cfg,
  2620. pstate->multirect_index);
  2621. }
  2622. if (psde->pipe_hw->ops.setup_pe &&
  2623. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2624. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2625. &psde->pixel_ext);
  2626. /**
  2627. * when programmed in multirect mode, scalar block will be
  2628. * bypassed. Still we need to update alpha and bitwidth
  2629. * ONLY for RECT0
  2630. */
  2631. if (psde->pipe_hw->ops.setup_scaler &&
  2632. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2633. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2634. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2635. &psde->pipe_cfg, &psde->pixel_ext,
  2636. &psde->scaler3_cfg);
  2637. }
  2638. /* update excl rect */
  2639. if (psde->pipe_hw->ops.setup_excl_rect)
  2640. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2641. &pstate->excl_rect,
  2642. pstate->multirect_index);
  2643. /* enable multirect config of corresponding rect */
  2644. if (psde->pipe_hw->ops.update_multirect)
  2645. psde->pipe_hw->ops.update_multirect(
  2646. psde->pipe_hw,
  2647. true,
  2648. pstate->multirect_index,
  2649. pstate->multirect_mode);
  2650. }
  2651. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2652. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2653. {
  2654. uint32_t src_flags = 0;
  2655. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2656. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2657. src_flags |= SDE_SSPP_FLIP_LR;
  2658. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2659. src_flags |= SDE_SSPP_FLIP_UD;
  2660. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2661. src_flags |= SDE_SSPP_ROT_90;
  2662. /* update format */
  2663. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2664. pstate->const_alpha_en, src_flags,
  2665. pstate->multirect_index);
  2666. if (psde->pipe_hw->ops.setup_cdp) {
  2667. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2668. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2669. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2670. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2671. cdp_cfg->ubwc_meta_enable =
  2672. SDE_FORMAT_IS_UBWC(fmt);
  2673. cdp_cfg->tile_amortize_enable =
  2674. SDE_FORMAT_IS_UBWC(fmt) ||
  2675. SDE_FORMAT_IS_TILE(fmt);
  2676. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2677. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2678. pstate->multirect_index);
  2679. }
  2680. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2681. /* update csc */
  2682. if (SDE_FORMAT_IS_YUV(fmt))
  2683. _sde_plane_setup_csc(psde);
  2684. else
  2685. psde->csc_ptr = 0;
  2686. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2687. uint32_t pma_mode = 0;
  2688. if (fmt->alpha_enable)
  2689. pma_mode = (uint32_t) sde_plane_get_property(
  2690. pstate, PLANE_PROP_INVERSE_PMA);
  2691. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2692. pstate->multirect_index, pma_mode);
  2693. }
  2694. if (psde->pipe_hw->ops.setup_dgm_csc)
  2695. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2696. pstate->multirect_index, psde->csc_usr_ptr);
  2697. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2698. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2699. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2700. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2701. else
  2702. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2703. pstate->multirect_index, NULL);
  2704. }
  2705. }
  2706. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2707. {
  2708. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2709. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2710. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2711. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2712. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2713. &psde->sharp_cfg);
  2714. }
  2715. static void _sde_plane_update_properties(struct drm_plane *plane,
  2716. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2717. {
  2718. uint32_t nplanes;
  2719. const struct msm_format *msm_fmt;
  2720. const struct sde_format *fmt;
  2721. struct sde_plane *psde;
  2722. struct drm_plane_state *state;
  2723. struct sde_plane_state *pstate;
  2724. psde = to_sde_plane(plane);
  2725. state = plane->state;
  2726. pstate = to_sde_plane_state(state);
  2727. if (!pstate) {
  2728. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2729. return;
  2730. }
  2731. msm_fmt = msm_framebuffer_format(fb);
  2732. if (!msm_fmt) {
  2733. SDE_ERROR("crtc%d plane%d: null format\n",
  2734. DRMID(crtc), DRMID(plane));
  2735. return;
  2736. }
  2737. fmt = to_sde_format(msm_fmt);
  2738. nplanes = fmt->num_planes;
  2739. /* update secure session flag */
  2740. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2741. _sde_plane_update_secure_session(psde, pstate);
  2742. /* update roi config */
  2743. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2744. _sde_plane_update_roi_config(plane, crtc, fb);
  2745. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2746. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2747. psde->pipe_hw->ops.setup_format)
  2748. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2749. sde_color_process_plane_setup(plane);
  2750. /* update sharpening */
  2751. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2752. psde->pipe_hw->ops.setup_sharpening)
  2753. _sde_plane_update_sharpening(psde);
  2754. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2755. SDE_PLANE_DIRTY_FORMAT))
  2756. _sde_plane_set_qos_lut(plane, crtc, fb);
  2757. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2758. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2759. _sde_plane_set_ot_limit(plane, crtc);
  2760. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2761. _sde_plane_set_ts_prefill(plane, pstate);
  2762. }
  2763. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2764. _sde_plane_set_qos_remap(plane);
  2765. /* clear dirty */
  2766. pstate->dirty = 0x0;
  2767. }
  2768. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2769. struct drm_plane_state *old_state)
  2770. {
  2771. struct sde_plane *psde;
  2772. struct drm_plane_state *state;
  2773. struct sde_plane_state *pstate;
  2774. struct sde_plane_state *old_pstate;
  2775. struct drm_crtc *crtc;
  2776. struct drm_framebuffer *fb;
  2777. int idx;
  2778. int dirty_prop_flag;
  2779. bool is_rt;
  2780. if (!plane) {
  2781. SDE_ERROR("invalid plane\n");
  2782. return -EINVAL;
  2783. } else if (!plane->state) {
  2784. SDE_ERROR("invalid plane state\n");
  2785. return -EINVAL;
  2786. } else if (!old_state) {
  2787. SDE_ERROR("invalid old state\n");
  2788. return -EINVAL;
  2789. }
  2790. psde = to_sde_plane(plane);
  2791. state = plane->state;
  2792. pstate = to_sde_plane_state(state);
  2793. old_pstate = to_sde_plane_state(old_state);
  2794. crtc = state->crtc;
  2795. fb = state->fb;
  2796. if (!crtc || !fb) {
  2797. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2798. !crtc, !fb);
  2799. return -EINVAL;
  2800. }
  2801. SDE_DEBUG(
  2802. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2803. plane->base.id,
  2804. state->fb->width, state->fb->height,
  2805. (char *) &state->fb->format->format,
  2806. state->fb->modifier,
  2807. state->src_w >> 16, state->src_h >> 16,
  2808. state->src_x >> 16, state->src_y >> 16,
  2809. pstate->rotation,
  2810. state->crtc_w, state->crtc_h,
  2811. state->crtc_x, state->crtc_y);
  2812. /* force reprogramming of all the parameters, if the flag is set */
  2813. if (psde->revalidate) {
  2814. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2815. plane->base.id);
  2816. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2817. psde->revalidate = false;
  2818. }
  2819. /* determine what needs to be refreshed */
  2820. mutex_lock(&psde->property_info.property_lock);
  2821. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2822. &pstate->property_state)) >= 0) {
  2823. dirty_prop_flag = plane_prop_array[idx];
  2824. pstate->dirty |= dirty_prop_flag;
  2825. }
  2826. mutex_unlock(&psde->property_info.property_lock);
  2827. /**
  2828. * since plane_atomic_check is invoked before crtc_atomic_check
  2829. * in the commit sequence, all the parameters for updating the
  2830. * plane dirty flag will not be available during
  2831. * plane_atomic_check as some features params are updated
  2832. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2833. * before sspp update.
  2834. */
  2835. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2836. old_state);
  2837. /* re-program the output rects always if partial update roi changed */
  2838. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2839. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2840. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2841. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2842. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2843. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2844. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2845. psde->is_rt_pipe = is_rt;
  2846. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2847. }
  2848. /* early out if nothing dirty */
  2849. if (!pstate->dirty)
  2850. return 0;
  2851. pstate->pending = true;
  2852. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2853. _sde_plane_update_properties(plane, crtc, fb);
  2854. return 0;
  2855. }
  2856. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2857. struct drm_plane_state *old_state)
  2858. {
  2859. struct sde_plane *psde;
  2860. struct drm_plane_state *state;
  2861. struct sde_plane_state *pstate;
  2862. u32 multirect_index = SDE_SSPP_RECT_0;
  2863. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2864. u32 blend_type;
  2865. if (!plane) {
  2866. SDE_ERROR("invalid plane\n");
  2867. return;
  2868. } else if (!plane->state) {
  2869. SDE_ERROR("invalid plane state\n");
  2870. return;
  2871. } else if (!old_state) {
  2872. SDE_ERROR("invalid old state\n");
  2873. return;
  2874. }
  2875. psde = to_sde_plane(plane);
  2876. state = plane->state;
  2877. pstate = to_sde_plane_state(state);
  2878. blend_type = sde_plane_get_property(pstate,
  2879. PLANE_PROP_BLEND_OP);
  2880. /* some of the color features are dependent on plane with skip blend.
  2881. * if skip blend plane is being disabled, we need to disable color properties.
  2882. */
  2883. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2884. skip_blend_plane.valid_plane = false;
  2885. skip_blend_plane.plane = SSPP_NONE;
  2886. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2887. sde_crtc_disable_cp_features(old_state->crtc);
  2888. }
  2889. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2890. pstate->multirect_mode);
  2891. pstate->pending = true;
  2892. if (is_sde_plane_virtual(plane))
  2893. multirect_index = SDE_SSPP_RECT_1;
  2894. /* disable multirect config of corresponding rect */
  2895. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2896. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2897. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2898. }
  2899. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2900. struct drm_plane_state *old_state)
  2901. {
  2902. struct sde_plane *psde;
  2903. struct drm_plane_state *state;
  2904. if (!plane) {
  2905. SDE_ERROR("invalid plane\n");
  2906. return;
  2907. } else if (!plane->state) {
  2908. SDE_ERROR("invalid plane state\n");
  2909. return;
  2910. }
  2911. psde = to_sde_plane(plane);
  2912. psde->is_error = false;
  2913. state = plane->state;
  2914. SDE_DEBUG_PLANE(psde, "\n");
  2915. if (!sde_plane_enabled(state)) {
  2916. _sde_plane_atomic_disable(plane, old_state);
  2917. } else {
  2918. int ret;
  2919. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2920. /* atomic_check should have ensured that this doesn't fail */
  2921. WARN_ON(ret < 0);
  2922. }
  2923. }
  2924. static void sde_plane_atomic_update(struct drm_plane *plane,
  2925. struct drm_atomic_state *atomic_state)
  2926. {
  2927. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  2928. _sde_plane_atomic_update(plane, old_state);
  2929. }
  2930. void sde_plane_restore(struct drm_plane *plane)
  2931. {
  2932. struct sde_plane *psde;
  2933. if (!plane || !plane->state) {
  2934. SDE_ERROR("invalid plane\n");
  2935. return;
  2936. }
  2937. psde = to_sde_plane(plane);
  2938. /*
  2939. * Revalidate is only true here if idle PC occurred and
  2940. * there is no plane state update in current commit cycle.
  2941. */
  2942. if (!psde->revalidate)
  2943. return;
  2944. SDE_DEBUG_PLANE(psde, "\n");
  2945. /* last plane state is same as current state */
  2946. _sde_plane_atomic_update(plane, plane->state);
  2947. }
  2948. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2949. enum sde_sys_cache_type type)
  2950. {
  2951. struct sde_plane_state *pstate;
  2952. if (!plane || !plane->state) {
  2953. SDE_ERROR("invalid plane\n");
  2954. return false;
  2955. }
  2956. pstate = to_sde_plane_state(plane->state);
  2957. /* check if llcc is required for the plane */
  2958. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2959. return true;
  2960. else
  2961. return false;
  2962. }
  2963. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2964. {
  2965. char feature_name[256];
  2966. if (psde->pipe_sblk->maxhdeciexp) {
  2967. msm_property_install_range(&psde->property_info,
  2968. "h_decimate", 0x0, 0,
  2969. psde->pipe_sblk->maxhdeciexp, 0,
  2970. PLANE_PROP_H_DECIMATE);
  2971. }
  2972. if (psde->pipe_sblk->maxvdeciexp) {
  2973. msm_property_install_range(&psde->property_info,
  2974. "v_decimate", 0x0, 0,
  2975. psde->pipe_sblk->maxvdeciexp, 0,
  2976. PLANE_PROP_V_DECIMATE);
  2977. }
  2978. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2979. msm_property_install_range(
  2980. &psde->property_info, "scaler_v2",
  2981. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2982. msm_property_install_blob(&psde->property_info,
  2983. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2984. msm_property_install_blob(&psde->property_info,
  2985. "lut_cir", 0,
  2986. PLANE_PROP_SCALER_LUT_CIR);
  2987. msm_property_install_blob(&psde->property_info,
  2988. "lut_sep", 0,
  2989. PLANE_PROP_SCALER_LUT_SEP);
  2990. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2991. msm_property_install_range(
  2992. &psde->property_info, "scaler_v2",
  2993. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2994. msm_property_install_blob(&psde->property_info,
  2995. "lut_sep", 0,
  2996. PLANE_PROP_SCALER_LUT_SEP);
  2997. } else if (psde->features & SDE_SSPP_SCALER) {
  2998. msm_property_install_range(
  2999. &psde->property_info, "scaler_v1", 0x0,
  3000. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3001. }
  3002. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3003. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3004. msm_property_install_volatile_range(
  3005. &psde->property_info, "csc_v1", 0x0,
  3006. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3007. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3008. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3009. "SDE_SSPP_HUE_V",
  3010. psde->pipe_sblk->hsic_blk.version >> 16);
  3011. msm_property_install_range(&psde->property_info,
  3012. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3013. PLANE_PROP_HUE_ADJUST);
  3014. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3015. "SDE_SSPP_SATURATION_V",
  3016. psde->pipe_sblk->hsic_blk.version >> 16);
  3017. msm_property_install_range(&psde->property_info,
  3018. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3019. PLANE_PROP_SATURATION_ADJUST);
  3020. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3021. "SDE_SSPP_VALUE_V",
  3022. psde->pipe_sblk->hsic_blk.version >> 16);
  3023. msm_property_install_range(&psde->property_info,
  3024. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3025. PLANE_PROP_VALUE_ADJUST);
  3026. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3027. "SDE_SSPP_CONTRAST_V",
  3028. psde->pipe_sblk->hsic_blk.version >> 16);
  3029. msm_property_install_range(&psde->property_info,
  3030. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3031. PLANE_PROP_CONTRAST_ADJUST);
  3032. }
  3033. }
  3034. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3035. struct sde_kms_info *info)
  3036. {
  3037. char feature_name[256];
  3038. bool is_master = !psde->is_virtual;
  3039. if ((is_master &&
  3040. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3041. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3042. msm_property_install_range(&psde->property_info,
  3043. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3044. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3045. }
  3046. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3047. msm_property_install_volatile_range(
  3048. &psde->property_info, "csc_dma_v1", 0x0,
  3049. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3050. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3051. }
  3052. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3053. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3054. "SDE_SSPP_SKIN_COLOR_V",
  3055. psde->pipe_sblk->memcolor_blk.version >> 16);
  3056. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3057. PLANE_PROP_SKIN_COLOR);
  3058. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3059. "SDE_SSPP_SKY_COLOR_V",
  3060. psde->pipe_sblk->memcolor_blk.version >> 16);
  3061. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3062. PLANE_PROP_SKY_COLOR);
  3063. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3064. "SDE_SSPP_FOLIAGE_COLOR_V",
  3065. psde->pipe_sblk->memcolor_blk.version >> 16);
  3066. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3067. PLANE_PROP_FOLIAGE_COLOR);
  3068. }
  3069. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3070. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3071. "SDE_VIG_3D_LUT_GAMUT_V",
  3072. psde->pipe_sblk->gamut_blk.version >> 16);
  3073. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3074. PLANE_PROP_VIG_GAMUT);
  3075. }
  3076. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3077. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3078. "SDE_VIG_1D_LUT_IGC_V",
  3079. psde->pipe_sblk->igc_blk[0].version >> 16);
  3080. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3081. PLANE_PROP_VIG_IGC);
  3082. }
  3083. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3084. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3085. "SDE_DGM_1D_LUT_IGC_V",
  3086. psde->pipe_sblk->igc_blk[0].version >> 16);
  3087. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3088. PLANE_PROP_DMA_IGC);
  3089. }
  3090. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3091. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3092. "SDE_DGM_1D_LUT_GC_V",
  3093. psde->pipe_sblk->gc_blk[0].version >> 16);
  3094. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3095. PLANE_PROP_DMA_GC);
  3096. }
  3097. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3098. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3099. "SDE_SSPP_FP16_IGC_V",
  3100. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3101. msm_property_install_range(&psde->property_info, feature_name,
  3102. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3103. }
  3104. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3105. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3106. "SDE_SSPP_FP16_GC_V",
  3107. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3108. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3109. PLANE_PROP_FP16_GC);
  3110. }
  3111. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3112. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3113. "SDE_SSPP_FP16_CSC_V",
  3114. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3115. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3116. PLANE_PROP_FP16_CSC);
  3117. }
  3118. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3119. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3120. "SDE_SSPP_FP16_UNMULT_V",
  3121. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3122. msm_property_install_range(&psde->property_info, feature_name,
  3123. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3124. }
  3125. }
  3126. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3127. u32 master_plane_id, struct sde_kms_info *info,
  3128. struct sde_mdss_cfg *catalog)
  3129. {
  3130. bool is_master = !psde->is_virtual;
  3131. const struct sde_format_extended *format_list;
  3132. u32 index;
  3133. int pipe_id;
  3134. if (is_master) {
  3135. format_list = psde->pipe_sblk->format_list;
  3136. } else {
  3137. format_list = psde->pipe_sblk->virt_format_list;
  3138. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3139. master_plane_id);
  3140. }
  3141. if (format_list) {
  3142. sde_kms_info_start(info, "pixel_formats");
  3143. while (format_list->fourcc_format) {
  3144. sde_kms_info_append_format(info,
  3145. format_list->fourcc_format,
  3146. format_list->modifier);
  3147. ++format_list;
  3148. }
  3149. sde_kms_info_stop(info);
  3150. }
  3151. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3152. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3153. sde_kms_info_add_keyint(info, "max_linewidth",
  3154. psde->pipe_sblk->maxlinewidth);
  3155. sde_kms_info_add_keyint(info, "max_upscale",
  3156. psde->pipe_sblk->maxupscale);
  3157. sde_kms_info_add_keyint(info, "max_downscale",
  3158. psde->pipe_sblk->maxdwnscale);
  3159. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3160. psde->pipe_sblk->maxhdeciexp);
  3161. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3162. psde->pipe_sblk->maxvdeciexp);
  3163. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3164. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3165. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3166. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3167. if (psde->pipe <= SSPP_VIG3 && psde->pipe >= SSPP_VIG0)
  3168. pipe_id = psde->pipe - SSPP_VIG0;
  3169. else if (psde->pipe <= SSPP_RGB3 && psde->pipe >= SSPP_RGB0)
  3170. pipe_id = psde->pipe - SSPP_RGB0;
  3171. else if (psde->pipe <= SSPP_DMA3 && psde->pipe >= SSPP_DMA0)
  3172. pipe_id = psde->pipe - SSPP_DMA0;
  3173. else
  3174. pipe_id = -1;
  3175. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3176. index = (master_plane_id == 0) ? 0 : 1;
  3177. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3178. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3179. sde_kms_info_add_keyint(info, "demura_block", index);
  3180. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3181. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3182. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3183. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3184. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3185. const struct sde_format_extended *inline_rot_fmt_list;
  3186. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3187. catalog->true_inline_rot_rev);
  3188. sde_kms_info_add_keyint(info,
  3189. "true_inline_dwnscale_rt",
  3190. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3191. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3192. sde_kms_info_add_keyint(info,
  3193. "true_inline_dwnscale_rt_numerator",
  3194. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3195. sde_kms_info_add_keyint(info,
  3196. "true_inline_dwnscale_rt_denominator",
  3197. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3198. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3199. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3200. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3201. psde->pipe_sblk->in_rot_maxheight);
  3202. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3203. if (inline_rot_fmt_list) {
  3204. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3205. while (inline_rot_fmt_list->fourcc_format) {
  3206. sde_kms_info_append_format(info,
  3207. inline_rot_fmt_list->fourcc_format,
  3208. inline_rot_fmt_list->modifier);
  3209. ++inline_rot_fmt_list;
  3210. }
  3211. sde_kms_info_stop(info);
  3212. }
  3213. }
  3214. }
  3215. /* helper to install properties which are common to planes and crtcs */
  3216. static void _sde_plane_install_properties(struct drm_plane *plane,
  3217. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3218. {
  3219. static const struct drm_prop_enum_list e_blend_op[] = {
  3220. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3221. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3222. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3223. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3224. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3225. };
  3226. static const struct drm_prop_enum_list e_src_config[] = {
  3227. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3228. };
  3229. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3230. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3231. {SDE_DRM_FB_SEC, "sec"},
  3232. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3233. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3234. };
  3235. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3236. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3237. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3238. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3239. };
  3240. struct sde_kms_info *info;
  3241. struct sde_plane *psde = to_sde_plane(plane);
  3242. bool is_master;
  3243. int zpos_max = 255;
  3244. int zpos_def = 0;
  3245. if (!plane || !psde) {
  3246. SDE_ERROR("invalid plane\n");
  3247. return;
  3248. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3249. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3250. !psde->pipe_hw, !psde->pipe_sblk);
  3251. return;
  3252. } else if (!catalog) {
  3253. SDE_ERROR("invalid catalog\n");
  3254. return;
  3255. }
  3256. psde->catalog = catalog;
  3257. is_master = !psde->is_virtual;
  3258. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3259. if (!info) {
  3260. SDE_ERROR("failed to allocate info memory\n");
  3261. return;
  3262. }
  3263. if (sde_is_custom_client()) {
  3264. if (catalog->mixer_count &&
  3265. catalog->mixer[0].sblk->maxblendstages) {
  3266. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3267. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3268. (zpos_max > SDE_STAGE_MAX - 1))
  3269. zpos_max = SDE_STAGE_MAX - 1;
  3270. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3271. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3272. }
  3273. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3274. /* reserve zpos == 0 for primary planes */
  3275. zpos_def = drm_plane_index(plane) + 1;
  3276. }
  3277. msm_property_install_range(&psde->property_info, "zpos",
  3278. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3279. msm_property_install_range(&psde->property_info, "alpha",
  3280. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3281. /* linux default file descriptor range on each process */
  3282. msm_property_install_range(&psde->property_info, "input_fence",
  3283. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3284. if (is_master)
  3285. _sde_plane_install_master_only_properties(psde);
  3286. else
  3287. msm_property_install_enum(&psde->property_info,
  3288. "multirect_mode", 0x0, 0, e_multirect_mode,
  3289. ARRAY_SIZE(e_multirect_mode), 0,
  3290. PLANE_PROP_MULTIRECT_MODE);
  3291. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3292. msm_property_install_volatile_range(&psde->property_info,
  3293. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3294. sde_plane_rot_install_properties(plane, catalog);
  3295. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3296. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3297. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3298. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3299. PLANE_PROP_SRC_CONFIG);
  3300. if (psde->pipe_hw->ops.setup_solidfill)
  3301. msm_property_install_range(&psde->property_info, "color_fill",
  3302. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3303. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3304. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3305. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3306. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3307. msm_property_install_blob(&psde->property_info, "capabilities",
  3308. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3309. sde_kms_info_reset(info);
  3310. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3311. catalog);
  3312. _sde_plane_install_colorproc_properties(psde, info);
  3313. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3314. info->data, SDE_KMS_INFO_DATALEN(info),
  3315. PLANE_PROP_INFO);
  3316. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3317. 0x0, 0, e_fb_translation_mode,
  3318. ARRAY_SIZE(e_fb_translation_mode), 0,
  3319. PLANE_PROP_FB_TRANSLATION_MODE);
  3320. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3321. msm_property_install_range(&psde->property_info, "ubwc_stats_roi",
  3322. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_UBWC_STATS_ROI);
  3323. kfree(info);
  3324. }
  3325. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3326. void __user *usr_ptr)
  3327. {
  3328. struct sde_drm_csc_v1 csc_v1;
  3329. int i;
  3330. if (!psde) {
  3331. SDE_ERROR("invalid plane\n");
  3332. return;
  3333. }
  3334. psde->csc_usr_ptr = NULL;
  3335. if (!usr_ptr) {
  3336. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3337. return;
  3338. }
  3339. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3340. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3341. return;
  3342. }
  3343. /* populate from user space */
  3344. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3345. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3346. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3347. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3348. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3349. }
  3350. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3351. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3352. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3353. }
  3354. psde->csc_usr_ptr = &psde->csc_cfg;
  3355. }
  3356. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3357. struct sde_plane_state *pstate, void __user *usr)
  3358. {
  3359. struct sde_drm_scaler_v1 scale_v1;
  3360. struct sde_hw_pixel_ext *pe;
  3361. int i;
  3362. if (!psde || !pstate) {
  3363. SDE_ERROR("invalid argument(s)\n");
  3364. return;
  3365. }
  3366. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3367. if (!usr) {
  3368. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3369. return;
  3370. }
  3371. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3372. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3373. return;
  3374. }
  3375. /* force property to be dirty, even if the pointer didn't change */
  3376. msm_property_set_dirty(&psde->property_info,
  3377. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3378. /* populate from user space */
  3379. pe = &pstate->pixel_ext;
  3380. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3381. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3382. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3383. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3384. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3385. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3386. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3387. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3388. }
  3389. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3390. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3391. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3392. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3393. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3394. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3395. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3396. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3397. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3398. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3399. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3400. }
  3401. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3402. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3403. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3404. }
  3405. static void _sde_plane_clear_predownscale_settings(
  3406. struct sde_plane_state *pstate)
  3407. {
  3408. pstate->pre_down.pre_downscale_x_0 = 0;
  3409. pstate->pre_down.pre_downscale_x_1 = 0;
  3410. pstate->pre_down.pre_downscale_y_0 = 0;
  3411. pstate->pre_down.pre_downscale_y_1 = 0;
  3412. }
  3413. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3414. struct sde_plane_state *pstate, void __user *usr)
  3415. {
  3416. struct sde_drm_scaler_v2 scale_v2;
  3417. struct sde_hw_pixel_ext *pe;
  3418. int i;
  3419. struct sde_hw_scaler3_cfg *cfg;
  3420. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3421. if (!psde || !pstate) {
  3422. SDE_ERROR("invalid argument(s)\n");
  3423. return;
  3424. }
  3425. cfg = &pstate->scaler3_cfg;
  3426. pd_cfg = &pstate->pre_down;
  3427. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3428. if (!usr) {
  3429. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3430. cfg->enable = 0;
  3431. _sde_plane_clear_predownscale_settings(pstate);
  3432. goto end;
  3433. }
  3434. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3435. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3436. return;
  3437. }
  3438. /* detach/ignore user data if 'disabled' */
  3439. if (!scale_v2.enable) {
  3440. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3441. cfg->enable = 0;
  3442. _sde_plane_clear_predownscale_settings(pstate);
  3443. goto end;
  3444. }
  3445. /* populate from user space */
  3446. sde_set_scaler_v2(cfg, &scale_v2);
  3447. if (_sde_plane_has_pre_downscale(psde)) {
  3448. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3449. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3450. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3451. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3452. }
  3453. pe = &pstate->pixel_ext;
  3454. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3455. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3456. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3457. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3458. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3459. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3460. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3461. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3462. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3463. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3464. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3465. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3466. }
  3467. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3468. end:
  3469. /* force property to be dirty, even if the pointer didn't change */
  3470. msm_property_set_dirty(&psde->property_info,
  3471. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3472. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3473. cfg->src_width[0], cfg->src_height[0],
  3474. cfg->dst_width, cfg->dst_height);
  3475. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3476. }
  3477. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3478. struct sde_plane_state *pstate, void __user *usr_ptr)
  3479. {
  3480. struct drm_clip_rect excl_rect_v1;
  3481. if (!psde || !pstate) {
  3482. SDE_ERROR("invalid argument(s)\n");
  3483. return;
  3484. }
  3485. if (!usr_ptr) {
  3486. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3487. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3488. return;
  3489. }
  3490. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3491. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3492. return;
  3493. }
  3494. /* populate from user space */
  3495. pstate->excl_rect.x = excl_rect_v1.x1;
  3496. pstate->excl_rect.y = excl_rect_v1.y1;
  3497. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3498. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3499. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3500. pstate->excl_rect.x, pstate->excl_rect.y,
  3501. pstate->excl_rect.w, pstate->excl_rect.h);
  3502. }
  3503. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3504. struct sde_plane_state *pstate, uint64_t roi)
  3505. {
  3506. uint16_t y0, y1;
  3507. if (!psde || !pstate) {
  3508. SDE_ERROR("invalid argument(s)\n");
  3509. return;
  3510. }
  3511. y0 = roi & 0xFFFF;
  3512. y1 = (roi >> 0x10) & 0xFFFF;
  3513. if (y0 > psde->pipe_cfg.src_rect.h || y1 > psde->pipe_cfg.src_rect.h) {
  3514. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3515. y0, y1, psde->pipe_cfg.src_rect.h);
  3516. y0 = 0;
  3517. y1 = 0;
  3518. }
  3519. pstate->ubwc_stats_roi.y_coord0 = y0;
  3520. pstate->ubwc_stats_roi.y_coord1 = y1;
  3521. }
  3522. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3523. struct drm_plane_state *state, struct drm_property *property,
  3524. uint64_t val)
  3525. {
  3526. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3527. struct sde_plane_state *pstate;
  3528. int idx, ret = -EINVAL;
  3529. SDE_DEBUG_PLANE(psde, "\n");
  3530. if (!plane) {
  3531. SDE_ERROR("invalid plane\n");
  3532. } else if (!state) {
  3533. SDE_ERROR_PLANE(psde, "invalid state\n");
  3534. } else {
  3535. pstate = to_sde_plane_state(state);
  3536. ret = msm_property_atomic_set(&psde->property_info,
  3537. &pstate->property_state, property, val);
  3538. if (!ret) {
  3539. idx = msm_property_index(&psde->property_info,
  3540. property);
  3541. switch (idx) {
  3542. case PLANE_PROP_INPUT_FENCE:
  3543. _sde_plane_set_input_fence(psde, pstate, val);
  3544. break;
  3545. case PLANE_PROP_CSC_V1:
  3546. case PLANE_PROP_CSC_DMA_V1:
  3547. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3548. break;
  3549. case PLANE_PROP_SCALER_V1:
  3550. _sde_plane_set_scaler_v1(psde, pstate,
  3551. (void *)(uintptr_t)val);
  3552. break;
  3553. case PLANE_PROP_SCALER_V2:
  3554. _sde_plane_set_scaler_v2(psde, pstate,
  3555. (void *)(uintptr_t)val);
  3556. break;
  3557. case PLANE_PROP_EXCL_RECT_V1:
  3558. _sde_plane_set_excl_rect_v1(psde, pstate,
  3559. (void *)(uintptr_t)val);
  3560. break;
  3561. case PLANE_PROP_UBWC_STATS_ROI:
  3562. _sde_plane_set_ubwc_stats_roi(psde, pstate, val);
  3563. break;
  3564. default:
  3565. /* nothing to do */
  3566. break;
  3567. }
  3568. }
  3569. }
  3570. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3571. property->name, property->base.id, val, ret);
  3572. return ret;
  3573. }
  3574. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3575. const struct drm_plane_state *state,
  3576. struct drm_property *property, uint64_t *val)
  3577. {
  3578. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3579. struct sde_plane_state *pstate;
  3580. int ret = -EINVAL;
  3581. if (!plane) {
  3582. SDE_ERROR("invalid plane\n");
  3583. } else if (!state) {
  3584. SDE_ERROR("invalid state\n");
  3585. } else {
  3586. SDE_DEBUG_PLANE(psde, "\n");
  3587. pstate = to_sde_plane_state(state);
  3588. ret = msm_property_atomic_get(&psde->property_info,
  3589. &pstate->property_state, property, val);
  3590. }
  3591. return ret;
  3592. }
  3593. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3594. struct drm_plane_state *plane_state)
  3595. {
  3596. struct sde_plane *psde;
  3597. struct sde_plane_state *pstate;
  3598. struct drm_property *drm_prop;
  3599. enum msm_mdp_plane_property prop_idx;
  3600. if (!plane || !plane_state) {
  3601. SDE_ERROR("invalid params\n");
  3602. return -EINVAL;
  3603. }
  3604. psde = to_sde_plane(plane);
  3605. pstate = to_sde_plane_state(plane_state);
  3606. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3607. uint64_t val = pstate->property_values[prop_idx].value;
  3608. uint64_t def;
  3609. int ret;
  3610. drm_prop = msm_property_index_to_drm_property(
  3611. &psde->property_info, prop_idx);
  3612. if (!drm_prop) {
  3613. /* not all props will be installed, based on caps */
  3614. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3615. prop_idx);
  3616. continue;
  3617. }
  3618. def = msm_property_get_default(&psde->property_info, prop_idx);
  3619. if (val == def)
  3620. continue;
  3621. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3622. drm_prop->name, prop_idx, val, def);
  3623. ret = sde_plane_atomic_set_property(plane, plane_state,
  3624. drm_prop, def);
  3625. if (ret) {
  3626. SDE_ERROR_PLANE(psde,
  3627. "set property failed, idx %d ret %d\n",
  3628. prop_idx, ret);
  3629. continue;
  3630. }
  3631. }
  3632. return 0;
  3633. }
  3634. static void sde_plane_destroy(struct drm_plane *plane)
  3635. {
  3636. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3637. SDE_DEBUG_PLANE(psde, "\n");
  3638. if (psde) {
  3639. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3640. if (psde->blob_info)
  3641. drm_property_blob_put(psde->blob_info);
  3642. msm_property_destroy(&psde->property_info);
  3643. mutex_destroy(&psde->lock);
  3644. /* this will destroy the states as well */
  3645. drm_plane_cleanup(plane);
  3646. if (psde->pipe_hw)
  3647. sde_hw_sspp_destroy(psde->pipe_hw);
  3648. kfree(psde);
  3649. }
  3650. }
  3651. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3652. {
  3653. struct sde_plane_state *pstate;
  3654. if (!state) {
  3655. SDE_ERROR("invalid arg state %d\n", !state);
  3656. return;
  3657. }
  3658. pstate = to_sde_plane_state(state);
  3659. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3660. SDE_DRM_FB_SEC) {
  3661. /* remove ref count for frame buffers */
  3662. if (state->fb) {
  3663. drm_framebuffer_put(state->fb);
  3664. state->fb = NULL;
  3665. }
  3666. }
  3667. }
  3668. static void sde_plane_destroy_state(struct drm_plane *plane,
  3669. struct drm_plane_state *state)
  3670. {
  3671. struct sde_plane *psde;
  3672. struct sde_plane_state *pstate;
  3673. if (!plane || !state) {
  3674. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3675. !plane, !state);
  3676. return;
  3677. }
  3678. psde = to_sde_plane(plane);
  3679. pstate = to_sde_plane_state(state);
  3680. SDE_DEBUG_PLANE(psde, "\n");
  3681. /* remove ref count for frame buffers */
  3682. if (state->fb)
  3683. drm_framebuffer_put(state->fb);
  3684. /* remove ref count for fence */
  3685. if (pstate->input_fence)
  3686. sde_sync_put(pstate->input_fence);
  3687. pstate->input_fence = 0;
  3688. /* destroy value helper */
  3689. msm_property_destroy_state(&psde->property_info, pstate,
  3690. &pstate->property_state);
  3691. }
  3692. static struct drm_plane_state *
  3693. sde_plane_duplicate_state(struct drm_plane *plane)
  3694. {
  3695. struct sde_plane *psde;
  3696. struct sde_plane_state *pstate;
  3697. struct sde_plane_state *old_state;
  3698. struct drm_property *drm_prop;
  3699. uint64_t input_fence_default;
  3700. if (!plane) {
  3701. SDE_ERROR("invalid plane\n");
  3702. return NULL;
  3703. } else if (!plane->state) {
  3704. SDE_ERROR("invalid plane state\n");
  3705. return NULL;
  3706. }
  3707. old_state = to_sde_plane_state(plane->state);
  3708. psde = to_sde_plane(plane);
  3709. if (old_state->cont_splash_populated) {
  3710. plane->state->crtc = NULL;
  3711. old_state->cont_splash_populated = false;
  3712. }
  3713. pstate = msm_property_alloc_state(&psde->property_info);
  3714. if (!pstate) {
  3715. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3716. return NULL;
  3717. }
  3718. SDE_DEBUG_PLANE(psde, "\n");
  3719. /* duplicate value helper */
  3720. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3721. &pstate->property_state, pstate->property_values);
  3722. /* clear out any input fence */
  3723. pstate->input_fence = 0;
  3724. input_fence_default = msm_property_get_default(
  3725. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3726. drm_prop = msm_property_index_to_drm_property(
  3727. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3728. if (msm_property_atomic_set(&psde->property_info,
  3729. &pstate->property_state, drm_prop,
  3730. input_fence_default))
  3731. SDE_DEBUG_PLANE(psde,
  3732. "error clearing duplicated input fence\n");
  3733. pstate->dirty = 0x0;
  3734. pstate->pending = false;
  3735. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3736. /* reset layout offset */
  3737. if (pstate->layout_offset) {
  3738. if (pstate->layout_offset > 0)
  3739. pstate->base.crtc_x += pstate->layout_offset;
  3740. pstate->layout = SDE_LAYOUT_NONE;
  3741. pstate->layout_offset = 0;
  3742. }
  3743. return &pstate->base;
  3744. }
  3745. static void sde_plane_reset(struct drm_plane *plane)
  3746. {
  3747. struct sde_plane *psde;
  3748. struct sde_plane_state *pstate;
  3749. if (!plane) {
  3750. SDE_ERROR("invalid plane\n");
  3751. return;
  3752. }
  3753. psde = to_sde_plane(plane);
  3754. SDE_DEBUG_PLANE(psde, "\n");
  3755. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3756. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3757. return;
  3758. }
  3759. /* remove previous state, if present */
  3760. if (plane->state) {
  3761. sde_plane_destroy_state(plane, plane->state);
  3762. plane->state = 0;
  3763. }
  3764. pstate = msm_property_alloc_state(&psde->property_info);
  3765. if (!pstate) {
  3766. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3767. return;
  3768. }
  3769. /* reset value helper */
  3770. msm_property_reset_state(&psde->property_info, pstate,
  3771. &pstate->property_state,
  3772. pstate->property_values);
  3773. pstate->base.plane = plane;
  3774. plane->state = &pstate->base;
  3775. }
  3776. void sde_plane_get_frame_data(struct drm_plane *plane,
  3777. struct sde_drm_plane_frame_data *data)
  3778. {
  3779. struct sde_plane *psde;
  3780. struct sde_plane_state *pstate;
  3781. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3782. if (!plane) {
  3783. SDE_ERROR("invalid plane\n");
  3784. return;
  3785. }
  3786. psde = to_sde_plane(plane);
  3787. pstate = to_sde_plane_state(plane->state);
  3788. ubwc_stats = &data->ubwc_stats;
  3789. data->plane_id = DRMID(plane);
  3790. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3791. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3792. sizeof(struct sde_drm_ubwc_stats_roi));
  3793. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3794. pstate->multirect_index, ubwc_stats);
  3795. }
  3796. if (psde->pipe_hw->ops.get_ubwc_error)
  3797. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3798. pstate->multirect_index);
  3799. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3800. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3801. if (psde->pipe_hw->ops.get_meta_error)
  3802. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3803. pstate->multirect_index);
  3804. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3805. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3806. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3807. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3808. SDE_EVTLOG_ERROR);
  3809. SDE_DEBUG_PLANE(psde, "plane%d ubwc_error %d meta_error %d\n",
  3810. ubwc_stats->error, ubwc_stats->meta_error);
  3811. }
  3812. }
  3813. #ifdef CONFIG_DEBUG_FS
  3814. static ssize_t _sde_plane_danger_read(struct file *file,
  3815. char __user *buff, size_t count, loff_t *ppos)
  3816. {
  3817. struct sde_kms *kms = file->private_data;
  3818. struct sde_mdss_cfg *cfg = kms->catalog;
  3819. int len = 0;
  3820. char buf[40] = {'\0'};
  3821. if (!cfg)
  3822. return -ENODEV;
  3823. if (*ppos)
  3824. return 0; /* the end */
  3825. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3826. if (len < 0 || len >= sizeof(buf))
  3827. return 0;
  3828. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3829. return -EFAULT;
  3830. *ppos += len; /* increase offset */
  3831. return len;
  3832. }
  3833. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3834. {
  3835. struct drm_plane *plane;
  3836. drm_for_each_plane(plane, kms->dev) {
  3837. if (plane->fb && plane->state) {
  3838. sde_plane_danger_signal_ctrl(plane, enable);
  3839. SDE_DEBUG("plane:%d img:%dx%d ",
  3840. plane->base.id, plane->fb->width,
  3841. plane->fb->height);
  3842. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3843. plane->state->src_x >> 16,
  3844. plane->state->src_y >> 16,
  3845. plane->state->src_w >> 16,
  3846. plane->state->src_h >> 16,
  3847. plane->state->crtc_x, plane->state->crtc_y,
  3848. plane->state->crtc_w, plane->state->crtc_h);
  3849. } else {
  3850. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3851. }
  3852. }
  3853. }
  3854. static ssize_t _sde_plane_danger_write(struct file *file,
  3855. const char __user *user_buf, size_t count, loff_t *ppos)
  3856. {
  3857. struct sde_kms *kms = file->private_data;
  3858. struct sde_mdss_cfg *cfg = kms->catalog;
  3859. int disable_panic;
  3860. char buf[10];
  3861. if (!cfg)
  3862. return -EFAULT;
  3863. if (count >= sizeof(buf))
  3864. return -EFAULT;
  3865. if (copy_from_user(buf, user_buf, count))
  3866. return -EFAULT;
  3867. buf[count] = 0; /* end of string */
  3868. if (kstrtoint(buf, 0, &disable_panic))
  3869. return -EFAULT;
  3870. if (disable_panic) {
  3871. /* Disable panic signal for all active pipes */
  3872. SDE_DEBUG("Disabling danger:\n");
  3873. _sde_plane_set_danger_state(kms, false);
  3874. kms->has_danger_ctrl = false;
  3875. } else {
  3876. /* Enable panic signal for all active pipes */
  3877. SDE_DEBUG("Enabling danger:\n");
  3878. kms->has_danger_ctrl = true;
  3879. _sde_plane_set_danger_state(kms, true);
  3880. }
  3881. return count;
  3882. }
  3883. static const struct file_operations sde_plane_danger_enable = {
  3884. .open = simple_open,
  3885. .read = _sde_plane_danger_read,
  3886. .write = _sde_plane_danger_write,
  3887. };
  3888. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3889. {
  3890. struct sde_plane *psde;
  3891. struct sde_kms *kms;
  3892. struct msm_drm_private *priv;
  3893. const struct sde_sspp_sub_blks *sblk = 0;
  3894. const struct sde_sspp_cfg *cfg = 0;
  3895. if (!plane || !plane->dev) {
  3896. SDE_ERROR("invalid arguments\n");
  3897. return -EINVAL;
  3898. }
  3899. priv = plane->dev->dev_private;
  3900. if (!priv || !priv->kms) {
  3901. SDE_ERROR("invalid KMS reference\n");
  3902. return -EINVAL;
  3903. }
  3904. kms = to_sde_kms(priv->kms);
  3905. psde = to_sde_plane(plane);
  3906. if (psde && psde->pipe_hw)
  3907. cfg = psde->pipe_hw->cap;
  3908. if (cfg)
  3909. sblk = cfg->sblk;
  3910. if (!sblk)
  3911. return 0;
  3912. /* create overall sub-directory for the pipe */
  3913. psde->debugfs_root =
  3914. debugfs_create_dir(psde->pipe_name,
  3915. plane->dev->primary->debugfs_root);
  3916. if (!psde->debugfs_root)
  3917. return -ENOMEM;
  3918. /* don't error check these */
  3919. debugfs_create_x64("features", 0400,
  3920. psde->debugfs_root, &psde->features);
  3921. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3922. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3923. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3924. debugfs_create_bool("default_scaling",
  3925. 0600,
  3926. psde->debugfs_root,
  3927. &psde->debugfs_default_scale);
  3928. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3929. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3930. 0600,
  3931. psde->debugfs_root,
  3932. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3933. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3934. 0600,
  3935. psde->debugfs_root,
  3936. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3937. debugfs_create_u32("in_rot_max_downscale_nrt",
  3938. 0600,
  3939. psde->debugfs_root,
  3940. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3941. debugfs_create_u32("in_rot_max_height",
  3942. 0600,
  3943. psde->debugfs_root,
  3944. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3945. }
  3946. debugfs_create_u32("xin_id",
  3947. 0400,
  3948. psde->debugfs_root,
  3949. (u32 *) &cfg->xin_id);
  3950. debugfs_create_x32("creq_vblank",
  3951. 0600,
  3952. psde->debugfs_root,
  3953. (u32 *) &sblk->creq_vblank);
  3954. debugfs_create_x32("danger_vblank",
  3955. 0600,
  3956. psde->debugfs_root,
  3957. (u32 *) &sblk->danger_vblank);
  3958. debugfs_create_file("disable_danger",
  3959. 0600,
  3960. psde->debugfs_root,
  3961. kms, &sde_plane_danger_enable);
  3962. return 0;
  3963. }
  3964. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3965. {
  3966. struct sde_plane *psde;
  3967. if (!plane)
  3968. return;
  3969. psde = to_sde_plane(plane);
  3970. debugfs_remove_recursive(psde->debugfs_root);
  3971. }
  3972. #else
  3973. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3974. {
  3975. return 0;
  3976. }
  3977. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3978. {
  3979. }
  3980. #endif
  3981. static int sde_plane_late_register(struct drm_plane *plane)
  3982. {
  3983. return _sde_plane_init_debugfs(plane);
  3984. }
  3985. static void sde_plane_early_unregister(struct drm_plane *plane)
  3986. {
  3987. _sde_plane_destroy_debugfs(plane);
  3988. }
  3989. static const struct drm_plane_funcs sde_plane_funcs = {
  3990. .update_plane = drm_atomic_helper_update_plane,
  3991. .disable_plane = drm_atomic_helper_disable_plane,
  3992. .destroy = sde_plane_destroy,
  3993. .atomic_set_property = sde_plane_atomic_set_property,
  3994. .atomic_get_property = sde_plane_atomic_get_property,
  3995. .reset = sde_plane_reset,
  3996. .atomic_duplicate_state = sde_plane_duplicate_state,
  3997. .atomic_destroy_state = sde_plane_destroy_state,
  3998. .late_register = sde_plane_late_register,
  3999. .early_unregister = sde_plane_early_unregister,
  4000. };
  4001. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4002. .prepare_fb = sde_plane_prepare_fb,
  4003. .cleanup_fb = sde_plane_cleanup_fb,
  4004. .atomic_check = sde_plane_atomic_check,
  4005. .atomic_update = sde_plane_atomic_update,
  4006. };
  4007. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4008. {
  4009. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4010. }
  4011. bool is_sde_plane_virtual(struct drm_plane *plane)
  4012. {
  4013. return plane ? to_sde_plane(plane)->is_virtual : false;
  4014. }
  4015. /* initialize plane */
  4016. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4017. uint32_t pipe, bool primary_plane,
  4018. unsigned long possible_crtcs, u32 master_plane_id)
  4019. {
  4020. struct drm_plane *plane = NULL, *master_plane = NULL;
  4021. const struct sde_format_extended *format_list;
  4022. struct sde_plane *psde;
  4023. struct msm_drm_private *priv;
  4024. struct sde_kms *kms;
  4025. enum drm_plane_type type;
  4026. struct sde_vbif_clk_client clk_client;
  4027. int ret = -EINVAL;
  4028. if (!dev) {
  4029. SDE_ERROR("[%u]device is NULL\n", pipe);
  4030. goto exit;
  4031. }
  4032. priv = dev->dev_private;
  4033. if (!priv) {
  4034. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4035. goto exit;
  4036. }
  4037. if (!priv->kms) {
  4038. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4039. goto exit;
  4040. }
  4041. kms = to_sde_kms(priv->kms);
  4042. if (!kms->catalog) {
  4043. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4044. goto exit;
  4045. }
  4046. /* create and zero local structure */
  4047. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4048. if (!psde) {
  4049. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4050. ret = -ENOMEM;
  4051. goto exit;
  4052. }
  4053. /* cache local stuff for later */
  4054. plane = &psde->base;
  4055. psde->pipe = pipe;
  4056. psde->is_virtual = (master_plane_id != 0);
  4057. INIT_LIST_HEAD(&psde->mplane_list);
  4058. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4059. if (master_plane) {
  4060. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4061. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4062. }
  4063. /* initialize underlying h/w driver */
  4064. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4065. &clk_client);
  4066. if (IS_ERR(psde->pipe_hw)) {
  4067. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4068. ret = PTR_ERR(psde->pipe_hw);
  4069. goto clean_plane;
  4070. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4071. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4072. goto clean_sspp;
  4073. }
  4074. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4075. ret = sde_vbif_clk_register(kms, &clk_client);
  4076. if (ret) {
  4077. SDE_ERROR("failed to register vbif client %d\n",
  4078. clk_client.clk_ctrl);
  4079. goto clean_sspp;
  4080. }
  4081. }
  4082. /* cache features mask for later */
  4083. psde->features = psde->pipe_hw->cap->features_ext;
  4084. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4085. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4086. if (!psde->pipe_sblk) {
  4087. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4088. goto clean_sspp;
  4089. }
  4090. if (psde->is_virtual)
  4091. format_list = psde->pipe_sblk->virt_format_list;
  4092. else
  4093. format_list = psde->pipe_sblk->format_list;
  4094. psde->nformats = sde_populate_formats(format_list,
  4095. psde->formats,
  4096. 0,
  4097. ARRAY_SIZE(psde->formats));
  4098. if (!psde->nformats) {
  4099. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4100. goto clean_sspp;
  4101. }
  4102. if (psde->features & BIT(SDE_SSPP_CURSOR))
  4103. type = DRM_PLANE_TYPE_CURSOR;
  4104. else if (primary_plane)
  4105. type = DRM_PLANE_TYPE_PRIMARY;
  4106. else
  4107. type = DRM_PLANE_TYPE_OVERLAY;
  4108. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4109. psde->formats, psde->nformats,
  4110. NULL, type, NULL);
  4111. if (ret)
  4112. goto clean_sspp;
  4113. /* Populate static array of plane property flags */
  4114. _sde_plane_map_prop_to_dirty_bits();
  4115. /* success! finalize initialization */
  4116. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4117. msm_property_init(&psde->property_info, &plane->base, dev,
  4118. priv->plane_property, psde->property_data,
  4119. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4120. sizeof(struct sde_plane_state));
  4121. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4122. /* save user friendly pipe name for later */
  4123. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4124. mutex_init(&psde->lock);
  4125. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4126. pipe, plane->base.id, master_plane_id);
  4127. return plane;
  4128. clean_sspp:
  4129. if (psde && psde->pipe_hw)
  4130. sde_hw_sspp_destroy(psde->pipe_hw);
  4131. clean_plane:
  4132. kfree(psde);
  4133. exit:
  4134. return ERR_PTR(ret);
  4135. }
  4136. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4137. {
  4138. struct sde_plane *sde_plane;
  4139. struct sde_plane_state *pstate;
  4140. sde_plane = to_sde_plane(plane);
  4141. pstate = to_sde_plane_state(plane->state);
  4142. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4143. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4144. }