hal_li_generic_api.c 37 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_li_api.h"
  20. #include "hal_li_hw_headers.h"
  21. #include "hal_li_reo.h"
  22. #include "hal_rx.h"
  23. #include "hal_li_rx.h"
  24. #include "hal_tx.h"
  25. #include <hal_api_mon.h>
  26. static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid)
  27. {
  28. /* Return descriptor size corresponding to window size of 2 since
  29. * we set ba_window_size to 2 while setting up REO descriptors as
  30. * a WAR to get 2k jump exception aggregates are received without
  31. * a BA session.
  32. */
  33. if (ba_window_size <= 1) {
  34. if (tid != HAL_NON_QOS_TID)
  35. return sizeof(struct rx_reo_queue) +
  36. sizeof(struct rx_reo_queue_ext);
  37. else
  38. return sizeof(struct rx_reo_queue);
  39. }
  40. if (ba_window_size <= 105)
  41. return sizeof(struct rx_reo_queue) +
  42. sizeof(struct rx_reo_queue_ext);
  43. if (ba_window_size <= 210)
  44. return sizeof(struct rx_reo_queue) +
  45. (2 * sizeof(struct rx_reo_queue_ext));
  46. return sizeof(struct rx_reo_queue) +
  47. (3 * sizeof(struct rx_reo_queue_ext));
  48. }
  49. void hal_set_link_desc_addr_li(void *desc, uint32_t cookie,
  50. qdf_dma_addr_t link_desc_paddr,
  51. uint8_t bm_id)
  52. {
  53. uint32_t *buf_addr = (uint32_t *)desc;
  54. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0,
  55. link_desc_paddr & 0xffffffff);
  56. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  57. (uint64_t)link_desc_paddr >> 32);
  58. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER,
  59. bm_id);
  60. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  61. cookie);
  62. }
  63. void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl,
  64. hal_ring_handle_t hal_ring_hdl)
  65. {
  66. uint8_t *desc_addr;
  67. struct hal_srng_params srng_params;
  68. uint32_t desc_size;
  69. uint32_t num_desc;
  70. hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
  71. desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
  72. desc_size = sizeof(struct tcl_data_cmd);
  73. num_desc = srng_params.num_entries;
  74. while (num_desc) {
  75. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG,
  76. desc_size);
  77. desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
  78. num_desc--;
  79. }
  80. }
  81. /*
  82. * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast
  83. * address
  84. * @nbuf: Network buffer
  85. *
  86. * Returns: flag to indicate whether the nbuf has MC/BC address
  87. */
  88. static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf)
  89. {
  90. uint8_t *buf = qdf_nbuf_data(nbuf);
  91. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  92. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  93. return rx_attn->mcast_bcast;
  94. }
  95. /**
  96. * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV
  97. * @hw_desc_addr: rx tlv desc
  98. *
  99. * Return: pkt decap format
  100. */
  101. static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr)
  102. {
  103. struct rx_msdu_start *rx_msdu_start;
  104. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  105. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  106. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  107. }
  108. /**
  109. * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of
  110. * RX TLVs
  111. * @ buf: pointer the pkt buffer.
  112. * @ dbg_level: log level.
  113. *
  114. * Return: void
  115. */
  116. static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl,
  117. uint8_t *buf, uint8_t dbg_level)
  118. {
  119. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  120. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  121. struct rx_mpdu_start *mpdu_start =
  122. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  123. struct rx_msdu_start *msdu_start =
  124. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  125. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  126. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  127. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  128. hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
  129. hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc);
  130. hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level);
  131. hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
  132. hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level);
  133. hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level);
  134. }
  135. /**
  136. * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV
  137. * @rx_tlv: RX tlv start address in buffer
  138. * @offload_info: Buffer to store the offload info
  139. *
  140. * Return: 0 on success, -EINVAL on failure.
  141. */
  142. static int
  143. hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv,
  144. struct hal_offload_info *offload_info)
  145. {
  146. offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv);
  147. offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv);
  148. offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv);
  149. offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv);
  150. if (offload_info->tcp_proto) {
  151. offload_info->tcp_pure_ack =
  152. HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv);
  153. offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv);
  154. offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv);
  155. offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv);
  156. offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv);
  157. }
  158. return 0;
  159. }
  160. /*
  161. * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
  162. * from rx attention
  163. * @buf: pointer to rx_pkt_tlvs
  164. *
  165. * Return: phy_ppdu_id
  166. */
  167. static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf)
  168. {
  169. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  170. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  171. uint16_t phy_ppdu_id;
  172. phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn);
  173. return phy_ppdu_id;
  174. }
  175. /**
  176. * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
  177. * from rx_msdu_start TLV
  178. *
  179. * @ buf: pointer to the start of RX PKT TLV headers
  180. * Return: msdu length
  181. */
  182. static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf)
  183. {
  184. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  185. struct rx_msdu_start *msdu_start =
  186. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  187. uint32_t msdu_len;
  188. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  189. return msdu_len;
  190. }
  191. /**
  192. * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
  193. *
  194. * @nbuf: Network buffer
  195. * Returns: rx more fragment bit
  196. *
  197. */
  198. static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf)
  199. {
  200. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  201. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  202. uint16_t frame_ctrl = 0;
  203. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  204. return frame_ctrl;
  205. }
  206. /**
  207. * hal_rx_get_proto_params_li() - Get l4 proto values from TLV
  208. * @buf: rx tlv address
  209. * @proto_params: Buffer to store proto parameters
  210. *
  211. * Return: 0 on success.
  212. */
  213. static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params)
  214. {
  215. struct hal_proto_params *param =
  216. (struct hal_proto_params *)proto_params;
  217. param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf);
  218. param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf);
  219. param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf);
  220. return 0;
  221. }
  222. /**
  223. * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV
  224. * @buf: rx tlv start address
  225. * @l3_hdr_offset: buffer to store l3 offset
  226. * @l4_hdr_offset: buffer to store l4 offset
  227. *
  228. * Return: 0 on success.
  229. */
  230. static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset,
  231. uint32_t *l4_hdr_offset)
  232. {
  233. *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf);
  234. *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf);
  235. return 0;
  236. }
  237. /**
  238. * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV
  239. * @buf: rx tlv address
  240. * @pn_num: buffer to store packet number
  241. *
  242. * Return: None
  243. */
  244. static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num)
  245. {
  246. struct rx_pkt_tlvs *rx_pkt_tlv =
  247. (struct rx_pkt_tlvs *)buf;
  248. struct rx_mpdu_info *rx_mpdu_info_details =
  249. &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  250. pn_num[0] = rx_mpdu_info_details->pn_31_0;
  251. pn_num[0] |=
  252. ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32);
  253. pn_num[1] = rx_mpdu_info_details->pn_95_64;
  254. pn_num[1] |=
  255. ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32);
  256. }
  257. #ifdef NO_RX_PKT_HDR_TLV
  258. /**
  259. * hal_rx_pkt_hdr_get_li() - Get rx packet header start address.
  260. * @buf: packet start address
  261. *
  262. * Return: packet data start address.
  263. */
  264. static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
  265. {
  266. return buf + RX_PKT_TLVS_LEN;
  267. }
  268. #else
  269. static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
  270. {
  271. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  272. return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr;
  273. }
  274. #endif
  275. /**
  276. * hal_rx_priv_info_set_in_tlv_li(): Save the private info to
  277. * the reserved bytes of rx_tlv_hdr
  278. * @buf: start of rx_tlv_hdr
  279. * @priv_data: hal_wbm_err_desc_info structure
  280. * @len: length of the private data
  281. * Return: void
  282. */
  283. static inline void
  284. hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data,
  285. uint32_t len)
  286. {
  287. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  288. uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
  289. RX_PADDING0_BYTES : len;
  290. qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len);
  291. }
  292. /**
  293. * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from
  294. * the reserved bytes of rx_tlv_hdr.
  295. * @buf: start of rx_tlv_hdr
  296. * @priv_data: hal_wbm_err_desc_info structure
  297. * @len: length of the private data
  298. * Return: void
  299. */
  300. static inline void
  301. hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data,
  302. uint32_t len)
  303. {
  304. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  305. uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
  306. RX_PADDING0_BYTES : len;
  307. qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len);
  308. }
  309. /**
  310. * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size
  311. * @rx_pkt_tlv_size: TLV size for regular RX packets
  312. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  313. *
  314. * Return: size of rx pkt tlv before the actual data
  315. */
  316. static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size,
  317. uint16_t *rx_mon_pkt_tlv_size)
  318. {
  319. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  320. *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV;
  321. }
  322. /**
  323. * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor
  324. * @ring_desc: ring descriptor
  325. *
  326. * Return: wbm error source
  327. */
  328. uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc)
  329. {
  330. return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc);
  331. }
  332. /**
  333. * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc
  334. * @ring_desc: ring descriptor
  335. *
  336. * Return: rbm
  337. */
  338. uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc)
  339. {
  340. /*
  341. * The following macro takes buf_addr_info as argument,
  342. * but since buf_addr_info is the first field in ring_desc
  343. * Hence the following call is OK
  344. */
  345. return HAL_RX_BUF_RBM_GET(ring_desc);
  346. }
  347. /**
  348. * hal_rx_reo_buf_paddr_get_li: Gets the physical address and
  349. * cookie from the REO destination ring element
  350. *
  351. * @ rx_desc: Opaque cookie pointer used by HAL to get to
  352. * the current descriptor
  353. * @ buf_info: structure to return the buffer information
  354. * Return: void
  355. */
  356. static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc,
  357. struct hal_buf_info *buf_info)
  358. {
  359. struct reo_destination_ring *reo_ring =
  360. (struct reo_destination_ring *)rx_desc;
  361. buf_info->paddr =
  362. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  363. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  364. buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
  365. }
  366. /**
  367. * hal_rx_msdu_link_desc_set_li: Retrieves MSDU Link Descriptor to WBM
  368. *
  369. * @ hal_soc_hdl : HAL version of the SOC pointer
  370. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  371. * @ buf_addr_info : void pointer to the buffer_addr_info
  372. * @ bm_action : put in IDLE list or release to MSDU_LIST
  373. *
  374. * Return: void
  375. */
  376. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  377. static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl,
  378. void *src_srng_desc,
  379. hal_buff_addrinfo_t buf_addr_info,
  380. uint8_t bm_action)
  381. {
  382. /*
  383. * The offsets for fields used in this function are same in
  384. * wbm_release_ring for Lithium and wbm_release_ring_tx
  385. * for Beryllium. hence we can use wbm_release_ring directly.
  386. */
  387. struct wbm_release_ring *wbm_rel_srng =
  388. (struct wbm_release_ring *)src_srng_desc;
  389. uint32_t addr_31_0;
  390. uint8_t addr_39_32;
  391. /* Structure copy !!! */
  392. wbm_rel_srng->released_buff_or_desc_addr_info =
  393. *(struct buffer_addr_info *)buf_addr_info;
  394. addr_31_0 =
  395. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
  396. addr_39_32 =
  397. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
  398. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  399. RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
  400. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION,
  401. bm_action);
  402. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  403. BUFFER_OR_DESC_TYPE,
  404. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
  405. /* WBM error is indicated when any of the link descriptors given to
  406. * WBM has a NULL address, and one those paths is the link descriptors
  407. * released from host after processing RXDMA errors,
  408. * or from Rx defrag path, and we want to add an assert here to ensure
  409. * host is not releasing descriptors with NULL address.
  410. */
  411. if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
  412. hal_dump_wbm_rel_desc(src_srng_desc);
  413. qdf_assert_always(0);
  414. }
  415. }
  416. static
  417. void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl,
  418. hal_buf_info_t buf_info_hdl)
  419. {
  420. struct hal_buf_info *buf_info =
  421. (struct hal_buf_info *)buf_info_hdl;
  422. struct buffer_addr_info *buf_addr_info =
  423. (struct buffer_addr_info *)buf_addr_info_hdl;
  424. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  425. /*
  426. * buffer addr info is the first member of ring desc, so the typecast
  427. * can be done.
  428. */
  429. buf_info->rbm = hal_rx_ret_buf_manager_get_li
  430. ((hal_ring_desc_t)buf_addr_info);
  431. }
  432. /**
  433. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  434. * from the MSDU link descriptor
  435. *
  436. * @ hal_soc_hdl : HAL version of the SOC pointer
  437. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  438. * MSDU link descriptor (struct rx_msdu_link)
  439. *
  440. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  441. *
  442. * @num_msdus: Number of MSDUs in the MPDU
  443. *
  444. * Return: void
  445. */
  446. static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl,
  447. void *msdu_link_desc,
  448. void *hal_msdu_list,
  449. uint16_t *num_msdus)
  450. {
  451. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  452. struct rx_msdu_details *msdu_details;
  453. struct rx_msdu_desc_info *msdu_desc_info;
  454. struct hal_rx_msdu_list *msdu_list = hal_msdu_list;
  455. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  456. int i;
  457. struct hal_buf_info buf_info;
  458. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  459. hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details);
  460. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  461. /* num_msdus received in mpdu descriptor may be incorrect
  462. * sometimes due to HW issue. Check msdu buffer address also
  463. */
  464. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  465. &msdu_details[i].buffer_addr_info_details) == 0))
  466. break;
  467. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  468. &msdu_details[i].buffer_addr_info_details) == 0) {
  469. /* set the last msdu bit in the prev msdu_desc_info */
  470. msdu_desc_info =
  471. hal_rx_msdu_desc_info_get_ptr
  472. (&msdu_details[i - 1], hal_soc);
  473. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  474. break;
  475. }
  476. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  477. hal_soc);
  478. /* set first MSDU bit or the last MSDU bit */
  479. if (!i)
  480. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  481. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  482. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  483. msdu_list->msdu_info[i].msdu_flags =
  484. hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info);
  485. msdu_list->msdu_info[i].msdu_len =
  486. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  487. /* addr field in buf_info will not be valid */
  488. hal_rx_buf_cookie_rbm_get_li(
  489. (uint32_t *)
  490. &msdu_details[i].buffer_addr_info_details,
  491. &buf_info);
  492. msdu_list->sw_cookie[i] = buf_info.sw_cookie;
  493. msdu_list->rbm[i] = buf_info.rbm;
  494. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  495. &msdu_details[i].buffer_addr_info_details) |
  496. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  497. &msdu_details[i].buffer_addr_info_details) << 32;
  498. hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]);
  499. }
  500. *num_msdus = i;
  501. }
  502. /*
  503. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  504. * rxdma ring entry.
  505. * @rxdma_entry: descriptor entry
  506. * @paddr: physical address of nbuf data pointer.
  507. * @cookie: SW cookie used as a index to SW rx desc.
  508. * @manager: who owns the nbuf (host, NSS, etc...).
  509. *
  510. */
  511. static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry,
  512. qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager)
  513. {
  514. uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
  515. uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
  516. HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
  517. HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
  518. HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
  519. HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
  520. }
  521. /**
  522. * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc
  523. * @rx_desc: rx descriptor
  524. *
  525. * Return: REO error code
  526. */
  527. static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc)
  528. {
  529. struct reo_destination_ring *reo_desc =
  530. (struct reo_destination_ring *)rx_desc;
  531. return HAL_RX_REO_ERROR_GET(reo_desc);
  532. }
  533. /**
  534. * hal_gen_reo_remap_val_generic_li() - Generate the reo map value
  535. * @ix0_map: mapping values for reo
  536. *
  537. * Return: IX0 reo remap register value to be written
  538. */
  539. static uint32_t
  540. hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg,
  541. uint8_t *ix0_map)
  542. {
  543. uint32_t ix_val = 0;
  544. switch (remap_reg) {
  545. case HAL_REO_REMAP_REG_IX0:
  546. ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) |
  547. HAL_REO_REMAP_IX0(ix0_map[1], 1) |
  548. HAL_REO_REMAP_IX0(ix0_map[2], 2) |
  549. HAL_REO_REMAP_IX0(ix0_map[3], 3) |
  550. HAL_REO_REMAP_IX0(ix0_map[4], 4) |
  551. HAL_REO_REMAP_IX0(ix0_map[5], 5) |
  552. HAL_REO_REMAP_IX0(ix0_map[6], 6) |
  553. HAL_REO_REMAP_IX0(ix0_map[7], 7);
  554. break;
  555. case HAL_REO_REMAP_REG_IX2:
  556. ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) |
  557. HAL_REO_REMAP_IX2(ix0_map[1], 17) |
  558. HAL_REO_REMAP_IX2(ix0_map[2], 18) |
  559. HAL_REO_REMAP_IX2(ix0_map[3], 19) |
  560. HAL_REO_REMAP_IX2(ix0_map[4], 20) |
  561. HAL_REO_REMAP_IX2(ix0_map[5], 21) |
  562. HAL_REO_REMAP_IX2(ix0_map[6], 22) |
  563. HAL_REO_REMAP_IX2(ix0_map[7], 23);
  564. break;
  565. default:
  566. break;
  567. }
  568. return ix_val;
  569. }
  570. /**
  571. * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag
  572. * @rx_tlv_hdr: start address of rx_tlv_hdr
  573. * @ip_csum_err: buffer to return ip_csum_fail flag
  574. * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag
  575. *
  576. * Return: None
  577. */
  578. static inline void
  579. hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err,
  580. uint32_t *tcp_udp_csum_err)
  581. {
  582. *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr);
  583. *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr);
  584. }
  585. static
  586. void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr,
  587. struct hal_rx_pkt_capture_flags *flags)
  588. {
  589. struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr;
  590. struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn;
  591. struct rx_mpdu_start *mpdu_start =
  592. &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start;
  593. struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end;
  594. struct rx_msdu_start *msdu_start =
  595. &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start;
  596. flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type;
  597. flags->fcs_err = mpdu_end->fcs_err;
  598. flags->fragment_flag = rx_attn->fragment_flag;
  599. flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  600. flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  601. flags->tsft = msdu_start->ppdu_start_timestamp;
  602. }
  603. static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc)
  604. {
  605. return HAL_RX_ERROR_STATUS_GET(rx_desc);
  606. }
  607. static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc)
  608. {
  609. return HAL_RX_REO_BUF_TYPE_GET(rx_desc);
  610. }
  611. static inline bool
  612. hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf)
  613. {
  614. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  615. struct rx_mpdu_start *mpdu_start =
  616. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  617. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  618. bool ampdu_flag;
  619. ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
  620. return ampdu_flag;
  621. }
  622. static
  623. uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr)
  624. {
  625. struct rx_attention *rx_attn;
  626. struct rx_mon_pkt_tlvs *rx_desc =
  627. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  628. rx_attn = &rx_desc->attn_tlv.rx_attn;
  629. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  630. }
  631. static
  632. uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr)
  633. {
  634. struct rx_attention *rx_attn;
  635. struct rx_mon_pkt_tlvs *rx_desc =
  636. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  637. rx_attn = &rx_desc->attn_tlv.rx_attn;
  638. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  639. }
  640. #ifdef NO_RX_PKT_HDR_TLV
  641. static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr)
  642. {
  643. uint8_t *rx_pkt_hdr;
  644. struct rx_mon_pkt_tlvs *rx_desc =
  645. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  646. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  647. return rx_pkt_hdr;
  648. }
  649. #else
  650. static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr)
  651. {
  652. uint8_t *rx_pkt_hdr;
  653. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  654. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  655. return rx_pkt_hdr;
  656. }
  657. #endif
  658. static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr)
  659. {
  660. struct rx_mon_pkt_tlvs *rx_desc =
  661. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  662. uint32_t user_id;
  663. user_id = HAL_RX_GET_USER_TLV32_USERID(
  664. &rx_desc->mpdu_start_tlv);
  665. return user_id;
  666. }
  667. /**
  668. * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length
  669. * from rx_msdu_start TLV
  670. *
  671. * @buf: pointer to the start of RX PKT TLV headers
  672. * @len: msdu length
  673. *
  674. * Return: none
  675. */
  676. static inline void
  677. hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len)
  678. {
  679. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  680. struct rx_msdu_start *msdu_start =
  681. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  682. void *wrd1;
  683. wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET;
  684. *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK);
  685. *(uint32_t *)wrd1 |= len;
  686. }
  687. /*
  688. * hal_rx_tlv_bw_get_li(): API to get the Bandwidth
  689. * Interval from rx_msdu_start
  690. *
  691. * @buf: pointer to the start of RX PKT TLV header
  692. * Return: uint32_t(bw)
  693. */
  694. static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf)
  695. {
  696. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  697. struct rx_msdu_start *msdu_start =
  698. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  699. uint32_t bw;
  700. bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
  701. return bw;
  702. }
  703. /*
  704. * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel
  705. * from rx_msdu_start
  706. *
  707. * @buf: pointer to the start of RX PKT TLV header
  708. * Return: uint32_t(frequency)
  709. */
  710. static inline uint32_t
  711. hal_rx_tlv_get_freq_li(uint8_t *buf)
  712. {
  713. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  714. struct rx_msdu_start *msdu_start =
  715. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  716. uint32_t freq;
  717. freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  718. return freq;
  719. }
  720. /**
  721. * hal_rx_tlv_sgi_get_li(): API to get the Short Gaurd
  722. * Interval from rx_msdu_start TLV
  723. *
  724. * @buf: pointer to the start of RX PKT TLV headers
  725. * Return: uint32_t(sgi)
  726. */
  727. static inline uint32_t
  728. hal_rx_tlv_sgi_get_li(uint8_t *buf)
  729. {
  730. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  731. struct rx_msdu_start *msdu_start =
  732. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  733. uint32_t sgi;
  734. sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
  735. return sgi;
  736. }
  737. /**
  738. * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate
  739. * from rx_msdu_start TLV
  740. *
  741. * @buf: pointer to the start of RX PKT TLV headers
  742. * Return: uint32_t(rate_mcs)
  743. */
  744. static inline uint32_t
  745. hal_rx_tlv_rate_mcs_get_li(uint8_t *buf)
  746. {
  747. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  748. struct rx_msdu_start *msdu_start =
  749. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  750. uint32_t rate_mcs;
  751. rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
  752. return rate_mcs;
  753. }
  754. /*
  755. * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type
  756. * from rx_msdu_start
  757. *
  758. * @buf: pointer to the start of RX PKT TLV header
  759. * Return: uint32_t(pkt type)
  760. */
  761. static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf)
  762. {
  763. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  764. struct rx_msdu_start *msdu_start =
  765. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  766. uint32_t pkt_type;
  767. pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
  768. return pkt_type;
  769. }
  770. /**
  771. * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR
  772. * from rx_mpdu_end TLV
  773. *
  774. * @buf: pointer to the start of RX PKT TLV headers
  775. * Return: uint32_t(mic_err)
  776. */
  777. static inline uint32_t
  778. hal_rx_tlv_mic_err_get_li(uint8_t *buf)
  779. {
  780. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  781. struct rx_mpdu_end *mpdu_end =
  782. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  783. uint32_t mic_err;
  784. mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
  785. return mic_err;
  786. }
  787. /**
  788. * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR
  789. * from rx_mpdu_end TLV
  790. *
  791. * @buf: pointer to the start of RX PKT TLV headers
  792. * Return: uint32_t(decrypt_err)
  793. */
  794. static inline uint32_t
  795. hal_rx_tlv_decrypt_err_get_li(uint8_t *buf)
  796. {
  797. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  798. struct rx_mpdu_end *mpdu_end =
  799. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  800. uint32_t decrypt_err;
  801. decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
  802. return decrypt_err;
  803. }
  804. /*
  805. * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention
  806. * @buf: pointer to rx_pkt_tlvs
  807. *
  808. * reutm: uint32_t(first_msdu)
  809. */
  810. static inline uint32_t
  811. hal_rx_tlv_first_mpdu_get_li(uint8_t *buf)
  812. {
  813. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  814. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  815. uint32_t first_mpdu;
  816. first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
  817. return first_mpdu;
  818. }
  819. /*
  820. * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet
  821. * from rx_msdu_end
  822. *
  823. * @buf: pointer to the start of RX PKT TLV header
  824. * Return: uint32_t(key id)
  825. */
  826. static inline uint8_t
  827. hal_rx_msdu_get_keyid_li(uint8_t *buf)
  828. {
  829. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  830. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  831. uint32_t keyid_octet;
  832. keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
  833. return keyid_octet & 0x3;
  834. }
  835. /*
  836. * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the
  837. * packet from rx_attention
  838. *
  839. * @buf: pointer to the start of RX PKT TLV header
  840. * Return: uint32_t(decryt status)
  841. */
  842. static inline uint32_t
  843. hal_rx_tlv_get_is_decrypted_li(uint8_t *buf)
  844. {
  845. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  846. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  847. uint32_t is_decrypt = 0;
  848. uint32_t decrypt_status;
  849. decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
  850. if (!decrypt_status)
  851. is_decrypt = 1;
  852. return is_decrypt;
  853. }
  854. /**
  855. * hal_rx_msdu_reo_dst_ind_get_li: Gets the REO
  856. * destination ring ID from the msdu desc info
  857. *
  858. * @ hal_soc_hdl : HAL version of the SOC pointer
  859. * @msdu_link_desc : Opaque cookie pointer used by HAL to get to
  860. * the current descriptor
  861. *
  862. * Return: dst_ind (REO destination ring ID)
  863. */
  864. static inline uint32_t
  865. hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl,
  866. void *msdu_link_desc)
  867. {
  868. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  869. struct rx_msdu_details *msdu_details;
  870. struct rx_msdu_desc_info *msdu_desc_info;
  871. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  872. uint32_t dst_ind;
  873. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  874. /* The first msdu in the link should exsist */
  875. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0],
  876. hal_soc);
  877. dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
  878. return dst_ind;
  879. }
  880. static inline void
  881. hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
  882. void *mpdu_desc, uint32_t seq_no)
  883. {
  884. struct rx_mpdu_desc_info *mpdu_desc_info =
  885. (struct rx_mpdu_desc_info *)mpdu_desc;
  886. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  887. MSDU_COUNT, 0x1);
  888. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  889. MPDU_SEQUENCE_NUMBER, seq_no);
  890. /* unset frag bit */
  891. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  892. FRAGMENT_FLAG, 0x0);
  893. /* set sa/da valid bits */
  894. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  895. SA_IS_VALID, 0x1);
  896. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  897. DA_IS_VALID, 0x1);
  898. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  899. RAW_MPDU, 0x0);
  900. }
  901. static inline void
  902. hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
  903. void *msdu_desc, uint32_t dst_ind,
  904. uint32_t nbuf_len)
  905. {
  906. struct rx_msdu_desc_info *msdu_desc_info =
  907. (struct rx_msdu_desc_info *)msdu_desc;
  908. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  909. FIRST_MSDU_IN_MPDU_FLAG, 1);
  910. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  911. LAST_MSDU_IN_MPDU_FLAG, 1);
  912. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  913. MSDU_CONTINUATION, 0x0);
  914. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  915. REO_DESTINATION_INDICATION,
  916. dst_ind);
  917. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  918. MSDU_LENGTH, nbuf_len);
  919. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  920. SA_IS_VALID, 1);
  921. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  922. DA_IS_VALID, 1);
  923. }
  924. static inline
  925. uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc)
  926. {
  927. return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
  928. }
  929. static inline
  930. void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind)
  931. {
  932. HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5,
  933. REO_DESTINATION_INDICATION, dst_ind);
  934. }
  935. static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl,
  936. hal_ring_desc_t reo_desc,
  937. void *st_handle,
  938. uint32_t tlv, int *num_ref)
  939. {
  940. union hal_reo_status *reo_status_ref;
  941. reo_status_ref = (union hal_reo_status *)st_handle;
  942. switch (tlv) {
  943. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  944. hal_reo_queue_stats_status_li(reo_desc,
  945. &reo_status_ref->queue_status,
  946. hal_soc_hdl);
  947. *num_ref = reo_status_ref->queue_status.header.cmd_num;
  948. break;
  949. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  950. hal_reo_flush_queue_status_li(reo_desc,
  951. &reo_status_ref->fl_queue_status,
  952. hal_soc_hdl);
  953. *num_ref = reo_status_ref->fl_queue_status.header.cmd_num;
  954. break;
  955. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  956. hal_reo_flush_cache_status_li(reo_desc,
  957. &reo_status_ref->fl_cache_status,
  958. hal_soc_hdl);
  959. *num_ref = reo_status_ref->fl_cache_status.header.cmd_num;
  960. break;
  961. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  962. hal_reo_unblock_cache_status_li(
  963. reo_desc, hal_soc_hdl,
  964. &reo_status_ref->unblk_cache_status);
  965. *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num;
  966. break;
  967. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  968. hal_reo_flush_timeout_list_status_li(
  969. reo_desc,
  970. &reo_status_ref->fl_timeout_status,
  971. hal_soc_hdl);
  972. *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num;
  973. break;
  974. case HAL_REO_DESC_THRES_STATUS_TLV:
  975. hal_reo_desc_thres_reached_status_li(
  976. reo_desc,
  977. &reo_status_ref->thres_status,
  978. hal_soc_hdl);
  979. *num_ref = reo_status_ref->thres_status.header.cmd_num;
  980. break;
  981. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  982. hal_reo_rx_update_queue_status_li(
  983. reo_desc,
  984. &reo_status_ref->rx_queue_status,
  985. hal_soc_hdl);
  986. *num_ref = reo_status_ref->rx_queue_status.header.cmd_num;
  987. break;
  988. default:
  989. QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN,
  990. "hal_soc %pK: no handler for TLV:%d",
  991. hal_soc_hdl, tlv);
  992. return QDF_STATUS_E_FAILURE;
  993. } /* switch */
  994. return QDF_STATUS_SUCCESS;
  995. }
  996. /**
  997. * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id
  998. * @chip_id: mlo chip_id
  999. *
  1000. * Returns: RBM ID
  1001. */
  1002. static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id)
  1003. {
  1004. return WBM_IDLE_DESC_LIST;
  1005. }
  1006. /**
  1007. * hal_hw_txrx_default_ops_attach_li() - Attach the default hal ops for
  1008. * lithium chipsets.
  1009. * @hal_soc_hdl: HAL soc handle
  1010. *
  1011. * Return: None
  1012. */
  1013. void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc)
  1014. {
  1015. hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li;
  1016. hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li;
  1017. hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li;
  1018. hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li;
  1019. hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li;
  1020. hal_soc->ops->hal_get_reo_reg_base_offset =
  1021. hal_get_reo_reg_base_offset_li;
  1022. hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li;
  1023. hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
  1024. hal_rx_msdu_is_wlan_mcast_generic_li;
  1025. hal_soc->ops->hal_rx_tlv_decap_format_get =
  1026. hal_rx_tlv_decap_format_get_li;
  1027. hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li;
  1028. hal_soc->ops->hal_rx_tlv_get_offload_info =
  1029. hal_rx_tlv_get_offload_info_li;
  1030. hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
  1031. hal_rx_attn_phy_ppdu_id_get_li;
  1032. hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li;
  1033. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1034. hal_rx_msdu_start_msdu_len_get_li;
  1035. hal_soc->ops->hal_rx_get_frame_ctrl_field =
  1036. hal_rx_get_frame_ctrl_field_li;
  1037. hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li;
  1038. hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li;
  1039. hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li;
  1040. hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li;
  1041. hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li;
  1042. hal_soc->ops->hal_rx_ret_buf_manager_get =
  1043. hal_rx_ret_buf_manager_get_li;
  1044. hal_soc->ops->hal_rxdma_buff_addr_info_set =
  1045. hal_rxdma_buff_addr_info_set_li;
  1046. hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li;
  1047. hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li;
  1048. hal_soc->ops->hal_gen_reo_remap_val =
  1049. hal_gen_reo_remap_val_generic_li;
  1050. hal_soc->ops->hal_rx_tlv_csum_err_get =
  1051. hal_rx_tlv_csum_err_get_li;
  1052. hal_soc->ops->hal_rx_mpdu_desc_info_get =
  1053. hal_rx_mpdu_desc_info_get_li;
  1054. hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li;
  1055. hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li;
  1056. hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li;
  1057. hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li;
  1058. hal_soc->ops->hal_rx_priv_info_set_in_tlv =
  1059. hal_rx_priv_info_set_in_tlv_li;
  1060. hal_soc->ops->hal_rx_priv_info_get_from_tlv =
  1061. hal_rx_priv_info_get_from_tlv_li;
  1062. hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
  1063. hal_rx_mpdu_info_ampdu_flag_get_li;
  1064. hal_soc->ops->hal_rx_tlv_mpdu_len_err_get =
  1065. hal_rx_tlv_mpdu_len_err_get_li;
  1066. hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get =
  1067. hal_rx_tlv_mpdu_fcs_err_get_li;
  1068. hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li;
  1069. hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
  1070. hal_rx_tlv_get_pkt_capture_flags_li;
  1071. hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li;
  1072. hal_soc->ops->hal_rx_hw_desc_mpdu_user_id =
  1073. hal_rx_hw_desc_mpdu_user_id_li;
  1074. hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li;
  1075. hal_soc->ops->hal_rx_tlv_msdu_len_set =
  1076. hal_rx_msdu_start_msdu_len_set_li;
  1077. hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li;
  1078. hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li;
  1079. hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li;
  1080. hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li;
  1081. hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li;
  1082. hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
  1083. hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
  1084. hal_soc->ops->hal_rx_tlv_decrypt_err_get =
  1085. hal_rx_tlv_decrypt_err_get_li;
  1086. hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li;
  1087. hal_soc->ops->hal_rx_tlv_get_is_decrypted =
  1088. hal_rx_tlv_get_is_decrypted_li;
  1089. hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li;
  1090. hal_soc->ops->hal_rx_msdu_reo_dst_ind_get =
  1091. hal_rx_msdu_reo_dst_ind_get_li;
  1092. hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li;
  1093. hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li;
  1094. hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li;
  1095. hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li;
  1096. hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
  1097. hal_get_reo_ent_desc_qdesc_addr_li;
  1098. hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li;
  1099. hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
  1100. hal_set_reo_ent_desc_reo_dest_ind_li;
  1101. hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li;
  1102. }