dp_be_rx.c 35 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_be_rx.h"
  24. #include "dp_peer.h"
  25. #include "hal_rx.h"
  26. #include "hal_be_rx.h"
  27. #include "hal_api.h"
  28. #include "hal_be_api.h"
  29. #include "qdf_nbuf.h"
  30. #ifdef MESH_MODE_SUPPORT
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "dp_internal.h"
  34. #include "dp_ipa.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #include "dp_hist.h"
  39. #include "dp_rx_buffer_pool.h"
  40. #ifndef AST_OFFLOAD_ENABLE
  41. static void
  42. dp_rx_wds_learn(struct dp_soc *soc,
  43. struct dp_vdev *vdev,
  44. uint8_t *rx_tlv_hdr,
  45. struct dp_peer *peer,
  46. qdf_nbuf_t nbuf,
  47. struct hal_rx_msdu_metadata msdu_metadata)
  48. {
  49. /* WDS Source Port Learning */
  50. if (qdf_likely(vdev->wds_enabled))
  51. dp_rx_wds_srcport_learn(soc,
  52. rx_tlv_hdr,
  53. peer,
  54. nbuf,
  55. msdu_metadata);
  56. }
  57. #else
  58. #ifdef QCA_SUPPORT_WDS_EXTENDED
  59. /**
  60. * dp_wds_ext_peer_learn_be() - function to send event to control
  61. * path on receiving 1st 4-address frame from backhaul.
  62. * @soc: DP soc
  63. * @ta_peer: WDS repeater peer
  64. * @rx_tlv_hdr : start address of rx tlvs
  65. *
  66. * Return: void
  67. */
  68. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  69. struct dp_peer *ta_peer,
  70. uint8_t *rx_tlv_hdr)
  71. {
  72. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  73. /* instead of checking addr4 is valid or not in per packet path
  74. * check for init bit, which will be set on reception of
  75. * first addr4 valid packet.
  76. */
  77. if (!ta_peer->vdev->wds_ext_enabled ||
  78. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT, &ta_peer->wds_ext.init))
  79. return;
  80. if (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc, rx_tlv_hdr)) {
  81. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  82. &ta_peer->wds_ext.init);
  83. qdf_mem_copy(wds_ext_src_mac, &ta_peer->mac_addr.raw[0],
  84. QDF_MAC_ADDR_SIZE);
  85. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  86. soc->ctrl_psoc,
  87. ta_peer->peer_id,
  88. ta_peer->vdev->vdev_id,
  89. wds_ext_src_mac);
  90. }
  91. }
  92. #else
  93. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  94. struct dp_peer *ta_peer,
  95. uint8_t *rx_tlv_hdr)
  96. {
  97. }
  98. #endif
  99. static void
  100. dp_rx_wds_learn(struct dp_soc *soc,
  101. struct dp_vdev *vdev,
  102. uint8_t *rx_tlv_hdr,
  103. struct dp_peer *ta_peer,
  104. qdf_nbuf_t nbuf,
  105. struct hal_rx_msdu_metadata msdu_metadata)
  106. {
  107. dp_wds_ext_peer_learn_be(soc, ta_peer, rx_tlv_hdr);
  108. }
  109. #endif
  110. /**
  111. * dp_rx_process_be() - Brain of the Rx processing functionality
  112. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  113. * @int_ctx: per interrupt context
  114. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  115. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  116. * @quota: No. of units (packets) that can be serviced in one shot.
  117. *
  118. * This function implements the core of Rx functionality. This is
  119. * expected to handle only non-error frames.
  120. *
  121. * Return: uint32_t: No. of elements processed
  122. */
  123. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  124. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  125. uint32_t quota)
  126. {
  127. hal_ring_desc_t ring_desc;
  128. hal_soc_handle_t hal_soc;
  129. struct dp_rx_desc *rx_desc = NULL;
  130. qdf_nbuf_t nbuf, next;
  131. bool near_full;
  132. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  133. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  134. uint32_t num_pending;
  135. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  136. uint16_t msdu_len = 0;
  137. uint16_t peer_id;
  138. uint8_t vdev_id;
  139. struct dp_peer *peer;
  140. struct dp_vdev *vdev;
  141. uint32_t pkt_len = 0;
  142. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  143. struct hal_rx_msdu_desc_info msdu_desc_info;
  144. enum hal_reo_error_status error;
  145. uint32_t peer_mdata;
  146. uint8_t *rx_tlv_hdr;
  147. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  148. uint8_t mac_id = 0;
  149. struct dp_pdev *rx_pdev;
  150. bool enh_flag;
  151. struct dp_srng *dp_rxdma_srng;
  152. struct rx_desc_pool *rx_desc_pool;
  153. struct dp_soc *soc = int_ctx->soc;
  154. uint8_t core_id = 0;
  155. struct cdp_tid_rx_stats *tid_stats;
  156. qdf_nbuf_t nbuf_head;
  157. qdf_nbuf_t nbuf_tail;
  158. qdf_nbuf_t deliver_list_head;
  159. qdf_nbuf_t deliver_list_tail;
  160. uint32_t num_rx_bufs_reaped = 0;
  161. uint32_t intr_id;
  162. struct hif_opaque_softc *scn;
  163. int32_t tid = 0;
  164. bool is_prev_msdu_last = true;
  165. uint32_t num_entries_avail = 0;
  166. uint32_t rx_ol_pkt_cnt = 0;
  167. uint32_t num_entries = 0;
  168. struct hal_rx_msdu_metadata msdu_metadata;
  169. QDF_STATUS status;
  170. qdf_nbuf_t ebuf_head;
  171. qdf_nbuf_t ebuf_tail;
  172. uint8_t pkt_capture_offload = 0;
  173. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  174. int max_reap_limit, ring_near_full;
  175. struct dp_soc *replenish_soc;
  176. DP_HIST_INIT();
  177. qdf_assert_always(soc && hal_ring_hdl);
  178. hal_soc = soc->hal_soc;
  179. qdf_assert_always(hal_soc);
  180. scn = soc->hif_handle;
  181. hif_pm_runtime_mark_dp_rx_busy(scn);
  182. intr_id = int_ctx->dp_intr_id;
  183. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  184. more_data:
  185. /* reset local variables here to be re-used in the function */
  186. nbuf_head = NULL;
  187. nbuf_tail = NULL;
  188. deliver_list_head = NULL;
  189. deliver_list_tail = NULL;
  190. peer = NULL;
  191. vdev = NULL;
  192. num_rx_bufs_reaped = 0;
  193. ebuf_head = NULL;
  194. ebuf_tail = NULL;
  195. ring_near_full = 0;
  196. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  197. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  198. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  199. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  200. qdf_mem_zero(head, sizeof(head));
  201. qdf_mem_zero(tail, sizeof(tail));
  202. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  203. &max_reap_limit);
  204. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  205. /*
  206. * Need API to convert from hal_ring pointer to
  207. * Ring Type / Ring Id combo
  208. */
  209. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  210. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  211. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  212. goto done;
  213. }
  214. /*
  215. * start reaping the buffers from reo ring and queue
  216. * them in per vdev queue.
  217. * Process the received pkts in a different per vdev loop.
  218. */
  219. while (qdf_likely(quota &&
  220. (ring_desc = hal_srng_dst_peek(hal_soc,
  221. hal_ring_hdl)))) {
  222. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  223. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  224. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  225. soc, hal_ring_hdl, error);
  226. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  227. 1);
  228. /* Don't know how to deal with this -- assert */
  229. qdf_assert(0);
  230. }
  231. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  232. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  233. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  234. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  235. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  236. break;
  237. }
  238. rx_desc = (struct dp_rx_desc *)
  239. hal_rx_get_reo_desc_va(ring_desc);
  240. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  241. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  242. ring_desc, rx_desc);
  243. if (QDF_IS_STATUS_ERROR(status)) {
  244. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  245. qdf_assert_always(!rx_desc->unmapped);
  246. dp_ipa_reo_ctx_buf_mapping_lock(
  247. soc,
  248. reo_ring_num);
  249. dp_ipa_handle_rx_buf_smmu_mapping(
  250. soc,
  251. rx_desc->nbuf,
  252. RX_DATA_BUFFER_SIZE,
  253. false);
  254. qdf_nbuf_unmap_nbytes_single(
  255. soc->osdev,
  256. rx_desc->nbuf,
  257. QDF_DMA_FROM_DEVICE,
  258. RX_DATA_BUFFER_SIZE);
  259. rx_desc->unmapped = 1;
  260. dp_ipa_reo_ctx_buf_mapping_unlock(
  261. soc,
  262. reo_ring_num);
  263. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  264. rx_desc->pool_id);
  265. dp_rx_add_to_free_desc_list(
  266. &head[rx_desc->pool_id],
  267. &tail[rx_desc->pool_id],
  268. rx_desc);
  269. }
  270. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  271. continue;
  272. }
  273. /*
  274. * this is a unlikely scenario where the host is reaping
  275. * a descriptor which it already reaped just a while ago
  276. * but is yet to replenish it back to HW.
  277. * In this case host will dump the last 128 descriptors
  278. * including the software descriptor rx_desc and assert.
  279. */
  280. if (qdf_unlikely(!rx_desc->in_use)) {
  281. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  282. dp_info_rl("Reaping rx_desc not in use!");
  283. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  284. ring_desc, rx_desc);
  285. /* ignore duplicate RX desc and continue to process */
  286. /* Pop out the descriptor */
  287. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  288. continue;
  289. }
  290. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  291. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  292. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  293. dp_info_rl("Nbuf sanity check failure!");
  294. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  295. ring_desc, rx_desc);
  296. rx_desc->in_err_state = 1;
  297. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  298. continue;
  299. }
  300. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  301. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  302. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  303. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  304. ring_desc, rx_desc);
  305. }
  306. /* Get MPDU DESC info */
  307. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  308. /* Get MSDU DESC info */
  309. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  310. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  311. HAL_MSDU_F_MSDU_CONTINUATION)) {
  312. /* previous msdu has end bit set, so current one is
  313. * the new MPDU
  314. */
  315. if (is_prev_msdu_last) {
  316. /* Get number of entries available in HW ring */
  317. num_entries_avail =
  318. hal_srng_dst_num_valid(hal_soc,
  319. hal_ring_hdl, 1);
  320. /* For new MPDU check if we can read complete
  321. * MPDU by comparing the number of buffers
  322. * available and number of buffers needed to
  323. * reap this MPDU
  324. */
  325. if ((msdu_desc_info.msdu_len /
  326. (RX_DATA_BUFFER_SIZE -
  327. soc->rx_pkt_tlv_size) + 1) >
  328. num_entries_avail) {
  329. DP_STATS_INC(soc,
  330. rx.msdu_scatter_wait_break,
  331. 1);
  332. dp_rx_cookie_reset_invalid_bit(
  333. ring_desc);
  334. break;
  335. }
  336. is_prev_msdu_last = false;
  337. }
  338. }
  339. core_id = smp_processor_id();
  340. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  341. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  342. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  343. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  344. HAL_MPDU_F_RAW_AMPDU))
  345. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  346. if (!is_prev_msdu_last &&
  347. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  348. is_prev_msdu_last = true;
  349. /* Pop out the descriptor*/
  350. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  351. rx_bufs_reaped[rx_desc->pool_id]++;
  352. peer_mdata = mpdu_desc_info.peer_meta_data;
  353. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  354. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  355. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  356. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  357. /* to indicate whether this msdu is rx offload */
  358. pkt_capture_offload =
  359. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  360. /*
  361. * save msdu flags first, last and continuation msdu in
  362. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  363. * length to nbuf->cb. This ensures the info required for
  364. * per pkt processing is always in the same cache line.
  365. * This helps in improving throughput for smaller pkt
  366. * sizes.
  367. */
  368. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  369. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  370. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  371. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  372. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  373. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  374. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  375. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  376. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  377. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  378. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  379. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  380. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  381. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  382. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  383. HAL_MPDU_F_QOS_CONTROL_VALID))
  384. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  385. /* set sw exception */
  386. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  387. rx_desc->nbuf,
  388. hal_rx_sw_exception_get_be(ring_desc));
  389. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  390. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  391. /*
  392. * move unmap after scattered msdu waiting break logic
  393. * in case double skb unmap happened.
  394. */
  395. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  396. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  397. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  398. rx_desc_pool->buf_size,
  399. false);
  400. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  401. QDF_DMA_FROM_DEVICE,
  402. rx_desc_pool->buf_size);
  403. rx_desc->unmapped = 1;
  404. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  405. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  406. ebuf_tail, rx_desc);
  407. /*
  408. * if continuation bit is set then we have MSDU spread
  409. * across multiple buffers, let us not decrement quota
  410. * till we reap all buffers of that MSDU.
  411. */
  412. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  413. quota -= 1;
  414. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  415. &tail[rx_desc->pool_id], rx_desc);
  416. num_rx_bufs_reaped++;
  417. /*
  418. * only if complete msdu is received for scatter case,
  419. * then allow break.
  420. */
  421. if (is_prev_msdu_last &&
  422. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  423. max_reap_limit))
  424. break;
  425. }
  426. done:
  427. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  428. replenish_soc = dp_rx_replensih_soc_get(soc, reo_ring_num);
  429. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  430. /*
  431. * continue with next mac_id if no pkts were reaped
  432. * from that pool
  433. */
  434. if (!rx_bufs_reaped[mac_id])
  435. continue;
  436. dp_rxdma_srng = &replenish_soc->rx_refill_buf_ring[mac_id];
  437. rx_desc_pool = &replenish_soc->rx_desc_buf[mac_id];
  438. dp_rx_buffers_replenish(replenish_soc, mac_id, dp_rxdma_srng,
  439. rx_desc_pool, rx_bufs_reaped[mac_id],
  440. &head[mac_id], &tail[mac_id]);
  441. }
  442. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  443. /* Peer can be NULL is case of LFR */
  444. if (qdf_likely(peer))
  445. vdev = NULL;
  446. /*
  447. * BIG loop where each nbuf is dequeued from global queue,
  448. * processed and queued back on a per vdev basis. These nbufs
  449. * are sent to stack as and when we run out of nbufs
  450. * or a new nbuf dequeued from global queue has a different
  451. * vdev when compared to previous nbuf.
  452. */
  453. nbuf = nbuf_head;
  454. while (nbuf) {
  455. next = nbuf->next;
  456. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  457. nbuf = next;
  458. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  459. continue;
  460. }
  461. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  462. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  463. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  464. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  465. peer_id, vdev_id)) {
  466. dp_rx_deliver_to_stack(soc, vdev, peer,
  467. deliver_list_head,
  468. deliver_list_tail);
  469. deliver_list_head = NULL;
  470. deliver_list_tail = NULL;
  471. }
  472. /* Get TID from struct cb->tid_val, save to tid */
  473. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  474. tid = qdf_nbuf_get_tid_val(nbuf);
  475. if (qdf_unlikely(!peer)) {
  476. peer = dp_peer_get_ref_by_id(soc, peer_id,
  477. DP_MOD_ID_RX);
  478. } else if (peer && peer->peer_id != peer_id) {
  479. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  480. peer = dp_peer_get_ref_by_id(soc, peer_id,
  481. DP_MOD_ID_RX);
  482. }
  483. if (peer) {
  484. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  485. qdf_dp_trace_set_track(nbuf, QDF_RX);
  486. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  487. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  488. QDF_NBUF_RX_PKT_DATA_TRACK;
  489. }
  490. rx_bufs_used++;
  491. if (qdf_likely(peer)) {
  492. vdev = peer->vdev;
  493. } else {
  494. nbuf->next = NULL;
  495. dp_rx_deliver_to_pkt_capture_no_peer(
  496. soc, nbuf, pkt_capture_offload);
  497. if (!pkt_capture_offload)
  498. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  499. nbuf = next;
  500. continue;
  501. }
  502. if (qdf_unlikely(!vdev)) {
  503. qdf_nbuf_free(nbuf);
  504. nbuf = next;
  505. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  506. continue;
  507. }
  508. /* when hlos tid override is enabled, save tid in
  509. * skb->priority
  510. */
  511. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  512. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  513. qdf_nbuf_set_priority(nbuf, tid);
  514. rx_pdev = vdev->pdev;
  515. DP_RX_TID_SAVE(nbuf, tid);
  516. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  517. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  518. soc->wlan_cfg_ctx)))
  519. qdf_nbuf_set_timestamp(nbuf);
  520. enh_flag = rx_pdev->enhanced_stats_en;
  521. tid_stats =
  522. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  523. /*
  524. * Check if DMA completed -- msdu_done is the last bit
  525. * to be written
  526. */
  527. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  528. !hal_rx_attn_msdu_done_get(hal_soc,
  529. rx_tlv_hdr))) {
  530. dp_err("MSDU DONE failure");
  531. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  532. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  533. QDF_TRACE_LEVEL_INFO);
  534. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  535. qdf_nbuf_free(nbuf);
  536. qdf_assert(0);
  537. nbuf = next;
  538. continue;
  539. }
  540. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  541. /*
  542. * First IF condition:
  543. * 802.11 Fragmented pkts are reinjected to REO
  544. * HW block as SG pkts and for these pkts we only
  545. * need to pull the RX TLVS header length.
  546. * Second IF condition:
  547. * The below condition happens when an MSDU is spread
  548. * across multiple buffers. This can happen in two cases
  549. * 1. The nbuf size is smaller then the received msdu.
  550. * ex: we have set the nbuf size to 2048 during
  551. * nbuf_alloc. but we received an msdu which is
  552. * 2304 bytes in size then this msdu is spread
  553. * across 2 nbufs.
  554. *
  555. * 2. AMSDUs when RAW mode is enabled.
  556. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  557. * across 1st nbuf and 2nd nbuf and last MSDU is
  558. * spread across 2nd nbuf and 3rd nbuf.
  559. *
  560. * for these scenarios let us create a skb frag_list and
  561. * append these buffers till the last MSDU of the AMSDU
  562. * Third condition:
  563. * This is the most likely case, we receive 802.3 pkts
  564. * decapsulated by HW, here we need to set the pkt length.
  565. */
  566. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  567. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  568. bool is_mcbc, is_sa_vld, is_da_vld;
  569. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  570. rx_tlv_hdr);
  571. is_sa_vld =
  572. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  573. rx_tlv_hdr);
  574. is_da_vld =
  575. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  576. rx_tlv_hdr);
  577. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  578. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  579. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  580. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  581. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  582. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  583. nbuf = dp_rx_sg_create(soc, nbuf);
  584. next = nbuf->next;
  585. if (qdf_nbuf_is_raw_frame(nbuf)) {
  586. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  587. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  588. } else {
  589. qdf_nbuf_free(nbuf);
  590. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  591. dp_info_rl("scatter msdu len %d, dropped",
  592. msdu_len);
  593. nbuf = next;
  594. continue;
  595. }
  596. } else {
  597. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  598. pkt_len = msdu_len +
  599. msdu_metadata.l3_hdr_pad +
  600. soc->rx_pkt_tlv_size;
  601. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  602. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  603. }
  604. /*
  605. * process frame for mulitpass phrase processing
  606. */
  607. if (qdf_unlikely(vdev->multipass_en)) {
  608. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  609. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  610. qdf_nbuf_free(nbuf);
  611. nbuf = next;
  612. continue;
  613. }
  614. }
  615. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  616. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  617. DP_STATS_INC(peer, rx.policy_check_drop, 1);
  618. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  619. /* Drop & free packet */
  620. qdf_nbuf_free(nbuf);
  621. /* Statistics */
  622. nbuf = next;
  623. continue;
  624. }
  625. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  626. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  627. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  628. rx_tlv_hdr) ==
  629. false))) {
  630. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  631. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  632. qdf_nbuf_free(nbuf);
  633. nbuf = next;
  634. continue;
  635. }
  636. /*
  637. * Drop non-EAPOL frames from unauthorized peer.
  638. */
  639. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize) &&
  640. !qdf_nbuf_is_raw_frame(nbuf)) {
  641. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  642. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  643. if (!is_eapol) {
  644. DP_STATS_INC(peer,
  645. rx.peer_unauth_rx_pkt_drop, 1);
  646. qdf_nbuf_free(nbuf);
  647. nbuf = next;
  648. continue;
  649. }
  650. }
  651. if (soc->process_rx_status)
  652. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  653. /* Update the protocol tag in SKB based on CCE metadata */
  654. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  655. reo_ring_num, false, true);
  656. /* Update the flow tag in SKB based on FSE metadata */
  657. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  658. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  659. reo_ring_num, tid_stats);
  660. if (qdf_unlikely(vdev->mesh_vdev)) {
  661. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  662. == QDF_STATUS_SUCCESS) {
  663. dp_rx_info("%pK: mesh pkt filtered", soc);
  664. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  665. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  666. 1);
  667. qdf_nbuf_free(nbuf);
  668. nbuf = next;
  669. continue;
  670. }
  671. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  672. }
  673. if (qdf_likely(vdev->rx_decap_type ==
  674. htt_cmn_pkt_type_ethernet) &&
  675. qdf_likely(!vdev->mesh_vdev)) {
  676. dp_rx_wds_learn(soc, vdev,
  677. rx_tlv_hdr,
  678. peer,
  679. nbuf,
  680. msdu_metadata);
  681. /* Intrabss-fwd */
  682. if (dp_rx_check_ap_bridge(vdev))
  683. if (dp_rx_intrabss_fwd_be(soc, peer, rx_tlv_hdr,
  684. nbuf,
  685. msdu_metadata)) {
  686. nbuf = next;
  687. tid_stats->intrabss_cnt++;
  688. continue; /* Get next desc */
  689. }
  690. }
  691. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  692. dp_rx_update_stats(soc, nbuf);
  693. DP_RX_LIST_APPEND(deliver_list_head,
  694. deliver_list_tail,
  695. nbuf);
  696. DP_PEER_TO_STACK_INCC_PKT(peer, 1, QDF_NBUF_CB_RX_PKT_LEN(nbuf),
  697. enh_flag);
  698. if (qdf_unlikely(peer->in_twt))
  699. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  700. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  701. tid_stats->delivered_to_stack++;
  702. nbuf = next;
  703. }
  704. if (qdf_likely(deliver_list_head)) {
  705. if (qdf_likely(peer)) {
  706. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  707. pkt_capture_offload,
  708. deliver_list_head);
  709. if (!pkt_capture_offload)
  710. dp_rx_deliver_to_stack(soc, vdev, peer,
  711. deliver_list_head,
  712. deliver_list_tail);
  713. } else {
  714. nbuf = deliver_list_head;
  715. while (nbuf) {
  716. next = nbuf->next;
  717. nbuf->next = NULL;
  718. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  719. nbuf = next;
  720. }
  721. }
  722. }
  723. if (qdf_likely(peer))
  724. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  725. /*
  726. * If we are processing in near-full condition, there are 3 scenario
  727. * 1) Ring entries has reached critical state
  728. * 2) Ring entries are still near high threshold
  729. * 3) Ring entries are below the safe level
  730. *
  731. * One more loop will move the state to normal processing and yield
  732. */
  733. if (ring_near_full && quota)
  734. goto more_data;
  735. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  736. if (quota) {
  737. num_pending =
  738. dp_rx_srng_get_num_pending(hal_soc,
  739. hal_ring_hdl,
  740. num_entries,
  741. &near_full);
  742. if (num_pending) {
  743. DP_STATS_INC(soc, rx.hp_oos2, 1);
  744. if (!hif_exec_should_yield(scn, intr_id))
  745. goto more_data;
  746. if (qdf_unlikely(near_full)) {
  747. DP_STATS_INC(soc, rx.near_full, 1);
  748. goto more_data;
  749. }
  750. }
  751. }
  752. if (vdev && vdev->osif_fisa_flush)
  753. vdev->osif_fisa_flush(soc, reo_ring_num);
  754. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  755. vdev->osif_gro_flush(vdev->osif_vdev,
  756. reo_ring_num);
  757. }
  758. }
  759. /* Update histogram statistics by looping through pdev's */
  760. DP_RX_HIST_STATS_PER_PDEV();
  761. return rx_bufs_used; /* Assume no scale factor for now */
  762. }
  763. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  764. /**
  765. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  766. * @soc: Handle to DP Soc structure
  767. * @rx_desc_pool: Rx descriptor pool handler
  768. * @pool_id: Rx descriptor pool ID
  769. *
  770. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  771. */
  772. static QDF_STATUS
  773. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  774. struct rx_desc_pool *rx_desc_pool,
  775. uint32_t pool_id)
  776. {
  777. struct dp_hw_cookie_conversion_t *cc_ctx;
  778. struct dp_soc_be *be_soc;
  779. union dp_rx_desc_list_elem_t *rx_desc_elem;
  780. struct dp_spt_page_desc *page_desc;
  781. uint32_t ppt_idx = 0;
  782. uint32_t avail_entry_index = 0;
  783. if (!rx_desc_pool->pool_size) {
  784. dp_err("desc_num 0 !!");
  785. return QDF_STATUS_E_FAILURE;
  786. }
  787. be_soc = dp_get_be_soc_from_dp_soc(soc);
  788. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  789. page_desc = &cc_ctx->page_desc_base[0];
  790. rx_desc_elem = rx_desc_pool->freelist;
  791. while (rx_desc_elem) {
  792. if (avail_entry_index == 0) {
  793. if (ppt_idx >= cc_ctx->total_page_num) {
  794. dp_alert("insufficient secondary page tables");
  795. qdf_assert_always(0);
  796. }
  797. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  798. }
  799. /* put each RX Desc VA to SPT pages and
  800. * get corresponding ID
  801. */
  802. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  803. avail_entry_index,
  804. &rx_desc_elem->rx_desc);
  805. rx_desc_elem->rx_desc.cookie =
  806. dp_cc_desc_id_generate(page_desc->ppt_index,
  807. avail_entry_index);
  808. rx_desc_elem->rx_desc.pool_id = pool_id;
  809. rx_desc_elem->rx_desc.in_use = 0;
  810. rx_desc_elem = rx_desc_elem->next;
  811. avail_entry_index = (avail_entry_index + 1) &
  812. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  813. }
  814. return QDF_STATUS_SUCCESS;
  815. }
  816. #else
  817. static QDF_STATUS
  818. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  819. struct rx_desc_pool *rx_desc_pool,
  820. uint32_t pool_id)
  821. {
  822. struct dp_hw_cookie_conversion_t *cc_ctx;
  823. struct dp_soc_be *be_soc;
  824. struct dp_spt_page_desc *page_desc;
  825. uint32_t ppt_idx = 0;
  826. uint32_t avail_entry_index = 0;
  827. int i = 0;
  828. if (!rx_desc_pool->pool_size) {
  829. dp_err("desc_num 0 !!");
  830. return QDF_STATUS_E_FAILURE;
  831. }
  832. be_soc = dp_get_be_soc_from_dp_soc(soc);
  833. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  834. page_desc = &cc_ctx->page_desc_base[0];
  835. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  836. if (i == rx_desc_pool->pool_size - 1)
  837. rx_desc_pool->array[i].next = NULL;
  838. else
  839. rx_desc_pool->array[i].next =
  840. &rx_desc_pool->array[i + 1];
  841. if (avail_entry_index == 0) {
  842. if (ppt_idx >= cc_ctx->total_page_num) {
  843. dp_alert("insufficient secondary page tables");
  844. qdf_assert_always(0);
  845. }
  846. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  847. }
  848. /* put each RX Desc VA to SPT pages and
  849. * get corresponding ID
  850. */
  851. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  852. avail_entry_index,
  853. &rx_desc_pool->array[i].rx_desc);
  854. rx_desc_pool->array[i].rx_desc.cookie =
  855. dp_cc_desc_id_generate(page_desc->ppt_index,
  856. avail_entry_index);
  857. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  858. rx_desc_pool->array[i].rx_desc.in_use = 0;
  859. avail_entry_index = (avail_entry_index + 1) &
  860. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  861. }
  862. return QDF_STATUS_SUCCESS;
  863. }
  864. #endif
  865. static void
  866. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  867. struct rx_desc_pool *rx_desc_pool,
  868. uint32_t pool_id)
  869. {
  870. struct dp_spt_page_desc *page_desc;
  871. struct dp_soc_be *be_soc;
  872. int i = 0;
  873. struct dp_hw_cookie_conversion_t *cc_ctx;
  874. be_soc = dp_get_be_soc_from_dp_soc(soc);
  875. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  876. for (i = 0; i < cc_ctx->total_page_num; i++) {
  877. page_desc = &cc_ctx->page_desc_base[i];
  878. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  879. }
  880. }
  881. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  882. struct rx_desc_pool *rx_desc_pool,
  883. uint32_t pool_id)
  884. {
  885. QDF_STATUS status = QDF_STATUS_SUCCESS;
  886. /* Only regular RX buffer desc pool use HW cookie conversion */
  887. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  888. dp_info("rx_desc_buf pool init");
  889. status = dp_rx_desc_pool_init_be_cc(soc,
  890. rx_desc_pool,
  891. pool_id);
  892. } else {
  893. dp_info("non_rx_desc_buf_pool init");
  894. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool,
  895. pool_id);
  896. }
  897. return status;
  898. }
  899. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  900. struct rx_desc_pool *rx_desc_pool,
  901. uint32_t pool_id)
  902. {
  903. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  904. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  905. }
  906. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  907. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  908. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  909. void *ring_desc,
  910. struct dp_rx_desc **r_rx_desc)
  911. {
  912. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  913. /* HW cookie conversion done */
  914. *r_rx_desc = (struct dp_rx_desc *)
  915. hal_rx_wbm_get_desc_va(ring_desc);
  916. } else {
  917. /* SW do cookie conversion */
  918. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  919. *r_rx_desc = (struct dp_rx_desc *)
  920. dp_cc_desc_find(soc, cookie);
  921. }
  922. return QDF_STATUS_SUCCESS;
  923. }
  924. #else
  925. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  926. void *ring_desc,
  927. struct dp_rx_desc **r_rx_desc)
  928. {
  929. *r_rx_desc = (struct dp_rx_desc *)
  930. hal_rx_wbm_get_desc_va(ring_desc);
  931. return QDF_STATUS_SUCCESS;
  932. }
  933. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  934. #else
  935. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  936. void *ring_desc,
  937. struct dp_rx_desc **r_rx_desc)
  938. {
  939. /* SW do cookie conversion */
  940. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  941. *r_rx_desc = (struct dp_rx_desc *)
  942. dp_cc_desc_find(soc, cookie);
  943. return QDF_STATUS_SUCCESS;
  944. }
  945. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  946. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  947. uint32_t cookie)
  948. {
  949. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  950. }
  951. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  952. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  953. hal_ring_handle_t hal_ring_hdl,
  954. uint8_t reo_ring_num,
  955. uint32_t quota)
  956. {
  957. struct dp_soc *soc = int_ctx->soc;
  958. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  959. uint32_t work_done = 0;
  960. if (dp_srng_get_near_full_level(soc, rx_ring) <
  961. DP_SRNG_THRESH_NEAR_FULL)
  962. return 0;
  963. qdf_atomic_set(&rx_ring->near_full, 1);
  964. work_done++;
  965. return work_done;
  966. }
  967. #endif
  968. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  969. #ifdef WLAN_FEATURE_11BE_MLO
  970. /**
  971. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  972. * @ta_peer: transmitter peer handle
  973. * @da_peer: destination peer handle
  974. *
  975. * Return: true - MLO forwarding case, false: not
  976. */
  977. static inline bool
  978. dp_rx_intrabss_fwd_mlo_allow(struct dp_peer *ta_peer,
  979. struct dp_peer *da_peer)
  980. {
  981. /* one of TA/DA peer should belong to MLO connection peer,
  982. * only MLD peer type is as expected
  983. */
  984. if (!IS_MLO_DP_MLD_PEER(ta_peer) &&
  985. !IS_MLO_DP_MLD_PEER(da_peer))
  986. return false;
  987. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  988. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  989. &da_peer->vdev->mld_mac_addr))
  990. return false;
  991. return true;
  992. }
  993. #else
  994. static inline bool
  995. dp_rx_intrabss_fwd_mlo_allow(struct dp_peer *ta_peer,
  996. struct dp_peer *da_peer)
  997. {
  998. return false;
  999. }
  1000. #endif
  1001. #ifdef INTRA_BSS_FWD_OFFLOAD
  1002. /**
  1003. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1004. for unicast frame
  1005. * @soc: SOC hanlde
  1006. * @nbuf: RX packet buffer
  1007. * @ta_peer: transmitter DP peer handle
  1008. * @msdu_metadata: MSDU meta data info
  1009. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1010. *
  1011. * Return: true - intrabss allowed
  1012. false - not allow
  1013. */
  1014. static bool
  1015. dp_rx_intrabss_ucast_check_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1016. struct dp_peer *ta_peer,
  1017. struct hal_rx_msdu_metadata *msdu_metadata,
  1018. uint8_t *p_tx_vdev_id)
  1019. {
  1020. uint16_t da_peer_id;
  1021. struct dp_peer *da_peer;
  1022. if (!qdf_nbuf_is_intra_bss(nbuf))
  1023. return false;
  1024. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1025. soc,
  1026. msdu_metadata->da_idx);
  1027. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id, DP_MOD_ID_RX);
  1028. if (!da_peer)
  1029. return false;
  1030. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  1031. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  1032. return true;
  1033. }
  1034. #else
  1035. static bool
  1036. dp_rx_intrabss_ucast_check_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1037. struct dp_peer *ta_peer,
  1038. struct hal_rx_msdu_metadata *msdu_metadata,
  1039. uint8_t *p_tx_vdev_id)
  1040. {
  1041. uint16_t da_peer_id;
  1042. struct dp_peer *da_peer;
  1043. bool ret = false;
  1044. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  1045. return false;
  1046. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1047. soc,
  1048. msdu_metadata->da_idx);
  1049. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id,
  1050. DP_MOD_ID_RX);
  1051. if (!da_peer)
  1052. return false;
  1053. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  1054. /* If the source or destination peer in the isolation
  1055. * list then dont forward instead push to bridge stack.
  1056. */
  1057. if (dp_get_peer_isolation(ta_peer) ||
  1058. dp_get_peer_isolation(da_peer))
  1059. goto rel_da_peer;
  1060. if (da_peer->bss_peer || da_peer == ta_peer)
  1061. goto rel_da_peer;
  1062. /* Same vdev, support Inra-BSS */
  1063. if (da_peer->vdev == ta_peer->vdev) {
  1064. ret = true;
  1065. goto rel_da_peer;
  1066. }
  1067. /* MLO specific Intra-BSS check */
  1068. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1069. ret = true;
  1070. goto rel_da_peer;
  1071. }
  1072. rel_da_peer:
  1073. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  1074. return ret;
  1075. }
  1076. #endif
  1077. /*
  1078. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1079. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1080. * @soc: core txrx main context
  1081. * @ta_peer: source peer entry
  1082. * @rx_tlv_hdr: start address of rx tlvs
  1083. * @nbuf: nbuf that has to be intrabss forwarded
  1084. * @msdu_metadata: msdu metadata
  1085. *
  1086. * Return: true if it is forwarded else false
  1087. */
  1088. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_peer *ta_peer,
  1089. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1090. struct hal_rx_msdu_metadata msdu_metadata)
  1091. {
  1092. uint8_t tx_vdev_id;
  1093. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1094. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1095. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1096. tid_stats.tid_rx_stats[ring_id][tid];
  1097. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1098. * source, then clone the pkt and send the cloned pkt for
  1099. * intra BSS forwarding and original pkt up the network stack
  1100. * Note: how do we handle multicast pkts. do we forward
  1101. * all multicast pkts as is or let a higher layer module
  1102. * like igmpsnoop decide whether to forward or not with
  1103. * Mcast enhancement.
  1104. */
  1105. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer)
  1106. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1107. nbuf, tid_stats);
  1108. if (dp_rx_intrabss_ucast_check_be(soc, nbuf, ta_peer,
  1109. &msdu_metadata, &tx_vdev_id))
  1110. return dp_rx_intrabss_ucast_fwd(soc, ta_peer, tx_vdev_id,
  1111. rx_tlv_hdr, nbuf, tid_stats);
  1112. return false;
  1113. }
  1114. #endif