main.c 99 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "main.h"
  28. #include "bus.h"
  29. #include "debug.h"
  30. #include "genl.h"
  31. #define CNSS_DUMP_FORMAT_VER 0x11
  32. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  33. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  34. #define CNSS_DUMP_NAME "CNSS_WLAN"
  35. #define CNSS_DUMP_DESC_SIZE 0x1000
  36. #define CNSS_DUMP_SEG_VER 0x1
  37. #define FILE_SYSTEM_READY 1
  38. #define FW_READY_TIMEOUT 20000
  39. #define FW_ASSERT_TIMEOUT 5000
  40. #define CNSS_EVENT_PENDING 2989
  41. #define POWER_RESET_MIN_DELAY_MS 100
  42. #define CNSS_QUIRKS_DEFAULT 0
  43. #ifdef CONFIG_CNSS_EMULATION
  44. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  45. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  46. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  47. #else
  48. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  49. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  50. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  51. #endif
  52. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  53. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  54. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  55. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  56. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  57. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  58. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  59. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  60. enum cnss_cal_db_op {
  61. CNSS_CAL_DB_UPLOAD,
  62. CNSS_CAL_DB_DOWNLOAD,
  63. CNSS_CAL_DB_INVALID_OP,
  64. };
  65. static struct cnss_plat_data *plat_env;
  66. static DECLARE_RWSEM(cnss_pm_sem);
  67. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  68. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  69. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  70. };
  71. static struct cnss_fw_files FW_FILES_DEFAULT = {
  72. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  73. "utfbd.bin", "epping.bin", "evicted.bin"
  74. };
  75. struct cnss_driver_event {
  76. struct list_head list;
  77. enum cnss_driver_event_type type;
  78. bool sync;
  79. struct completion complete;
  80. int ret;
  81. void *data;
  82. };
  83. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  84. struct cnss_plat_data *plat_priv)
  85. {
  86. plat_env = plat_priv;
  87. }
  88. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  89. {
  90. return plat_env;
  91. }
  92. /**
  93. * cnss_get_mem_seg_count - Get segment count of memory
  94. * @type: memory type
  95. * @seg: segment count
  96. *
  97. * Return: 0 on success, negative value on failure
  98. */
  99. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  100. {
  101. struct cnss_plat_data *plat_priv;
  102. plat_priv = cnss_get_plat_priv(NULL);
  103. if (!plat_priv)
  104. return -ENODEV;
  105. switch (type) {
  106. case CNSS_REMOTE_MEM_TYPE_FW:
  107. *seg = plat_priv->fw_mem_seg_len;
  108. break;
  109. case CNSS_REMOTE_MEM_TYPE_QDSS:
  110. *seg = plat_priv->qdss_mem_seg_len;
  111. break;
  112. default:
  113. return -EINVAL;
  114. }
  115. return 0;
  116. }
  117. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  118. /**
  119. * cnss_get_mem_segment_info - Get memory info of different type
  120. * @type: memory type
  121. * @segment: array to save the segment info
  122. * @seg: segment count
  123. *
  124. * Return: 0 on success, negative value on failure
  125. */
  126. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  127. struct cnss_mem_segment segment[],
  128. u32 segment_count)
  129. {
  130. struct cnss_plat_data *plat_priv;
  131. u32 i;
  132. plat_priv = cnss_get_plat_priv(NULL);
  133. if (!plat_priv)
  134. return -ENODEV;
  135. switch (type) {
  136. case CNSS_REMOTE_MEM_TYPE_FW:
  137. if (segment_count > plat_priv->fw_mem_seg_len)
  138. segment_count = plat_priv->fw_mem_seg_len;
  139. for (i = 0; i < segment_count; i++) {
  140. segment[i].size = plat_priv->fw_mem[i].size;
  141. segment[i].va = plat_priv->fw_mem[i].va;
  142. segment[i].pa = plat_priv->fw_mem[i].pa;
  143. }
  144. break;
  145. case CNSS_REMOTE_MEM_TYPE_QDSS:
  146. if (segment_count > plat_priv->qdss_mem_seg_len)
  147. segment_count = plat_priv->qdss_mem_seg_len;
  148. for (i = 0; i < segment_count; i++) {
  149. segment[i].size = plat_priv->qdss_mem[i].size;
  150. segment[i].va = plat_priv->qdss_mem[i].va;
  151. segment[i].pa = plat_priv->qdss_mem[i].pa;
  152. }
  153. break;
  154. default:
  155. return -EINVAL;
  156. }
  157. return 0;
  158. }
  159. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  160. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  161. enum cnss_feature_v01 feature)
  162. {
  163. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  164. return -EINVAL;
  165. plat_priv->feature_list |= 1 << feature;
  166. return 0;
  167. }
  168. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  169. u64 *feature_list)
  170. {
  171. if (unlikely(!plat_priv))
  172. return -EINVAL;
  173. *feature_list = plat_priv->feature_list;
  174. return 0;
  175. }
  176. static int cnss_pm_notify(struct notifier_block *b,
  177. unsigned long event, void *p)
  178. {
  179. switch (event) {
  180. case PM_SUSPEND_PREPARE:
  181. down_write(&cnss_pm_sem);
  182. break;
  183. case PM_POST_SUSPEND:
  184. up_write(&cnss_pm_sem);
  185. break;
  186. }
  187. return NOTIFY_DONE;
  188. }
  189. static struct notifier_block cnss_pm_notifier = {
  190. .notifier_call = cnss_pm_notify,
  191. };
  192. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  193. {
  194. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  195. return;
  196. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  197. plat_priv->driver_state,
  198. atomic_read(&plat_priv->pm_count));
  199. pm_stay_awake(&plat_priv->plat_dev->dev);
  200. }
  201. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  202. {
  203. int r = atomic_dec_return(&plat_priv->pm_count);
  204. WARN_ON(r < 0);
  205. if (r != 0)
  206. return;
  207. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  208. plat_priv->driver_state,
  209. atomic_read(&plat_priv->pm_count));
  210. pm_relax(&plat_priv->plat_dev->dev);
  211. }
  212. void cnss_lock_pm_sem(struct device *dev)
  213. {
  214. down_read(&cnss_pm_sem);
  215. }
  216. EXPORT_SYMBOL(cnss_lock_pm_sem);
  217. void cnss_release_pm_sem(struct device *dev)
  218. {
  219. up_read(&cnss_pm_sem);
  220. }
  221. EXPORT_SYMBOL(cnss_release_pm_sem);
  222. int cnss_get_fw_files_for_target(struct device *dev,
  223. struct cnss_fw_files *pfw_files,
  224. u32 target_type, u32 target_version)
  225. {
  226. if (!pfw_files)
  227. return -ENODEV;
  228. switch (target_version) {
  229. case QCA6174_REV3_VERSION:
  230. case QCA6174_REV3_2_VERSION:
  231. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  232. break;
  233. default:
  234. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  235. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  236. target_type, target_version);
  237. break;
  238. }
  239. return 0;
  240. }
  241. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  242. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  243. {
  244. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  245. if (!plat_priv)
  246. return -ENODEV;
  247. if (!cap)
  248. return -EINVAL;
  249. *cap = plat_priv->cap;
  250. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  251. return 0;
  252. }
  253. EXPORT_SYMBOL(cnss_get_platform_cap);
  254. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  255. {
  256. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  257. if (!plat_priv)
  258. return;
  259. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  260. }
  261. EXPORT_SYMBOL(cnss_request_pm_qos);
  262. void cnss_remove_pm_qos(struct device *dev)
  263. {
  264. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  265. if (!plat_priv)
  266. return;
  267. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  268. }
  269. EXPORT_SYMBOL(cnss_remove_pm_qos);
  270. int cnss_wlan_enable(struct device *dev,
  271. struct cnss_wlan_enable_cfg *config,
  272. enum cnss_driver_mode mode,
  273. const char *host_version)
  274. {
  275. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  276. int ret = 0;
  277. if (!plat_priv)
  278. return -ENODEV;
  279. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  280. return 0;
  281. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  282. return 0;
  283. if (!config || !host_version) {
  284. cnss_pr_err("Invalid config or host_version pointer\n");
  285. return -EINVAL;
  286. }
  287. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  288. mode, config, host_version);
  289. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  290. goto skip_cfg;
  291. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  292. if (ret)
  293. goto out;
  294. skip_cfg:
  295. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  296. out:
  297. return ret;
  298. }
  299. EXPORT_SYMBOL(cnss_wlan_enable);
  300. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  301. {
  302. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  303. int ret = 0;
  304. if (!plat_priv)
  305. return -ENODEV;
  306. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  307. return 0;
  308. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  309. return 0;
  310. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  311. cnss_bus_free_qdss_mem(plat_priv);
  312. return ret;
  313. }
  314. EXPORT_SYMBOL(cnss_wlan_disable);
  315. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  316. u32 data_len, u8 *output)
  317. {
  318. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  319. int ret = 0;
  320. if (!plat_priv) {
  321. cnss_pr_err("plat_priv is NULL!\n");
  322. return -EINVAL;
  323. }
  324. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  325. return 0;
  326. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  327. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  328. plat_priv->driver_state);
  329. ret = -EINVAL;
  330. goto out;
  331. }
  332. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  333. data_len, output);
  334. out:
  335. return ret;
  336. }
  337. EXPORT_SYMBOL(cnss_athdiag_read);
  338. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  339. u32 data_len, u8 *input)
  340. {
  341. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  342. int ret = 0;
  343. if (!plat_priv) {
  344. cnss_pr_err("plat_priv is NULL!\n");
  345. return -EINVAL;
  346. }
  347. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  348. return 0;
  349. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  350. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  351. plat_priv->driver_state);
  352. ret = -EINVAL;
  353. goto out;
  354. }
  355. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  356. data_len, input);
  357. out:
  358. return ret;
  359. }
  360. EXPORT_SYMBOL(cnss_athdiag_write);
  361. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  362. {
  363. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  364. if (!plat_priv)
  365. return -ENODEV;
  366. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  367. return 0;
  368. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  369. }
  370. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  371. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  372. {
  373. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  374. if (!plat_priv)
  375. return -EINVAL;
  376. if (plat_priv->device_id != QCA6490_DEVICE_ID ||
  377. !plat_priv->fw_pcie_gen_switch)
  378. return -EOPNOTSUPP;
  379. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  380. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  381. return -EINVAL;
  382. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  383. plat_priv->pcie_gen_speed = pcie_gen_speed;
  384. return 0;
  385. }
  386. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  387. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  388. {
  389. int ret = 0;
  390. if (!plat_priv)
  391. return -ENODEV;
  392. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  393. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  394. if (ret)
  395. goto out;
  396. if (plat_priv->hds_enabled)
  397. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  398. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  399. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  400. plat_priv->ctrl_params.bdf_type);
  401. if (ret)
  402. goto out;
  403. ret = cnss_bus_load_m3(plat_priv);
  404. if (ret)
  405. goto out;
  406. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  407. if (ret)
  408. goto out;
  409. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  410. return 0;
  411. out:
  412. return ret;
  413. }
  414. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  415. {
  416. int ret = 0;
  417. if (!plat_priv->antenna) {
  418. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  419. if (ret)
  420. goto out;
  421. }
  422. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  423. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  424. if (ret)
  425. goto out;
  426. }
  427. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  428. if (ret)
  429. goto out;
  430. return 0;
  431. out:
  432. return ret;
  433. }
  434. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  435. {
  436. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  437. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  438. }
  439. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  440. {
  441. u32 i;
  442. int ret = 0;
  443. struct cnss_plat_ipc_daemon_config *cfg;
  444. ret = cnss_qmi_get_dms_mac(plat_priv);
  445. if (ret == 0 && plat_priv->dms.mac_valid)
  446. goto qmi_send;
  447. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  448. * Thus assert on failure to get MAC from DMS even after retries
  449. */
  450. if (plat_priv->use_nv_mac) {
  451. /* Check if Daemon says platform support DMS MAC provisioning */
  452. cfg = cnss_plat_ipc_qmi_daemon_config();
  453. if (cfg) {
  454. if (!cfg->dms_mac_addr_supported) {
  455. cnss_pr_err("DMS MAC address not supported\n");
  456. CNSS_ASSERT(0);
  457. return -EINVAL;
  458. }
  459. }
  460. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  461. if (plat_priv->dms.mac_valid)
  462. break;
  463. ret = cnss_qmi_get_dms_mac(plat_priv);
  464. if (ret == 0)
  465. break;
  466. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  467. }
  468. if (!plat_priv->dms.mac_valid) {
  469. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  470. CNSS_ASSERT(0);
  471. return -EINVAL;
  472. }
  473. }
  474. qmi_send:
  475. if (plat_priv->dms.mac_valid)
  476. ret =
  477. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  478. ARRAY_SIZE(plat_priv->dms.mac));
  479. return ret;
  480. }
  481. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  482. enum cnss_cal_db_op op, u32 *size)
  483. {
  484. int ret = 0;
  485. u32 timeout = cnss_get_timeout(plat_priv,
  486. CNSS_TIMEOUT_DAEMON_CONNECTION);
  487. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  488. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  489. if (op >= CNSS_CAL_DB_INVALID_OP)
  490. return -EINVAL;
  491. if (!plat_priv->cbc_file_download) {
  492. cnss_pr_info("CAL DB file not required as per BDF\n");
  493. return 0;
  494. }
  495. if (*size == 0) {
  496. cnss_pr_err("Invalid cal file size\n");
  497. return -EINVAL;
  498. }
  499. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  500. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  501. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  502. msecs_to_jiffies(timeout));
  503. if (!ret) {
  504. cnss_pr_err("Daemon not yet connected\n");
  505. CNSS_ASSERT(0);
  506. return ret;
  507. }
  508. }
  509. if (!plat_priv->cal_mem->va) {
  510. cnss_pr_err("CAL DB Memory not setup for FW\n");
  511. return -EINVAL;
  512. }
  513. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  514. if (op == CNSS_CAL_DB_DOWNLOAD) {
  515. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  516. ret = cnss_plat_ipc_qmi_file_download(client_id,
  517. CNSS_CAL_DB_FILE_NAME,
  518. plat_priv->cal_mem->va,
  519. size);
  520. } else {
  521. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  522. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  523. CNSS_CAL_DB_FILE_NAME,
  524. plat_priv->cal_mem->va,
  525. *size);
  526. }
  527. if (ret)
  528. cnss_pr_err("Cal DB file %s %s failure\n",
  529. CNSS_CAL_DB_FILE_NAME,
  530. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  531. else
  532. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  533. CNSS_CAL_DB_FILE_NAME,
  534. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  535. *size);
  536. return ret;
  537. }
  538. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  539. {
  540. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  541. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  542. return -EINVAL;
  543. }
  544. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  545. &plat_priv->cal_file_size);
  546. }
  547. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  548. u32 *cal_file_size)
  549. {
  550. /* To download pass the total size of cal DB mem allocated.
  551. * After cal file is download to mem, its size is updated in
  552. * return pointer
  553. */
  554. *cal_file_size = plat_priv->cal_mem->size;
  555. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  556. cal_file_size);
  557. }
  558. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  559. {
  560. int ret = 0;
  561. u32 cal_file_size = 0;
  562. if (!plat_priv)
  563. return -ENODEV;
  564. cnss_pr_dbg("Processing FW Init Done..\n");
  565. del_timer(&plat_priv->fw_boot_timer);
  566. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  567. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  568. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  569. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  570. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  571. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  572. }
  573. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  574. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  575. CNSS_WALTEST);
  576. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  577. cnss_request_antenna_sharing(plat_priv);
  578. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  579. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  580. plat_priv->cal_time = jiffies;
  581. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  582. CNSS_CALIBRATION);
  583. } else {
  584. ret = cnss_setup_dms_mac(plat_priv);
  585. ret = cnss_bus_call_driver_probe(plat_priv);
  586. }
  587. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  588. goto out;
  589. else if (ret)
  590. goto shutdown;
  591. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  592. return 0;
  593. shutdown:
  594. cnss_bus_dev_shutdown(plat_priv);
  595. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  596. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  597. out:
  598. return ret;
  599. }
  600. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  601. {
  602. switch (type) {
  603. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  604. return "SERVER_ARRIVE";
  605. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  606. return "SERVER_EXIT";
  607. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  608. return "REQUEST_MEM";
  609. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  610. return "FW_MEM_READY";
  611. case CNSS_DRIVER_EVENT_FW_READY:
  612. return "FW_READY";
  613. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  614. return "COLD_BOOT_CAL_START";
  615. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  616. return "COLD_BOOT_CAL_DONE";
  617. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  618. return "REGISTER_DRIVER";
  619. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  620. return "UNREGISTER_DRIVER";
  621. case CNSS_DRIVER_EVENT_RECOVERY:
  622. return "RECOVERY";
  623. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  624. return "FORCE_FW_ASSERT";
  625. case CNSS_DRIVER_EVENT_POWER_UP:
  626. return "POWER_UP";
  627. case CNSS_DRIVER_EVENT_POWER_DOWN:
  628. return "POWER_DOWN";
  629. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  630. return "IDLE_RESTART";
  631. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  632. return "IDLE_SHUTDOWN";
  633. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  634. return "IMS_WFC_CALL_IND";
  635. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  636. return "WLFW_TWC_CFG_IND";
  637. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  638. return "QDSS_TRACE_REQ_MEM";
  639. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  640. return "FW_MEM_FILE_SAVE";
  641. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  642. return "QDSS_TRACE_FREE";
  643. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  644. return "QDSS_TRACE_REQ_DATA";
  645. case CNSS_DRIVER_EVENT_MAX:
  646. return "EVENT_MAX";
  647. }
  648. return "UNKNOWN";
  649. };
  650. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  651. enum cnss_driver_event_type type,
  652. u32 flags, void *data)
  653. {
  654. struct cnss_driver_event *event;
  655. unsigned long irq_flags;
  656. int gfp = GFP_KERNEL;
  657. int ret = 0;
  658. if (!plat_priv)
  659. return -ENODEV;
  660. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  661. cnss_driver_event_to_str(type), type,
  662. flags ? "-sync" : "", plat_priv->driver_state, flags);
  663. if (type >= CNSS_DRIVER_EVENT_MAX) {
  664. cnss_pr_err("Invalid Event type: %d, can't post", type);
  665. return -EINVAL;
  666. }
  667. if (in_interrupt() || irqs_disabled())
  668. gfp = GFP_ATOMIC;
  669. event = kzalloc(sizeof(*event), gfp);
  670. if (!event)
  671. return -ENOMEM;
  672. cnss_pm_stay_awake(plat_priv);
  673. event->type = type;
  674. event->data = data;
  675. init_completion(&event->complete);
  676. event->ret = CNSS_EVENT_PENDING;
  677. event->sync = !!(flags & CNSS_EVENT_SYNC);
  678. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  679. list_add_tail(&event->list, &plat_priv->event_list);
  680. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  681. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  682. if (!(flags & CNSS_EVENT_SYNC))
  683. goto out;
  684. if (flags & CNSS_EVENT_UNKILLABLE)
  685. wait_for_completion(&event->complete);
  686. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  687. ret = wait_for_completion_killable(&event->complete);
  688. else
  689. ret = wait_for_completion_interruptible(&event->complete);
  690. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  691. cnss_driver_event_to_str(type), type,
  692. plat_priv->driver_state, ret, event->ret);
  693. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  694. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  695. event->sync = false;
  696. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  697. ret = -EINTR;
  698. goto out;
  699. }
  700. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  701. ret = event->ret;
  702. kfree(event);
  703. out:
  704. cnss_pm_relax(plat_priv);
  705. return ret;
  706. }
  707. /**
  708. * cnss_get_timeout - Get timeout for corresponding type.
  709. * @plat_priv: Pointer to platform driver context.
  710. * @cnss_timeout_type: Timeout type.
  711. *
  712. * Return: Timeout in milliseconds.
  713. */
  714. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  715. enum cnss_timeout_type timeout_type)
  716. {
  717. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  718. switch (timeout_type) {
  719. case CNSS_TIMEOUT_QMI:
  720. return qmi_timeout;
  721. case CNSS_TIMEOUT_POWER_UP:
  722. return (qmi_timeout << 2);
  723. case CNSS_TIMEOUT_IDLE_RESTART:
  724. /* In idle restart power up sequence, we have fw_boot_timer to
  725. * handle FW initialization failure.
  726. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  727. * account for FW dump collection and FW re-initialization on
  728. * retry.
  729. */
  730. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  731. case CNSS_TIMEOUT_CALIBRATION:
  732. /* Similar to mission mode, in CBC if FW init fails
  733. * fw recovery is tried. Thus return 2x the CBC timeout.
  734. */
  735. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  736. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  737. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  738. case CNSS_TIMEOUT_RDDM:
  739. return CNSS_RDDM_TIMEOUT_MS;
  740. case CNSS_TIMEOUT_RECOVERY:
  741. return RECOVERY_TIMEOUT;
  742. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  743. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  744. default:
  745. return qmi_timeout;
  746. }
  747. }
  748. unsigned int cnss_get_boot_timeout(struct device *dev)
  749. {
  750. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  751. if (!plat_priv) {
  752. cnss_pr_err("plat_priv is NULL\n");
  753. return 0;
  754. }
  755. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  756. }
  757. EXPORT_SYMBOL(cnss_get_boot_timeout);
  758. int cnss_power_up(struct device *dev)
  759. {
  760. int ret = 0;
  761. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  762. unsigned int timeout;
  763. if (!plat_priv) {
  764. cnss_pr_err("plat_priv is NULL\n");
  765. return -ENODEV;
  766. }
  767. cnss_pr_dbg("Powering up device\n");
  768. ret = cnss_driver_event_post(plat_priv,
  769. CNSS_DRIVER_EVENT_POWER_UP,
  770. CNSS_EVENT_SYNC, NULL);
  771. if (ret)
  772. goto out;
  773. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  774. goto out;
  775. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  776. reinit_completion(&plat_priv->power_up_complete);
  777. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  778. msecs_to_jiffies(timeout));
  779. if (!ret) {
  780. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  781. timeout);
  782. ret = -EAGAIN;
  783. goto out;
  784. }
  785. return 0;
  786. out:
  787. return ret;
  788. }
  789. EXPORT_SYMBOL(cnss_power_up);
  790. int cnss_power_down(struct device *dev)
  791. {
  792. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  793. if (!plat_priv) {
  794. cnss_pr_err("plat_priv is NULL\n");
  795. return -ENODEV;
  796. }
  797. cnss_pr_dbg("Powering down device\n");
  798. return cnss_driver_event_post(plat_priv,
  799. CNSS_DRIVER_EVENT_POWER_DOWN,
  800. CNSS_EVENT_SYNC, NULL);
  801. }
  802. EXPORT_SYMBOL(cnss_power_down);
  803. int cnss_idle_restart(struct device *dev)
  804. {
  805. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  806. unsigned int timeout;
  807. int ret = 0;
  808. if (!plat_priv) {
  809. cnss_pr_err("plat_priv is NULL\n");
  810. return -ENODEV;
  811. }
  812. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  813. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  814. return -EBUSY;
  815. }
  816. cnss_pr_dbg("Doing idle restart\n");
  817. reinit_completion(&plat_priv->power_up_complete);
  818. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  819. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  820. ret = -EINVAL;
  821. goto out;
  822. }
  823. ret = cnss_driver_event_post(plat_priv,
  824. CNSS_DRIVER_EVENT_IDLE_RESTART,
  825. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  826. if (ret)
  827. goto out;
  828. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  829. ret = cnss_bus_call_driver_probe(plat_priv);
  830. goto out;
  831. }
  832. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  833. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  834. msecs_to_jiffies(timeout));
  835. if (plat_priv->power_up_error) {
  836. ret = plat_priv->power_up_error;
  837. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  838. cnss_pr_dbg("Power up error:%d, exiting\n",
  839. plat_priv->power_up_error);
  840. goto out;
  841. }
  842. if (!ret) {
  843. /* This exception occurs after attempting retry of FW recovery.
  844. * Thus we can safely power off the device.
  845. */
  846. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  847. timeout);
  848. ret = -ETIMEDOUT;
  849. cnss_power_down(dev);
  850. CNSS_ASSERT(0);
  851. goto out;
  852. }
  853. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  854. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  855. del_timer(&plat_priv->fw_boot_timer);
  856. ret = -EINVAL;
  857. goto out;
  858. }
  859. mutex_unlock(&plat_priv->driver_ops_lock);
  860. return 0;
  861. out:
  862. mutex_unlock(&plat_priv->driver_ops_lock);
  863. return ret;
  864. }
  865. EXPORT_SYMBOL(cnss_idle_restart);
  866. int cnss_idle_shutdown(struct device *dev)
  867. {
  868. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  869. unsigned int timeout;
  870. int ret;
  871. if (!plat_priv) {
  872. cnss_pr_err("plat_priv is NULL\n");
  873. return -ENODEV;
  874. }
  875. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  876. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  877. return -EAGAIN;
  878. }
  879. cnss_pr_dbg("Doing idle shutdown\n");
  880. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  881. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  882. goto skip_wait;
  883. reinit_completion(&plat_priv->recovery_complete);
  884. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  885. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  886. msecs_to_jiffies(timeout));
  887. if (!ret) {
  888. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  889. timeout);
  890. CNSS_ASSERT(0);
  891. }
  892. skip_wait:
  893. return cnss_driver_event_post(plat_priv,
  894. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  895. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  896. }
  897. EXPORT_SYMBOL(cnss_idle_shutdown);
  898. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  899. {
  900. int ret = 0;
  901. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  902. if (ret) {
  903. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  904. goto out;
  905. }
  906. ret = cnss_get_clk(plat_priv);
  907. if (ret) {
  908. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  909. goto put_vreg;
  910. }
  911. ret = cnss_get_pinctrl(plat_priv);
  912. if (ret) {
  913. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  914. goto put_clk;
  915. }
  916. return 0;
  917. put_clk:
  918. cnss_put_clk(plat_priv);
  919. put_vreg:
  920. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  921. out:
  922. return ret;
  923. }
  924. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  925. {
  926. cnss_put_clk(plat_priv);
  927. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  928. }
  929. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  930. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  931. unsigned long code,
  932. void *ss_handle)
  933. {
  934. struct cnss_plat_data *plat_priv =
  935. container_of(nb, struct cnss_plat_data, modem_nb);
  936. struct cnss_esoc_info *esoc_info;
  937. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  938. if (!plat_priv)
  939. return NOTIFY_DONE;
  940. esoc_info = &plat_priv->esoc_info;
  941. if (code == SUBSYS_AFTER_POWERUP)
  942. esoc_info->modem_current_status = 1;
  943. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  944. esoc_info->modem_current_status = 0;
  945. else
  946. return NOTIFY_DONE;
  947. if (!cnss_bus_call_driver_modem_status(plat_priv,
  948. esoc_info->modem_current_status))
  949. return NOTIFY_DONE;
  950. return NOTIFY_OK;
  951. }
  952. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  953. {
  954. int ret = 0;
  955. struct device *dev;
  956. struct cnss_esoc_info *esoc_info;
  957. struct esoc_desc *esoc_desc;
  958. const char *client_desc;
  959. dev = &plat_priv->plat_dev->dev;
  960. esoc_info = &plat_priv->esoc_info;
  961. esoc_info->notify_modem_status =
  962. of_property_read_bool(dev->of_node,
  963. "qcom,notify-modem-status");
  964. if (!esoc_info->notify_modem_status)
  965. goto out;
  966. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  967. &client_desc);
  968. if (ret) {
  969. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  970. } else {
  971. esoc_desc = devm_register_esoc_client(dev, client_desc);
  972. if (IS_ERR_OR_NULL(esoc_desc)) {
  973. ret = PTR_RET(esoc_desc);
  974. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  975. ret);
  976. goto out;
  977. }
  978. esoc_info->esoc_desc = esoc_desc;
  979. }
  980. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  981. esoc_info->modem_current_status = 0;
  982. esoc_info->modem_notify_handler =
  983. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  984. esoc_info->esoc_desc->name :
  985. "modem", &plat_priv->modem_nb);
  986. if (IS_ERR(esoc_info->modem_notify_handler)) {
  987. ret = PTR_ERR(esoc_info->modem_notify_handler);
  988. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  989. ret);
  990. goto unreg_esoc;
  991. }
  992. return 0;
  993. unreg_esoc:
  994. if (esoc_info->esoc_desc)
  995. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  996. out:
  997. return ret;
  998. }
  999. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1000. {
  1001. struct device *dev;
  1002. struct cnss_esoc_info *esoc_info;
  1003. dev = &plat_priv->plat_dev->dev;
  1004. esoc_info = &plat_priv->esoc_info;
  1005. if (esoc_info->notify_modem_status)
  1006. subsys_notif_unregister_notifier
  1007. (esoc_info->modem_notify_handler,
  1008. &plat_priv->modem_nb);
  1009. if (esoc_info->esoc_desc)
  1010. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1011. }
  1012. #else
  1013. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1014. {
  1015. return 0;
  1016. }
  1017. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1018. #endif
  1019. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1020. {
  1021. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1022. int ret = 0;
  1023. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1024. return 0;
  1025. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1026. if (ret)
  1027. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1028. ret);
  1029. return ret;
  1030. }
  1031. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1032. {
  1033. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1034. int ret = 0;
  1035. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1036. return 0;
  1037. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1038. if (ret)
  1039. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1040. ret);
  1041. return ret;
  1042. }
  1043. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1044. {
  1045. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1046. if (sol_gpio->dev_sol_gpio < 0)
  1047. return -EINVAL;
  1048. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1049. }
  1050. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1051. {
  1052. struct cnss_plat_data *plat_priv = data;
  1053. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1054. sol_gpio->dev_sol_counter++;
  1055. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1056. irq, sol_gpio->dev_sol_counter);
  1057. /* Make sure abort current suspend */
  1058. cnss_pm_stay_awake(plat_priv);
  1059. cnss_pm_relax(plat_priv);
  1060. pm_system_wakeup();
  1061. cnss_bus_handle_dev_sol_irq(plat_priv);
  1062. return IRQ_HANDLED;
  1063. }
  1064. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1065. {
  1066. struct device *dev = &plat_priv->plat_dev->dev;
  1067. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1068. int ret = 0;
  1069. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1070. "wlan-dev-sol-gpio", 0);
  1071. if (sol_gpio->dev_sol_gpio < 0)
  1072. goto out;
  1073. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1074. sol_gpio->dev_sol_gpio);
  1075. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1076. if (ret) {
  1077. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1078. ret);
  1079. goto out;
  1080. }
  1081. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1082. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1083. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1084. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1085. if (ret) {
  1086. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1087. goto free_gpio;
  1088. }
  1089. return 0;
  1090. free_gpio:
  1091. gpio_free(sol_gpio->dev_sol_gpio);
  1092. out:
  1093. return ret;
  1094. }
  1095. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1096. {
  1097. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1098. if (sol_gpio->dev_sol_gpio < 0)
  1099. return;
  1100. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1101. gpio_free(sol_gpio->dev_sol_gpio);
  1102. }
  1103. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1104. {
  1105. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1106. if (sol_gpio->host_sol_gpio < 0)
  1107. return -EINVAL;
  1108. if (value)
  1109. cnss_pr_dbg("Assert host SOL GPIO\n");
  1110. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1111. return 0;
  1112. }
  1113. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1114. {
  1115. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1116. if (sol_gpio->host_sol_gpio < 0)
  1117. return -EINVAL;
  1118. return gpio_get_value(sol_gpio->host_sol_gpio);
  1119. }
  1120. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1121. {
  1122. struct device *dev = &plat_priv->plat_dev->dev;
  1123. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1124. int ret = 0;
  1125. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1126. "wlan-host-sol-gpio", 0);
  1127. if (sol_gpio->host_sol_gpio < 0)
  1128. goto out;
  1129. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1130. sol_gpio->host_sol_gpio);
  1131. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1132. if (ret) {
  1133. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1134. ret);
  1135. goto out;
  1136. }
  1137. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1138. return 0;
  1139. out:
  1140. return ret;
  1141. }
  1142. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1143. {
  1144. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1145. if (sol_gpio->host_sol_gpio < 0)
  1146. return;
  1147. gpio_free(sol_gpio->host_sol_gpio);
  1148. }
  1149. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1150. {
  1151. int ret;
  1152. ret = cnss_init_dev_sol_gpio(plat_priv);
  1153. if (ret)
  1154. goto out;
  1155. ret = cnss_init_host_sol_gpio(plat_priv);
  1156. if (ret)
  1157. goto deinit_dev_sol;
  1158. return 0;
  1159. deinit_dev_sol:
  1160. cnss_deinit_dev_sol_gpio(plat_priv);
  1161. out:
  1162. return ret;
  1163. }
  1164. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1165. {
  1166. cnss_deinit_host_sol_gpio(plat_priv);
  1167. cnss_deinit_dev_sol_gpio(plat_priv);
  1168. }
  1169. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1170. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1171. {
  1172. struct cnss_plat_data *plat_priv;
  1173. int ret = 0;
  1174. if (!subsys_desc->dev) {
  1175. cnss_pr_err("dev from subsys_desc is NULL\n");
  1176. return -ENODEV;
  1177. }
  1178. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1179. if (!plat_priv) {
  1180. cnss_pr_err("plat_priv is NULL\n");
  1181. return -ENODEV;
  1182. }
  1183. if (!plat_priv->driver_state) {
  1184. cnss_pr_dbg("Powerup is ignored\n");
  1185. return 0;
  1186. }
  1187. ret = cnss_bus_dev_powerup(plat_priv);
  1188. if (ret)
  1189. __pm_relax(plat_priv->recovery_ws);
  1190. return ret;
  1191. }
  1192. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1193. bool force_stop)
  1194. {
  1195. struct cnss_plat_data *plat_priv;
  1196. if (!subsys_desc->dev) {
  1197. cnss_pr_err("dev from subsys_desc is NULL\n");
  1198. return -ENODEV;
  1199. }
  1200. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1201. if (!plat_priv) {
  1202. cnss_pr_err("plat_priv is NULL\n");
  1203. return -ENODEV;
  1204. }
  1205. if (!plat_priv->driver_state) {
  1206. cnss_pr_dbg("shutdown is ignored\n");
  1207. return 0;
  1208. }
  1209. return cnss_bus_dev_shutdown(plat_priv);
  1210. }
  1211. void cnss_device_crashed(struct device *dev)
  1212. {
  1213. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1214. struct cnss_subsys_info *subsys_info;
  1215. if (!plat_priv)
  1216. return;
  1217. subsys_info = &plat_priv->subsys_info;
  1218. if (subsys_info->subsys_device) {
  1219. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1220. subsys_set_crash_status(subsys_info->subsys_device, true);
  1221. subsystem_restart_dev(subsys_info->subsys_device);
  1222. }
  1223. }
  1224. EXPORT_SYMBOL(cnss_device_crashed);
  1225. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1226. {
  1227. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1228. if (!plat_priv) {
  1229. cnss_pr_err("plat_priv is NULL\n");
  1230. return;
  1231. }
  1232. cnss_bus_dev_crash_shutdown(plat_priv);
  1233. }
  1234. static int cnss_subsys_ramdump(int enable,
  1235. const struct subsys_desc *subsys_desc)
  1236. {
  1237. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1238. if (!plat_priv) {
  1239. cnss_pr_err("plat_priv is NULL\n");
  1240. return -ENODEV;
  1241. }
  1242. if (!enable)
  1243. return 0;
  1244. return cnss_bus_dev_ramdump(plat_priv);
  1245. }
  1246. static void cnss_recovery_work_handler(struct work_struct *work)
  1247. {
  1248. }
  1249. #else
  1250. static void cnss_recovery_work_handler(struct work_struct *work)
  1251. {
  1252. int ret;
  1253. struct cnss_plat_data *plat_priv =
  1254. container_of(work, struct cnss_plat_data, recovery_work);
  1255. if (!plat_priv->recovery_enabled)
  1256. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1257. cnss_bus_dev_shutdown(plat_priv);
  1258. cnss_bus_dev_ramdump(plat_priv);
  1259. msleep(POWER_RESET_MIN_DELAY_MS);
  1260. ret = cnss_bus_dev_powerup(plat_priv);
  1261. if (ret)
  1262. __pm_relax(plat_priv->recovery_ws);
  1263. return;
  1264. }
  1265. void cnss_device_crashed(struct device *dev)
  1266. {
  1267. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1268. if (!plat_priv)
  1269. return;
  1270. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1271. schedule_work(&plat_priv->recovery_work);
  1272. }
  1273. EXPORT_SYMBOL(cnss_device_crashed);
  1274. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1275. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1276. {
  1277. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1278. struct cnss_ramdump_info *ramdump_info;
  1279. if (!plat_priv)
  1280. return NULL;
  1281. ramdump_info = &plat_priv->ramdump_info;
  1282. *size = ramdump_info->ramdump_size;
  1283. return ramdump_info->ramdump_va;
  1284. }
  1285. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1286. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1287. {
  1288. switch (reason) {
  1289. case CNSS_REASON_DEFAULT:
  1290. return "DEFAULT";
  1291. case CNSS_REASON_LINK_DOWN:
  1292. return "LINK_DOWN";
  1293. case CNSS_REASON_RDDM:
  1294. return "RDDM";
  1295. case CNSS_REASON_TIMEOUT:
  1296. return "TIMEOUT";
  1297. }
  1298. return "UNKNOWN";
  1299. };
  1300. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1301. enum cnss_recovery_reason reason)
  1302. {
  1303. plat_priv->recovery_count++;
  1304. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1305. goto self_recovery;
  1306. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1307. cnss_pr_dbg("Skip device recovery\n");
  1308. return 0;
  1309. }
  1310. /* FW recovery sequence has multiple steps and firmware load requires
  1311. * linux PM in awake state. Thus hold the cnss wake source until
  1312. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1313. * time taken in this process.
  1314. */
  1315. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1316. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1317. true);
  1318. switch (reason) {
  1319. case CNSS_REASON_LINK_DOWN:
  1320. if (!cnss_bus_check_link_status(plat_priv)) {
  1321. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1322. return 0;
  1323. }
  1324. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1325. &plat_priv->ctrl_params.quirks))
  1326. goto self_recovery;
  1327. if (!cnss_bus_recover_link_down(plat_priv)) {
  1328. /* clear recovery bit here to avoid skipping
  1329. * the recovery work for RDDM later
  1330. */
  1331. clear_bit(CNSS_DRIVER_RECOVERY,
  1332. &plat_priv->driver_state);
  1333. return 0;
  1334. }
  1335. break;
  1336. case CNSS_REASON_RDDM:
  1337. cnss_bus_collect_dump_info(plat_priv, false);
  1338. break;
  1339. case CNSS_REASON_DEFAULT:
  1340. case CNSS_REASON_TIMEOUT:
  1341. break;
  1342. default:
  1343. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1344. cnss_recovery_reason_to_str(reason), reason);
  1345. break;
  1346. }
  1347. cnss_bus_device_crashed(plat_priv);
  1348. return 0;
  1349. self_recovery:
  1350. cnss_pr_dbg("Going for self recovery\n");
  1351. cnss_bus_dev_shutdown(plat_priv);
  1352. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1353. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1354. &plat_priv->ctrl_params.quirks);
  1355. cnss_bus_dev_powerup(plat_priv);
  1356. return 0;
  1357. }
  1358. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1359. void *data)
  1360. {
  1361. struct cnss_recovery_data *recovery_data = data;
  1362. int ret = 0;
  1363. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1364. cnss_recovery_reason_to_str(recovery_data->reason),
  1365. recovery_data->reason);
  1366. if (!plat_priv->driver_state) {
  1367. cnss_pr_err("Improper driver state, ignore recovery\n");
  1368. ret = -EINVAL;
  1369. goto out;
  1370. }
  1371. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1372. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1373. ret = -EINVAL;
  1374. goto out;
  1375. }
  1376. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1377. cnss_pr_err("Recovery is already in progress\n");
  1378. CNSS_ASSERT(0);
  1379. ret = -EINVAL;
  1380. goto out;
  1381. }
  1382. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1383. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1384. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1385. ret = -EINVAL;
  1386. goto out;
  1387. }
  1388. switch (plat_priv->device_id) {
  1389. case QCA6174_DEVICE_ID:
  1390. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1391. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1392. &plat_priv->driver_state)) {
  1393. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1394. ret = -EINVAL;
  1395. goto out;
  1396. }
  1397. break;
  1398. default:
  1399. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1400. set_bit(CNSS_FW_BOOT_RECOVERY,
  1401. &plat_priv->driver_state);
  1402. }
  1403. break;
  1404. }
  1405. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1406. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1407. out:
  1408. kfree(data);
  1409. return ret;
  1410. }
  1411. int cnss_self_recovery(struct device *dev,
  1412. enum cnss_recovery_reason reason)
  1413. {
  1414. cnss_schedule_recovery(dev, reason);
  1415. return 0;
  1416. }
  1417. EXPORT_SYMBOL(cnss_self_recovery);
  1418. void cnss_schedule_recovery(struct device *dev,
  1419. enum cnss_recovery_reason reason)
  1420. {
  1421. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1422. struct cnss_recovery_data *data;
  1423. int gfp = GFP_KERNEL;
  1424. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1425. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1426. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1427. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1428. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1429. return;
  1430. }
  1431. if (in_interrupt() || irqs_disabled())
  1432. gfp = GFP_ATOMIC;
  1433. data = kzalloc(sizeof(*data), gfp);
  1434. if (!data)
  1435. return;
  1436. data->reason = reason;
  1437. cnss_driver_event_post(plat_priv,
  1438. CNSS_DRIVER_EVENT_RECOVERY,
  1439. 0, data);
  1440. }
  1441. EXPORT_SYMBOL(cnss_schedule_recovery);
  1442. int cnss_force_fw_assert(struct device *dev)
  1443. {
  1444. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1445. if (!plat_priv) {
  1446. cnss_pr_err("plat_priv is NULL\n");
  1447. return -ENODEV;
  1448. }
  1449. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1450. cnss_pr_info("Forced FW assert is not supported\n");
  1451. return -EOPNOTSUPP;
  1452. }
  1453. if (cnss_bus_is_device_down(plat_priv)) {
  1454. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1455. return 0;
  1456. }
  1457. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1458. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1459. return 0;
  1460. }
  1461. if (in_interrupt() || irqs_disabled())
  1462. cnss_driver_event_post(plat_priv,
  1463. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1464. 0, NULL);
  1465. else
  1466. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1467. return 0;
  1468. }
  1469. EXPORT_SYMBOL(cnss_force_fw_assert);
  1470. int cnss_force_collect_rddm(struct device *dev)
  1471. {
  1472. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1473. unsigned int timeout;
  1474. int ret = 0;
  1475. if (!plat_priv) {
  1476. cnss_pr_err("plat_priv is NULL\n");
  1477. return -ENODEV;
  1478. }
  1479. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1480. cnss_pr_info("Force collect rddm is not supported\n");
  1481. return -EOPNOTSUPP;
  1482. }
  1483. if (cnss_bus_is_device_down(plat_priv)) {
  1484. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1485. goto wait_rddm;
  1486. }
  1487. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1488. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1489. goto wait_rddm;
  1490. }
  1491. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1492. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1493. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1494. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1495. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1496. return 0;
  1497. }
  1498. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1499. if (ret)
  1500. return ret;
  1501. wait_rddm:
  1502. reinit_completion(&plat_priv->rddm_complete);
  1503. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1504. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1505. msecs_to_jiffies(timeout));
  1506. if (!ret) {
  1507. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1508. timeout);
  1509. ret = -ETIMEDOUT;
  1510. } else if (ret > 0) {
  1511. ret = 0;
  1512. }
  1513. return ret;
  1514. }
  1515. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1516. int cnss_qmi_send_get(struct device *dev)
  1517. {
  1518. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1519. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1520. return 0;
  1521. return cnss_bus_qmi_send_get(plat_priv);
  1522. }
  1523. EXPORT_SYMBOL(cnss_qmi_send_get);
  1524. int cnss_qmi_send_put(struct device *dev)
  1525. {
  1526. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1527. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1528. return 0;
  1529. return cnss_bus_qmi_send_put(plat_priv);
  1530. }
  1531. EXPORT_SYMBOL(cnss_qmi_send_put);
  1532. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1533. int cmd_len, void *cb_ctx,
  1534. int (*cb)(void *ctx, void *event, int event_len))
  1535. {
  1536. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1537. int ret;
  1538. if (!plat_priv)
  1539. return -ENODEV;
  1540. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1541. return -EINVAL;
  1542. plat_priv->get_info_cb = cb;
  1543. plat_priv->get_info_cb_ctx = cb_ctx;
  1544. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1545. if (ret) {
  1546. plat_priv->get_info_cb = NULL;
  1547. plat_priv->get_info_cb_ctx = NULL;
  1548. }
  1549. return ret;
  1550. }
  1551. EXPORT_SYMBOL(cnss_qmi_send);
  1552. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1553. {
  1554. int ret = 0;
  1555. u32 retry = 0;
  1556. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1557. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1558. goto out;
  1559. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1560. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1561. goto out;
  1562. }
  1563. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1564. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1565. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1566. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1567. CNSS_ASSERT(0);
  1568. return -EINVAL;
  1569. }
  1570. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1571. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1572. break;
  1573. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1574. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1575. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1576. CNSS_ASSERT(0);
  1577. ret = -EINVAL;
  1578. goto mark_cal_fail;
  1579. }
  1580. }
  1581. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1582. reinit_completion(&plat_priv->cal_complete);
  1583. ret = cnss_bus_dev_powerup(plat_priv);
  1584. mark_cal_fail:
  1585. if (ret) {
  1586. complete(&plat_priv->cal_complete);
  1587. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1588. /* Set CBC done in driver state to mark attempt and note error
  1589. * since calibration cannot be retried at boot.
  1590. */
  1591. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1592. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1593. }
  1594. out:
  1595. return ret;
  1596. }
  1597. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1598. void *data)
  1599. {
  1600. struct cnss_cal_info *cal_info = data;
  1601. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1602. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1603. goto out;
  1604. switch (cal_info->cal_status) {
  1605. case CNSS_CAL_DONE:
  1606. cnss_pr_dbg("Calibration completed successfully\n");
  1607. plat_priv->cal_done = true;
  1608. break;
  1609. case CNSS_CAL_TIMEOUT:
  1610. case CNSS_CAL_FAILURE:
  1611. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1612. cal_info->cal_status);
  1613. break;
  1614. default:
  1615. cnss_pr_err("Unknown calibration status: %u\n",
  1616. cal_info->cal_status);
  1617. break;
  1618. }
  1619. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1620. cnss_bus_free_qdss_mem(plat_priv);
  1621. cnss_release_antenna_sharing(plat_priv);
  1622. cnss_bus_dev_shutdown(plat_priv);
  1623. msleep(POWER_RESET_MIN_DELAY_MS);
  1624. complete(&plat_priv->cal_complete);
  1625. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1626. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1627. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1628. cnss_cal_mem_upload_to_file(plat_priv);
  1629. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work)
  1630. ) {
  1631. cnss_pr_dbg("Schedule WLAN driver load\n");
  1632. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1633. 0);
  1634. }
  1635. }
  1636. out:
  1637. kfree(data);
  1638. return 0;
  1639. }
  1640. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1641. {
  1642. int ret;
  1643. ret = cnss_bus_dev_powerup(plat_priv);
  1644. if (ret)
  1645. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1646. return ret;
  1647. }
  1648. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1649. {
  1650. cnss_bus_dev_shutdown(plat_priv);
  1651. return 0;
  1652. }
  1653. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1654. {
  1655. int ret = 0;
  1656. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1657. if (ret < 0)
  1658. return ret;
  1659. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1660. }
  1661. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1662. u32 mem_seg_len, u64 pa, u32 size)
  1663. {
  1664. int i = 0;
  1665. u64 offset = 0;
  1666. void *va = NULL;
  1667. u64 local_pa;
  1668. u32 local_size;
  1669. for (i = 0; i < mem_seg_len; i++) {
  1670. local_pa = (u64)fw_mem[i].pa;
  1671. local_size = (u32)fw_mem[i].size;
  1672. if (pa == local_pa && size <= local_size) {
  1673. va = fw_mem[i].va;
  1674. break;
  1675. }
  1676. if (pa > local_pa &&
  1677. pa < local_pa + local_size &&
  1678. pa + size <= local_pa + local_size) {
  1679. offset = pa - local_pa;
  1680. va = fw_mem[i].va + offset;
  1681. break;
  1682. }
  1683. }
  1684. return va;
  1685. }
  1686. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1687. void *data)
  1688. {
  1689. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1690. struct cnss_fw_mem *fw_mem_seg;
  1691. int ret = 0L;
  1692. void *va = NULL;
  1693. u32 i, fw_mem_seg_len;
  1694. switch (event_data->mem_type) {
  1695. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1696. if (!plat_priv->fw_mem_seg_len)
  1697. goto invalid_mem_save;
  1698. fw_mem_seg = plat_priv->fw_mem;
  1699. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1700. break;
  1701. case QMI_WLFW_MEM_QDSS_V01:
  1702. if (!plat_priv->qdss_mem_seg_len)
  1703. goto invalid_mem_save;
  1704. fw_mem_seg = plat_priv->qdss_mem;
  1705. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1706. break;
  1707. default:
  1708. goto invalid_mem_save;
  1709. }
  1710. for (i = 0; i < event_data->mem_seg_len; i++) {
  1711. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1712. event_data->mem_seg[i].addr,
  1713. event_data->mem_seg[i].size);
  1714. if (!va) {
  1715. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1716. &event_data->mem_seg[i].addr,
  1717. event_data->mem_type);
  1718. ret = -EINVAL;
  1719. break;
  1720. }
  1721. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1722. event_data->file_name,
  1723. event_data->mem_seg[i].size);
  1724. if (ret < 0) {
  1725. cnss_pr_err("Fail to save fw mem data: %d\n",
  1726. ret);
  1727. break;
  1728. }
  1729. }
  1730. kfree(data);
  1731. return ret;
  1732. invalid_mem_save:
  1733. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1734. event_data->mem_type);
  1735. kfree(data);
  1736. return -EINVAL;
  1737. }
  1738. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1739. {
  1740. cnss_bus_free_qdss_mem(plat_priv);
  1741. return 0;
  1742. }
  1743. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1744. void *data)
  1745. {
  1746. int ret = 0;
  1747. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1748. if (!plat_priv)
  1749. return -ENODEV;
  1750. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1751. event_data->total_size);
  1752. kfree(data);
  1753. return ret;
  1754. }
  1755. static void cnss_driver_event_work(struct work_struct *work)
  1756. {
  1757. struct cnss_plat_data *plat_priv =
  1758. container_of(work, struct cnss_plat_data, event_work);
  1759. struct cnss_driver_event *event;
  1760. unsigned long flags;
  1761. int ret = 0;
  1762. if (!plat_priv) {
  1763. cnss_pr_err("plat_priv is NULL!\n");
  1764. return;
  1765. }
  1766. cnss_pm_stay_awake(plat_priv);
  1767. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1768. while (!list_empty(&plat_priv->event_list)) {
  1769. event = list_first_entry(&plat_priv->event_list,
  1770. struct cnss_driver_event, list);
  1771. list_del(&event->list);
  1772. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1773. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1774. cnss_driver_event_to_str(event->type),
  1775. event->sync ? "-sync" : "", event->type,
  1776. plat_priv->driver_state);
  1777. switch (event->type) {
  1778. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1779. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1780. break;
  1781. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1782. ret = cnss_wlfw_server_exit(plat_priv);
  1783. break;
  1784. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1785. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1786. if (ret)
  1787. break;
  1788. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1789. break;
  1790. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1791. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1792. break;
  1793. case CNSS_DRIVER_EVENT_FW_READY:
  1794. ret = cnss_fw_ready_hdlr(plat_priv);
  1795. break;
  1796. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1797. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1798. break;
  1799. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1800. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1801. event->data);
  1802. break;
  1803. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1804. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1805. event->data);
  1806. break;
  1807. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1808. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1809. break;
  1810. case CNSS_DRIVER_EVENT_RECOVERY:
  1811. ret = cnss_driver_recovery_hdlr(plat_priv,
  1812. event->data);
  1813. break;
  1814. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1815. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1816. break;
  1817. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1818. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1819. &plat_priv->driver_state);
  1820. /* fall through */
  1821. case CNSS_DRIVER_EVENT_POWER_UP:
  1822. ret = cnss_power_up_hdlr(plat_priv);
  1823. break;
  1824. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1825. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1826. &plat_priv->driver_state);
  1827. /* fall through */
  1828. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1829. ret = cnss_power_down_hdlr(plat_priv);
  1830. break;
  1831. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1832. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1833. event->data);
  1834. break;
  1835. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1836. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1837. event->data);
  1838. break;
  1839. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1840. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1841. break;
  1842. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1843. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1844. event->data);
  1845. break;
  1846. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1847. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1848. break;
  1849. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1850. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1851. event->data);
  1852. break;
  1853. default:
  1854. cnss_pr_err("Invalid driver event type: %d",
  1855. event->type);
  1856. kfree(event);
  1857. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1858. continue;
  1859. }
  1860. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1861. if (event->sync) {
  1862. event->ret = ret;
  1863. complete(&event->complete);
  1864. continue;
  1865. }
  1866. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1867. kfree(event);
  1868. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1869. }
  1870. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1871. cnss_pm_relax(plat_priv);
  1872. }
  1873. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1874. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1875. {
  1876. int ret = 0;
  1877. struct cnss_subsys_info *subsys_info;
  1878. subsys_info = &plat_priv->subsys_info;
  1879. subsys_info->subsys_desc.name = "wlan";
  1880. subsys_info->subsys_desc.owner = THIS_MODULE;
  1881. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1882. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1883. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1884. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1885. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1886. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1887. if (IS_ERR(subsys_info->subsys_device)) {
  1888. ret = PTR_ERR(subsys_info->subsys_device);
  1889. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1890. goto out;
  1891. }
  1892. subsys_info->subsys_handle =
  1893. subsystem_get(subsys_info->subsys_desc.name);
  1894. if (!subsys_info->subsys_handle) {
  1895. cnss_pr_err("Failed to get subsys_handle!\n");
  1896. ret = -EINVAL;
  1897. goto unregister_subsys;
  1898. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1899. ret = PTR_ERR(subsys_info->subsys_handle);
  1900. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1901. goto unregister_subsys;
  1902. }
  1903. return 0;
  1904. unregister_subsys:
  1905. subsys_unregister(subsys_info->subsys_device);
  1906. out:
  1907. return ret;
  1908. }
  1909. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1910. {
  1911. struct cnss_subsys_info *subsys_info;
  1912. subsys_info = &plat_priv->subsys_info;
  1913. subsystem_put(subsys_info->subsys_handle);
  1914. subsys_unregister(subsys_info->subsys_device);
  1915. }
  1916. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  1917. {
  1918. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  1919. return create_ramdump_device(subsys_info->subsys_desc.name,
  1920. subsys_info->subsys_desc.dev);
  1921. }
  1922. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  1923. void *ramdump_dev)
  1924. {
  1925. destroy_ramdump_device(ramdump_dev);
  1926. }
  1927. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  1928. {
  1929. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  1930. struct ramdump_segment segment;
  1931. memset(&segment, 0, sizeof(segment));
  1932. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  1933. segment.size = ramdump_info->ramdump_size;
  1934. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  1935. }
  1936. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  1937. {
  1938. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  1939. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  1940. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  1941. struct ramdump_segment *ramdump_segs, *s;
  1942. struct cnss_dump_meta_info meta_info = {0};
  1943. int i, ret = 0;
  1944. ramdump_segs = kcalloc(dump_data->nentries + 1,
  1945. sizeof(*ramdump_segs),
  1946. GFP_KERNEL);
  1947. if (!ramdump_segs)
  1948. return -ENOMEM;
  1949. s = ramdump_segs + 1;
  1950. for (i = 0; i < dump_data->nentries; i++) {
  1951. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  1952. cnss_pr_err("Unsupported dump type: %d",
  1953. dump_seg->type);
  1954. continue;
  1955. }
  1956. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  1957. meta_info.entry[dump_seg->type].type = dump_seg->type;
  1958. meta_info.entry[dump_seg->type].entry_start = i + 1;
  1959. }
  1960. meta_info.entry[dump_seg->type].entry_num++;
  1961. s->address = dump_seg->address;
  1962. s->v_address = (void __iomem *)dump_seg->v_address;
  1963. s->size = dump_seg->size;
  1964. s++;
  1965. dump_seg++;
  1966. }
  1967. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  1968. meta_info.version = CNSS_RAMDUMP_VERSION;
  1969. meta_info.chipset = plat_priv->device_id;
  1970. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  1971. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  1972. ramdump_segs->size = sizeof(meta_info);
  1973. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  1974. dump_data->nentries + 1);
  1975. kfree(ramdump_segs);
  1976. return ret;
  1977. }
  1978. #else
  1979. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  1980. void *data)
  1981. {
  1982. struct cnss_plat_data *plat_priv =
  1983. container_of(nb, struct cnss_plat_data, panic_nb);
  1984. cnss_bus_dev_crash_shutdown(plat_priv);
  1985. return NOTIFY_DONE;
  1986. }
  1987. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1988. {
  1989. int ret;
  1990. if (!plat_priv)
  1991. return -ENODEV;
  1992. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  1993. ret = atomic_notifier_chain_register(&panic_notifier_list,
  1994. &plat_priv->panic_nb);
  1995. if (ret) {
  1996. cnss_pr_err("Failed to register panic handler\n");
  1997. return -EINVAL;
  1998. }
  1999. return 0;
  2000. }
  2001. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2002. {
  2003. int ret;
  2004. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2005. &plat_priv->panic_nb);
  2006. if (ret)
  2007. cnss_pr_err("Failed to unregister panic handler\n");
  2008. }
  2009. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2010. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2011. {
  2012. return &plat_priv->plat_dev->dev;
  2013. }
  2014. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2015. void *ramdump_dev)
  2016. {
  2017. }
  2018. #endif
  2019. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2020. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2021. {
  2022. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2023. struct qcom_dump_segment segment;
  2024. struct list_head head;
  2025. INIT_LIST_HEAD(&head);
  2026. memset(&segment, 0, sizeof(segment));
  2027. segment.va = ramdump_info->ramdump_va;
  2028. segment.size = ramdump_info->ramdump_size;
  2029. list_add(&segment.node, &head);
  2030. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2031. }
  2032. #else
  2033. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2034. {
  2035. return 0;
  2036. }
  2037. /* Using completion event inside dynamically allocated ramdump_desc
  2038. * may result a race between freeing the event after setting it to
  2039. * complete inside dev coredump free callback and the thread that is
  2040. * waiting for completion.
  2041. */
  2042. DECLARE_COMPLETION(dump_done);
  2043. #define TIMEOUT_SAVE_DUMP_MS 30000
  2044. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2045. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2046. { \
  2047. if (class == ELFCLASS32) \
  2048. return sizeof(struct elf32_##__xhdr); \
  2049. else \
  2050. return sizeof(struct elf64_##__xhdr); \
  2051. }
  2052. SIZEOF_ELF_STRUCT(phdr)
  2053. SIZEOF_ELF_STRUCT(hdr)
  2054. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2055. do { \
  2056. if (class == ELFCLASS32) \
  2057. ((struct elf32_##__xhdr *)arg)->member = value; \
  2058. else \
  2059. ((struct elf64_##__xhdr *)arg)->member = value; \
  2060. } while (0)
  2061. #define set_ehdr_property(arg, class, member, value) \
  2062. set_xhdr_property(hdr, arg, class, member, value)
  2063. #define set_phdr_property(arg, class, member, value) \
  2064. set_xhdr_property(phdr, arg, class, member, value)
  2065. /* These replace qcom_ramdump driver APIs called from common API
  2066. * cnss_do_elf_dump() by the ones defined here.
  2067. */
  2068. #define qcom_dump_segment cnss_qcom_dump_segment
  2069. #define qcom_elf_dump cnss_qcom_elf_dump
  2070. #define dump_enabled cnss_dump_enabled
  2071. struct cnss_qcom_dump_segment {
  2072. struct list_head node;
  2073. dma_addr_t da;
  2074. void *va;
  2075. size_t size;
  2076. };
  2077. struct cnss_qcom_ramdump_desc {
  2078. void *data;
  2079. struct completion dump_done;
  2080. };
  2081. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2082. void *data, size_t datalen)
  2083. {
  2084. struct cnss_qcom_ramdump_desc *desc = data;
  2085. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2086. datalen);
  2087. }
  2088. static void cnss_qcom_devcd_freev(void *data)
  2089. {
  2090. struct cnss_qcom_ramdump_desc *desc = data;
  2091. cnss_pr_dbg("Free dump data for dev coredump\n");
  2092. complete(&dump_done);
  2093. vfree(desc->data);
  2094. kfree(desc);
  2095. }
  2096. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2097. gfp_t gfp)
  2098. {
  2099. struct cnss_qcom_ramdump_desc *desc;
  2100. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2101. int ret;
  2102. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2103. if (!desc)
  2104. return -ENOMEM;
  2105. desc->data = data;
  2106. reinit_completion(&dump_done);
  2107. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2108. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2109. ret = wait_for_completion_timeout(&dump_done,
  2110. msecs_to_jiffies(timeout));
  2111. if (!ret)
  2112. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2113. timeout);
  2114. return ret ? 0 : -ETIMEDOUT;
  2115. }
  2116. /* Since the elf32 and elf64 identification is identical apart from
  2117. * the class, use elf32 by default.
  2118. */
  2119. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2120. {
  2121. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2122. ehdr->e_ident[EI_CLASS] = class;
  2123. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2124. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2125. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2126. }
  2127. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2128. unsigned char class)
  2129. {
  2130. struct cnss_qcom_dump_segment *segment;
  2131. void *phdr, *ehdr;
  2132. size_t data_size, offset;
  2133. int phnum = 0;
  2134. void *data;
  2135. void __iomem *ptr;
  2136. if (!segs || list_empty(segs))
  2137. return -EINVAL;
  2138. data_size = sizeof_elf_hdr(class);
  2139. list_for_each_entry(segment, segs, node) {
  2140. data_size += sizeof_elf_phdr(class) + segment->size;
  2141. phnum++;
  2142. }
  2143. data = vmalloc(data_size);
  2144. if (!data)
  2145. return -ENOMEM;
  2146. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2147. ehdr = data;
  2148. memset(ehdr, 0, sizeof_elf_hdr(class));
  2149. init_elf_identification(ehdr, class);
  2150. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2151. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2152. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2153. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2154. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2155. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2156. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2157. phdr = data + sizeof_elf_hdr(class);
  2158. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2159. list_for_each_entry(segment, segs, node) {
  2160. memset(phdr, 0, sizeof_elf_phdr(class));
  2161. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2162. set_phdr_property(phdr, class, p_offset, offset);
  2163. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2164. set_phdr_property(phdr, class, p_paddr, segment->da);
  2165. set_phdr_property(phdr, class, p_filesz, segment->size);
  2166. set_phdr_property(phdr, class, p_memsz, segment->size);
  2167. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2168. set_phdr_property(phdr, class, p_align, 0);
  2169. if (segment->va) {
  2170. memcpy(data + offset, segment->va, segment->size);
  2171. } else {
  2172. ptr = devm_ioremap(dev, segment->da, segment->size);
  2173. if (!ptr) {
  2174. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2175. &segment->da, segment->size);
  2176. memset(data + offset, 0xff, segment->size);
  2177. } else {
  2178. memcpy_fromio(data + offset, ptr,
  2179. segment->size);
  2180. }
  2181. }
  2182. offset += segment->size;
  2183. phdr += sizeof_elf_phdr(class);
  2184. }
  2185. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2186. }
  2187. /* Saving dump to file system is always needed in this case. */
  2188. static bool cnss_dump_enabled(void)
  2189. {
  2190. return true;
  2191. }
  2192. #endif /* CONFIG_QCOM_RAMDUMP */
  2193. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2194. {
  2195. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2196. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2197. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2198. struct qcom_dump_segment *seg;
  2199. struct cnss_dump_meta_info meta_info = {0};
  2200. struct list_head head;
  2201. int i, ret = 0;
  2202. if (!dump_enabled()) {
  2203. cnss_pr_info("Dump collection is not enabled\n");
  2204. return ret;
  2205. }
  2206. INIT_LIST_HEAD(&head);
  2207. for (i = 0; i < dump_data->nentries; i++) {
  2208. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2209. cnss_pr_err("Unsupported dump type: %d",
  2210. dump_seg->type);
  2211. continue;
  2212. }
  2213. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2214. if (!seg)
  2215. continue;
  2216. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2217. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2218. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2219. }
  2220. meta_info.entry[dump_seg->type].entry_num++;
  2221. seg->da = dump_seg->address;
  2222. seg->va = dump_seg->v_address;
  2223. seg->size = dump_seg->size;
  2224. list_add_tail(&seg->node, &head);
  2225. dump_seg++;
  2226. }
  2227. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2228. if (!seg)
  2229. goto do_elf_dump;
  2230. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2231. meta_info.version = CNSS_RAMDUMP_VERSION;
  2232. meta_info.chipset = plat_priv->device_id;
  2233. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2234. seg->va = &meta_info;
  2235. seg->size = sizeof(meta_info);
  2236. list_add(&seg->node, &head);
  2237. do_elf_dump:
  2238. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2239. while (!list_empty(&head)) {
  2240. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2241. list_del(&seg->node);
  2242. kfree(seg);
  2243. }
  2244. return ret;
  2245. }
  2246. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2247. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2248. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2249. {
  2250. struct cnss_ramdump_info *ramdump_info;
  2251. struct msm_dump_entry dump_entry;
  2252. ramdump_info = &plat_priv->ramdump_info;
  2253. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2254. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2255. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2256. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2257. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2258. sizeof(ramdump_info->dump_data.name));
  2259. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2260. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2261. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2262. &dump_entry);
  2263. }
  2264. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2265. {
  2266. int ret = 0;
  2267. struct device *dev;
  2268. struct cnss_ramdump_info *ramdump_info;
  2269. u32 ramdump_size = 0;
  2270. dev = &plat_priv->plat_dev->dev;
  2271. ramdump_info = &plat_priv->ramdump_info;
  2272. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2273. &ramdump_size) == 0) {
  2274. ramdump_info->ramdump_va =
  2275. dma_alloc_coherent(dev, ramdump_size,
  2276. &ramdump_info->ramdump_pa,
  2277. GFP_KERNEL);
  2278. if (ramdump_info->ramdump_va)
  2279. ramdump_info->ramdump_size = ramdump_size;
  2280. }
  2281. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2282. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2283. if (ramdump_info->ramdump_size == 0) {
  2284. cnss_pr_info("Ramdump will not be collected");
  2285. goto out;
  2286. }
  2287. ret = cnss_init_dump_entry(plat_priv);
  2288. if (ret) {
  2289. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2290. goto free_ramdump;
  2291. }
  2292. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2293. if (!ramdump_info->ramdump_dev) {
  2294. cnss_pr_err("Failed to create ramdump device!");
  2295. ret = -ENOMEM;
  2296. goto free_ramdump;
  2297. }
  2298. return 0;
  2299. free_ramdump:
  2300. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2301. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2302. out:
  2303. return ret;
  2304. }
  2305. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2306. {
  2307. struct device *dev;
  2308. struct cnss_ramdump_info *ramdump_info;
  2309. dev = &plat_priv->plat_dev->dev;
  2310. ramdump_info = &plat_priv->ramdump_info;
  2311. if (ramdump_info->ramdump_dev)
  2312. cnss_destroy_ramdump_device(plat_priv,
  2313. ramdump_info->ramdump_dev);
  2314. if (ramdump_info->ramdump_va)
  2315. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2316. ramdump_info->ramdump_va,
  2317. ramdump_info->ramdump_pa);
  2318. }
  2319. /**
  2320. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2321. * @ret: Error returned by msm_dump_data_register_nominidump
  2322. *
  2323. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2324. * ignore failure.
  2325. *
  2326. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2327. */
  2328. static int cnss_ignore_dump_data_reg_fail(int ret)
  2329. {
  2330. return ret;
  2331. }
  2332. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2333. {
  2334. int ret = 0;
  2335. struct cnss_ramdump_info_v2 *info_v2;
  2336. struct cnss_dump_data *dump_data;
  2337. struct msm_dump_entry dump_entry;
  2338. struct device *dev = &plat_priv->plat_dev->dev;
  2339. u32 ramdump_size = 0;
  2340. info_v2 = &plat_priv->ramdump_info_v2;
  2341. dump_data = &info_v2->dump_data;
  2342. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2343. &ramdump_size) == 0)
  2344. info_v2->ramdump_size = ramdump_size;
  2345. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2346. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2347. if (!info_v2->dump_data_vaddr)
  2348. return -ENOMEM;
  2349. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2350. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2351. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2352. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2353. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2354. sizeof(dump_data->name));
  2355. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2356. dump_entry.addr = virt_to_phys(dump_data);
  2357. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2358. &dump_entry);
  2359. if (ret) {
  2360. ret = cnss_ignore_dump_data_reg_fail(ret);
  2361. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2362. ret ? "Error" : "Ignoring", ret);
  2363. goto free_ramdump;
  2364. }
  2365. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2366. if (!info_v2->ramdump_dev) {
  2367. cnss_pr_err("Failed to create ramdump device!\n");
  2368. ret = -ENOMEM;
  2369. goto free_ramdump;
  2370. }
  2371. return 0;
  2372. free_ramdump:
  2373. kfree(info_v2->dump_data_vaddr);
  2374. info_v2->dump_data_vaddr = NULL;
  2375. return ret;
  2376. }
  2377. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2378. {
  2379. struct cnss_ramdump_info_v2 *info_v2;
  2380. info_v2 = &plat_priv->ramdump_info_v2;
  2381. if (info_v2->ramdump_dev)
  2382. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2383. kfree(info_v2->dump_data_vaddr);
  2384. info_v2->dump_data_vaddr = NULL;
  2385. info_v2->dump_data_valid = false;
  2386. }
  2387. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2388. {
  2389. int ret = 0;
  2390. switch (plat_priv->device_id) {
  2391. case QCA6174_DEVICE_ID:
  2392. ret = cnss_register_ramdump_v1(plat_priv);
  2393. break;
  2394. case QCA6290_DEVICE_ID:
  2395. case QCA6390_DEVICE_ID:
  2396. case QCA6490_DEVICE_ID:
  2397. case KIWI_DEVICE_ID:
  2398. ret = cnss_register_ramdump_v2(plat_priv);
  2399. break;
  2400. default:
  2401. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2402. ret = -ENODEV;
  2403. break;
  2404. }
  2405. return ret;
  2406. }
  2407. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2408. {
  2409. switch (plat_priv->device_id) {
  2410. case QCA6174_DEVICE_ID:
  2411. cnss_unregister_ramdump_v1(plat_priv);
  2412. break;
  2413. case QCA6290_DEVICE_ID:
  2414. case QCA6390_DEVICE_ID:
  2415. case QCA6490_DEVICE_ID:
  2416. case KIWI_DEVICE_ID:
  2417. cnss_unregister_ramdump_v2(plat_priv);
  2418. break;
  2419. default:
  2420. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2421. break;
  2422. }
  2423. }
  2424. #else
  2425. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2426. {
  2427. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2428. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2429. struct device *dev = &plat_priv->plat_dev->dev;
  2430. u32 ramdump_size = 0;
  2431. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2432. &ramdump_size) == 0)
  2433. info_v2->ramdump_size = ramdump_size;
  2434. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2435. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2436. if (!info_v2->dump_data_vaddr)
  2437. return -ENOMEM;
  2438. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2439. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2440. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2441. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2442. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2443. sizeof(dump_data->name));
  2444. info_v2->ramdump_dev = dev;
  2445. return 0;
  2446. }
  2447. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2448. {
  2449. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2450. info_v2->ramdump_dev = NULL;
  2451. kfree(info_v2->dump_data_vaddr);
  2452. info_v2->dump_data_vaddr = NULL;
  2453. info_v2->dump_data_valid = false;
  2454. }
  2455. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2456. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2457. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2458. phys_addr_t *pa, unsigned long attrs)
  2459. {
  2460. struct sg_table sgt;
  2461. int ret;
  2462. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2463. if (ret) {
  2464. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2465. va, &dma, size, attrs);
  2466. return -EINVAL;
  2467. }
  2468. *pa = page_to_phys(sg_page(sgt.sgl));
  2469. sg_free_table(&sgt);
  2470. return 0;
  2471. }
  2472. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2473. enum cnss_fw_dump_type type, int seg_no,
  2474. void *va, phys_addr_t pa, size_t size)
  2475. {
  2476. struct md_region md_entry;
  2477. int ret;
  2478. switch (type) {
  2479. case CNSS_FW_IMAGE:
  2480. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2481. seg_no);
  2482. break;
  2483. case CNSS_FW_RDDM:
  2484. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2485. seg_no);
  2486. break;
  2487. case CNSS_FW_REMOTE_HEAP:
  2488. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2489. seg_no);
  2490. break;
  2491. default:
  2492. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2493. return -EINVAL;
  2494. }
  2495. md_entry.phys_addr = pa;
  2496. md_entry.virt_addr = (uintptr_t)va;
  2497. md_entry.size = size;
  2498. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2499. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2500. md_entry.name, va, &pa, size);
  2501. ret = msm_minidump_add_region(&md_entry);
  2502. if (ret < 0)
  2503. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2504. return ret;
  2505. }
  2506. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2507. enum cnss_fw_dump_type type, int seg_no,
  2508. void *va, phys_addr_t pa, size_t size)
  2509. {
  2510. struct md_region md_entry;
  2511. int ret;
  2512. switch (type) {
  2513. case CNSS_FW_IMAGE:
  2514. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2515. seg_no);
  2516. break;
  2517. case CNSS_FW_RDDM:
  2518. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2519. seg_no);
  2520. break;
  2521. case CNSS_FW_REMOTE_HEAP:
  2522. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2523. seg_no);
  2524. break;
  2525. default:
  2526. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2527. return -EINVAL;
  2528. }
  2529. md_entry.phys_addr = pa;
  2530. md_entry.virt_addr = (uintptr_t)va;
  2531. md_entry.size = size;
  2532. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2533. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2534. md_entry.name, va, &pa, size);
  2535. ret = msm_minidump_remove_region(&md_entry);
  2536. if (ret)
  2537. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2538. ret);
  2539. return ret;
  2540. }
  2541. #else
  2542. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2543. phys_addr_t *pa, unsigned long attrs)
  2544. {
  2545. return 0;
  2546. }
  2547. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2548. enum cnss_fw_dump_type type, int seg_no,
  2549. void *va, phys_addr_t pa, size_t size)
  2550. {
  2551. return 0;
  2552. }
  2553. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2554. enum cnss_fw_dump_type type, int seg_no,
  2555. void *va, phys_addr_t pa, size_t size)
  2556. {
  2557. return 0;
  2558. }
  2559. #endif /* CONFIG_QCOM_MINIDUMP */
  2560. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2561. const struct firmware **fw_entry,
  2562. const char *filename)
  2563. {
  2564. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2565. return request_firmware_direct(fw_entry, filename,
  2566. &plat_priv->plat_dev->dev);
  2567. else
  2568. return firmware_request_nowarn(fw_entry, filename,
  2569. &plat_priv->plat_dev->dev);
  2570. }
  2571. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2572. /**
  2573. * cnss_register_bus_scale() - Setup interconnect voting data
  2574. * @plat_priv: Platform data structure
  2575. *
  2576. * For different interconnect path configured in device tree setup voting data
  2577. * for list of bandwidth requirements.
  2578. *
  2579. * Result: 0 for success. -EINVAL if not configured
  2580. */
  2581. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2582. {
  2583. int ret = -EINVAL;
  2584. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2585. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2586. struct device *dev = &plat_priv->plat_dev->dev;
  2587. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2588. ret = of_property_read_u32(dev->of_node,
  2589. "qcom,icc-path-count",
  2590. &plat_priv->icc.path_count);
  2591. if (ret) {
  2592. cnss_pr_err("Platform Bus Interconnect path not configured\n");
  2593. return -EINVAL;
  2594. }
  2595. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2596. "qcom,bus-bw-cfg-count",
  2597. &plat_priv->icc.bus_bw_cfg_count);
  2598. if (ret) {
  2599. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2600. goto cleanup;
  2601. }
  2602. cfg_arr_size = plat_priv->icc.path_count *
  2603. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2604. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2605. if (!cfg_arr) {
  2606. cnss_pr_err("Failed to alloc cfg table mem\n");
  2607. ret = -ENOMEM;
  2608. goto cleanup;
  2609. }
  2610. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2611. "qcom,bus-bw-cfg", cfg_arr,
  2612. cfg_arr_size);
  2613. if (ret) {
  2614. cnss_pr_err("Invalid Bus BW Config Table\n");
  2615. goto cleanup;
  2616. }
  2617. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2618. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2619. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2620. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2621. GFP_KERNEL);
  2622. if (!bus_bw_info) {
  2623. ret = -ENOMEM;
  2624. goto out;
  2625. }
  2626. ret = of_property_read_string_index(dev->of_node,
  2627. "interconnect-names", idx,
  2628. &bus_bw_info->icc_name);
  2629. if (ret)
  2630. goto out;
  2631. bus_bw_info->icc_path =
  2632. of_icc_get(&plat_priv->plat_dev->dev,
  2633. bus_bw_info->icc_name);
  2634. if (IS_ERR(bus_bw_info->icc_path)) {
  2635. ret = PTR_ERR(bus_bw_info->icc_path);
  2636. if (ret != -EPROBE_DEFER) {
  2637. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2638. bus_bw_info->icc_name, ret);
  2639. goto out;
  2640. }
  2641. }
  2642. bus_bw_info->cfg_table =
  2643. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2644. sizeof(*bus_bw_info->cfg_table),
  2645. GFP_KERNEL);
  2646. if (!bus_bw_info->cfg_table) {
  2647. ret = -ENOMEM;
  2648. goto out;
  2649. }
  2650. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2651. bus_bw_info->icc_name);
  2652. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2653. CNSS_ICC_VOTE_MAX);
  2654. i < plat_priv->icc.bus_bw_cfg_count;
  2655. i++, j += 2) {
  2656. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2657. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2658. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2659. i, bus_bw_info->cfg_table[i].avg_bw,
  2660. bus_bw_info->cfg_table[i].peak_bw);
  2661. }
  2662. list_add_tail(&bus_bw_info->list,
  2663. &plat_priv->icc.list_head);
  2664. }
  2665. kfree(cfg_arr);
  2666. return 0;
  2667. out:
  2668. list_for_each_entry_safe(bus_bw_info, tmp,
  2669. &plat_priv->icc.list_head, list) {
  2670. list_del(&bus_bw_info->list);
  2671. }
  2672. cleanup:
  2673. kfree(cfg_arr);
  2674. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2675. return ret;
  2676. }
  2677. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2678. {
  2679. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2680. list_for_each_entry_safe(bus_bw_info, tmp,
  2681. &plat_priv->icc.list_head, list) {
  2682. list_del(&bus_bw_info->list);
  2683. if (bus_bw_info->icc_path)
  2684. icc_put(bus_bw_info->icc_path);
  2685. }
  2686. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2687. }
  2688. #else
  2689. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2690. {
  2691. return 0;
  2692. }
  2693. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2694. #endif /* CONFIG_INTERCONNECT */
  2695. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2696. {
  2697. struct cnss_plat_data *plat_priv = cb_ctx;
  2698. if (!plat_priv) {
  2699. cnss_pr_err("%s: Invalid context\n", __func__);
  2700. return;
  2701. }
  2702. if (status) {
  2703. cnss_pr_info("CNSS Daemon connected\n");
  2704. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2705. complete(&plat_priv->daemon_connected);
  2706. } else {
  2707. cnss_pr_info("CNSS Daemon disconnected\n");
  2708. reinit_completion(&plat_priv->daemon_connected);
  2709. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2710. }
  2711. }
  2712. static ssize_t enable_hds_store(struct device *dev,
  2713. struct device_attribute *attr,
  2714. const char *buf, size_t count)
  2715. {
  2716. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2717. unsigned int enable_hds = 0;
  2718. if (!plat_priv)
  2719. return -ENODEV;
  2720. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2721. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2722. return -EINVAL;
  2723. }
  2724. if (enable_hds)
  2725. plat_priv->hds_enabled = true;
  2726. else
  2727. plat_priv->hds_enabled = false;
  2728. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2729. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2730. return count;
  2731. }
  2732. static ssize_t recovery_store(struct device *dev,
  2733. struct device_attribute *attr,
  2734. const char *buf, size_t count)
  2735. {
  2736. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2737. unsigned int recovery = 0;
  2738. if (!plat_priv)
  2739. return -ENODEV;
  2740. if (sscanf(buf, "%du", &recovery) != 1) {
  2741. cnss_pr_err("Invalid recovery sysfs command\n");
  2742. return -EINVAL;
  2743. }
  2744. if (recovery)
  2745. plat_priv->recovery_enabled = true;
  2746. else
  2747. plat_priv->recovery_enabled = false;
  2748. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2749. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2750. return count;
  2751. }
  2752. static ssize_t shutdown_store(struct device *dev,
  2753. struct device_attribute *attr,
  2754. const char *buf, size_t count)
  2755. {
  2756. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2757. if (plat_priv) {
  2758. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2759. del_timer(&plat_priv->fw_boot_timer);
  2760. complete_all(&plat_priv->power_up_complete);
  2761. complete_all(&plat_priv->cal_complete);
  2762. }
  2763. cnss_pr_dbg("Received shutdown notification\n");
  2764. return count;
  2765. }
  2766. static ssize_t fs_ready_store(struct device *dev,
  2767. struct device_attribute *attr,
  2768. const char *buf, size_t count)
  2769. {
  2770. int fs_ready = 0;
  2771. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2772. if (sscanf(buf, "%du", &fs_ready) != 1)
  2773. return -EINVAL;
  2774. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2775. fs_ready, count);
  2776. if (!plat_priv) {
  2777. cnss_pr_err("plat_priv is NULL\n");
  2778. return count;
  2779. }
  2780. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2781. cnss_pr_dbg("QMI is bypassed\n");
  2782. return count;
  2783. }
  2784. switch (plat_priv->device_id) {
  2785. case QCA6290_DEVICE_ID:
  2786. case QCA6390_DEVICE_ID:
  2787. case QCA6490_DEVICE_ID:
  2788. case KIWI_DEVICE_ID:
  2789. break;
  2790. default:
  2791. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2792. plat_priv->device_id);
  2793. return count;
  2794. }
  2795. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2796. cnss_driver_event_post(plat_priv,
  2797. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2798. 0, NULL);
  2799. }
  2800. return count;
  2801. }
  2802. static ssize_t qdss_trace_start_store(struct device *dev,
  2803. struct device_attribute *attr,
  2804. const char *buf, size_t count)
  2805. {
  2806. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2807. wlfw_qdss_trace_start(plat_priv);
  2808. cnss_pr_dbg("Received QDSS start command\n");
  2809. return count;
  2810. }
  2811. static ssize_t qdss_trace_stop_store(struct device *dev,
  2812. struct device_attribute *attr,
  2813. const char *buf, size_t count)
  2814. {
  2815. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2816. u32 option = 0;
  2817. if (sscanf(buf, "%du", &option) != 1)
  2818. return -EINVAL;
  2819. wlfw_qdss_trace_stop(plat_priv, option);
  2820. cnss_pr_dbg("Received QDSS stop command\n");
  2821. return count;
  2822. }
  2823. static ssize_t qdss_conf_download_store(struct device *dev,
  2824. struct device_attribute *attr,
  2825. const char *buf, size_t count)
  2826. {
  2827. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2828. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2829. cnss_pr_dbg("Received QDSS download config command\n");
  2830. return count;
  2831. }
  2832. static ssize_t hw_trace_override_store(struct device *dev,
  2833. struct device_attribute *attr,
  2834. const char *buf, size_t count)
  2835. {
  2836. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2837. int tmp = 0;
  2838. if (sscanf(buf, "%du", &tmp) != 1)
  2839. return -EINVAL;
  2840. plat_priv->hw_trc_override = tmp;
  2841. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2842. return count;
  2843. }
  2844. static DEVICE_ATTR_WO(fs_ready);
  2845. static DEVICE_ATTR_WO(shutdown);
  2846. static DEVICE_ATTR_WO(recovery);
  2847. static DEVICE_ATTR_WO(enable_hds);
  2848. static DEVICE_ATTR_WO(qdss_trace_start);
  2849. static DEVICE_ATTR_WO(qdss_trace_stop);
  2850. static DEVICE_ATTR_WO(qdss_conf_download);
  2851. static DEVICE_ATTR_WO(hw_trace_override);
  2852. static struct attribute *cnss_attrs[] = {
  2853. &dev_attr_fs_ready.attr,
  2854. &dev_attr_shutdown.attr,
  2855. &dev_attr_recovery.attr,
  2856. &dev_attr_enable_hds.attr,
  2857. &dev_attr_qdss_trace_start.attr,
  2858. &dev_attr_qdss_trace_stop.attr,
  2859. &dev_attr_qdss_conf_download.attr,
  2860. &dev_attr_hw_trace_override.attr,
  2861. NULL,
  2862. };
  2863. static struct attribute_group cnss_attr_group = {
  2864. .attrs = cnss_attrs,
  2865. };
  2866. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  2867. {
  2868. struct device *dev = &plat_priv->plat_dev->dev;
  2869. int ret;
  2870. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  2871. if (ret) {
  2872. cnss_pr_err("Failed to create cnss link, err = %d\n",
  2873. ret);
  2874. goto out;
  2875. }
  2876. /* This is only for backward compatibility. */
  2877. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  2878. if (ret) {
  2879. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  2880. ret);
  2881. goto rm_cnss_link;
  2882. }
  2883. return 0;
  2884. rm_cnss_link:
  2885. sysfs_remove_link(kernel_kobj, "cnss");
  2886. out:
  2887. return ret;
  2888. }
  2889. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  2890. {
  2891. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  2892. sysfs_remove_link(kernel_kobj, "cnss");
  2893. }
  2894. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  2895. {
  2896. int ret = 0;
  2897. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  2898. &cnss_attr_group);
  2899. if (ret) {
  2900. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  2901. ret);
  2902. goto out;
  2903. }
  2904. cnss_create_sysfs_link(plat_priv);
  2905. return 0;
  2906. out:
  2907. return ret;
  2908. }
  2909. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  2910. {
  2911. cnss_remove_sysfs_link(plat_priv);
  2912. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  2913. }
  2914. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  2915. {
  2916. spin_lock_init(&plat_priv->event_lock);
  2917. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  2918. WQ_UNBOUND, 1);
  2919. if (!plat_priv->event_wq) {
  2920. cnss_pr_err("Failed to create event workqueue!\n");
  2921. return -EFAULT;
  2922. }
  2923. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  2924. INIT_LIST_HEAD(&plat_priv->event_list);
  2925. return 0;
  2926. }
  2927. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  2928. {
  2929. destroy_workqueue(plat_priv->event_wq);
  2930. }
  2931. static int cnss_reboot_notifier(struct notifier_block *nb,
  2932. unsigned long action,
  2933. void *data)
  2934. {
  2935. struct cnss_plat_data *plat_priv =
  2936. container_of(nb, struct cnss_plat_data, reboot_nb);
  2937. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2938. del_timer(&plat_priv->fw_boot_timer);
  2939. complete_all(&plat_priv->power_up_complete);
  2940. complete_all(&plat_priv->cal_complete);
  2941. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  2942. return NOTIFY_DONE;
  2943. }
  2944. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  2945. {
  2946. int ret;
  2947. ret = cnss_init_sol_gpio(plat_priv);
  2948. if (ret)
  2949. return ret;
  2950. timer_setup(&plat_priv->fw_boot_timer,
  2951. cnss_bus_fw_boot_timeout_hdlr, 0);
  2952. ret = register_pm_notifier(&cnss_pm_notifier);
  2953. if (ret)
  2954. cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
  2955. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  2956. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  2957. if (ret)
  2958. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  2959. ret);
  2960. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  2961. if (ret)
  2962. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  2963. ret);
  2964. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  2965. init_completion(&plat_priv->power_up_complete);
  2966. init_completion(&plat_priv->cal_complete);
  2967. init_completion(&plat_priv->rddm_complete);
  2968. init_completion(&plat_priv->recovery_complete);
  2969. init_completion(&plat_priv->daemon_connected);
  2970. mutex_init(&plat_priv->dev_lock);
  2971. mutex_init(&plat_priv->driver_ops_lock);
  2972. plat_priv->recovery_ws =
  2973. wakeup_source_register(&plat_priv->plat_dev->dev,
  2974. "CNSS_FW_RECOVERY");
  2975. if (!plat_priv->recovery_ws)
  2976. cnss_pr_err("Failed to setup FW recovery wake source\n");
  2977. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  2978. cnss_daemon_connection_update_cb,
  2979. plat_priv);
  2980. if (ret)
  2981. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  2982. ret);
  2983. return 0;
  2984. }
  2985. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  2986. {
  2987. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  2988. plat_priv);
  2989. complete_all(&plat_priv->recovery_complete);
  2990. complete_all(&plat_priv->rddm_complete);
  2991. complete_all(&plat_priv->cal_complete);
  2992. complete_all(&plat_priv->power_up_complete);
  2993. complete_all(&plat_priv->daemon_connected);
  2994. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  2995. unregister_reboot_notifier(&plat_priv->reboot_nb);
  2996. unregister_pm_notifier(&cnss_pm_notifier);
  2997. del_timer(&plat_priv->fw_boot_timer);
  2998. wakeup_source_unregister(plat_priv->recovery_ws);
  2999. cnss_deinit_sol_gpio(plat_priv);
  3000. }
  3001. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3002. {
  3003. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3004. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3005. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3006. "qcom,wlan-cbc-enabled");
  3007. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3008. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3009. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3010. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3011. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3012. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3013. * enabled by default
  3014. */
  3015. plat_priv->adsp_pc_enabled = true;
  3016. }
  3017. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3018. {
  3019. struct device *dev = &plat_priv->plat_dev->dev;
  3020. plat_priv->use_pm_domain =
  3021. of_property_read_bool(dev->of_node, "use-pm-domain");
  3022. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3023. }
  3024. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3025. {
  3026. struct device *dev = &plat_priv->plat_dev->dev;
  3027. plat_priv->set_wlaon_pwr_ctrl =
  3028. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3029. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3030. plat_priv->set_wlaon_pwr_ctrl);
  3031. }
  3032. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3033. {
  3034. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3035. "qcom,converged-dt") ||
  3036. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3037. "qcom,same-dt-multi-dev"));
  3038. }
  3039. static const struct platform_device_id cnss_platform_id_table[] = {
  3040. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3041. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3042. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3043. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3044. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3045. { },
  3046. };
  3047. static const struct of_device_id cnss_of_match_table[] = {
  3048. {
  3049. .compatible = "qcom,cnss",
  3050. .data = (void *)&cnss_platform_id_table[0]},
  3051. {
  3052. .compatible = "qcom,cnss-qca6290",
  3053. .data = (void *)&cnss_platform_id_table[1]},
  3054. {
  3055. .compatible = "qcom,cnss-qca6390",
  3056. .data = (void *)&cnss_platform_id_table[2]},
  3057. {
  3058. .compatible = "qcom,cnss-qca6490",
  3059. .data = (void *)&cnss_platform_id_table[3]},
  3060. {
  3061. .compatible = "qcom,cnss-kiwi",
  3062. .data = (void *)&cnss_platform_id_table[4]},
  3063. { },
  3064. };
  3065. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3066. static inline bool
  3067. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3068. {
  3069. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3070. "use-nv-mac");
  3071. }
  3072. static int cnss_probe(struct platform_device *plat_dev)
  3073. {
  3074. int ret = 0;
  3075. struct cnss_plat_data *plat_priv;
  3076. const struct of_device_id *of_id;
  3077. const struct platform_device_id *device_id;
  3078. int retry = 0;
  3079. if (cnss_get_plat_priv(plat_dev)) {
  3080. cnss_pr_err("Driver is already initialized!\n");
  3081. ret = -EEXIST;
  3082. goto out;
  3083. }
  3084. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3085. if (!of_id || !of_id->data) {
  3086. cnss_pr_err("Failed to find of match device!\n");
  3087. ret = -ENODEV;
  3088. goto out;
  3089. }
  3090. device_id = of_id->data;
  3091. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3092. GFP_KERNEL);
  3093. if (!plat_priv) {
  3094. ret = -ENOMEM;
  3095. goto out;
  3096. }
  3097. plat_priv->plat_dev = plat_dev;
  3098. plat_priv->device_id = device_id->driver_data;
  3099. plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
  3100. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3101. plat_priv->use_fw_path_with_prefix =
  3102. cnss_use_fw_path_with_prefix(plat_priv);
  3103. cnss_set_plat_priv(plat_dev, plat_priv);
  3104. platform_set_drvdata(plat_dev, plat_priv);
  3105. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3106. INIT_LIST_HEAD(&plat_priv->clk_list);
  3107. cnss_get_pm_domain_info(plat_priv);
  3108. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3109. cnss_get_tcs_info(plat_priv);
  3110. cnss_get_cpr_info(plat_priv);
  3111. cnss_aop_mbox_init(plat_priv);
  3112. cnss_init_control_params(plat_priv);
  3113. ret = cnss_get_resources(plat_priv);
  3114. if (ret)
  3115. goto reset_ctx;
  3116. ret = cnss_register_esoc(plat_priv);
  3117. if (ret)
  3118. goto free_res;
  3119. ret = cnss_register_bus_scale(plat_priv);
  3120. if (ret)
  3121. goto unreg_esoc;
  3122. ret = cnss_create_sysfs(plat_priv);
  3123. if (ret)
  3124. goto unreg_bus_scale;
  3125. ret = cnss_event_work_init(plat_priv);
  3126. if (ret)
  3127. goto remove_sysfs;
  3128. ret = cnss_qmi_init(plat_priv);
  3129. if (ret)
  3130. goto deinit_event_work;
  3131. ret = cnss_dms_init(plat_priv);
  3132. if (ret)
  3133. goto deinit_qmi;
  3134. ret = cnss_debugfs_create(plat_priv);
  3135. if (ret)
  3136. goto deinit_dms;
  3137. ret = cnss_misc_init(plat_priv);
  3138. if (ret)
  3139. goto destroy_debugfs;
  3140. /* Make sure all platform related init are done before
  3141. * device power on and bus init.
  3142. */
  3143. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) {
  3144. retry:
  3145. ret = cnss_power_on_device(plat_priv);
  3146. if (ret)
  3147. goto deinit_misc;
  3148. ret = cnss_bus_init(plat_priv);
  3149. if (ret) {
  3150. if ((ret != -EPROBE_DEFER) &&
  3151. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3152. cnss_power_off_device(plat_priv);
  3153. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3154. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3155. goto retry;
  3156. }
  3157. goto power_off;
  3158. }
  3159. }
  3160. cnss_register_coex_service(plat_priv);
  3161. cnss_register_ims_service(plat_priv);
  3162. ret = cnss_genl_init();
  3163. if (ret < 0)
  3164. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3165. cnss_pr_info("Platform driver probed successfully.\n");
  3166. return 0;
  3167. power_off:
  3168. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3169. cnss_power_off_device(plat_priv);
  3170. deinit_misc:
  3171. cnss_misc_deinit(plat_priv);
  3172. destroy_debugfs:
  3173. cnss_debugfs_destroy(plat_priv);
  3174. deinit_dms:
  3175. cnss_dms_deinit(plat_priv);
  3176. deinit_qmi:
  3177. cnss_qmi_deinit(plat_priv);
  3178. deinit_event_work:
  3179. cnss_event_work_deinit(plat_priv);
  3180. remove_sysfs:
  3181. cnss_remove_sysfs(plat_priv);
  3182. unreg_bus_scale:
  3183. cnss_unregister_bus_scale(plat_priv);
  3184. unreg_esoc:
  3185. cnss_unregister_esoc(plat_priv);
  3186. free_res:
  3187. cnss_put_resources(plat_priv);
  3188. reset_ctx:
  3189. platform_set_drvdata(plat_dev, NULL);
  3190. cnss_set_plat_priv(plat_dev, NULL);
  3191. out:
  3192. return ret;
  3193. }
  3194. static int cnss_remove(struct platform_device *plat_dev)
  3195. {
  3196. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3197. cnss_genl_exit();
  3198. cnss_unregister_ims_service(plat_priv);
  3199. cnss_unregister_coex_service(plat_priv);
  3200. cnss_bus_deinit(plat_priv);
  3201. cnss_misc_deinit(plat_priv);
  3202. cnss_debugfs_destroy(plat_priv);
  3203. cnss_dms_deinit(plat_priv);
  3204. cnss_qmi_deinit(plat_priv);
  3205. cnss_event_work_deinit(plat_priv);
  3206. cnss_remove_sysfs(plat_priv);
  3207. cnss_unregister_bus_scale(plat_priv);
  3208. cnss_unregister_esoc(plat_priv);
  3209. cnss_put_resources(plat_priv);
  3210. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3211. mbox_free_channel(plat_priv->mbox_chan);
  3212. platform_set_drvdata(plat_dev, NULL);
  3213. plat_env = NULL;
  3214. return 0;
  3215. }
  3216. static struct platform_driver cnss_platform_driver = {
  3217. .probe = cnss_probe,
  3218. .remove = cnss_remove,
  3219. .driver = {
  3220. .name = "cnss2",
  3221. .of_match_table = cnss_of_match_table,
  3222. #ifdef CONFIG_CNSS_ASYNC
  3223. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3224. #endif
  3225. },
  3226. };
  3227. /**
  3228. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3229. *
  3230. * Valid device tree node means a node with "compatible" property from the
  3231. * device match table and "status" property is not disabled.
  3232. *
  3233. * Return: true if valid device tree node found, false if not found
  3234. */
  3235. static bool cnss_is_valid_dt_node_found(void)
  3236. {
  3237. struct device_node *dn = NULL;
  3238. for_each_matching_node(dn, cnss_of_match_table) {
  3239. if (of_device_is_available(dn))
  3240. break;
  3241. }
  3242. if (dn)
  3243. return true;
  3244. return false;
  3245. }
  3246. static int __init cnss_initialize(void)
  3247. {
  3248. int ret = 0;
  3249. if (!cnss_is_valid_dt_node_found())
  3250. return -ENODEV;
  3251. cnss_debug_init();
  3252. ret = platform_driver_register(&cnss_platform_driver);
  3253. if (ret)
  3254. cnss_debug_deinit();
  3255. return ret;
  3256. }
  3257. static void __exit cnss_exit(void)
  3258. {
  3259. platform_driver_unregister(&cnss_platform_driver);
  3260. cnss_debug_deinit();
  3261. }
  3262. module_init(cnss_initialize);
  3263. module_exit(cnss_exit);
  3264. MODULE_LICENSE("GPL v2");
  3265. MODULE_DESCRIPTION("CNSS2 Platform Driver");