qmi.c 109 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define CONN_ROAM_FILE_NAME "wlan-connection-roaming"
  28. #define INI_EXT ".ini"
  29. #define INI_FILE_NAME_LEN 100
  30. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  31. /*
  32. * Download QDSS config file based on build type. Add build type string to
  33. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  34. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  35. */
  36. #ifdef CONFIG_CNSS2_DEBUG
  37. #define QDSS_FILE_BUILD_STR "debug_"
  38. #else
  39. #define QDSS_FILE_BUILD_STR "perf_"
  40. #endif
  41. #define HW_V1_NUMBER "v1"
  42. #define HW_V2_NUMBER "v2"
  43. #define CE_MSI_NAME "CE"
  44. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  45. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  46. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  47. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  48. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  49. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  50. #define DMS_QMI_MAX_MSG_LEN SZ_256
  51. #define MAX_SHADOW_REG_RESERVED 2
  52. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  53. MAX_SHADOW_REG_RESERVED)
  54. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  55. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  56. enum nm_modem_bit {
  57. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  58. HOST_CSTATE_BIT = BIT(2),
  59. };
  60. #ifdef CONFIG_CNSS2_DEBUG
  61. static bool ignore_qmi_failure;
  62. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  63. void cnss_ignore_qmi_failure(bool ignore)
  64. {
  65. ignore_qmi_failure = ignore;
  66. }
  67. #else
  68. #define CNSS_QMI_ASSERT() do { } while (0)
  69. void cnss_ignore_qmi_failure(bool ignore) { }
  70. #endif
  71. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  72. {
  73. switch (mode) {
  74. case CNSS_MISSION:
  75. return "MISSION";
  76. case CNSS_FTM:
  77. return "FTM";
  78. case CNSS_EPPING:
  79. return "EPPING";
  80. case CNSS_WALTEST:
  81. return "WALTEST";
  82. case CNSS_OFF:
  83. return "OFF";
  84. case CNSS_CCPM:
  85. return "CCPM";
  86. case CNSS_QVIT:
  87. return "QVIT";
  88. case CNSS_CALIBRATION:
  89. return "CALIBRATION";
  90. default:
  91. return "UNKNOWN";
  92. }
  93. }
  94. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  95. struct qmi_elem_info *req_ei,
  96. struct qmi_elem_info *rsp_ei,
  97. int req_id, size_t req_len,
  98. unsigned long timeout)
  99. {
  100. struct qmi_txn txn;
  101. int ret;
  102. char *err_msg;
  103. struct qmi_response_type_v01 *resp = rsp;
  104. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  105. if (ret < 0) {
  106. err_msg = "Qmi fail: fail to init txn,";
  107. goto out;
  108. }
  109. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  110. req_len, req_ei, req);
  111. if (ret < 0) {
  112. qmi_txn_cancel(&txn);
  113. err_msg = "Qmi fail: fail to send req,";
  114. goto out;
  115. }
  116. ret = qmi_txn_wait(&txn, timeout);
  117. if (ret < 0) {
  118. err_msg = "Qmi fail: wait timeout,";
  119. goto out;
  120. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  121. err_msg = "Qmi fail: request rejected,";
  122. cnss_pr_err("Qmi fail: respons with error:%d\n",
  123. resp->error);
  124. ret = -resp->result;
  125. goto out;
  126. }
  127. cnss_pr_dbg("req %x success\n", req_id);
  128. return 0;
  129. out:
  130. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  131. return ret;
  132. }
  133. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  134. {
  135. struct wlfw_ind_register_req_msg_v01 *req;
  136. struct wlfw_ind_register_resp_msg_v01 *resp;
  137. struct qmi_txn txn;
  138. int ret = 0;
  139. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  140. plat_priv->driver_state);
  141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  142. if (!req)
  143. return -ENOMEM;
  144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  145. if (!resp) {
  146. kfree(req);
  147. return -ENOMEM;
  148. }
  149. req->client_id_valid = 1;
  150. req->client_id = WLFW_CLIENT_ID;
  151. req->request_mem_enable_valid = 1;
  152. req->request_mem_enable = 1;
  153. req->fw_mem_ready_enable_valid = 1;
  154. req->fw_mem_ready_enable = 1;
  155. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  156. req->fw_init_done_enable_valid = 1;
  157. req->fw_init_done_enable = 1;
  158. req->pin_connect_result_enable_valid = 1;
  159. req->pin_connect_result_enable = 1;
  160. req->cal_done_enable_valid = 1;
  161. req->cal_done_enable = 1;
  162. req->qdss_trace_req_mem_enable_valid = 1;
  163. req->qdss_trace_req_mem_enable = 1;
  164. req->qdss_trace_save_enable_valid = 1;
  165. req->qdss_trace_save_enable = 1;
  166. req->qdss_trace_free_enable_valid = 1;
  167. req->qdss_trace_free_enable = 1;
  168. req->respond_get_info_enable_valid = 1;
  169. req->respond_get_info_enable = 1;
  170. req->wfc_call_twt_config_enable_valid = 1;
  171. req->wfc_call_twt_config_enable = 1;
  172. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  173. wlfw_ind_register_resp_msg_v01_ei, resp);
  174. if (ret < 0) {
  175. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  176. ret);
  177. goto out;
  178. }
  179. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  180. QMI_WLFW_IND_REGISTER_REQ_V01,
  181. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  182. wlfw_ind_register_req_msg_v01_ei, req);
  183. if (ret < 0) {
  184. qmi_txn_cancel(&txn);
  185. cnss_pr_err("Failed to send indication register request, err: %d\n",
  186. ret);
  187. goto out;
  188. }
  189. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  190. if (ret < 0) {
  191. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  192. ret);
  193. goto out;
  194. }
  195. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  196. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  197. resp->resp.result, resp->resp.error);
  198. ret = -resp->resp.result;
  199. goto out;
  200. }
  201. if (resp->fw_status_valid) {
  202. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  203. ret = -EALREADY;
  204. goto qmi_registered;
  205. }
  206. }
  207. kfree(req);
  208. kfree(resp);
  209. return 0;
  210. out:
  211. CNSS_QMI_ASSERT();
  212. qmi_registered:
  213. kfree(req);
  214. kfree(resp);
  215. return ret;
  216. }
  217. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  218. struct wlfw_host_cap_req_msg_v01 *req)
  219. {
  220. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  221. plat_priv->device_id == MANGO_DEVICE_ID ||
  222. plat_priv->device_id == PEACH_DEVICE_ID) {
  223. req->mlo_capable_valid = 1;
  224. req->mlo_capable = 1;
  225. req->mlo_chip_id_valid = 1;
  226. req->mlo_chip_id = 0;
  227. req->mlo_group_id_valid = 1;
  228. req->mlo_group_id = 0;
  229. req->max_mlo_peer_valid = 1;
  230. /* Max peer number generally won't change for the same device
  231. * but needs to be synced with host driver.
  232. */
  233. req->max_mlo_peer = 32;
  234. req->mlo_num_chips_valid = 1;
  235. req->mlo_num_chips = 1;
  236. req->mlo_chip_info_valid = 1;
  237. req->mlo_chip_info[0].chip_id = 0;
  238. req->mlo_chip_info[0].num_local_links = 2;
  239. req->mlo_chip_info[0].hw_link_id[0] = 0;
  240. req->mlo_chip_info[0].hw_link_id[1] = 1;
  241. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  242. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  243. }
  244. }
  245. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  246. {
  247. struct wlfw_host_cap_req_msg_v01 *req;
  248. struct wlfw_host_cap_resp_msg_v01 *resp;
  249. struct qmi_txn txn;
  250. int ret = 0;
  251. u64 iova_start = 0, iova_size = 0,
  252. iova_ipa_start = 0, iova_ipa_size = 0;
  253. u64 feature_list = 0;
  254. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  255. plat_priv->driver_state);
  256. req = kzalloc(sizeof(*req), GFP_KERNEL);
  257. if (!req)
  258. return -ENOMEM;
  259. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  260. if (!resp) {
  261. kfree(req);
  262. return -ENOMEM;
  263. }
  264. req->num_clients_valid = 1;
  265. req->num_clients = 1;
  266. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  267. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  268. if (req->wake_msi) {
  269. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  270. req->wake_msi_valid = 1;
  271. }
  272. req->bdf_support_valid = 1;
  273. req->bdf_support = 1;
  274. req->m3_support_valid = 1;
  275. req->m3_support = 1;
  276. req->m3_cache_support_valid = 1;
  277. req->m3_cache_support = 1;
  278. req->cal_done_valid = 1;
  279. req->cal_done = plat_priv->cal_done;
  280. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  281. if (plat_priv->sleep_clk) {
  282. req->nm_modem_valid = 1;
  283. /* Notify firmware about the sleep clock selection,
  284. * nm_modem_bit[1] is used for this purpose.
  285. */
  286. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  287. }
  288. if (plat_priv->supported_link_speed) {
  289. req->pcie_link_info_valid = 1;
  290. req->pcie_link_info.pci_link_speed =
  291. plat_priv->supported_link_speed;
  292. cnss_pr_dbg("Supported link speed in Host Cap %d\n",
  293. plat_priv->supported_link_speed);
  294. }
  295. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  296. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  297. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  298. &iova_ipa_size)) {
  299. req->ddr_range_valid = 1;
  300. req->ddr_range[0].start = iova_start;
  301. req->ddr_range[0].size = iova_size + iova_ipa_size;
  302. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  303. req->ddr_range[0].start, req->ddr_range[0].size);
  304. }
  305. req->host_build_type_valid = 1;
  306. req->host_build_type = cnss_get_host_build_type();
  307. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  308. ret = cnss_get_feature_list(plat_priv, &feature_list);
  309. if (!ret) {
  310. req->feature_list_valid = 1;
  311. req->feature_list = feature_list;
  312. cnss_pr_dbg("Sending feature list 0x%llx\n",
  313. req->feature_list);
  314. }
  315. if (cnss_get_platform_name(plat_priv, req->platform_name,
  316. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  317. req->platform_name_valid = 1;
  318. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  319. wlfw_host_cap_resp_msg_v01_ei, resp);
  320. if (ret < 0) {
  321. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  322. ret);
  323. goto out;
  324. }
  325. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  326. QMI_WLFW_HOST_CAP_REQ_V01,
  327. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  328. wlfw_host_cap_req_msg_v01_ei, req);
  329. if (ret < 0) {
  330. qmi_txn_cancel(&txn);
  331. cnss_pr_err("Failed to send host capability request, err: %d\n",
  332. ret);
  333. goto out;
  334. }
  335. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  336. if (ret < 0) {
  337. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  338. ret);
  339. goto out;
  340. }
  341. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  342. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  343. resp->resp.result, resp->resp.error);
  344. ret = -resp->resp.result;
  345. goto out;
  346. }
  347. kfree(req);
  348. kfree(resp);
  349. return 0;
  350. out:
  351. CNSS_QMI_ASSERT();
  352. kfree(req);
  353. kfree(resp);
  354. return ret;
  355. }
  356. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  357. {
  358. struct wlfw_respond_mem_req_msg_v01 *req;
  359. struct wlfw_respond_mem_resp_msg_v01 *resp;
  360. struct qmi_txn txn;
  361. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  362. int ret = 0, i;
  363. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  364. plat_priv->driver_state);
  365. req = kzalloc(sizeof(*req), GFP_KERNEL);
  366. if (!req)
  367. return -ENOMEM;
  368. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  369. if (!resp) {
  370. kfree(req);
  371. return -ENOMEM;
  372. }
  373. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  374. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  375. ret = -EINVAL;
  376. goto out;
  377. }
  378. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  379. for (i = 0; i < req->mem_seg_len; i++) {
  380. if (!fw_mem[i].pa || !fw_mem[i].size) {
  381. if (fw_mem[i].type == 0) {
  382. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  383. i);
  384. ret = -EINVAL;
  385. goto out;
  386. }
  387. cnss_pr_err("Memory for FW is not available for type: %u\n",
  388. fw_mem[i].type);
  389. ret = -ENOMEM;
  390. goto out;
  391. }
  392. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  393. fw_mem[i].va, &fw_mem[i].pa,
  394. fw_mem[i].size, fw_mem[i].type);
  395. req->mem_seg[i].addr = fw_mem[i].pa;
  396. req->mem_seg[i].size = fw_mem[i].size;
  397. req->mem_seg[i].type = fw_mem[i].type;
  398. }
  399. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  400. wlfw_respond_mem_resp_msg_v01_ei, resp);
  401. if (ret < 0) {
  402. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  403. ret);
  404. goto out;
  405. }
  406. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  407. QMI_WLFW_RESPOND_MEM_REQ_V01,
  408. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  409. wlfw_respond_mem_req_msg_v01_ei, req);
  410. if (ret < 0) {
  411. qmi_txn_cancel(&txn);
  412. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  413. ret);
  414. goto out;
  415. }
  416. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  417. if (ret < 0) {
  418. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  419. ret);
  420. goto out;
  421. }
  422. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  423. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  424. resp->resp.result, resp->resp.error);
  425. ret = -resp->resp.result;
  426. goto out;
  427. }
  428. kfree(req);
  429. kfree(resp);
  430. return 0;
  431. out:
  432. CNSS_QMI_ASSERT();
  433. kfree(req);
  434. kfree(resp);
  435. return ret;
  436. }
  437. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  438. {
  439. struct wlfw_cap_req_msg_v01 *req;
  440. struct wlfw_cap_resp_msg_v01 *resp;
  441. struct qmi_txn txn;
  442. char *fw_build_timestamp;
  443. int ret = 0, i;
  444. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  445. plat_priv->driver_state);
  446. req = kzalloc(sizeof(*req), GFP_KERNEL);
  447. if (!req)
  448. return -ENOMEM;
  449. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  450. if (!resp) {
  451. kfree(req);
  452. return -ENOMEM;
  453. }
  454. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  455. wlfw_cap_resp_msg_v01_ei, resp);
  456. if (ret < 0) {
  457. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  458. ret);
  459. goto out;
  460. }
  461. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  462. QMI_WLFW_CAP_REQ_V01,
  463. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  464. wlfw_cap_req_msg_v01_ei, req);
  465. if (ret < 0) {
  466. qmi_txn_cancel(&txn);
  467. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  468. ret);
  469. goto out;
  470. }
  471. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  472. if (ret < 0) {
  473. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  474. ret);
  475. goto out;
  476. }
  477. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  478. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  479. resp->resp.result, resp->resp.error);
  480. ret = -resp->resp.result;
  481. goto out;
  482. }
  483. if (resp->chip_info_valid) {
  484. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  485. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  486. }
  487. if (resp->board_info_valid)
  488. plat_priv->board_info.board_id = resp->board_info.board_id;
  489. else
  490. plat_priv->board_info.board_id = 0xFF;
  491. if (resp->soc_info_valid)
  492. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  493. if (resp->fw_version_info_valid) {
  494. plat_priv->fw_version_info.fw_version =
  495. resp->fw_version_info.fw_version;
  496. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  497. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  498. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  499. resp->fw_version_info.fw_build_timestamp,
  500. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  501. }
  502. if (resp->fw_build_id_valid) {
  503. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  504. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  505. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  506. }
  507. /* FW will send aop retention volatage for qca6490 */
  508. if (resp->voltage_mv_valid) {
  509. plat_priv->cpr_info.voltage = resp->voltage_mv;
  510. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  511. plat_priv->cpr_info.voltage);
  512. cnss_update_cpr_info(plat_priv);
  513. }
  514. if (resp->time_freq_hz_valid) {
  515. plat_priv->device_freq_hz = resp->time_freq_hz;
  516. cnss_pr_dbg("Device frequency is %d HZ\n",
  517. plat_priv->device_freq_hz);
  518. }
  519. if (resp->otp_version_valid)
  520. plat_priv->otp_version = resp->otp_version;
  521. if (resp->dev_mem_info_valid) {
  522. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  523. plat_priv->dev_mem_info[i].start =
  524. resp->dev_mem_info[i].start;
  525. plat_priv->dev_mem_info[i].size =
  526. resp->dev_mem_info[i].size;
  527. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  528. i, plat_priv->dev_mem_info[i].start,
  529. plat_priv->dev_mem_info[i].size);
  530. }
  531. }
  532. if (resp->fw_caps_valid) {
  533. plat_priv->fw_pcie_gen_switch =
  534. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  535. plat_priv->fw_aux_uc_support =
  536. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  537. cnss_pr_dbg("FW aux uc support capability: %d\n",
  538. plat_priv->fw_aux_uc_support);
  539. plat_priv->fw_caps = resp->fw_caps;
  540. }
  541. if (resp->hang_data_length_valid &&
  542. resp->hang_data_length &&
  543. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  544. plat_priv->hang_event_data_len = resp->hang_data_length;
  545. else
  546. plat_priv->hang_event_data_len = 0;
  547. if (resp->hang_data_addr_offset_valid)
  548. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  549. else
  550. plat_priv->hang_data_addr_offset = 0;
  551. if (resp->hwid_bitmap_valid)
  552. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  553. if (resp->ol_cpr_cfg_valid)
  554. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  555. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  556. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  557. **/
  558. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  559. if (plat_priv->board_info.board_id ==
  560. plat_priv->on_chip_pmic_board_ids[i]) {
  561. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  562. plat_priv->board_info.board_id);
  563. ret = cnss_aop_send_msg(plat_priv,
  564. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  565. if (ret < 0)
  566. cnss_pr_dbg("Failed to Send AOP Msg");
  567. break;
  568. }
  569. }
  570. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  571. plat_priv->chip_info.chip_id,
  572. plat_priv->chip_info.chip_family,
  573. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  574. plat_priv->otp_version);
  575. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  576. plat_priv->fw_version_info.fw_version,
  577. plat_priv->fw_version_info.fw_build_timestamp,
  578. plat_priv->fw_build_id,
  579. plat_priv->hwid_bitmap);
  580. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  581. plat_priv->hang_event_data_len,
  582. plat_priv->hang_data_addr_offset);
  583. kfree(req);
  584. kfree(resp);
  585. return 0;
  586. out:
  587. CNSS_QMI_ASSERT();
  588. kfree(req);
  589. kfree(resp);
  590. return ret;
  591. }
  592. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  593. {
  594. switch (bdf_type) {
  595. case CNSS_BDF_BIN:
  596. case CNSS_BDF_ELF:
  597. return "BDF";
  598. case CNSS_BDF_REGDB:
  599. return "REGDB";
  600. case CNSS_BDF_HDS:
  601. return "HDS";
  602. default:
  603. return "UNKNOWN";
  604. }
  605. }
  606. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  607. u32 bdf_type, char *filename,
  608. u32 filename_len)
  609. {
  610. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  611. int ret = 0;
  612. switch (bdf_type) {
  613. case CNSS_BDF_ELF:
  614. /* Board ID will be equal or less than 0xFF in GF mask case */
  615. if (plat_priv->board_info.board_id == 0xFF) {
  616. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  617. snprintf(filename_tmp, filename_len,
  618. ELF_BDF_FILE_NAME_GF);
  619. else
  620. snprintf(filename_tmp, filename_len,
  621. ELF_BDF_FILE_NAME);
  622. } else if (plat_priv->board_info.board_id < 0xFF) {
  623. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  624. snprintf(filename_tmp, filename_len,
  625. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  626. plat_priv->board_info.board_id);
  627. else
  628. snprintf(filename_tmp, filename_len,
  629. ELF_BDF_FILE_NAME_PREFIX "%02x",
  630. plat_priv->board_info.board_id);
  631. } else {
  632. snprintf(filename_tmp, filename_len,
  633. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  634. plat_priv->board_info.board_id >> 8 & 0xFF,
  635. plat_priv->board_info.board_id & 0xFF);
  636. }
  637. break;
  638. case CNSS_BDF_BIN:
  639. if (plat_priv->board_info.board_id == 0xFF) {
  640. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  641. snprintf(filename_tmp, filename_len,
  642. BIN_BDF_FILE_NAME_GF);
  643. else
  644. snprintf(filename_tmp, filename_len,
  645. BIN_BDF_FILE_NAME);
  646. } else if (plat_priv->board_info.board_id < 0xFF) {
  647. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  648. snprintf(filename_tmp, filename_len,
  649. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  650. plat_priv->board_info.board_id);
  651. else
  652. snprintf(filename_tmp, filename_len,
  653. BIN_BDF_FILE_NAME_PREFIX "%02x",
  654. plat_priv->board_info.board_id);
  655. } else {
  656. snprintf(filename_tmp, filename_len,
  657. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  658. plat_priv->board_info.board_id >> 8 & 0xFF,
  659. plat_priv->board_info.board_id & 0xFF);
  660. }
  661. break;
  662. case CNSS_BDF_REGDB:
  663. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  664. break;
  665. case CNSS_BDF_HDS:
  666. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  667. break;
  668. default:
  669. cnss_pr_err("Invalid BDF type: %d\n",
  670. plat_priv->ctrl_params.bdf_type);
  671. ret = -EINVAL;
  672. break;
  673. }
  674. if (!ret)
  675. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  676. return ret;
  677. }
  678. int cnss_wlfw_ini_file_send_sync(struct cnss_plat_data *plat_priv,
  679. enum wlfw_ini_file_type_v01 file_type)
  680. {
  681. struct wlfw_ini_file_download_req_msg_v01 *req;
  682. struct wlfw_ini_file_download_resp_msg_v01 *resp;
  683. struct qmi_txn txn;
  684. int ret = 0;
  685. const struct firmware *fw;
  686. char filename[INI_FILE_NAME_LEN] = {0};
  687. char tmp_filename[INI_FILE_NAME_LEN] = {0};
  688. const u8 *temp;
  689. unsigned int remaining;
  690. bool backup_supported = false;
  691. req = kzalloc(sizeof(*req), GFP_KERNEL);
  692. if (!req)
  693. return -ENOMEM;
  694. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  695. if (!resp) {
  696. kfree(req);
  697. return -ENOMEM;
  698. }
  699. switch (file_type) {
  700. case WLFW_CONN_ROAM_INI_V01:
  701. snprintf(tmp_filename, sizeof(tmp_filename),
  702. CONN_ROAM_FILE_NAME);
  703. backup_supported = true;
  704. break;
  705. default:
  706. cnss_pr_err("Invalid file type: %u\n", file_type);
  707. ret = -EINVAL;
  708. goto err_req_fw;
  709. }
  710. snprintf(filename, sizeof(filename), "%s%s", tmp_filename, INI_EXT);
  711. /* Fetch the file */
  712. ret = firmware_request_nowarn(&fw, filename, &plat_priv->plat_dev->dev);
  713. if (ret) {
  714. if (!backup_supported)
  715. goto err_req_fw;
  716. snprintf(filename, sizeof(filename),
  717. "%s-%s%s", tmp_filename, "backup", INI_EXT);
  718. ret = firmware_request_nowarn(&fw, filename,
  719. &plat_priv->plat_dev->dev);
  720. if (ret)
  721. goto err_req_fw;
  722. }
  723. temp = fw->data;
  724. remaining = fw->size;
  725. cnss_pr_dbg("Downloading INI file: %s, size: %u\n", filename,
  726. remaining);
  727. while (remaining) {
  728. req->file_type_valid = 1;
  729. req->file_type = file_type;
  730. req->total_size_valid = 1;
  731. req->total_size = remaining;
  732. req->seg_id_valid = 1;
  733. req->data_valid = 1;
  734. req->end_valid = 1;
  735. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  736. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  737. } else {
  738. req->data_len = remaining;
  739. req->end = 1;
  740. }
  741. memcpy(req->data, temp, req->data_len);
  742. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  743. wlfw_ini_file_download_resp_msg_v01_ei,
  744. resp);
  745. if (ret < 0) {
  746. cnss_pr_err("Failed to initialize txn for INI file download request, err: %d\n",
  747. ret);
  748. goto err;
  749. }
  750. ret = qmi_send_request
  751. (&plat_priv->qmi_wlfw, NULL, &txn,
  752. QMI_WLFW_INI_FILE_DOWNLOAD_REQ_V01,
  753. WLFW_INI_FILE_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  754. wlfw_ini_file_download_req_msg_v01_ei, req);
  755. if (ret < 0) {
  756. qmi_txn_cancel(&txn);
  757. cnss_pr_err("Failed to send INI File download request, err: %d\n",
  758. ret);
  759. goto err;
  760. }
  761. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  762. if (ret < 0) {
  763. cnss_pr_err("Failed to wait for response of INI File download request, err: %d\n",
  764. ret);
  765. goto err;
  766. }
  767. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  768. cnss_pr_err("INI file download request failed, result: %d, err: %d\n",
  769. resp->resp.result, resp->resp.error);
  770. ret = -resp->resp.result;
  771. goto err;
  772. }
  773. remaining -= req->data_len;
  774. temp += req->data_len;
  775. req->seg_id++;
  776. }
  777. release_firmware(fw);
  778. kfree(req);
  779. kfree(resp);
  780. return 0;
  781. err:
  782. release_firmware(fw);
  783. err_req_fw:
  784. kfree(req);
  785. kfree(resp);
  786. return ret;
  787. }
  788. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  789. u32 bdf_type)
  790. {
  791. struct wlfw_bdf_download_req_msg_v01 *req;
  792. struct wlfw_bdf_download_resp_msg_v01 *resp;
  793. struct qmi_txn txn;
  794. char filename[MAX_FIRMWARE_NAME_LEN];
  795. const struct firmware *fw_entry = NULL;
  796. const u8 *temp;
  797. unsigned int remaining;
  798. int ret = 0;
  799. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  800. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  801. req = kzalloc(sizeof(*req), GFP_KERNEL);
  802. if (!req)
  803. return -ENOMEM;
  804. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  805. if (!resp) {
  806. kfree(req);
  807. return -ENOMEM;
  808. }
  809. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  810. filename, sizeof(filename));
  811. if (ret)
  812. goto err_req_fw;
  813. if (bdf_type == CNSS_BDF_REGDB)
  814. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  815. filename);
  816. else
  817. ret = firmware_request_nowarn(&fw_entry, filename,
  818. &plat_priv->plat_dev->dev);
  819. if (ret) {
  820. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  821. cnss_bdf_type_to_str(bdf_type), filename, ret);
  822. goto err_req_fw;
  823. }
  824. temp = fw_entry->data;
  825. remaining = fw_entry->size;
  826. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  827. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  828. while (remaining) {
  829. req->valid = 1;
  830. req->file_id_valid = 1;
  831. req->file_id = plat_priv->board_info.board_id;
  832. req->total_size_valid = 1;
  833. req->total_size = remaining;
  834. req->seg_id_valid = 1;
  835. req->data_valid = 1;
  836. req->end_valid = 1;
  837. req->bdf_type_valid = 1;
  838. req->bdf_type = bdf_type;
  839. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  840. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  841. } else {
  842. req->data_len = remaining;
  843. req->end = 1;
  844. }
  845. memcpy(req->data, temp, req->data_len);
  846. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  847. wlfw_bdf_download_resp_msg_v01_ei, resp);
  848. if (ret < 0) {
  849. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  850. cnss_bdf_type_to_str(bdf_type), ret);
  851. goto err_send;
  852. }
  853. ret = qmi_send_request
  854. (&plat_priv->qmi_wlfw, NULL, &txn,
  855. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  856. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  857. wlfw_bdf_download_req_msg_v01_ei, req);
  858. if (ret < 0) {
  859. qmi_txn_cancel(&txn);
  860. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  861. cnss_bdf_type_to_str(bdf_type), ret);
  862. goto err_send;
  863. }
  864. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  865. if (ret < 0) {
  866. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  867. cnss_bdf_type_to_str(bdf_type), ret);
  868. goto err_send;
  869. }
  870. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  871. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  872. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  873. resp->resp.error);
  874. ret = -resp->resp.result;
  875. goto err_send;
  876. }
  877. remaining -= req->data_len;
  878. temp += req->data_len;
  879. req->seg_id++;
  880. }
  881. release_firmware(fw_entry);
  882. if (resp->host_bdf_data_valid) {
  883. /* QCA6490 enable S3E regulator for IPA configuration only */
  884. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  885. cnss_enable_int_pow_amp_vreg(plat_priv);
  886. plat_priv->cbc_file_download =
  887. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  888. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  889. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  890. plat_priv->cbc_file_download);
  891. }
  892. kfree(req);
  893. kfree(resp);
  894. return 0;
  895. err_send:
  896. release_firmware(fw_entry);
  897. err_req_fw:
  898. if (!(bdf_type == CNSS_BDF_REGDB ||
  899. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  900. ret == -EAGAIN))
  901. CNSS_QMI_ASSERT();
  902. kfree(req);
  903. kfree(resp);
  904. return ret;
  905. }
  906. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  907. enum wlfw_tme_lite_file_type_v01 file)
  908. {
  909. struct wlfw_tme_lite_info_req_msg_v01 *req;
  910. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  911. struct qmi_txn txn;
  912. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  913. int ret = 0;
  914. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  915. plat_priv->driver_state);
  916. if (plat_priv->device_id != PEACH_DEVICE_ID)
  917. return 0;
  918. req = kzalloc(sizeof(*req), GFP_KERNEL);
  919. if (!req)
  920. return -ENOMEM;
  921. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  922. if (!resp) {
  923. kfree(req);
  924. return -ENOMEM;
  925. }
  926. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  927. cnss_pr_err("Memory for TME patch is not available\n");
  928. ret = -ENOMEM;
  929. goto out;
  930. }
  931. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  932. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  933. req->tme_file = file;
  934. req->addr = plat_priv->tme_lite_mem.pa;
  935. req->size = plat_priv->tme_lite_mem.size;
  936. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  937. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  938. if (ret < 0) {
  939. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  940. ret);
  941. goto out;
  942. }
  943. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  944. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  945. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  946. wlfw_tme_lite_info_req_msg_v01_ei, req);
  947. if (ret < 0) {
  948. qmi_txn_cancel(&txn);
  949. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  950. ret);
  951. goto out;
  952. }
  953. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  954. if (ret < 0) {
  955. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  956. ret);
  957. goto out;
  958. }
  959. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  960. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  961. resp->resp.result, resp->resp.error);
  962. ret = -resp->resp.result;
  963. goto out;
  964. }
  965. kfree(req);
  966. kfree(resp);
  967. return 0;
  968. out:
  969. kfree(req);
  970. kfree(resp);
  971. return ret;
  972. }
  973. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  974. {
  975. struct wlfw_m3_info_req_msg_v01 *req;
  976. struct wlfw_m3_info_resp_msg_v01 *resp;
  977. struct qmi_txn txn;
  978. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  979. int ret = 0;
  980. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  981. plat_priv->driver_state);
  982. req = kzalloc(sizeof(*req), GFP_KERNEL);
  983. if (!req)
  984. return -ENOMEM;
  985. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  986. if (!resp) {
  987. kfree(req);
  988. return -ENOMEM;
  989. }
  990. if (!m3_mem->pa || !m3_mem->size) {
  991. cnss_pr_err("Memory for M3 is not available\n");
  992. ret = -ENOMEM;
  993. goto out;
  994. }
  995. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  996. m3_mem->va, &m3_mem->pa, m3_mem->size);
  997. req->addr = plat_priv->m3_mem.pa;
  998. req->size = plat_priv->m3_mem.size;
  999. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1000. wlfw_m3_info_resp_msg_v01_ei, resp);
  1001. if (ret < 0) {
  1002. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  1003. ret);
  1004. goto out;
  1005. }
  1006. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1007. QMI_WLFW_M3_INFO_REQ_V01,
  1008. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1009. wlfw_m3_info_req_msg_v01_ei, req);
  1010. if (ret < 0) {
  1011. qmi_txn_cancel(&txn);
  1012. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  1013. ret);
  1014. goto out;
  1015. }
  1016. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1017. if (ret < 0) {
  1018. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  1019. ret);
  1020. goto out;
  1021. }
  1022. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1023. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  1024. resp->resp.result, resp->resp.error);
  1025. ret = -resp->resp.result;
  1026. goto out;
  1027. }
  1028. kfree(req);
  1029. kfree(resp);
  1030. return 0;
  1031. out:
  1032. CNSS_QMI_ASSERT();
  1033. kfree(req);
  1034. kfree(resp);
  1035. return ret;
  1036. }
  1037. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1038. {
  1039. struct wlfw_aux_uc_info_req_msg_v01 *req;
  1040. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  1041. struct qmi_txn txn;
  1042. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  1043. int ret = 0;
  1044. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  1045. plat_priv->driver_state);
  1046. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1047. if (!req)
  1048. return -ENOMEM;
  1049. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1050. if (!resp) {
  1051. kfree(req);
  1052. return -ENOMEM;
  1053. }
  1054. if (!aux_mem->pa || !aux_mem->size) {
  1055. cnss_pr_err("Memory for AUX is not available\n");
  1056. ret = -ENOMEM;
  1057. goto out;
  1058. }
  1059. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  1060. aux_mem->va, &aux_mem->pa, aux_mem->size);
  1061. req->addr = plat_priv->aux_mem.pa;
  1062. req->size = plat_priv->aux_mem.size;
  1063. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1064. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  1065. if (ret < 0) {
  1066. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1067. ret);
  1068. goto out;
  1069. }
  1070. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1071. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  1072. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1073. wlfw_aux_uc_info_req_msg_v01_ei, req);
  1074. if (ret < 0) {
  1075. qmi_txn_cancel(&txn);
  1076. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1077. ret);
  1078. goto out;
  1079. }
  1080. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1081. if (ret < 0) {
  1082. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1083. ret);
  1084. goto out;
  1085. }
  1086. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1087. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  1088. resp->resp.result, resp->resp.error);
  1089. ret = -resp->resp.result;
  1090. goto out;
  1091. }
  1092. kfree(req);
  1093. kfree(resp);
  1094. return 0;
  1095. out:
  1096. CNSS_QMI_ASSERT();
  1097. kfree(req);
  1098. kfree(resp);
  1099. return ret;
  1100. }
  1101. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  1102. u8 *mac, u32 mac_len)
  1103. {
  1104. struct wlfw_mac_addr_req_msg_v01 req;
  1105. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  1106. struct qmi_txn txn;
  1107. int ret;
  1108. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  1109. return -EINVAL;
  1110. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1111. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1112. if (ret < 0) {
  1113. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1114. ret);
  1115. ret = -EIO;
  1116. goto out;
  1117. }
  1118. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1119. mac, plat_priv->driver_state);
  1120. memcpy(req.mac_addr, mac, mac_len);
  1121. req.mac_addr_valid = 1;
  1122. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1123. QMI_WLFW_MAC_ADDR_REQ_V01,
  1124. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1125. wlfw_mac_addr_req_msg_v01_ei, &req);
  1126. if (ret < 0) {
  1127. qmi_txn_cancel(&txn);
  1128. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1129. ret = -EIO;
  1130. goto out;
  1131. }
  1132. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1133. if (ret < 0) {
  1134. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1135. ret);
  1136. ret = -EIO;
  1137. goto out;
  1138. }
  1139. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1140. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1141. resp.resp.result);
  1142. ret = -resp.resp.result;
  1143. }
  1144. out:
  1145. return ret;
  1146. }
  1147. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1148. u32 total_size)
  1149. {
  1150. int ret = 0;
  1151. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1152. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1153. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1154. unsigned int remaining;
  1155. struct qmi_txn txn;
  1156. cnss_pr_dbg("%s\n", __func__);
  1157. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1158. if (!req)
  1159. return -ENOMEM;
  1160. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1161. if (!resp) {
  1162. kfree(req);
  1163. return -ENOMEM;
  1164. }
  1165. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1166. if (!p_qdss_trace_data) {
  1167. ret = ENOMEM;
  1168. goto end;
  1169. }
  1170. remaining = total_size;
  1171. p_qdss_trace_data_temp = p_qdss_trace_data;
  1172. while (remaining && resp->end == 0) {
  1173. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1174. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1175. if (ret < 0) {
  1176. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1177. ret);
  1178. goto fail;
  1179. }
  1180. ret = qmi_send_request
  1181. (&plat_priv->qmi_wlfw, NULL, &txn,
  1182. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1183. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1184. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1185. if (ret < 0) {
  1186. qmi_txn_cancel(&txn);
  1187. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1188. ret);
  1189. goto fail;
  1190. }
  1191. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1192. if (ret < 0) {
  1193. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1194. ret);
  1195. goto fail;
  1196. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1197. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1198. resp->resp.result, resp->resp.error);
  1199. ret = -resp->resp.result;
  1200. goto fail;
  1201. } else {
  1202. ret = 0;
  1203. }
  1204. cnss_pr_dbg("%s: response total size %d data len %d",
  1205. __func__, resp->total_size, resp->data_len);
  1206. if ((resp->total_size_valid == 1 &&
  1207. resp->total_size == total_size) &&
  1208. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1209. (resp->data_valid == 1 &&
  1210. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1211. resp->data_len <= remaining) {
  1212. memcpy(p_qdss_trace_data_temp,
  1213. resp->data, resp->data_len);
  1214. } else {
  1215. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1216. __func__,
  1217. total_size, req->seg_id,
  1218. resp->total_size_valid,
  1219. resp->total_size,
  1220. resp->seg_id_valid,
  1221. resp->seg_id,
  1222. resp->data_valid,
  1223. resp->data_len);
  1224. ret = -1;
  1225. goto fail;
  1226. }
  1227. remaining -= resp->data_len;
  1228. p_qdss_trace_data_temp += resp->data_len;
  1229. req->seg_id++;
  1230. }
  1231. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1232. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1233. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1234. total_size);
  1235. if (ret < 0) {
  1236. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1237. ret);
  1238. ret = -1;
  1239. goto fail;
  1240. }
  1241. } else {
  1242. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1243. __func__,
  1244. remaining, resp->end_valid, resp->end);
  1245. ret = -1;
  1246. goto fail;
  1247. }
  1248. fail:
  1249. kfree(p_qdss_trace_data);
  1250. end:
  1251. kfree(req);
  1252. kfree(resp);
  1253. return ret;
  1254. }
  1255. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1256. char *filename, u32 filename_len,
  1257. bool fallback_file)
  1258. {
  1259. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1260. char *build_str = QDSS_FILE_BUILD_STR;
  1261. if (fallback_file)
  1262. build_str = "";
  1263. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1264. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1265. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1266. else
  1267. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1268. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1269. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1270. }
  1271. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1272. {
  1273. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1274. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1275. struct qmi_txn txn;
  1276. const struct firmware *fw_entry = NULL;
  1277. const u8 *temp;
  1278. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1279. unsigned int remaining;
  1280. int ret = 0;
  1281. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1282. plat_priv->driver_state);
  1283. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1284. if (!req)
  1285. return -ENOMEM;
  1286. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1287. if (!resp) {
  1288. kfree(req);
  1289. return -ENOMEM;
  1290. }
  1291. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1292. sizeof(qdss_cfg_filename), false);
  1293. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1294. qdss_cfg_filename);
  1295. if (ret) {
  1296. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1297. qdss_cfg_filename, ret);
  1298. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1299. sizeof(qdss_cfg_filename),
  1300. true);
  1301. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1302. qdss_cfg_filename);
  1303. if (ret) {
  1304. cnss_pr_err("Unable to load %s ret %d\n",
  1305. qdss_cfg_filename, ret);
  1306. goto err_req_fw;
  1307. }
  1308. }
  1309. temp = fw_entry->data;
  1310. remaining = fw_entry->size;
  1311. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1312. qdss_cfg_filename, remaining);
  1313. while (remaining) {
  1314. req->total_size_valid = 1;
  1315. req->total_size = remaining;
  1316. req->seg_id_valid = 1;
  1317. req->data_valid = 1;
  1318. req->end_valid = 1;
  1319. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1320. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1321. } else {
  1322. req->data_len = remaining;
  1323. req->end = 1;
  1324. }
  1325. memcpy(req->data, temp, req->data_len);
  1326. ret = qmi_txn_init
  1327. (&plat_priv->qmi_wlfw, &txn,
  1328. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1329. resp);
  1330. if (ret < 0) {
  1331. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1332. ret);
  1333. goto err_send;
  1334. }
  1335. ret = qmi_send_request
  1336. (&plat_priv->qmi_wlfw, NULL, &txn,
  1337. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1338. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1339. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1340. if (ret < 0) {
  1341. qmi_txn_cancel(&txn);
  1342. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1343. ret);
  1344. goto err_send;
  1345. }
  1346. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1347. if (ret < 0) {
  1348. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1349. ret);
  1350. goto err_send;
  1351. }
  1352. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1353. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1354. resp->resp.result, resp->resp.error);
  1355. ret = -resp->resp.result;
  1356. goto err_send;
  1357. }
  1358. remaining -= req->data_len;
  1359. temp += req->data_len;
  1360. req->seg_id++;
  1361. }
  1362. release_firmware(fw_entry);
  1363. kfree(req);
  1364. kfree(resp);
  1365. return 0;
  1366. err_send:
  1367. release_firmware(fw_entry);
  1368. err_req_fw:
  1369. kfree(req);
  1370. kfree(resp);
  1371. return ret;
  1372. }
  1373. static int wlfw_send_qdss_trace_mode_req
  1374. (struct cnss_plat_data *plat_priv,
  1375. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1376. unsigned long long option)
  1377. {
  1378. int rc = 0;
  1379. int tmp = 0;
  1380. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1381. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1382. struct qmi_txn txn;
  1383. if (!plat_priv)
  1384. return -ENODEV;
  1385. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1386. if (!req)
  1387. return -ENOMEM;
  1388. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1389. if (!resp) {
  1390. kfree(req);
  1391. return -ENOMEM;
  1392. }
  1393. req->mode_valid = 1;
  1394. req->mode = mode;
  1395. req->option_valid = 1;
  1396. req->option = option;
  1397. tmp = plat_priv->hw_trc_override;
  1398. req->hw_trc_disable_override_valid = 1;
  1399. req->hw_trc_disable_override =
  1400. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1401. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1402. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1403. __func__, mode, option, req->hw_trc_disable_override);
  1404. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1405. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1406. if (rc < 0) {
  1407. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1408. rc);
  1409. goto out;
  1410. }
  1411. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1412. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1413. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1414. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1415. if (rc < 0) {
  1416. qmi_txn_cancel(&txn);
  1417. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1418. goto out;
  1419. }
  1420. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1421. if (rc < 0) {
  1422. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1423. rc);
  1424. goto out;
  1425. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1426. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1427. resp->resp.result, resp->resp.error);
  1428. rc = -resp->resp.result;
  1429. goto out;
  1430. }
  1431. kfree(resp);
  1432. kfree(req);
  1433. return rc;
  1434. out:
  1435. kfree(resp);
  1436. kfree(req);
  1437. CNSS_QMI_ASSERT();
  1438. return rc;
  1439. }
  1440. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1441. {
  1442. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1443. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1444. }
  1445. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1446. {
  1447. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1448. option);
  1449. }
  1450. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1451. enum cnss_driver_mode mode)
  1452. {
  1453. struct wlfw_wlan_mode_req_msg_v01 *req;
  1454. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1455. struct qmi_txn txn;
  1456. int ret = 0;
  1457. if (!plat_priv)
  1458. return -ENODEV;
  1459. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1460. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1461. if (mode == CNSS_OFF &&
  1462. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1463. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1464. return 0;
  1465. }
  1466. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1467. if (!req)
  1468. return -ENOMEM;
  1469. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1470. if (!resp) {
  1471. kfree(req);
  1472. return -ENOMEM;
  1473. }
  1474. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1475. req->hw_debug_valid = 1;
  1476. req->hw_debug = 0;
  1477. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1478. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1479. if (ret < 0) {
  1480. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1481. cnss_qmi_mode_to_str(mode), mode, ret);
  1482. goto out;
  1483. }
  1484. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1485. QMI_WLFW_WLAN_MODE_REQ_V01,
  1486. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1487. wlfw_wlan_mode_req_msg_v01_ei, req);
  1488. if (ret < 0) {
  1489. qmi_txn_cancel(&txn);
  1490. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1491. cnss_qmi_mode_to_str(mode), mode, ret);
  1492. goto out;
  1493. }
  1494. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1495. if (ret < 0) {
  1496. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1497. cnss_qmi_mode_to_str(mode), mode, ret);
  1498. goto out;
  1499. }
  1500. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1501. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1502. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1503. resp->resp.error);
  1504. ret = -resp->resp.result;
  1505. goto out;
  1506. }
  1507. kfree(req);
  1508. kfree(resp);
  1509. return 0;
  1510. out:
  1511. if (mode == CNSS_OFF) {
  1512. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1513. ret = 0;
  1514. } else {
  1515. CNSS_QMI_ASSERT();
  1516. }
  1517. kfree(req);
  1518. kfree(resp);
  1519. return ret;
  1520. }
  1521. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1522. struct cnss_wlan_enable_cfg *config,
  1523. const char *host_version)
  1524. {
  1525. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1526. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1527. struct qmi_txn txn;
  1528. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1529. int ret = 0;
  1530. if (!plat_priv)
  1531. return -ENODEV;
  1532. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1533. plat_priv->driver_state);
  1534. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1535. if (!req)
  1536. return -ENOMEM;
  1537. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1538. if (!resp) {
  1539. kfree(req);
  1540. return -ENOMEM;
  1541. }
  1542. req->host_version_valid = 1;
  1543. strlcpy(req->host_version, host_version,
  1544. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1545. req->tgt_cfg_valid = 1;
  1546. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1547. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1548. else
  1549. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1550. for (i = 0; i < req->tgt_cfg_len; i++) {
  1551. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1552. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1553. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1554. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1555. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1556. }
  1557. req->svc_cfg_valid = 1;
  1558. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1559. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1560. else
  1561. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1562. for (i = 0; i < req->svc_cfg_len; i++) {
  1563. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1564. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1565. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1566. }
  1567. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1568. plat_priv->device_id != MANGO_DEVICE_ID &&
  1569. plat_priv->device_id != PEACH_DEVICE_ID) {
  1570. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1571. config->num_shadow_reg_cfg) {
  1572. req->shadow_reg_valid = 1;
  1573. if (config->num_shadow_reg_cfg >
  1574. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1575. req->shadow_reg_len =
  1576. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1577. else
  1578. req->shadow_reg_len =
  1579. config->num_shadow_reg_cfg;
  1580. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1581. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1582. req->shadow_reg_len);
  1583. } else {
  1584. req->shadow_reg_v2_valid = 1;
  1585. if (config->num_shadow_reg_v2_cfg >
  1586. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1587. req->shadow_reg_v2_len =
  1588. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1589. else
  1590. req->shadow_reg_v2_len =
  1591. config->num_shadow_reg_v2_cfg;
  1592. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1593. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1594. req->shadow_reg_v2_len);
  1595. }
  1596. } else {
  1597. req->shadow_reg_v3_valid = 1;
  1598. if (config->num_shadow_reg_v3_cfg >
  1599. MAX_NUM_SHADOW_REG_V3)
  1600. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1601. else
  1602. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1603. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1604. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1605. plat_priv->num_shadow_regs_v3);
  1606. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1607. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1608. req->shadow_reg_v3_len);
  1609. }
  1610. if (config->rri_over_ddr_cfg_valid) {
  1611. req->rri_over_ddr_cfg_valid = 1;
  1612. req->rri_over_ddr_cfg.base_addr_low =
  1613. config->rri_over_ddr_cfg.base_addr_low;
  1614. req->rri_over_ddr_cfg.base_addr_high =
  1615. config->rri_over_ddr_cfg.base_addr_high;
  1616. }
  1617. if (config->send_msi_ce) {
  1618. ret = cnss_bus_get_msi_assignment(plat_priv,
  1619. CE_MSI_NAME,
  1620. &num_vectors,
  1621. &user_base_data,
  1622. &base_vector);
  1623. if (!ret) {
  1624. req->msi_cfg_valid = 1;
  1625. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1626. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1627. ce_id++) {
  1628. req->msi_cfg[ce_id].ce_id = ce_id;
  1629. req->msi_cfg[ce_id].msi_vector =
  1630. (ce_id % num_vectors) + base_vector;
  1631. }
  1632. }
  1633. }
  1634. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1635. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1636. if (ret < 0) {
  1637. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1638. ret);
  1639. goto out;
  1640. }
  1641. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1642. QMI_WLFW_WLAN_CFG_REQ_V01,
  1643. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1644. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1645. if (ret < 0) {
  1646. qmi_txn_cancel(&txn);
  1647. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1648. ret);
  1649. goto out;
  1650. }
  1651. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1652. if (ret < 0) {
  1653. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1654. ret);
  1655. goto out;
  1656. }
  1657. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1658. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1659. resp->resp.result, resp->resp.error);
  1660. ret = -resp->resp.result;
  1661. goto out;
  1662. }
  1663. kfree(req);
  1664. kfree(resp);
  1665. return 0;
  1666. out:
  1667. CNSS_QMI_ASSERT();
  1668. kfree(req);
  1669. kfree(resp);
  1670. return ret;
  1671. }
  1672. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1673. u32 offset, u32 mem_type,
  1674. u32 data_len, u8 *data)
  1675. {
  1676. struct wlfw_athdiag_read_req_msg_v01 *req;
  1677. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1678. struct qmi_txn txn;
  1679. int ret = 0;
  1680. if (!plat_priv)
  1681. return -ENODEV;
  1682. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1683. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1684. data, data_len);
  1685. return -EINVAL;
  1686. }
  1687. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1688. plat_priv->driver_state, offset, mem_type, data_len);
  1689. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1690. if (!req)
  1691. return -ENOMEM;
  1692. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1693. if (!resp) {
  1694. kfree(req);
  1695. return -ENOMEM;
  1696. }
  1697. req->offset = offset;
  1698. req->mem_type = mem_type;
  1699. req->data_len = data_len;
  1700. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1701. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1702. if (ret < 0) {
  1703. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1704. ret);
  1705. goto out;
  1706. }
  1707. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1708. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1709. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1710. wlfw_athdiag_read_req_msg_v01_ei, req);
  1711. if (ret < 0) {
  1712. qmi_txn_cancel(&txn);
  1713. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1714. ret);
  1715. goto out;
  1716. }
  1717. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1718. if (ret < 0) {
  1719. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1720. ret);
  1721. goto out;
  1722. }
  1723. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1724. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1725. resp->resp.result, resp->resp.error);
  1726. ret = -resp->resp.result;
  1727. goto out;
  1728. }
  1729. if (!resp->data_valid || resp->data_len != data_len) {
  1730. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1731. resp->data_valid, resp->data_len);
  1732. ret = -EINVAL;
  1733. goto out;
  1734. }
  1735. memcpy(data, resp->data, resp->data_len);
  1736. kfree(req);
  1737. kfree(resp);
  1738. return 0;
  1739. out:
  1740. kfree(req);
  1741. kfree(resp);
  1742. return ret;
  1743. }
  1744. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1745. u32 offset, u32 mem_type,
  1746. u32 data_len, u8 *data)
  1747. {
  1748. struct wlfw_athdiag_write_req_msg_v01 *req;
  1749. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1750. struct qmi_txn txn;
  1751. int ret = 0;
  1752. if (!plat_priv)
  1753. return -ENODEV;
  1754. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1755. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1756. data, data_len);
  1757. return -EINVAL;
  1758. }
  1759. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1760. plat_priv->driver_state, offset, mem_type, data_len, data);
  1761. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1762. if (!req)
  1763. return -ENOMEM;
  1764. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1765. if (!resp) {
  1766. kfree(req);
  1767. return -ENOMEM;
  1768. }
  1769. req->offset = offset;
  1770. req->mem_type = mem_type;
  1771. req->data_len = data_len;
  1772. memcpy(req->data, data, data_len);
  1773. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1774. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1775. if (ret < 0) {
  1776. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1777. ret);
  1778. goto out;
  1779. }
  1780. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1781. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1782. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1783. wlfw_athdiag_write_req_msg_v01_ei, req);
  1784. if (ret < 0) {
  1785. qmi_txn_cancel(&txn);
  1786. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1787. ret);
  1788. goto out;
  1789. }
  1790. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1791. if (ret < 0) {
  1792. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1793. ret);
  1794. goto out;
  1795. }
  1796. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1797. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1798. resp->resp.result, resp->resp.error);
  1799. ret = -resp->resp.result;
  1800. goto out;
  1801. }
  1802. kfree(req);
  1803. kfree(resp);
  1804. return 0;
  1805. out:
  1806. kfree(req);
  1807. kfree(resp);
  1808. return ret;
  1809. }
  1810. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1811. u8 fw_log_mode)
  1812. {
  1813. struct wlfw_ini_req_msg_v01 *req;
  1814. struct wlfw_ini_resp_msg_v01 *resp;
  1815. struct qmi_txn txn;
  1816. int ret = 0;
  1817. if (!plat_priv)
  1818. return -ENODEV;
  1819. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1820. plat_priv->driver_state, fw_log_mode);
  1821. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1822. if (!req)
  1823. return -ENOMEM;
  1824. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1825. if (!resp) {
  1826. kfree(req);
  1827. return -ENOMEM;
  1828. }
  1829. req->enablefwlog_valid = 1;
  1830. req->enablefwlog = fw_log_mode;
  1831. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1832. wlfw_ini_resp_msg_v01_ei, resp);
  1833. if (ret < 0) {
  1834. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1835. fw_log_mode, ret);
  1836. goto out;
  1837. }
  1838. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1839. QMI_WLFW_INI_REQ_V01,
  1840. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1841. wlfw_ini_req_msg_v01_ei, req);
  1842. if (ret < 0) {
  1843. qmi_txn_cancel(&txn);
  1844. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1845. fw_log_mode, ret);
  1846. goto out;
  1847. }
  1848. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1849. if (ret < 0) {
  1850. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1851. fw_log_mode, ret);
  1852. goto out;
  1853. }
  1854. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1855. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1856. fw_log_mode, resp->resp.result, resp->resp.error);
  1857. ret = -resp->resp.result;
  1858. goto out;
  1859. }
  1860. kfree(req);
  1861. kfree(resp);
  1862. return 0;
  1863. out:
  1864. kfree(req);
  1865. kfree(resp);
  1866. return ret;
  1867. }
  1868. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1869. {
  1870. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1871. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1872. struct qmi_txn txn;
  1873. int ret = 0;
  1874. if (!plat_priv)
  1875. return -ENODEV;
  1876. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1877. !plat_priv->fw_pcie_gen_switch) {
  1878. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1879. return 0;
  1880. }
  1881. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1882. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1883. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1884. plat_priv->pcie_gen_speed;
  1885. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1886. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1887. if (ret < 0) {
  1888. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1889. ret);
  1890. goto out;
  1891. }
  1892. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1893. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1894. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1895. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1896. if (ret < 0) {
  1897. qmi_txn_cancel(&txn);
  1898. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1899. goto out;
  1900. }
  1901. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1902. if (ret < 0) {
  1903. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1904. ret);
  1905. goto out;
  1906. }
  1907. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1908. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1909. plat_priv->pcie_gen_speed, resp.resp.result,
  1910. resp.resp.error);
  1911. ret = -resp.resp.result;
  1912. }
  1913. out:
  1914. /* Reset PCIE Gen speed after one time use */
  1915. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1916. return ret;
  1917. }
  1918. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1919. {
  1920. struct wlfw_antenna_switch_req_msg_v01 *req;
  1921. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1922. struct qmi_txn txn;
  1923. int ret = 0;
  1924. if (!plat_priv)
  1925. return -ENODEV;
  1926. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1927. plat_priv->driver_state);
  1928. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1929. if (!req)
  1930. return -ENOMEM;
  1931. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1932. if (!resp) {
  1933. kfree(req);
  1934. return -ENOMEM;
  1935. }
  1936. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1937. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1938. if (ret < 0) {
  1939. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1940. ret);
  1941. goto out;
  1942. }
  1943. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1944. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1945. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1946. wlfw_antenna_switch_req_msg_v01_ei, req);
  1947. if (ret < 0) {
  1948. qmi_txn_cancel(&txn);
  1949. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1950. ret);
  1951. goto out;
  1952. }
  1953. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1954. if (ret < 0) {
  1955. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1956. ret);
  1957. goto out;
  1958. }
  1959. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1960. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1961. resp->resp.result, resp->resp.error);
  1962. ret = -resp->resp.result;
  1963. goto out;
  1964. }
  1965. if (resp->antenna_valid)
  1966. plat_priv->antenna = resp->antenna;
  1967. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1968. resp->antenna_valid, resp->antenna);
  1969. kfree(req);
  1970. kfree(resp);
  1971. return 0;
  1972. out:
  1973. kfree(req);
  1974. kfree(resp);
  1975. return ret;
  1976. }
  1977. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1978. {
  1979. struct wlfw_antenna_grant_req_msg_v01 *req;
  1980. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1981. struct qmi_txn txn;
  1982. int ret = 0;
  1983. if (!plat_priv)
  1984. return -ENODEV;
  1985. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1986. plat_priv->driver_state, plat_priv->grant);
  1987. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1988. if (!req)
  1989. return -ENOMEM;
  1990. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1991. if (!resp) {
  1992. kfree(req);
  1993. return -ENOMEM;
  1994. }
  1995. req->grant_valid = 1;
  1996. req->grant = plat_priv->grant;
  1997. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1998. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1999. if (ret < 0) {
  2000. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  2001. ret);
  2002. goto out;
  2003. }
  2004. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2005. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  2006. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  2007. wlfw_antenna_grant_req_msg_v01_ei, req);
  2008. if (ret < 0) {
  2009. qmi_txn_cancel(&txn);
  2010. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  2011. ret);
  2012. goto out;
  2013. }
  2014. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2015. if (ret < 0) {
  2016. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  2017. ret);
  2018. goto out;
  2019. }
  2020. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2021. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  2022. resp->resp.result, resp->resp.error);
  2023. ret = -resp->resp.result;
  2024. goto out;
  2025. }
  2026. kfree(req);
  2027. kfree(resp);
  2028. return 0;
  2029. out:
  2030. kfree(req);
  2031. kfree(resp);
  2032. return ret;
  2033. }
  2034. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  2035. {
  2036. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  2037. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  2038. struct qmi_txn txn;
  2039. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  2040. int ret = 0;
  2041. int i;
  2042. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  2043. plat_priv->driver_state);
  2044. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2045. if (!req)
  2046. return -ENOMEM;
  2047. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2048. if (!resp) {
  2049. kfree(req);
  2050. return -ENOMEM;
  2051. }
  2052. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2053. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  2054. ret = -EINVAL;
  2055. goto out;
  2056. }
  2057. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  2058. for (i = 0; i < req->mem_seg_len; i++) {
  2059. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  2060. qdss_mem[i].va, &qdss_mem[i].pa,
  2061. qdss_mem[i].size, qdss_mem[i].type);
  2062. req->mem_seg[i].addr = qdss_mem[i].pa;
  2063. req->mem_seg[i].size = qdss_mem[i].size;
  2064. req->mem_seg[i].type = qdss_mem[i].type;
  2065. }
  2066. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2067. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  2068. if (ret < 0) {
  2069. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  2070. ret);
  2071. goto out;
  2072. }
  2073. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2074. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  2075. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2076. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  2077. if (ret < 0) {
  2078. qmi_txn_cancel(&txn);
  2079. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  2080. ret);
  2081. goto out;
  2082. }
  2083. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2084. if (ret < 0) {
  2085. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  2086. ret);
  2087. goto out;
  2088. }
  2089. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2090. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  2091. resp->resp.result, resp->resp.error);
  2092. ret = -resp->resp.result;
  2093. goto out;
  2094. }
  2095. kfree(req);
  2096. kfree(resp);
  2097. return 0;
  2098. out:
  2099. kfree(req);
  2100. kfree(resp);
  2101. return ret;
  2102. }
  2103. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  2104. struct cnss_wfc_cfg cfg)
  2105. {
  2106. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2107. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2108. struct qmi_txn txn;
  2109. int ret = 0;
  2110. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2111. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2112. return -EINVAL;
  2113. }
  2114. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2115. if (!req)
  2116. return -ENOMEM;
  2117. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2118. if (!resp) {
  2119. kfree(req);
  2120. return -ENOMEM;
  2121. }
  2122. req->wfc_call_active_valid = 1;
  2123. req->wfc_call_active = cfg.mode;
  2124. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2125. plat_priv->driver_state);
  2126. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2127. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2128. if (ret < 0) {
  2129. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2130. ret);
  2131. goto out;
  2132. }
  2133. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2134. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2135. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2136. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2137. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2138. if (ret < 0) {
  2139. qmi_txn_cancel(&txn);
  2140. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2141. ret);
  2142. goto out;
  2143. }
  2144. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2145. if (ret < 0) {
  2146. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2147. ret);
  2148. goto out;
  2149. }
  2150. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2151. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2152. resp->resp.result, resp->resp.error);
  2153. ret = -EINVAL;
  2154. goto out;
  2155. }
  2156. ret = 0;
  2157. out:
  2158. kfree(req);
  2159. kfree(resp);
  2160. return ret;
  2161. }
  2162. static int cnss_wlfw_wfc_call_status_send_sync
  2163. (struct cnss_plat_data *plat_priv,
  2164. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2165. {
  2166. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2167. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2168. struct qmi_txn txn;
  2169. int ret = 0;
  2170. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2171. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2172. return -EINVAL;
  2173. }
  2174. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2175. if (!req)
  2176. return -ENOMEM;
  2177. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2178. if (!resp) {
  2179. kfree(req);
  2180. return -ENOMEM;
  2181. }
  2182. /**
  2183. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2184. * But in r2 update QMI structure is expanded and as an effect qmi
  2185. * decoded structures have padding. Thus we cannot use buffer design.
  2186. * For backward compatibility for r1 design copy only wfc_call_active
  2187. * value in hex buffer.
  2188. */
  2189. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2190. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2191. /* wfc_call_active is mandatory in IMS indication */
  2192. req->wfc_call_active_valid = 1;
  2193. req->wfc_call_active = ind_msg->wfc_call_active;
  2194. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2195. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2196. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2197. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2198. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2199. req->twt_ims_start = ind_msg->twt_ims_start;
  2200. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2201. req->twt_ims_int = ind_msg->twt_ims_int;
  2202. req->media_quality_valid = ind_msg->media_quality_valid;
  2203. req->media_quality =
  2204. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2205. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2206. plat_priv->driver_state);
  2207. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2208. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2209. if (ret < 0) {
  2210. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2211. ret);
  2212. goto out;
  2213. }
  2214. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2215. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2216. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2217. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2218. if (ret < 0) {
  2219. qmi_txn_cancel(&txn);
  2220. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2221. ret);
  2222. goto out;
  2223. }
  2224. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2225. if (ret < 0) {
  2226. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2227. ret);
  2228. goto out;
  2229. }
  2230. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2231. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2232. resp->resp.result, resp->resp.error);
  2233. ret = -resp->resp.result;
  2234. goto out;
  2235. }
  2236. ret = 0;
  2237. out:
  2238. kfree(req);
  2239. kfree(resp);
  2240. return ret;
  2241. }
  2242. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2243. {
  2244. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2245. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2246. struct qmi_txn txn;
  2247. int ret = 0;
  2248. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2249. plat_priv->dynamic_feature,
  2250. plat_priv->driver_state);
  2251. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2252. if (!req)
  2253. return -ENOMEM;
  2254. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2255. if (!resp) {
  2256. kfree(req);
  2257. return -ENOMEM;
  2258. }
  2259. req->mask_valid = 1;
  2260. req->mask = plat_priv->dynamic_feature;
  2261. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2262. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2263. if (ret < 0) {
  2264. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2265. ret);
  2266. goto out;
  2267. }
  2268. ret = qmi_send_request
  2269. (&plat_priv->qmi_wlfw, NULL, &txn,
  2270. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2271. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2272. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2273. if (ret < 0) {
  2274. qmi_txn_cancel(&txn);
  2275. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2276. ret);
  2277. goto out;
  2278. }
  2279. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2280. if (ret < 0) {
  2281. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2282. ret);
  2283. goto out;
  2284. }
  2285. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2286. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2287. resp->resp.result, resp->resp.error);
  2288. ret = -resp->resp.result;
  2289. goto out;
  2290. }
  2291. out:
  2292. kfree(req);
  2293. kfree(resp);
  2294. return ret;
  2295. }
  2296. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2297. void *cmd, int cmd_len)
  2298. {
  2299. struct wlfw_get_info_req_msg_v01 *req;
  2300. struct wlfw_get_info_resp_msg_v01 *resp;
  2301. struct qmi_txn txn;
  2302. int ret = 0;
  2303. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2304. type, cmd_len, plat_priv->driver_state);
  2305. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2306. return -EINVAL;
  2307. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2308. if (!req)
  2309. return -ENOMEM;
  2310. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2311. if (!resp) {
  2312. kfree(req);
  2313. return -ENOMEM;
  2314. }
  2315. req->type = type;
  2316. req->data_len = cmd_len;
  2317. memcpy(req->data, cmd, req->data_len);
  2318. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2319. wlfw_get_info_resp_msg_v01_ei, resp);
  2320. if (ret < 0) {
  2321. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2322. ret);
  2323. goto out;
  2324. }
  2325. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2326. QMI_WLFW_GET_INFO_REQ_V01,
  2327. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2328. wlfw_get_info_req_msg_v01_ei, req);
  2329. if (ret < 0) {
  2330. qmi_txn_cancel(&txn);
  2331. cnss_pr_err("Failed to send get info request, err: %d\n",
  2332. ret);
  2333. goto out;
  2334. }
  2335. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2336. if (ret < 0) {
  2337. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2338. ret);
  2339. goto out;
  2340. }
  2341. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2342. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2343. resp->resp.result, resp->resp.error);
  2344. ret = -resp->resp.result;
  2345. goto out;
  2346. }
  2347. kfree(req);
  2348. kfree(resp);
  2349. return 0;
  2350. out:
  2351. kfree(req);
  2352. kfree(resp);
  2353. return ret;
  2354. }
  2355. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2356. {
  2357. return QMI_WLFW_TIMEOUT_MS;
  2358. }
  2359. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2360. struct sockaddr_qrtr *sq,
  2361. struct qmi_txn *txn, const void *data)
  2362. {
  2363. struct cnss_plat_data *plat_priv =
  2364. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2365. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2366. int i;
  2367. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2368. if (!txn) {
  2369. cnss_pr_err("Spurious indication\n");
  2370. return;
  2371. }
  2372. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2373. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2374. return;
  2375. }
  2376. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2377. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2378. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2379. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2380. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2381. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2382. if (!plat_priv->fw_mem[i].va &&
  2383. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2384. plat_priv->fw_mem[i].attrs |=
  2385. DMA_ATTR_FORCE_CONTIGUOUS;
  2386. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2387. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2388. }
  2389. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2390. 0, NULL);
  2391. }
  2392. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2393. struct sockaddr_qrtr *sq,
  2394. struct qmi_txn *txn, const void *data)
  2395. {
  2396. struct cnss_plat_data *plat_priv =
  2397. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2398. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2399. if (!txn) {
  2400. cnss_pr_err("Spurious indication\n");
  2401. return;
  2402. }
  2403. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2404. 0, NULL);
  2405. }
  2406. /**
  2407. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2408. *
  2409. * This event is not required for HST/ HSP as FW calibration done is
  2410. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2411. */
  2412. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2413. struct sockaddr_qrtr *sq,
  2414. struct qmi_txn *txn, const void *data)
  2415. {
  2416. struct cnss_plat_data *plat_priv =
  2417. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2418. struct cnss_cal_info *cal_info;
  2419. if (!txn) {
  2420. cnss_pr_err("Spurious indication\n");
  2421. return;
  2422. }
  2423. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2424. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2425. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2426. return;
  2427. }
  2428. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2429. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2430. if (!cal_info)
  2431. return;
  2432. cal_info->cal_status = CNSS_CAL_DONE;
  2433. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2434. 0, cal_info);
  2435. }
  2436. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2437. struct sockaddr_qrtr *sq,
  2438. struct qmi_txn *txn, const void *data)
  2439. {
  2440. struct cnss_plat_data *plat_priv =
  2441. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2442. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2443. if (!txn) {
  2444. cnss_pr_err("Spurious indication\n");
  2445. return;
  2446. }
  2447. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2448. }
  2449. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2450. struct sockaddr_qrtr *sq,
  2451. struct qmi_txn *txn, const void *data)
  2452. {
  2453. struct cnss_plat_data *plat_priv =
  2454. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2455. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2456. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2457. if (!txn) {
  2458. cnss_pr_err("Spurious indication\n");
  2459. return;
  2460. }
  2461. if (ind_msg->pwr_pin_result_valid)
  2462. plat_priv->pin_result.fw_pwr_pin_result =
  2463. ind_msg->pwr_pin_result;
  2464. if (ind_msg->phy_io_pin_result_valid)
  2465. plat_priv->pin_result.fw_phy_io_pin_result =
  2466. ind_msg->phy_io_pin_result;
  2467. if (ind_msg->rf_pin_result_valid)
  2468. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2469. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2470. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2471. ind_msg->rf_pin_result);
  2472. }
  2473. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2474. u32 cal_file_download_size)
  2475. {
  2476. struct wlfw_cal_report_req_msg_v01 req = {0};
  2477. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2478. struct qmi_txn txn;
  2479. int ret = 0;
  2480. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2481. cal_file_download_size, plat_priv->driver_state);
  2482. req.cal_file_download_size_valid = 1;
  2483. req.cal_file_download_size = cal_file_download_size;
  2484. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2485. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2486. if (ret < 0) {
  2487. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2488. ret);
  2489. goto out;
  2490. }
  2491. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2492. QMI_WLFW_CAL_REPORT_REQ_V01,
  2493. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2494. wlfw_cal_report_req_msg_v01_ei, &req);
  2495. if (ret < 0) {
  2496. qmi_txn_cancel(&txn);
  2497. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2498. ret);
  2499. goto out;
  2500. }
  2501. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2502. if (ret < 0) {
  2503. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2504. ret);
  2505. goto out;
  2506. }
  2507. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2508. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2509. resp.resp.result, resp.resp.error);
  2510. ret = -resp.resp.result;
  2511. goto out;
  2512. }
  2513. out:
  2514. return ret;
  2515. }
  2516. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2517. struct sockaddr_qrtr *sq,
  2518. struct qmi_txn *txn, const void *data)
  2519. {
  2520. struct cnss_plat_data *plat_priv =
  2521. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2522. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2523. struct cnss_cal_info *cal_info;
  2524. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2525. ind->cal_file_upload_size);
  2526. cnss_pr_info("Calibration took %d ms\n",
  2527. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2528. if (!txn) {
  2529. cnss_pr_err("Spurious indication\n");
  2530. return;
  2531. }
  2532. if (ind->cal_file_upload_size_valid)
  2533. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2534. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2535. if (!cal_info)
  2536. return;
  2537. cal_info->cal_status = CNSS_CAL_DONE;
  2538. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2539. 0, cal_info);
  2540. }
  2541. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2542. struct sockaddr_qrtr *sq,
  2543. struct qmi_txn *txn,
  2544. const void *data)
  2545. {
  2546. struct cnss_plat_data *plat_priv =
  2547. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2548. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2549. int i;
  2550. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2551. if (!txn) {
  2552. cnss_pr_err("Spurious indication\n");
  2553. return;
  2554. }
  2555. if (plat_priv->qdss_mem_seg_len) {
  2556. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2557. plat_priv->qdss_mem_seg_len);
  2558. return;
  2559. }
  2560. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2561. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2562. return;
  2563. }
  2564. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2565. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2566. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2567. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2568. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2569. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2570. }
  2571. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2572. 0, NULL);
  2573. }
  2574. /**
  2575. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2576. *
  2577. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2578. * fw memory segment for dumping to file system. Only one type of mem can be
  2579. * saved per indication and is provided in mem seg index 0.
  2580. *
  2581. * Return: None
  2582. */
  2583. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2584. struct sockaddr_qrtr *sq,
  2585. struct qmi_txn *txn,
  2586. const void *data)
  2587. {
  2588. struct cnss_plat_data *plat_priv =
  2589. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2590. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2591. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2592. int i = 0;
  2593. if (!txn || !data) {
  2594. cnss_pr_err("Spurious indication\n");
  2595. return;
  2596. }
  2597. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2598. ind_msg->source, ind_msg->mem_seg_valid,
  2599. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2600. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2601. if (!event_data)
  2602. return;
  2603. event_data->mem_type = ind_msg->mem_seg[0].type;
  2604. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2605. event_data->total_size = ind_msg->total_size;
  2606. if (ind_msg->mem_seg_valid) {
  2607. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2608. cnss_pr_err("Invalid seg len indication\n");
  2609. goto free_event_data;
  2610. }
  2611. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2612. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2613. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2614. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2615. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2616. goto free_event_data;
  2617. }
  2618. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2619. i, ind_msg->mem_seg[i].addr,
  2620. ind_msg->mem_seg[i].size);
  2621. }
  2622. }
  2623. if (ind_msg->file_name_valid)
  2624. strlcpy(event_data->file_name, ind_msg->file_name,
  2625. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2626. if (ind_msg->source == 1) {
  2627. if (!ind_msg->file_name_valid)
  2628. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2629. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2630. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2631. 0, event_data);
  2632. } else {
  2633. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2634. if (!ind_msg->file_name_valid)
  2635. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2636. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2637. } else {
  2638. if (!ind_msg->file_name_valid)
  2639. strlcpy(event_data->file_name, "fw_mem_dump",
  2640. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2641. }
  2642. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2643. 0, event_data);
  2644. }
  2645. return;
  2646. free_event_data:
  2647. kfree(event_data);
  2648. }
  2649. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2650. struct sockaddr_qrtr *sq,
  2651. struct qmi_txn *txn,
  2652. const void *data)
  2653. {
  2654. struct cnss_plat_data *plat_priv =
  2655. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2656. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2657. 0, NULL);
  2658. }
  2659. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2660. struct sockaddr_qrtr *sq,
  2661. struct qmi_txn *txn,
  2662. const void *data)
  2663. {
  2664. struct cnss_plat_data *plat_priv =
  2665. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2666. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2667. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2668. if (!txn) {
  2669. cnss_pr_err("Spurious indication\n");
  2670. return;
  2671. }
  2672. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2673. ind_msg->data_len, ind_msg->type,
  2674. ind_msg->is_last, ind_msg->seq_no);
  2675. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2676. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2677. (void *)ind_msg->data,
  2678. ind_msg->data_len);
  2679. }
  2680. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2681. (struct cnss_plat_data *plat_priv,
  2682. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2683. {
  2684. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2685. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2686. struct qmi_txn txn;
  2687. int ret = 0;
  2688. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2689. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2690. return -EINVAL;
  2691. }
  2692. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2693. if (!req)
  2694. return -ENOMEM;
  2695. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2696. if (!resp) {
  2697. kfree(req);
  2698. return -ENOMEM;
  2699. }
  2700. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2701. req->twt_sta_start = ind_msg->twt_sta_start;
  2702. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2703. req->twt_sta_int = ind_msg->twt_sta_int;
  2704. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2705. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2706. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2707. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2708. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2709. req->twt_sta_dl = req->twt_sta_dl;
  2710. req->twt_sta_config_changed_valid =
  2711. ind_msg->twt_sta_config_changed_valid;
  2712. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2713. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2714. plat_priv->driver_state);
  2715. ret =
  2716. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2717. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2718. resp);
  2719. if (ret < 0) {
  2720. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2721. ret);
  2722. goto out;
  2723. }
  2724. ret =
  2725. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2726. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2727. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2728. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2729. if (ret < 0) {
  2730. qmi_txn_cancel(&txn);
  2731. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2732. goto out;
  2733. }
  2734. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2735. if (ret < 0) {
  2736. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2737. goto out;
  2738. }
  2739. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2740. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2741. resp->resp.result, resp->resp.error);
  2742. ret = -resp->resp.result;
  2743. goto out;
  2744. }
  2745. ret = 0;
  2746. out:
  2747. kfree(req);
  2748. kfree(resp);
  2749. return ret;
  2750. }
  2751. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2752. void *data)
  2753. {
  2754. int ret;
  2755. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2756. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2757. kfree(data);
  2758. return ret;
  2759. }
  2760. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2761. struct sockaddr_qrtr *sq,
  2762. struct qmi_txn *txn,
  2763. const void *data)
  2764. {
  2765. struct cnss_plat_data *plat_priv =
  2766. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2767. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2768. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2769. if (!txn) {
  2770. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2771. return;
  2772. }
  2773. if (!ind_msg) {
  2774. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2775. return;
  2776. }
  2777. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2778. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2779. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2780. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2781. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2782. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2783. ind_msg->twt_sta_config_changed_valid,
  2784. ind_msg->twt_sta_config_changed);
  2785. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2786. if (!event_data)
  2787. return;
  2788. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2789. event_data);
  2790. }
  2791. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2792. {
  2793. .type = QMI_INDICATION,
  2794. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2795. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2796. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2797. .fn = cnss_wlfw_request_mem_ind_cb
  2798. },
  2799. {
  2800. .type = QMI_INDICATION,
  2801. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2802. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2803. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2804. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2805. },
  2806. {
  2807. .type = QMI_INDICATION,
  2808. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2809. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2810. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2811. .fn = cnss_wlfw_fw_ready_ind_cb
  2812. },
  2813. {
  2814. .type = QMI_INDICATION,
  2815. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2816. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2817. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2818. .fn = cnss_wlfw_fw_init_done_ind_cb
  2819. },
  2820. {
  2821. .type = QMI_INDICATION,
  2822. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2823. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2824. .decoded_size =
  2825. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2826. .fn = cnss_wlfw_pin_result_ind_cb
  2827. },
  2828. {
  2829. .type = QMI_INDICATION,
  2830. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2831. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2832. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2833. .fn = cnss_wlfw_cal_done_ind_cb
  2834. },
  2835. {
  2836. .type = QMI_INDICATION,
  2837. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2838. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2839. .decoded_size =
  2840. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2841. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2842. },
  2843. {
  2844. .type = QMI_INDICATION,
  2845. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2846. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2847. .decoded_size =
  2848. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2849. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2850. },
  2851. {
  2852. .type = QMI_INDICATION,
  2853. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2854. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2855. .decoded_size =
  2856. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2857. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2858. },
  2859. {
  2860. .type = QMI_INDICATION,
  2861. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2862. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2863. .decoded_size =
  2864. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2865. .fn = cnss_wlfw_respond_get_info_ind_cb
  2866. },
  2867. {
  2868. .type = QMI_INDICATION,
  2869. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2870. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2871. .decoded_size =
  2872. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2873. .fn = cnss_wlfw_process_twt_cfg_ind
  2874. },
  2875. {}
  2876. };
  2877. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2878. void *data)
  2879. {
  2880. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2881. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2882. struct sockaddr_qrtr sq = { 0 };
  2883. int ret = 0;
  2884. if (!event_data)
  2885. return -EINVAL;
  2886. sq.sq_family = AF_QIPCRTR;
  2887. sq.sq_node = event_data->node;
  2888. sq.sq_port = event_data->port;
  2889. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2890. sizeof(sq), 0);
  2891. if (ret < 0) {
  2892. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2893. goto out;
  2894. }
  2895. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2896. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2897. plat_priv->driver_state);
  2898. kfree(data);
  2899. return 0;
  2900. out:
  2901. CNSS_QMI_ASSERT();
  2902. kfree(data);
  2903. return ret;
  2904. }
  2905. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2906. {
  2907. int ret = 0;
  2908. if (!plat_priv)
  2909. return -ENODEV;
  2910. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2911. cnss_pr_err("Unexpected WLFW server arrive\n");
  2912. CNSS_ASSERT(0);
  2913. return -EINVAL;
  2914. }
  2915. cnss_ignore_qmi_failure(false);
  2916. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2917. if (ret < 0)
  2918. goto out;
  2919. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2920. if (ret < 0) {
  2921. if (ret == -EALREADY)
  2922. ret = 0;
  2923. goto out;
  2924. }
  2925. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2926. if (ret < 0)
  2927. goto out;
  2928. return 0;
  2929. out:
  2930. return ret;
  2931. }
  2932. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2933. {
  2934. int ret;
  2935. if (!plat_priv)
  2936. return -ENODEV;
  2937. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2938. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2939. plat_priv->driver_state);
  2940. cnss_qmi_deinit(plat_priv);
  2941. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2942. ret = cnss_qmi_init(plat_priv);
  2943. if (ret < 0) {
  2944. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2945. CNSS_ASSERT(0);
  2946. }
  2947. return 0;
  2948. }
  2949. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2950. struct qmi_service *service)
  2951. {
  2952. struct cnss_plat_data *plat_priv =
  2953. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2954. struct cnss_qmi_event_server_arrive_data *event_data;
  2955. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2956. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2957. plat_priv->driver_state);
  2958. return 0;
  2959. }
  2960. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2961. service->node, service->port);
  2962. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2963. if (!event_data)
  2964. return -ENOMEM;
  2965. event_data->node = service->node;
  2966. event_data->port = service->port;
  2967. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2968. 0, event_data);
  2969. return 0;
  2970. }
  2971. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2972. struct qmi_service *service)
  2973. {
  2974. struct cnss_plat_data *plat_priv =
  2975. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2976. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2977. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2978. plat_priv->driver_state);
  2979. return;
  2980. }
  2981. cnss_pr_dbg("WLFW server exiting\n");
  2982. if (plat_priv) {
  2983. cnss_ignore_qmi_failure(true);
  2984. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2985. }
  2986. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2987. 0, NULL);
  2988. }
  2989. static struct qmi_ops qmi_wlfw_ops = {
  2990. .new_server = wlfw_new_server,
  2991. .del_server = wlfw_del_server,
  2992. };
  2993. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  2994. {
  2995. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  2996. /* In order to support dual wlan card attach case,
  2997. * need separate qmi service instance id for each dev
  2998. */
  2999. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  3000. plat_priv->wlfw_service_instance_id != 0)
  3001. id = plat_priv->wlfw_service_instance_id;
  3002. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  3003. WLFW_SERVICE_VERS_V01, id);
  3004. }
  3005. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  3006. {
  3007. int ret = 0;
  3008. cnss_get_qrtr_info(plat_priv);
  3009. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  3010. QMI_WLFW_MAX_RECV_BUF_SIZE,
  3011. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  3012. if (ret < 0) {
  3013. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  3014. ret);
  3015. goto out;
  3016. }
  3017. ret = cnss_qmi_add_lookup(plat_priv);
  3018. if (ret < 0)
  3019. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  3020. out:
  3021. return ret;
  3022. }
  3023. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  3024. {
  3025. qmi_handle_release(&plat_priv->qmi_wlfw);
  3026. }
  3027. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  3028. {
  3029. struct dms_get_mac_address_req_msg_v01 req;
  3030. struct dms_get_mac_address_resp_msg_v01 resp;
  3031. struct qmi_txn txn;
  3032. int ret = 0;
  3033. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  3034. cnss_pr_err("DMS QMI connection not established\n");
  3035. return -EINVAL;
  3036. }
  3037. cnss_pr_dbg("Requesting DMS MAC address");
  3038. memset(&resp, 0, sizeof(resp));
  3039. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  3040. dms_get_mac_address_resp_msg_v01_ei, &resp);
  3041. if (ret < 0) {
  3042. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  3043. ret);
  3044. goto out;
  3045. }
  3046. req.device = DMS_DEVICE_MAC_WLAN_V01;
  3047. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  3048. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  3049. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  3050. dms_get_mac_address_req_msg_v01_ei, &req);
  3051. if (ret < 0) {
  3052. qmi_txn_cancel(&txn);
  3053. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  3054. ret);
  3055. goto out;
  3056. }
  3057. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  3058. if (ret < 0) {
  3059. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  3060. ret);
  3061. goto out;
  3062. }
  3063. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  3064. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  3065. resp.resp.result, resp.resp.error);
  3066. ret = -resp.resp.result;
  3067. goto out;
  3068. }
  3069. if (!resp.mac_address_valid ||
  3070. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  3071. cnss_pr_err("Invalid MAC address received from DMS\n");
  3072. plat_priv->dms.mac_valid = false;
  3073. goto out;
  3074. }
  3075. plat_priv->dms.mac_valid = true;
  3076. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  3077. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  3078. out:
  3079. return ret;
  3080. }
  3081. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  3082. unsigned int node, unsigned int port)
  3083. {
  3084. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  3085. struct sockaddr_qrtr sq = {0};
  3086. int ret = 0;
  3087. sq.sq_family = AF_QIPCRTR;
  3088. sq.sq_node = node;
  3089. sq.sq_port = port;
  3090. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  3091. sizeof(sq), 0);
  3092. if (ret < 0) {
  3093. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  3094. node, port);
  3095. goto out;
  3096. }
  3097. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3098. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  3099. plat_priv->driver_state);
  3100. out:
  3101. return ret;
  3102. }
  3103. static int dms_new_server(struct qmi_handle *qmi_dms,
  3104. struct qmi_service *service)
  3105. {
  3106. struct cnss_plat_data *plat_priv =
  3107. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3108. if (!service)
  3109. return -EINVAL;
  3110. return cnss_dms_connect_to_server(plat_priv, service->node,
  3111. service->port);
  3112. }
  3113. static void cnss_dms_server_exit_work(struct work_struct *work)
  3114. {
  3115. int ret;
  3116. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3117. cnss_dms_deinit(plat_priv);
  3118. cnss_pr_info("QMI DMS Server Exit");
  3119. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3120. ret = cnss_dms_init(plat_priv);
  3121. if (ret < 0)
  3122. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3123. }
  3124. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3125. static void dms_del_server(struct qmi_handle *qmi_dms,
  3126. struct qmi_service *service)
  3127. {
  3128. struct cnss_plat_data *plat_priv =
  3129. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3130. if (!plat_priv)
  3131. return;
  3132. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3133. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3134. plat_priv->driver_state);
  3135. return;
  3136. }
  3137. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3138. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3139. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3140. plat_priv->driver_state);
  3141. schedule_work(&cnss_dms_del_work);
  3142. }
  3143. void cnss_cancel_dms_work(void)
  3144. {
  3145. cancel_work_sync(&cnss_dms_del_work);
  3146. }
  3147. static struct qmi_ops qmi_dms_ops = {
  3148. .new_server = dms_new_server,
  3149. .del_server = dms_del_server,
  3150. };
  3151. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3152. {
  3153. int ret = 0;
  3154. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3155. &qmi_dms_ops, NULL);
  3156. if (ret < 0) {
  3157. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3158. goto out;
  3159. }
  3160. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3161. DMS_SERVICE_VERS_V01, 0);
  3162. if (ret < 0)
  3163. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3164. out:
  3165. return ret;
  3166. }
  3167. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3168. {
  3169. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3170. qmi_handle_release(&plat_priv->qmi_dms);
  3171. }
  3172. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3173. {
  3174. int ret;
  3175. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3176. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3177. struct qmi_txn txn;
  3178. if (!plat_priv)
  3179. return -ENODEV;
  3180. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3181. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3182. if (!req)
  3183. return -ENOMEM;
  3184. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3185. if (!resp) {
  3186. kfree(req);
  3187. return -ENOMEM;
  3188. }
  3189. req->antenna = plat_priv->antenna;
  3190. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3191. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3192. if (ret < 0) {
  3193. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3194. ret);
  3195. goto out;
  3196. }
  3197. ret = qmi_send_request
  3198. (&plat_priv->coex_qmi, NULL, &txn,
  3199. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3200. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3201. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3202. if (ret < 0) {
  3203. qmi_txn_cancel(&txn);
  3204. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3205. ret);
  3206. goto out;
  3207. }
  3208. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3209. if (ret < 0) {
  3210. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3211. ret);
  3212. goto out;
  3213. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3214. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3215. resp->resp.result, resp->resp.error);
  3216. ret = -resp->resp.result;
  3217. goto out;
  3218. }
  3219. if (resp->grant_valid)
  3220. plat_priv->grant = resp->grant;
  3221. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3222. kfree(resp);
  3223. kfree(req);
  3224. return 0;
  3225. out:
  3226. kfree(resp);
  3227. kfree(req);
  3228. return ret;
  3229. }
  3230. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3231. {
  3232. int ret;
  3233. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3234. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3235. struct qmi_txn txn;
  3236. if (!plat_priv)
  3237. return -ENODEV;
  3238. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3239. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3240. if (!req)
  3241. return -ENOMEM;
  3242. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3243. if (!resp) {
  3244. kfree(req);
  3245. return -ENOMEM;
  3246. }
  3247. req->antenna = plat_priv->antenna;
  3248. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3249. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3250. if (ret < 0) {
  3251. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3252. ret);
  3253. goto out;
  3254. }
  3255. ret = qmi_send_request
  3256. (&plat_priv->coex_qmi, NULL, &txn,
  3257. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3258. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3259. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3260. if (ret < 0) {
  3261. qmi_txn_cancel(&txn);
  3262. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3263. ret);
  3264. goto out;
  3265. }
  3266. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3267. if (ret < 0) {
  3268. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3269. ret);
  3270. goto out;
  3271. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3272. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3273. resp->resp.result, resp->resp.error);
  3274. ret = -resp->resp.result;
  3275. goto out;
  3276. }
  3277. kfree(resp);
  3278. kfree(req);
  3279. return 0;
  3280. out:
  3281. kfree(resp);
  3282. kfree(req);
  3283. return ret;
  3284. }
  3285. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3286. {
  3287. int ret;
  3288. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3289. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3290. u8 pcss_enabled;
  3291. if (!plat_priv)
  3292. return -ENODEV;
  3293. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3294. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3295. return 0;
  3296. }
  3297. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3298. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3299. req.restart_level_type_valid = 1;
  3300. req.restart_level_type = pcss_enabled;
  3301. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3302. wlfw_subsys_restart_level_req_msg_v01_ei,
  3303. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3304. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3305. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3306. QMI_WLFW_TIMEOUT_JF);
  3307. if (ret < 0)
  3308. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3309. return ret;
  3310. }
  3311. static int coex_new_server(struct qmi_handle *qmi,
  3312. struct qmi_service *service)
  3313. {
  3314. struct cnss_plat_data *plat_priv =
  3315. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3316. struct sockaddr_qrtr sq = { 0 };
  3317. int ret = 0;
  3318. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3319. service->node, service->port);
  3320. sq.sq_family = AF_QIPCRTR;
  3321. sq.sq_node = service->node;
  3322. sq.sq_port = service->port;
  3323. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3324. if (ret < 0) {
  3325. cnss_pr_err("Fail to connect to remote service port\n");
  3326. return ret;
  3327. }
  3328. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3329. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3330. plat_priv->driver_state);
  3331. return 0;
  3332. }
  3333. static void coex_del_server(struct qmi_handle *qmi,
  3334. struct qmi_service *service)
  3335. {
  3336. struct cnss_plat_data *plat_priv =
  3337. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3338. cnss_pr_dbg("COEX server exit\n");
  3339. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3340. }
  3341. static struct qmi_ops coex_qmi_ops = {
  3342. .new_server = coex_new_server,
  3343. .del_server = coex_del_server,
  3344. };
  3345. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3346. { int ret;
  3347. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3348. COEX_SERVICE_MAX_MSG_LEN,
  3349. &coex_qmi_ops, NULL);
  3350. if (ret < 0)
  3351. return ret;
  3352. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3353. COEX_SERVICE_VERS_V01, 0);
  3354. return ret;
  3355. }
  3356. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3357. {
  3358. qmi_handle_release(&plat_priv->coex_qmi);
  3359. }
  3360. /* IMS Service */
  3361. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3362. {
  3363. int ret;
  3364. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3365. struct qmi_txn *txn;
  3366. if (!plat_priv)
  3367. return -ENODEV;
  3368. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3369. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3370. if (!req)
  3371. return -ENOMEM;
  3372. req->wfc_call_status_valid = 1;
  3373. req->wfc_call_status = 1;
  3374. txn = &plat_priv->txn;
  3375. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3376. if (ret < 0) {
  3377. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3378. ret);
  3379. goto out;
  3380. }
  3381. ret = qmi_send_request
  3382. (&plat_priv->ims_qmi, NULL, txn,
  3383. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3384. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3385. ims_private_service_subscribe_for_indications_req_msg_v01_ei, req);
  3386. if (ret < 0) {
  3387. qmi_txn_cancel(txn);
  3388. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3389. ret);
  3390. goto out;
  3391. }
  3392. kfree(req);
  3393. return 0;
  3394. out:
  3395. kfree(req);
  3396. return ret;
  3397. }
  3398. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3399. struct sockaddr_qrtr *sq,
  3400. struct qmi_txn *txn,
  3401. const void *data)
  3402. {
  3403. const
  3404. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3405. data;
  3406. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3407. if (!txn) {
  3408. cnss_pr_err("spurious response\n");
  3409. return;
  3410. }
  3411. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3412. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3413. resp->resp.result, resp->resp.error);
  3414. txn->result = -resp->resp.result;
  3415. }
  3416. }
  3417. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3418. void *data)
  3419. {
  3420. int ret;
  3421. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3422. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3423. kfree(data);
  3424. return ret;
  3425. }
  3426. static void
  3427. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3428. struct sockaddr_qrtr *sq,
  3429. struct qmi_txn *txn, const void *data)
  3430. {
  3431. struct cnss_plat_data *plat_priv =
  3432. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3433. const
  3434. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3435. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3436. if (!txn) {
  3437. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3438. return;
  3439. }
  3440. if (!ind_msg) {
  3441. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3442. return;
  3443. }
  3444. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3445. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3446. ind_msg->all_wfc_calls_held,
  3447. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3448. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3449. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3450. ind_msg->media_quality_valid, ind_msg->media_quality);
  3451. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3452. if (!event_data)
  3453. return;
  3454. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3455. 0, event_data);
  3456. }
  3457. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3458. {
  3459. .type = QMI_RESPONSE,
  3460. .msg_id =
  3461. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3462. .ei =
  3463. ims_private_service_subscribe_for_indications_rsp_msg_v01_ei,
  3464. .decoded_size = sizeof(struct
  3465. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3466. .fn = ims_subscribe_for_indication_resp_cb
  3467. },
  3468. {
  3469. .type = QMI_INDICATION,
  3470. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3471. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3472. .decoded_size =
  3473. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3474. .fn = cnss_ims_process_wfc_call_ind_cb
  3475. },
  3476. {}
  3477. };
  3478. static int ims_new_server(struct qmi_handle *qmi,
  3479. struct qmi_service *service)
  3480. {
  3481. struct cnss_plat_data *plat_priv =
  3482. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3483. struct sockaddr_qrtr sq = { 0 };
  3484. int ret = 0;
  3485. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3486. service->node, service->port);
  3487. sq.sq_family = AF_QIPCRTR;
  3488. sq.sq_node = service->node;
  3489. sq.sq_port = service->port;
  3490. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3491. if (ret < 0) {
  3492. cnss_pr_err("Fail to connect to remote service port\n");
  3493. return ret;
  3494. }
  3495. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3496. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3497. plat_priv->driver_state);
  3498. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3499. return ret;
  3500. }
  3501. static void ims_del_server(struct qmi_handle *qmi,
  3502. struct qmi_service *service)
  3503. {
  3504. struct cnss_plat_data *plat_priv =
  3505. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3506. cnss_pr_dbg("IMS server exit\n");
  3507. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3508. }
  3509. static struct qmi_ops ims_qmi_ops = {
  3510. .new_server = ims_new_server,
  3511. .del_server = ims_del_server,
  3512. };
  3513. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3514. { int ret;
  3515. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3516. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3517. &ims_qmi_ops, qmi_ims_msg_handlers);
  3518. if (ret < 0)
  3519. return ret;
  3520. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3521. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3522. return ret;
  3523. }
  3524. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3525. {
  3526. qmi_handle_release(&plat_priv->ims_qmi);
  3527. }