hif.h 46 KB

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  1. /*
  2. * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HIF_H_
  19. #define _HIF_H_
  20. #ifdef __cplusplus
  21. extern "C" {
  22. #endif /* __cplusplus */
  23. /* Header files */
  24. #include <qdf_status.h>
  25. #include "qdf_nbuf.h"
  26. #include "qdf_lro.h"
  27. #include "ol_if_athvar.h"
  28. #include <linux/platform_device.h>
  29. #ifdef HIF_PCI
  30. #include <linux/pci.h>
  31. #endif /* HIF_PCI */
  32. #ifdef HIF_USB
  33. #include <linux/usb.h>
  34. #endif /* HIF_USB */
  35. #ifdef IPA_OFFLOAD
  36. #include <linux/ipa.h>
  37. #endif
  38. #include "cfg_ucfg_api.h"
  39. #include "qdf_dev.h"
  40. #define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
  41. typedef void __iomem *A_target_id_t;
  42. typedef void *hif_handle_t;
  43. #define HIF_TYPE_AR6002 2
  44. #define HIF_TYPE_AR6003 3
  45. #define HIF_TYPE_AR6004 5
  46. #define HIF_TYPE_AR9888 6
  47. #define HIF_TYPE_AR6320 7
  48. #define HIF_TYPE_AR6320V2 8
  49. /* For attaching Peregrine 2.0 board host_reg_tbl only */
  50. #define HIF_TYPE_AR9888V2 9
  51. #define HIF_TYPE_ADRASTEA 10
  52. #define HIF_TYPE_AR900B 11
  53. #define HIF_TYPE_QCA9984 12
  54. #define HIF_TYPE_IPQ4019 13
  55. #define HIF_TYPE_QCA9888 14
  56. #define HIF_TYPE_QCA8074 15
  57. #define HIF_TYPE_QCA6290 16
  58. #define HIF_TYPE_QCN7605 17
  59. #define HIF_TYPE_QCA6390 18
  60. #define HIF_TYPE_QCA8074V2 19
  61. #define HIF_TYPE_QCA6018 20
  62. #define HIF_TYPE_QCN9000 21
  63. #define HIF_TYPE_QCA6490 22
  64. #define HIF_TYPE_QCA6750 23
  65. #define HIF_TYPE_QCA5018 24
  66. #define DMA_COHERENT_MASK_DEFAULT 37
  67. #ifdef IPA_OFFLOAD
  68. #define DMA_COHERENT_MASK_BELOW_IPA_VER_3 32
  69. #endif
  70. /* enum hif_ic_irq - enum defining integrated chip irq numbers
  71. * defining irq nubers that can be used by external modules like datapath
  72. */
  73. enum hif_ic_irq {
  74. host2wbm_desc_feed = 16,
  75. host2reo_re_injection,
  76. host2reo_command,
  77. host2rxdma_monitor_ring3,
  78. host2rxdma_monitor_ring2,
  79. host2rxdma_monitor_ring1,
  80. reo2host_exception,
  81. wbm2host_rx_release,
  82. reo2host_status,
  83. reo2host_destination_ring4,
  84. reo2host_destination_ring3,
  85. reo2host_destination_ring2,
  86. reo2host_destination_ring1,
  87. rxdma2host_monitor_destination_mac3,
  88. rxdma2host_monitor_destination_mac2,
  89. rxdma2host_monitor_destination_mac1,
  90. ppdu_end_interrupts_mac3,
  91. ppdu_end_interrupts_mac2,
  92. ppdu_end_interrupts_mac1,
  93. rxdma2host_monitor_status_ring_mac3,
  94. rxdma2host_monitor_status_ring_mac2,
  95. rxdma2host_monitor_status_ring_mac1,
  96. host2rxdma_host_buf_ring_mac3,
  97. host2rxdma_host_buf_ring_mac2,
  98. host2rxdma_host_buf_ring_mac1,
  99. rxdma2host_destination_ring_mac3,
  100. rxdma2host_destination_ring_mac2,
  101. rxdma2host_destination_ring_mac1,
  102. host2tcl_input_ring4,
  103. host2tcl_input_ring3,
  104. host2tcl_input_ring2,
  105. host2tcl_input_ring1,
  106. wbm2host_tx_completions_ring3,
  107. wbm2host_tx_completions_ring2,
  108. wbm2host_tx_completions_ring1,
  109. tcl2host_status_ring,
  110. };
  111. struct CE_state;
  112. #define CE_COUNT_MAX 12
  113. #define HIF_MAX_GRP_IRQ 16
  114. #ifndef HIF_MAX_GROUP
  115. #define HIF_MAX_GROUP 7
  116. #endif
  117. #ifndef NAPI_YIELD_BUDGET_BASED
  118. #ifndef QCA_NAPI_DEF_SCALE_BIN_SHIFT
  119. #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 4
  120. #endif
  121. #else /* NAPI_YIELD_BUDGET_BASED */
  122. #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 2
  123. #endif /* NAPI_YIELD_BUDGET_BASED */
  124. #define QCA_NAPI_BUDGET 64
  125. #define QCA_NAPI_DEF_SCALE \
  126. (1 << QCA_NAPI_DEF_SCALE_BIN_SHIFT)
  127. #define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
  128. /* NOTE: "napi->scale" can be changed,
  129. * but this does not change the number of buckets
  130. */
  131. #define QCA_NAPI_NUM_BUCKETS 4
  132. /**
  133. * qca_napi_stat - stats structure for execution contexts
  134. * @napi_schedules - number of times the schedule function is called
  135. * @napi_polls - number of times the execution context runs
  136. * @napi_completes - number of times that the generating interrupt is reenabled
  137. * @napi_workdone - cumulative of all work done reported by handler
  138. * @cpu_corrected - incremented when execution context runs on a different core
  139. * than the one that its irq is affined to.
  140. * @napi_budget_uses - histogram of work done per execution run
  141. * @time_limit_reache - count of yields due to time limit threshholds
  142. * @rxpkt_thresh_reached - count of yields due to a work limit
  143. * @poll_time_buckets - histogram of poll times for the napi
  144. *
  145. */
  146. struct qca_napi_stat {
  147. uint32_t napi_schedules;
  148. uint32_t napi_polls;
  149. uint32_t napi_completes;
  150. uint32_t napi_workdone;
  151. uint32_t cpu_corrected;
  152. uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS];
  153. uint32_t time_limit_reached;
  154. uint32_t rxpkt_thresh_reached;
  155. unsigned long long napi_max_poll_time;
  156. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  157. uint32_t poll_time_buckets[QCA_NAPI_NUM_BUCKETS];
  158. #endif
  159. };
  160. /**
  161. * per NAPI instance data structure
  162. * This data structure holds stuff per NAPI instance.
  163. * Note that, in the current implementation, though scale is
  164. * an instance variable, it is set to the same value for all
  165. * instances.
  166. */
  167. struct qca_napi_info {
  168. struct net_device netdev; /* dummy net_dev */
  169. void *hif_ctx;
  170. struct napi_struct napi;
  171. uint8_t scale; /* currently same on all instances */
  172. uint8_t id;
  173. uint8_t cpu;
  174. int irq;
  175. cpumask_t cpumask;
  176. struct qca_napi_stat stats[NR_CPUS];
  177. #ifdef RECEIVE_OFFLOAD
  178. /* will only be present for data rx CE's */
  179. void (*offld_flush_cb)(void *);
  180. struct napi_struct rx_thread_napi;
  181. struct net_device rx_thread_netdev;
  182. #endif /* RECEIVE_OFFLOAD */
  183. qdf_lro_ctx_t lro_ctx;
  184. };
  185. enum qca_napi_tput_state {
  186. QCA_NAPI_TPUT_UNINITIALIZED,
  187. QCA_NAPI_TPUT_LO,
  188. QCA_NAPI_TPUT_HI
  189. };
  190. enum qca_napi_cpu_state {
  191. QCA_NAPI_CPU_UNINITIALIZED,
  192. QCA_NAPI_CPU_DOWN,
  193. QCA_NAPI_CPU_UP };
  194. /**
  195. * struct qca_napi_cpu - an entry of the napi cpu table
  196. * @core_id: physical core id of the core
  197. * @cluster_id: cluster this core belongs to
  198. * @core_mask: mask to match all core of this cluster
  199. * @thread_mask: mask for this core within the cluster
  200. * @max_freq: maximum clock this core can be clocked at
  201. * same for all cpus of the same core.
  202. * @napis: bitmap of napi instances on this core
  203. * @execs: bitmap of execution contexts on this core
  204. * cluster_nxt: chain to link cores within the same cluster
  205. *
  206. * This structure represents a single entry in the napi cpu
  207. * table. The table is part of struct qca_napi_data.
  208. * This table is initialized by the init function, called while
  209. * the first napi instance is being created, updated by hotplug
  210. * notifier and when cpu affinity decisions are made (by throughput
  211. * detection), and deleted when the last napi instance is removed.
  212. */
  213. struct qca_napi_cpu {
  214. enum qca_napi_cpu_state state;
  215. int core_id;
  216. int cluster_id;
  217. cpumask_t core_mask;
  218. cpumask_t thread_mask;
  219. unsigned int max_freq;
  220. uint32_t napis;
  221. uint32_t execs;
  222. int cluster_nxt; /* index, not pointer */
  223. };
  224. /**
  225. * struct qca_napi_data - collection of napi data for a single hif context
  226. * @hif_softc: pointer to the hif context
  227. * @lock: spinlock used in the event state machine
  228. * @state: state variable used in the napi stat machine
  229. * @ce_map: bit map indicating which ce's have napis running
  230. * @exec_map: bit map of instanciated exec contexts
  231. * @user_cpu_affin_map: CPU affinity map from INI config.
  232. * @napi_cpu: cpu info for irq affinty
  233. * @lilcl_head:
  234. * @bigcl_head:
  235. * @napi_mode: irq affinity & clock voting mode
  236. * @cpuhp_handler: CPU hotplug event registration handle
  237. */
  238. struct qca_napi_data {
  239. struct hif_softc *hif_softc;
  240. qdf_spinlock_t lock;
  241. uint32_t state;
  242. /* bitmap of created/registered NAPI instances, indexed by pipe_id,
  243. * not used by clients (clients use an id returned by create)
  244. */
  245. uint32_t ce_map;
  246. uint32_t exec_map;
  247. uint32_t user_cpu_affin_mask;
  248. struct qca_napi_info *napis[CE_COUNT_MAX];
  249. struct qca_napi_cpu napi_cpu[NR_CPUS];
  250. int lilcl_head, bigcl_head;
  251. enum qca_napi_tput_state napi_mode;
  252. struct qdf_cpuhp_handler *cpuhp_handler;
  253. uint8_t flags;
  254. };
  255. /**
  256. * struct hif_config_info - Place Holder for HIF configuration
  257. * @enable_self_recovery: Self Recovery
  258. * @enable_runtime_pm: Enable Runtime PM
  259. * @runtime_pm_delay: Runtime PM Delay
  260. * @rx_softirq_max_yield_duration_ns: Max Yield time duration for RX Softirq
  261. *
  262. * Structure for holding HIF ini parameters.
  263. */
  264. struct hif_config_info {
  265. bool enable_self_recovery;
  266. #ifdef FEATURE_RUNTIME_PM
  267. uint8_t enable_runtime_pm;
  268. u_int32_t runtime_pm_delay;
  269. #endif
  270. uint64_t rx_softirq_max_yield_duration_ns;
  271. };
  272. /**
  273. * struct hif_target_info - Target Information
  274. * @target_version: Target Version
  275. * @target_type: Target Type
  276. * @target_revision: Target Revision
  277. * @soc_version: SOC Version
  278. * @hw_name: pointer to hardware name
  279. *
  280. * Structure to hold target information.
  281. */
  282. struct hif_target_info {
  283. uint32_t target_version;
  284. uint32_t target_type;
  285. uint32_t target_revision;
  286. uint32_t soc_version;
  287. char *hw_name;
  288. };
  289. struct hif_opaque_softc {
  290. };
  291. /**
  292. * enum hif_event_type - Type of DP events to be recorded
  293. * @HIF_EVENT_IRQ_TRIGGER: IRQ trigger event
  294. * @HIF_EVENT_BH_SCHED: NAPI POLL scheduled event
  295. * @HIF_EVENT_SRNG_ACCESS_START: hal ring access start event
  296. * @HIF_EVENT_SRNG_ACCESS_END: hal ring access end event
  297. */
  298. enum hif_event_type {
  299. HIF_EVENT_IRQ_TRIGGER,
  300. HIF_EVENT_BH_SCHED,
  301. HIF_EVENT_SRNG_ACCESS_START,
  302. HIF_EVENT_SRNG_ACCESS_END,
  303. };
  304. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  305. /* HIF_EVENT_HIST_MAX should always be power of 2 */
  306. #define HIF_EVENT_HIST_MAX 512
  307. #define HIF_NUM_INT_CONTEXTS HIF_MAX_GROUP
  308. #define HIF_EVENT_HIST_DISABLE_MASK 0
  309. /**
  310. * struct hif_event_record - an entry of the DP event history
  311. * @hal_ring_id: ring id for which event is recorded
  312. * @hp: head pointer of the ring (may not be applicable for all events)
  313. * @tp: tail pointer of the ring (may not be applicable for all events)
  314. * @cpu_id: cpu id on which the event occurred
  315. * @timestamp: timestamp when event occurred
  316. * @type: type of the event
  317. *
  318. * This structure represents the information stored for every datapath
  319. * event which is logged in the history.
  320. */
  321. struct hif_event_record {
  322. uint8_t hal_ring_id;
  323. uint32_t hp;
  324. uint32_t tp;
  325. int cpu_id;
  326. uint64_t timestamp;
  327. enum hif_event_type type;
  328. };
  329. /**
  330. * struct hif_event_history - history for one interrupt group
  331. * @index: index to store new event
  332. * @event: event entry
  333. *
  334. * This structure represents the datapath history for one
  335. * interrupt group.
  336. */
  337. struct hif_event_history {
  338. qdf_atomic_t index;
  339. struct hif_event_record event[HIF_EVENT_HIST_MAX];
  340. };
  341. /**
  342. * hif_hist_record_event() - Record one datapath event in history
  343. * @hif_ctx: HIF opaque context
  344. * @event: DP event entry
  345. * @intr_grp_id: interrupt group ID registered with hif
  346. *
  347. * Return: None
  348. */
  349. void hif_hist_record_event(struct hif_opaque_softc *hif_ctx,
  350. struct hif_event_record *event,
  351. uint8_t intr_grp_id);
  352. /**
  353. * hif_record_event() - Wrapper function to form and record DP event
  354. * @hif_ctx: HIF opaque context
  355. * @intr_grp_id: interrupt group ID registered with hif
  356. * @hal_ring_id: ring id for which event is recorded
  357. * @hp: head pointer index of the srng
  358. * @tp: tail pointer index of the srng
  359. * @type: type of the event to be logged in history
  360. *
  361. * Return: None
  362. */
  363. static inline void hif_record_event(struct hif_opaque_softc *hif_ctx,
  364. uint8_t intr_grp_id,
  365. uint8_t hal_ring_id,
  366. uint32_t hp,
  367. uint32_t tp,
  368. enum hif_event_type type)
  369. {
  370. struct hif_event_record event;
  371. event.hal_ring_id = hal_ring_id;
  372. event.hp = hp;
  373. event.tp = tp;
  374. event.type = type;
  375. return hif_hist_record_event(hif_ctx, &event,
  376. intr_grp_id);
  377. }
  378. #else
  379. static inline void hif_record_event(struct hif_opaque_softc *hif_ctx,
  380. uint8_t intr_grp_id,
  381. uint8_t hal_ring_id,
  382. uint32_t hp,
  383. uint32_t tp,
  384. enum hif_event_type type)
  385. {
  386. }
  387. #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */
  388. /**
  389. * enum HIF_DEVICE_POWER_CHANGE_TYPE: Device Power change type
  390. *
  391. * @HIF_DEVICE_POWER_UP: HIF layer should power up interface and/or module
  392. * @HIF_DEVICE_POWER_DOWN: HIF layer should initiate bus-specific measures to
  393. * minimize power
  394. * @HIF_DEVICE_POWER_CUT: HIF layer should initiate bus-specific AND/OR
  395. * platform-specific measures to completely power-off
  396. * the module and associated hardware (i.e. cut power
  397. * supplies)
  398. */
  399. enum HIF_DEVICE_POWER_CHANGE_TYPE {
  400. HIF_DEVICE_POWER_UP,
  401. HIF_DEVICE_POWER_DOWN,
  402. HIF_DEVICE_POWER_CUT
  403. };
  404. /**
  405. * enum hif_enable_type: what triggered the enabling of hif
  406. *
  407. * @HIF_ENABLE_TYPE_PROBE: probe triggered enable
  408. * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable
  409. */
  410. enum hif_enable_type {
  411. HIF_ENABLE_TYPE_PROBE,
  412. HIF_ENABLE_TYPE_REINIT,
  413. HIF_ENABLE_TYPE_MAX
  414. };
  415. /**
  416. * enum hif_disable_type: what triggered the disabling of hif
  417. *
  418. * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
  419. * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered disable
  420. * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
  421. * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
  422. */
  423. enum hif_disable_type {
  424. HIF_DISABLE_TYPE_PROBE_ERROR,
  425. HIF_DISABLE_TYPE_REINIT_ERROR,
  426. HIF_DISABLE_TYPE_REMOVE,
  427. HIF_DISABLE_TYPE_SHUTDOWN,
  428. HIF_DISABLE_TYPE_MAX
  429. };
  430. /**
  431. * enum hif_device_config_opcode: configure mode
  432. *
  433. * @HIF_DEVICE_POWER_STATE: device power state
  434. * @HIF_DEVICE_GET_BLOCK_SIZE: get block size
  435. * @HIF_DEVICE_GET_ADDR: get block address
  436. * @HIF_DEVICE_GET_PENDING_EVENTS_FUNC: get pending events functions
  437. * @HIF_DEVICE_GET_IRQ_PROC_MODE: get irq proc mode
  438. * @HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC: receive event function
  439. * @HIF_DEVICE_POWER_STATE_CHANGE: change power state
  440. * @HIF_DEVICE_GET_IRQ_YIELD_PARAMS: get yield params
  441. * @HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: configure scatter request
  442. * @HIF_DEVICE_GET_OS_DEVICE: get OS device
  443. * @HIF_DEVICE_DEBUG_BUS_STATE: debug bus state
  444. * @HIF_BMI_DONE: bmi done
  445. * @HIF_DEVICE_SET_TARGET_TYPE: set target type
  446. * @HIF_DEVICE_SET_HTC_CONTEXT: set htc context
  447. * @HIF_DEVICE_GET_HTC_CONTEXT: get htc context
  448. */
  449. enum hif_device_config_opcode {
  450. HIF_DEVICE_POWER_STATE = 0,
  451. HIF_DEVICE_GET_BLOCK_SIZE,
  452. HIF_DEVICE_GET_FIFO_ADDR,
  453. HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
  454. HIF_DEVICE_GET_IRQ_PROC_MODE,
  455. HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
  456. HIF_DEVICE_POWER_STATE_CHANGE,
  457. HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
  458. HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
  459. HIF_DEVICE_GET_OS_DEVICE,
  460. HIF_DEVICE_DEBUG_BUS_STATE,
  461. HIF_BMI_DONE,
  462. HIF_DEVICE_SET_TARGET_TYPE,
  463. HIF_DEVICE_SET_HTC_CONTEXT,
  464. HIF_DEVICE_GET_HTC_CONTEXT,
  465. };
  466. #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
  467. struct HID_ACCESS_LOG {
  468. uint32_t seqnum;
  469. bool is_write;
  470. void *addr;
  471. uint32_t value;
  472. };
  473. #endif
  474. void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset,
  475. uint32_t value);
  476. uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset);
  477. #define HIF_MAX_DEVICES 1
  478. /**
  479. * struct htc_callbacks - Structure for HTC Callbacks methods
  480. * @context: context to pass to the dsrhandler
  481. * note : rwCompletionHandler is provided the context
  482. * passed to hif_read_write
  483. * @rwCompletionHandler: Read / write completion handler
  484. * @dsrHandler: DSR Handler
  485. */
  486. struct htc_callbacks {
  487. void *context;
  488. QDF_STATUS(*rw_compl_handler)(void *rw_ctx, QDF_STATUS status);
  489. QDF_STATUS(*dsr_handler)(void *context);
  490. };
  491. /**
  492. * struct hif_driver_state_callbacks - Callbacks for HIF to query Driver state
  493. * @context: Private data context
  494. * @set_recovery_in_progress: To Set Driver state for recovery in progress
  495. * @is_recovery_in_progress: Query if driver state is recovery in progress
  496. * @is_load_unload_in_progress: Query if driver state Load/Unload in Progress
  497. * @is_driver_unloading: Query if driver is unloading.
  498. * @get_bandwidth_level: Query current bandwidth level for the driver
  499. * This Structure provides callback pointer for HIF to query hdd for driver
  500. * states.
  501. */
  502. struct hif_driver_state_callbacks {
  503. void *context;
  504. void (*set_recovery_in_progress)(void *context, uint8_t val);
  505. bool (*is_recovery_in_progress)(void *context);
  506. bool (*is_load_unload_in_progress)(void *context);
  507. bool (*is_driver_unloading)(void *context);
  508. bool (*is_target_ready)(void *context);
  509. int (*get_bandwidth_level)(void *context);
  510. };
  511. /* This API detaches the HTC layer from the HIF device */
  512. void hif_detach_htc(struct hif_opaque_softc *hif_ctx);
  513. /****************************************************************/
  514. /* BMI and Diag window abstraction */
  515. /****************************************************************/
  516. #define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0))
  517. #define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be
  518. * handled atomically by
  519. * DiagRead/DiagWrite
  520. */
  521. #ifdef WLAN_FEATURE_BMI
  522. /*
  523. * API to handle HIF-specific BMI message exchanges, this API is synchronous
  524. * and only allowed to be called from a context that can block (sleep)
  525. */
  526. QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
  527. qdf_dma_addr_t cmd, qdf_dma_addr_t rsp,
  528. uint8_t *pSendMessage, uint32_t Length,
  529. uint8_t *pResponseMessage,
  530. uint32_t *pResponseLength, uint32_t TimeoutMS);
  531. void hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx);
  532. bool hif_needs_bmi(struct hif_opaque_softc *hif_ctx);
  533. #else /* WLAN_FEATURE_BMI */
  534. static inline void
  535. hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx)
  536. {
  537. }
  538. static inline bool
  539. hif_needs_bmi(struct hif_opaque_softc *hif_ctx)
  540. {
  541. return false;
  542. }
  543. #endif /* WLAN_FEATURE_BMI */
  544. /*
  545. * APIs to handle HIF specific diagnostic read accesses. These APIs are
  546. * synchronous and only allowed to be called from a context that
  547. * can block (sleep). They are not high performance APIs.
  548. *
  549. * hif_diag_read_access reads a 4 Byte aligned/length value from a
  550. * Target register or memory word.
  551. *
  552. * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
  553. */
  554. QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
  555. uint32_t address, uint32_t *data);
  556. QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address,
  557. uint8_t *data, int nbytes);
  558. void hif_dump_target_memory(struct hif_opaque_softc *hif_ctx,
  559. void *ramdump_base, uint32_t address, uint32_t size);
  560. /*
  561. * APIs to handle HIF specific diagnostic write accesses. These APIs are
  562. * synchronous and only allowed to be called from a context that
  563. * can block (sleep).
  564. * They are not high performance APIs.
  565. *
  566. * hif_diag_write_access writes a 4 Byte aligned/length value to a
  567. * Target register or memory word.
  568. *
  569. * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
  570. */
  571. QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx,
  572. uint32_t address, uint32_t data);
  573. QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx,
  574. uint32_t address, uint8_t *data, int nbytes);
  575. typedef void (*fastpath_msg_handler)(void *, qdf_nbuf_t *, uint32_t);
  576. void hif_enable_polled_mode(struct hif_opaque_softc *hif_ctx);
  577. bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx);
  578. /*
  579. * Set the FASTPATH_mode_on flag in sc, for use by data path
  580. */
  581. #ifdef WLAN_FEATURE_FASTPATH
  582. void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx);
  583. bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx);
  584. void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret);
  585. int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx,
  586. fastpath_msg_handler handler, void *context);
  587. #else
  588. static inline int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx,
  589. fastpath_msg_handler handler,
  590. void *context)
  591. {
  592. return QDF_STATUS_E_FAILURE;
  593. }
  594. static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret)
  595. {
  596. return NULL;
  597. }
  598. #endif
  599. /*
  600. * Enable/disable CDC max performance workaround
  601. * For max-performace set this to 0
  602. * To allow SoC to enter sleep set this to 1
  603. */
  604. #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
  605. void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx,
  606. qdf_shared_mem_t **ce_sr,
  607. uint32_t *ce_sr_ring_size,
  608. qdf_dma_addr_t *ce_reg_paddr);
  609. /**
  610. * @brief List of callbacks - filled in by HTC.
  611. */
  612. struct hif_msg_callbacks {
  613. void *Context;
  614. /**< context meaningful to HTC */
  615. QDF_STATUS (*txCompletionHandler)(void *Context, qdf_nbuf_t wbuf,
  616. uint32_t transferID,
  617. uint32_t toeplitz_hash_result);
  618. QDF_STATUS (*rxCompletionHandler)(void *Context, qdf_nbuf_t wbuf,
  619. uint8_t pipeID);
  620. void (*txResourceAvailHandler)(void *context, uint8_t pipe);
  621. void (*fwEventHandler)(void *context, QDF_STATUS status);
  622. void (*update_bundle_stats)(void *context, uint8_t no_of_pkt_in_bundle);
  623. };
  624. enum hif_target_status {
  625. TARGET_STATUS_CONNECTED = 0, /* target connected */
  626. TARGET_STATUS_RESET, /* target got reset */
  627. TARGET_STATUS_EJECT, /* target got ejected */
  628. TARGET_STATUS_SUSPEND /*target got suspend */
  629. };
  630. /**
  631. * enum hif_attribute_flags: configure hif
  632. *
  633. * @HIF_LOWDESC_CE_CFG: Configure HIF with Low descriptor CE
  634. * @HIF_LOWDESC_CE_NO_PKTLOG_CFG: Configure HIF with Low descriptor
  635. * + No pktlog CE
  636. */
  637. enum hif_attribute_flags {
  638. HIF_LOWDESC_CE_CFG = 1,
  639. HIF_LOWDESC_CE_NO_PKTLOG_CFG
  640. };
  641. #define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \
  642. (attr |= (v & 0x01) << 5)
  643. #define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \
  644. (attr |= (v & 0x03) << 6)
  645. #define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \
  646. (attr |= (v & 0x01) << 13)
  647. #define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \
  648. (attr |= (v & 0x01) << 14)
  649. #define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \
  650. (attr |= (v & 0x01) << 15)
  651. #define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \
  652. (attr |= (v & 0x0FFF) << 16)
  653. #define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \
  654. (attr |= (v & 0x01) << 30)
  655. struct hif_ul_pipe_info {
  656. unsigned int nentries;
  657. unsigned int nentries_mask;
  658. unsigned int sw_index;
  659. unsigned int write_index; /* cached copy */
  660. unsigned int hw_index; /* cached copy */
  661. void *base_addr_owner_space; /* Host address space */
  662. qdf_dma_addr_t base_addr_CE_space; /* CE address space */
  663. };
  664. struct hif_dl_pipe_info {
  665. unsigned int nentries;
  666. unsigned int nentries_mask;
  667. unsigned int sw_index;
  668. unsigned int write_index; /* cached copy */
  669. unsigned int hw_index; /* cached copy */
  670. void *base_addr_owner_space; /* Host address space */
  671. qdf_dma_addr_t base_addr_CE_space; /* CE address space */
  672. };
  673. struct hif_pipe_addl_info {
  674. uint32_t pci_mem;
  675. uint32_t ctrl_addr;
  676. struct hif_ul_pipe_info ul_pipe;
  677. struct hif_dl_pipe_info dl_pipe;
  678. };
  679. #ifdef CONFIG_SLUB_DEBUG_ON
  680. #define MSG_FLUSH_NUM 16
  681. #else /* PERF build */
  682. #define MSG_FLUSH_NUM 32
  683. #endif /* SLUB_DEBUG_ON */
  684. struct hif_bus_id;
  685. void hif_claim_device(struct hif_opaque_softc *hif_ctx);
  686. QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx,
  687. int opcode, void *config, uint32_t config_len);
  688. void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx);
  689. void hif_mask_interrupt_call(struct hif_opaque_softc *hif_ctx);
  690. void hif_post_init(struct hif_opaque_softc *hif_ctx, void *hHTC,
  691. struct hif_msg_callbacks *callbacks);
  692. QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx);
  693. void hif_stop(struct hif_opaque_softc *hif_ctx);
  694. void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx);
  695. void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t CmdId, bool start);
  696. void hif_trigger_dump(struct hif_opaque_softc *hif_ctx,
  697. uint8_t cmd_id, bool start);
  698. QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
  699. uint32_t transferID, uint32_t nbytes,
  700. qdf_nbuf_t wbuf, uint32_t data_attr);
  701. void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
  702. int force);
  703. void hif_shut_down_device(struct hif_opaque_softc *hif_ctx);
  704. void hif_get_default_pipe(struct hif_opaque_softc *hif_ctx, uint8_t *ULPipe,
  705. uint8_t *DLPipe);
  706. int hif_map_service_to_pipe(struct hif_opaque_softc *hif_ctx, uint16_t svc_id,
  707. uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
  708. int *dl_is_polled);
  709. uint16_t
  710. hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t PipeID);
  711. void *hif_get_targetdef(struct hif_opaque_softc *hif_ctx);
  712. uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
  713. void hif_set_target_sleep(struct hif_opaque_softc *hif_ctx, bool sleep_ok,
  714. bool wait_for_it);
  715. int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx);
  716. #ifndef HIF_PCI
  717. static inline int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
  718. {
  719. return 0;
  720. }
  721. #else
  722. int hif_check_soc_status(struct hif_opaque_softc *hif_ctx);
  723. #endif
  724. void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
  725. u32 *revision, const char **target_name);
  726. #ifdef RECEIVE_OFFLOAD
  727. /**
  728. * hif_offld_flush_cb_register() - Register the offld flush callback
  729. * @scn: HIF opaque context
  730. * @offld_flush_handler: Flush callback is either ol_flush, incase of rx_thread
  731. * Or GRO/LRO flush when RxThread is not enabled. Called
  732. * with corresponding context for flush.
  733. * Return: None
  734. */
  735. void hif_offld_flush_cb_register(struct hif_opaque_softc *scn,
  736. void (offld_flush_handler)(void *ol_ctx));
  737. /**
  738. * hif_offld_flush_cb_deregister() - deRegister the offld flush callback
  739. * @scn: HIF opaque context
  740. *
  741. * Return: None
  742. */
  743. void hif_offld_flush_cb_deregister(struct hif_opaque_softc *scn);
  744. #endif
  745. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  746. /**
  747. * hif_exec_should_yield() - Check if hif napi context should yield
  748. * @hif_ctx - HIF opaque context
  749. * @grp_id - grp_id of the napi for which check needs to be done
  750. *
  751. * The function uses grp_id to look for NAPI and checks if NAPI needs to
  752. * yield. HIF_EXT_GROUP_MAX_YIELD_DURATION_NS is the duration used for
  753. * yield decision.
  754. *
  755. * Return: true if NAPI needs to yield, else false
  756. */
  757. bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx, uint grp_id);
  758. #else
  759. static inline bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx,
  760. uint grp_id)
  761. {
  762. return false;
  763. }
  764. #endif
  765. void hif_disable_isr(struct hif_opaque_softc *hif_ctx);
  766. void hif_reset_soc(struct hif_opaque_softc *hif_ctx);
  767. void hif_save_htc_htt_config_endpoint(struct hif_opaque_softc *hif_ctx,
  768. int htc_htt_tx_endpoint);
  769. /**
  770. * hif_open() - Create hif handle
  771. * @qdf_ctx: qdf context
  772. * @mode: Driver Mode
  773. * @bus_type: Bus Type
  774. * @cbk: CDS Callbacks
  775. * @psoc: psoc object manager
  776. *
  777. * API to open HIF Context
  778. *
  779. * Return: HIF Opaque Pointer
  780. */
  781. struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx,
  782. uint32_t mode,
  783. enum qdf_bus_type bus_type,
  784. struct hif_driver_state_callbacks *cbk,
  785. struct wlan_objmgr_psoc *psoc);
  786. void hif_close(struct hif_opaque_softc *hif_ctx);
  787. QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev,
  788. void *bdev, const struct hif_bus_id *bid,
  789. enum qdf_bus_type bus_type,
  790. enum hif_enable_type type);
  791. void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type);
  792. #ifdef CE_TASKLET_DEBUG_ENABLE
  793. void hif_enable_ce_latency_stats(struct hif_opaque_softc *hif_ctx,
  794. uint8_t value);
  795. #endif
  796. void hif_display_stats(struct hif_opaque_softc *hif_ctx);
  797. void hif_clear_stats(struct hif_opaque_softc *hif_ctx);
  798. /**
  799. * enum wlan_rtpm_dbgid - runtime pm put/get debug id
  800. * @RTPM_ID_RESVERD: Reserved
  801. * @RTPM_ID_WMI: WMI sending msg, expect put happen at
  802. * tx completion from CE level directly.
  803. * @RTPM_ID_HTC: pkt sending by HTT_DATA_MSG_SVC, expect
  804. * put from fw response or just in
  805. * htc_issue_packets
  806. * @RTPM_ID_QOS_NOTIFY: pm qos notifer
  807. * @RTPM_ID_DP_TX_DESC_ALLOC_FREE: tx desc alloc/free
  808. * @RTPM_ID_CE_SEND_FAST: operation in ce_send_fast, not include
  809. * the pkt put happens outside this function
  810. * @RTPM_ID_SUSPEND_RESUME: suspend/resume in hdd
  811. * @RTPM_ID_DW_TX_HW_ENQUEUE: operation in functin dp_tx_hw_enqueue
  812. * @RTPM_ID_HAL_REO_CMD: HAL_REO_CMD operation
  813. * @RTPM_ID_DP_PRINT_RING_STATS: operation in dp_print_ring_stats
  814. */
  815. /* New value added to the enum must also be reflected in function
  816. * rtpm_string_from_dbgid()
  817. */
  818. typedef enum {
  819. RTPM_ID_RESVERD = 0,
  820. RTPM_ID_WMI = 1,
  821. RTPM_ID_HTC = 2,
  822. RTPM_ID_QOS_NOTIFY = 3,
  823. RTPM_ID_DP_TX_DESC_ALLOC_FREE = 4,
  824. RTPM_ID_CE_SEND_FAST = 5,
  825. RTPM_ID_SUSPEND_RESUME = 6,
  826. RTPM_ID_DW_TX_HW_ENQUEUE = 7,
  827. RTPM_ID_HAL_REO_CMD = 8,
  828. RTPM_ID_DP_PRINT_RING_STATS = 9,
  829. RTPM_ID_MAX,
  830. } wlan_rtpm_dbgid;
  831. /**
  832. * rtpm_string_from_dbgid() - Convert dbgid to respective string
  833. * @id - debug id
  834. *
  835. * Debug support function to convert dbgid to string.
  836. * Please note to add new string in the array at index equal to
  837. * its enum value in wlan_rtpm_dbgid.
  838. */
  839. static inline char *rtpm_string_from_dbgid(wlan_rtpm_dbgid id)
  840. {
  841. static const char *strings[] = { "RTPM_ID_RESVERD",
  842. "RTPM_ID_WMI",
  843. "RTPM_ID_HTC",
  844. "RTPM_ID_QOS_NOTIFY",
  845. "RTPM_ID_DP_TX_DESC_ALLOC_FREE",
  846. "RTPM_ID_CE_SEND_FAST",
  847. "RTPM_ID_SUSPEND_RESUME",
  848. "RTPM_ID_DW_TX_HW_ENQUEUE",
  849. "RTPM_ID_HAL_REO_CMD",
  850. "RTPM_ID_DP_PRINT_RING_STATS",
  851. "RTPM_ID_MAX"};
  852. return (char *)strings[id];
  853. }
  854. #ifdef FEATURE_RUNTIME_PM
  855. struct hif_pm_runtime_lock;
  856. void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx);
  857. int hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx,
  858. wlan_rtpm_dbgid rtpm_dbgid);
  859. int hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx,
  860. wlan_rtpm_dbgid rtpm_dbgid);
  861. int hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx);
  862. int hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx,
  863. wlan_rtpm_dbgid rtpm_dbgid);
  864. void hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx,
  865. wlan_rtpm_dbgid rtpm_dbgid);
  866. int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx,
  867. wlan_rtpm_dbgid rtpm_dbgid);
  868. int hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx,
  869. wlan_rtpm_dbgid rtpm_dbgid);
  870. void hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx);
  871. int hif_runtime_lock_init(qdf_runtime_lock_t *lock, const char *name);
  872. void hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx,
  873. struct hif_pm_runtime_lock *lock);
  874. int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc,
  875. struct hif_pm_runtime_lock *lock);
  876. int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc,
  877. struct hif_pm_runtime_lock *lock);
  878. int hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc,
  879. struct hif_pm_runtime_lock *lock, unsigned int delay);
  880. bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx);
  881. int hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx);
  882. void hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx,
  883. int val);
  884. void hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx);
  885. int hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx);
  886. qdf_time_t hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx);
  887. int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx);
  888. #else
  889. struct hif_pm_runtime_lock {
  890. const char *name;
  891. };
  892. static inline void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx) {}
  893. static inline int
  894. hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx,
  895. wlan_rtpm_dbgid rtpm_dbgid)
  896. { return 0; }
  897. static inline int
  898. hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx,
  899. wlan_rtpm_dbgid rtpm_dbgid)
  900. { return 0; }
  901. static inline int
  902. hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx)
  903. { return 0; }
  904. static inline void
  905. hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx,
  906. wlan_rtpm_dbgid rtpm_dbgid)
  907. {}
  908. static inline int
  909. hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid)
  910. { return 0; }
  911. static inline int
  912. hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid)
  913. { return 0; }
  914. static inline int
  915. hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx,
  916. wlan_rtpm_dbgid rtpm_dbgid)
  917. { return 0; }
  918. static inline void
  919. hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx) {};
  920. static inline int hif_runtime_lock_init(qdf_runtime_lock_t *lock,
  921. const char *name)
  922. { return 0; }
  923. static inline void
  924. hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx,
  925. struct hif_pm_runtime_lock *lock) {}
  926. static inline int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc,
  927. struct hif_pm_runtime_lock *lock)
  928. { return 0; }
  929. static inline int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc,
  930. struct hif_pm_runtime_lock *lock)
  931. { return 0; }
  932. static inline int
  933. hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc,
  934. struct hif_pm_runtime_lock *lock, unsigned int delay)
  935. { return 0; }
  936. static inline bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx)
  937. { return false; }
  938. static inline int
  939. hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx)
  940. { return 0; }
  941. static inline void
  942. hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx, int val)
  943. { return; }
  944. static inline void
  945. hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx) {};
  946. static inline int
  947. hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx)
  948. { return 0; }
  949. static inline qdf_time_t
  950. hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx)
  951. { return 0; }
  952. static inline int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx)
  953. { return 0; }
  954. #endif
  955. void hif_enable_power_management(struct hif_opaque_softc *hif_ctx,
  956. bool is_packet_log_enabled);
  957. void hif_disable_power_management(struct hif_opaque_softc *hif_ctx);
  958. void hif_vote_link_down(struct hif_opaque_softc *hif_ctx);
  959. void hif_vote_link_up(struct hif_opaque_softc *hif_ctx);
  960. bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx);
  961. #ifdef IPA_OFFLOAD
  962. /**
  963. * hif_get_ipa_hw_type() - get IPA hw type
  964. *
  965. * This API return the IPA hw type.
  966. *
  967. * Return: IPA hw type
  968. */
  969. static inline
  970. enum ipa_hw_type hif_get_ipa_hw_type(void)
  971. {
  972. return ipa_get_hw_type();
  973. }
  974. /**
  975. * hif_get_ipa_present() - get IPA hw status
  976. *
  977. * This API return the IPA hw status.
  978. *
  979. * Return: true if IPA is present or false otherwise
  980. */
  981. static inline
  982. bool hif_get_ipa_present(void)
  983. {
  984. if (ipa_uc_reg_rdyCB(NULL) != -EPERM)
  985. return true;
  986. else
  987. return false;
  988. }
  989. #endif
  990. int hif_bus_resume(struct hif_opaque_softc *hif_ctx);
  991. /**
  992. * hif_bus_ealry_suspend() - stop non wmi tx traffic
  993. * @context: hif context
  994. */
  995. int hif_bus_early_suspend(struct hif_opaque_softc *hif_ctx);
  996. /**
  997. * hif_bus_late_resume() - resume non wmi traffic
  998. * @context: hif context
  999. */
  1000. int hif_bus_late_resume(struct hif_opaque_softc *hif_ctx);
  1001. int hif_bus_suspend(struct hif_opaque_softc *hif_ctx);
  1002. int hif_bus_resume_noirq(struct hif_opaque_softc *hif_ctx);
  1003. int hif_bus_suspend_noirq(struct hif_opaque_softc *hif_ctx);
  1004. /**
  1005. * hif_apps_irqs_enable() - Enables all irqs from the APPS side
  1006. * @hif_ctx: an opaque HIF handle to use
  1007. *
  1008. * As opposed to the standard hif_irq_enable, this function always applies to
  1009. * the APPS side kernel interrupt handling.
  1010. *
  1011. * Return: errno
  1012. */
  1013. int hif_apps_irqs_enable(struct hif_opaque_softc *hif_ctx);
  1014. /**
  1015. * hif_apps_irqs_disable() - Disables all irqs from the APPS side
  1016. * @hif_ctx: an opaque HIF handle to use
  1017. *
  1018. * As opposed to the standard hif_irq_disable, this function always applies to
  1019. * the APPS side kernel interrupt handling.
  1020. *
  1021. * Return: errno
  1022. */
  1023. int hif_apps_irqs_disable(struct hif_opaque_softc *hif_ctx);
  1024. /**
  1025. * hif_apps_wake_irq_enable() - Enables the wake irq from the APPS side
  1026. * @hif_ctx: an opaque HIF handle to use
  1027. *
  1028. * As opposed to the standard hif_irq_enable, this function always applies to
  1029. * the APPS side kernel interrupt handling.
  1030. *
  1031. * Return: errno
  1032. */
  1033. int hif_apps_wake_irq_enable(struct hif_opaque_softc *hif_ctx);
  1034. /**
  1035. * hif_apps_wake_irq_disable() - Disables the wake irq from the APPS side
  1036. * @hif_ctx: an opaque HIF handle to use
  1037. *
  1038. * As opposed to the standard hif_irq_disable, this function always applies to
  1039. * the APPS side kernel interrupt handling.
  1040. *
  1041. * Return: errno
  1042. */
  1043. int hif_apps_wake_irq_disable(struct hif_opaque_softc *hif_ctx);
  1044. #ifdef FEATURE_RUNTIME_PM
  1045. int hif_pre_runtime_suspend(struct hif_opaque_softc *hif_ctx);
  1046. void hif_pre_runtime_resume(struct hif_opaque_softc *hif_ctx);
  1047. int hif_runtime_suspend(struct hif_opaque_softc *hif_ctx);
  1048. int hif_runtime_resume(struct hif_opaque_softc *hif_ctx);
  1049. void hif_process_runtime_suspend_success(struct hif_opaque_softc *hif_ctx);
  1050. void hif_process_runtime_suspend_failure(struct hif_opaque_softc *hif_ctx);
  1051. void hif_process_runtime_resume_success(struct hif_opaque_softc *hif_ctx);
  1052. #endif
  1053. int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size);
  1054. int hif_dump_registers(struct hif_opaque_softc *scn);
  1055. int ol_copy_ramdump(struct hif_opaque_softc *scn);
  1056. void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx);
  1057. void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
  1058. u32 *revision, const char **target_name);
  1059. enum qdf_bus_type hif_get_bus_type(struct hif_opaque_softc *hif_hdl);
  1060. struct hif_target_info *hif_get_target_info_handle(struct hif_opaque_softc *
  1061. scn);
  1062. struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *hif_ctx);
  1063. struct ramdump_info *hif_get_ramdump_ctx(struct hif_opaque_softc *hif_ctx);
  1064. enum hif_target_status hif_get_target_status(struct hif_opaque_softc *hif_ctx);
  1065. void hif_set_target_status(struct hif_opaque_softc *hif_ctx, enum
  1066. hif_target_status);
  1067. void hif_init_ini_config(struct hif_opaque_softc *hif_ctx,
  1068. struct hif_config_info *cfg);
  1069. void hif_update_tx_ring(struct hif_opaque_softc *osc, u_int32_t num_htt_cmpls);
  1070. qdf_nbuf_t hif_batch_send(struct hif_opaque_softc *osc, qdf_nbuf_t msdu,
  1071. uint32_t transfer_id, u_int32_t len, uint32_t sendhead);
  1072. QDF_STATUS hif_send_single(struct hif_opaque_softc *osc, qdf_nbuf_t msdu,
  1073. uint32_t transfer_id, u_int32_t len);
  1074. int hif_send_fast(struct hif_opaque_softc *osc, qdf_nbuf_t nbuf,
  1075. uint32_t transfer_id, uint32_t download_len);
  1076. void hif_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len);
  1077. void hif_ce_war_disable(void);
  1078. void hif_ce_war_enable(void);
  1079. void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num);
  1080. #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT
  1081. struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc,
  1082. struct hif_pipe_addl_info *hif_info, uint32_t pipe_number);
  1083. uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc,
  1084. uint32_t pipe_num);
  1085. int32_t hif_get_nss_wifiol_bypass_nw_process(struct hif_opaque_softc *osc);
  1086. #endif /* QCA_NSS_WIFI_OFFLOAD_SUPPORT */
  1087. void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled,
  1088. int rx_bundle_cnt);
  1089. int hif_bus_reset_resume(struct hif_opaque_softc *hif_ctx);
  1090. void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib);
  1091. void *hif_get_lro_info(int ctx_id, struct hif_opaque_softc *hif_hdl);
  1092. enum hif_exec_type {
  1093. HIF_EXEC_NAPI_TYPE,
  1094. HIF_EXEC_TASKLET_TYPE,
  1095. };
  1096. typedef uint32_t (*ext_intr_handler)(void *, uint32_t);
  1097. /**
  1098. * hif_get_int_ctx_irq_num() - retrieve an irq num for an interrupt context id
  1099. * @softc: hif opaque context owning the exec context
  1100. * @id: the id of the interrupt context
  1101. *
  1102. * Return: IRQ number of the first (zero'th) IRQ within the interrupt context ID
  1103. * 'id' registered with the OS
  1104. */
  1105. int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc,
  1106. uint8_t id);
  1107. uint32_t hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx);
  1108. uint32_t hif_register_ext_group(struct hif_opaque_softc *hif_ctx,
  1109. uint32_t numirq, uint32_t irq[], ext_intr_handler handler,
  1110. void *cb_ctx, const char *context_name,
  1111. enum hif_exec_type type, uint32_t scale);
  1112. void hif_deregister_exec_group(struct hif_opaque_softc *hif_ctx,
  1113. const char *context_name);
  1114. void hif_update_pipe_callback(struct hif_opaque_softc *osc,
  1115. u_int8_t pipeid,
  1116. struct hif_msg_callbacks *callbacks);
  1117. /**
  1118. * hif_print_napi_stats() - Display HIF NAPI stats
  1119. * @hif_ctx - HIF opaque context
  1120. *
  1121. * Return: None
  1122. */
  1123. void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx);
  1124. /* hif_clear_napi_stats() - function clears the stats of the
  1125. * latency when called.
  1126. * @hif_ctx - the HIF context to assign the callback to
  1127. *
  1128. * Return: None
  1129. */
  1130. void hif_clear_napi_stats(struct hif_opaque_softc *hif_ctx);
  1131. #ifdef __cplusplus
  1132. }
  1133. #endif
  1134. #ifdef FORCE_WAKE
  1135. /**
  1136. * hif_force_wake_request() - Function to wake from power collapse
  1137. * @handle: HIF opaque handle
  1138. *
  1139. * Description: API to check if the device is awake or not before
  1140. * read/write to BAR + 4K registers. If device is awake return
  1141. * success otherwise write '1' to
  1142. * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG which will interrupt
  1143. * the device and does wakeup the PCI and MHI within 50ms
  1144. * and then the device writes a value to
  1145. * PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG to complete the
  1146. * handshake process to let the host know the device is awake.
  1147. *
  1148. * Return: zero - success/non-zero - failure
  1149. */
  1150. int hif_force_wake_request(struct hif_opaque_softc *handle);
  1151. /**
  1152. * hif_force_wake_release() - API to release/reset the SOC wake register
  1153. * from interrupting the device.
  1154. * @handle: HIF opaque handle
  1155. *
  1156. * Description: API to set the
  1157. * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG to '0'
  1158. * to release the interrupt line.
  1159. *
  1160. * Return: zero - success/non-zero - failure
  1161. */
  1162. int hif_force_wake_release(struct hif_opaque_softc *handle);
  1163. #else
  1164. static inline
  1165. int hif_force_wake_request(struct hif_opaque_softc *handle)
  1166. {
  1167. return 0;
  1168. }
  1169. static inline
  1170. int hif_force_wake_release(struct hif_opaque_softc *handle)
  1171. {
  1172. return 0;
  1173. }
  1174. #endif /* FORCE_WAKE */
  1175. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1176. /**
  1177. * hif_prevent_link_low_power_states() - Prevent from going to low power states
  1178. * @hif - HIF opaque context
  1179. *
  1180. * Return: 0 on success. Error code on failure.
  1181. */
  1182. int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif);
  1183. /**
  1184. * hif_allow_link_low_power_states() - Allow link to go to low power states
  1185. * @hif - HIF opaque context
  1186. *
  1187. * Return: None
  1188. */
  1189. void hif_allow_link_low_power_states(struct hif_opaque_softc *hif);
  1190. #else
  1191. static inline
  1192. int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif)
  1193. {
  1194. return 0;
  1195. }
  1196. static inline
  1197. void hif_allow_link_low_power_states(struct hif_opaque_softc *hif)
  1198. {
  1199. }
  1200. #endif
  1201. void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle);
  1202. /**
  1203. * hif_set_initial_wakeup_cb() - set the initial wakeup event handler function
  1204. * @hif_ctx - the HIF context to assign the callback to
  1205. * @callback - the callback to assign
  1206. * @priv - the private data to pass to the callback when invoked
  1207. *
  1208. * Return: None
  1209. */
  1210. void hif_set_initial_wakeup_cb(struct hif_opaque_softc *hif_ctx,
  1211. void (*callback)(void *),
  1212. void *priv);
  1213. /*
  1214. * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked
  1215. * for defined here
  1216. */
  1217. #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)
  1218. ssize_t hif_dump_desc_trace_buf(struct device *dev,
  1219. struct device_attribute *attr, char *buf);
  1220. ssize_t hif_input_desc_trace_buf_index(struct hif_softc *scn,
  1221. const char *buf, size_t size);
  1222. ssize_t hif_ce_en_desc_hist(struct hif_softc *scn,
  1223. const char *buf, size_t size);
  1224. ssize_t hif_disp_ce_enable_desc_data_hist(struct hif_softc *scn, char *buf);
  1225. ssize_t hif_dump_desc_event(struct hif_softc *scn, char *buf);
  1226. #endif/*#if defined(HIF_CONFIG_SLUB_DEBUG_ON)||defined(HIF_CE_DEBUG_DATA_BUF)*/
  1227. /**
  1228. * hif_set_ce_service_max_yield_time() - sets CE service max yield time
  1229. * @hif: hif context
  1230. * @ce_service_max_yield_time: CE service max yield time to set
  1231. *
  1232. * This API storess CE service max yield time in hif context based
  1233. * on ini value.
  1234. *
  1235. * Return: void
  1236. */
  1237. void hif_set_ce_service_max_yield_time(struct hif_opaque_softc *hif,
  1238. uint32_t ce_service_max_yield_time);
  1239. /**
  1240. * hif_get_ce_service_max_yield_time() - get CE service max yield time
  1241. * @hif: hif context
  1242. *
  1243. * This API returns CE service max yield time.
  1244. *
  1245. * Return: CE service max yield time
  1246. */
  1247. unsigned long long
  1248. hif_get_ce_service_max_yield_time(struct hif_opaque_softc *hif);
  1249. /**
  1250. * hif_set_ce_service_max_rx_ind_flush() - sets CE service max rx ind flush
  1251. * @hif: hif context
  1252. * @ce_service_max_rx_ind_flush: CE service max rx ind flush to set
  1253. *
  1254. * This API stores CE service max rx ind flush in hif context based
  1255. * on ini value.
  1256. *
  1257. * Return: void
  1258. */
  1259. void hif_set_ce_service_max_rx_ind_flush(struct hif_opaque_softc *hif,
  1260. uint8_t ce_service_max_rx_ind_flush);
  1261. #ifdef OL_ATH_SMART_LOGGING
  1262. /*
  1263. * hif_log_ce_dump() - Copy all the CE DEST ring to buf
  1264. * @scn : HIF handler
  1265. * @buf_cur: Current pointer in ring buffer
  1266. * @buf_init:Start of the ring buffer
  1267. * @buf_sz: Size of the ring buffer
  1268. * @ce: Copy Engine id
  1269. * @skb_sz: Max size of the SKB buffer to be copied
  1270. *
  1271. * Calls the respective function to dump all the CE SRC/DEST ring descriptors
  1272. * and buffers pointed by them in to the given buf
  1273. *
  1274. * Return: Current pointer in ring buffer
  1275. */
  1276. uint8_t *hif_log_dump_ce(struct hif_softc *scn, uint8_t *buf_cur,
  1277. uint8_t *buf_init, uint32_t buf_sz,
  1278. uint32_t ce, uint32_t skb_sz);
  1279. #endif /* OL_ATH_SMART_LOGGING */
  1280. /*
  1281. * hif_softc_to_hif_opaque_softc - API to convert hif_softc handle
  1282. * to hif_opaque_softc handle
  1283. * @hif_handle - hif_softc type
  1284. *
  1285. * Return: hif_opaque_softc type
  1286. */
  1287. static inline struct hif_opaque_softc *
  1288. hif_softc_to_hif_opaque_softc(struct hif_softc *hif_handle)
  1289. {
  1290. return (struct hif_opaque_softc *)hif_handle;
  1291. }
  1292. #ifdef FORCE_WAKE
  1293. /**
  1294. * hif_srng_init_phase(): Indicate srng initialization phase
  1295. * to avoid force wake as UMAC power collapse is not yet
  1296. * enabled
  1297. * @hif_ctx: hif opaque handle
  1298. * @init_phase: initialization phase
  1299. *
  1300. * Return: None
  1301. */
  1302. void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx,
  1303. bool init_phase);
  1304. #else
  1305. static inline
  1306. void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx,
  1307. bool init_phase)
  1308. {
  1309. }
  1310. #endif /* FORCE_WAKE */
  1311. #ifdef HIF_CE_LOG_INFO
  1312. /**
  1313. * hif_log_ce_info() - API to log ce info
  1314. * @scn: hif handle
  1315. * @data: hang event data buffer
  1316. * @offset: offset at which data needs to be written
  1317. *
  1318. * Return: None
  1319. */
  1320. void hif_log_ce_info(struct hif_softc *scn, uint8_t *data,
  1321. unsigned int *offset);
  1322. #else
  1323. static inline
  1324. void hif_log_ce_info(struct hif_softc *scn, uint8_t *data,
  1325. unsigned int *offset)
  1326. {
  1327. }
  1328. #endif
  1329. #ifdef HIF_CPU_PERF_AFFINE_MASK
  1330. /**
  1331. * hif_config_irq_set_perf_affinity_hint() - API to set affinity
  1332. * @hif_ctx: hif opaque handle
  1333. *
  1334. * This function is used to move the WLAN IRQs to perf cores in
  1335. * case of defconfig builds.
  1336. *
  1337. * Return: None
  1338. */
  1339. void hif_config_irq_set_perf_affinity_hint(
  1340. struct hif_opaque_softc *hif_ctx);
  1341. #else
  1342. static inline void hif_config_irq_set_perf_affinity_hint(
  1343. struct hif_opaque_softc *hif_ctx)
  1344. {
  1345. }
  1346. #endif
  1347. #endif /* _HIF_H_ */