dp_tx.c 117 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421
  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. /* TODO Add support in TSO */
  43. #define DP_DESC_NUM_FRAG(x) 0
  44. /* disable TQM_BYPASS */
  45. #define TQM_BYPASS_WAR 0
  46. /* invalid peer id for reinject*/
  47. #define DP_INVALID_PEER 0XFFFE
  48. /*mapping between hal encrypt type and cdp_sec_type*/
  49. #define MAX_CDP_SEC_TYPE 12
  50. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  51. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  52. HAL_TX_ENCRYPT_TYPE_WEP_128,
  53. HAL_TX_ENCRYPT_TYPE_WEP_104,
  54. HAL_TX_ENCRYPT_TYPE_WEP_40,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  57. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  58. HAL_TX_ENCRYPT_TYPE_WAPI,
  59. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  62. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  63. #ifdef QCA_TX_LIMIT_CHECK
  64. /**
  65. * dp_tx_limit_check - Check if allocated tx descriptors reached
  66. * soc max limit and pdev max limit
  67. * @vdev: DP vdev handle
  68. *
  69. * Return: true if allocated tx descriptors reached max configured value, else
  70. * false
  71. */
  72. static inline bool
  73. dp_tx_limit_check(struct dp_vdev *vdev)
  74. {
  75. struct dp_pdev *pdev = vdev->pdev;
  76. struct dp_soc *soc = pdev->soc;
  77. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  78. soc->num_tx_allowed) {
  79. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  80. "%s: queued packets are more than max tx, drop the frame",
  81. __func__);
  82. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  83. return true;
  84. }
  85. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  86. pdev->num_tx_allowed) {
  87. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  88. "%s: queued packets are more than max tx, drop the frame",
  89. __func__);
  90. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  91. return true;
  92. }
  93. return false;
  94. }
  95. /**
  96. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  97. * @vdev: DP pdev handle
  98. *
  99. * Return: void
  100. */
  101. static inline void
  102. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  103. {
  104. struct dp_soc *soc = pdev->soc;
  105. qdf_atomic_inc(&pdev->num_tx_outstanding);
  106. qdf_atomic_inc(&soc->num_tx_outstanding);
  107. }
  108. /**
  109. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  110. * @vdev: DP pdev handle
  111. *
  112. * Return: void
  113. */
  114. static inline void
  115. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  116. {
  117. struct dp_soc *soc = pdev->soc;
  118. qdf_atomic_dec(&pdev->num_tx_outstanding);
  119. qdf_atomic_dec(&soc->num_tx_outstanding);
  120. }
  121. #else //QCA_TX_LIMIT_CHECK
  122. static inline bool
  123. dp_tx_limit_check(struct dp_vdev *vdev)
  124. {
  125. return false;
  126. }
  127. static inline void
  128. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  129. {
  130. qdf_atomic_inc(&pdev->num_tx_outstanding);
  131. }
  132. static inline void
  133. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  134. {
  135. qdf_atomic_dec(&pdev->num_tx_outstanding);
  136. }
  137. #endif //QCA_TX_LIMIT_CHECK
  138. #if defined(FEATURE_TSO)
  139. /**
  140. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  141. *
  142. * @soc - core txrx main context
  143. * @seg_desc - tso segment descriptor
  144. * @num_seg_desc - tso number segment descriptor
  145. */
  146. static void dp_tx_tso_unmap_segment(
  147. struct dp_soc *soc,
  148. struct qdf_tso_seg_elem_t *seg_desc,
  149. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  150. {
  151. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  152. if (qdf_unlikely(!seg_desc)) {
  153. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  154. __func__, __LINE__);
  155. qdf_assert(0);
  156. } else if (qdf_unlikely(!num_seg_desc)) {
  157. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  158. __func__, __LINE__);
  159. qdf_assert(0);
  160. } else {
  161. bool is_last_seg;
  162. /* no tso segment left to do dma unmap */
  163. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  164. return;
  165. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  166. true : false;
  167. qdf_nbuf_unmap_tso_segment(soc->osdev,
  168. seg_desc, is_last_seg);
  169. num_seg_desc->num_seg.tso_cmn_num_seg--;
  170. }
  171. }
  172. /**
  173. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  174. * back to the freelist
  175. *
  176. * @soc - soc device handle
  177. * @tx_desc - Tx software descriptor
  178. */
  179. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  180. struct dp_tx_desc_s *tx_desc)
  181. {
  182. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  183. if (qdf_unlikely(!tx_desc->tso_desc)) {
  184. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  185. "%s %d TSO desc is NULL!",
  186. __func__, __LINE__);
  187. qdf_assert(0);
  188. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  189. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  190. "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  195. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  196. /* Add the tso num segment into the free list */
  197. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  198. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  199. tx_desc->tso_num_desc);
  200. tx_desc->tso_num_desc = NULL;
  201. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  202. }
  203. /* Add the tso segment into the free list*/
  204. dp_tx_tso_desc_free(soc,
  205. tx_desc->pool_id, tx_desc->tso_desc);
  206. tx_desc->tso_desc = NULL;
  207. }
  208. }
  209. #else
  210. static void dp_tx_tso_unmap_segment(
  211. struct dp_soc *soc,
  212. struct qdf_tso_seg_elem_t *seg_desc,
  213. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  214. {
  215. }
  216. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  217. struct dp_tx_desc_s *tx_desc)
  218. {
  219. }
  220. #endif
  221. /**
  222. * dp_tx_desc_release() - Release Tx Descriptor
  223. * @tx_desc : Tx Descriptor
  224. * @desc_pool_id: Descriptor Pool ID
  225. *
  226. * Deallocate all resources attached to Tx descriptor and free the Tx
  227. * descriptor.
  228. *
  229. * Return:
  230. */
  231. static void
  232. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  233. {
  234. struct dp_pdev *pdev = tx_desc->pdev;
  235. struct dp_soc *soc;
  236. uint8_t comp_status = 0;
  237. qdf_assert(pdev);
  238. soc = pdev->soc;
  239. if (tx_desc->frm_type == dp_tx_frm_tso)
  240. dp_tx_tso_desc_release(soc, tx_desc);
  241. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  242. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  243. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  244. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  245. dp_tx_outstanding_dec(pdev);
  246. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  247. qdf_atomic_dec(&pdev->num_tx_exception);
  248. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  249. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  250. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  251. soc->hal_soc);
  252. else
  253. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  255. "Tx Completion Release desc %d status %d outstanding %d",
  256. tx_desc->id, comp_status,
  257. qdf_atomic_read(&pdev->num_tx_outstanding));
  258. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  259. return;
  260. }
  261. /**
  262. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  263. * @vdev: DP vdev Handle
  264. * @nbuf: skb
  265. * @msdu_info: msdu_info required to create HTT metadata
  266. *
  267. * Prepares and fills HTT metadata in the frame pre-header for special frames
  268. * that should be transmitted using varying transmit parameters.
  269. * There are 2 VDEV modes that currently needs this special metadata -
  270. * 1) Mesh Mode
  271. * 2) DSRC Mode
  272. *
  273. * Return: HTT metadata size
  274. *
  275. */
  276. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  277. struct dp_tx_msdu_info_s *msdu_info)
  278. {
  279. uint32_t *meta_data = msdu_info->meta_data;
  280. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  281. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  282. uint8_t htt_desc_size;
  283. /* Size rounded of multiple of 8 bytes */
  284. uint8_t htt_desc_size_aligned;
  285. uint8_t *hdr = NULL;
  286. /*
  287. * Metadata - HTT MSDU Extension header
  288. */
  289. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  290. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  291. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  292. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  293. meta_data[0])) {
  294. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  295. htt_desc_size_aligned)) {
  296. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  297. htt_desc_size_aligned);
  298. if (!nbuf) {
  299. /*
  300. * qdf_nbuf_realloc_headroom won't do skb_clone
  301. * as skb_realloc_headroom does. so, no free is
  302. * needed here.
  303. */
  304. DP_STATS_INC(vdev,
  305. tx_i.dropped.headroom_insufficient,
  306. 1);
  307. qdf_print(" %s[%d] skb_realloc_headroom failed",
  308. __func__, __LINE__);
  309. return 0;
  310. }
  311. }
  312. /* Fill and add HTT metaheader */
  313. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  314. if (!hdr) {
  315. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  316. "Error in filling HTT metadata");
  317. return 0;
  318. }
  319. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  320. } else if (vdev->opmode == wlan_op_mode_ocb) {
  321. /* Todo - Add support for DSRC */
  322. }
  323. return htt_desc_size_aligned;
  324. }
  325. /**
  326. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  327. * @tso_seg: TSO segment to process
  328. * @ext_desc: Pointer to MSDU extension descriptor
  329. *
  330. * Return: void
  331. */
  332. #if defined(FEATURE_TSO)
  333. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  334. void *ext_desc)
  335. {
  336. uint8_t num_frag;
  337. uint32_t tso_flags;
  338. /*
  339. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  340. * tcp_flag_mask
  341. *
  342. * Checksum enable flags are set in TCL descriptor and not in Extension
  343. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  344. */
  345. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  346. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  347. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  348. tso_seg->tso_flags.ip_len);
  349. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  350. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  351. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  352. uint32_t lo = 0;
  353. uint32_t hi = 0;
  354. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  355. (tso_seg->tso_frags[num_frag].length));
  356. qdf_dmaaddr_to_32s(
  357. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  358. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  359. tso_seg->tso_frags[num_frag].length);
  360. }
  361. return;
  362. }
  363. #else
  364. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  365. void *ext_desc)
  366. {
  367. return;
  368. }
  369. #endif
  370. #if defined(FEATURE_TSO)
  371. /**
  372. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  373. * allocated and free them
  374. *
  375. * @soc: soc handle
  376. * @free_seg: list of tso segments
  377. * @msdu_info: msdu descriptor
  378. *
  379. * Return - void
  380. */
  381. static void dp_tx_free_tso_seg_list(
  382. struct dp_soc *soc,
  383. struct qdf_tso_seg_elem_t *free_seg,
  384. struct dp_tx_msdu_info_s *msdu_info)
  385. {
  386. struct qdf_tso_seg_elem_t *next_seg;
  387. while (free_seg) {
  388. next_seg = free_seg->next;
  389. dp_tx_tso_desc_free(soc,
  390. msdu_info->tx_queue.desc_pool_id,
  391. free_seg);
  392. free_seg = next_seg;
  393. }
  394. }
  395. /**
  396. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  397. * allocated and free them
  398. *
  399. * @soc: soc handle
  400. * @free_num_seg: list of tso number segments
  401. * @msdu_info: msdu descriptor
  402. * Return - void
  403. */
  404. static void dp_tx_free_tso_num_seg_list(
  405. struct dp_soc *soc,
  406. struct qdf_tso_num_seg_elem_t *free_num_seg,
  407. struct dp_tx_msdu_info_s *msdu_info)
  408. {
  409. struct qdf_tso_num_seg_elem_t *next_num_seg;
  410. while (free_num_seg) {
  411. next_num_seg = free_num_seg->next;
  412. dp_tso_num_seg_free(soc,
  413. msdu_info->tx_queue.desc_pool_id,
  414. free_num_seg);
  415. free_num_seg = next_num_seg;
  416. }
  417. }
  418. /**
  419. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  420. * do dma unmap for each segment
  421. *
  422. * @soc: soc handle
  423. * @free_seg: list of tso segments
  424. * @num_seg_desc: tso number segment descriptor
  425. *
  426. * Return - void
  427. */
  428. static void dp_tx_unmap_tso_seg_list(
  429. struct dp_soc *soc,
  430. struct qdf_tso_seg_elem_t *free_seg,
  431. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  432. {
  433. struct qdf_tso_seg_elem_t *next_seg;
  434. if (qdf_unlikely(!num_seg_desc)) {
  435. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  436. return;
  437. }
  438. while (free_seg) {
  439. next_seg = free_seg->next;
  440. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  441. free_seg = next_seg;
  442. }
  443. }
  444. #ifdef FEATURE_TSO_STATS
  445. /**
  446. * dp_tso_get_stats_idx: Retrieve the tso packet id
  447. * @pdev - pdev handle
  448. *
  449. * Return: id
  450. */
  451. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  452. {
  453. uint32_t stats_idx;
  454. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  455. % CDP_MAX_TSO_PACKETS);
  456. return stats_idx;
  457. }
  458. #else
  459. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  460. {
  461. return 0;
  462. }
  463. #endif /* FEATURE_TSO_STATS */
  464. /**
  465. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  466. * free the tso segments descriptor and
  467. * tso num segments descriptor
  468. *
  469. * @soc: soc handle
  470. * @msdu_info: msdu descriptor
  471. * @tso_seg_unmap: flag to show if dma unmap is necessary
  472. *
  473. * Return - void
  474. */
  475. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  476. struct dp_tx_msdu_info_s *msdu_info,
  477. bool tso_seg_unmap)
  478. {
  479. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  480. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  481. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  482. tso_info->tso_num_seg_list;
  483. /* do dma unmap for each segment */
  484. if (tso_seg_unmap)
  485. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  486. /* free all tso number segment descriptor though looks only have 1 */
  487. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  488. /* free all tso segment descriptor */
  489. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  490. }
  491. /**
  492. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  493. * @vdev: virtual device handle
  494. * @msdu: network buffer
  495. * @msdu_info: meta data associated with the msdu
  496. *
  497. * Return: QDF_STATUS_SUCCESS success
  498. */
  499. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  500. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  501. {
  502. struct qdf_tso_seg_elem_t *tso_seg;
  503. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  504. struct dp_soc *soc = vdev->pdev->soc;
  505. struct dp_pdev *pdev = vdev->pdev;
  506. struct qdf_tso_info_t *tso_info;
  507. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  508. tso_info = &msdu_info->u.tso_info;
  509. tso_info->curr_seg = NULL;
  510. tso_info->tso_seg_list = NULL;
  511. tso_info->num_segs = num_seg;
  512. msdu_info->frm_type = dp_tx_frm_tso;
  513. tso_info->tso_num_seg_list = NULL;
  514. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  515. while (num_seg) {
  516. tso_seg = dp_tx_tso_desc_alloc(
  517. soc, msdu_info->tx_queue.desc_pool_id);
  518. if (tso_seg) {
  519. tso_seg->next = tso_info->tso_seg_list;
  520. tso_info->tso_seg_list = tso_seg;
  521. num_seg--;
  522. } else {
  523. dp_err_rl("Failed to alloc tso seg desc");
  524. DP_STATS_INC_PKT(vdev->pdev,
  525. tso_stats.tso_no_mem_dropped, 1,
  526. qdf_nbuf_len(msdu));
  527. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  528. return QDF_STATUS_E_NOMEM;
  529. }
  530. }
  531. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  532. tso_num_seg = dp_tso_num_seg_alloc(soc,
  533. msdu_info->tx_queue.desc_pool_id);
  534. if (tso_num_seg) {
  535. tso_num_seg->next = tso_info->tso_num_seg_list;
  536. tso_info->tso_num_seg_list = tso_num_seg;
  537. } else {
  538. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  539. __func__);
  540. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  541. return QDF_STATUS_E_NOMEM;
  542. }
  543. msdu_info->num_seg =
  544. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  545. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  546. msdu_info->num_seg);
  547. if (!(msdu_info->num_seg)) {
  548. /*
  549. * Free allocated TSO seg desc and number seg desc,
  550. * do unmap for segments if dma map has done.
  551. */
  552. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  553. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  554. return QDF_STATUS_E_INVAL;
  555. }
  556. tso_info->curr_seg = tso_info->tso_seg_list;
  557. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  558. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  559. msdu, msdu_info->num_seg);
  560. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  561. tso_info->msdu_stats_idx);
  562. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  563. return QDF_STATUS_SUCCESS;
  564. }
  565. #else
  566. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  567. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  568. {
  569. return QDF_STATUS_E_NOMEM;
  570. }
  571. #endif
  572. /**
  573. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  574. * @vdev: DP Vdev handle
  575. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  576. * @desc_pool_id: Descriptor Pool ID
  577. *
  578. * Return:
  579. */
  580. static
  581. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  582. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  583. {
  584. uint8_t i;
  585. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  586. struct dp_tx_seg_info_s *seg_info;
  587. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  588. struct dp_soc *soc = vdev->pdev->soc;
  589. /* Allocate an extension descriptor */
  590. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  591. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  592. if (!msdu_ext_desc) {
  593. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  594. return NULL;
  595. }
  596. if (msdu_info->exception_fw &&
  597. qdf_unlikely(vdev->mesh_vdev)) {
  598. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  599. &msdu_info->meta_data[0],
  600. sizeof(struct htt_tx_msdu_desc_ext2_t));
  601. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  602. }
  603. switch (msdu_info->frm_type) {
  604. case dp_tx_frm_sg:
  605. case dp_tx_frm_me:
  606. case dp_tx_frm_raw:
  607. seg_info = msdu_info->u.sg_info.curr_seg;
  608. /* Update the buffer pointers in MSDU Extension Descriptor */
  609. for (i = 0; i < seg_info->frag_cnt; i++) {
  610. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  611. seg_info->frags[i].paddr_lo,
  612. seg_info->frags[i].paddr_hi,
  613. seg_info->frags[i].len);
  614. }
  615. break;
  616. case dp_tx_frm_tso:
  617. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  618. &cached_ext_desc[0]);
  619. break;
  620. default:
  621. break;
  622. }
  623. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  624. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  625. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  626. msdu_ext_desc->vaddr);
  627. return msdu_ext_desc;
  628. }
  629. /**
  630. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  631. *
  632. * @skb: skb to be traced
  633. * @msdu_id: msdu_id of the packet
  634. * @vdev_id: vdev_id of the packet
  635. *
  636. * Return: None
  637. */
  638. #ifdef DP_DISABLE_TX_PKT_TRACE
  639. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  640. uint8_t vdev_id)
  641. {
  642. }
  643. #else
  644. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  645. uint8_t vdev_id)
  646. {
  647. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  648. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  649. DPTRACE(qdf_dp_trace_ptr(skb,
  650. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  651. QDF_TRACE_DEFAULT_PDEV_ID,
  652. qdf_nbuf_data_addr(skb),
  653. sizeof(qdf_nbuf_data(skb)),
  654. msdu_id, vdev_id));
  655. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  656. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  657. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  658. msdu_id, QDF_TX));
  659. }
  660. #endif
  661. /**
  662. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  663. * @vdev: DP vdev handle
  664. * @nbuf: skb
  665. * @desc_pool_id: Descriptor pool ID
  666. * @meta_data: Metadata to the fw
  667. * @tx_exc_metadata: Handle that holds exception path metadata
  668. * Allocate and prepare Tx descriptor with msdu information.
  669. *
  670. * Return: Pointer to Tx Descriptor on success,
  671. * NULL on failure
  672. */
  673. static
  674. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  675. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  676. struct dp_tx_msdu_info_s *msdu_info,
  677. struct cdp_tx_exception_metadata *tx_exc_metadata)
  678. {
  679. uint8_t align_pad;
  680. uint8_t is_exception = 0;
  681. uint8_t htt_hdr_size;
  682. struct dp_tx_desc_s *tx_desc;
  683. struct dp_pdev *pdev = vdev->pdev;
  684. struct dp_soc *soc = pdev->soc;
  685. if (dp_tx_limit_check(vdev))
  686. return NULL;
  687. /* Allocate software Tx descriptor */
  688. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  689. if (qdf_unlikely(!tx_desc)) {
  690. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  691. return NULL;
  692. }
  693. dp_tx_outstanding_inc(pdev);
  694. /* Initialize the SW tx descriptor */
  695. tx_desc->nbuf = nbuf;
  696. tx_desc->frm_type = dp_tx_frm_std;
  697. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  698. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  699. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  700. tx_desc->vdev = vdev;
  701. tx_desc->pdev = pdev;
  702. tx_desc->msdu_ext_desc = NULL;
  703. tx_desc->pkt_offset = 0;
  704. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  705. if (qdf_unlikely(vdev->multipass_en)) {
  706. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  707. goto failure;
  708. }
  709. /*
  710. * For special modes (vdev_type == ocb or mesh), data frames should be
  711. * transmitted using varying transmit parameters (tx spec) which include
  712. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  713. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  714. * These frames are sent as exception packets to firmware.
  715. *
  716. * HW requirement is that metadata should always point to a
  717. * 8-byte aligned address. So we add alignment pad to start of buffer.
  718. * HTT Metadata should be ensured to be multiple of 8-bytes,
  719. * to get 8-byte aligned start address along with align_pad added
  720. *
  721. * |-----------------------------|
  722. * | |
  723. * |-----------------------------| <-----Buffer Pointer Address given
  724. * | | ^ in HW descriptor (aligned)
  725. * | HTT Metadata | |
  726. * | | |
  727. * | | | Packet Offset given in descriptor
  728. * | | |
  729. * |-----------------------------| |
  730. * | Alignment Pad | v
  731. * |-----------------------------| <----- Actual buffer start address
  732. * | SKB Data | (Unaligned)
  733. * | |
  734. * | |
  735. * | |
  736. * | |
  737. * | |
  738. * |-----------------------------|
  739. */
  740. if (qdf_unlikely((msdu_info->exception_fw)) ||
  741. (vdev->opmode == wlan_op_mode_ocb) ||
  742. (tx_exc_metadata &&
  743. tx_exc_metadata->is_tx_sniffer)) {
  744. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  745. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  746. DP_STATS_INC(vdev,
  747. tx_i.dropped.headroom_insufficient, 1);
  748. goto failure;
  749. }
  750. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  751. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  752. "qdf_nbuf_push_head failed");
  753. goto failure;
  754. }
  755. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  756. msdu_info);
  757. if (htt_hdr_size == 0)
  758. goto failure;
  759. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  760. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  761. is_exception = 1;
  762. }
  763. #if !TQM_BYPASS_WAR
  764. if (is_exception || tx_exc_metadata)
  765. #endif
  766. {
  767. /* Temporary WAR due to TQM VP issues */
  768. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  769. qdf_atomic_inc(&pdev->num_tx_exception);
  770. }
  771. return tx_desc;
  772. failure:
  773. dp_tx_desc_release(tx_desc, desc_pool_id);
  774. return NULL;
  775. }
  776. /**
  777. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  778. * @vdev: DP vdev handle
  779. * @nbuf: skb
  780. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  781. * @desc_pool_id : Descriptor Pool ID
  782. *
  783. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  784. * information. For frames wth fragments, allocate and prepare
  785. * an MSDU extension descriptor
  786. *
  787. * Return: Pointer to Tx Descriptor on success,
  788. * NULL on failure
  789. */
  790. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  791. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  792. uint8_t desc_pool_id)
  793. {
  794. struct dp_tx_desc_s *tx_desc;
  795. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  796. struct dp_pdev *pdev = vdev->pdev;
  797. struct dp_soc *soc = pdev->soc;
  798. if (dp_tx_limit_check(vdev))
  799. return NULL;
  800. /* Allocate software Tx descriptor */
  801. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  802. if (!tx_desc) {
  803. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  804. return NULL;
  805. }
  806. dp_tx_outstanding_inc(pdev);
  807. /* Initialize the SW tx descriptor */
  808. tx_desc->nbuf = nbuf;
  809. tx_desc->frm_type = msdu_info->frm_type;
  810. tx_desc->tx_encap_type = vdev->tx_encap_type;
  811. tx_desc->vdev = vdev;
  812. tx_desc->pdev = pdev;
  813. tx_desc->pkt_offset = 0;
  814. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  815. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  816. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  817. /* Handle scattered frames - TSO/SG/ME */
  818. /* Allocate and prepare an extension descriptor for scattered frames */
  819. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  820. if (!msdu_ext_desc) {
  821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  822. "%s Tx Extension Descriptor Alloc Fail",
  823. __func__);
  824. goto failure;
  825. }
  826. #if TQM_BYPASS_WAR
  827. /* Temporary WAR due to TQM VP issues */
  828. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  829. qdf_atomic_inc(&pdev->num_tx_exception);
  830. #endif
  831. if (qdf_unlikely(msdu_info->exception_fw))
  832. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  833. tx_desc->msdu_ext_desc = msdu_ext_desc;
  834. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  835. return tx_desc;
  836. failure:
  837. dp_tx_desc_release(tx_desc, desc_pool_id);
  838. return NULL;
  839. }
  840. /**
  841. * dp_tx_prepare_raw() - Prepare RAW packet TX
  842. * @vdev: DP vdev handle
  843. * @nbuf: buffer pointer
  844. * @seg_info: Pointer to Segment info Descriptor to be prepared
  845. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  846. * descriptor
  847. *
  848. * Return:
  849. */
  850. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  851. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  852. {
  853. qdf_nbuf_t curr_nbuf = NULL;
  854. uint16_t total_len = 0;
  855. qdf_dma_addr_t paddr;
  856. int32_t i;
  857. int32_t mapped_buf_num = 0;
  858. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  859. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  860. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  861. /* Continue only if frames are of DATA type */
  862. if (!DP_FRAME_IS_DATA(qos_wh)) {
  863. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  864. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  865. "Pkt. recd is of not data type");
  866. goto error;
  867. }
  868. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  869. if (vdev->raw_mode_war &&
  870. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  871. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  872. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  873. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  874. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  875. if (QDF_STATUS_SUCCESS !=
  876. qdf_nbuf_map_nbytes_single(vdev->osdev,
  877. curr_nbuf,
  878. QDF_DMA_TO_DEVICE,
  879. curr_nbuf->len)) {
  880. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  881. "%s dma map error ", __func__);
  882. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  883. mapped_buf_num = i;
  884. goto error;
  885. }
  886. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  887. seg_info->frags[i].paddr_lo = paddr;
  888. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  889. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  890. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  891. total_len += qdf_nbuf_len(curr_nbuf);
  892. }
  893. seg_info->frag_cnt = i;
  894. seg_info->total_len = total_len;
  895. seg_info->next = NULL;
  896. sg_info->curr_seg = seg_info;
  897. msdu_info->frm_type = dp_tx_frm_raw;
  898. msdu_info->num_seg = 1;
  899. return nbuf;
  900. error:
  901. i = 0;
  902. while (nbuf) {
  903. curr_nbuf = nbuf;
  904. if (i < mapped_buf_num) {
  905. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  906. QDF_DMA_TO_DEVICE,
  907. curr_nbuf->len);
  908. i++;
  909. }
  910. nbuf = qdf_nbuf_next(nbuf);
  911. qdf_nbuf_free(curr_nbuf);
  912. }
  913. return NULL;
  914. }
  915. /**
  916. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  917. * @soc: DP soc handle
  918. * @nbuf: Buffer pointer
  919. *
  920. * unmap the chain of nbufs that belong to this RAW frame.
  921. *
  922. * Return: None
  923. */
  924. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  925. qdf_nbuf_t nbuf)
  926. {
  927. qdf_nbuf_t cur_nbuf = nbuf;
  928. do {
  929. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  930. QDF_DMA_TO_DEVICE,
  931. cur_nbuf->len);
  932. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  933. } while (cur_nbuf);
  934. }
  935. #ifdef VDEV_PEER_PROTOCOL_COUNT
  936. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  937. { \
  938. qdf_nbuf_t nbuf_local; \
  939. struct dp_vdev *vdev_local = vdev_hdl; \
  940. do { \
  941. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  942. break; \
  943. nbuf_local = nbuf; \
  944. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  945. htt_cmn_pkt_type_raw)) \
  946. break; \
  947. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  948. break; \
  949. else if (qdf_nbuf_is_tso((nbuf_local))) \
  950. break; \
  951. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  952. (nbuf_local), \
  953. NULL, 1, 0); \
  954. } while (0); \
  955. }
  956. #else
  957. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  958. #endif
  959. /**
  960. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  961. * @soc: DP Soc Handle
  962. * @vdev: DP vdev handle
  963. * @tx_desc: Tx Descriptor Handle
  964. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  965. * @fw_metadata: Metadata to send to Target Firmware along with frame
  966. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  967. * @tx_exc_metadata: Handle that holds exception path meta data
  968. *
  969. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  970. * from software Tx descriptor
  971. *
  972. * Return: QDF_STATUS_SUCCESS: success
  973. * QDF_STATUS_E_RESOURCES: Error return
  974. */
  975. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  976. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  977. uint16_t fw_metadata, uint8_t ring_id,
  978. struct cdp_tx_exception_metadata
  979. *tx_exc_metadata)
  980. {
  981. uint8_t type;
  982. uint16_t length;
  983. void *hal_tx_desc;
  984. uint32_t *hal_tx_desc_cached;
  985. qdf_dma_addr_t dma_addr;
  986. /*
  987. * Setting it initialization statically here to avoid
  988. * a memset call jump with qdf_mem_set call
  989. */
  990. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  991. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  992. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  993. tx_exc_metadata->sec_type : vdev->sec_type);
  994. /* Return Buffer Manager ID */
  995. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  996. hal_ring_handle_t hal_ring_hdl = NULL;
  997. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  998. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  999. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1000. return QDF_STATUS_E_RESOURCES;
  1001. }
  1002. hal_tx_desc_cached = (void *) cached_desc;
  1003. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1004. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1005. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1006. dma_addr = tx_desc->msdu_ext_desc->paddr;
  1007. } else {
  1008. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  1009. type = HAL_TX_BUF_TYPE_BUFFER;
  1010. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1011. }
  1012. qdf_assert_always(dma_addr);
  1013. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1014. dma_addr, bm_id, tx_desc->id,
  1015. type);
  1016. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1017. vdev->lmac_id);
  1018. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1019. vdev->search_type);
  1020. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1021. vdev->bss_ast_idx);
  1022. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1023. vdev->dscp_tid_map_id);
  1024. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1025. sec_type_map[sec_type]);
  1026. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1027. (vdev->bss_ast_hash & 0xF));
  1028. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1029. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  1030. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1031. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1032. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1033. vdev->hal_desc_addr_search_flags);
  1034. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1035. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1036. /* verify checksum offload configuration*/
  1037. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1038. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1039. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1040. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1041. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1042. }
  1043. if (tid != HTT_TX_EXT_TID_INVALID)
  1044. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1045. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1046. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1047. if (qdf_unlikely(vdev->pdev->delay_stats_flag))
  1048. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1049. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1050. length, type, (uint64_t)dma_addr,
  1051. tx_desc->pkt_offset, tx_desc->id);
  1052. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1053. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1054. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1055. "%s %d : HAL RING Access Failed -- %pK",
  1056. __func__, __LINE__, hal_ring_hdl);
  1057. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1058. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1059. return status;
  1060. }
  1061. /* Sync cached descriptor with HW */
  1062. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1063. if (qdf_unlikely(!hal_tx_desc)) {
  1064. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1065. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1066. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1067. goto ring_access_fail;
  1068. }
  1069. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1070. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1071. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1072. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1073. status = QDF_STATUS_SUCCESS;
  1074. ring_access_fail:
  1075. if (hif_pm_runtime_get(soc->hif_handle,
  1076. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1077. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1078. hif_pm_runtime_put(soc->hif_handle,
  1079. RTPM_ID_DW_TX_HW_ENQUEUE);
  1080. } else {
  1081. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1082. }
  1083. return status;
  1084. }
  1085. /**
  1086. * dp_cce_classify() - Classify the frame based on CCE rules
  1087. * @vdev: DP vdev handle
  1088. * @nbuf: skb
  1089. *
  1090. * Classify frames based on CCE rules
  1091. * Return: bool( true if classified,
  1092. * else false)
  1093. */
  1094. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1095. {
  1096. qdf_ether_header_t *eh = NULL;
  1097. uint16_t ether_type;
  1098. qdf_llc_t *llcHdr;
  1099. qdf_nbuf_t nbuf_clone = NULL;
  1100. qdf_dot3_qosframe_t *qos_wh = NULL;
  1101. /* for mesh packets don't do any classification */
  1102. if (qdf_unlikely(vdev->mesh_vdev))
  1103. return false;
  1104. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1105. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1106. ether_type = eh->ether_type;
  1107. llcHdr = (qdf_llc_t *)(nbuf->data +
  1108. sizeof(qdf_ether_header_t));
  1109. } else {
  1110. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1111. /* For encrypted packets don't do any classification */
  1112. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1113. return false;
  1114. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1115. if (qdf_unlikely(
  1116. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1117. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1118. ether_type = *(uint16_t *)(nbuf->data
  1119. + QDF_IEEE80211_4ADDR_HDR_LEN
  1120. + sizeof(qdf_llc_t)
  1121. - sizeof(ether_type));
  1122. llcHdr = (qdf_llc_t *)(nbuf->data +
  1123. QDF_IEEE80211_4ADDR_HDR_LEN);
  1124. } else {
  1125. ether_type = *(uint16_t *)(nbuf->data
  1126. + QDF_IEEE80211_3ADDR_HDR_LEN
  1127. + sizeof(qdf_llc_t)
  1128. - sizeof(ether_type));
  1129. llcHdr = (qdf_llc_t *)(nbuf->data +
  1130. QDF_IEEE80211_3ADDR_HDR_LEN);
  1131. }
  1132. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1133. && (ether_type ==
  1134. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1135. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1136. return true;
  1137. }
  1138. }
  1139. return false;
  1140. }
  1141. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1142. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1143. sizeof(*llcHdr));
  1144. nbuf_clone = qdf_nbuf_clone(nbuf);
  1145. if (qdf_unlikely(nbuf_clone)) {
  1146. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1147. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1148. qdf_nbuf_pull_head(nbuf_clone,
  1149. sizeof(qdf_net_vlanhdr_t));
  1150. }
  1151. }
  1152. } else {
  1153. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1154. nbuf_clone = qdf_nbuf_clone(nbuf);
  1155. if (qdf_unlikely(nbuf_clone)) {
  1156. qdf_nbuf_pull_head(nbuf_clone,
  1157. sizeof(qdf_net_vlanhdr_t));
  1158. }
  1159. }
  1160. }
  1161. if (qdf_unlikely(nbuf_clone))
  1162. nbuf = nbuf_clone;
  1163. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1164. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1165. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1166. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1167. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1168. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1169. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1170. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1171. if (qdf_unlikely(nbuf_clone))
  1172. qdf_nbuf_free(nbuf_clone);
  1173. return true;
  1174. }
  1175. if (qdf_unlikely(nbuf_clone))
  1176. qdf_nbuf_free(nbuf_clone);
  1177. return false;
  1178. }
  1179. /**
  1180. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1181. * @vdev: DP vdev handle
  1182. * @nbuf: skb
  1183. *
  1184. * Extract the DSCP or PCP information from frame and map into TID value.
  1185. *
  1186. * Return: void
  1187. */
  1188. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1189. struct dp_tx_msdu_info_s *msdu_info)
  1190. {
  1191. uint8_t tos = 0, dscp_tid_override = 0;
  1192. uint8_t *hdr_ptr, *L3datap;
  1193. uint8_t is_mcast = 0;
  1194. qdf_ether_header_t *eh = NULL;
  1195. qdf_ethervlan_header_t *evh = NULL;
  1196. uint16_t ether_type;
  1197. qdf_llc_t *llcHdr;
  1198. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1199. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1200. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1201. eh = (qdf_ether_header_t *)nbuf->data;
  1202. hdr_ptr = eh->ether_dhost;
  1203. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1204. } else {
  1205. qdf_dot3_qosframe_t *qos_wh =
  1206. (qdf_dot3_qosframe_t *) nbuf->data;
  1207. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1208. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1209. return;
  1210. }
  1211. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1212. ether_type = eh->ether_type;
  1213. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1214. /*
  1215. * Check if packet is dot3 or eth2 type.
  1216. */
  1217. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1218. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1219. sizeof(*llcHdr));
  1220. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1221. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1222. sizeof(*llcHdr);
  1223. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1224. + sizeof(*llcHdr) +
  1225. sizeof(qdf_net_vlanhdr_t));
  1226. } else {
  1227. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1228. sizeof(*llcHdr);
  1229. }
  1230. } else {
  1231. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1232. evh = (qdf_ethervlan_header_t *) eh;
  1233. ether_type = evh->ether_type;
  1234. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1235. }
  1236. }
  1237. /*
  1238. * Find priority from IP TOS DSCP field
  1239. */
  1240. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1241. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1242. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1243. /* Only for unicast frames */
  1244. if (!is_mcast) {
  1245. /* send it on VO queue */
  1246. msdu_info->tid = DP_VO_TID;
  1247. }
  1248. } else {
  1249. /*
  1250. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1251. * from TOS byte.
  1252. */
  1253. tos = ip->ip_tos;
  1254. dscp_tid_override = 1;
  1255. }
  1256. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1257. /* TODO
  1258. * use flowlabel
  1259. *igmpmld cases to be handled in phase 2
  1260. */
  1261. unsigned long ver_pri_flowlabel;
  1262. unsigned long pri;
  1263. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1264. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1265. DP_IPV6_PRIORITY_SHIFT;
  1266. tos = pri;
  1267. dscp_tid_override = 1;
  1268. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1269. msdu_info->tid = DP_VO_TID;
  1270. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1271. /* Only for unicast frames */
  1272. if (!is_mcast) {
  1273. /* send ucast arp on VO queue */
  1274. msdu_info->tid = DP_VO_TID;
  1275. }
  1276. }
  1277. /*
  1278. * Assign all MCAST packets to BE
  1279. */
  1280. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1281. if (is_mcast) {
  1282. tos = 0;
  1283. dscp_tid_override = 1;
  1284. }
  1285. }
  1286. if (dscp_tid_override == 1) {
  1287. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1288. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1289. }
  1290. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1291. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1292. return;
  1293. }
  1294. /**
  1295. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1296. * @vdev: DP vdev handle
  1297. * @nbuf: skb
  1298. *
  1299. * Software based TID classification is required when more than 2 DSCP-TID
  1300. * mapping tables are needed.
  1301. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1302. *
  1303. * Return: void
  1304. */
  1305. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1306. struct dp_tx_msdu_info_s *msdu_info)
  1307. {
  1308. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1309. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1310. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1311. return;
  1312. /* for mesh packets don't do any classification */
  1313. if (qdf_unlikely(vdev->mesh_vdev))
  1314. return;
  1315. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1316. }
  1317. #ifdef FEATURE_WLAN_TDLS
  1318. /**
  1319. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1320. * @tx_desc: TX descriptor
  1321. *
  1322. * Return: None
  1323. */
  1324. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1325. {
  1326. if (tx_desc->vdev) {
  1327. if (tx_desc->vdev->is_tdls_frame) {
  1328. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1329. tx_desc->vdev->is_tdls_frame = false;
  1330. }
  1331. }
  1332. }
  1333. /**
  1334. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1335. * @tx_desc: TX descriptor
  1336. * @vdev: datapath vdev handle
  1337. *
  1338. * Return: None
  1339. */
  1340. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1341. struct dp_vdev *vdev)
  1342. {
  1343. struct hal_tx_completion_status ts = {0};
  1344. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1345. if (qdf_unlikely(!vdev)) {
  1346. dp_err("vdev is null!");
  1347. return;
  1348. }
  1349. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1350. if (vdev->tx_non_std_data_callback.func) {
  1351. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1352. vdev->tx_non_std_data_callback.func(
  1353. vdev->tx_non_std_data_callback.ctxt,
  1354. nbuf, ts.status);
  1355. return;
  1356. }
  1357. }
  1358. #else
  1359. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1360. {
  1361. }
  1362. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1363. struct dp_vdev *vdev)
  1364. {
  1365. }
  1366. #endif
  1367. /**
  1368. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1369. * @vdev: DP vdev handle
  1370. * @nbuf: skb
  1371. *
  1372. * Return: 1 if frame needs to be dropped else 0
  1373. */
  1374. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1375. {
  1376. struct dp_pdev *pdev = NULL;
  1377. struct dp_ast_entry *src_ast_entry = NULL;
  1378. struct dp_ast_entry *dst_ast_entry = NULL;
  1379. struct dp_soc *soc = NULL;
  1380. qdf_assert(vdev);
  1381. pdev = vdev->pdev;
  1382. qdf_assert(pdev);
  1383. soc = pdev->soc;
  1384. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1385. (soc, dstmac, vdev->pdev->pdev_id);
  1386. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1387. (soc, srcmac, vdev->pdev->pdev_id);
  1388. if (dst_ast_entry && src_ast_entry) {
  1389. if (dst_ast_entry->peer->peer_ids[0] ==
  1390. src_ast_entry->peer->peer_ids[0])
  1391. return 1;
  1392. }
  1393. return 0;
  1394. }
  1395. /**
  1396. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1397. * @vdev: DP vdev handle
  1398. * @nbuf: skb
  1399. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1400. * @meta_data: Metadata to the fw
  1401. * @tx_q: Tx queue to be used for this Tx frame
  1402. * @peer_id: peer_id of the peer in case of NAWDS frames
  1403. * @tx_exc_metadata: Handle that holds exception path metadata
  1404. *
  1405. * Return: NULL on success,
  1406. * nbuf when it fails to send
  1407. */
  1408. qdf_nbuf_t
  1409. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1410. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1411. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1412. {
  1413. struct dp_pdev *pdev = vdev->pdev;
  1414. struct dp_soc *soc = pdev->soc;
  1415. struct dp_tx_desc_s *tx_desc;
  1416. QDF_STATUS status;
  1417. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1418. uint16_t htt_tcl_metadata = 0;
  1419. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1420. uint8_t tid = msdu_info->tid;
  1421. struct cdp_tid_tx_stats *tid_stats = NULL;
  1422. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1423. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1424. msdu_info, tx_exc_metadata);
  1425. if (!tx_desc) {
  1426. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1427. vdev, tx_q->desc_pool_id);
  1428. drop_code = TX_DESC_ERR;
  1429. goto fail_return;
  1430. }
  1431. if (qdf_unlikely(soc->cce_disable)) {
  1432. if (dp_cce_classify(vdev, nbuf) == true) {
  1433. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1434. tid = DP_VO_TID;
  1435. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1436. }
  1437. }
  1438. dp_tx_update_tdls_flags(tx_desc);
  1439. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1440. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1441. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1442. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1443. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1444. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1445. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1446. peer_id);
  1447. } else
  1448. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1449. if (msdu_info->exception_fw)
  1450. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1451. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1452. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1453. QDF_DMA_TO_DEVICE, nbuf->len))) {
  1454. /* Handle failure */
  1455. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1456. "qdf_nbuf_map failed");
  1457. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1458. drop_code = TX_DMA_MAP_ERR;
  1459. goto release_desc;
  1460. }
  1461. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1462. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1463. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1464. if (status != QDF_STATUS_SUCCESS) {
  1465. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1466. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1467. __func__, tx_desc, tx_q->ring_id);
  1468. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1469. QDF_DMA_TO_DEVICE,
  1470. nbuf->len);
  1471. drop_code = TX_HW_ENQUEUE;
  1472. goto release_desc;
  1473. }
  1474. return NULL;
  1475. release_desc:
  1476. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1477. fail_return:
  1478. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1479. tid_stats = &pdev->stats.tid_stats.
  1480. tid_tx_stats[tx_q->ring_id][tid];
  1481. tid_stats->swdrop_cnt[drop_code]++;
  1482. return nbuf;
  1483. }
  1484. /**
  1485. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1486. * @vdev: DP vdev handle
  1487. * @nbuf: skb
  1488. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1489. *
  1490. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1491. *
  1492. * Return: NULL on success,
  1493. * nbuf when it fails to send
  1494. */
  1495. #if QDF_LOCK_STATS
  1496. noinline
  1497. #else
  1498. #endif
  1499. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1500. struct dp_tx_msdu_info_s *msdu_info)
  1501. {
  1502. uint8_t i;
  1503. struct dp_pdev *pdev = vdev->pdev;
  1504. struct dp_soc *soc = pdev->soc;
  1505. struct dp_tx_desc_s *tx_desc;
  1506. bool is_cce_classified = false;
  1507. QDF_STATUS status;
  1508. uint16_t htt_tcl_metadata = 0;
  1509. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1510. struct cdp_tid_tx_stats *tid_stats = NULL;
  1511. if (qdf_unlikely(soc->cce_disable)) {
  1512. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1513. if (is_cce_classified) {
  1514. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1515. msdu_info->tid = DP_VO_TID;
  1516. }
  1517. }
  1518. if (msdu_info->frm_type == dp_tx_frm_me)
  1519. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1520. i = 0;
  1521. /* Print statement to track i and num_seg */
  1522. /*
  1523. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1524. * descriptors using information in msdu_info
  1525. */
  1526. while (i < msdu_info->num_seg) {
  1527. /*
  1528. * Setup Tx descriptor for an MSDU, and MSDU extension
  1529. * descriptor
  1530. */
  1531. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1532. tx_q->desc_pool_id);
  1533. if (!tx_desc) {
  1534. if (msdu_info->frm_type == dp_tx_frm_me) {
  1535. dp_tx_me_free_buf(pdev,
  1536. (void *)(msdu_info->u.sg_info
  1537. .curr_seg->frags[0].vaddr));
  1538. i++;
  1539. continue;
  1540. }
  1541. goto done;
  1542. }
  1543. if (msdu_info->frm_type == dp_tx_frm_me) {
  1544. tx_desc->me_buffer =
  1545. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1546. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1547. }
  1548. if (is_cce_classified)
  1549. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1550. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1551. if (msdu_info->exception_fw) {
  1552. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1553. }
  1554. /*
  1555. * Enqueue the Tx MSDU descriptor to HW for transmit
  1556. */
  1557. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1558. htt_tcl_metadata, tx_q->ring_id, NULL);
  1559. if (status != QDF_STATUS_SUCCESS) {
  1560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1561. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1562. __func__, tx_desc, tx_q->ring_id);
  1563. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1564. tid_stats = &pdev->stats.tid_stats.
  1565. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1566. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1567. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1568. if (msdu_info->frm_type == dp_tx_frm_me) {
  1569. i++;
  1570. continue;
  1571. }
  1572. goto done;
  1573. }
  1574. /*
  1575. * TODO
  1576. * if tso_info structure can be modified to have curr_seg
  1577. * as first element, following 2 blocks of code (for TSO and SG)
  1578. * can be combined into 1
  1579. */
  1580. /*
  1581. * For frames with multiple segments (TSO, ME), jump to next
  1582. * segment.
  1583. */
  1584. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1585. if (msdu_info->u.tso_info.curr_seg->next) {
  1586. msdu_info->u.tso_info.curr_seg =
  1587. msdu_info->u.tso_info.curr_seg->next;
  1588. /*
  1589. * If this is a jumbo nbuf, then increment the number of
  1590. * nbuf users for each additional segment of the msdu.
  1591. * This will ensure that the skb is freed only after
  1592. * receiving tx completion for all segments of an nbuf
  1593. */
  1594. qdf_nbuf_inc_users(nbuf);
  1595. /* Check with MCL if this is needed */
  1596. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1597. }
  1598. }
  1599. /*
  1600. * For Multicast-Unicast converted packets,
  1601. * each converted frame (for a client) is represented as
  1602. * 1 segment
  1603. */
  1604. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1605. (msdu_info->frm_type == dp_tx_frm_me)) {
  1606. if (msdu_info->u.sg_info.curr_seg->next) {
  1607. msdu_info->u.sg_info.curr_seg =
  1608. msdu_info->u.sg_info.curr_seg->next;
  1609. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1610. }
  1611. }
  1612. i++;
  1613. }
  1614. nbuf = NULL;
  1615. done:
  1616. return nbuf;
  1617. }
  1618. /**
  1619. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1620. * for SG frames
  1621. * @vdev: DP vdev handle
  1622. * @nbuf: skb
  1623. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1624. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1625. *
  1626. * Return: NULL on success,
  1627. * nbuf when it fails to send
  1628. */
  1629. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1630. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1631. {
  1632. uint32_t cur_frag, nr_frags;
  1633. qdf_dma_addr_t paddr;
  1634. struct dp_tx_sg_info_s *sg_info;
  1635. sg_info = &msdu_info->u.sg_info;
  1636. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1637. if (QDF_STATUS_SUCCESS !=
  1638. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1639. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1641. "dma map error");
  1642. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1643. qdf_nbuf_free(nbuf);
  1644. return NULL;
  1645. }
  1646. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1647. seg_info->frags[0].paddr_lo = paddr;
  1648. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1649. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1650. seg_info->frags[0].vaddr = (void *) nbuf;
  1651. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1652. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1653. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1655. "frag dma map error");
  1656. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1657. qdf_nbuf_free(nbuf);
  1658. return NULL;
  1659. }
  1660. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1661. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1662. seg_info->frags[cur_frag + 1].paddr_hi =
  1663. ((uint64_t) paddr) >> 32;
  1664. seg_info->frags[cur_frag + 1].len =
  1665. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1666. }
  1667. seg_info->frag_cnt = (cur_frag + 1);
  1668. seg_info->total_len = qdf_nbuf_len(nbuf);
  1669. seg_info->next = NULL;
  1670. sg_info->curr_seg = seg_info;
  1671. msdu_info->frm_type = dp_tx_frm_sg;
  1672. msdu_info->num_seg = 1;
  1673. return nbuf;
  1674. }
  1675. /**
  1676. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1677. * @vdev: DP vdev handle
  1678. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1679. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1680. *
  1681. * Return: NULL on failure,
  1682. * nbuf when extracted successfully
  1683. */
  1684. static
  1685. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1686. struct dp_tx_msdu_info_s *msdu_info,
  1687. uint16_t ppdu_cookie)
  1688. {
  1689. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1690. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1691. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1692. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1693. (msdu_info->meta_data[5], 1);
  1694. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1695. (msdu_info->meta_data[5], 1);
  1696. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1697. (msdu_info->meta_data[6], ppdu_cookie);
  1698. msdu_info->exception_fw = 1;
  1699. msdu_info->is_tx_sniffer = 1;
  1700. }
  1701. #ifdef MESH_MODE_SUPPORT
  1702. /**
  1703. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1704. and prepare msdu_info for mesh frames.
  1705. * @vdev: DP vdev handle
  1706. * @nbuf: skb
  1707. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1708. *
  1709. * Return: NULL on failure,
  1710. * nbuf when extracted successfully
  1711. */
  1712. static
  1713. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1714. struct dp_tx_msdu_info_s *msdu_info)
  1715. {
  1716. struct meta_hdr_s *mhdr;
  1717. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1718. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1719. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1720. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1721. msdu_info->exception_fw = 0;
  1722. goto remove_meta_hdr;
  1723. }
  1724. msdu_info->exception_fw = 1;
  1725. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1726. meta_data->host_tx_desc_pool = 1;
  1727. meta_data->update_peer_cache = 1;
  1728. meta_data->learning_frame = 1;
  1729. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1730. meta_data->power = mhdr->power;
  1731. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1732. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1733. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1734. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1735. meta_data->dyn_bw = 1;
  1736. meta_data->valid_pwr = 1;
  1737. meta_data->valid_mcs_mask = 1;
  1738. meta_data->valid_nss_mask = 1;
  1739. meta_data->valid_preamble_type = 1;
  1740. meta_data->valid_retries = 1;
  1741. meta_data->valid_bw_info = 1;
  1742. }
  1743. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1744. meta_data->encrypt_type = 0;
  1745. meta_data->valid_encrypt_type = 1;
  1746. meta_data->learning_frame = 0;
  1747. }
  1748. meta_data->valid_key_flags = 1;
  1749. meta_data->key_flags = (mhdr->keyix & 0x3);
  1750. remove_meta_hdr:
  1751. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1752. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1753. "qdf_nbuf_pull_head failed");
  1754. qdf_nbuf_free(nbuf);
  1755. return NULL;
  1756. }
  1757. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1758. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1759. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1760. " tid %d to_fw %d",
  1761. __func__, msdu_info->meta_data[0],
  1762. msdu_info->meta_data[1],
  1763. msdu_info->meta_data[2],
  1764. msdu_info->meta_data[3],
  1765. msdu_info->meta_data[4],
  1766. msdu_info->meta_data[5],
  1767. msdu_info->tid, msdu_info->exception_fw);
  1768. return nbuf;
  1769. }
  1770. #else
  1771. static
  1772. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1773. struct dp_tx_msdu_info_s *msdu_info)
  1774. {
  1775. return nbuf;
  1776. }
  1777. #endif
  1778. /**
  1779. * dp_check_exc_metadata() - Checks if parameters are valid
  1780. * @tx_exc - holds all exception path parameters
  1781. *
  1782. * Returns true when all the parameters are valid else false
  1783. *
  1784. */
  1785. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1786. {
  1787. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1788. HTT_INVALID_TID);
  1789. bool invalid_encap_type =
  1790. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1791. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1792. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1793. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1794. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1795. tx_exc->ppdu_cookie == 0);
  1796. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1797. invalid_cookie) {
  1798. return false;
  1799. }
  1800. return true;
  1801. }
  1802. /**
  1803. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1804. * @soc: DP soc handle
  1805. * @vdev_id: id of DP vdev handle
  1806. * @nbuf: skb
  1807. * @tx_exc_metadata: Handle that holds exception path meta data
  1808. *
  1809. * Entry point for Core Tx layer (DP_TX) invoked from
  1810. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1811. *
  1812. * Return: NULL on success,
  1813. * nbuf when it fails to send
  1814. */
  1815. qdf_nbuf_t
  1816. dp_tx_send_exception(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf,
  1817. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1818. {
  1819. qdf_ether_header_t *eh = NULL;
  1820. struct dp_tx_msdu_info_s msdu_info;
  1821. struct dp_vdev *vdev =
  1822. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1823. vdev_id);
  1824. if (qdf_unlikely(!vdev))
  1825. goto fail;
  1826. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1827. if (!tx_exc_metadata)
  1828. goto fail;
  1829. msdu_info.tid = tx_exc_metadata->tid;
  1830. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1831. dp_verbose_debug("skb %pM", nbuf->data);
  1832. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1833. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1834. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1835. "Invalid parameters in exception path");
  1836. goto fail;
  1837. }
  1838. /* Basic sanity checks for unsupported packets */
  1839. /* MESH mode */
  1840. if (qdf_unlikely(vdev->mesh_vdev)) {
  1841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1842. "Mesh mode is not supported in exception path");
  1843. goto fail;
  1844. }
  1845. /* TSO or SG */
  1846. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1847. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1848. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1849. "TSO and SG are not supported in exception path");
  1850. goto fail;
  1851. }
  1852. /* RAW */
  1853. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1854. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1855. "Raw frame is not supported in exception path");
  1856. goto fail;
  1857. }
  1858. /* Mcast enhancement*/
  1859. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1860. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1861. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1862. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1863. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1864. }
  1865. }
  1866. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1867. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1868. qdf_nbuf_len(nbuf));
  1869. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1870. tx_exc_metadata->ppdu_cookie);
  1871. }
  1872. /*
  1873. * Get HW Queue to use for this frame.
  1874. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1875. * dedicated for data and 1 for command.
  1876. * "queue_id" maps to one hardware ring.
  1877. * With each ring, we also associate a unique Tx descriptor pool
  1878. * to minimize lock contention for these resources.
  1879. */
  1880. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1881. /* Single linear frame */
  1882. /*
  1883. * If nbuf is a simple linear frame, use send_single function to
  1884. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1885. * SRNG. There is no need to setup a MSDU extension descriptor.
  1886. */
  1887. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1888. tx_exc_metadata->peer_id, tx_exc_metadata);
  1889. return nbuf;
  1890. fail:
  1891. dp_verbose_debug("pkt send failed");
  1892. return nbuf;
  1893. }
  1894. /**
  1895. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1896. * @soc: DP soc handle
  1897. * @vdev_id: DP vdev handle
  1898. * @nbuf: skb
  1899. *
  1900. * Entry point for Core Tx layer (DP_TX) invoked from
  1901. * hard_start_xmit in OSIF/HDD
  1902. *
  1903. * Return: NULL on success,
  1904. * nbuf when it fails to send
  1905. */
  1906. #ifdef MESH_MODE_SUPPORT
  1907. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1908. qdf_nbuf_t nbuf)
  1909. {
  1910. struct meta_hdr_s *mhdr;
  1911. qdf_nbuf_t nbuf_mesh = NULL;
  1912. qdf_nbuf_t nbuf_clone = NULL;
  1913. struct dp_vdev *vdev;
  1914. uint8_t no_enc_frame = 0;
  1915. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1916. if (!nbuf_mesh) {
  1917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1918. "qdf_nbuf_unshare failed");
  1919. return nbuf;
  1920. }
  1921. vdev = dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1922. vdev_id);
  1923. if (!vdev) {
  1924. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1925. "vdev is NULL for vdev_id %d", vdev_id);
  1926. return nbuf;
  1927. }
  1928. nbuf = nbuf_mesh;
  1929. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1930. if ((vdev->sec_type != cdp_sec_type_none) &&
  1931. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1932. no_enc_frame = 1;
  1933. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1934. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1935. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1936. !no_enc_frame) {
  1937. nbuf_clone = qdf_nbuf_clone(nbuf);
  1938. if (!nbuf_clone) {
  1939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1940. "qdf_nbuf_clone failed");
  1941. return nbuf;
  1942. }
  1943. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1944. }
  1945. if (nbuf_clone) {
  1946. if (!dp_tx_send(soc, vdev_id, nbuf_clone)) {
  1947. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1948. } else {
  1949. qdf_nbuf_free(nbuf_clone);
  1950. }
  1951. }
  1952. if (no_enc_frame)
  1953. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1954. else
  1955. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1956. nbuf = dp_tx_send(soc, vdev_id, nbuf);
  1957. if ((!nbuf) && no_enc_frame) {
  1958. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1959. }
  1960. return nbuf;
  1961. }
  1962. #else
  1963. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1964. qdf_nbuf_t nbuf)
  1965. {
  1966. return dp_tx_send(soc, vdev_id, nbuf);
  1967. }
  1968. #endif
  1969. /**
  1970. * dp_tx_nawds_handler() - NAWDS handler
  1971. *
  1972. * @soc: DP soc handle
  1973. * @vdev_id: id of DP vdev handle
  1974. * @msdu_info: msdu_info required to create HTT metadata
  1975. * @nbuf: skb
  1976. *
  1977. * This API transfers the multicast frames with the peer id
  1978. * on NAWDS enabled peer.
  1979. * Return: none
  1980. */
  1981. static inline
  1982. void dp_tx_nawds_handler(struct cdp_soc_t *soc, struct dp_vdev *vdev,
  1983. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  1984. {
  1985. struct dp_peer *peer = NULL;
  1986. qdf_nbuf_t nbuf_clone = NULL;
  1987. struct dp_soc *dp_soc = (struct dp_soc *)soc;
  1988. uint16_t peer_id = DP_INVALID_PEER;
  1989. struct dp_peer *sa_peer = NULL;
  1990. struct dp_ast_entry *ast_entry = NULL;
  1991. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1992. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  1993. qdf_spin_lock_bh(&dp_soc->ast_lock);
  1994. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1995. (dp_soc,
  1996. (uint8_t *)(eh->ether_shost),
  1997. vdev->pdev->pdev_id);
  1998. if (ast_entry)
  1999. sa_peer = ast_entry->peer;
  2000. qdf_spin_unlock_bh(&dp_soc->ast_lock);
  2001. }
  2002. qdf_spin_lock_bh(&dp_soc->peer_ref_mutex);
  2003. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2004. if (!peer->bss_peer && peer->nawds_enabled) {
  2005. peer_id = peer->peer_ids[0];
  2006. /* Multicast packets needs to be
  2007. * dropped in case of intra bss forwarding
  2008. */
  2009. if (sa_peer == peer) {
  2010. QDF_TRACE(QDF_MODULE_ID_DP,
  2011. QDF_TRACE_LEVEL_DEBUG,
  2012. " %s: multicast packet", __func__);
  2013. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2014. continue;
  2015. }
  2016. nbuf_clone = qdf_nbuf_clone(nbuf);
  2017. if (!nbuf_clone) {
  2018. QDF_TRACE(QDF_MODULE_ID_DP,
  2019. QDF_TRACE_LEVEL_ERROR,
  2020. FL("nbuf clone failed"));
  2021. break;
  2022. }
  2023. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2024. msdu_info, peer_id,
  2025. NULL);
  2026. if (nbuf_clone) {
  2027. QDF_TRACE(QDF_MODULE_ID_DP,
  2028. QDF_TRACE_LEVEL_DEBUG,
  2029. FL("pkt send failed"));
  2030. qdf_nbuf_free(nbuf_clone);
  2031. } else {
  2032. if (peer_id != DP_INVALID_PEER)
  2033. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2034. 1, qdf_nbuf_len(nbuf));
  2035. }
  2036. }
  2037. }
  2038. qdf_spin_unlock_bh(&dp_soc->peer_ref_mutex);
  2039. }
  2040. /**
  2041. * dp_tx_send() - Transmit a frame on a given VAP
  2042. * @soc: DP soc handle
  2043. * @vdev_id: id of DP vdev handle
  2044. * @nbuf: skb
  2045. *
  2046. * Entry point for Core Tx layer (DP_TX) invoked from
  2047. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2048. * cases
  2049. *
  2050. * Return: NULL on success,
  2051. * nbuf when it fails to send
  2052. */
  2053. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf)
  2054. {
  2055. uint16_t peer_id = HTT_INVALID_PEER;
  2056. /*
  2057. * doing a memzero is causing additional function call overhead
  2058. * so doing static stack clearing
  2059. */
  2060. struct dp_tx_msdu_info_s msdu_info = {0};
  2061. struct dp_vdev *vdev =
  2062. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  2063. vdev_id);
  2064. if (qdf_unlikely(!vdev))
  2065. return nbuf;
  2066. dp_verbose_debug("skb %pM", nbuf->data);
  2067. /*
  2068. * Set Default Host TID value to invalid TID
  2069. * (TID override disabled)
  2070. */
  2071. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2072. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2073. if (qdf_unlikely(vdev->mesh_vdev)) {
  2074. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2075. &msdu_info);
  2076. if (!nbuf_mesh) {
  2077. dp_verbose_debug("Extracting mesh metadata failed");
  2078. return nbuf;
  2079. }
  2080. nbuf = nbuf_mesh;
  2081. }
  2082. /*
  2083. * Get HW Queue to use for this frame.
  2084. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2085. * dedicated for data and 1 for command.
  2086. * "queue_id" maps to one hardware ring.
  2087. * With each ring, we also associate a unique Tx descriptor pool
  2088. * to minimize lock contention for these resources.
  2089. */
  2090. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2091. /*
  2092. * TCL H/W supports 2 DSCP-TID mapping tables.
  2093. * Table 1 - Default DSCP-TID mapping table
  2094. * Table 2 - 1 DSCP-TID override table
  2095. *
  2096. * If we need a different DSCP-TID mapping for this vap,
  2097. * call tid_classify to extract DSCP/ToS from frame and
  2098. * map to a TID and store in msdu_info. This is later used
  2099. * to fill in TCL Input descriptor (per-packet TID override).
  2100. */
  2101. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2102. /*
  2103. * Classify the frame and call corresponding
  2104. * "prepare" function which extracts the segment (TSO)
  2105. * and fragmentation information (for TSO , SG, ME, or Raw)
  2106. * into MSDU_INFO structure which is later used to fill
  2107. * SW and HW descriptors.
  2108. */
  2109. if (qdf_nbuf_is_tso(nbuf)) {
  2110. dp_verbose_debug("TSO frame %pK", vdev);
  2111. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2112. qdf_nbuf_len(nbuf));
  2113. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2114. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2115. qdf_nbuf_len(nbuf));
  2116. return nbuf;
  2117. }
  2118. goto send_multiple;
  2119. }
  2120. /* SG */
  2121. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2122. struct dp_tx_seg_info_s seg_info = {0};
  2123. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2124. if (!nbuf)
  2125. return NULL;
  2126. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2127. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2128. qdf_nbuf_len(nbuf));
  2129. goto send_multiple;
  2130. }
  2131. #ifdef ATH_SUPPORT_IQUE
  2132. /* Mcast to Ucast Conversion*/
  2133. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2134. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2135. qdf_nbuf_data(nbuf);
  2136. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2137. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2138. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2139. DP_STATS_INC_PKT(vdev,
  2140. tx_i.mcast_en.mcast_pkt, 1,
  2141. qdf_nbuf_len(nbuf));
  2142. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2143. QDF_STATUS_SUCCESS) {
  2144. return NULL;
  2145. }
  2146. }
  2147. }
  2148. #endif
  2149. /* RAW */
  2150. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2151. struct dp_tx_seg_info_s seg_info = {0};
  2152. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2153. if (!nbuf)
  2154. return NULL;
  2155. dp_verbose_debug("Raw frame %pK", vdev);
  2156. goto send_multiple;
  2157. }
  2158. if (qdf_unlikely(vdev->nawds_enabled)) {
  2159. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2160. qdf_nbuf_data(nbuf);
  2161. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2162. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2163. peer_id = DP_INVALID_PEER;
  2164. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2165. 1, qdf_nbuf_len(nbuf));
  2166. }
  2167. /* Single linear frame */
  2168. /*
  2169. * If nbuf is a simple linear frame, use send_single function to
  2170. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2171. * SRNG. There is no need to setup a MSDU extension descriptor.
  2172. */
  2173. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2174. return nbuf;
  2175. send_multiple:
  2176. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2177. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2178. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2179. return nbuf;
  2180. }
  2181. /**
  2182. * dp_tx_reinject_handler() - Tx Reinject Handler
  2183. * @tx_desc: software descriptor head pointer
  2184. * @status : Tx completion status from HTT descriptor
  2185. *
  2186. * This function reinjects frames back to Target.
  2187. * Todo - Host queue needs to be added
  2188. *
  2189. * Return: none
  2190. */
  2191. static
  2192. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2193. {
  2194. struct dp_vdev *vdev;
  2195. struct dp_peer *peer = NULL;
  2196. uint32_t peer_id = HTT_INVALID_PEER;
  2197. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2198. qdf_nbuf_t nbuf_copy = NULL;
  2199. struct dp_tx_msdu_info_s msdu_info;
  2200. struct dp_soc *soc = NULL;
  2201. #ifdef WDS_VENDOR_EXTENSION
  2202. int is_mcast = 0, is_ucast = 0;
  2203. int num_peers_3addr = 0;
  2204. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2205. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2206. #endif
  2207. vdev = tx_desc->vdev;
  2208. soc = vdev->pdev->soc;
  2209. qdf_assert(vdev);
  2210. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2211. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2213. "%s Tx reinject path", __func__);
  2214. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2215. qdf_nbuf_len(tx_desc->nbuf));
  2216. #ifdef WDS_VENDOR_EXTENSION
  2217. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2218. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2219. } else {
  2220. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2221. }
  2222. is_ucast = !is_mcast;
  2223. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2224. if (peer->bss_peer)
  2225. continue;
  2226. /* Detect wds peers that use 3-addr framing for mcast.
  2227. * if there are any, the bss_peer is used to send the
  2228. * the mcast frame using 3-addr format. all wds enabled
  2229. * peers that use 4-addr framing for mcast frames will
  2230. * be duplicated and sent as 4-addr frames below.
  2231. */
  2232. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2233. num_peers_3addr = 1;
  2234. break;
  2235. }
  2236. }
  2237. #endif
  2238. if (qdf_unlikely(vdev->mesh_vdev)) {
  2239. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2240. } else {
  2241. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2242. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2243. #ifdef WDS_VENDOR_EXTENSION
  2244. /*
  2245. * . if 3-addr STA, then send on BSS Peer
  2246. * . if Peer WDS enabled and accept 4-addr mcast,
  2247. * send mcast on that peer only
  2248. * . if Peer WDS enabled and accept 4-addr ucast,
  2249. * send ucast on that peer only
  2250. */
  2251. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2252. (peer->wds_enabled &&
  2253. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2254. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2255. #else
  2256. ((peer->bss_peer &&
  2257. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2258. #endif
  2259. peer_id = DP_INVALID_PEER;
  2260. nbuf_copy = qdf_nbuf_copy(nbuf);
  2261. if (!nbuf_copy) {
  2262. QDF_TRACE(QDF_MODULE_ID_DP,
  2263. QDF_TRACE_LEVEL_DEBUG,
  2264. FL("nbuf copy failed"));
  2265. break;
  2266. }
  2267. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2268. nbuf_copy,
  2269. &msdu_info,
  2270. peer_id,
  2271. NULL);
  2272. if (nbuf_copy) {
  2273. QDF_TRACE(QDF_MODULE_ID_DP,
  2274. QDF_TRACE_LEVEL_DEBUG,
  2275. FL("pkt send failed"));
  2276. qdf_nbuf_free(nbuf_copy);
  2277. } else {
  2278. if (peer_id != DP_INVALID_PEER)
  2279. DP_STATS_INC_PKT(peer,
  2280. tx.nawds_mcast,
  2281. 1, qdf_nbuf_len(nbuf));
  2282. }
  2283. }
  2284. }
  2285. }
  2286. qdf_nbuf_free(nbuf);
  2287. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2288. }
  2289. /**
  2290. * dp_tx_inspect_handler() - Tx Inspect Handler
  2291. * @tx_desc: software descriptor head pointer
  2292. * @status : Tx completion status from HTT descriptor
  2293. *
  2294. * Handles Tx frames sent back to Host for inspection
  2295. * (ProxyARP)
  2296. *
  2297. * Return: none
  2298. */
  2299. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2300. {
  2301. struct dp_soc *soc;
  2302. struct dp_pdev *pdev = tx_desc->pdev;
  2303. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2304. "%s Tx inspect path",
  2305. __func__);
  2306. qdf_assert(pdev);
  2307. soc = pdev->soc;
  2308. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2309. qdf_nbuf_len(tx_desc->nbuf));
  2310. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2311. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2312. }
  2313. #ifdef FEATURE_PERPKT_INFO
  2314. /**
  2315. * dp_get_completion_indication_for_stack() - send completion to stack
  2316. * @soc : dp_soc handle
  2317. * @pdev: dp_pdev handle
  2318. * @peer: dp peer handle
  2319. * @ts: transmit completion status structure
  2320. * @netbuf: Buffer pointer for free
  2321. *
  2322. * This function is used for indication whether buffer needs to be
  2323. * sent to stack for freeing or not
  2324. */
  2325. QDF_STATUS
  2326. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2327. struct dp_pdev *pdev,
  2328. struct dp_peer *peer,
  2329. struct hal_tx_completion_status *ts,
  2330. qdf_nbuf_t netbuf,
  2331. uint64_t time_latency)
  2332. {
  2333. struct tx_capture_hdr *ppdu_hdr;
  2334. uint16_t peer_id = ts->peer_id;
  2335. uint32_t ppdu_id = ts->ppdu_id;
  2336. uint8_t first_msdu = ts->first_msdu;
  2337. uint8_t last_msdu = ts->last_msdu;
  2338. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2339. !pdev->latency_capture_enable))
  2340. return QDF_STATUS_E_NOSUPPORT;
  2341. if (!peer) {
  2342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2343. FL("Peer Invalid"));
  2344. return QDF_STATUS_E_INVAL;
  2345. }
  2346. if (pdev->mcopy_mode) {
  2347. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2348. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2349. return QDF_STATUS_E_INVAL;
  2350. }
  2351. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2352. pdev->m_copy_id.tx_peer_id = peer_id;
  2353. }
  2354. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2355. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2356. FL("No headroom"));
  2357. return QDF_STATUS_E_NOMEM;
  2358. }
  2359. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2360. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2361. QDF_MAC_ADDR_SIZE);
  2362. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2363. QDF_MAC_ADDR_SIZE);
  2364. ppdu_hdr->ppdu_id = ppdu_id;
  2365. ppdu_hdr->peer_id = peer_id;
  2366. ppdu_hdr->first_msdu = first_msdu;
  2367. ppdu_hdr->last_msdu = last_msdu;
  2368. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2369. ppdu_hdr->tsf = ts->tsf;
  2370. ppdu_hdr->time_latency = time_latency;
  2371. }
  2372. return QDF_STATUS_SUCCESS;
  2373. }
  2374. /**
  2375. * dp_send_completion_to_stack() - send completion to stack
  2376. * @soc : dp_soc handle
  2377. * @pdev: dp_pdev handle
  2378. * @peer_id: peer_id of the peer for which completion came
  2379. * @ppdu_id: ppdu_id
  2380. * @netbuf: Buffer pointer for free
  2381. *
  2382. * This function is used to send completion to stack
  2383. * to free buffer
  2384. */
  2385. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2386. uint16_t peer_id, uint32_t ppdu_id,
  2387. qdf_nbuf_t netbuf)
  2388. {
  2389. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2390. netbuf, peer_id,
  2391. WDI_NO_VAL, pdev->pdev_id);
  2392. }
  2393. #else
  2394. static QDF_STATUS
  2395. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2396. struct dp_pdev *pdev,
  2397. struct dp_peer *peer,
  2398. struct hal_tx_completion_status *ts,
  2399. qdf_nbuf_t netbuf,
  2400. uint64_t time_latency)
  2401. {
  2402. return QDF_STATUS_E_NOSUPPORT;
  2403. }
  2404. static void
  2405. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2406. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2407. {
  2408. }
  2409. #endif
  2410. /**
  2411. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2412. * @soc: Soc handle
  2413. * @desc: software Tx descriptor to be processed
  2414. *
  2415. * Return: none
  2416. */
  2417. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2418. struct dp_tx_desc_s *desc)
  2419. {
  2420. struct dp_vdev *vdev = desc->vdev;
  2421. qdf_nbuf_t nbuf = desc->nbuf;
  2422. /* nbuf already freed in vdev detach path */
  2423. if (!nbuf)
  2424. return;
  2425. /* If it is TDLS mgmt, don't unmap or free the frame */
  2426. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2427. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2428. /* 0 : MSDU buffer, 1 : MLE */
  2429. if (desc->msdu_ext_desc) {
  2430. /* TSO free */
  2431. if (hal_tx_ext_desc_get_tso_enable(
  2432. desc->msdu_ext_desc->vaddr)) {
  2433. /* unmap eash TSO seg before free the nbuf */
  2434. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2435. desc->tso_num_desc);
  2436. qdf_nbuf_free(nbuf);
  2437. return;
  2438. }
  2439. }
  2440. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2441. QDF_DMA_TO_DEVICE, nbuf->len);
  2442. if (qdf_unlikely(!vdev)) {
  2443. qdf_nbuf_free(nbuf);
  2444. return;
  2445. }
  2446. if (qdf_likely(!vdev->mesh_vdev))
  2447. qdf_nbuf_free(nbuf);
  2448. else {
  2449. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2450. qdf_nbuf_free(nbuf);
  2451. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2452. } else
  2453. vdev->osif_tx_free_ext((nbuf));
  2454. }
  2455. }
  2456. #ifdef MESH_MODE_SUPPORT
  2457. /**
  2458. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2459. * in mesh meta header
  2460. * @tx_desc: software descriptor head pointer
  2461. * @ts: pointer to tx completion stats
  2462. * Return: none
  2463. */
  2464. static
  2465. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2466. struct hal_tx_completion_status *ts)
  2467. {
  2468. struct meta_hdr_s *mhdr;
  2469. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2470. if (!tx_desc->msdu_ext_desc) {
  2471. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2472. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2473. "netbuf %pK offset %d",
  2474. netbuf, tx_desc->pkt_offset);
  2475. return;
  2476. }
  2477. }
  2478. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2480. "netbuf %pK offset %lu", netbuf,
  2481. sizeof(struct meta_hdr_s));
  2482. return;
  2483. }
  2484. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2485. mhdr->rssi = ts->ack_frame_rssi;
  2486. mhdr->band = tx_desc->pdev->operating_channel.band;
  2487. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2488. }
  2489. #else
  2490. static
  2491. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2492. struct hal_tx_completion_status *ts)
  2493. {
  2494. }
  2495. #endif
  2496. /**
  2497. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2498. * to pass in correct fields
  2499. *
  2500. * @vdev: pdev handle
  2501. * @tx_desc: tx descriptor
  2502. * @tid: tid value
  2503. * @ring_id: TCL or WBM ring number for transmit path
  2504. * Return: none
  2505. */
  2506. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2507. struct dp_tx_desc_s *tx_desc,
  2508. uint8_t tid, uint8_t ring_id)
  2509. {
  2510. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2511. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2512. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2513. return;
  2514. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2515. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2516. timestamp_hw_enqueue = tx_desc->timestamp;
  2517. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2518. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2519. timestamp_hw_enqueue);
  2520. interframe_delay = (uint32_t)(timestamp_ingress -
  2521. vdev->prev_tx_enq_tstamp);
  2522. /*
  2523. * Delay in software enqueue
  2524. */
  2525. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2526. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2527. /*
  2528. * Delay between packet enqueued to HW and Tx completion
  2529. */
  2530. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2531. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2532. /*
  2533. * Update interframe delay stats calculated at hardstart receive point.
  2534. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2535. * interframe delay will not be calculate correctly for 1st frame.
  2536. * On the other side, this will help in avoiding extra per packet check
  2537. * of !vdev->prev_tx_enq_tstamp.
  2538. */
  2539. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2540. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2541. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2542. }
  2543. #ifdef DISABLE_DP_STATS
  2544. static
  2545. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2546. {
  2547. }
  2548. #else
  2549. static
  2550. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2551. {
  2552. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2553. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2554. if (subtype != QDF_PROTO_INVALID)
  2555. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2556. }
  2557. #endif
  2558. /**
  2559. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2560. * per wbm ring
  2561. *
  2562. * @tx_desc: software descriptor head pointer
  2563. * @ts: Tx completion status
  2564. * @peer: peer handle
  2565. * @ring_id: ring number
  2566. *
  2567. * Return: None
  2568. */
  2569. static inline void
  2570. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2571. struct hal_tx_completion_status *ts,
  2572. struct dp_peer *peer, uint8_t ring_id)
  2573. {
  2574. struct dp_pdev *pdev = peer->vdev->pdev;
  2575. struct dp_soc *soc = NULL;
  2576. uint8_t mcs, pkt_type;
  2577. uint8_t tid = ts->tid;
  2578. uint32_t length;
  2579. struct cdp_tid_tx_stats *tid_stats;
  2580. if (!pdev)
  2581. return;
  2582. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2583. tid = CDP_MAX_DATA_TIDS - 1;
  2584. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2585. soc = pdev->soc;
  2586. mcs = ts->mcs;
  2587. pkt_type = ts->pkt_type;
  2588. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2589. dp_err("Release source is not from TQM");
  2590. return;
  2591. }
  2592. length = qdf_nbuf_len(tx_desc->nbuf);
  2593. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2594. if (qdf_unlikely(pdev->delay_stats_flag))
  2595. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2596. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2597. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2598. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2599. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2600. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2601. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2602. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2603. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2604. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2605. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2606. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2607. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2608. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2609. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2610. /*
  2611. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2612. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2613. * are no completions for failed cases. Hence updating tx_failed from
  2614. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2615. * then this has to be removed
  2616. */
  2617. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2618. peer->stats.tx.dropped.fw_rem_notx +
  2619. peer->stats.tx.dropped.fw_rem_tx +
  2620. peer->stats.tx.dropped.age_out +
  2621. peer->stats.tx.dropped.fw_reason1 +
  2622. peer->stats.tx.dropped.fw_reason2 +
  2623. peer->stats.tx.dropped.fw_reason3;
  2624. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2625. tid_stats->tqm_status_cnt[ts->status]++;
  2626. }
  2627. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2628. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2629. return;
  2630. }
  2631. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2632. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2633. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2634. /*
  2635. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2636. * Return from here if HTT PPDU events are enabled.
  2637. */
  2638. if (!(soc->process_tx_status))
  2639. return;
  2640. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2641. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2642. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2643. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2644. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2645. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2646. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2647. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2648. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2649. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2650. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2651. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2652. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2653. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2654. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2655. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2656. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2657. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2658. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2659. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2660. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2661. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2662. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2663. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2664. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2665. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2666. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2667. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2668. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2669. &peer->stats, ts->peer_id,
  2670. UPDATE_PEER_STATS, pdev->pdev_id);
  2671. #endif
  2672. }
  2673. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2674. /**
  2675. * dp_tx_flow_pool_lock() - take flow pool lock
  2676. * @soc: core txrx main context
  2677. * @tx_desc: tx desc
  2678. *
  2679. * Return: None
  2680. */
  2681. static inline
  2682. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2683. struct dp_tx_desc_s *tx_desc)
  2684. {
  2685. struct dp_tx_desc_pool_s *pool;
  2686. uint8_t desc_pool_id;
  2687. desc_pool_id = tx_desc->pool_id;
  2688. pool = &soc->tx_desc[desc_pool_id];
  2689. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2690. }
  2691. /**
  2692. * dp_tx_flow_pool_unlock() - release flow pool lock
  2693. * @soc: core txrx main context
  2694. * @tx_desc: tx desc
  2695. *
  2696. * Return: None
  2697. */
  2698. static inline
  2699. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2700. struct dp_tx_desc_s *tx_desc)
  2701. {
  2702. struct dp_tx_desc_pool_s *pool;
  2703. uint8_t desc_pool_id;
  2704. desc_pool_id = tx_desc->pool_id;
  2705. pool = &soc->tx_desc[desc_pool_id];
  2706. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2707. }
  2708. #else
  2709. static inline
  2710. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2711. {
  2712. }
  2713. static inline
  2714. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2715. {
  2716. }
  2717. #endif
  2718. /**
  2719. * dp_tx_notify_completion() - Notify tx completion for this desc
  2720. * @soc: core txrx main context
  2721. * @tx_desc: tx desc
  2722. * @netbuf: buffer
  2723. *
  2724. * Return: none
  2725. */
  2726. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2727. struct dp_tx_desc_s *tx_desc,
  2728. qdf_nbuf_t netbuf)
  2729. {
  2730. void *osif_dev;
  2731. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2732. qdf_assert(tx_desc);
  2733. dp_tx_flow_pool_lock(soc, tx_desc);
  2734. if (!tx_desc->vdev ||
  2735. !tx_desc->vdev->osif_vdev) {
  2736. dp_tx_flow_pool_unlock(soc, tx_desc);
  2737. return;
  2738. }
  2739. osif_dev = tx_desc->vdev->osif_vdev;
  2740. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2741. dp_tx_flow_pool_unlock(soc, tx_desc);
  2742. if (tx_compl_cbk)
  2743. tx_compl_cbk(netbuf, osif_dev);
  2744. }
  2745. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2746. * @pdev: pdev handle
  2747. * @tid: tid value
  2748. * @txdesc_ts: timestamp from txdesc
  2749. * @ppdu_id: ppdu id
  2750. *
  2751. * Return: none
  2752. */
  2753. #ifdef FEATURE_PERPKT_INFO
  2754. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2755. struct dp_peer *peer,
  2756. uint8_t tid,
  2757. uint64_t txdesc_ts,
  2758. uint32_t ppdu_id)
  2759. {
  2760. uint64_t delta_ms;
  2761. struct cdp_tx_sojourn_stats *sojourn_stats;
  2762. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2763. return;
  2764. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2765. tid >= CDP_DATA_TID_MAX))
  2766. return;
  2767. if (qdf_unlikely(!pdev->sojourn_buf))
  2768. return;
  2769. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2770. qdf_nbuf_data(pdev->sojourn_buf);
  2771. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2772. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2773. txdesc_ts;
  2774. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2775. delta_ms);
  2776. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2777. sojourn_stats->num_msdus[tid] = 1;
  2778. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2779. peer->avg_sojourn_msdu[tid].internal;
  2780. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2781. pdev->sojourn_buf, HTT_INVALID_PEER,
  2782. WDI_NO_VAL, pdev->pdev_id);
  2783. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2784. sojourn_stats->num_msdus[tid] = 0;
  2785. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2786. }
  2787. #else
  2788. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2789. struct dp_peer *peer,
  2790. uint8_t tid,
  2791. uint64_t txdesc_ts,
  2792. uint32_t ppdu_id)
  2793. {
  2794. }
  2795. #endif
  2796. /**
  2797. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2798. * @soc: DP Soc handle
  2799. * @tx_desc: software Tx descriptor
  2800. * @ts : Tx completion status from HAL/HTT descriptor
  2801. *
  2802. * Return: none
  2803. */
  2804. static inline void
  2805. dp_tx_comp_process_desc(struct dp_soc *soc,
  2806. struct dp_tx_desc_s *desc,
  2807. struct hal_tx_completion_status *ts,
  2808. struct dp_peer *peer)
  2809. {
  2810. uint64_t time_latency = 0;
  2811. /*
  2812. * m_copy/tx_capture modes are not supported for
  2813. * scatter gather packets
  2814. */
  2815. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2816. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2817. desc->timestamp);
  2818. }
  2819. if (!(desc->msdu_ext_desc)) {
  2820. if (QDF_STATUS_SUCCESS ==
  2821. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2822. return;
  2823. }
  2824. if (QDF_STATUS_SUCCESS ==
  2825. dp_get_completion_indication_for_stack(soc,
  2826. desc->pdev,
  2827. peer, ts,
  2828. desc->nbuf,
  2829. time_latency)) {
  2830. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  2831. QDF_DMA_TO_DEVICE,
  2832. desc->nbuf->len);
  2833. dp_send_completion_to_stack(soc,
  2834. desc->pdev,
  2835. ts->peer_id,
  2836. ts->ppdu_id,
  2837. desc->nbuf);
  2838. return;
  2839. }
  2840. }
  2841. dp_tx_comp_free_buf(soc, desc);
  2842. }
  2843. /**
  2844. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2845. * @tx_desc: software descriptor head pointer
  2846. * @ts: Tx completion status
  2847. * @peer: peer handle
  2848. * @ring_id: ring number
  2849. *
  2850. * Return: none
  2851. */
  2852. static inline
  2853. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2854. struct hal_tx_completion_status *ts,
  2855. struct dp_peer *peer, uint8_t ring_id)
  2856. {
  2857. uint32_t length;
  2858. qdf_ether_header_t *eh;
  2859. struct dp_soc *soc = NULL;
  2860. struct dp_vdev *vdev = tx_desc->vdev;
  2861. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2862. if (!vdev || !nbuf) {
  2863. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  2864. goto out;
  2865. }
  2866. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2867. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2868. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2869. QDF_TRACE_DEFAULT_PDEV_ID,
  2870. qdf_nbuf_data_addr(nbuf),
  2871. sizeof(qdf_nbuf_data(nbuf)),
  2872. tx_desc->id,
  2873. ts->status));
  2874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2875. "-------------------- \n"
  2876. "Tx Completion Stats: \n"
  2877. "-------------------- \n"
  2878. "ack_frame_rssi = %d \n"
  2879. "first_msdu = %d \n"
  2880. "last_msdu = %d \n"
  2881. "msdu_part_of_amsdu = %d \n"
  2882. "rate_stats valid = %d \n"
  2883. "bw = %d \n"
  2884. "pkt_type = %d \n"
  2885. "stbc = %d \n"
  2886. "ldpc = %d \n"
  2887. "sgi = %d \n"
  2888. "mcs = %d \n"
  2889. "ofdma = %d \n"
  2890. "tones_in_ru = %d \n"
  2891. "tsf = %d \n"
  2892. "ppdu_id = %d \n"
  2893. "transmit_cnt = %d \n"
  2894. "tid = %d \n"
  2895. "peer_id = %d\n",
  2896. ts->ack_frame_rssi, ts->first_msdu,
  2897. ts->last_msdu, ts->msdu_part_of_amsdu,
  2898. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2899. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2900. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2901. ts->transmit_cnt, ts->tid, ts->peer_id);
  2902. soc = vdev->pdev->soc;
  2903. /* Update SoC level stats */
  2904. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2905. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2906. /* Update per-packet stats for mesh mode */
  2907. if (qdf_unlikely(vdev->mesh_vdev) &&
  2908. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2909. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2910. length = qdf_nbuf_len(nbuf);
  2911. /* Update peer level stats */
  2912. if (!peer) {
  2913. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2914. "peer is null or deletion in progress");
  2915. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2916. goto out;
  2917. }
  2918. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2919. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2920. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2921. if ((peer->vdev->tx_encap_type ==
  2922. htt_cmn_pkt_type_ethernet) &&
  2923. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2924. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2925. }
  2926. }
  2927. } else {
  2928. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2929. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2930. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2931. }
  2932. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2933. #ifdef QCA_SUPPORT_RDK_STATS
  2934. if (soc->wlanstats_enabled)
  2935. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2936. tx_desc->timestamp,
  2937. ts->ppdu_id);
  2938. #endif
  2939. out:
  2940. return;
  2941. }
  2942. /**
  2943. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2944. * @soc: core txrx main context
  2945. * @comp_head: software descriptor head pointer
  2946. * @ring_id: ring number
  2947. *
  2948. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2949. * and release the software descriptors after processing is complete
  2950. *
  2951. * Return: none
  2952. */
  2953. static void
  2954. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2955. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2956. {
  2957. struct dp_tx_desc_s *desc;
  2958. struct dp_tx_desc_s *next;
  2959. struct hal_tx_completion_status ts = {0};
  2960. struct dp_peer *peer;
  2961. qdf_nbuf_t netbuf;
  2962. desc = comp_head;
  2963. while (desc) {
  2964. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2965. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2966. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2967. netbuf = desc->nbuf;
  2968. /* check tx complete notification */
  2969. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2970. dp_tx_notify_completion(soc, desc, netbuf);
  2971. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2972. if (peer)
  2973. dp_peer_unref_del_find_by_id(peer);
  2974. next = desc->next;
  2975. dp_tx_desc_release(desc, desc->pool_id);
  2976. desc = next;
  2977. }
  2978. }
  2979. /**
  2980. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2981. * @tx_desc: software descriptor head pointer
  2982. * @status : Tx completion status from HTT descriptor
  2983. * @ring_id: ring number
  2984. *
  2985. * This function will process HTT Tx indication messages from Target
  2986. *
  2987. * Return: none
  2988. */
  2989. static
  2990. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2991. uint8_t ring_id)
  2992. {
  2993. uint8_t tx_status;
  2994. struct dp_pdev *pdev;
  2995. struct dp_vdev *vdev;
  2996. struct dp_soc *soc;
  2997. struct hal_tx_completion_status ts = {0};
  2998. uint32_t *htt_desc = (uint32_t *)status;
  2999. struct dp_peer *peer;
  3000. struct cdp_tid_tx_stats *tid_stats = NULL;
  3001. struct htt_soc *htt_handle;
  3002. qdf_assert(tx_desc->pdev);
  3003. pdev = tx_desc->pdev;
  3004. vdev = tx_desc->vdev;
  3005. soc = pdev->soc;
  3006. if (!vdev)
  3007. return;
  3008. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3009. htt_handle = (struct htt_soc *)soc->htt_handle;
  3010. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3011. switch (tx_status) {
  3012. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3013. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3014. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3015. {
  3016. uint8_t tid;
  3017. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3018. ts.peer_id =
  3019. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3020. htt_desc[2]);
  3021. ts.tid =
  3022. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3023. htt_desc[2]);
  3024. } else {
  3025. ts.peer_id = HTT_INVALID_PEER;
  3026. ts.tid = HTT_INVALID_TID;
  3027. }
  3028. ts.ppdu_id =
  3029. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3030. htt_desc[1]);
  3031. ts.ack_frame_rssi =
  3032. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3033. htt_desc[1]);
  3034. ts.first_msdu = 1;
  3035. ts.last_msdu = 1;
  3036. tid = ts.tid;
  3037. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3038. tid = CDP_MAX_DATA_TIDS - 1;
  3039. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3040. if (qdf_unlikely(pdev->delay_stats_flag))
  3041. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3042. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3043. tid_stats->htt_status_cnt[tx_status]++;
  3044. }
  3045. peer = dp_peer_find_by_id(soc, ts.peer_id);
  3046. if (qdf_likely(peer))
  3047. dp_peer_unref_del_find_by_id(peer);
  3048. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  3049. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3050. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3051. break;
  3052. }
  3053. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3054. {
  3055. dp_tx_reinject_handler(tx_desc, status);
  3056. break;
  3057. }
  3058. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3059. {
  3060. dp_tx_inspect_handler(tx_desc, status);
  3061. break;
  3062. }
  3063. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3064. {
  3065. dp_tx_mec_handler(vdev, status);
  3066. break;
  3067. }
  3068. default:
  3069. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3070. "%s Invalid HTT tx_status %d\n",
  3071. __func__, tx_status);
  3072. break;
  3073. }
  3074. }
  3075. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3076. static inline
  3077. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3078. {
  3079. bool limit_hit = false;
  3080. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3081. limit_hit =
  3082. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3083. if (limit_hit)
  3084. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3085. return limit_hit;
  3086. }
  3087. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3088. {
  3089. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3090. }
  3091. #else
  3092. static inline
  3093. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3094. {
  3095. return false;
  3096. }
  3097. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3098. {
  3099. return false;
  3100. }
  3101. #endif
  3102. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3103. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3104. uint32_t quota)
  3105. {
  3106. void *tx_comp_hal_desc;
  3107. uint8_t buffer_src;
  3108. uint8_t pool_id;
  3109. uint32_t tx_desc_id;
  3110. struct dp_tx_desc_s *tx_desc = NULL;
  3111. struct dp_tx_desc_s *head_desc = NULL;
  3112. struct dp_tx_desc_s *tail_desc = NULL;
  3113. uint32_t num_processed = 0;
  3114. uint32_t count = 0;
  3115. bool force_break = false;
  3116. DP_HIST_INIT();
  3117. more_data:
  3118. /* Re-initialize local variables to be re-used */
  3119. head_desc = NULL;
  3120. tail_desc = NULL;
  3121. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3122. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3123. return 0;
  3124. }
  3125. /* Find head descriptor from completion ring */
  3126. while (qdf_likely(tx_comp_hal_desc =
  3127. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  3128. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3129. /* If this buffer was not released by TQM or FW, then it is not
  3130. * Tx completion indication, assert */
  3131. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3132. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3133. uint8_t wbm_internal_error;
  3134. dp_err_rl(
  3135. "Tx comp release_src != TQM | FW but from %d",
  3136. buffer_src);
  3137. hal_dump_comp_desc(tx_comp_hal_desc);
  3138. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3139. /* When WBM sees NULL buffer_addr_info in any of
  3140. * ingress rings it sends an error indication,
  3141. * with wbm_internal_error=1, to a specific ring.
  3142. * The WBM2SW ring used to indicate these errors is
  3143. * fixed in HW, and that ring is being used as Tx
  3144. * completion ring. These errors are not related to
  3145. * Tx completions, and should just be ignored
  3146. */
  3147. wbm_internal_error = hal_get_wbm_internal_error(
  3148. soc->hal_soc,
  3149. tx_comp_hal_desc);
  3150. if (wbm_internal_error) {
  3151. dp_err_rl("Tx comp wbm_internal_error!!");
  3152. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3153. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3154. buffer_src)
  3155. dp_handle_wbm_internal_error(
  3156. soc,
  3157. tx_comp_hal_desc,
  3158. hal_tx_comp_get_buffer_type(
  3159. tx_comp_hal_desc));
  3160. } else {
  3161. dp_err_rl("Tx comp wbm_internal_error false");
  3162. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3163. }
  3164. continue;
  3165. }
  3166. /* Get descriptor id */
  3167. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3168. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3169. DP_TX_DESC_ID_POOL_OS;
  3170. /* Find Tx descriptor */
  3171. tx_desc = dp_tx_desc_find(soc, pool_id,
  3172. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3173. DP_TX_DESC_ID_PAGE_OS,
  3174. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3175. DP_TX_DESC_ID_OFFSET_OS);
  3176. /*
  3177. * If the descriptor is already freed in vdev_detach,
  3178. * continue to next descriptor
  3179. */
  3180. if (!tx_desc->vdev && !tx_desc->flags) {
  3181. QDF_TRACE(QDF_MODULE_ID_DP,
  3182. QDF_TRACE_LEVEL_INFO,
  3183. "Descriptor freed in vdev_detach %d",
  3184. tx_desc_id);
  3185. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3186. count++;
  3187. continue;
  3188. }
  3189. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3190. QDF_TRACE(QDF_MODULE_ID_DP,
  3191. QDF_TRACE_LEVEL_INFO,
  3192. "pdev in down state %d",
  3193. tx_desc_id);
  3194. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3195. count++;
  3196. dp_tx_comp_free_buf(soc, tx_desc);
  3197. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3198. continue;
  3199. }
  3200. /*
  3201. * If the release source is FW, process the HTT status
  3202. */
  3203. if (qdf_unlikely(buffer_src ==
  3204. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3205. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3206. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3207. htt_tx_status);
  3208. dp_tx_process_htt_completion(tx_desc,
  3209. htt_tx_status, ring_id);
  3210. } else {
  3211. /* Pool id is not matching. Error */
  3212. if (tx_desc->pool_id != pool_id) {
  3213. QDF_TRACE(QDF_MODULE_ID_DP,
  3214. QDF_TRACE_LEVEL_FATAL,
  3215. "Tx Comp pool id %d not matched %d",
  3216. pool_id, tx_desc->pool_id);
  3217. qdf_assert_always(0);
  3218. }
  3219. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3220. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3221. QDF_TRACE(QDF_MODULE_ID_DP,
  3222. QDF_TRACE_LEVEL_FATAL,
  3223. "Txdesc invalid, flgs = %x,id = %d",
  3224. tx_desc->flags, tx_desc_id);
  3225. qdf_assert_always(0);
  3226. }
  3227. /* First ring descriptor on the cycle */
  3228. if (!head_desc) {
  3229. head_desc = tx_desc;
  3230. tail_desc = tx_desc;
  3231. }
  3232. tail_desc->next = tx_desc;
  3233. tx_desc->next = NULL;
  3234. tail_desc = tx_desc;
  3235. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3236. /* Collect hw completion contents */
  3237. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3238. &tx_desc->comp, 1);
  3239. }
  3240. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3241. /*
  3242. * Processed packet count is more than given quota
  3243. * stop to processing
  3244. */
  3245. if (num_processed >= quota) {
  3246. force_break = true;
  3247. break;
  3248. }
  3249. count++;
  3250. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3251. break;
  3252. }
  3253. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3254. /* Process the reaped descriptors */
  3255. if (head_desc)
  3256. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3257. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3258. if (!force_break &&
  3259. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3260. hal_ring_hdl)) {
  3261. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3262. if (!hif_exec_should_yield(soc->hif_handle,
  3263. int_ctx->dp_intr_id))
  3264. goto more_data;
  3265. }
  3266. }
  3267. DP_TX_HIST_STATS_PER_PDEV();
  3268. return num_processed;
  3269. }
  3270. #ifdef FEATURE_WLAN_TDLS
  3271. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3272. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3273. {
  3274. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3275. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3276. if (!vdev) {
  3277. dp_err("vdev handle for id %d is NULL", vdev_id);
  3278. return NULL;
  3279. }
  3280. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3281. vdev->is_tdls_frame = true;
  3282. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3283. }
  3284. #endif
  3285. /**
  3286. * dp_tx_vdev_attach() - attach vdev to dp tx
  3287. * @vdev: virtual device instance
  3288. *
  3289. * Return: QDF_STATUS_SUCCESS: success
  3290. * QDF_STATUS_E_RESOURCES: Error return
  3291. */
  3292. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3293. {
  3294. int pdev_id;
  3295. /*
  3296. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3297. */
  3298. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3299. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3300. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3301. vdev->vdev_id);
  3302. pdev_id =
  3303. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3304. vdev->pdev->pdev_id);
  3305. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3306. /*
  3307. * Set HTT Extension Valid bit to 0 by default
  3308. */
  3309. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3310. dp_tx_vdev_update_search_flags(vdev);
  3311. return QDF_STATUS_SUCCESS;
  3312. }
  3313. #ifndef FEATURE_WDS
  3314. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3315. {
  3316. return false;
  3317. }
  3318. #endif
  3319. /**
  3320. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3321. * @vdev: virtual device instance
  3322. *
  3323. * Return: void
  3324. *
  3325. */
  3326. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3327. {
  3328. struct dp_soc *soc = vdev->pdev->soc;
  3329. /*
  3330. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3331. * for TDLS link
  3332. *
  3333. * Enable AddrY (SA based search) only for non-WDS STA and
  3334. * ProxySTA VAP (in HKv1) modes.
  3335. *
  3336. * In all other VAP modes, only DA based search should be
  3337. * enabled
  3338. */
  3339. if (vdev->opmode == wlan_op_mode_sta &&
  3340. vdev->tdls_link_connected)
  3341. vdev->hal_desc_addr_search_flags =
  3342. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3343. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3344. !dp_tx_da_search_override(vdev))
  3345. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3346. else
  3347. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3348. /* Set search type only when peer map v2 messaging is enabled
  3349. * as we will have the search index (AST hash) only when v2 is
  3350. * enabled
  3351. */
  3352. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3353. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3354. else
  3355. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3356. }
  3357. static inline bool
  3358. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3359. struct dp_vdev *vdev,
  3360. struct dp_tx_desc_s *tx_desc)
  3361. {
  3362. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3363. return false;
  3364. /*
  3365. * if vdev is given, then only check whether desc
  3366. * vdev match. if vdev is NULL, then check whether
  3367. * desc pdev match.
  3368. */
  3369. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3370. }
  3371. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3372. /**
  3373. * dp_tx_desc_flush() - release resources associated
  3374. * to TX Desc
  3375. *
  3376. * @dp_pdev: Handle to DP pdev structure
  3377. * @vdev: virtual device instance
  3378. * NULL: no specific Vdev is required and check all allcated TX desc
  3379. * on this pdev.
  3380. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3381. *
  3382. * @force_free:
  3383. * true: flush the TX desc.
  3384. * false: only reset the Vdev in each allocated TX desc
  3385. * that associated to current Vdev.
  3386. *
  3387. * This function will go through the TX desc pool to flush
  3388. * the outstanding TX data or reset Vdev to NULL in associated TX
  3389. * Desc.
  3390. */
  3391. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3392. struct dp_vdev *vdev,
  3393. bool force_free)
  3394. {
  3395. uint8_t i;
  3396. uint32_t j;
  3397. uint32_t num_desc, page_id, offset;
  3398. uint16_t num_desc_per_page;
  3399. struct dp_soc *soc = pdev->soc;
  3400. struct dp_tx_desc_s *tx_desc = NULL;
  3401. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3402. if (!vdev && !force_free) {
  3403. dp_err("Reset TX desc vdev, Vdev param is required!");
  3404. return;
  3405. }
  3406. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3407. tx_desc_pool = &soc->tx_desc[i];
  3408. if (!(tx_desc_pool->pool_size) ||
  3409. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3410. !(tx_desc_pool->desc_pages.cacheable_pages))
  3411. continue;
  3412. /*
  3413. * Add flow pool lock protection in case pool is freed
  3414. * due to all tx_desc is recycled when handle TX completion.
  3415. * this is not necessary when do force flush as:
  3416. * a. double lock will happen if dp_tx_desc_release is
  3417. * also trying to acquire it.
  3418. * b. dp interrupt has been disabled before do force TX desc
  3419. * flush in dp_pdev_deinit().
  3420. */
  3421. if (!force_free)
  3422. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3423. num_desc = tx_desc_pool->pool_size;
  3424. num_desc_per_page =
  3425. tx_desc_pool->desc_pages.num_element_per_page;
  3426. for (j = 0; j < num_desc; j++) {
  3427. page_id = j / num_desc_per_page;
  3428. offset = j % num_desc_per_page;
  3429. if (qdf_unlikely(!(tx_desc_pool->
  3430. desc_pages.cacheable_pages)))
  3431. break;
  3432. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3433. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3434. /*
  3435. * Free TX desc if force free is
  3436. * required, otherwise only reset vdev
  3437. * in this TX desc.
  3438. */
  3439. if (force_free) {
  3440. dp_tx_comp_free_buf(soc, tx_desc);
  3441. dp_tx_desc_release(tx_desc, i);
  3442. } else {
  3443. tx_desc->vdev = NULL;
  3444. }
  3445. }
  3446. }
  3447. if (!force_free)
  3448. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3449. }
  3450. }
  3451. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3452. /**
  3453. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3454. *
  3455. * @soc: Handle to DP soc structure
  3456. * @tx_desc: pointer of one TX desc
  3457. * @desc_pool_id: TX Desc pool id
  3458. */
  3459. static inline void
  3460. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3461. uint8_t desc_pool_id)
  3462. {
  3463. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3464. tx_desc->vdev = NULL;
  3465. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3466. }
  3467. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3468. struct dp_vdev *vdev,
  3469. bool force_free)
  3470. {
  3471. uint8_t i, num_pool;
  3472. uint32_t j;
  3473. uint32_t num_desc, page_id, offset;
  3474. uint16_t num_desc_per_page;
  3475. struct dp_soc *soc = pdev->soc;
  3476. struct dp_tx_desc_s *tx_desc = NULL;
  3477. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3478. if (!vdev && !force_free) {
  3479. dp_err("Reset TX desc vdev, Vdev param is required!");
  3480. return;
  3481. }
  3482. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3483. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3484. for (i = 0; i < num_pool; i++) {
  3485. tx_desc_pool = &soc->tx_desc[i];
  3486. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3487. continue;
  3488. num_desc_per_page =
  3489. tx_desc_pool->desc_pages.num_element_per_page;
  3490. for (j = 0; j < num_desc; j++) {
  3491. page_id = j / num_desc_per_page;
  3492. offset = j % num_desc_per_page;
  3493. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3494. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3495. if (force_free) {
  3496. dp_tx_comp_free_buf(soc, tx_desc);
  3497. dp_tx_desc_release(tx_desc, i);
  3498. } else {
  3499. dp_tx_desc_reset_vdev(soc, tx_desc,
  3500. i);
  3501. }
  3502. }
  3503. }
  3504. }
  3505. }
  3506. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3507. /**
  3508. * dp_tx_vdev_detach() - detach vdev from dp tx
  3509. * @vdev: virtual device instance
  3510. *
  3511. * Return: QDF_STATUS_SUCCESS: success
  3512. * QDF_STATUS_E_RESOURCES: Error return
  3513. */
  3514. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3515. {
  3516. struct dp_pdev *pdev = vdev->pdev;
  3517. /* Reset TX desc associated to this Vdev as NULL */
  3518. dp_tx_desc_flush(pdev, vdev, false);
  3519. dp_tx_vdev_multipass_deinit(vdev);
  3520. return QDF_STATUS_SUCCESS;
  3521. }
  3522. /**
  3523. * dp_tx_pdev_attach() - attach pdev to dp tx
  3524. * @pdev: physical device instance
  3525. *
  3526. * Return: QDF_STATUS_SUCCESS: success
  3527. * QDF_STATUS_E_RESOURCES: Error return
  3528. */
  3529. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3530. {
  3531. struct dp_soc *soc = pdev->soc;
  3532. /* Initialize Flow control counters */
  3533. qdf_atomic_init(&pdev->num_tx_exception);
  3534. qdf_atomic_init(&pdev->num_tx_outstanding);
  3535. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3536. /* Initialize descriptors in TCL Ring */
  3537. hal_tx_init_data_ring(soc->hal_soc,
  3538. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3539. }
  3540. return QDF_STATUS_SUCCESS;
  3541. }
  3542. /**
  3543. * dp_tx_pdev_detach() - detach pdev from dp tx
  3544. * @pdev: physical device instance
  3545. *
  3546. * Return: QDF_STATUS_SUCCESS: success
  3547. * QDF_STATUS_E_RESOURCES: Error return
  3548. */
  3549. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3550. {
  3551. /* flush TX outstanding data per pdev */
  3552. dp_tx_desc_flush(pdev, NULL, true);
  3553. dp_tx_me_exit(pdev);
  3554. return QDF_STATUS_SUCCESS;
  3555. }
  3556. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3557. /* Pools will be allocated dynamically */
  3558. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3559. int num_desc)
  3560. {
  3561. uint8_t i;
  3562. for (i = 0; i < num_pool; i++) {
  3563. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3564. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3565. }
  3566. return 0;
  3567. }
  3568. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3569. {
  3570. uint8_t i;
  3571. for (i = 0; i < num_pool; i++)
  3572. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3573. }
  3574. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3575. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3576. int num_desc)
  3577. {
  3578. uint8_t i;
  3579. /* Allocate software Tx descriptor pools */
  3580. for (i = 0; i < num_pool; i++) {
  3581. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3583. "%s Tx Desc Pool alloc %d failed %pK",
  3584. __func__, i, soc);
  3585. return ENOMEM;
  3586. }
  3587. }
  3588. return 0;
  3589. }
  3590. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3591. {
  3592. uint8_t i;
  3593. for (i = 0; i < num_pool; i++) {
  3594. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3595. if (dp_tx_desc_pool_free(soc, i)) {
  3596. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3597. "%s Tx Desc Pool Free failed", __func__);
  3598. }
  3599. }
  3600. }
  3601. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3602. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3603. /**
  3604. * dp_tso_attach_wifi3() - TSO attach handler
  3605. * @txrx_soc: Opaque Dp handle
  3606. *
  3607. * Reserve TSO descriptor buffers
  3608. *
  3609. * Return: QDF_STATUS_E_FAILURE on failure or
  3610. * QDF_STATUS_SUCCESS on success
  3611. */
  3612. static
  3613. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3614. {
  3615. return dp_tso_soc_attach(txrx_soc);
  3616. }
  3617. /**
  3618. * dp_tso_detach_wifi3() - TSO Detach handler
  3619. * @txrx_soc: Opaque Dp handle
  3620. *
  3621. * Deallocate TSO descriptor buffers
  3622. *
  3623. * Return: QDF_STATUS_E_FAILURE on failure or
  3624. * QDF_STATUS_SUCCESS on success
  3625. */
  3626. static
  3627. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3628. {
  3629. return dp_tso_soc_detach(txrx_soc);
  3630. }
  3631. #else
  3632. static
  3633. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3634. {
  3635. return QDF_STATUS_SUCCESS;
  3636. }
  3637. static
  3638. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3639. {
  3640. return QDF_STATUS_SUCCESS;
  3641. }
  3642. #endif
  3643. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  3644. {
  3645. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3646. uint8_t i;
  3647. uint8_t num_pool;
  3648. uint32_t num_desc;
  3649. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3650. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3651. for (i = 0; i < num_pool; i++)
  3652. dp_tx_tso_desc_pool_free(soc, i);
  3653. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3654. __func__, num_pool, num_desc);
  3655. for (i = 0; i < num_pool; i++)
  3656. dp_tx_tso_num_seg_pool_free(soc, i);
  3657. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3658. __func__, num_pool, num_desc);
  3659. return QDF_STATUS_SUCCESS;
  3660. }
  3661. /**
  3662. * dp_tso_attach() - TSO attach handler
  3663. * @txrx_soc: Opaque Dp handle
  3664. *
  3665. * Reserve TSO descriptor buffers
  3666. *
  3667. * Return: QDF_STATUS_E_FAILURE on failure or
  3668. * QDF_STATUS_SUCCESS on success
  3669. */
  3670. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  3671. {
  3672. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3673. uint8_t i;
  3674. uint8_t num_pool;
  3675. uint32_t num_desc;
  3676. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3677. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3678. for (i = 0; i < num_pool; i++) {
  3679. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3680. dp_err("TSO Desc Pool alloc %d failed %pK",
  3681. i, soc);
  3682. return QDF_STATUS_E_FAILURE;
  3683. }
  3684. }
  3685. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3686. __func__, num_pool, num_desc);
  3687. for (i = 0; i < num_pool; i++) {
  3688. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3689. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3690. i, soc);
  3691. return QDF_STATUS_E_FAILURE;
  3692. }
  3693. }
  3694. return QDF_STATUS_SUCCESS;
  3695. }
  3696. /**
  3697. * dp_tx_soc_detach() - detach soc from dp tx
  3698. * @soc: core txrx main context
  3699. *
  3700. * This function will detach dp tx into main device context
  3701. * will free dp tx resource and initialize resources
  3702. *
  3703. * Return: QDF_STATUS_SUCCESS: success
  3704. * QDF_STATUS_E_RESOURCES: Error return
  3705. */
  3706. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3707. {
  3708. uint8_t num_pool;
  3709. uint16_t num_desc;
  3710. uint16_t num_ext_desc;
  3711. uint8_t i;
  3712. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3713. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3714. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3715. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3716. dp_tx_flow_control_deinit(soc);
  3717. dp_tx_delete_static_pools(soc, num_pool);
  3718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3719. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3720. __func__, num_pool, num_desc);
  3721. for (i = 0; i < num_pool; i++) {
  3722. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3723. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3724. "%s Tx Ext Desc Pool Free failed",
  3725. __func__);
  3726. return QDF_STATUS_E_RESOURCES;
  3727. }
  3728. }
  3729. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3730. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3731. __func__, num_pool, num_ext_desc);
  3732. status = dp_tso_detach_wifi3(soc);
  3733. if (status != QDF_STATUS_SUCCESS)
  3734. return status;
  3735. return QDF_STATUS_SUCCESS;
  3736. }
  3737. /**
  3738. * dp_tx_soc_attach() - attach soc to dp tx
  3739. * @soc: core txrx main context
  3740. *
  3741. * This function will attach dp tx into main device context
  3742. * will allocate dp tx resource and initialize resources
  3743. *
  3744. * Return: QDF_STATUS_SUCCESS: success
  3745. * QDF_STATUS_E_RESOURCES: Error return
  3746. */
  3747. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3748. {
  3749. uint8_t i;
  3750. uint8_t num_pool;
  3751. uint32_t num_desc;
  3752. uint32_t num_ext_desc;
  3753. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3754. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3755. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3756. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3757. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3758. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3759. __func__, num_pool, num_desc);
  3760. if ((num_pool > MAX_TXDESC_POOLS) ||
  3761. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  3762. goto fail;
  3763. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3764. goto fail;
  3765. dp_tx_flow_control_init(soc);
  3766. /* Allocate extension tx descriptor pools */
  3767. for (i = 0; i < num_pool; i++) {
  3768. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3769. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3770. "MSDU Ext Desc Pool alloc %d failed %pK",
  3771. i, soc);
  3772. goto fail;
  3773. }
  3774. }
  3775. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3776. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3777. __func__, num_pool, num_ext_desc);
  3778. status = dp_tso_attach_wifi3((void *)soc);
  3779. if (status != QDF_STATUS_SUCCESS)
  3780. goto fail;
  3781. /* Initialize descriptors in TCL Rings */
  3782. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3783. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3784. hal_tx_init_data_ring(soc->hal_soc,
  3785. soc->tcl_data_ring[i].hal_srng);
  3786. }
  3787. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3788. hal_tx_init_data_ring(soc->hal_soc,
  3789. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng);
  3790. }
  3791. /*
  3792. * Initialize command/credit ring descriptor
  3793. * Command/CREDIT ring also used for sending DATA cmds
  3794. */
  3795. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  3796. soc->tcl_cmd_credit_ring.hal_srng);
  3797. /*
  3798. * todo - Add a runtime config option to enable this.
  3799. */
  3800. /*
  3801. * Due to multiple issues on NPR EMU, enable it selectively
  3802. * only for NPR EMU, should be removed, once NPR platforms
  3803. * are stable.
  3804. */
  3805. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3806. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3807. "%s HAL Tx init Success", __func__);
  3808. return QDF_STATUS_SUCCESS;
  3809. fail:
  3810. /* Detach will take care of freeing only allocated resources */
  3811. dp_tx_soc_detach(soc);
  3812. return QDF_STATUS_E_RESOURCES;
  3813. }