wcd939x.c 168 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/stringify.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <linux/regmap.h>
  19. #include <sound/soc.h>
  20. #include <sound/soc-dapm.h>
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include <asoc/msm-cdc-pinctrl.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include <asoc/wcd-mbhc-v2-api.h>
  25. #include <bindings/audio-codec-port-types.h>
  26. #include <linux/qti-regmap-debugfs.h>
  27. #include "wcd939x-registers.h"
  28. #include "wcd939x.h"
  29. #include "internal.h"
  30. #include "asoc/bolero-slave-internal.h"
  31. #include "wcd939x-reg-masks.h"
  32. #include "wcd939x-reg-shifts.h"
  33. #if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
  34. #include <linux/soc/qcom/wcd939x-i2c.h>
  35. #endif
  36. #define NUM_SWRS_DT_PARAMS 5
  37. #define WCD939X_VARIANT_ENTRY_SIZE 32
  38. #define WCD939X_VERSION_ENTRY_SIZE 32
  39. #define ADC_MODE_VAL_HIFI 0x01
  40. #define ADC_MODE_VAL_LO_HIF 0x02
  41. #define ADC_MODE_VAL_NORMAL 0x03
  42. #define ADC_MODE_VAL_LP 0x05
  43. #define ADC_MODE_VAL_ULP1 0x09
  44. #define ADC_MODE_VAL_ULP2 0x0B
  45. #define HPH_IMPEDANCE_2VPK_MODE_OHMS 260
  46. #define XTALK_L_CH_NUM 0
  47. #define XTALK_R_CH_NUM 1
  48. #define GND_EXT_FET_MARGIN_MOHMS 200
  49. #define NUM_ATTEMPTS 5
  50. #define COMP_MAX_COEFF 25
  51. #define HPH_MODE_MAX 4
  52. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  53. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  54. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  55. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  56. #define WCD939X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  57. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  58. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  59. SNDRV_PCM_RATE_384000)
  60. /* Fractional Rates */
  61. #define WCD939X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  62. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  63. #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  64. SNDRV_PCM_FMTBIT_S24_LE |\
  65. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  66. #define REG_FIELD_VALUE(register_name, field_name, value) \
  67. WCD939X_##register_name, FIELD_MASK(register_name, field_name), \
  68. value << FIELD_SHIFT(register_name, field_name)
  69. #define WCD939X_COMP_OFFSET \
  70. (WCD939X_R_BASE - WCD939X_COMPANDER_HPHL_BASE)
  71. #define WCD939X_XTALK_OFFSET \
  72. (WCD939X_HPHR_RX_PATH_SEC0 - WCD939X_HPHL_RX_PATH_SEC0)
  73. enum {
  74. CODEC_TX = 0,
  75. CODEC_RX,
  76. };
  77. enum {
  78. WCD_ADC1 = 0,
  79. WCD_ADC2,
  80. WCD_ADC3,
  81. WCD_ADC4,
  82. ALLOW_BUCK_DISABLE,
  83. HPH_COMP_DELAY,
  84. HPH_PA_DELAY,
  85. AMIC2_BCS_ENABLE,
  86. WCD_SUPPLIES_LPM_MODE,
  87. WCD_ADC1_MODE,
  88. WCD_ADC2_MODE,
  89. WCD_ADC3_MODE,
  90. WCD_ADC4_MODE,
  91. };
  92. enum {
  93. ADC_MODE_INVALID = 0,
  94. ADC_MODE_HIFI,
  95. ADC_MODE_LO_HIF,
  96. ADC_MODE_NORMAL,
  97. ADC_MODE_LP,
  98. ADC_MODE_ULP1,
  99. ADC_MODE_ULP2,
  100. };
  101. enum {
  102. SUPPLY_LEVEL_2VPK,
  103. REGULATOR_MODE_2VPK,
  104. SET_HPH_GAIN_2VPK,
  105. };
  106. static u8 tx_mode_bit[] = {
  107. [ADC_MODE_INVALID] = 0x00,
  108. [ADC_MODE_HIFI] = 0x01,
  109. [ADC_MODE_LO_HIF] = 0x02,
  110. [ADC_MODE_NORMAL] = 0x04,
  111. [ADC_MODE_LP] = 0x08,
  112. [ADC_MODE_ULP1] = 0x10,
  113. [ADC_MODE_ULP2] = 0x20,
  114. };
  115. extern const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS];
  116. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(hph_analog_gain, 600, -3000);
  117. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  118. /* Will be set by reading the registers during bind()*/
  119. static int wcd939x_version = WCD939X_VERSION_2_0;
  120. static int wcd939x_handle_post_irq(void *data);
  121. static int wcd939x_reset(struct device *dev);
  122. static int wcd939x_reset_low(struct device *dev);
  123. static int wcd939x_get_adc_mode(int val);
  124. static void wcd939x_config_2Vpk_mode(struct snd_soc_component *component,
  125. struct wcd939x_priv *wcd939x, int mode_2vpk);
  126. static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
  127. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  128. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  129. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  130. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  131. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
  132. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
  133. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
  134. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
  135. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
  136. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
  137. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
  138. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  139. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  140. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
  141. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  142. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  143. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  144. };
  145. static struct regmap_irq_chip wcd939x_regmap_irq_chip = {
  146. .name = "wcd939x",
  147. .irqs = wcd939x_irqs,
  148. .num_irqs = ARRAY_SIZE(wcd939x_irqs),
  149. .num_regs = 3,
  150. .status_base = WCD939X_INTR_STATUS_0,
  151. .mask_base = WCD939X_INTR_MASK_0,
  152. .type_base = WCD939X_INTR_LEVEL_0,
  153. .ack_base = WCD939X_INTR_CLEAR_0,
  154. .use_ack = 1,
  155. .runtime_pm = false,
  156. .handle_post_irq = wcd939x_handle_post_irq,
  157. .irq_drv_data = NULL,
  158. };
  159. static bool wcd939x_readable_register(struct device *dev, unsigned int reg)
  160. {
  161. if (reg <= WCD939X_BASE + 1)
  162. return 0;
  163. if (reg >= WCD939X_FLYBACK_NEW_CTRL_2 && reg <= WCD939X_FLYBACK_NEW_CTRL_4) {
  164. if (wcd939x_version == WCD939X_VERSION_1_0)
  165. return 0;
  166. }
  167. return wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG;
  168. }
  169. static int wcd939x_handle_post_irq(void *data)
  170. {
  171. struct wcd939x_priv *wcd939x = data;
  172. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  173. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_0, &sts1);
  174. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_1, &sts2);
  175. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_2, &sts3);
  176. wcd939x->tx_swr_dev->slave_irq_pending =
  177. ((sts1 || sts2 || sts3) ? true : false);
  178. return IRQ_HANDLED;
  179. }
  180. static int wcd939x_hph_compander_get(struct snd_kcontrol *kcontrol,
  181. struct snd_ctl_elem_value *ucontrol)
  182. {
  183. struct snd_soc_component *component =
  184. snd_soc_kcontrol_component(kcontrol);
  185. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  186. int compander = ((struct soc_multi_mixer_control *)
  187. kcontrol->private_value)->shift;
  188. ucontrol->value.integer.value[0] = wcd939x->compander_enabled[compander];
  189. return 0;
  190. }
  191. static int wcd939x_hph_compander_put(struct snd_kcontrol *kcontrol,
  192. struct snd_ctl_elem_value *ucontrol)
  193. {
  194. struct snd_soc_component *component =
  195. snd_soc_kcontrol_component(kcontrol);
  196. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  197. int compander = ((struct soc_multi_mixer_control *)
  198. kcontrol->private_value)->shift;
  199. int value = ucontrol->value.integer.value[0];
  200. if (value < WCD939X_HPH_MAX && value >= 0)
  201. wcd939x->compander_enabled[compander] = value;
  202. else {
  203. dev_err(component->dev, "%s: Invalid comp value = %d\n", __func__, value);
  204. return -EINVAL;
  205. }
  206. dev_dbg(component->dev, "%s: Compander %d value %d\n",
  207. __func__, wcd939x->compander_enabled[compander], value);
  208. return 0;
  209. }
  210. static int wcd939x_hph_xtalk_put(struct snd_kcontrol *kcontrol,
  211. struct snd_ctl_elem_value *ucontrol)
  212. {
  213. struct snd_soc_component *component =
  214. snd_soc_kcontrol_component(kcontrol);
  215. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  216. int xtalk = ((struct soc_multi_mixer_control *)
  217. kcontrol->private_value)->shift;
  218. int value = ucontrol->value.integer.value[0];
  219. if (value < WCD939X_HPH_MAX && value >= 0)
  220. wcd939x->xtalk_enabled[xtalk] = value;
  221. else {
  222. dev_err(component->dev, "%s: Invalid xtalk value = %d\n", __func__, value);
  223. return -EINVAL;
  224. }
  225. dev_dbg(component->dev, "%s: xtalk %d value %d\n",
  226. __func__, wcd939x->xtalk_enabled[xtalk], value);
  227. return 0;
  228. }
  229. static int wcd939x_hph_xtalk_get(struct snd_kcontrol *kcontrol,
  230. struct snd_ctl_elem_value *ucontrol)
  231. {
  232. struct snd_soc_component *component =
  233. snd_soc_kcontrol_component(kcontrol);
  234. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  235. int xtalk = ((struct soc_multi_mixer_control *)
  236. kcontrol->private_value)->shift;
  237. ucontrol->value.integer.value[0] = wcd939x->xtalk_enabled[xtalk];
  238. return 0;
  239. }
  240. static int wcd939x_hph_pcm_enable_put(struct snd_kcontrol *kcontrol,
  241. struct snd_ctl_elem_value *ucontrol)
  242. {
  243. struct snd_soc_component *component =
  244. snd_soc_kcontrol_component(kcontrol);
  245. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  246. wcd939x->hph_pcm_enabled = ucontrol->value.integer.value[0];
  247. dev_dbg(component->dev, "%s: pcm enabled %d \n",
  248. __func__, wcd939x->hph_pcm_enabled);
  249. return 0;
  250. }
  251. static int wcd939x_hph_pcm_enable_get(struct snd_kcontrol *kcontrol,
  252. struct snd_ctl_elem_value *ucontrol)
  253. {
  254. struct snd_soc_component *component =
  255. snd_soc_kcontrol_component(kcontrol);
  256. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  257. ucontrol->value.integer.value[0] = wcd939x->hph_pcm_enabled;
  258. return 0;
  259. }
  260. static int wcd939x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  261. {
  262. int ret = 0;
  263. int bank = 0;
  264. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  265. if (ret)
  266. return -EINVAL;
  267. return ((bank & 0x40) ? 1: 0);
  268. }
  269. static int wcd939x_get_clk_rate(int mode)
  270. {
  271. int rate;
  272. switch (mode) {
  273. case ADC_MODE_ULP2:
  274. rate = SWR_CLK_RATE_0P6MHZ;
  275. break;
  276. case ADC_MODE_ULP1:
  277. rate = SWR_CLK_RATE_1P2MHZ;
  278. break;
  279. case ADC_MODE_LP:
  280. rate = SWR_CLK_RATE_4P8MHZ;
  281. break;
  282. case ADC_MODE_NORMAL:
  283. case ADC_MODE_LO_HIF:
  284. case ADC_MODE_HIFI:
  285. case ADC_MODE_INVALID:
  286. default:
  287. rate = SWR_CLK_RATE_9P6MHZ;
  288. break;
  289. }
  290. return rate;
  291. }
  292. static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component,
  293. int rate, int bank)
  294. {
  295. u8 mask = (bank ? 0xF0 : 0x0F);
  296. u8 val = 0;
  297. switch (rate) {
  298. case SWR_CLK_RATE_0P6MHZ:
  299. val = (bank ? 0x60 : 0x06);
  300. break;
  301. case SWR_CLK_RATE_1P2MHZ:
  302. val = (bank ? 0x50 : 0x05);
  303. break;
  304. case SWR_CLK_RATE_2P4MHZ:
  305. val = (bank ? 0x30 : 0x03);
  306. break;
  307. case SWR_CLK_RATE_4P8MHZ:
  308. val = (bank ? 0x10 : 0x01);
  309. break;
  310. case SWR_CLK_RATE_9P6MHZ:
  311. default:
  312. val = 0x00;
  313. break;
  314. }
  315. snd_soc_component_update_bits(component,
  316. WCD939X_SWR_TX_CLK_RATE,
  317. mask, val);
  318. return 0;
  319. }
  320. static int wcd939x_init_reg(struct snd_soc_component *component)
  321. {
  322. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  323. snd_soc_component_update_bits(component,
  324. REG_FIELD_VALUE(BIAS, ANALOG_BIAS_EN, 0x01));
  325. snd_soc_component_update_bits(component,
  326. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x01));
  327. /* 10 msec delay as per HW requirement */
  328. usleep_range(10000, 10010);
  329. snd_soc_component_update_bits(component,
  330. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x00));
  331. snd_soc_component_update_bits(component,
  332. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x15));
  333. snd_soc_component_update_bits(component,
  334. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x15));
  335. snd_soc_component_update_bits(component,
  336. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  337. snd_soc_component_update_bits(component,
  338. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_SCBIAS_ULP0P6M, 0x1));
  339. snd_soc_component_update_bits(component,
  340. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_STG2CASC_ULP, 0x4));
  341. snd_soc_component_update_bits(component,
  342. REG_FIELD_VALUE(TXFE_ICTRL_STG2MAIN_ULP, ICTRL_STG2MAIN_ULP, 0x08));
  343. snd_soc_component_update_bits(component,
  344. REG_FIELD_VALUE(TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  345. snd_soc_component_update_bits(component,
  346. REG_FIELD_VALUE(MICB2_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  347. snd_soc_component_update_bits(component,
  348. REG_FIELD_VALUE(MICB3_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  349. snd_soc_component_update_bits(component,
  350. REG_FIELD_VALUE(MICB4_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  351. snd_soc_component_update_bits(component,
  352. REG_FIELD_VALUE(TEST_BLK_EN2, TXFE2_MBHC_CLKRST_EN, 0x00));
  353. if (of_find_property(component->card->dev->of_node, "qcom,wcd-disable-legacy-surge", NULL)) {
  354. snd_soc_component_update_bits(component,
  355. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x00));
  356. snd_soc_component_update_bits(component,
  357. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x00));
  358. }
  359. else {
  360. snd_soc_component_update_bits(component,
  361. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x01));
  362. snd_soc_component_update_bits(component,
  363. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x01));
  364. }
  365. snd_soc_component_update_bits(component,
  366. REG_FIELD_VALUE(HPH_OCP_CTL, OCP_FSM_EN, 0x01));
  367. snd_soc_component_update_bits(component,
  368. REG_FIELD_VALUE(HPH_OCP_CTL, SCD_OP_EN, 0x01));
  369. if (wcd939x->version != WCD939X_VERSION_2_0)
  370. snd_soc_component_write(component, WCD939X_CFG0, 0x05);
  371. /*
  372. * Disable 1M pull-up by default during boot by writing 0b1 to bit[7].
  373. * This gets re-enabled when headset is inserted.
  374. */
  375. snd_soc_component_update_bits(component, WCD939X_ZDET_BIAS_CTL, 0x80, 0x80);
  376. return 0;
  377. }
  378. static int wcd939x_set_port_params(struct snd_soc_component *component,
  379. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  380. u8 *ch_mask, u32 *ch_rate,
  381. u8 *port_type, u8 path)
  382. {
  383. int i, j;
  384. u8 num_ports = 0;
  385. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  386. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  387. switch (path) {
  388. case CODEC_RX:
  389. map = &wcd939x->rx_port_mapping;
  390. num_ports = wcd939x->num_rx_ports;
  391. break;
  392. case CODEC_TX:
  393. map = &wcd939x->tx_port_mapping;
  394. num_ports = wcd939x->num_tx_ports;
  395. break;
  396. default:
  397. dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
  398. __func__, path);
  399. return -EINVAL;
  400. }
  401. for (i = 0; i <= num_ports; i++) {
  402. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  403. if ((*map)[i][j].slave_port_type == slv_prt_type)
  404. goto found;
  405. }
  406. }
  407. found:
  408. if (i > num_ports || j == MAX_CH_PER_PORT) {
  409. dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
  410. __func__, slv_prt_type);
  411. return -EINVAL;
  412. }
  413. *port_id = i;
  414. *num_ch = (*map)[i][j].num_ch;
  415. *ch_mask = (*map)[i][j].ch_mask;
  416. *ch_rate = (*map)[i][j].ch_rate;
  417. *port_type = (*map)[i][j].master_port_type;
  418. return 0;
  419. }
  420. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  421. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  422. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  423. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  424. static int wcd939x_parse_port_params(struct device *dev,
  425. char *prop, u8 path)
  426. {
  427. u32 *dt_array, map_size, max_uc;
  428. int ret = 0;
  429. u32 cnt = 0;
  430. u32 i, j;
  431. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  432. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  433. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  434. switch (path) {
  435. case CODEC_TX:
  436. map = &wcd939x->tx_port_params;
  437. map_uc = &wcd939x->swr_tx_port_params;
  438. break;
  439. default:
  440. ret = -EINVAL;
  441. goto err_port_map;
  442. }
  443. if (!of_find_property(dev->of_node, prop,
  444. &map_size)) {
  445. dev_err(dev, "missing port mapping prop %s\n", prop);
  446. ret = -EINVAL;
  447. goto err_port_map;
  448. }
  449. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  450. if (max_uc != SWR_UC_MAX) {
  451. dev_err(dev, "%s: port params not provided for all usecases\n",
  452. __func__);
  453. ret = -EINVAL;
  454. goto err_port_map;
  455. }
  456. dt_array = kzalloc(map_size, GFP_KERNEL);
  457. if (!dt_array) {
  458. ret = -ENOMEM;
  459. goto err_alloc;
  460. }
  461. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  462. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  463. if (ret) {
  464. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  465. __func__, prop);
  466. goto err_pdata_fail;
  467. }
  468. for (i = 0; i < max_uc; i++) {
  469. for (j = 0; j < SWR_NUM_PORTS; j++) {
  470. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  471. (*map)[i][j].offset1 = dt_array[cnt];
  472. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  473. }
  474. (*map_uc)[i].pp = &(*map)[i][0];
  475. }
  476. kfree(dt_array);
  477. return 0;
  478. err_pdata_fail:
  479. kfree(dt_array);
  480. err_alloc:
  481. err_port_map:
  482. return ret;
  483. }
  484. static int wcd939x_parse_port_mapping(struct device *dev,
  485. char *prop, u8 path)
  486. {
  487. u32 *dt_array, map_size, map_length;
  488. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  489. u32 slave_port_type, master_port_type;
  490. u32 i, ch_iter = 0;
  491. int ret = 0;
  492. u8 *num_ports = NULL;
  493. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  494. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  495. switch (path) {
  496. case CODEC_RX:
  497. map = &wcd939x->rx_port_mapping;
  498. num_ports = &wcd939x->num_rx_ports;
  499. break;
  500. case CODEC_TX:
  501. map = &wcd939x->tx_port_mapping;
  502. num_ports = &wcd939x->num_tx_ports;
  503. break;
  504. default:
  505. dev_err(dev, "%s Invalid path selected %u\n",
  506. __func__, path);
  507. return -EINVAL;
  508. }
  509. if (!of_find_property(dev->of_node, prop,
  510. &map_size)) {
  511. dev_err(dev, "missing port mapping prop %s\n", prop);
  512. ret = -EINVAL;
  513. goto err_port_map;
  514. }
  515. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  516. dt_array = kzalloc(map_size, GFP_KERNEL);
  517. if (!dt_array) {
  518. ret = -ENOMEM;
  519. goto err_alloc;
  520. }
  521. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  522. NUM_SWRS_DT_PARAMS * map_length);
  523. if (ret) {
  524. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  525. __func__, prop);
  526. goto err_pdata_fail;
  527. }
  528. for (i = 0; i < map_length; i++) {
  529. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  530. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  531. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  532. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  533. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  534. if (port_num != old_port_num)
  535. ch_iter = 0;
  536. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  537. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  538. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  539. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  540. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  541. old_port_num = port_num;
  542. }
  543. *num_ports = port_num;
  544. kfree(dt_array);
  545. return 0;
  546. err_pdata_fail:
  547. kfree(dt_array);
  548. err_alloc:
  549. err_port_map:
  550. return ret;
  551. }
  552. static int wcd939x_tx_connect_port(struct snd_soc_component *component,
  553. u8 slv_port_type, int clk_rate,
  554. u8 enable)
  555. {
  556. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  557. u8 port_id, num_ch, ch_mask;
  558. u8 ch_type = 0;
  559. u32 ch_rate;
  560. int slave_ch_idx;
  561. u8 num_port = 1;
  562. int ret = 0;
  563. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  564. &num_ch, &ch_mask, &ch_rate,
  565. &ch_type, CODEC_TX);
  566. if (ret)
  567. return ret;
  568. if (clk_rate)
  569. ch_rate = clk_rate;
  570. slave_ch_idx = wcd939x_slave_get_slave_ch_val(slv_port_type);
  571. if (slave_ch_idx != -EINVAL)
  572. ch_type = wcd939x->tx_master_ch_map[slave_ch_idx];
  573. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  574. __func__, slave_ch_idx, ch_type);
  575. if (enable)
  576. ret = swr_connect_port(wcd939x->tx_swr_dev, &port_id,
  577. num_port, &ch_mask, &ch_rate,
  578. &num_ch, &ch_type);
  579. else
  580. ret = swr_disconnect_port(wcd939x->tx_swr_dev, &port_id,
  581. num_port, &ch_mask, &ch_type);
  582. return ret;
  583. }
  584. static int wcd939x_rx_connect_port(struct snd_soc_component *component,
  585. u8 slv_port_type, u8 enable)
  586. {
  587. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  588. u8 port_id, num_ch, ch_mask, port_type;
  589. u32 ch_rate;
  590. u8 num_port = 1;
  591. int ret = 0;
  592. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  593. &num_ch, &ch_mask, &ch_rate,
  594. &port_type, CODEC_RX);
  595. if (ret)
  596. return ret;
  597. if (enable)
  598. ret = swr_connect_port(wcd939x->rx_swr_dev, &port_id,
  599. num_port, &ch_mask, &ch_rate,
  600. &num_ch, &port_type);
  601. else
  602. ret = swr_disconnect_port(wcd939x->rx_swr_dev, &port_id,
  603. num_port, &ch_mask, &port_type);
  604. return ret;
  605. }
  606. static int wcd939x_rx_clk_enable(struct snd_soc_component *component, int rx_num)
  607. {
  608. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  609. dev_dbg(component->dev, "%s rx_clk_cnt: %d\n", __func__, wcd939x->rx_clk_cnt);
  610. if (wcd939x->rx_clk_cnt == 0) {
  611. snd_soc_component_update_bits(component,
  612. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x01));
  613. /*Analog path clock controls*/
  614. snd_soc_component_update_bits(component,
  615. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x01));
  616. snd_soc_component_update_bits(component,
  617. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x01));
  618. snd_soc_component_update_bits(component,
  619. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x01));
  620. /*Digital path clock controls*/
  621. snd_soc_component_update_bits(component,
  622. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
  623. snd_soc_component_update_bits(component,
  624. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x01));
  625. snd_soc_component_update_bits(component,
  626. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x01));
  627. }
  628. wcd939x->rx_clk_cnt++;
  629. return 0;
  630. }
  631. static int wcd939x_rx_clk_disable(struct snd_soc_component *component)
  632. {
  633. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  634. dev_dbg(component->dev, "%s rx_clk_cnt: %d\n", __func__, wcd939x->rx_clk_cnt);
  635. if (wcd939x->rx_clk_cnt == 0)
  636. return 0;
  637. wcd939x->rx_clk_cnt--;
  638. if (wcd939x->rx_clk_cnt == 0) {
  639. snd_soc_component_update_bits(component,
  640. REG_FIELD_VALUE(RX_SUPPLIES, VNEG_EN, 0x00));
  641. snd_soc_component_update_bits(component,
  642. REG_FIELD_VALUE(RX_SUPPLIES, VPOS_EN, 0x00));
  643. snd_soc_component_update_bits(component,
  644. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x00));
  645. snd_soc_component_update_bits(component,
  646. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x00));
  647. snd_soc_component_update_bits(component,
  648. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
  649. snd_soc_component_update_bits(component,
  650. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x00));
  651. snd_soc_component_update_bits(component,
  652. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x00));
  653. snd_soc_component_update_bits(component,
  654. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x00));
  655. snd_soc_component_update_bits(component,
  656. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x00));
  657. }
  658. return 0;
  659. }
  660. /*
  661. * wcd939x_soc_get_mbhc: get wcd939x_mbhc handle of corresponding component
  662. * @component: handle to snd_soc_component *
  663. *
  664. * return wcd939x_mbhc handle or error code in case of failure
  665. */
  666. struct wcd939x_mbhc *wcd939x_soc_get_mbhc(struct snd_soc_component *component)
  667. {
  668. struct wcd939x_priv *wcd939x;
  669. if (!component) {
  670. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  671. return NULL;
  672. }
  673. wcd939x = snd_soc_component_get_drvdata(component);
  674. if (!wcd939x) {
  675. pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
  676. return NULL;
  677. }
  678. return wcd939x->mbhc;
  679. }
  680. EXPORT_SYMBOL(wcd939x_soc_get_mbhc);
  681. static int wcd939x_config_power_mode(struct snd_soc_component *component,
  682. int event, int index, int mode)
  683. {
  684. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  685. switch (event) {
  686. case SND_SOC_DAPM_PRE_PMU:
  687. if (mode == CLS_H_ULP) {
  688. snd_soc_component_update_bits(component,
  689. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFP_IOUT_CTL, 0x1));
  690. snd_soc_component_update_bits(component,
  691. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFN_IOUT_CTL, 0x1));
  692. if (wcd939x->compander_enabled[index]) {
  693. if (index == WCD939X_HPHL) {
  694. snd_soc_component_update_bits(component,
  695. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x21));
  696. snd_soc_component_update_bits(component,
  697. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x30));
  698. snd_soc_component_update_bits(component,
  699. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x3F));
  700. snd_soc_component_update_bits(component,
  701. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x48));
  702. snd_soc_component_update_bits(component,
  703. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x0C));
  704. } else if (index == WCD939X_HPHR) {
  705. snd_soc_component_update_bits(component,
  706. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x21));
  707. snd_soc_component_update_bits(component,
  708. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x30));
  709. snd_soc_component_update_bits(component,
  710. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x3F));
  711. snd_soc_component_update_bits(component,
  712. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x48));
  713. snd_soc_component_update_bits(component,
  714. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x0C));
  715. }
  716. }
  717. } else {
  718. if (wcd939x->compander_enabled[index]) {
  719. if (index == WCD939X_HPHL) {
  720. snd_soc_component_update_bits(component,
  721. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x1E));
  722. snd_soc_component_update_bits(component,
  723. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x2A));
  724. snd_soc_component_update_bits(component,
  725. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x36));
  726. snd_soc_component_update_bits(component,
  727. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x3C));
  728. snd_soc_component_update_bits(component,
  729. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x00));
  730. } else if (index == WCD939X_HPHR) {
  731. snd_soc_component_update_bits(component,
  732. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x1E));
  733. snd_soc_component_update_bits(component,
  734. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x2A));
  735. snd_soc_component_update_bits(component,
  736. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x36));
  737. snd_soc_component_update_bits(component,
  738. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x3C));
  739. snd_soc_component_update_bits(component,
  740. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x00));
  741. }
  742. }
  743. }
  744. break;
  745. case SND_SOC_DAPM_POST_PMD:
  746. if (mode == CLS_H_ULP) {
  747. snd_soc_component_update_bits(component,
  748. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFN_IOUT_CTL, 0x0));
  749. snd_soc_component_update_bits(component,
  750. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFP_IOUT_CTL, 0x0));
  751. }
  752. break;
  753. }
  754. return 0;
  755. }
  756. static int wcd939x_get_usbss_hph_power_mode(int hph_mode)
  757. {
  758. switch (hph_mode) {
  759. case CLS_H_HIFI:
  760. case CLS_H_LOHIFI:
  761. return 0x4;
  762. default:
  763. /* set default mode to ULP */
  764. return 0x2;
  765. }
  766. }
  767. static int wcd939x_enable_hph_pcm_index(struct snd_soc_component *component,
  768. int event, int hph)
  769. {
  770. struct wcd939x_priv *wcd939x = NULL;
  771. if (!component) {
  772. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  773. return -EINVAL;
  774. }
  775. wcd939x = snd_soc_component_get_drvdata(component);
  776. if (!wcd939x->hph_pcm_enabled)
  777. return 0;
  778. switch (event) {
  779. case SND_SOC_DAPM_POST_PMU:
  780. if (hph == WCD939X_HPHL) {
  781. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  782. snd_soc_component_update_bits(component,
  783. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  784. RX_DC_DROOP_COEFF_SEL, 0x2));
  785. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  786. snd_soc_component_update_bits(component,
  787. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  788. RX_DC_DROOP_COEFF_SEL, 0x3));
  789. snd_soc_component_update_bits(component,
  790. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  791. DLY_ZN_EN, 0x1));
  792. snd_soc_component_update_bits(component,
  793. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  794. INT_EN, 0x3));
  795. } else if (hph == WCD939X_HPHR) {
  796. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  797. snd_soc_component_update_bits(component,
  798. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  799. RX_DC_DROOP_COEFF_SEL, 0x2));
  800. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  801. snd_soc_component_update_bits(component,
  802. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  803. RX_DC_DROOP_COEFF_SEL, 0x3));
  804. snd_soc_component_update_bits(component,
  805. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  806. DLY_ZN_EN, 0x1));
  807. snd_soc_component_update_bits(component,
  808. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  809. INT_EN, 0x3));
  810. }
  811. break;
  812. case SND_SOC_DAPM_POST_PMD:
  813. break;
  814. }
  815. return 0;
  816. }
  817. static int wcd939x_config_compander(struct snd_soc_component *component,
  818. int event, int compander_indx)
  819. {
  820. u16 comp_ctl7_reg = 0, comp_ctl0_reg = 0;
  821. u16 comp_en_mask_val = 0, gain_source_sel = 0;
  822. struct wcd939x_priv *wcd939x;
  823. if (compander_indx >= WCD939X_HPH_MAX || compander_indx < 0) {
  824. pr_err_ratelimited("%s: Invalid compander value: %d\n",
  825. __func__, compander_indx);
  826. return -EINVAL;
  827. }
  828. if (!component) {
  829. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  830. return -EINVAL;
  831. }
  832. wcd939x = snd_soc_component_get_drvdata(component);
  833. if (!wcd939x->hph_pcm_enabled)
  834. return 0;
  835. dev_dbg(component->dev, "%s compander_index = %d\n", __func__, compander_indx);
  836. if (!wcd939x->compander_enabled[compander_indx]) {
  837. if (SND_SOC_DAPM_EVENT_ON(event))
  838. gain_source_sel = 0x01;
  839. else
  840. gain_source_sel = 0x00;
  841. if (compander_indx == WCD939X_HPHL) {
  842. snd_soc_component_update_bits(component,
  843. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, gain_source_sel));
  844. } else if (compander_indx == WCD939X_HPHR) {
  845. snd_soc_component_update_bits(component,
  846. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, gain_source_sel));
  847. }
  848. wcd939x_config_2Vpk_mode(component, wcd939x, SET_HPH_GAIN_2VPK);
  849. return 0;
  850. }
  851. if (compander_indx == WCD939X_HPHL)
  852. comp_en_mask_val = 1 << 1;
  853. else if (compander_indx == WCD939X_HPHR)
  854. comp_en_mask_val = 1 << 0;
  855. else
  856. return 0;
  857. comp_ctl0_reg = WCD939X_CTL0 + (compander_indx * WCD939X_COMP_OFFSET);
  858. comp_ctl7_reg = WCD939X_CTL7 + (compander_indx * WCD939X_COMP_OFFSET);
  859. if (SND_SOC_DAPM_EVENT_ON(event)) {
  860. snd_soc_component_update_bits(component,
  861. comp_ctl7_reg, 0x1E, 0x00);
  862. /* Enable compander clock*/
  863. snd_soc_component_update_bits(component,
  864. comp_ctl0_reg , 0x01, 0x01);
  865. /* 250us sleep required as per HW Sequence */
  866. usleep_range(250, 260);
  867. snd_soc_component_update_bits(component,
  868. comp_ctl0_reg, 0x02, 0x02);
  869. snd_soc_component_update_bits(component,
  870. comp_ctl0_reg, 0x02, 0x00);
  871. /* Enable compander*/
  872. snd_soc_component_update_bits(component,
  873. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, comp_en_mask_val);
  874. } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
  875. snd_soc_component_update_bits(component,
  876. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, 0x00);
  877. snd_soc_component_update_bits(component,
  878. comp_ctl0_reg , 0x01, 0x00);
  879. if (compander_indx == WCD939X_HPHL)
  880. snd_soc_component_update_bits(component,
  881. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x0));
  882. if (compander_indx == WCD939X_HPHR)
  883. snd_soc_component_update_bits(component,
  884. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x0));
  885. }
  886. return 0;
  887. }
  888. static int wcd939x_config_xtalk(struct snd_soc_component *component,
  889. int event, int xtalk_indx)
  890. {
  891. u16 xtalk_sec0 = 0, xtalk_sec1 = 0, xtalk_sec2 = 0, xtalk_sec3 = 0;
  892. struct wcd939x_priv *wcd939x = NULL;
  893. struct wcd939x_pdata *pdata = NULL;
  894. if (!component) {
  895. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  896. return -EINVAL;
  897. }
  898. wcd939x = snd_soc_component_get_drvdata(component);
  899. if (!wcd939x->xtalk_enabled[xtalk_indx])
  900. return 0;
  901. pdata = dev_get_platdata(wcd939x->dev);
  902. dev_dbg(component->dev, "%s xtalk_indx = %d event = %d\n",
  903. __func__, xtalk_indx, event);
  904. switch(event) {
  905. case SND_SOC_DAPM_PRE_PMU:
  906. xtalk_sec0 = WCD939X_HPHL_RX_PATH_SEC0 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  907. xtalk_sec1 = WCD939X_HPHL_RX_PATH_SEC1 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  908. xtalk_sec2 = WCD939X_HPHL_RX_PATH_SEC2 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  909. xtalk_sec3 = WCD939X_HPHL_RX_PATH_SEC3 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  910. /* Write scale and alpha based on channel */
  911. if (xtalk_indx == XTALK_L_CH_NUM) {
  912. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF,
  913. pdata->usbcss_hs.xtalk.alpha_l);
  914. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F,
  915. pdata->usbcss_hs.xtalk.scale_l);
  916. } else if (xtalk_indx == XTALK_R_CH_NUM) {
  917. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF,
  918. pdata->usbcss_hs.xtalk.alpha_r);
  919. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F,
  920. pdata->usbcss_hs.xtalk.scale_r);
  921. } else {
  922. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF, MIN_XTALK_ALPHA);
  923. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F, MAX_XTALK_SCALE);
  924. }
  925. dev_dbg(component->dev, "%s Scale = 0x%x, Alpha = 0x%x\n", __func__,
  926. snd_soc_component_read(component, xtalk_sec0),
  927. snd_soc_component_read(component, xtalk_sec1));
  928. snd_soc_component_update_bits(component, xtalk_sec3, 0xFF, 0x4F);
  929. snd_soc_component_update_bits(component, xtalk_sec2, 0x1F, 0x11);
  930. break;
  931. case SND_SOC_DAPM_POST_PMU:
  932. /* enable xtalk for L and R channels*/
  933. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  934. 0x0F, 0x0F);
  935. break;
  936. case SND_SOC_DAPM_POST_PMD:
  937. /* Disable Xtalk for L and R channels*/
  938. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  939. 0x00, 0x00);
  940. break;
  941. }
  942. return 0;
  943. }
  944. static int wcd939x_rx3_mux(struct snd_soc_dapm_widget *w,
  945. struct snd_kcontrol *kcontrol, int event)
  946. {
  947. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  948. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  949. __func__, event, w->shift, w->name);
  950. switch (event) {
  951. case SND_SOC_DAPM_PRE_PMU:
  952. wcd939x_rx_clk_enable(component, w->shift);
  953. break;
  954. case SND_SOC_DAPM_POST_PMD:
  955. wcd939x_rx_clk_disable(component);
  956. break;
  957. }
  958. return 0;
  959. }
  960. static int wcd939x_rx_mux(struct snd_soc_dapm_widget *w,
  961. struct snd_kcontrol *kcontrol,
  962. int event)
  963. {
  964. int hph_mode = 0;
  965. struct wcd939x_priv *wcd939x = NULL;
  966. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  967. wcd939x = snd_soc_component_get_drvdata(component);
  968. hph_mode = wcd939x->hph_mode;
  969. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  970. __func__, event, w->shift, w->name);
  971. switch (event) {
  972. case SND_SOC_DAPM_PRE_PMU:
  973. wcd939x_rx_clk_enable(component, w->shift);
  974. if (wcd939x->hph_pcm_enabled)
  975. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  976. wcd939x_config_compander(component, event, w->shift);
  977. wcd939x_config_xtalk(component, event, w->shift);
  978. break;
  979. case SND_SOC_DAPM_POST_PMU:
  980. wcd939x_config_xtalk(component, event, w->shift);
  981. /*TBD: need to revisit , for both L & R we are updating, but in QCRG only once*/
  982. if (wcd939x->hph_pcm_enabled) {
  983. if (hph_mode == CLS_H_HIFI || hph_mode == CLS_AB_HIFI)
  984. snd_soc_component_update_bits(component,
  985. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x1));
  986. else
  987. snd_soc_component_update_bits(component,
  988. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x0));
  989. }
  990. wcd939x_enable_hph_pcm_index(component, event, w->shift);
  991. break;
  992. case SND_SOC_DAPM_POST_PMD:
  993. wcd939x_config_xtalk(component, event, w->shift);
  994. wcd939x_config_compander(component, event, w->shift);
  995. if (wcd939x->hph_pcm_enabled)
  996. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  997. wcd939x_rx_clk_disable(component);
  998. break;
  999. }
  1000. return 0;
  1001. }
  1002. static void wcd939x_config_2Vpk_mode(struct snd_soc_component *component,
  1003. struct wcd939x_priv *wcd939x, int mode_2vpk)
  1004. {
  1005. uint32_t zl = 0, zr = 0;
  1006. int rc;
  1007. if (!wcd939x->in_2Vpk_mode)
  1008. return;
  1009. rc = wcd_mbhc_get_impedance(&wcd939x->mbhc->wcd_mbhc, &zl, &zr);
  1010. if (rc) {
  1011. dev_err_ratelimited(component->dev, "%s: Unable to get impedance for 2Vpk mode", __func__);
  1012. return;
  1013. }
  1014. switch (mode_2vpk) {
  1015. case SUPPLY_LEVEL_2VPK:
  1016. snd_soc_component_update_bits(component,
  1017. REG_FIELD_VALUE(PA_GAIN_CTL_L, RX_SUPPLY_LEVEL, 0x01));
  1018. if (zl < HPH_IMPEDANCE_2VPK_MODE_OHMS)
  1019. snd_soc_component_update_bits(component,
  1020. REG_FIELD_VALUE(PA_GAIN_CTL_L, EN_HPHPA_2VPK, 0x00));
  1021. else
  1022. snd_soc_component_update_bits(component,
  1023. REG_FIELD_VALUE(PA_GAIN_CTL_L, EN_HPHPA_2VPK, 0x01));
  1024. break;
  1025. case REGULATOR_MODE_2VPK:
  1026. if (zl >= HPH_IMPEDANCE_2VPK_MODE_OHMS) {
  1027. snd_soc_component_update_bits(component,
  1028. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1029. snd_soc_component_update_bits(component, WCD939X_FLYBACK_TEST_CTL,
  1030. 0x0F, 0x02);
  1031. } else {
  1032. snd_soc_component_update_bits(component, WCD939X_FLYBACK_TEST_CTL,
  1033. 0x0F, 0x0D);
  1034. }
  1035. break;
  1036. case SET_HPH_GAIN_2VPK:
  1037. if (zl >= HPH_IMPEDANCE_2VPK_MODE_OHMS) {
  1038. snd_soc_component_update_bits(component, WCD939X_PA_GAIN_CTL_L, 0x1F, 0x02);
  1039. snd_soc_component_update_bits(component, WCD939X_PA_GAIN_CTL_R, 0x1F, 0x02);
  1040. }
  1041. break;
  1042. }
  1043. }
  1044. static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1045. struct snd_kcontrol *kcontrol,
  1046. int event)
  1047. {
  1048. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1049. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1050. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1051. w->name, event);
  1052. switch (event) {
  1053. case SND_SOC_DAPM_PRE_PMU:
  1054. if (!wcd939x->hph_pcm_enabled)
  1055. snd_soc_component_update_bits(component,
  1056. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1057. wcd939x_config_2Vpk_mode(component, wcd939x, SUPPLY_LEVEL_2VPK);
  1058. snd_soc_component_update_bits(component,
  1059. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x01));
  1060. break;
  1061. case SND_SOC_DAPM_POST_PMU:
  1062. snd_soc_component_update_bits(component,
  1063. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x1D));
  1064. if (!wcd939x->hph_pcm_enabled) {
  1065. if (wcd939x->comp1_enable) {
  1066. snd_soc_component_update_bits(component,
  1067. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
  1068. /* 5msec compander delay as per HW requirement */
  1069. if (!wcd939x->comp2_enable ||
  1070. (snd_soc_component_read(component,
  1071. WCD939X_CDC_COMP_CTL_0) & 0x01))
  1072. usleep_range(5000, 5010);
  1073. snd_soc_component_update_bits(component,
  1074. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1075. } else {
  1076. snd_soc_component_update_bits(component,
  1077. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
  1078. snd_soc_component_update_bits(component,
  1079. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x01));
  1080. }
  1081. }
  1082. if (wcd939x->hph_pcm_enabled) {
  1083. snd_soc_component_update_bits(component,
  1084. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1085. snd_soc_component_write(component, WCD939X_VNEG_CTRL_1, 0xEB);
  1086. if (wcd939x->hph_mode == CLS_H_LOHIFI)
  1087. snd_soc_component_write(component,
  1088. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x52);
  1089. else
  1090. snd_soc_component_write(component,
  1091. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64);
  1092. }
  1093. break;
  1094. case SND_SOC_DAPM_POST_PMD:
  1095. snd_soc_component_update_bits(component,
  1096. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x01));
  1097. snd_soc_component_update_bits(component,
  1098. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x00));
  1099. break;
  1100. }
  1101. return 0;
  1102. }
  1103. static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1104. struct snd_kcontrol *kcontrol,
  1105. int event)
  1106. {
  1107. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1108. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1109. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1110. w->name, event);
  1111. switch (event) {
  1112. case SND_SOC_DAPM_PRE_PMU:
  1113. if (!wcd939x->hph_pcm_enabled)
  1114. snd_soc_component_update_bits(component,
  1115. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1116. wcd939x_config_2Vpk_mode(component, wcd939x, SUPPLY_LEVEL_2VPK);
  1117. snd_soc_component_update_bits(component,
  1118. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x01));
  1119. break;
  1120. case SND_SOC_DAPM_POST_PMU:
  1121. snd_soc_component_update_bits(component,
  1122. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x1D));
  1123. if (!wcd939x->hph_pcm_enabled) {
  1124. if (wcd939x->comp1_enable) {
  1125. snd_soc_component_update_bits(component,
  1126. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x01));
  1127. /* 5msec compander delay as per HW requirement */
  1128. if (!wcd939x->comp2_enable ||
  1129. (snd_soc_component_read(component,
  1130. WCD939X_CDC_COMP_CTL_0) & 0x02))
  1131. usleep_range(5000, 5010);
  1132. snd_soc_component_update_bits(component,
  1133. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1134. } else {
  1135. snd_soc_component_update_bits(component,
  1136. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x00));
  1137. snd_soc_component_update_bits(component,
  1138. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x01));
  1139. }
  1140. }
  1141. if (wcd939x->hph_pcm_enabled) {
  1142. snd_soc_component_write(component, WCD939X_VNEG_CTRL_1, 0xEB);
  1143. if (wcd939x->hph_mode == CLS_H_LOHIFI)
  1144. snd_soc_component_write(component,
  1145. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x52);
  1146. else
  1147. snd_soc_component_write(component,
  1148. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64);
  1149. }
  1150. break;
  1151. case SND_SOC_DAPM_POST_PMD:
  1152. snd_soc_component_update_bits(component,
  1153. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x01));
  1154. snd_soc_component_update_bits(component,
  1155. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x00));
  1156. break;
  1157. }
  1158. return 0;
  1159. }
  1160. static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1161. struct snd_kcontrol *kcontrol,
  1162. int event)
  1163. {
  1164. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1165. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1166. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1167. w->name, event);
  1168. switch (event) {
  1169. case SND_SOC_DAPM_PRE_PMU:
  1170. snd_soc_component_update_bits(component,
  1171. REG_FIELD_VALUE(CDC_EAR_GAIN_CTL, EAR_EN, 0x01));
  1172. snd_soc_component_update_bits(component,
  1173. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x00));
  1174. /* 5 msec delay as per HW requirement */
  1175. usleep_range(5000, 5010);
  1176. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1177. WCD_CLSH_EVENT_PRE_DAC,
  1178. WCD_CLSH_STATE_EAR,
  1179. CLS_AB_HIFI);
  1180. snd_soc_component_update_bits(component,
  1181. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1182. break;
  1183. case SND_SOC_DAPM_POST_PMD:
  1184. snd_soc_component_update_bits(component,
  1185. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x01));
  1186. break;
  1187. };
  1188. return 0;
  1189. }
  1190. static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1191. struct snd_kcontrol *kcontrol,
  1192. int event)
  1193. {
  1194. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1195. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1196. int ret = 0;
  1197. int hph_mode = wcd939x->hph_mode;
  1198. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1199. w->name, event);
  1200. switch (event) {
  1201. case SND_SOC_DAPM_PRE_PMU:
  1202. if (wcd939x->ldoh)
  1203. snd_soc_component_update_bits(component,
  1204. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1205. if (wcd939x->update_wcd_event)
  1206. wcd939x->update_wcd_event(wcd939x->handle,
  1207. SLV_BOLERO_EVT_RX_MUTE,
  1208. (WCD_RX2 << 0x10 | 0x1));
  1209. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1210. wcd939x->rx_swr_dev->dev_num,
  1211. true);
  1212. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1213. WCD_CLSH_EVENT_PRE_DAC,
  1214. WCD_CLSH_STATE_HPHR,
  1215. hph_mode);
  1216. wcd939x_config_2Vpk_mode(component, wcd939x, REGULATOR_MODE_2VPK);
  1217. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1218. hph_mode == CLS_H_ULP) {
  1219. if (!wcd939x->hph_pcm_enabled)
  1220. snd_soc_component_update_bits(component,
  1221. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1222. }
  1223. /* update Mode for LOHIFI */
  1224. if (hph_mode == CLS_H_LOHIFI) {
  1225. snd_soc_component_update_bits(component,
  1226. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1227. }
  1228. /* update USBSS power mode for AATC */
  1229. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog)
  1230. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE,
  1231. wcd939x_get_usbss_hph_power_mode(hph_mode));
  1232. snd_soc_component_update_bits(component,
  1233. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1234. snd_soc_component_update_bits(component,
  1235. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x01));
  1236. if ((snd_soc_component_read(component, WCD939X_HPH) & 0x30) == 0x30)
  1237. usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
  1238. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1239. if (!wcd939x->hph_pcm_enabled)
  1240. snd_soc_component_update_bits(component,
  1241. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x03));
  1242. break;
  1243. case SND_SOC_DAPM_POST_PMU:
  1244. /*
  1245. * 7ms sleep is required if compander is enabled as per
  1246. * HW requirement. If compander is disabled, then
  1247. * 20ms delay is required.
  1248. */
  1249. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1250. if (!wcd939x->comp2_enable)
  1251. usleep_range(20000, 20100);
  1252. else
  1253. usleep_range(7000, 7100);
  1254. if (hph_mode == CLS_H_LP ||
  1255. hph_mode == CLS_H_LOHIFI ||
  1256. hph_mode == CLS_H_ULP)
  1257. if (!wcd939x->hph_pcm_enabled)
  1258. snd_soc_component_update_bits(component,
  1259. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1260. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1261. }
  1262. snd_soc_component_update_bits(component,
  1263. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1264. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1265. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1266. snd_soc_component_update_bits(component,
  1267. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1268. if (wcd939x->update_wcd_event)
  1269. wcd939x->update_wcd_event(wcd939x->handle,
  1270. SLV_BOLERO_EVT_RX_MUTE,
  1271. (WCD_RX2 << 0x10));
  1272. /*Enable PDM INT for PDM data path only*/
  1273. if (!wcd939x->hph_pcm_enabled)
  1274. wcd_enable_irq(&wcd939x->irq_info,
  1275. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1276. break;
  1277. case SND_SOC_DAPM_PRE_PMD:
  1278. if (wcd939x->update_wcd_event)
  1279. wcd939x->update_wcd_event(wcd939x->handle,
  1280. SLV_BOLERO_EVT_RX_MUTE,
  1281. (WCD_RX2 << 0x10 | 0x1));
  1282. wcd_disable_irq(&wcd939x->irq_info,
  1283. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1284. if (wcd939x->update_wcd_event && wcd939x->comp2_enable)
  1285. wcd939x->update_wcd_event(wcd939x->handle,
  1286. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1287. (WCD_RX2 << 0x10));
  1288. /*
  1289. * 7ms sleep is required if compander is enabled as per
  1290. * HW requirement. If compander is disabled, then
  1291. * 20ms delay is required.
  1292. */
  1293. if (!wcd939x->comp2_enable)
  1294. usleep_range(20000, 20100);
  1295. else
  1296. usleep_range(7000, 7100);
  1297. snd_soc_component_update_bits(component,
  1298. REG_FIELD_VALUE(HPH, HPHR_ENABLE, 0x00));
  1299. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1300. WCD_EVENT_PRE_HPHR_PA_OFF,
  1301. &wcd939x->mbhc->wcd_mbhc);
  1302. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1303. break;
  1304. case SND_SOC_DAPM_POST_PMD:
  1305. /*
  1306. * 7ms sleep is required if compander is enabled as per
  1307. * HW requirement. If compander is disabled, then
  1308. * 20ms delay is required.
  1309. */
  1310. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1311. if (!wcd939x->comp2_enable)
  1312. usleep_range(20000, 20100);
  1313. else
  1314. usleep_range(7000, 7100);
  1315. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1316. }
  1317. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1318. WCD_EVENT_POST_HPHR_PA_OFF,
  1319. &wcd939x->mbhc->wcd_mbhc);
  1320. snd_soc_component_update_bits(component,
  1321. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x00));
  1322. snd_soc_component_update_bits(component,
  1323. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x00));
  1324. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog &&
  1325. !(snd_soc_component_read(component, WCD939X_HPH) & 0XC0))
  1326. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE, 1);
  1327. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1328. WCD_CLSH_EVENT_POST_PA,
  1329. WCD_CLSH_STATE_HPHR,
  1330. hph_mode);
  1331. if (wcd939x->ldoh)
  1332. snd_soc_component_update_bits(component,
  1333. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1334. break;
  1335. };
  1336. return ret;
  1337. }
  1338. static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1339. struct snd_kcontrol *kcontrol,
  1340. int event)
  1341. {
  1342. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1343. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1344. int ret = 0;
  1345. int hph_mode = wcd939x->hph_mode;
  1346. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1347. w->name, event);
  1348. switch (event) {
  1349. case SND_SOC_DAPM_PRE_PMU:
  1350. if (wcd939x->ldoh)
  1351. snd_soc_component_update_bits(component,
  1352. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1353. if (wcd939x->update_wcd_event)
  1354. wcd939x->update_wcd_event(wcd939x->handle,
  1355. SLV_BOLERO_EVT_RX_MUTE,
  1356. (WCD_RX1 << 0x10 | 0x01));
  1357. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1358. wcd939x->rx_swr_dev->dev_num,
  1359. true);
  1360. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1361. WCD_CLSH_EVENT_PRE_DAC,
  1362. WCD_CLSH_STATE_HPHL,
  1363. hph_mode);
  1364. wcd939x_config_2Vpk_mode(component, wcd939x, REGULATOR_MODE_2VPK);
  1365. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1366. hph_mode == CLS_H_ULP) {
  1367. if (!wcd939x->hph_pcm_enabled)
  1368. snd_soc_component_update_bits(component,
  1369. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1370. }
  1371. /* update Mode for LOHIFI */
  1372. if (hph_mode == CLS_H_LOHIFI) {
  1373. snd_soc_component_update_bits(component,
  1374. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1375. }
  1376. /* update USBSS power mode for AATC */
  1377. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog)
  1378. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE,
  1379. wcd939x_get_usbss_hph_power_mode(hph_mode));
  1380. snd_soc_component_update_bits(component,
  1381. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1382. snd_soc_component_update_bits(component,
  1383. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x01));
  1384. if ((snd_soc_component_read(component, WCD939X_HPH) & 0x30) == 0x30)
  1385. usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
  1386. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1387. if (!wcd939x->hph_pcm_enabled)
  1388. snd_soc_component_update_bits(component,
  1389. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1390. break;
  1391. case SND_SOC_DAPM_POST_PMU:
  1392. /*
  1393. * 7ms sleep is required if compander is enabled as per
  1394. * HW requirement. If compander is disabled, then
  1395. * 20ms delay is required.
  1396. */
  1397. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1398. if (!wcd939x->comp1_enable)
  1399. usleep_range(20000, 20100);
  1400. else
  1401. usleep_range(7000, 7100);
  1402. if (hph_mode == CLS_H_LP ||
  1403. hph_mode == CLS_H_LOHIFI ||
  1404. hph_mode == CLS_H_ULP)
  1405. if (!wcd939x->hph_pcm_enabled)
  1406. snd_soc_component_update_bits(component,
  1407. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1408. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1409. }
  1410. snd_soc_component_update_bits(component,
  1411. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1412. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1413. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1414. snd_soc_component_update_bits(component,
  1415. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1416. if (wcd939x->update_wcd_event)
  1417. wcd939x->update_wcd_event(wcd939x->handle,
  1418. SLV_BOLERO_EVT_RX_MUTE,
  1419. (WCD_RX1 << 0x10));
  1420. /*Enable PDM INT for PDM data path only*/
  1421. if (!wcd939x->hph_pcm_enabled)
  1422. wcd_enable_irq(&wcd939x->irq_info,
  1423. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1424. break;
  1425. case SND_SOC_DAPM_PRE_PMD:
  1426. if (wcd939x->update_wcd_event)
  1427. wcd939x->update_wcd_event(wcd939x->handle,
  1428. SLV_BOLERO_EVT_RX_MUTE,
  1429. (WCD_RX1 << 0x10 | 0x1));
  1430. wcd_disable_irq(&wcd939x->irq_info,
  1431. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1432. if (wcd939x->update_wcd_event && wcd939x->comp1_enable)
  1433. wcd939x->update_wcd_event(wcd939x->handle,
  1434. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1435. (WCD_RX1 << 0x10));
  1436. /*
  1437. * 7ms sleep is required if compander is enabled as per
  1438. * HW requirement. If compander is disabled, then
  1439. * 20ms delay is required.
  1440. */
  1441. if (!wcd939x->comp1_enable)
  1442. usleep_range(20000, 20100);
  1443. else
  1444. usleep_range(7000, 7100);
  1445. snd_soc_component_update_bits(component,
  1446. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  1447. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1448. WCD_EVENT_PRE_HPHL_PA_OFF,
  1449. &wcd939x->mbhc->wcd_mbhc);
  1450. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1451. break;
  1452. case SND_SOC_DAPM_POST_PMD:
  1453. /*
  1454. * 7ms sleep is required if compander is enabled as per
  1455. * HW requirement. If compander is disabled, then
  1456. * 20ms delay is required.
  1457. */
  1458. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1459. if (!wcd939x->comp1_enable)
  1460. usleep_range(21000, 21100);
  1461. else
  1462. usleep_range(7000, 7100);
  1463. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1464. }
  1465. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1466. WCD_EVENT_POST_HPHL_PA_OFF,
  1467. &wcd939x->mbhc->wcd_mbhc);
  1468. snd_soc_component_update_bits(component,
  1469. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x00));
  1470. snd_soc_component_update_bits(component,
  1471. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1472. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog &&
  1473. !(snd_soc_component_read(component, WCD939X_HPH) & 0XC0))
  1474. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE, 1);
  1475. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1476. WCD_CLSH_EVENT_POST_PA,
  1477. WCD_CLSH_STATE_HPHL,
  1478. hph_mode);
  1479. if (wcd939x->ldoh)
  1480. snd_soc_component_update_bits(component,
  1481. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1482. break;
  1483. };
  1484. return ret;
  1485. }
  1486. static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1487. struct snd_kcontrol *kcontrol,
  1488. int event)
  1489. {
  1490. struct snd_soc_component *component =
  1491. snd_soc_dapm_to_component(w->dapm);
  1492. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1493. int ret = 0;
  1494. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1495. w->name, event);
  1496. switch (event) {
  1497. case SND_SOC_DAPM_PRE_PMU:
  1498. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1499. wcd939x->rx_swr_dev->dev_num,
  1500. true);
  1501. /*
  1502. * Enable watchdog interrupt for HPHL
  1503. */
  1504. snd_soc_component_update_bits(component,
  1505. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1506. /* For EAR, use CLASS_AB regulator mode */
  1507. snd_soc_component_update_bits(component,
  1508. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1509. snd_soc_component_update_bits(component,
  1510. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x01));
  1511. break;
  1512. case SND_SOC_DAPM_POST_PMU:
  1513. /* 6 msec delay as per HW requirement */
  1514. usleep_range(6000, 6010);
  1515. if (wcd939x->update_wcd_event)
  1516. wcd939x->update_wcd_event(wcd939x->handle,
  1517. SLV_BOLERO_EVT_RX_MUTE,
  1518. (WCD_RX3 << 0x10));
  1519. wcd_enable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  1520. break;
  1521. case SND_SOC_DAPM_PRE_PMD:
  1522. wcd_disable_irq(&wcd939x->irq_info,
  1523. WCD939X_IRQ_EAR_PDM_WD_INT);
  1524. if (wcd939x->update_wcd_event)
  1525. wcd939x->update_wcd_event(wcd939x->handle,
  1526. SLV_BOLERO_EVT_RX_MUTE,
  1527. (WCD_RX3 << 0x10 | 0x1));
  1528. break;
  1529. case SND_SOC_DAPM_POST_PMD:
  1530. snd_soc_component_update_bits(component,
  1531. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
  1532. /* 7 msec delay as per HW requirement */
  1533. usleep_range(7000, 7010);
  1534. snd_soc_component_update_bits(component,
  1535. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1536. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1537. WCD_CLSH_EVENT_POST_PA,
  1538. WCD_CLSH_STATE_EAR,
  1539. CLS_AB_HIFI);
  1540. break;
  1541. };
  1542. return ret;
  1543. }
  1544. static int wcd939x_clsh_dummy(struct snd_soc_dapm_widget *w,
  1545. struct snd_kcontrol *kcontrol,
  1546. int event)
  1547. {
  1548. struct snd_soc_component *component =
  1549. snd_soc_dapm_to_component(w->dapm);
  1550. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1551. int ret = 0;
  1552. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1553. w->name, event);
  1554. if (SND_SOC_DAPM_EVENT_OFF(event))
  1555. ret = swr_slvdev_datapath_control(
  1556. wcd939x->rx_swr_dev,
  1557. wcd939x->rx_swr_dev->dev_num,
  1558. false);
  1559. return ret;
  1560. }
  1561. static int wcd939x_enable_clsh(struct snd_soc_dapm_widget *w,
  1562. struct snd_kcontrol *kcontrol,
  1563. int event)
  1564. {
  1565. struct snd_soc_component *component =
  1566. snd_soc_dapm_to_component(w->dapm);
  1567. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1568. int mode = wcd939x->hph_mode;
  1569. int ret = 0;
  1570. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1571. w->name, event);
  1572. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1573. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1574. wcd939x_rx_connect_port(component, CLSH,
  1575. SND_SOC_DAPM_EVENT_ON(event));
  1576. }
  1577. if (SND_SOC_DAPM_EVENT_OFF(event))
  1578. ret = swr_slvdev_datapath_control(
  1579. wcd939x->rx_swr_dev,
  1580. wcd939x->rx_swr_dev->dev_num,
  1581. false);
  1582. return ret;
  1583. }
  1584. static int wcd939x_enable_rx1(struct snd_soc_dapm_widget *w,
  1585. struct snd_kcontrol *kcontrol,
  1586. int event)
  1587. {
  1588. struct snd_soc_component *component =
  1589. snd_soc_dapm_to_component(w->dapm);
  1590. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1591. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1592. w->name, event);
  1593. switch (event) {
  1594. case SND_SOC_DAPM_PRE_PMU:
  1595. if (wcd939x->hph_pcm_enabled)
  1596. wcd939x_rx_connect_port(component, HIFI_PCM_L, true);
  1597. else {
  1598. wcd939x_rx_connect_port(component, HPH_L, true);
  1599. if (wcd939x->comp1_enable)
  1600. wcd939x_rx_connect_port(component, COMP_L, true);
  1601. }
  1602. break;
  1603. case SND_SOC_DAPM_POST_PMD:
  1604. if (wcd939x->hph_pcm_enabled)
  1605. wcd939x_rx_connect_port(component, HIFI_PCM_L, false);
  1606. else {
  1607. wcd939x_rx_connect_port(component, HPH_L, false);
  1608. if (wcd939x->comp1_enable)
  1609. wcd939x_rx_connect_port(component, COMP_L, false);
  1610. }
  1611. break;
  1612. };
  1613. return 0;
  1614. }
  1615. static int wcd939x_enable_rx2(struct snd_soc_dapm_widget *w,
  1616. struct snd_kcontrol *kcontrol, int event)
  1617. {
  1618. struct snd_soc_component *component =
  1619. snd_soc_dapm_to_component(w->dapm);
  1620. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1621. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1622. w->name, event);
  1623. switch (event) {
  1624. case SND_SOC_DAPM_PRE_PMU:
  1625. if (wcd939x->hph_pcm_enabled)
  1626. wcd939x_rx_connect_port(component, HIFI_PCM_R, true);
  1627. else {
  1628. wcd939x_rx_connect_port(component, HPH_R, true);
  1629. if (wcd939x->comp2_enable)
  1630. wcd939x_rx_connect_port(component, COMP_R, true);
  1631. }
  1632. break;
  1633. case SND_SOC_DAPM_POST_PMD:
  1634. if (wcd939x->hph_pcm_enabled)
  1635. wcd939x_rx_connect_port(component, HIFI_PCM_R, false);
  1636. else {
  1637. wcd939x_rx_connect_port(component, HPH_R, false);
  1638. if (wcd939x->comp2_enable)
  1639. wcd939x_rx_connect_port(component, COMP_R, false);
  1640. }
  1641. break;
  1642. };
  1643. return 0;
  1644. }
  1645. static int wcd939x_enable_rx3(struct snd_soc_dapm_widget *w,
  1646. struct snd_kcontrol *kcontrol,
  1647. int event)
  1648. {
  1649. struct snd_soc_component *component =
  1650. snd_soc_dapm_to_component(w->dapm);
  1651. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1652. w->name, event);
  1653. switch (event) {
  1654. case SND_SOC_DAPM_PRE_PMU:
  1655. wcd939x_rx_connect_port(component, LO, true);
  1656. break;
  1657. case SND_SOC_DAPM_POST_PMD:
  1658. wcd939x_rx_connect_port(component, LO, false);
  1659. /* 6 msec delay as per HW requirement */
  1660. usleep_range(6000, 6010);
  1661. break;
  1662. }
  1663. return 0;
  1664. }
  1665. static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1666. struct snd_kcontrol *kcontrol,
  1667. int event)
  1668. {
  1669. struct snd_soc_component *component =
  1670. snd_soc_dapm_to_component(w->dapm);
  1671. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1672. u16 dmic_clk_reg, dmic_clk_en_reg;
  1673. s32 *dmic_clk_cnt;
  1674. u8 dmic_ctl_shift = 0;
  1675. u8 dmic_clk_shift = 0;
  1676. u8 dmic_clk_mask = 0;
  1677. u16 dmic2_left_en = 0;
  1678. int ret = 0;
  1679. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1680. w->name, event);
  1681. switch (w->shift) {
  1682. case 0:
  1683. case 1:
  1684. dmic_clk_cnt = &(wcd939x->dmic_0_1_clk_cnt);
  1685. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1686. dmic_clk_en_reg = WCD939X_CDC_DMIC1_CTL;
  1687. dmic_clk_mask = 0x0F;
  1688. dmic_clk_shift = 0x00;
  1689. dmic_ctl_shift = 0x00;
  1690. break;
  1691. case 2:
  1692. dmic2_left_en = WCD939X_CDC_DMIC2_CTL;
  1693. fallthrough;
  1694. case 3:
  1695. dmic_clk_cnt = &(wcd939x->dmic_2_3_clk_cnt);
  1696. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1697. dmic_clk_en_reg = WCD939X_CDC_DMIC2_CTL;
  1698. dmic_clk_mask = 0xF0;
  1699. dmic_clk_shift = 0x04;
  1700. dmic_ctl_shift = 0x01;
  1701. break;
  1702. case 4:
  1703. case 5:
  1704. dmic_clk_cnt = &(wcd939x->dmic_4_5_clk_cnt);
  1705. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1706. dmic_clk_en_reg = WCD939X_CDC_DMIC3_CTL;
  1707. dmic_clk_mask = 0x0F;
  1708. dmic_clk_shift = 0x00;
  1709. dmic_ctl_shift = 0x02;
  1710. break;
  1711. case 6:
  1712. case 7:
  1713. dmic_clk_cnt = &(wcd939x->dmic_6_7_clk_cnt);
  1714. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1715. dmic_clk_en_reg = WCD939X_CDC_DMIC4_CTL;
  1716. dmic_clk_mask = 0xF0;
  1717. dmic_clk_shift = 0x04;
  1718. dmic_ctl_shift = 0x03;
  1719. break;
  1720. default:
  1721. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  1722. __func__);
  1723. return -EINVAL;
  1724. };
  1725. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1726. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1727. switch (event) {
  1728. case SND_SOC_DAPM_PRE_PMU:
  1729. snd_soc_component_update_bits(component,
  1730. WCD939X_CDC_AMIC_CTL,
  1731. (0x01 << dmic_ctl_shift), 0x00);
  1732. /* 250us sleep as per HW requirement */
  1733. usleep_range(250, 260);
  1734. if (dmic2_left_en)
  1735. snd_soc_component_update_bits(component,
  1736. dmic2_left_en, 0x80, 0x80);
  1737. /* Setting DMIC clock rate to 2.4MHz */
  1738. snd_soc_component_update_bits(component,
  1739. dmic_clk_reg, dmic_clk_mask,
  1740. (0x03 << dmic_clk_shift));
  1741. snd_soc_component_update_bits(component,
  1742. dmic_clk_en_reg, 0x08, 0x08);
  1743. /* enable clock scaling */
  1744. snd_soc_component_update_bits(component,
  1745. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  1746. snd_soc_component_update_bits(component,
  1747. REG_FIELD_VALUE(CDC_DMIC_CTL, DMIC_DIV_BAK_EN, 0x01));
  1748. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1749. wcd939x->tx_swr_dev->dev_num,
  1750. true);
  1751. break;
  1752. case SND_SOC_DAPM_POST_PMD:
  1753. wcd939x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1754. false);
  1755. snd_soc_component_update_bits(component,
  1756. WCD939X_CDC_AMIC_CTL,
  1757. (0x01 << dmic_ctl_shift),
  1758. (0x01 << dmic_ctl_shift));
  1759. if (dmic2_left_en)
  1760. snd_soc_component_update_bits(component,
  1761. dmic2_left_en, 0x80, 0x00);
  1762. snd_soc_component_update_bits(component,
  1763. dmic_clk_en_reg, 0x08, 0x00);
  1764. break;
  1765. };
  1766. return ret;
  1767. }
  1768. /*
  1769. * wcd939x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1770. * @micb_mv: micbias in mv
  1771. *
  1772. * return register value converted
  1773. */
  1774. int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
  1775. {
  1776. /* min micbias voltage is 1V and maximum is 2.85V */
  1777. if (micb_mv < 1000 || micb_mv > 2850) {
  1778. pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
  1779. return -EINVAL;
  1780. }
  1781. return (micb_mv - 1000) / 50;
  1782. }
  1783. EXPORT_SYMBOL(wcd939x_get_micb_vout_ctl_val);
  1784. /*
  1785. * wcd939x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1786. * @component: handle to snd_soc_component *
  1787. * @req_volt: micbias voltage to be set
  1788. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1789. *
  1790. * return 0 if adjustment is success or error code in case of failure
  1791. */
  1792. int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1793. int req_volt, int micb_num)
  1794. {
  1795. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1796. int cur_vout_ctl, req_vout_ctl;
  1797. int micb_reg, micb_val, micb_en;
  1798. int ret = 0;
  1799. switch (micb_num) {
  1800. case MIC_BIAS_1:
  1801. micb_reg = WCD939X_MICB1;
  1802. break;
  1803. case MIC_BIAS_2:
  1804. micb_reg = WCD939X_MICB2;
  1805. break;
  1806. case MIC_BIAS_3:
  1807. micb_reg = WCD939X_MICB3;
  1808. break;
  1809. case MIC_BIAS_4:
  1810. micb_reg = WCD939X_MICB4;
  1811. break;
  1812. default:
  1813. return -EINVAL;
  1814. }
  1815. mutex_lock(&wcd939x->micb_lock);
  1816. /*
  1817. * If requested micbias voltage is same as current micbias
  1818. * voltage, then just return. Otherwise, adjust voltage as
  1819. * per requested value. If micbias is already enabled, then
  1820. * to avoid slow micbias ramp-up or down enable pull-up
  1821. * momentarily, change the micbias value and then re-enable
  1822. * micbias.
  1823. */
  1824. micb_val = snd_soc_component_read(component, micb_reg);
  1825. micb_en = (micb_val & 0xC0) >> 6;
  1826. cur_vout_ctl = micb_val & 0x3F;
  1827. req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
  1828. if (req_vout_ctl < 0) {
  1829. ret = -EINVAL;
  1830. goto exit;
  1831. }
  1832. if (cur_vout_ctl == req_vout_ctl) {
  1833. ret = 0;
  1834. goto exit;
  1835. }
  1836. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1837. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1838. req_volt, micb_en);
  1839. if (micb_en == 0x1)
  1840. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1841. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1842. if (micb_en == 0x1) {
  1843. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1844. /*
  1845. * Add 2ms delay as per HW requirement after enabling
  1846. * micbias
  1847. */
  1848. usleep_range(2000, 2100);
  1849. }
  1850. exit:
  1851. mutex_unlock(&wcd939x->micb_lock);
  1852. return ret;
  1853. }
  1854. EXPORT_SYMBOL(wcd939x_mbhc_micb_adjust_voltage);
  1855. static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1856. struct snd_kcontrol *kcontrol,
  1857. int event)
  1858. {
  1859. struct snd_soc_component *component =
  1860. snd_soc_dapm_to_component(w->dapm);
  1861. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1862. int ret = 0;
  1863. int bank = 0;
  1864. u8 mode = 0;
  1865. int i = 0;
  1866. int rate = 0;
  1867. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  1868. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  1869. /* power mode is applicable only to analog mics */
  1870. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1871. /* Get channel rate */
  1872. rate = wcd939x_get_clk_rate(wcd939x->tx_mode[w->shift - ADC1]);
  1873. }
  1874. switch (event) {
  1875. case SND_SOC_DAPM_PRE_PMU:
  1876. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1877. if (w->shift == ADC2 &&
  1878. (((snd_soc_component_read(component, WCD939X_TX_CH12_MUX) &
  1879. 0x38) >> 3) == 0x2)) {
  1880. if (!wcd939x->bcs_dis) {
  1881. wcd939x_tx_connect_port(component, MBHC,
  1882. SWR_CLK_RATE_4P8MHZ, true);
  1883. set_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  1884. }
  1885. }
  1886. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1887. set_bit(w->shift - ADC1, &wcd939x->status_mask);
  1888. wcd939x_tx_connect_port(component, w->shift, rate,
  1889. true);
  1890. } else {
  1891. wcd939x_tx_connect_port(component, w->shift,
  1892. SWR_CLK_RATE_2P4MHZ, true);
  1893. }
  1894. break;
  1895. case SND_SOC_DAPM_POST_PMD:
  1896. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1897. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1898. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  1899. clear_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  1900. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1901. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  1902. clear_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  1903. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1904. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  1905. clear_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  1906. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1907. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  1908. clear_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  1909. }
  1910. }
  1911. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1912. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  1913. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  1914. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  1915. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  1916. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  1917. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  1918. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  1919. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  1920. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  1921. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  1922. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  1923. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  1924. if (mode != 0) {
  1925. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1926. if (mode & (1 << i)) {
  1927. i++;
  1928. break;
  1929. }
  1930. }
  1931. }
  1932. rate = wcd939x_get_clk_rate(i);
  1933. if (wcd939x->adc_count) {
  1934. rate = (wcd939x->adc_count * rate);
  1935. if (rate > SWR_CLK_RATE_9P6MHZ)
  1936. rate = SWR_CLK_RATE_9P6MHZ;
  1937. }
  1938. wcd939x_set_swr_clk_rate(component, rate, bank);
  1939. }
  1940. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1941. wcd939x->tx_swr_dev->dev_num,
  1942. false);
  1943. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1944. wcd939x_set_swr_clk_rate(component, rate, !bank);
  1945. break;
  1946. };
  1947. return ret;
  1948. }
  1949. static int wcd939x_get_adc_mode(int val)
  1950. {
  1951. int ret = 0;
  1952. switch (val) {
  1953. case ADC_MODE_INVALID:
  1954. ret = ADC_MODE_VAL_NORMAL;
  1955. break;
  1956. case ADC_MODE_HIFI:
  1957. ret = ADC_MODE_VAL_HIFI;
  1958. break;
  1959. case ADC_MODE_LO_HIF:
  1960. ret = ADC_MODE_VAL_LO_HIF;
  1961. break;
  1962. case ADC_MODE_NORMAL:
  1963. ret = ADC_MODE_VAL_NORMAL;
  1964. break;
  1965. case ADC_MODE_LP:
  1966. ret = ADC_MODE_VAL_LP;
  1967. break;
  1968. case ADC_MODE_ULP1:
  1969. ret = ADC_MODE_VAL_ULP1;
  1970. break;
  1971. case ADC_MODE_ULP2:
  1972. ret = ADC_MODE_VAL_ULP2;
  1973. break;
  1974. default:
  1975. ret = -EINVAL;
  1976. pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
  1977. break;
  1978. }
  1979. return ret;
  1980. }
  1981. int wcd939x_tx_channel_config(struct snd_soc_component *component,
  1982. int channel, int mode)
  1983. {
  1984. int reg = WCD939X_TX_CH2, mask = 0, val = 0;
  1985. int ret = 0;
  1986. switch (channel) {
  1987. case 0:
  1988. reg = WCD939X_TX_CH2;
  1989. mask = 0x40;
  1990. break;
  1991. case 1:
  1992. reg = WCD939X_TX_CH2;
  1993. mask = 0x20;
  1994. break;
  1995. case 2:
  1996. reg = WCD939X_TX_CH4;
  1997. mask = 0x40;
  1998. break;
  1999. case 3:
  2000. reg = WCD939X_TX_CH4;
  2001. mask = 0x20;
  2002. break;
  2003. default:
  2004. pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
  2005. ret = -EINVAL;
  2006. break;
  2007. }
  2008. if (!mode)
  2009. val = 0x00;
  2010. else
  2011. val = mask;
  2012. if (!ret)
  2013. snd_soc_component_update_bits(component, reg, mask, val);
  2014. return ret;
  2015. }
  2016. static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  2017. struct snd_kcontrol *kcontrol,
  2018. int event){
  2019. struct snd_soc_component *component =
  2020. snd_soc_dapm_to_component(w->dapm);
  2021. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2022. int clk_rate = 0, ret = 0;
  2023. int mode = 0, i = 0, bank = 0;
  2024. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2025. w->name, event);
  2026. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  2027. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  2028. switch (event) {
  2029. case SND_SOC_DAPM_PRE_PMU:
  2030. wcd939x->adc_count++;
  2031. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  2032. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  2033. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  2034. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  2035. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  2036. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  2037. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  2038. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  2039. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  2040. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  2041. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  2042. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  2043. if (mode != 0) {
  2044. for (i = 0; i < ADC_MODE_ULP2; i++) {
  2045. if (mode & (1 << i)) {
  2046. i++;
  2047. break;
  2048. }
  2049. }
  2050. }
  2051. clk_rate = wcd939x_get_clk_rate(i);
  2052. /* clk_rate depends on number of paths getting enabled */
  2053. clk_rate = (wcd939x->adc_count * clk_rate);
  2054. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  2055. clk_rate = SWR_CLK_RATE_9P6MHZ;
  2056. wcd939x_set_swr_clk_rate(component, clk_rate, bank);
  2057. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  2058. wcd939x->tx_swr_dev->dev_num,
  2059. true);
  2060. wcd939x_set_swr_clk_rate(component, clk_rate, !bank);
  2061. break;
  2062. case SND_SOC_DAPM_POST_PMD:
  2063. wcd939x->adc_count--;
  2064. if (wcd939x->adc_count < 0)
  2065. wcd939x->adc_count = 0;
  2066. wcd939x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  2067. if (w->shift + ADC1 == ADC2 &&
  2068. test_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask)) {
  2069. wcd939x_tx_connect_port(component, MBHC, 0,
  2070. false);
  2071. clear_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  2072. }
  2073. break;
  2074. };
  2075. return ret;
  2076. }
  2077. void wcd939x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  2078. bool bcs_disable)
  2079. {
  2080. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2081. if (wcd939x->update_wcd_event) {
  2082. if (bcs_disable)
  2083. wcd939x->update_wcd_event(wcd939x->handle,
  2084. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  2085. else
  2086. wcd939x->update_wcd_event(wcd939x->handle,
  2087. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  2088. }
  2089. }
  2090. static int wcd939x_enable_req(struct snd_soc_dapm_widget *w,
  2091. struct snd_kcontrol *kcontrol, int event)
  2092. {
  2093. struct snd_soc_component *component =
  2094. snd_soc_dapm_to_component(w->dapm);
  2095. struct wcd939x_priv *wcd939x =
  2096. snd_soc_component_get_drvdata(component);
  2097. int ret = 0;
  2098. u8 mode = 0;
  2099. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2100. w->name, event);
  2101. switch (event) {
  2102. case SND_SOC_DAPM_PRE_PMU:
  2103. snd_soc_component_update_bits(component,
  2104. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x01));
  2105. snd_soc_component_update_bits(component,
  2106. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2107. snd_soc_component_update_bits(component,
  2108. REG_FIELD_VALUE(CDC_REQ_CTL, FS_RATE_4P8, 0x01));
  2109. snd_soc_component_update_bits(component,
  2110. REG_FIELD_VALUE(CDC_REQ_CTL, NO_NOTCH, 0x00));
  2111. ret = wcd939x_tx_channel_config(component, w->shift, 1);
  2112. mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
  2113. if (mode < 0) {
  2114. dev_info_ratelimited(component->dev,
  2115. "%s: invalid mode, setting to normal mode\n",
  2116. __func__);
  2117. mode = ADC_MODE_VAL_NORMAL;
  2118. }
  2119. switch (w->shift) {
  2120. case 0:
  2121. snd_soc_component_update_bits(component,
  2122. WCD939X_CDC_TX_ANA_MODE_0_1, 0x0F,
  2123. mode);
  2124. snd_soc_component_update_bits(component,
  2125. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x01));
  2126. break;
  2127. case 1:
  2128. snd_soc_component_update_bits(component,
  2129. WCD939X_CDC_TX_ANA_MODE_0_1, 0xF0,
  2130. mode << 4);
  2131. snd_soc_component_update_bits(component,
  2132. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x01));
  2133. break;
  2134. case 2:
  2135. snd_soc_component_update_bits(component,
  2136. WCD939X_CDC_TX_ANA_MODE_2_3, 0x0F,
  2137. mode);
  2138. snd_soc_component_update_bits(component,
  2139. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x01));
  2140. break;
  2141. case 3:
  2142. snd_soc_component_update_bits(component,
  2143. WCD939X_CDC_TX_ANA_MODE_2_3, 0xF0,
  2144. mode << 4);
  2145. snd_soc_component_update_bits(component,
  2146. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x01));
  2147. break;
  2148. default:
  2149. break;
  2150. }
  2151. ret |= wcd939x_tx_channel_config(component, w->shift, 0);
  2152. break;
  2153. case SND_SOC_DAPM_POST_PMD:
  2154. switch (w->shift) {
  2155. case 0:
  2156. snd_soc_component_update_bits(component,
  2157. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD0_MODE, 0x00));
  2158. snd_soc_component_update_bits(component,
  2159. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x00));
  2160. break;
  2161. case 1:
  2162. snd_soc_component_update_bits(component,
  2163. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD1_MODE, 0x00));
  2164. snd_soc_component_update_bits(component,
  2165. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x00));
  2166. break;
  2167. case 2:
  2168. snd_soc_component_update_bits(component,
  2169. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD2_MODE, 0x00));
  2170. snd_soc_component_update_bits(component,
  2171. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x00));
  2172. break;
  2173. case 3:
  2174. snd_soc_component_update_bits(component,
  2175. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD3_MODE, 0x00));
  2176. snd_soc_component_update_bits(component,
  2177. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x00));
  2178. break;
  2179. default:
  2180. break;
  2181. }
  2182. if (wcd939x->adc_count == 0) {
  2183. snd_soc_component_update_bits(component,
  2184. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x00));
  2185. snd_soc_component_update_bits(component,
  2186. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x00));
  2187. }
  2188. break;
  2189. };
  2190. return ret;
  2191. }
  2192. int wcd939x_micbias_control(struct snd_soc_component *component,
  2193. int micb_num, int req, bool is_dapm)
  2194. {
  2195. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2196. int micb_index = micb_num - 1;
  2197. u16 micb_reg;
  2198. int pre_off_event = 0, post_off_event = 0;
  2199. int post_on_event = 0, post_dapm_off = 0;
  2200. int post_dapm_on = 0;
  2201. int ret = 0;
  2202. if ((micb_index < 0) || (micb_index > WCD939X_MAX_MICBIAS - 1)) {
  2203. dev_err_ratelimited(component->dev,
  2204. "%s: Invalid micbias index, micb_ind:%d\n",
  2205. __func__, micb_index);
  2206. return -EINVAL;
  2207. }
  2208. if (NULL == wcd939x) {
  2209. dev_err_ratelimited(component->dev,
  2210. "%s: wcd939x private data is NULL\n", __func__);
  2211. return -EINVAL;
  2212. }
  2213. switch (micb_num) {
  2214. case MIC_BIAS_1:
  2215. micb_reg = WCD939X_MICB1;
  2216. break;
  2217. case MIC_BIAS_2:
  2218. micb_reg = WCD939X_MICB2;
  2219. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  2220. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  2221. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  2222. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  2223. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  2224. break;
  2225. case MIC_BIAS_3:
  2226. micb_reg = WCD939X_MICB3;
  2227. break;
  2228. case MIC_BIAS_4:
  2229. micb_reg = WCD939X_MICB4;
  2230. break;
  2231. default:
  2232. dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
  2233. __func__, micb_num);
  2234. return -EINVAL;
  2235. };
  2236. mutex_lock(&wcd939x->micb_lock);
  2237. switch (req) {
  2238. case MICB_PULLUP_ENABLE:
  2239. if (!wcd939x->dev_up) {
  2240. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2241. __func__, req);
  2242. ret = -ENODEV;
  2243. goto done;
  2244. }
  2245. wcd939x->pullup_ref[micb_index]++;
  2246. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2247. (wcd939x->micb_ref[micb_index] == 0))
  2248. snd_soc_component_update_bits(component, micb_reg,
  2249. 0xC0, 0x80);
  2250. break;
  2251. case MICB_PULLUP_DISABLE:
  2252. if (wcd939x->pullup_ref[micb_index] > 0)
  2253. wcd939x->pullup_ref[micb_index]--;
  2254. if (!wcd939x->dev_up) {
  2255. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2256. __func__, req);
  2257. ret = -ENODEV;
  2258. goto done;
  2259. }
  2260. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2261. (wcd939x->micb_ref[micb_index] == 0))
  2262. snd_soc_component_update_bits(component, micb_reg,
  2263. 0xC0, 0x00);
  2264. break;
  2265. case MICB_ENABLE:
  2266. if (!wcd939x->dev_up) {
  2267. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2268. __func__, req);
  2269. ret = -ENODEV;
  2270. goto done;
  2271. }
  2272. wcd939x->micb_ref[micb_index]++;
  2273. if (wcd939x->micb_ref[micb_index] == 1) {
  2274. snd_soc_component_update_bits(component,
  2275. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD3_CLK_EN, 0x01));
  2276. snd_soc_component_update_bits(component,
  2277. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD2_CLK_EN, 0x01));
  2278. snd_soc_component_update_bits(component,
  2279. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD1_CLK_EN, 0x01));
  2280. snd_soc_component_update_bits(component,
  2281. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD0_CLK_EN, 0x01));
  2282. snd_soc_component_update_bits(component,
  2283. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2284. snd_soc_component_update_bits(component,
  2285. REG_FIELD_VALUE(CDC_ANA_TX_CLK_CTL, ANA_TXSCBIAS_CLK_EN, 0x01));
  2286. snd_soc_component_update_bits(component,
  2287. REG_FIELD_VALUE(TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2288. snd_soc_component_update_bits(component,
  2289. REG_FIELD_VALUE(MICB2_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2290. snd_soc_component_update_bits(component,
  2291. REG_FIELD_VALUE(MICB3_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2292. snd_soc_component_update_bits(component,
  2293. REG_FIELD_VALUE(MICB4_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2294. snd_soc_component_update_bits(component,
  2295. micb_reg, 0xC0, 0x40);
  2296. if (post_on_event)
  2297. blocking_notifier_call_chain(
  2298. &wcd939x->mbhc->notifier,
  2299. post_on_event,
  2300. &wcd939x->mbhc->wcd_mbhc);
  2301. }
  2302. if (is_dapm && post_dapm_on && wcd939x->mbhc)
  2303. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2304. post_dapm_on,
  2305. &wcd939x->mbhc->wcd_mbhc);
  2306. break;
  2307. case MICB_DISABLE:
  2308. if (wcd939x->micb_ref[micb_index] > 0)
  2309. wcd939x->micb_ref[micb_index]--;
  2310. if (!wcd939x->dev_up) {
  2311. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2312. __func__, req);
  2313. ret = -ENODEV;
  2314. goto done;
  2315. }
  2316. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2317. (wcd939x->pullup_ref[micb_index] > 0))
  2318. snd_soc_component_update_bits(component, micb_reg,
  2319. 0xC0, 0x80);
  2320. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2321. (wcd939x->pullup_ref[micb_index] == 0)) {
  2322. if (pre_off_event && wcd939x->mbhc)
  2323. blocking_notifier_call_chain(
  2324. &wcd939x->mbhc->notifier,
  2325. pre_off_event,
  2326. &wcd939x->mbhc->wcd_mbhc);
  2327. snd_soc_component_update_bits(component, micb_reg,
  2328. 0xC0, 0x00);
  2329. if (post_off_event && wcd939x->mbhc)
  2330. blocking_notifier_call_chain(
  2331. &wcd939x->mbhc->notifier,
  2332. post_off_event,
  2333. &wcd939x->mbhc->wcd_mbhc);
  2334. }
  2335. if (is_dapm && post_dapm_off && wcd939x->mbhc)
  2336. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2337. post_dapm_off,
  2338. &wcd939x->mbhc->wcd_mbhc);
  2339. break;
  2340. };
  2341. dev_dbg(component->dev,
  2342. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2343. __func__, micb_num, wcd939x->micb_ref[micb_index],
  2344. wcd939x->pullup_ref[micb_index]);
  2345. done:
  2346. mutex_unlock(&wcd939x->micb_lock);
  2347. return ret;
  2348. }
  2349. EXPORT_SYMBOL(wcd939x_micbias_control);
  2350. static int wcd939x_get_logical_addr(struct swr_device *swr_dev)
  2351. {
  2352. int ret = 0;
  2353. uint8_t devnum = 0;
  2354. int num_retry = NUM_ATTEMPTS;
  2355. do {
  2356. /* retry after 1ms */
  2357. usleep_range(1000, 1010);
  2358. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2359. } while (ret && --num_retry);
  2360. if (ret)
  2361. dev_err_ratelimited(&swr_dev->dev,
  2362. "%s get devnum %d for dev addr %llx failed\n",
  2363. __func__, devnum, swr_dev->addr);
  2364. swr_dev->dev_num = devnum;
  2365. return 0;
  2366. }
  2367. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2368. struct wcd_mbhc_config *mbhc_cfg)
  2369. {
  2370. if (mbhc_cfg->enable_usbc_analog) {
  2371. if (!(snd_soc_component_read(component, WCD939X_MBHC_MECH)
  2372. & 0x20))
  2373. return true;
  2374. }
  2375. return false;
  2376. }
  2377. int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *component,
  2378. struct notifier_block *nblock,
  2379. bool enable)
  2380. {
  2381. struct wcd939x_priv *wcd939x_priv;
  2382. if(NULL == component) {
  2383. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2384. return -EINVAL;
  2385. }
  2386. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2387. wcd939x_priv->notify_swr_dmic = enable;
  2388. if (enable)
  2389. return blocking_notifier_chain_register(&wcd939x_priv->notifier,
  2390. nblock);
  2391. else
  2392. return blocking_notifier_chain_unregister(
  2393. &wcd939x_priv->notifier, nblock);
  2394. }
  2395. EXPORT_SYMBOL(wcd939x_swr_dmic_register_notifier);
  2396. static int wcd939x_event_notify(struct notifier_block *block,
  2397. unsigned long val,
  2398. void *data)
  2399. {
  2400. u16 event = (val & 0xffff);
  2401. int ret = 0;
  2402. int rx_clk_type;
  2403. struct wcd939x_priv *wcd939x = dev_get_drvdata((struct device *)data);
  2404. struct snd_soc_component *component = wcd939x->component;
  2405. struct wcd_mbhc *mbhc;
  2406. switch (event) {
  2407. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2408. if (test_bit(WCD_ADC1, &wcd939x->status_mask)) {
  2409. snd_soc_component_update_bits(component,
  2410. REG_FIELD_VALUE(TX_CH2, HPF1_INIT, 0x00));
  2411. set_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  2412. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  2413. }
  2414. if (test_bit(WCD_ADC2, &wcd939x->status_mask)) {
  2415. snd_soc_component_update_bits(component,
  2416. REG_FIELD_VALUE(TX_CH2, HPF2_INIT, 0x00));
  2417. set_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  2418. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  2419. }
  2420. if (test_bit(WCD_ADC3, &wcd939x->status_mask)) {
  2421. snd_soc_component_update_bits(component,
  2422. REG_FIELD_VALUE(TX_CH4, HPF3_INIT, 0x00));
  2423. set_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  2424. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  2425. }
  2426. if (test_bit(WCD_ADC4, &wcd939x->status_mask)) {
  2427. snd_soc_component_update_bits(component,
  2428. REG_FIELD_VALUE(TX_CH4, HPF4_INIT, 0x00));
  2429. set_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  2430. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  2431. }
  2432. break;
  2433. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2434. snd_soc_component_update_bits(component,
  2435. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  2436. snd_soc_component_update_bits(component,
  2437. REG_FIELD_VALUE(HPH, HPHR_ENABLE , 0x00));
  2438. snd_soc_component_update_bits(component,
  2439. REG_FIELD_VALUE(EAR, ENABLE, 0x00));
  2440. break;
  2441. case BOLERO_SLV_EVT_SSR_DOWN:
  2442. wcd939x->dev_up = false;
  2443. if(wcd939x->notify_swr_dmic)
  2444. blocking_notifier_call_chain(&wcd939x->notifier,
  2445. WCD939X_EVT_SSR_DOWN,
  2446. NULL);
  2447. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2448. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2449. wcd939x->usbc_hs_status = get_usbc_hs_status(component,
  2450. mbhc->mbhc_cfg);
  2451. wcd939x_mbhc_ssr_down(wcd939x->mbhc, component);
  2452. wcd939x_reset_low(wcd939x->dev);
  2453. break;
  2454. case BOLERO_SLV_EVT_SSR_UP:
  2455. wcd939x_reset(wcd939x->dev);
  2456. /* allow reset to take effect */
  2457. usleep_range(10000, 10010);
  2458. wcd939x_get_logical_addr(wcd939x->tx_swr_dev);
  2459. wcd939x_get_logical_addr(wcd939x->rx_swr_dev);
  2460. wcd939x_init_reg(component);
  2461. regcache_mark_dirty(wcd939x->regmap);
  2462. regcache_sync(wcd939x->regmap);
  2463. /* Initialize MBHC module */
  2464. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2465. ret = wcd939x_mbhc_post_ssr_init(wcd939x->mbhc, component);
  2466. if (ret) {
  2467. dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
  2468. __func__);
  2469. } else {
  2470. wcd939x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2471. }
  2472. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2473. wcd939x->dev_up = true;
  2474. if(wcd939x->notify_swr_dmic)
  2475. blocking_notifier_call_chain(&wcd939x->notifier,
  2476. WCD939X_EVT_SSR_UP,
  2477. NULL);
  2478. if (wcd939x->usbc_hs_status)
  2479. mdelay(500);
  2480. break;
  2481. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2482. snd_soc_component_update_bits(component,
  2483. WCD939X_TOP_CLK_CFG, 0x06,
  2484. ((val >> 0x10) << 0x01));
  2485. rx_clk_type = (val >> 0x10);
  2486. switch(rx_clk_type) {
  2487. case RX_CLK_12P288MHZ:
  2488. wcd939x->rx_clk_config = RX_CLK_12P288MHZ;
  2489. break;
  2490. case RX_CLK_11P2896MHZ:
  2491. wcd939x->rx_clk_config = RX_CLK_11P2896MHZ;
  2492. break;
  2493. default:
  2494. wcd939x->rx_clk_config = RX_CLK_9P6MHZ;
  2495. break;
  2496. }
  2497. dev_dbg(component->dev, "%s: rx clk config %d\n", __func__, wcd939x->rx_clk_config);
  2498. break;
  2499. default:
  2500. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2501. break;
  2502. }
  2503. return 0;
  2504. }
  2505. static int __wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2506. int event)
  2507. {
  2508. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2509. int micb_num;
  2510. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2511. __func__, w->name, event);
  2512. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2513. micb_num = MIC_BIAS_1;
  2514. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2515. micb_num = MIC_BIAS_2;
  2516. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2517. micb_num = MIC_BIAS_3;
  2518. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2519. micb_num = MIC_BIAS_4;
  2520. else
  2521. return -EINVAL;
  2522. switch (event) {
  2523. case SND_SOC_DAPM_PRE_PMU:
  2524. wcd939x_micbias_control(component, micb_num,
  2525. MICB_ENABLE, true);
  2526. break;
  2527. case SND_SOC_DAPM_POST_PMU:
  2528. /* 1 msec delay as per HW requirement */
  2529. usleep_range(1000, 1100);
  2530. break;
  2531. case SND_SOC_DAPM_POST_PMD:
  2532. wcd939x_micbias_control(component, micb_num,
  2533. MICB_DISABLE, true);
  2534. break;
  2535. };
  2536. return 0;
  2537. }
  2538. static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2539. struct snd_kcontrol *kcontrol,
  2540. int event)
  2541. {
  2542. return __wcd939x_codec_enable_micbias(w, event);
  2543. }
  2544. static int __wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2545. int event)
  2546. {
  2547. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2548. int micb_num;
  2549. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2550. __func__, w->name, event);
  2551. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2552. micb_num = MIC_BIAS_1;
  2553. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2554. micb_num = MIC_BIAS_2;
  2555. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2556. micb_num = MIC_BIAS_3;
  2557. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2558. micb_num = MIC_BIAS_4;
  2559. else
  2560. return -EINVAL;
  2561. switch (event) {
  2562. case SND_SOC_DAPM_PRE_PMU:
  2563. wcd939x_micbias_control(component, micb_num,
  2564. MICB_PULLUP_ENABLE, true);
  2565. break;
  2566. case SND_SOC_DAPM_POST_PMU:
  2567. /* 1 msec delay as per HW requirement */
  2568. usleep_range(1000, 1100);
  2569. break;
  2570. case SND_SOC_DAPM_POST_PMD:
  2571. wcd939x_micbias_control(component, micb_num,
  2572. MICB_PULLUP_DISABLE, true);
  2573. break;
  2574. };
  2575. return 0;
  2576. }
  2577. static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2578. struct snd_kcontrol *kcontrol,
  2579. int event)
  2580. {
  2581. return __wcd939x_codec_enable_micbias_pullup(w, event);
  2582. }
  2583. static int wcd939x_wakeup(void *handle, bool enable)
  2584. {
  2585. struct wcd939x_priv *priv;
  2586. int ret = 0;
  2587. if (!handle) {
  2588. pr_err_ratelimited("%s: NULL handle\n", __func__);
  2589. return -EINVAL;
  2590. }
  2591. priv = (struct wcd939x_priv *)handle;
  2592. if (!priv->tx_swr_dev) {
  2593. pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
  2594. return -EINVAL;
  2595. }
  2596. mutex_lock(&priv->wakeup_lock);
  2597. if (enable)
  2598. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2599. else
  2600. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2601. mutex_unlock(&priv->wakeup_lock);
  2602. return ret;
  2603. }
  2604. static int wcd939x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2605. struct snd_kcontrol *kcontrol,
  2606. int event)
  2607. {
  2608. int ret = 0;
  2609. struct snd_soc_component *component =
  2610. snd_soc_dapm_to_component(w->dapm);
  2611. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2612. switch (event) {
  2613. case SND_SOC_DAPM_PRE_PMU:
  2614. wcd939x_wakeup(wcd939x, true);
  2615. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2616. wcd939x_wakeup(wcd939x, false);
  2617. break;
  2618. case SND_SOC_DAPM_POST_PMD:
  2619. wcd939x_wakeup(wcd939x, true);
  2620. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2621. wcd939x_wakeup(wcd939x, false);
  2622. break;
  2623. }
  2624. return ret;
  2625. }
  2626. static int wcd939x_enable_micbias(struct wcd939x_priv *wcd939x,
  2627. int micb_num, int req)
  2628. {
  2629. int micb_index = micb_num - 1;
  2630. u16 micb_reg;
  2631. if (NULL == wcd939x) {
  2632. pr_err_ratelimited("%s: wcd939x private data is NULL\n", __func__);
  2633. return -EINVAL;
  2634. }
  2635. switch (micb_num) {
  2636. case MIC_BIAS_1:
  2637. micb_reg = WCD939X_MICB1;
  2638. break;
  2639. case MIC_BIAS_2:
  2640. micb_reg = WCD939X_MICB2;
  2641. break;
  2642. case MIC_BIAS_3:
  2643. micb_reg = WCD939X_MICB3;
  2644. break;
  2645. case MIC_BIAS_4:
  2646. micb_reg = WCD939X_MICB4;
  2647. break;
  2648. default:
  2649. pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2650. return -EINVAL;
  2651. };
  2652. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2653. __func__, req, micb_num, wcd939x->micb_ref[micb_index],
  2654. wcd939x->pullup_ref[micb_index]);
  2655. mutex_lock(&wcd939x->micb_lock);
  2656. switch (req) {
  2657. case MICB_ENABLE:
  2658. wcd939x->micb_ref[micb_index]++;
  2659. if (wcd939x->micb_ref[micb_index] == 1) {
  2660. regmap_update_bits(wcd939x->regmap,
  2661. WCD939X_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2662. regmap_update_bits(wcd939x->regmap,
  2663. WCD939X_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2664. regmap_update_bits(wcd939x->regmap,
  2665. WCD939X_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2666. regmap_update_bits(wcd939x->regmap,
  2667. WCD939X_TEST_CTL_2, 0x01, 0x01);
  2668. regmap_update_bits(wcd939x->regmap,
  2669. WCD939X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2670. regmap_update_bits(wcd939x->regmap,
  2671. WCD939X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2672. regmap_update_bits(wcd939x->regmap,
  2673. WCD939X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2674. regmap_update_bits(wcd939x->regmap,
  2675. micb_reg, 0xC0, 0x40);
  2676. regmap_update_bits(wcd939x->regmap, micb_reg, 0x3F, 0x10);
  2677. }
  2678. break;
  2679. case MICB_PULLUP_ENABLE:
  2680. wcd939x->pullup_ref[micb_index]++;
  2681. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2682. (wcd939x->micb_ref[micb_index] == 0))
  2683. regmap_update_bits(wcd939x->regmap, micb_reg,
  2684. 0xC0, 0x80);
  2685. break;
  2686. case MICB_PULLUP_DISABLE:
  2687. if (wcd939x->pullup_ref[micb_index] > 0)
  2688. wcd939x->pullup_ref[micb_index]--;
  2689. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2690. (wcd939x->micb_ref[micb_index] == 0))
  2691. regmap_update_bits(wcd939x->regmap, micb_reg,
  2692. 0xC0, 0x00);
  2693. break;
  2694. case MICB_DISABLE:
  2695. if (wcd939x->micb_ref[micb_index] > 0)
  2696. wcd939x->micb_ref[micb_index]--;
  2697. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2698. (wcd939x->pullup_ref[micb_index] > 0))
  2699. regmap_update_bits(wcd939x->regmap, micb_reg,
  2700. 0xC0, 0x80);
  2701. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2702. (wcd939x->pullup_ref[micb_index] == 0))
  2703. regmap_update_bits(wcd939x->regmap, micb_reg,
  2704. 0xC0, 0x00);
  2705. break;
  2706. };
  2707. mutex_unlock(&wcd939x->micb_lock);
  2708. return 0;
  2709. }
  2710. int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2711. int event, int micb_num)
  2712. {
  2713. struct wcd939x_priv *wcd939x_priv = NULL;
  2714. int ret = 0;
  2715. int micb_index = micb_num - 1;
  2716. if(NULL == component) {
  2717. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2718. return -EINVAL;
  2719. }
  2720. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2721. pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
  2722. return -EINVAL;
  2723. }
  2724. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2725. pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2726. return -EINVAL;
  2727. }
  2728. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2729. if (!wcd939x_priv->dev_up) {
  2730. if ((wcd939x_priv->pullup_ref[micb_index] > 0) &&
  2731. (event == SND_SOC_DAPM_POST_PMD)) {
  2732. wcd939x_priv->pullup_ref[micb_index]--;
  2733. ret = -ENODEV;
  2734. goto done;
  2735. }
  2736. }
  2737. switch (event) {
  2738. case SND_SOC_DAPM_PRE_PMU:
  2739. wcd939x_wakeup(wcd939x_priv, true);
  2740. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_ENABLE);
  2741. wcd939x_wakeup(wcd939x_priv, false);
  2742. break;
  2743. case SND_SOC_DAPM_POST_PMD:
  2744. wcd939x_wakeup(wcd939x_priv, true);
  2745. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_DISABLE);
  2746. wcd939x_wakeup(wcd939x_priv, false);
  2747. break;
  2748. }
  2749. done:
  2750. return ret;
  2751. }
  2752. EXPORT_SYMBOL(wcd939x_codec_force_enable_micbias_v2);
  2753. static inline int wcd939x_tx_path_get(const char *wname,
  2754. unsigned int *path_num)
  2755. {
  2756. int ret = 0;
  2757. char *widget_name = NULL;
  2758. char *w_name = NULL;
  2759. char *path_num_char = NULL;
  2760. char *path_name = NULL;
  2761. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2762. if (!widget_name)
  2763. return -EINVAL;
  2764. w_name = widget_name;
  2765. path_name = strsep(&widget_name, " ");
  2766. if (!path_name) {
  2767. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  2768. __func__, widget_name);
  2769. ret = -EINVAL;
  2770. goto err;
  2771. }
  2772. path_num_char = strpbrk(path_name, "0123");
  2773. if (!path_num_char) {
  2774. pr_err_ratelimited("%s: tx path index not found\n",
  2775. __func__);
  2776. ret = -EINVAL;
  2777. goto err;
  2778. }
  2779. ret = kstrtouint(path_num_char, 10, path_num);
  2780. if (ret < 0)
  2781. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  2782. __func__, w_name);
  2783. err:
  2784. kfree(w_name);
  2785. return ret;
  2786. }
  2787. static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2788. struct snd_ctl_elem_value *ucontrol)
  2789. {
  2790. struct snd_soc_component *component =
  2791. snd_soc_kcontrol_component(kcontrol);
  2792. struct wcd939x_priv *wcd939x = NULL;
  2793. int ret = 0;
  2794. unsigned int path = 0;
  2795. if (!component)
  2796. return -EINVAL;
  2797. wcd939x = snd_soc_component_get_drvdata(component);
  2798. if (!wcd939x)
  2799. return -EINVAL;
  2800. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2801. if (ret < 0)
  2802. return ret;
  2803. ucontrol->value.integer.value[0] = wcd939x->tx_mode[path];
  2804. return 0;
  2805. }
  2806. static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2807. struct snd_ctl_elem_value *ucontrol)
  2808. {
  2809. struct snd_soc_component *component =
  2810. snd_soc_kcontrol_component(kcontrol);
  2811. struct wcd939x_priv *wcd939x = NULL;
  2812. u32 mode_val;
  2813. unsigned int path = 0;
  2814. int ret = 0;
  2815. if (!component)
  2816. return -EINVAL;
  2817. wcd939x = snd_soc_component_get_drvdata(component);
  2818. if (!wcd939x)
  2819. return -EINVAL;
  2820. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2821. if (ret)
  2822. return ret;
  2823. mode_val = ucontrol->value.enumerated.item[0];
  2824. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2825. wcd939x->tx_mode[path] = mode_val;
  2826. return 0;
  2827. }
  2828. static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2829. struct snd_ctl_elem_value *ucontrol)
  2830. {
  2831. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2832. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2833. ucontrol->value.integer.value[0] = wcd939x->hph_mode;
  2834. return 0;
  2835. }
  2836. static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2837. struct snd_ctl_elem_value *ucontrol)
  2838. {
  2839. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2840. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2841. u32 mode_val;
  2842. mode_val = ucontrol->value.enumerated.item[0];
  2843. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2844. if (wcd939x->variant == WCD9390) {
  2845. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2846. dev_info_ratelimited(component->dev,
  2847. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2848. __func__);
  2849. mode_val = CLS_H_ULP;
  2850. }
  2851. }
  2852. if (mode_val == CLS_H_NORMAL) {
  2853. dev_info_ratelimited(component->dev,
  2854. "%s:Invalid HPH Mode, default to class_AB\n",
  2855. __func__);
  2856. mode_val = CLS_H_ULP;
  2857. }
  2858. wcd939x->hph_mode = mode_val;
  2859. return 0;
  2860. }
  2861. static int wcd939x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2862. struct snd_ctl_elem_value *ucontrol)
  2863. {
  2864. u8 ear_pa_gain = 0;
  2865. struct snd_soc_component *component =
  2866. snd_soc_kcontrol_component(kcontrol);
  2867. ear_pa_gain = snd_soc_component_read(component,
  2868. WCD939X_EAR_COMPANDER_CTL);
  2869. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2870. ucontrol->value.integer.value[0] = ear_pa_gain;
  2871. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2872. ear_pa_gain);
  2873. return 0;
  2874. }
  2875. static int wcd939x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2876. struct snd_ctl_elem_value *ucontrol)
  2877. {
  2878. u8 ear_pa_gain = 0;
  2879. struct snd_soc_component *component =
  2880. snd_soc_kcontrol_component(kcontrol);
  2881. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2882. __func__, ucontrol->value.integer.value[0]);
  2883. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2884. snd_soc_component_update_bits(component,
  2885. WCD939X_EAR_COMPANDER_CTL,
  2886. 0x7C, ear_pa_gain);
  2887. return 0;
  2888. }
  2889. /* wcd939x_codec_get_dev_num - returns swr device number
  2890. * @component: Codec instance
  2891. *
  2892. * Return: swr device number on success or negative error
  2893. * code on failure.
  2894. */
  2895. int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
  2896. {
  2897. struct wcd939x_priv *wcd939x;
  2898. if (!component)
  2899. return -EINVAL;
  2900. wcd939x = snd_soc_component_get_drvdata(component);
  2901. if (!wcd939x || !wcd939x->rx_swr_dev) {
  2902. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2903. return -EINVAL;
  2904. }
  2905. return wcd939x->rx_swr_dev->dev_num;
  2906. }
  2907. EXPORT_SYMBOL(wcd939x_codec_get_dev_num);
  2908. static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
  2909. struct snd_ctl_elem_value *ucontrol)
  2910. {
  2911. struct snd_soc_component *component =
  2912. snd_soc_kcontrol_component(kcontrol);
  2913. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2914. bool hphr;
  2915. struct soc_multi_mixer_control *mc;
  2916. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2917. hphr = mc->shift;
  2918. ucontrol->value.integer.value[0] = hphr ? wcd939x->comp2_enable :
  2919. wcd939x->comp1_enable;
  2920. return 0;
  2921. }
  2922. static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
  2923. struct snd_ctl_elem_value *ucontrol)
  2924. {
  2925. struct snd_soc_component *component =
  2926. snd_soc_kcontrol_component(kcontrol);
  2927. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2928. int value = ucontrol->value.integer.value[0];
  2929. bool hphr;
  2930. struct soc_multi_mixer_control *mc;
  2931. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2932. hphr = mc->shift;
  2933. if (hphr)
  2934. wcd939x->comp2_enable = value;
  2935. else
  2936. wcd939x->comp1_enable = value;
  2937. return 0;
  2938. }
  2939. static int wcd939x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2940. struct snd_kcontrol *kcontrol,
  2941. int event)
  2942. {
  2943. struct snd_soc_component *component =
  2944. snd_soc_dapm_to_component(w->dapm);
  2945. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2946. struct wcd939x_pdata *pdata = NULL;
  2947. int ret = 0;
  2948. pdata = dev_get_platdata(wcd939x->dev);
  2949. if (!pdata) {
  2950. dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
  2951. return -EINVAL;
  2952. }
  2953. if (!msm_cdc_is_ondemand_supply(wcd939x->dev,
  2954. wcd939x->supplies,
  2955. pdata->regulator,
  2956. pdata->num_supplies,
  2957. "cdc-vdd-buck"))
  2958. return 0;
  2959. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2960. w->name, event);
  2961. switch (event) {
  2962. case SND_SOC_DAPM_PRE_PMU:
  2963. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  2964. dev_dbg(component->dev,
  2965. "%s: buck already in enabled state\n",
  2966. __func__);
  2967. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2968. return 0;
  2969. }
  2970. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  2971. wcd939x->supplies,
  2972. pdata->regulator,
  2973. pdata->num_supplies,
  2974. "cdc-vdd-buck");
  2975. if (ret == -EINVAL) {
  2976. dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
  2977. __func__);
  2978. return ret;
  2979. }
  2980. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2981. /*
  2982. * 200us sleep is required after LDO is enabled as per
  2983. * HW requirement
  2984. */
  2985. usleep_range(200, 250);
  2986. break;
  2987. case SND_SOC_DAPM_POST_PMD:
  2988. set_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2989. break;
  2990. }
  2991. return 0;
  2992. }
  2993. static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
  2994. struct snd_ctl_elem_value *ucontrol)
  2995. {
  2996. struct snd_soc_component *component =
  2997. snd_soc_kcontrol_component(kcontrol);
  2998. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2999. ucontrol->value.integer.value[0] = wcd939x->ldoh;
  3000. return 0;
  3001. }
  3002. static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
  3003. struct snd_ctl_elem_value *ucontrol)
  3004. {
  3005. struct snd_soc_component *component =
  3006. snd_soc_kcontrol_component(kcontrol);
  3007. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3008. wcd939x->ldoh = ucontrol->value.integer.value[0];
  3009. return 0;
  3010. }
  3011. const char * const tx_master_ch_text[] = {
  3012. "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
  3013. "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
  3014. "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
  3015. "SWRM_TX3_CH4", "SWRM_PCM_IN",
  3016. };
  3017. const struct soc_enum tx_master_ch_enum =
  3018. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  3019. tx_master_ch_text);
  3020. static void wcd939x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  3021. {
  3022. u8 ch_type = 0;
  3023. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  3024. ch_type = ADC1;
  3025. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  3026. ch_type = ADC2;
  3027. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  3028. ch_type = ADC3;
  3029. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  3030. ch_type = ADC4;
  3031. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  3032. ch_type = DMIC0;
  3033. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  3034. ch_type = DMIC1;
  3035. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  3036. ch_type = MBHC;
  3037. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  3038. ch_type = DMIC2;
  3039. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  3040. ch_type = DMIC3;
  3041. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  3042. ch_type = DMIC4;
  3043. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  3044. ch_type = DMIC5;
  3045. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  3046. ch_type = DMIC6;
  3047. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  3048. ch_type = DMIC7;
  3049. else
  3050. pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
  3051. if (ch_type)
  3052. *ch_idx = wcd939x_slave_get_slave_ch_val(ch_type);
  3053. else
  3054. *ch_idx = -EINVAL;
  3055. }
  3056. static int wcd939x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  3057. struct snd_ctl_elem_value *ucontrol)
  3058. {
  3059. struct snd_soc_component *component =
  3060. snd_soc_kcontrol_component(kcontrol);
  3061. struct wcd939x_priv *wcd939x = NULL;
  3062. int slave_ch_idx = -EINVAL;
  3063. if (component == NULL)
  3064. return -EINVAL;
  3065. wcd939x = snd_soc_component_get_drvdata(component);
  3066. if (wcd939x == NULL)
  3067. return -EINVAL;
  3068. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  3069. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  3070. return -EINVAL;
  3071. ucontrol->value.integer.value[0] = wcd939x_slave_get_master_ch_val(
  3072. wcd939x->tx_master_ch_map[slave_ch_idx]);
  3073. return 0;
  3074. }
  3075. static int wcd939x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  3076. struct snd_ctl_elem_value *ucontrol)
  3077. {
  3078. struct snd_soc_component *component =
  3079. snd_soc_kcontrol_component(kcontrol);
  3080. struct wcd939x_priv *wcd939x = NULL;
  3081. int slave_ch_idx = -EINVAL, idx = 0;
  3082. if (component == NULL)
  3083. return -EINVAL;
  3084. wcd939x = snd_soc_component_get_drvdata(component);
  3085. if (wcd939x == NULL)
  3086. return -EINVAL;
  3087. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  3088. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  3089. return -EINVAL;
  3090. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  3091. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  3092. __func__, ucontrol->value.enumerated.item[0]);
  3093. idx = ucontrol->value.enumerated.item[0];
  3094. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  3095. return -EINVAL;
  3096. wcd939x->tx_master_ch_map[slave_ch_idx] = wcd939x_slave_get_master_ch(idx);
  3097. return 0;
  3098. }
  3099. static int wcd939x_bcs_get(struct snd_kcontrol *kcontrol,
  3100. struct snd_ctl_elem_value *ucontrol)
  3101. {
  3102. struct snd_soc_component *component =
  3103. snd_soc_kcontrol_component(kcontrol);
  3104. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3105. ucontrol->value.integer.value[0] = wcd939x->bcs_dis;
  3106. return 0;
  3107. }
  3108. static int wcd939x_bcs_put(struct snd_kcontrol *kcontrol,
  3109. struct snd_ctl_elem_value *ucontrol)
  3110. {
  3111. struct snd_soc_component *component =
  3112. snd_soc_kcontrol_component(kcontrol);
  3113. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3114. wcd939x->bcs_dis = ucontrol->value.integer.value[0];
  3115. return 0;
  3116. }
  3117. static const char * const tx_mode_mux_text_wcd9390[] = {
  3118. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3119. };
  3120. static const struct soc_enum tx_mode_mux_enum_wcd9390 =
  3121. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9390),
  3122. tx_mode_mux_text_wcd9390);
  3123. static const char * const tx_mode_mux_text[] = {
  3124. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3125. "ADC_ULP1", "ADC_ULP2",
  3126. };
  3127. static const struct soc_enum tx_mode_mux_enum =
  3128. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  3129. tx_mode_mux_text);
  3130. static const char * const rx_hph_mode_mux_text_wcd9390[] = {
  3131. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  3132. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  3133. "CLS_AB_LOHIFI",
  3134. };
  3135. static const char * const wcd939x_ear_pa_gain_text[] = {
  3136. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  3137. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  3138. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  3139. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  3140. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  3141. };
  3142. static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
  3143. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
  3144. rx_hph_mode_mux_text_wcd9390);
  3145. static SOC_ENUM_SINGLE_EXT_DECL(wcd939x_ear_pa_gain_enum,
  3146. wcd939x_ear_pa_gain_text);
  3147. static const char * const rx_hph_mode_mux_text[] = {
  3148. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  3149. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  3150. };
  3151. static const struct soc_enum rx_hph_mode_mux_enum =
  3152. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  3153. rx_hph_mode_mux_text);
  3154. static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
  3155. SOC_ENUM_EXT("EAR PA GAIN", wcd939x_ear_pa_gain_enum,
  3156. wcd939x_ear_pa_gain_get, wcd939x_ear_pa_gain_put),
  3157. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
  3158. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3159. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9390,
  3160. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3161. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9390,
  3162. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3163. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9390,
  3164. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3165. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9390,
  3166. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3167. };
  3168. static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
  3169. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  3170. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3171. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  3172. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3173. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  3174. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3175. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  3176. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3177. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  3178. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3179. };
  3180. static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
  3181. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  3182. wcd939x_get_compander, wcd939x_set_compander),
  3183. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  3184. wcd939x_get_compander, wcd939x_set_compander),
  3185. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  3186. wcd939x_ldoh_get, wcd939x_ldoh_put),
  3187. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  3188. wcd939x_bcs_get, wcd939x_bcs_put),
  3189. SOC_SINGLE_TLV("HPHL Volume", WCD939X_PA_GAIN_CTL_L, 0, 0x18, 0, hph_analog_gain),
  3190. SOC_SINGLE_TLV("HPHR Volume", WCD939X_PA_GAIN_CTL_R, 0, 0x18, 0, hph_analog_gain),
  3191. SOC_SINGLE_TLV("ADC1 Volume", WCD939X_TX_CH1, 0, 20, 0,
  3192. analog_gain),
  3193. SOC_SINGLE_TLV("ADC2 Volume", WCD939X_TX_CH2, 0, 20, 0,
  3194. analog_gain),
  3195. SOC_SINGLE_TLV("ADC3 Volume", WCD939X_TX_CH3, 0, 20, 0,
  3196. analog_gain),
  3197. SOC_SINGLE_TLV("ADC4 Volume", WCD939X_TX_CH4, 0, 20, 0,
  3198. analog_gain),
  3199. SOC_SINGLE_EXT("HPHL Compander", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3200. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3201. SOC_SINGLE_EXT("HPHR Compander", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3202. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3203. SOC_SINGLE_EXT("HPHL XTALK", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3204. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3205. SOC_SINGLE_EXT("HPHR XTALK", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3206. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3207. SOC_SINGLE_EXT("HPH PCM Enable", SND_SOC_NOPM, 0, 1, 0,
  3208. wcd939x_hph_pcm_enable_get, wcd939x_hph_pcm_enable_put),
  3209. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  3210. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3211. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  3212. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3213. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  3214. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3215. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  3216. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3217. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  3218. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3219. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  3220. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3221. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  3222. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3223. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  3224. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3225. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  3226. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3227. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  3228. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3229. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  3230. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3231. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  3232. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3233. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  3234. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3235. };
  3236. static const struct snd_kcontrol_new adc1_switch[] = {
  3237. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3238. };
  3239. static const struct snd_kcontrol_new adc2_switch[] = {
  3240. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3241. };
  3242. static const struct snd_kcontrol_new adc3_switch[] = {
  3243. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3244. };
  3245. static const struct snd_kcontrol_new adc4_switch[] = {
  3246. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3247. };
  3248. static const struct snd_kcontrol_new amic1_switch[] = {
  3249. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3250. };
  3251. static const struct snd_kcontrol_new amic2_switch[] = {
  3252. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3253. };
  3254. static const struct snd_kcontrol_new amic3_switch[] = {
  3255. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3256. };
  3257. static const struct snd_kcontrol_new amic4_switch[] = {
  3258. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3259. };
  3260. static const struct snd_kcontrol_new amic5_switch[] = {
  3261. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3262. };
  3263. static const struct snd_kcontrol_new va_amic1_switch[] = {
  3264. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3265. };
  3266. static const struct snd_kcontrol_new va_amic2_switch[] = {
  3267. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3268. };
  3269. static const struct snd_kcontrol_new va_amic3_switch[] = {
  3270. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3271. };
  3272. static const struct snd_kcontrol_new va_amic4_switch[] = {
  3273. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3274. };
  3275. static const struct snd_kcontrol_new va_amic5_switch[] = {
  3276. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3277. };
  3278. static const struct snd_kcontrol_new dmic1_switch[] = {
  3279. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3280. };
  3281. static const struct snd_kcontrol_new dmic2_switch[] = {
  3282. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3283. };
  3284. static const struct snd_kcontrol_new dmic3_switch[] = {
  3285. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3286. };
  3287. static const struct snd_kcontrol_new dmic4_switch[] = {
  3288. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3289. };
  3290. static const struct snd_kcontrol_new dmic5_switch[] = {
  3291. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3292. };
  3293. static const struct snd_kcontrol_new dmic6_switch[] = {
  3294. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3295. };
  3296. static const struct snd_kcontrol_new dmic7_switch[] = {
  3297. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3298. };
  3299. static const struct snd_kcontrol_new dmic8_switch[] = {
  3300. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3301. };
  3302. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  3303. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3304. };
  3305. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  3306. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3307. };
  3308. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  3309. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3310. };
  3311. static const char * const adc1_mux_text[] = {
  3312. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
  3313. };
  3314. static const struct soc_enum adc1_enum =
  3315. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH1_SEL_SHIFT,
  3316. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  3317. static const struct snd_kcontrol_new tx_adc1_mux =
  3318. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  3319. static const char * const adc2_mux_text[] = {
  3320. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
  3321. };
  3322. static const struct soc_enum adc2_enum =
  3323. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH2_SEL_SHIFT,
  3324. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  3325. static const struct snd_kcontrol_new tx_adc2_mux =
  3326. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  3327. static const char * const adc3_mux_text[] = {
  3328. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
  3329. };
  3330. static const struct soc_enum adc3_enum =
  3331. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH3_SEL_SHIFT,
  3332. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  3333. static const struct snd_kcontrol_new tx_adc3_mux =
  3334. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  3335. static const char * const adc4_mux_text[] = {
  3336. "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
  3337. };
  3338. static const struct soc_enum adc4_enum =
  3339. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH4_SEL_SHIFT,
  3340. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  3341. static const struct snd_kcontrol_new tx_adc4_mux =
  3342. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  3343. static const char * const rdac3_mux_text[] = {
  3344. "RX3", "RX1"
  3345. };
  3346. static const struct soc_enum rdac3_enum =
  3347. SOC_ENUM_SINGLE(WCD939X_CDC_EAR_PATH_CTL, 0,
  3348. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  3349. static const struct snd_kcontrol_new rx_rdac3_mux =
  3350. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  3351. static const char * const rx1_mux_text[] = {
  3352. "ZERO", "RX1 MUX"
  3353. };
  3354. static const struct soc_enum rx1_enum =
  3355. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx1_mux_text);
  3356. static const struct snd_kcontrol_new rx1_mux =
  3357. SOC_DAPM_ENUM("RX1 MUX Mux", rx1_enum);
  3358. static const char * const rx2_mux_text[] = {
  3359. "ZERO", "RX2 MUX"
  3360. };
  3361. static const struct soc_enum rx2_enum =
  3362. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx2_mux_text);
  3363. static const struct snd_kcontrol_new rx2_mux =
  3364. SOC_DAPM_ENUM("RX2 MUX Mux", rx2_enum);
  3365. static const char * const rx3_mux_text[] = {
  3366. "ZERO", "RX3 MUX"
  3367. };
  3368. static const struct soc_enum rx3_enum =
  3369. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx3_mux_text);
  3370. static const struct snd_kcontrol_new rx3_mux =
  3371. SOC_DAPM_ENUM("RX3 MUX Mux", rx3_enum);
  3372. static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
  3373. /*input widgets*/
  3374. SND_SOC_DAPM_INPUT("AMIC1"),
  3375. SND_SOC_DAPM_INPUT("AMIC2"),
  3376. SND_SOC_DAPM_INPUT("AMIC3"),
  3377. SND_SOC_DAPM_INPUT("AMIC4"),
  3378. SND_SOC_DAPM_INPUT("AMIC5"),
  3379. SND_SOC_DAPM_INPUT("VA AMIC1"),
  3380. SND_SOC_DAPM_INPUT("VA AMIC2"),
  3381. SND_SOC_DAPM_INPUT("VA AMIC3"),
  3382. SND_SOC_DAPM_INPUT("VA AMIC4"),
  3383. SND_SOC_DAPM_INPUT("VA AMIC5"),
  3384. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  3385. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  3386. SND_SOC_DAPM_INPUT("IN3_EAR"),
  3387. /*
  3388. * These dummy widgets are null connected to WCD939x dapm input and
  3389. * output widgets which are not actual path endpoints. This ensures
  3390. * dapm doesnt set these dapm input and output widgets as endpoints.
  3391. */
  3392. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  3393. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  3394. /*tx widgets*/
  3395. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  3396. wcd939x_codec_enable_adc,
  3397. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3398. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  3399. wcd939x_codec_enable_adc,
  3400. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3401. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  3402. wcd939x_codec_enable_adc,
  3403. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3404. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3405. wcd939x_codec_enable_adc,
  3406. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3407. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3408. wcd939x_codec_enable_dmic,
  3409. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3410. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3411. wcd939x_codec_enable_dmic,
  3412. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3413. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3414. wcd939x_codec_enable_dmic,
  3415. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3416. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3417. wcd939x_codec_enable_dmic,
  3418. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3419. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3420. wcd939x_codec_enable_dmic,
  3421. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3422. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3423. wcd939x_codec_enable_dmic,
  3424. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3425. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3426. wcd939x_codec_enable_dmic,
  3427. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3428. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3429. wcd939x_codec_enable_dmic,
  3430. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3431. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3432. NULL, 0, wcd939x_enable_req,
  3433. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3434. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3435. NULL, 0, wcd939x_enable_req,
  3436. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3437. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3438. NULL, 0, wcd939x_enable_req,
  3439. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3440. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3441. NULL, 0, wcd939x_enable_req,
  3442. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3443. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3444. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3445. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3446. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3447. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3448. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3449. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3450. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3451. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3452. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3453. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3454. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3455. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3456. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3457. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3458. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3459. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3460. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3461. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3462. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3463. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3464. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3465. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3466. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3467. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3468. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3469. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3470. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3471. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3472. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3473. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  3474. &tx_adc1_mux),
  3475. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3476. &tx_adc2_mux),
  3477. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3478. &tx_adc3_mux),
  3479. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3480. &tx_adc4_mux),
  3481. /*tx mixers*/
  3482. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3483. adc1_switch, ARRAY_SIZE(adc1_switch),
  3484. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3485. SND_SOC_DAPM_POST_PMD),
  3486. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3487. adc2_switch, ARRAY_SIZE(adc2_switch),
  3488. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3489. SND_SOC_DAPM_POST_PMD),
  3490. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3491. ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
  3492. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3493. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3494. ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
  3495. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3496. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3497. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3498. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3499. SND_SOC_DAPM_POST_PMD),
  3500. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3501. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3502. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3503. SND_SOC_DAPM_POST_PMD),
  3504. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3505. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3506. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3507. SND_SOC_DAPM_POST_PMD),
  3508. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3509. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3510. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3511. SND_SOC_DAPM_POST_PMD),
  3512. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3513. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3514. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3515. SND_SOC_DAPM_POST_PMD),
  3516. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3517. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3518. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3519. SND_SOC_DAPM_POST_PMD),
  3520. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3521. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3522. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3523. SND_SOC_DAPM_POST_PMD),
  3524. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3525. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3526. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3527. SND_SOC_DAPM_POST_PMD),
  3528. /* micbias widgets*/
  3529. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3530. wcd939x_codec_enable_micbias,
  3531. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3532. SND_SOC_DAPM_POST_PMD),
  3533. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3534. wcd939x_codec_enable_micbias,
  3535. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3536. SND_SOC_DAPM_POST_PMD),
  3537. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3538. wcd939x_codec_enable_micbias,
  3539. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3540. SND_SOC_DAPM_POST_PMD),
  3541. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3542. wcd939x_codec_enable_micbias,
  3543. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3544. SND_SOC_DAPM_POST_PMD),
  3545. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3546. wcd939x_codec_force_enable_micbias,
  3547. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3548. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3549. wcd939x_codec_force_enable_micbias,
  3550. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3551. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3552. wcd939x_codec_force_enable_micbias,
  3553. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3554. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3555. wcd939x_codec_force_enable_micbias,
  3556. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3557. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3558. wcd939x_codec_enable_vdd_buck,
  3559. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3560. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3561. wcd939x_enable_clsh,
  3562. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3563. SND_SOC_DAPM_SUPPLY_S("CLS_H_DUMMY", 1, SND_SOC_NOPM, 0, 0,
  3564. wcd939x_clsh_dummy, SND_SOC_DAPM_POST_PMD),
  3565. /*rx widgets*/
  3566. SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_EAR, 7, 0, NULL, 0,
  3567. wcd939x_codec_enable_ear_pa,
  3568. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3569. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3570. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_HPH, 7, 0, NULL, 0,
  3571. wcd939x_codec_enable_hphl_pa,
  3572. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3573. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3574. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_HPH, 6, 0, NULL, 0,
  3575. wcd939x_codec_enable_hphr_pa,
  3576. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3577. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3578. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3579. wcd939x_codec_hphl_dac_event,
  3580. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3581. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3582. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3583. wcd939x_codec_hphr_dac_event,
  3584. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3585. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3586. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3587. wcd939x_codec_ear_dac_event,
  3588. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3589. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3590. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3591. SND_SOC_DAPM_MUX_E("RX1 MUX", SND_SOC_NOPM, WCD_RX1, 0, &rx1_mux,
  3592. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3593. | SND_SOC_DAPM_POST_PMD),
  3594. SND_SOC_DAPM_MUX_E("RX2 MUX", SND_SOC_NOPM, WCD_RX2, 0, &rx2_mux,
  3595. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3596. | SND_SOC_DAPM_POST_PMD),
  3597. SND_SOC_DAPM_MUX_E("RX3 MUX", SND_SOC_NOPM, WCD_RX3, 0, &rx3_mux,
  3598. wcd939x_rx3_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3599. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3600. wcd939x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3601. SND_SOC_DAPM_POST_PMD),
  3602. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3603. wcd939x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3604. SND_SOC_DAPM_POST_PMD),
  3605. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3606. wcd939x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3607. SND_SOC_DAPM_POST_PMD),
  3608. /* rx mixer widgets*/
  3609. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3610. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3611. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3612. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3613. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3614. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3615. /*output widgets tx*/
  3616. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3617. /*output widgets rx*/
  3618. SND_SOC_DAPM_OUTPUT("EAR"),
  3619. SND_SOC_DAPM_OUTPUT("HPHL"),
  3620. SND_SOC_DAPM_OUTPUT("HPHR"),
  3621. /* micbias pull up widgets*/
  3622. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3623. wcd939x_codec_enable_micbias_pullup,
  3624. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3625. SND_SOC_DAPM_POST_PMD),
  3626. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3627. wcd939x_codec_enable_micbias_pullup,
  3628. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3629. SND_SOC_DAPM_POST_PMD),
  3630. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3631. wcd939x_codec_enable_micbias_pullup,
  3632. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3633. SND_SOC_DAPM_POST_PMD),
  3634. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3635. wcd939x_codec_enable_micbias_pullup,
  3636. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3637. SND_SOC_DAPM_POST_PMD),
  3638. };
  3639. static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
  3640. /*ADC-1 (channel-1)*/
  3641. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3642. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3643. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3644. {"ADC1 REQ", NULL, "ADC1"},
  3645. {"ADC1", NULL, "ADC1 MUX"},
  3646. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3647. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3648. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3649. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3650. {"ADC1 MUX", "CH1_AMIC5", "AMIC5_MIXER"},
  3651. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3652. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3653. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3654. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3655. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3656. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3657. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3658. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3659. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3660. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3661. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3662. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3663. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3664. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3665. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3666. /*ADC-2 (channel-2)*/
  3667. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3668. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3669. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3670. {"ADC2 REQ", NULL, "ADC2"},
  3671. {"ADC2", NULL, "ADC2 MUX"},
  3672. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3673. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3674. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3675. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3676. {"ADC2 MUX", "CH2_AMIC5", "AMIC5_MIXER"},
  3677. /*ADC-3 (channel-3)*/
  3678. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3679. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3680. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3681. {"ADC3 REQ", NULL, "ADC3"},
  3682. {"ADC3", NULL, "ADC3 MUX"},
  3683. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3684. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3685. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3686. {"ADC3 MUX", "CH3_AMIC5", "AMIC5_MIXER"},
  3687. /*ADC-4 (channel-4)*/
  3688. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3689. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3690. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3691. {"ADC4 REQ", NULL, "ADC4"},
  3692. {"ADC4", NULL, "ADC4 MUX"},
  3693. {"ADC4 MUX", "CH4_AMIC1", "AMIC1_MIXER"},
  3694. {"ADC4 MUX", "CH4_AMIC3", "AMIC3_MIXER"},
  3695. {"ADC4 MUX", "CH4_AMIC4", "AMIC4_MIXER"},
  3696. {"ADC4 MUX", "CH4_AMIC5", "AMIC5_MIXER"},
  3697. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3698. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3699. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3700. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3701. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3702. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3703. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3704. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3705. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3706. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3707. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3708. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3709. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3710. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3711. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3712. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3713. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3714. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3715. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3716. {"RX1 MUX", NULL, "IN1_HPHL"},
  3717. {"RX1", NULL, "RX1 MUX"},
  3718. {"RDAC1", NULL, "RX1"},
  3719. {"HPHL_RDAC", "Switch", "RDAC1"},
  3720. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3721. {"HPHL", NULL, "HPHL PGA"},
  3722. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3723. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3724. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3725. {"RX2 MUX", NULL, "IN2_HPHR"},
  3726. {"RX2", NULL, "RX2 MUX"},
  3727. {"RDAC2", NULL, "RX2"},
  3728. {"HPHR_RDAC", "Switch", "RDAC2"},
  3729. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3730. {"HPHR", NULL, "HPHR PGA"},
  3731. {"IN3_EAR", NULL, "WCD_RX_DUMMY"},
  3732. {"IN3_EAR", NULL, "VDD_BUCK"},
  3733. {"IN3_EAR", NULL, "CLS_H_DUMMY"},
  3734. {"RX3 MUX", NULL, "IN3_EAR"},
  3735. {"RX3", NULL, "RX3 MUX"},
  3736. {"RDAC3_MUX", "RX3", "RX3"},
  3737. {"RDAC3_MUX", "RX1", "RX1"},
  3738. {"RDAC3", NULL, "RDAC3_MUX"},
  3739. {"EAR_RDAC", "Switch", "RDAC3"},
  3740. {"EAR PGA", NULL, "EAR_RDAC"},
  3741. {"EAR", NULL, "EAR PGA"},
  3742. };
  3743. static ssize_t wcd939x_version_read(struct snd_info_entry *entry,
  3744. void *file_private_data,
  3745. struct file *file,
  3746. char __user *buf, size_t count,
  3747. loff_t pos)
  3748. {
  3749. struct wcd939x_priv *priv;
  3750. char buffer[WCD939X_VERSION_ENTRY_SIZE];
  3751. int len = 0;
  3752. priv = (struct wcd939x_priv *) entry->private_data;
  3753. if (!priv) {
  3754. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3755. return -EINVAL;
  3756. }
  3757. switch (priv->version) {
  3758. case WCD939X_VERSION_1_0:
  3759. case WCD939X_VERSION_1_1:
  3760. len = snprintf(buffer, sizeof(buffer), "WCD939X_1_0\n");
  3761. break;
  3762. case WCD939X_VERSION_2_0:
  3763. len = snprintf(buffer, sizeof(buffer), "WCD939X_2_0\n");
  3764. break;
  3765. default:
  3766. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3767. }
  3768. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3769. }
  3770. static struct snd_info_entry_ops wcd939x_info_ops = {
  3771. .read = wcd939x_version_read,
  3772. };
  3773. static ssize_t wcd939x_variant_read(struct snd_info_entry *entry,
  3774. void *file_private_data,
  3775. struct file *file,
  3776. char __user *buf, size_t count,
  3777. loff_t pos)
  3778. {
  3779. struct wcd939x_priv *priv;
  3780. char buffer[WCD939X_VARIANT_ENTRY_SIZE];
  3781. int len = 0;
  3782. priv = (struct wcd939x_priv *) entry->private_data;
  3783. if (!priv) {
  3784. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3785. return -EINVAL;
  3786. }
  3787. switch (priv->variant) {
  3788. case WCD9390:
  3789. len = snprintf(buffer, sizeof(buffer), "WCD9390\n");
  3790. break;
  3791. case WCD9395:
  3792. len = snprintf(buffer, sizeof(buffer), "WCD9395\n");
  3793. break;
  3794. default:
  3795. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3796. }
  3797. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3798. }
  3799. static struct snd_info_entry_ops wcd939x_variant_ops = {
  3800. .read = wcd939x_variant_read,
  3801. };
  3802. /*
  3803. * wcd939x_get_codec_variant
  3804. * @component: component instance
  3805. *
  3806. * Return: codec variant or -EINVAL in error.
  3807. */
  3808. int wcd939x_get_codec_variant(struct snd_soc_component *component)
  3809. {
  3810. struct wcd939x_priv *priv = NULL;
  3811. if (!component)
  3812. return -EINVAL;
  3813. priv = snd_soc_component_get_drvdata(component);
  3814. if (!priv) {
  3815. dev_err(component->dev,
  3816. "%s:wcd939x not probed\n", __func__);
  3817. return 0;
  3818. }
  3819. return priv->variant;
  3820. }
  3821. EXPORT_SYMBOL(wcd939x_get_codec_variant);
  3822. /*
  3823. * wcd939x_info_create_codec_entry - creates wcd939x module
  3824. * @codec_root: The parent directory
  3825. * @component: component instance
  3826. *
  3827. * Creates wcd939x module, variant and version entry under the given
  3828. * parent directory.
  3829. *
  3830. * Return: 0 on success or negative error code on failure.
  3831. */
  3832. int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3833. struct snd_soc_component *component)
  3834. {
  3835. struct snd_info_entry *version_entry;
  3836. struct snd_info_entry *variant_entry;
  3837. struct wcd939x_priv *priv;
  3838. struct snd_soc_card *card;
  3839. if (!codec_root || !component)
  3840. return -EINVAL;
  3841. priv = snd_soc_component_get_drvdata(component);
  3842. if (priv->entry) {
  3843. dev_dbg(priv->dev,
  3844. "%s:wcd939x module already created\n", __func__);
  3845. return 0;
  3846. }
  3847. card = component->card;
  3848. priv->entry = snd_info_create_module_entry(codec_root->module,
  3849. "wcd939x", codec_root);
  3850. if (!priv->entry) {
  3851. dev_dbg(component->dev, "%s: failed to create wcd939x entry\n",
  3852. __func__);
  3853. return -ENOMEM;
  3854. }
  3855. priv->entry->mode = S_IFDIR | 0555;
  3856. if (snd_info_register(priv->entry) < 0) {
  3857. snd_info_free_entry(priv->entry);
  3858. return -ENOMEM;
  3859. }
  3860. version_entry = snd_info_create_card_entry(card->snd_card,
  3861. "version",
  3862. priv->entry);
  3863. if (!version_entry) {
  3864. dev_dbg(component->dev, "%s: failed to create wcd939x version entry\n",
  3865. __func__);
  3866. snd_info_free_entry(priv->entry);
  3867. return -ENOMEM;
  3868. }
  3869. version_entry->private_data = priv;
  3870. version_entry->size = WCD939X_VERSION_ENTRY_SIZE;
  3871. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3872. version_entry->c.ops = &wcd939x_info_ops;
  3873. if (snd_info_register(version_entry) < 0) {
  3874. snd_info_free_entry(version_entry);
  3875. snd_info_free_entry(priv->entry);
  3876. return -ENOMEM;
  3877. }
  3878. priv->version_entry = version_entry;
  3879. variant_entry = snd_info_create_card_entry(card->snd_card,
  3880. "variant",
  3881. priv->entry);
  3882. if (!variant_entry) {
  3883. dev_dbg(component->dev, "%s: failed to create wcd939x variant entry\n",
  3884. __func__);
  3885. snd_info_free_entry(version_entry);
  3886. snd_info_free_entry(priv->entry);
  3887. return -ENOMEM;
  3888. }
  3889. variant_entry->private_data = priv;
  3890. variant_entry->size = WCD939X_VARIANT_ENTRY_SIZE;
  3891. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3892. variant_entry->c.ops = &wcd939x_variant_ops;
  3893. if (snd_info_register(variant_entry) < 0) {
  3894. snd_info_free_entry(variant_entry);
  3895. snd_info_free_entry(version_entry);
  3896. snd_info_free_entry(priv->entry);
  3897. return -ENOMEM;
  3898. }
  3899. priv->variant_entry = variant_entry;
  3900. return 0;
  3901. }
  3902. EXPORT_SYMBOL(wcd939x_info_create_codec_entry);
  3903. static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x,
  3904. struct wcd939x_pdata *pdata)
  3905. {
  3906. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3907. int rc = 0;
  3908. if (!pdata) {
  3909. dev_err(wcd939x->dev, "%s: NULL pdata\n", __func__);
  3910. return -ENODEV;
  3911. }
  3912. /* set micbias voltage */
  3913. vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3914. vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3915. vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3916. vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3917. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3918. vout_ctl_4 < 0) {
  3919. rc = -EINVAL;
  3920. goto done;
  3921. }
  3922. regmap_update_bits(wcd939x->regmap, WCD939X_MICB1, 0x3F,
  3923. vout_ctl_1);
  3924. regmap_update_bits(wcd939x->regmap, WCD939X_MICB2, 0x3F,
  3925. vout_ctl_2);
  3926. regmap_update_bits(wcd939x->regmap, WCD939X_MICB3, 0x3F,
  3927. vout_ctl_3);
  3928. regmap_update_bits(wcd939x->regmap, WCD939X_MICB4, 0x3F,
  3929. vout_ctl_4);
  3930. done:
  3931. return rc;
  3932. }
  3933. static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
  3934. {
  3935. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3936. struct snd_soc_dapm_context *dapm =
  3937. snd_soc_component_get_dapm(component);
  3938. int ret = -EINVAL;
  3939. dev_info(component->dev, "%s()\n", __func__);
  3940. wcd939x = snd_soc_component_get_drvdata(component);
  3941. if (!wcd939x)
  3942. return -EINVAL;
  3943. wcd939x->component = component;
  3944. snd_soc_component_init_regmap(component, wcd939x->regmap);
  3945. devm_regmap_qti_debugfs_register(&wcd939x->tx_swr_dev->dev, wcd939x->regmap);
  3946. /*Harmonium contains only one variant i.e wcd9395*/
  3947. wcd939x->variant = WCD9395;
  3948. /* Check device tree to see if 2Vpk flag is enabled, this value should not be changed */
  3949. wcd939x->in_2Vpk_mode = of_find_property(wcd939x->dev->of_node,
  3950. "qcom,hph-2p15v-mode", NULL) != NULL;
  3951. wcd939x->fw_data = devm_kzalloc(component->dev,
  3952. sizeof(*(wcd939x->fw_data)),
  3953. GFP_KERNEL);
  3954. if (!wcd939x->fw_data) {
  3955. dev_err(component->dev, "Failed to allocate fw_data\n");
  3956. ret = -ENOMEM;
  3957. goto err;
  3958. }
  3959. set_bit(WCD9XXX_MBHC_CAL, wcd939x->fw_data->cal_bit);
  3960. ret = wcd_cal_create_hwdep(wcd939x->fw_data,
  3961. WCD9XXX_CODEC_HWDEP_NODE, component);
  3962. if (ret < 0) {
  3963. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3964. goto err_hwdep;
  3965. }
  3966. ret = wcd939x_mbhc_init(&wcd939x->mbhc, component, wcd939x->fw_data);
  3967. if (ret) {
  3968. pr_err("%s: mbhc initialization failed\n", __func__);
  3969. goto err_hwdep;
  3970. }
  3971. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Playback");
  3972. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Capture");
  3973. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3974. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3975. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3976. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3977. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3978. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3979. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3980. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3981. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3982. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3983. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3984. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3985. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3986. snd_soc_dapm_ignore_suspend(dapm, "IN3_EAR");
  3987. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3988. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3989. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3990. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3991. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3992. snd_soc_dapm_sync(dapm);
  3993. wcd_cls_h_init(&wcd939x->clsh_info);
  3994. wcd939x_init_reg(component);
  3995. if (wcd939x->variant == WCD9390) {
  3996. ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
  3997. ARRAY_SIZE(wcd9390_snd_controls));
  3998. if (ret < 0) {
  3999. dev_err(component->dev,
  4000. "%s: Failed to add snd ctrls for variant: %d\n",
  4001. __func__, wcd939x->variant);
  4002. goto err_hwdep;
  4003. }
  4004. }
  4005. if (wcd939x->variant == WCD9395) {
  4006. ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
  4007. ARRAY_SIZE(wcd9395_snd_controls));
  4008. if (ret < 0) {
  4009. dev_err(component->dev,
  4010. "%s: Failed to add snd ctrls for variant: %d\n",
  4011. __func__, wcd939x->variant);
  4012. goto err_hwdep;
  4013. }
  4014. }
  4015. /* Register event notifier */
  4016. wcd939x->nblock.notifier_call = wcd939x_event_notify;
  4017. if (wcd939x->register_notifier) {
  4018. ret = wcd939x->register_notifier(wcd939x->handle,
  4019. &wcd939x->nblock,
  4020. true);
  4021. if (ret) {
  4022. dev_err(component->dev,
  4023. "%s: Failed to register notifier %d\n",
  4024. __func__, ret);
  4025. return ret;
  4026. }
  4027. }
  4028. return ret;
  4029. err_hwdep:
  4030. wcd939x->fw_data = NULL;
  4031. err:
  4032. return ret;
  4033. }
  4034. static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
  4035. {
  4036. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4037. if (!wcd939x) {
  4038. dev_err(component->dev, "%s: wcd939x is already NULL\n",
  4039. __func__);
  4040. return;
  4041. }
  4042. if (wcd939x->register_notifier)
  4043. wcd939x->register_notifier(wcd939x->handle,
  4044. &wcd939x->nblock,
  4045. false);
  4046. }
  4047. static int wcd939x_soc_codec_suspend(struct snd_soc_component *component)
  4048. {
  4049. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4050. if (!wcd939x)
  4051. return 0;
  4052. wcd939x->dapm_bias_off = true;
  4053. return 0;
  4054. }
  4055. static int wcd939x_soc_codec_resume(struct snd_soc_component *component)
  4056. {
  4057. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4058. if (!wcd939x)
  4059. return 0;
  4060. wcd939x->dapm_bias_off = false;
  4061. return 0;
  4062. }
  4063. static struct snd_soc_component_driver soc_codec_dev_wcd939x = {
  4064. .name = WCD939X_DRV_NAME,
  4065. .probe = wcd939x_soc_codec_probe,
  4066. .remove = wcd939x_soc_codec_remove,
  4067. .controls = wcd939x_snd_controls,
  4068. .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
  4069. .dapm_widgets = wcd939x_dapm_widgets,
  4070. .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
  4071. .dapm_routes = wcd939x_audio_map,
  4072. .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
  4073. .suspend = wcd939x_soc_codec_suspend,
  4074. .resume = wcd939x_soc_codec_resume,
  4075. };
  4076. static int wcd939x_reset(struct device *dev)
  4077. {
  4078. struct wcd939x_priv *wcd939x = NULL;
  4079. int rc = 0;
  4080. int value = 0;
  4081. if (!dev)
  4082. return -ENODEV;
  4083. wcd939x = dev_get_drvdata(dev);
  4084. if (!wcd939x)
  4085. return -EINVAL;
  4086. if (!wcd939x->rst_np) {
  4087. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4088. __func__);
  4089. return -EINVAL;
  4090. }
  4091. value = msm_cdc_pinctrl_get_state(wcd939x->rst_np);
  4092. if (value > 0)
  4093. return 0;
  4094. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4095. if (rc) {
  4096. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4097. __func__);
  4098. return rc;
  4099. }
  4100. /* 20us sleep required after pulling the reset gpio to LOW */
  4101. usleep_range(20, 30);
  4102. rc = msm_cdc_pinctrl_select_active_state(wcd939x->rst_np);
  4103. if (rc) {
  4104. dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
  4105. __func__);
  4106. return rc;
  4107. }
  4108. /* 20us sleep required after pulling the reset gpio to HIGH */
  4109. usleep_range(20, 30);
  4110. return rc;
  4111. }
  4112. static int wcd939x_read_of_property_u32(struct device *dev, const char *name,
  4113. u32 *val)
  4114. {
  4115. int rc = 0;
  4116. rc = of_property_read_u32(dev->of_node, name, val);
  4117. if (rc)
  4118. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  4119. __func__, name, dev->of_node->full_name);
  4120. return rc;
  4121. }
  4122. static int wcd939x_read_of_property_s32(struct device *dev, const char *name,
  4123. s32 *val)
  4124. {
  4125. int rc = 0;
  4126. rc = of_property_read_s32(dev->of_node, name, val);
  4127. if (rc)
  4128. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  4129. __func__, name, dev->of_node->full_name);
  4130. return rc;
  4131. }
  4132. static void wcd939x_dt_parse_micbias_info(struct device *dev,
  4133. struct wcd939x_micbias_setting *mb)
  4134. {
  4135. u32 prop_val = 0;
  4136. int rc = 0;
  4137. /* MB1 */
  4138. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  4139. NULL)) {
  4140. rc = wcd939x_read_of_property_u32(dev,
  4141. "qcom,cdc-micbias1-mv",
  4142. &prop_val);
  4143. if (!rc)
  4144. mb->micb1_mv = prop_val;
  4145. } else {
  4146. dev_info(dev, "%s: Micbias1 DT property not found\n",
  4147. __func__);
  4148. }
  4149. /* MB2 */
  4150. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  4151. NULL)) {
  4152. rc = wcd939x_read_of_property_u32(dev,
  4153. "qcom,cdc-micbias2-mv",
  4154. &prop_val);
  4155. if (!rc)
  4156. mb->micb2_mv = prop_val;
  4157. } else {
  4158. dev_info(dev, "%s: Micbias2 DT property not found\n",
  4159. __func__);
  4160. }
  4161. /* MB3 */
  4162. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  4163. NULL)) {
  4164. rc = wcd939x_read_of_property_u32(dev,
  4165. "qcom,cdc-micbias3-mv",
  4166. &prop_val);
  4167. if (!rc)
  4168. mb->micb3_mv = prop_val;
  4169. } else {
  4170. dev_info(dev, "%s: Micbias3 DT property not found\n",
  4171. __func__);
  4172. }
  4173. /* MB4 */
  4174. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  4175. NULL)) {
  4176. rc = wcd939x_read_of_property_u32(dev,
  4177. "qcom,cdc-micbias4-mv",
  4178. &prop_val);
  4179. if (!rc)
  4180. mb->micb4_mv = prop_val;
  4181. } else {
  4182. dev_info(dev, "%s: Micbias4 DT property not found\n",
  4183. __func__);
  4184. }
  4185. }
  4186. static void fill_r_common_gnd_buffer(struct wcd939x_usbcss_hs_params *usbcss_hs, u32 val)
  4187. {
  4188. size_t i;
  4189. for (i = 0; i < R_COMMON_GND_BUFFER_SIZE; i++)
  4190. usbcss_hs->gnd.r_cm_gnd_buffer.data[i] = val;
  4191. }
  4192. static void init_usbcss_hs_params(struct wcd939x_usbcss_hs_params *usbcss_hs)
  4193. {
  4194. fill_r_common_gnd_buffer(usbcss_hs, 0);
  4195. usbcss_hs->gnd.sbu1.r_gnd_int_fet_mohms = 183;
  4196. usbcss_hs->gnd.sbu2.r_gnd_int_fet_mohms = 127;
  4197. usbcss_hs->gnd.r_cm_gnd_buffer.write_index = 0;
  4198. usbcss_hs->gnd.rdson_mohms = 500;
  4199. usbcss_hs->gnd.rdson_3p6v_mohms = 545;
  4200. usbcss_hs->gnd.r_gnd_ext_fet_mohms = 0; /* to be computed during MBHC zdet */
  4201. usbcss_hs->gnd.r_common_gnd_mohms = 0;
  4202. usbcss_hs->gnd.r_common_gnd_offset = 0;
  4203. usbcss_hs->gnd.r_common_gnd_margin = 500;
  4204. usbcss_hs->gnd.gnd_ext_fet_delta_mohms = 45;
  4205. usbcss_hs->gnd.gnd_ext_fet_min_mohms = 0;
  4206. usbcss_hs->gnd.sbu1.r_gnd_par_route1_mohms = 5;
  4207. usbcss_hs->gnd.sbu2.r_gnd_par_route1_mohms = 5;
  4208. usbcss_hs->gnd.sbu1.r_gnd_par_route2_mohms = 330;
  4209. usbcss_hs->gnd.sbu2.r_gnd_par_route2_mohms = 330;
  4210. usbcss_hs->gnd.sbu1.r_gnd_par_tot_mohms = 0;
  4211. usbcss_hs->gnd.sbu2.r_gnd_par_tot_mohms = 0;
  4212. usbcss_hs->gnd.sbu1.r_gnd_res_tot_mohms = 0;
  4213. usbcss_hs->gnd.sbu2.r_gnd_res_tot_mohms = 0;
  4214. usbcss_hs->aud.l.r_aud_int_fet_mohms = 290;
  4215. usbcss_hs->aud.r.r_aud_int_fet_mohms = 290;
  4216. usbcss_hs->aud.l.r_aud_ext_fet_mohms = 0; /* to be computed during MBHC zdet */
  4217. usbcss_hs->aud.r.r_aud_ext_fet_mohms = 0; /* to be computed during MBHC zdet */
  4218. usbcss_hs->aud.l.r_aud_res_tot_mohms = 0;
  4219. usbcss_hs->aud.r.r_aud_res_tot_mohms = 0;
  4220. usbcss_hs->aud.r_surge_mohms = 229;
  4221. usbcss_hs->aud.l.r_load_eff_mohms = 0; /* to be computed during MBHC zdet */
  4222. usbcss_hs->aud.r.r_load_eff_mohms = 0; /* to be computed during MBHC zdet */
  4223. usbcss_hs->aud.l.zval = 0; /* to be computed during MBHC zdet */
  4224. usbcss_hs->aud.r.zval = 0; /* to be computed during MBHC zdet */
  4225. usbcss_hs->zdiffval = 0; /* to be computed during MBHC zdet */
  4226. usbcss_hs->diff_slope_factor_times_1000 = 9898;
  4227. usbcss_hs->se_slope_factor_times_1000 = 9906;
  4228. usbcss_hs->aud.l.r1 = 310;
  4229. usbcss_hs->aud.r.r1 = 310;
  4230. usbcss_hs->aud.l.r3 = 1;
  4231. usbcss_hs->aud.r.r3 = 1;
  4232. usbcss_hs->gnd.sbu1.r4 = 530;
  4233. usbcss_hs->gnd.sbu2.r4 = 530;
  4234. usbcss_hs->gnd.sbu1.r5 = 5;
  4235. usbcss_hs->gnd.sbu2.r5 = 5;
  4236. usbcss_hs->gnd.sbu1.r6 = 1;
  4237. usbcss_hs->gnd.sbu2.r6 = 1;
  4238. usbcss_hs->gnd.sbu1.r7 = 5;
  4239. usbcss_hs->gnd.sbu2.r7 = 5;
  4240. usbcss_hs->aud.k_aud_times_100 = 13;
  4241. usbcss_hs->aud.aud_tap_offset = 0;
  4242. usbcss_hs->xtalk.scale_l = MAX_XTALK_SCALE;
  4243. usbcss_hs->xtalk.alpha_l = MIN_XTALK_ALPHA;
  4244. usbcss_hs->xtalk.scale_r = MAX_XTALK_SCALE;
  4245. usbcss_hs->xtalk.alpha_r = MIN_XTALK_ALPHA;
  4246. usbcss_hs->xtalk.xtalk_config = XTALK_NONE;
  4247. }
  4248. static void parse_xtalk_param(struct device *dev, u32 default_val, u32 *prop_val_p,
  4249. char *prop)
  4250. {
  4251. int rc = 0;
  4252. if (of_find_property(dev->of_node, prop, NULL)) {
  4253. rc = wcd939x_read_of_property_u32(dev, prop, prop_val_p);
  4254. if ((!rc) && (*prop_val_p <= MAX_USBCSS_HS_IMPEDANCE_MOHMS) && (*prop_val_p > 0))
  4255. return;
  4256. *prop_val_p = default_val;
  4257. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n", __func__, prop,
  4258. default_val);
  4259. } else {
  4260. *prop_val_p = default_val;
  4261. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4262. __func__, prop, default_val);
  4263. }
  4264. }
  4265. static void wcd939x_dt_parse_usbcss_hs_info(struct device *dev,
  4266. struct wcd939x_usbcss_hs_params *usbcss_hs)
  4267. {
  4268. u32 prop_val = 0, r_common_gnd_mohms = 0;
  4269. s32 prop_val_signed = 0;
  4270. int rc = 0;
  4271. /* Default values for parameters */
  4272. init_usbcss_hs_params(usbcss_hs);
  4273. /* xtalk_config: Determine type of crosstalk: none (0), digital (1), or analog (2) */
  4274. if (of_find_property(dev->of_node, "qcom,usbcss-hs-xtalk-config", NULL)) {
  4275. rc = wcd939x_read_of_property_u32(dev, "qcom,usbcss-hs-xtalk-config", &prop_val);
  4276. if ((!rc) && (prop_val == XTALK_NONE || prop_val == XTALK_DIGITAL
  4277. || prop_val == XTALK_ANALOG)) {
  4278. usbcss_hs->xtalk.xtalk_config = (enum xtalk_mode) prop_val;
  4279. } else
  4280. dev_dbg(dev, "%s: %s OOB. Default value of %s used.\n",
  4281. __func__, "qcom,usbcss-hs-xtalk-config", "XTALK_NONE");
  4282. } else
  4283. dev_dbg(dev, "%s: %s property not found. Default value of %s used.\n",
  4284. __func__, "qcom,usbcss-hs-xtalk-config", "XTALK_NONE");
  4285. /* k values for linearizer */
  4286. if (of_find_property(dev->of_node, "qcom,usbcss-hs-lin-k-aud", NULL)) {
  4287. rc = wcd939x_read_of_property_s32(dev, "qcom,usbcss-hs-lin-k-aud",
  4288. &prop_val_signed);
  4289. if ((!rc) && (prop_val_signed <= MAX_K_TIMES_100) &&
  4290. (prop_val_signed >= MIN_K_TIMES_100))
  4291. usbcss_hs->aud.k_aud_times_100 = prop_val_signed;
  4292. else
  4293. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n",
  4294. __func__, "qcom,usbcss-hs-lin-k-aud",
  4295. usbcss_hs->aud.k_aud_times_100);
  4296. } else {
  4297. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4298. __func__, "qcom,usbcss-hs-lin-k-aud",
  4299. usbcss_hs->aud.k_aud_times_100);
  4300. }
  4301. /* Differential slope factor */
  4302. if (of_find_property(dev->of_node, "qcom,usbcss-hs-diff-slope", NULL)) {
  4303. rc = wcd939x_read_of_property_u32(dev, "qcom,usbcss-hs-diff-slope", &prop_val);
  4304. if ((!rc) && (prop_val <= MAX_DIFF_SLOPE_FACTOR) &&
  4305. (prop_val >= MIN_DIFF_SLOPE_FACTOR))
  4306. usbcss_hs->diff_slope_factor_times_1000 = prop_val;
  4307. else
  4308. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n",
  4309. __func__, "qcom,usbcss-hs-diff-slope",
  4310. usbcss_hs->diff_slope_factor_times_1000);
  4311. } else {
  4312. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4313. __func__, "qcom,usbcss-hs-diff-slope",
  4314. usbcss_hs->diff_slope_factor_times_1000);
  4315. }
  4316. /* R_ds(on) */
  4317. parse_xtalk_param(dev, usbcss_hs->gnd.rdson_mohms, &prop_val, "qcom,usbcss-hs-rdson-6v");
  4318. usbcss_hs->gnd.rdson_mohms = prop_val;
  4319. /* R_ds(on) Vgs=3.6V */
  4320. parse_xtalk_param(dev, usbcss_hs->gnd.rdson_3p6v_mohms, &prop_val,
  4321. "qcom,usbcss-hs-rdson-3p6v");
  4322. usbcss_hs->gnd.rdson_3p6v_mohms = prop_val;
  4323. usbcss_hs->gnd.gnd_ext_fet_delta_mohms = (s32) (usbcss_hs->gnd.rdson_3p6v_mohms -
  4324. usbcss_hs->gnd.rdson_mohms);
  4325. /* r_common_gnd_margin */
  4326. parse_xtalk_param(dev, usbcss_hs->gnd.r_common_gnd_margin, &prop_val,
  4327. "qcom,usbcss-hs-rcom-margin");
  4328. usbcss_hs->gnd.r_common_gnd_margin = prop_val;
  4329. /* r1 */
  4330. parse_xtalk_param(dev, usbcss_hs->aud.l.r1, &prop_val,
  4331. "qcom,usbcss-hs-r1-l");
  4332. usbcss_hs->aud.l.r1 = prop_val;
  4333. parse_xtalk_param(dev, usbcss_hs->aud.r.r1, &prop_val,
  4334. "qcom,usbcss-hs-r1-r");
  4335. usbcss_hs->aud.r.r1 = prop_val;
  4336. /* r3 */
  4337. parse_xtalk_param(dev, usbcss_hs->aud.l.r3, &prop_val,
  4338. "qcom,usbcss-hs-r3-l");
  4339. usbcss_hs->aud.l.r3 = prop_val;
  4340. parse_xtalk_param(dev, usbcss_hs->aud.r.r3, &prop_val,
  4341. "qcom,usbcss-hs-r3-r");
  4342. usbcss_hs->aud.r.r3 = prop_val;
  4343. /* r4 */
  4344. parse_xtalk_param(dev, usbcss_hs->gnd.sbu1.r4, &prop_val,
  4345. "qcom,usbcss-hs-r4-sbu1");
  4346. usbcss_hs->gnd.sbu1.r4 = prop_val;
  4347. parse_xtalk_param(dev, usbcss_hs->gnd.sbu2.r4, &prop_val,
  4348. "qcom,usbcss-hs-r4-sbu2");
  4349. usbcss_hs->gnd.sbu2.r4 = prop_val;
  4350. /* r_gnd_par_route1_mohms and r_gnd_par_route2_mohms */
  4351. if (usbcss_hs->xtalk.xtalk_config == XTALK_ANALOG) {
  4352. parse_xtalk_param(dev, usbcss_hs->gnd.sbu1.r5, &prop_val,
  4353. "qcom,usbcss-hs-r5-sbu1");
  4354. usbcss_hs->gnd.sbu1.r5 = prop_val;
  4355. parse_xtalk_param(dev, usbcss_hs->gnd.sbu2.r5, &prop_val,
  4356. "qcom,usbcss-hs-r5-sbu2");
  4357. usbcss_hs->gnd.sbu2.r5 = prop_val;
  4358. usbcss_hs->gnd.sbu1.r_gnd_par_route1_mohms = usbcss_hs->gnd.sbu1.r5 +
  4359. usbcss_hs->gnd.sbu1.r4;
  4360. usbcss_hs->gnd.sbu2.r_gnd_par_route1_mohms = usbcss_hs->gnd.sbu2.r5 +
  4361. usbcss_hs->gnd.sbu2.r4;
  4362. usbcss_hs->gnd.sbu1.r_gnd_par_route2_mohms = 125;
  4363. usbcss_hs->gnd.sbu2.r_gnd_par_route2_mohms = 125;
  4364. } else if (usbcss_hs->xtalk.xtalk_config == XTALK_DIGITAL) {
  4365. parse_xtalk_param(dev, usbcss_hs->gnd.sbu1.r6, &prop_val,
  4366. "qcom,usbcss-hs-r6-sbu1");
  4367. usbcss_hs->gnd.sbu1.r6 = prop_val;
  4368. parse_xtalk_param(dev, usbcss_hs->gnd.sbu2.r6, &prop_val,
  4369. "qcom,usbcss-hs-r6-sbu2");
  4370. usbcss_hs->gnd.sbu2.r6 = prop_val;
  4371. usbcss_hs->gnd.sbu1.r_gnd_par_route2_mohms = usbcss_hs->gnd.sbu1.r6 +
  4372. usbcss_hs->gnd.sbu1.r4;
  4373. usbcss_hs->gnd.sbu2.r_gnd_par_route2_mohms = usbcss_hs->gnd.sbu2.r6 +
  4374. usbcss_hs->gnd.sbu2.r4;
  4375. parse_xtalk_param(dev, usbcss_hs->gnd.sbu1.r7, &prop_val,
  4376. "qcom,usbcss-hs-r7-sbu1");
  4377. usbcss_hs->gnd.sbu1.r7 = prop_val;
  4378. usbcss_hs->gnd.sbu1.r_gnd_par_route1_mohms = prop_val;
  4379. parse_xtalk_param(dev, usbcss_hs->gnd.sbu2.r7, &prop_val,
  4380. "qcom,usbcss-hs-r7-sbu2");
  4381. usbcss_hs->gnd.sbu2.r7 = prop_val;
  4382. usbcss_hs->gnd.sbu2.r_gnd_par_route1_mohms = prop_val;
  4383. }
  4384. /* Compute total resistances */
  4385. usbcss_hs->gnd.sbu1.r_gnd_par_tot_mohms = usbcss_hs->gnd.sbu1.r_gnd_par_route1_mohms +
  4386. usbcss_hs->gnd.sbu1.r_gnd_par_route2_mohms;
  4387. usbcss_hs->gnd.sbu2.r_gnd_par_tot_mohms = usbcss_hs->gnd.sbu2.r_gnd_par_route1_mohms +
  4388. usbcss_hs->gnd.sbu2.r_gnd_par_route2_mohms;
  4389. usbcss_hs->gnd.sbu1.r_gnd_res_tot_mohms = get_r_gnd_res_tot_mohms(
  4390. usbcss_hs->gnd.sbu1.r_gnd_int_fet_mohms,
  4391. usbcss_hs->gnd.r_gnd_ext_fet_mohms,
  4392. usbcss_hs->gnd.sbu1.r_gnd_par_tot_mohms);
  4393. usbcss_hs->gnd.sbu2.r_gnd_res_tot_mohms = get_r_gnd_res_tot_mohms(
  4394. usbcss_hs->gnd.sbu2.r_gnd_int_fet_mohms,
  4395. usbcss_hs->gnd.r_gnd_ext_fet_mohms,
  4396. usbcss_hs->gnd.sbu2.r_gnd_par_tot_mohms);
  4397. usbcss_hs->aud.l.r_aud_res_tot_mohms = get_r_aud_res_tot_mohms(
  4398. usbcss_hs->aud.l.r_aud_int_fet_mohms,
  4399. usbcss_hs->aud.l.r_aud_ext_fet_mohms,
  4400. usbcss_hs->aud.l.r3);
  4401. usbcss_hs->aud.r.r_aud_res_tot_mohms = get_r_aud_res_tot_mohms(
  4402. usbcss_hs->aud.r.r_aud_int_fet_mohms,
  4403. usbcss_hs->aud.r.r_aud_ext_fet_mohms,
  4404. usbcss_hs->aud.r.r3);
  4405. /* Fill r_common_gnd buffer */
  4406. r_common_gnd_mohms = usbcss_hs->gnd.rdson_mohms +
  4407. (usbcss_hs->gnd.sbu1.r_gnd_par_route2_mohms +
  4408. usbcss_hs->gnd.sbu2.r_gnd_par_route2_mohms) / 2;
  4409. fill_r_common_gnd_buffer(usbcss_hs, r_common_gnd_mohms);
  4410. /* Determine min val used for linearizer audio tap calculations */
  4411. if (usbcss_hs->gnd.rdson_3p6v_mohms < GND_EXT_FET_MARGIN_MOHMS)
  4412. usbcss_hs->gnd.gnd_ext_fet_min_mohms = 0;
  4413. else if ((usbcss_hs->gnd.rdson_3p6v_mohms - GND_EXT_FET_MARGIN_MOHMS)
  4414. < GND_EXT_FET_MARGIN_MOHMS)
  4415. usbcss_hs->gnd.gnd_ext_fet_min_mohms = usbcss_hs->gnd.rdson_3p6v_mohms -
  4416. GND_EXT_FET_MARGIN_MOHMS;
  4417. else
  4418. usbcss_hs->gnd.gnd_ext_fet_min_mohms = GND_EXT_FET_MARGIN_MOHMS;
  4419. /* Set linearizer calibration codes to be sourced from SW */
  4420. wcd_usbss_linearizer_rdac_cal_code_select(LINEARIZER_SOURCE_SW);
  4421. }
  4422. static int wcd939x_reset_low(struct device *dev)
  4423. {
  4424. struct wcd939x_priv *wcd939x = NULL;
  4425. int rc = 0;
  4426. if (!dev)
  4427. return -ENODEV;
  4428. wcd939x = dev_get_drvdata(dev);
  4429. if (!wcd939x)
  4430. return -EINVAL;
  4431. if (!wcd939x->rst_np) {
  4432. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4433. __func__);
  4434. return -EINVAL;
  4435. }
  4436. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4437. if (rc) {
  4438. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4439. __func__);
  4440. return rc;
  4441. }
  4442. /* 20us sleep required after pulling the reset gpio to LOW */
  4443. usleep_range(20, 30);
  4444. return rc;
  4445. }
  4446. struct wcd939x_pdata *wcd939x_populate_dt_data(struct device *dev)
  4447. {
  4448. struct wcd939x_pdata *pdata = NULL;
  4449. pdata = devm_kzalloc(dev, sizeof(struct wcd939x_pdata),
  4450. GFP_KERNEL);
  4451. if (!pdata)
  4452. return NULL;
  4453. pdata->rst_np = of_parse_phandle(dev->of_node,
  4454. "qcom,wcd-rst-gpio-node", 0);
  4455. if (!pdata->rst_np) {
  4456. dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
  4457. __func__, "qcom,wcd-rst-gpio-node",
  4458. dev->of_node->full_name);
  4459. return NULL;
  4460. }
  4461. /* Parse power supplies */
  4462. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  4463. &pdata->num_supplies);
  4464. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  4465. dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
  4466. __func__);
  4467. return NULL;
  4468. }
  4469. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  4470. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  4471. wcd939x_dt_parse_micbias_info(dev, &pdata->micbias);
  4472. wcd939x_dt_parse_usbcss_hs_info(dev, &pdata->usbcss_hs);
  4473. return pdata;
  4474. }
  4475. static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
  4476. {
  4477. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  4478. __func__, irq);
  4479. return IRQ_HANDLED;
  4480. }
  4481. static struct snd_soc_dai_driver wcd939x_dai[] = {
  4482. {
  4483. .name = "wcd939x_cdc",
  4484. .playback = {
  4485. .stream_name = "WCD939X_AIF Playback",
  4486. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4487. .formats = WCD939X_FORMATS,
  4488. .rate_max = 384000,
  4489. .rate_min = 8000,
  4490. .channels_min = 1,
  4491. .channels_max = 4,
  4492. },
  4493. .capture = {
  4494. .stream_name = "WCD939X_AIF Capture",
  4495. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4496. .formats = WCD939X_FORMATS,
  4497. .rate_max = 384000,
  4498. .rate_min = 8000,
  4499. .channels_min = 1,
  4500. .channels_max = 4,
  4501. },
  4502. },
  4503. };
  4504. static const struct reg_default reg_def_1_1[] = {
  4505. {WCD939X_VBG_FINE_ADJ, 0xA5},
  4506. {WCD939X_FLYBACK_NEW_CTRL_2, 0x0},
  4507. {WCD939X_FLYBACK_NEW_CTRL_3, 0x0},
  4508. {WCD939X_FLYBACK_NEW_CTRL_4, 0x44},
  4509. {WCD939X_PA_GAIN_CTL_R, 0x80},
  4510. };
  4511. static const struct reg_default reg_def_2_0[] = {
  4512. {WCD939X_INTR_MASK_2, 0x3E},
  4513. };
  4514. static const char *version_to_str(u32 version)
  4515. {
  4516. switch (version) {
  4517. case WCD939X_VERSION_1_0:
  4518. return __stringify(WCD939X_1_0);
  4519. case WCD939X_VERSION_1_1:
  4520. return __stringify(WCD939X_1_1);
  4521. case WCD939X_VERSION_2_0:
  4522. return __stringify(WCD939X_2_0);
  4523. }
  4524. return NULL;
  4525. }
  4526. static void wcd939x_update_regmap_cache(struct wcd939x_priv *wcd939x)
  4527. {
  4528. if (wcd939x->version == WCD939X_VERSION_1_0)
  4529. return;
  4530. if (wcd939x->version >= WCD939X_VERSION_1_1) {
  4531. for (int i = 0; i < ARRAY_SIZE(reg_def_1_1); ++i)
  4532. regmap_write(wcd939x->regmap, reg_def_1_1[i].reg, reg_def_1_1[i].def);
  4533. }
  4534. if (wcd939x->version == WCD939X_VERSION_2_0) {
  4535. for (int i = 0; i < ARRAY_SIZE(reg_def_2_0); ++i)
  4536. regmap_write(wcd939x->regmap, reg_def_2_0[i].reg, reg_def_2_0[i].def);
  4537. }
  4538. }
  4539. static int wcd939x_bind(struct device *dev)
  4540. {
  4541. int ret = 0, i = 0, val = 0;
  4542. struct wcd939x_pdata *pdata = dev_get_platdata(dev);
  4543. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4544. u8 id1 = 0, status1 = 0;
  4545. /*
  4546. * Add 5msec delay to provide sufficient time for
  4547. * soundwire auto enumeration of slave devices as
  4548. * as per HW requirement.
  4549. */
  4550. usleep_range(5000, 5010);
  4551. ret = component_bind_all(dev, wcd939x);
  4552. if (ret) {
  4553. dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
  4554. __func__, ret);
  4555. return ret;
  4556. }
  4557. wcd939x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  4558. if (!wcd939x->rx_swr_dev) {
  4559. dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
  4560. __func__);
  4561. ret = -ENODEV;
  4562. goto err;
  4563. }
  4564. wcd939x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  4565. if (!wcd939x->tx_swr_dev) {
  4566. dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
  4567. __func__);
  4568. ret = -ENODEV;
  4569. goto err;
  4570. }
  4571. swr_init_port_params(wcd939x->tx_swr_dev, SWR_NUM_PORTS,
  4572. wcd939x->swr_tx_port_params);
  4573. /* Check WCD9395 version */
  4574. swr_read(wcd939x->tx_swr_dev, wcd939x->tx_swr_dev->dev_num,
  4575. WCD939X_CHIP_ID1, &id1, 1);
  4576. swr_read(wcd939x->tx_swr_dev, wcd939x->tx_swr_dev->dev_num,
  4577. WCD939X_STATUS_REG_1, &status1, 1);
  4578. if (id1 == 0)
  4579. wcd939x->version = ((status1 & 0x3) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
  4580. else if (id1 == 1)
  4581. wcd939x->version = WCD939X_VERSION_2_0;
  4582. wcd939x_version = wcd939x->version;
  4583. dev_info(dev, "%s: wcd9395 version: %s\n", __func__,
  4584. version_to_str(wcd939x->version));
  4585. wcd939x_regmap_config.readable_reg = wcd939x_readable_register;
  4586. wcd939x->regmap = devm_regmap_init_swr(wcd939x->tx_swr_dev,
  4587. &wcd939x_regmap_config);
  4588. if (!wcd939x->regmap) {
  4589. dev_err_ratelimited(dev, "%s: Regmap init failed\n",
  4590. __func__);
  4591. goto err;
  4592. }
  4593. #if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
  4594. regmap_read(wcd939x->regmap, WCD939X_EFUSE_REG_17, &val);
  4595. if (wcd939x_version == WCD939X_VERSION_2_0 && val < 3)
  4596. wcd_usbss_update_default_trim();
  4597. #endif
  4598. wcd939x_update_regmap_cache(wcd939x);
  4599. /* Set all interupts as edge triggered */
  4600. for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
  4601. regmap_write(wcd939x->regmap,
  4602. (WCD939X_INTR_LEVEL_0 + i), 0);
  4603. wcd939x_regmap_irq_chip.irq_drv_data = wcd939x;
  4604. wcd939x->irq_info.wcd_regmap_irq_chip = &wcd939x_regmap_irq_chip;
  4605. wcd939x->irq_info.codec_name = "WCD939X";
  4606. wcd939x->irq_info.regmap = wcd939x->regmap;
  4607. wcd939x->irq_info.dev = dev;
  4608. ret = wcd_irq_init(&wcd939x->irq_info, &wcd939x->virq);
  4609. if (ret) {
  4610. dev_err_ratelimited(wcd939x->dev, "%s: IRQ init failed: %d\n",
  4611. __func__, ret);
  4612. goto err;
  4613. }
  4614. wcd939x->tx_swr_dev->slave_irq = wcd939x->virq;
  4615. ret = wcd939x_set_micbias_data(wcd939x, pdata);
  4616. if (ret < 0) {
  4617. dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
  4618. goto err_irq;
  4619. }
  4620. /* Request for watchdog interrupt */
  4621. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT,
  4622. "HPHR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4623. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT,
  4624. "HPHL PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4625. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT,
  4626. "EAR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4627. /* Disable watchdog interrupt for HPH and EAR */
  4628. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT);
  4629. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT);
  4630. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  4631. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
  4632. wcd939x_dai, ARRAY_SIZE(wcd939x_dai));
  4633. if (ret) {
  4634. dev_err_ratelimited(dev, "%s: Codec registration failed\n",
  4635. __func__);
  4636. goto err_irq;
  4637. }
  4638. wcd939x->dev_up = true;
  4639. return ret;
  4640. err_irq:
  4641. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4642. err:
  4643. component_unbind_all(dev, wcd939x);
  4644. return ret;
  4645. }
  4646. static void wcd939x_unbind(struct device *dev)
  4647. {
  4648. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4649. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT, NULL);
  4650. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT, NULL);
  4651. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT, NULL);
  4652. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4653. snd_soc_unregister_component(dev);
  4654. component_unbind_all(dev, wcd939x);
  4655. }
  4656. static const struct of_device_id wcd939x_dt_match[] = {
  4657. { .compatible = "qcom,wcd939x-codec", .data = "wcd939x"},
  4658. {}
  4659. };
  4660. static const struct component_master_ops wcd939x_comp_ops = {
  4661. .bind = wcd939x_bind,
  4662. .unbind = wcd939x_unbind,
  4663. };
  4664. static int wcd939x_compare_of(struct device *dev, void *data)
  4665. {
  4666. return dev->of_node == data;
  4667. }
  4668. static void wcd939x_release_of(struct device *dev, void *data)
  4669. {
  4670. of_node_put(data);
  4671. }
  4672. static int wcd939x_add_slave_components(struct device *dev,
  4673. struct component_match **matchptr)
  4674. {
  4675. struct device_node *np, *rx_node, *tx_node;
  4676. np = dev->of_node;
  4677. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  4678. if (!rx_node) {
  4679. dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
  4680. return -ENODEV;
  4681. }
  4682. of_node_get(rx_node);
  4683. component_match_add_release(dev, matchptr,
  4684. wcd939x_release_of,
  4685. wcd939x_compare_of,
  4686. rx_node);
  4687. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  4688. if (!tx_node) {
  4689. dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
  4690. return -ENODEV;
  4691. }
  4692. of_node_get(tx_node);
  4693. component_match_add_release(dev, matchptr,
  4694. wcd939x_release_of,
  4695. wcd939x_compare_of,
  4696. tx_node);
  4697. return 0;
  4698. }
  4699. static int wcd939x_probe(struct platform_device *pdev)
  4700. {
  4701. struct component_match *match = NULL;
  4702. struct wcd939x_priv *wcd939x = NULL;
  4703. struct wcd939x_pdata *pdata = NULL;
  4704. struct wcd_ctrl_platform_data *plat_data = NULL;
  4705. struct device *dev = &pdev->dev;
  4706. int ret;
  4707. wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
  4708. GFP_KERNEL);
  4709. if (!wcd939x)
  4710. return -ENOMEM;
  4711. dev_set_drvdata(dev, wcd939x);
  4712. wcd939x->dev = dev;
  4713. pdata = wcd939x_populate_dt_data(dev);
  4714. if (!pdata) {
  4715. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4716. return -EINVAL;
  4717. }
  4718. dev->platform_data = pdata;
  4719. wcd939x->rst_np = pdata->rst_np;
  4720. ret = msm_cdc_init_supplies(dev, &wcd939x->supplies,
  4721. pdata->regulator, pdata->num_supplies);
  4722. if (!wcd939x->supplies) {
  4723. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4724. __func__);
  4725. return ret;
  4726. }
  4727. plat_data = dev_get_platdata(dev->parent);
  4728. if (!plat_data) {
  4729. dev_err(dev, "%s: platform data from parent is NULL\n",
  4730. __func__);
  4731. return -EINVAL;
  4732. }
  4733. wcd939x->handle = (void *)plat_data->handle;
  4734. if (!wcd939x->handle) {
  4735. dev_err(dev, "%s: handle is NULL\n", __func__);
  4736. return -EINVAL;
  4737. }
  4738. wcd939x->update_wcd_event = plat_data->update_wcd_event;
  4739. if (!wcd939x->update_wcd_event) {
  4740. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4741. __func__);
  4742. return -EINVAL;
  4743. }
  4744. wcd939x->register_notifier = plat_data->register_notifier;
  4745. if (!wcd939x->register_notifier) {
  4746. dev_err(dev, "%s: register_notifier api is null!\n",
  4747. __func__);
  4748. return -EINVAL;
  4749. }
  4750. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd939x->supplies,
  4751. pdata->regulator,
  4752. pdata->num_supplies);
  4753. if (ret) {
  4754. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4755. __func__);
  4756. return ret;
  4757. }
  4758. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies,
  4759. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4760. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  4761. wcd939x->supplies, pdata->regulator,
  4762. pdata->num_supplies, "cdc-vdd-px");
  4763. if (ret) {
  4764. dev_err(dev, "%s: vdd px supply enable failed!\n",
  4765. __func__);
  4766. return ret;
  4767. }
  4768. }
  4769. ret = wcd939x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4770. CODEC_RX);
  4771. ret |= wcd939x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4772. CODEC_TX);
  4773. if (ret) {
  4774. dev_err(dev, "Failed to read port mapping\n");
  4775. goto err;
  4776. }
  4777. ret = wcd939x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4778. CODEC_TX);
  4779. if (ret) {
  4780. dev_err(dev, "Failed to read port params\n");
  4781. goto err;
  4782. }
  4783. mutex_init(&wcd939x->wakeup_lock);
  4784. mutex_init(&wcd939x->micb_lock);
  4785. ret = wcd939x_add_slave_components(dev, &match);
  4786. if (ret)
  4787. goto err_lock_init;
  4788. wcd939x_reset(dev);
  4789. wcd939x->wakeup = wcd939x_wakeup;
  4790. return component_master_add_with_match(dev,
  4791. &wcd939x_comp_ops, match);
  4792. err_lock_init:
  4793. mutex_destroy(&wcd939x->micb_lock);
  4794. mutex_destroy(&wcd939x->wakeup_lock);
  4795. err:
  4796. return ret;
  4797. }
  4798. static int wcd939x_remove(struct platform_device *pdev)
  4799. {
  4800. struct wcd939x_priv *wcd939x = NULL;
  4801. wcd939x = platform_get_drvdata(pdev);
  4802. component_master_del(&pdev->dev, &wcd939x_comp_ops);
  4803. mutex_destroy(&wcd939x->micb_lock);
  4804. mutex_destroy(&wcd939x->wakeup_lock);
  4805. dev_set_drvdata(&pdev->dev, NULL);
  4806. return 0;
  4807. }
  4808. #ifdef CONFIG_PM_SLEEP
  4809. static int wcd939x_suspend(struct device *dev)
  4810. {
  4811. struct wcd939x_priv *wcd939x = NULL;
  4812. int ret = 0;
  4813. struct wcd939x_pdata *pdata = NULL;
  4814. if (!dev)
  4815. return -ENODEV;
  4816. wcd939x = dev_get_drvdata(dev);
  4817. if (!wcd939x)
  4818. return -EINVAL;
  4819. pdata = dev_get_platdata(wcd939x->dev);
  4820. if (!pdata) {
  4821. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4822. return -EINVAL;
  4823. }
  4824. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  4825. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4826. wcd939x->supplies,
  4827. pdata->regulator,
  4828. pdata->num_supplies,
  4829. "cdc-vdd-buck");
  4830. if (ret == -EINVAL) {
  4831. dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
  4832. __func__);
  4833. return 0;
  4834. }
  4835. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  4836. }
  4837. if (wcd939x->dapm_bias_off ||
  4838. (wcd939x->component &&
  4839. (snd_soc_component_get_bias_level(wcd939x->component) ==
  4840. SND_SOC_BIAS_OFF))) {
  4841. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4842. wcd939x->supplies,
  4843. pdata->regulator,
  4844. pdata->num_supplies,
  4845. true);
  4846. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4847. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies, pdata->regulator,
  4848. pdata->num_supplies, "cdc-vdd-px")) {
  4849. if (msm_cdc_supply_supports_retention_mode(wcd939x->dev, wcd939x->supplies,
  4850. pdata->regulator, pdata->num_supplies, "cdc-vdd-px") &&
  4851. msm_cdc_check_supply_vote(wcd939x->dev, wcd939x->supplies,
  4852. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4853. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4854. wcd939x->supplies, pdata->regulator,
  4855. pdata->num_supplies, "cdc-vdd-px");
  4856. if (ret) {
  4857. dev_dbg(dev, "%s: vdd px supply suspend failed!\n",
  4858. __func__);
  4859. }
  4860. }
  4861. }
  4862. }
  4863. return 0;
  4864. }
  4865. static int wcd939x_resume(struct device *dev)
  4866. {
  4867. int ret = 0;
  4868. struct wcd939x_priv *wcd939x = NULL;
  4869. struct wcd939x_pdata *pdata = NULL;
  4870. if (!dev)
  4871. return -ENODEV;
  4872. wcd939x = dev_get_drvdata(dev);
  4873. if (!wcd939x)
  4874. return -EINVAL;
  4875. pdata = dev_get_platdata(wcd939x->dev);
  4876. if (!pdata) {
  4877. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4878. return -EINVAL;
  4879. }
  4880. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies, pdata->regulator,
  4881. pdata->num_supplies, "cdc-vdd-px")) {
  4882. if (msm_cdc_supply_supports_retention_mode(wcd939x->dev, wcd939x->supplies,
  4883. pdata->regulator, pdata->num_supplies, "cdc-vdd-px") &&
  4884. !msm_cdc_check_supply_vote(wcd939x->dev, wcd939x->supplies,
  4885. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4886. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev, wcd939x->supplies,
  4887. pdata->regulator, pdata->num_supplies, "cdc-vdd-px");
  4888. if (ret) {
  4889. dev_dbg(dev, "%s: vdd px supply resume failed!\n",
  4890. __func__);
  4891. }
  4892. }
  4893. }
  4894. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask)) {
  4895. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4896. wcd939x->supplies,
  4897. pdata->regulator,
  4898. pdata->num_supplies,
  4899. false);
  4900. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4901. }
  4902. return 0;
  4903. }
  4904. static const struct dev_pm_ops wcd939x_dev_pm_ops = {
  4905. .suspend_late = wcd939x_suspend,
  4906. .resume_early = wcd939x_resume,
  4907. };
  4908. #endif
  4909. static struct platform_driver wcd939x_codec_driver = {
  4910. .probe = wcd939x_probe,
  4911. .remove = wcd939x_remove,
  4912. .driver = {
  4913. .name = "wcd939x_codec",
  4914. .owner = THIS_MODULE,
  4915. .of_match_table = of_match_ptr(wcd939x_dt_match),
  4916. #ifdef CONFIG_PM_SLEEP
  4917. .pm = &wcd939x_dev_pm_ops,
  4918. #endif
  4919. .suppress_bind_attrs = true,
  4920. },
  4921. };
  4922. module_platform_driver(wcd939x_codec_driver);
  4923. MODULE_DESCRIPTION("WCD939X Codec driver");
  4924. MODULE_LICENSE("GPL v2");