kona.c 183 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "sm8250-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. enum {
  69. TDM_0 = 0,
  70. TDM_1,
  71. TDM_2,
  72. TDM_3,
  73. TDM_4,
  74. TDM_5,
  75. TDM_6,
  76. TDM_7,
  77. TDM_PORT_MAX,
  78. };
  79. enum {
  80. TDM_PRI = 0,
  81. TDM_SEC,
  82. TDM_TERT,
  83. TDM_INTERFACE_MAX,
  84. };
  85. enum {
  86. PRIM_AUX_PCM = 0,
  87. SEC_AUX_PCM,
  88. TERT_AUX_PCM,
  89. AUX_PCM_MAX,
  90. };
  91. enum {
  92. PRIM_MI2S = 0,
  93. SEC_MI2S,
  94. TERT_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. WSA_CDC_DMA_RX_0 = 0,
  99. WSA_CDC_DMA_RX_1,
  100. RX_CDC_DMA_RX_0,
  101. RX_CDC_DMA_RX_1,
  102. RX_CDC_DMA_RX_2,
  103. RX_CDC_DMA_RX_3,
  104. RX_CDC_DMA_RX_5,
  105. CDC_DMA_RX_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_TX_0 = 0,
  109. WSA_CDC_DMA_TX_1,
  110. WSA_CDC_DMA_TX_2,
  111. TX_CDC_DMA_TX_0,
  112. TX_CDC_DMA_TX_3,
  113. TX_CDC_DMA_TX_4,
  114. VA_CDC_DMA_TX_0,
  115. VA_CDC_DMA_TX_1,
  116. VA_CDC_DMA_TX_2,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. SLIM_RX_7 = 0,
  121. SLIM_RX_MAX,
  122. };
  123. enum {
  124. SLIM_TX_7 = 0,
  125. SLIM_TX_MAX,
  126. };
  127. enum {
  128. AFE_LOOPBACK_TX_IDX = 0,
  129. AFE_LOOPBACK_TX_IDX_MAX,
  130. };
  131. struct msm_asoc_mach_data {
  132. struct snd_info_entry *codec_root;
  133. int usbc_en2_gpio; /* used by gpio driver API */
  134. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  135. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  136. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  137. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  138. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  139. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  140. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  141. bool is_afe_config_done;
  142. struct device_node *fsa_handle;
  143. };
  144. struct tdm_port {
  145. u32 mode;
  146. u32 channel;
  147. };
  148. enum {
  149. EXT_DISP_RX_IDX_DP = 0,
  150. EXT_DISP_RX_IDX_MAX,
  151. };
  152. struct msm_wsa881x_dev_info {
  153. struct device_node *of_node;
  154. u32 index;
  155. };
  156. struct aux_codec_dev_info {
  157. struct device_node *of_node;
  158. u32 index;
  159. };
  160. struct dev_config {
  161. u32 sample_rate;
  162. u32 bit_format;
  163. u32 channels;
  164. };
  165. /* Default configuration of slimbus channels */
  166. static struct dev_config slim_rx_cfg[] = {
  167. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  168. };
  169. static struct dev_config slim_tx_cfg[] = {
  170. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  171. };
  172. /* Default configuration of external display BE */
  173. static struct dev_config ext_disp_rx_cfg[] = {
  174. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  175. };
  176. static struct dev_config usb_rx_cfg = {
  177. .sample_rate = SAMPLING_RATE_48KHZ,
  178. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  179. .channels = 2,
  180. };
  181. static struct dev_config usb_tx_cfg = {
  182. .sample_rate = SAMPLING_RATE_48KHZ,
  183. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  184. .channels = 1,
  185. };
  186. static struct dev_config proxy_rx_cfg = {
  187. .sample_rate = SAMPLING_RATE_48KHZ,
  188. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  189. .channels = 2,
  190. };
  191. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  192. {
  193. AFE_API_VERSION_I2S_CONFIG,
  194. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  195. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  196. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  197. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  198. 0,
  199. },
  200. {
  201. AFE_API_VERSION_I2S_CONFIG,
  202. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  203. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  204. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  205. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  206. 0,
  207. },
  208. {
  209. AFE_API_VERSION_I2S_CONFIG,
  210. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  211. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  212. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  213. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  214. 0,
  215. },
  216. };
  217. struct mi2s_conf {
  218. struct mutex lock;
  219. u32 ref_cnt;
  220. u32 msm_is_mi2s_master;
  221. };
  222. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  223. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  224. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  225. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  226. };
  227. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  228. /* Default configuration of TDM channels */
  229. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  230. { /* PRI TDM */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  239. },
  240. { /* SEC TDM */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  249. },
  250. { /* TERT TDM */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  259. },
  260. };
  261. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  262. { /* PRI TDM */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  271. },
  272. { /* SEC TDM */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  281. },
  282. { /* TERT TDM */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  291. },
  292. };
  293. /* Default configuration of AUX PCM channels */
  294. static struct dev_config aux_pcm_rx_cfg[] = {
  295. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  296. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  297. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  298. };
  299. static struct dev_config aux_pcm_tx_cfg[] = {
  300. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  301. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  302. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. };
  304. /* Default configuration of MI2S channels */
  305. static struct dev_config mi2s_rx_cfg[] = {
  306. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  307. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  308. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  309. };
  310. static struct dev_config mi2s_tx_cfg[] = {
  311. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. };
  315. /* Default configuration of Codec DMA Interface RX */
  316. static struct dev_config cdc_dma_rx_cfg[] = {
  317. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  318. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  319. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  320. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  321. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  322. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  323. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  324. };
  325. /* Default configuration of Codec DMA Interface TX */
  326. static struct dev_config cdc_dma_tx_cfg[] = {
  327. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  329. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  330. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  331. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  334. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  335. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  336. };
  337. static struct dev_config afe_loopback_tx_cfg[] = {
  338. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  339. };
  340. static int msm_vi_feed_tx_ch = 2;
  341. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  342. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  343. "S32_LE"};
  344. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  345. "Six", "Seven", "Eight"};
  346. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  347. "KHZ_16", "KHZ_22P05",
  348. "KHZ_32", "KHZ_44P1", "KHZ_48",
  349. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  350. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  351. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  352. "Five", "Six", "Seven",
  353. "Eight"};
  354. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  355. "KHZ_48", "KHZ_176P4",
  356. "KHZ_352P8"};
  357. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  358. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  359. "Five", "Six", "Seven", "Eight"};
  360. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  361. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  362. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  363. "KHZ_48", "KHZ_96", "KHZ_192"};
  364. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  365. "Five", "Six", "Seven",
  366. "Eight"};
  367. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  368. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  369. "Five", "Six", "Seven",
  370. "Eight"};
  371. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  372. "KHZ_16", "KHZ_22P05",
  373. "KHZ_32", "KHZ_44P1", "KHZ_48",
  374. "KHZ_88P2", "KHZ_96",
  375. "KHZ_176P4", "KHZ_192",
  376. "KHZ_352P8", "KHZ_384"};
  377. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  378. "S24_3LE"};
  379. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  380. "KHZ_192", "KHZ_32", "KHZ_44P1",
  381. "KHZ_88P2", "KHZ_176P4"};
  382. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  383. "KHZ_44P1", "KHZ_48",
  384. "KHZ_88P2", "KHZ_96"};
  385. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  386. "KHZ_44P1", "KHZ_48",
  387. "KHZ_88P2", "KHZ_96"};
  388. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  389. "KHZ_44P1", "KHZ_48",
  390. "KHZ_88P2", "KHZ_96"};
  391. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  392. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  393. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  394. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  395. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  396. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  397. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  398. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  399. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  400. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  401. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  402. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  403. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  404. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  405. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  406. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  407. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  408. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  409. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  410. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  411. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  412. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  413. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  414. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  415. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  416. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  417. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  418. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  419. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  420. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  421. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  460. cdc_dma_sample_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  462. cdc_dma_sample_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  464. cdc_dma_sample_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  466. cdc_dma_sample_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  468. cdc_dma_sample_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  470. cdc_dma_sample_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  472. cdc_dma_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  474. cdc_dma_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  476. cdc_dma_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  478. cdc_dma_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  480. cdc_dma_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  482. cdc_dma_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  484. cdc_dma_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  486. cdc_dma_sample_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  488. cdc_dma_sample_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  490. cdc_dma_sample_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  494. ext_disp_sample_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  499. static bool is_initial_boot;
  500. static bool codec_reg_done;
  501. static struct snd_soc_aux_dev *msm_aux_dev;
  502. static struct snd_soc_codec_conf *msm_codec_conf;
  503. static struct snd_soc_card snd_soc_card_kona_msm;
  504. static int dmic_0_1_gpio_cnt;
  505. static int dmic_2_3_gpio_cnt;
  506. static int dmic_4_5_gpio_cnt;
  507. static void *def_wcd_mbhc_cal(void);
  508. /*
  509. * Need to report LINEIN
  510. * if R/L channel impedance is larger than 5K ohm
  511. */
  512. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  513. .read_fw_bin = false,
  514. .calibration = NULL,
  515. .detect_extn_cable = true,
  516. .mono_stero_detection = false,
  517. .swap_gnd_mic = NULL,
  518. .hs_ext_micbias = true,
  519. .key_code[0] = KEY_MEDIA,
  520. .key_code[1] = KEY_VOICECOMMAND,
  521. .key_code[2] = KEY_VOLUMEUP,
  522. .key_code[3] = KEY_VOLUMEDOWN,
  523. .key_code[4] = 0,
  524. .key_code[5] = 0,
  525. .key_code[6] = 0,
  526. .key_code[7] = 0,
  527. .linein_th = 5000,
  528. .moisture_en = true,
  529. .mbhc_micbias = MIC_BIAS_2,
  530. .anc_micbias = MIC_BIAS_2,
  531. .enable_anc_mic_detect = false,
  532. };
  533. static inline int param_is_mask(int p)
  534. {
  535. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  536. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  537. }
  538. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  539. int n)
  540. {
  541. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  542. }
  543. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  544. unsigned int bit)
  545. {
  546. if (bit >= SNDRV_MASK_MAX)
  547. return;
  548. if (param_is_mask(n)) {
  549. struct snd_mask *m = param_to_mask(p, n);
  550. m->bits[0] = 0;
  551. m->bits[1] = 0;
  552. m->bits[bit >> 5] |= (1 << (bit & 31));
  553. }
  554. }
  555. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  556. struct snd_ctl_elem_value *ucontrol)
  557. {
  558. int sample_rate_val = 0;
  559. switch (usb_rx_cfg.sample_rate) {
  560. case SAMPLING_RATE_384KHZ:
  561. sample_rate_val = 12;
  562. break;
  563. case SAMPLING_RATE_352P8KHZ:
  564. sample_rate_val = 11;
  565. break;
  566. case SAMPLING_RATE_192KHZ:
  567. sample_rate_val = 10;
  568. break;
  569. case SAMPLING_RATE_176P4KHZ:
  570. sample_rate_val = 9;
  571. break;
  572. case SAMPLING_RATE_96KHZ:
  573. sample_rate_val = 8;
  574. break;
  575. case SAMPLING_RATE_88P2KHZ:
  576. sample_rate_val = 7;
  577. break;
  578. case SAMPLING_RATE_48KHZ:
  579. sample_rate_val = 6;
  580. break;
  581. case SAMPLING_RATE_44P1KHZ:
  582. sample_rate_val = 5;
  583. break;
  584. case SAMPLING_RATE_32KHZ:
  585. sample_rate_val = 4;
  586. break;
  587. case SAMPLING_RATE_22P05KHZ:
  588. sample_rate_val = 3;
  589. break;
  590. case SAMPLING_RATE_16KHZ:
  591. sample_rate_val = 2;
  592. break;
  593. case SAMPLING_RATE_11P025KHZ:
  594. sample_rate_val = 1;
  595. break;
  596. case SAMPLING_RATE_8KHZ:
  597. default:
  598. sample_rate_val = 0;
  599. break;
  600. }
  601. ucontrol->value.integer.value[0] = sample_rate_val;
  602. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  603. usb_rx_cfg.sample_rate);
  604. return 0;
  605. }
  606. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  607. struct snd_ctl_elem_value *ucontrol)
  608. {
  609. switch (ucontrol->value.integer.value[0]) {
  610. case 12:
  611. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  612. break;
  613. case 11:
  614. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  615. break;
  616. case 10:
  617. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  618. break;
  619. case 9:
  620. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  621. break;
  622. case 8:
  623. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  624. break;
  625. case 7:
  626. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  627. break;
  628. case 6:
  629. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  630. break;
  631. case 5:
  632. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  633. break;
  634. case 4:
  635. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  636. break;
  637. case 3:
  638. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  639. break;
  640. case 2:
  641. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  642. break;
  643. case 1:
  644. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  645. break;
  646. case 0:
  647. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  648. break;
  649. default:
  650. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  651. break;
  652. }
  653. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  654. __func__, ucontrol->value.integer.value[0],
  655. usb_rx_cfg.sample_rate);
  656. return 0;
  657. }
  658. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  659. struct snd_ctl_elem_value *ucontrol)
  660. {
  661. int sample_rate_val = 0;
  662. switch (usb_tx_cfg.sample_rate) {
  663. case SAMPLING_RATE_384KHZ:
  664. sample_rate_val = 12;
  665. break;
  666. case SAMPLING_RATE_352P8KHZ:
  667. sample_rate_val = 11;
  668. break;
  669. case SAMPLING_RATE_192KHZ:
  670. sample_rate_val = 10;
  671. break;
  672. case SAMPLING_RATE_176P4KHZ:
  673. sample_rate_val = 9;
  674. break;
  675. case SAMPLING_RATE_96KHZ:
  676. sample_rate_val = 8;
  677. break;
  678. case SAMPLING_RATE_88P2KHZ:
  679. sample_rate_val = 7;
  680. break;
  681. case SAMPLING_RATE_48KHZ:
  682. sample_rate_val = 6;
  683. break;
  684. case SAMPLING_RATE_44P1KHZ:
  685. sample_rate_val = 5;
  686. break;
  687. case SAMPLING_RATE_32KHZ:
  688. sample_rate_val = 4;
  689. break;
  690. case SAMPLING_RATE_22P05KHZ:
  691. sample_rate_val = 3;
  692. break;
  693. case SAMPLING_RATE_16KHZ:
  694. sample_rate_val = 2;
  695. break;
  696. case SAMPLING_RATE_11P025KHZ:
  697. sample_rate_val = 1;
  698. break;
  699. case SAMPLING_RATE_8KHZ:
  700. sample_rate_val = 0;
  701. break;
  702. default:
  703. sample_rate_val = 6;
  704. break;
  705. }
  706. ucontrol->value.integer.value[0] = sample_rate_val;
  707. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  708. usb_tx_cfg.sample_rate);
  709. return 0;
  710. }
  711. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  712. struct snd_ctl_elem_value *ucontrol)
  713. {
  714. switch (ucontrol->value.integer.value[0]) {
  715. case 12:
  716. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  717. break;
  718. case 11:
  719. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  720. break;
  721. case 10:
  722. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  723. break;
  724. case 9:
  725. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  726. break;
  727. case 8:
  728. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  729. break;
  730. case 7:
  731. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  732. break;
  733. case 6:
  734. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  735. break;
  736. case 5:
  737. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  738. break;
  739. case 4:
  740. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  741. break;
  742. case 3:
  743. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  744. break;
  745. case 2:
  746. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  747. break;
  748. case 1:
  749. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  750. break;
  751. case 0:
  752. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  753. break;
  754. default:
  755. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  756. break;
  757. }
  758. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  759. __func__, ucontrol->value.integer.value[0],
  760. usb_tx_cfg.sample_rate);
  761. return 0;
  762. }
  763. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  764. struct snd_ctl_elem_value *ucontrol)
  765. {
  766. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  767. afe_loopback_tx_cfg[0].channels);
  768. ucontrol->value.enumerated.item[0] =
  769. afe_loopback_tx_cfg[0].channels - 1;
  770. return 0;
  771. }
  772. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  773. struct snd_ctl_elem_value *ucontrol)
  774. {
  775. afe_loopback_tx_cfg[0].channels =
  776. ucontrol->value.enumerated.item[0] + 1;
  777. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  778. afe_loopback_tx_cfg[0].channels);
  779. return 1;
  780. }
  781. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  782. struct snd_ctl_elem_value *ucontrol)
  783. {
  784. switch (usb_rx_cfg.bit_format) {
  785. case SNDRV_PCM_FORMAT_S32_LE:
  786. ucontrol->value.integer.value[0] = 3;
  787. break;
  788. case SNDRV_PCM_FORMAT_S24_3LE:
  789. ucontrol->value.integer.value[0] = 2;
  790. break;
  791. case SNDRV_PCM_FORMAT_S24_LE:
  792. ucontrol->value.integer.value[0] = 1;
  793. break;
  794. case SNDRV_PCM_FORMAT_S16_LE:
  795. default:
  796. ucontrol->value.integer.value[0] = 0;
  797. break;
  798. }
  799. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  800. __func__, usb_rx_cfg.bit_format,
  801. ucontrol->value.integer.value[0]);
  802. return 0;
  803. }
  804. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  805. struct snd_ctl_elem_value *ucontrol)
  806. {
  807. int rc = 0;
  808. switch (ucontrol->value.integer.value[0]) {
  809. case 3:
  810. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  811. break;
  812. case 2:
  813. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  814. break;
  815. case 1:
  816. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  817. break;
  818. case 0:
  819. default:
  820. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  821. break;
  822. }
  823. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  824. __func__, usb_rx_cfg.bit_format,
  825. ucontrol->value.integer.value[0]);
  826. return rc;
  827. }
  828. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. switch (usb_tx_cfg.bit_format) {
  832. case SNDRV_PCM_FORMAT_S32_LE:
  833. ucontrol->value.integer.value[0] = 3;
  834. break;
  835. case SNDRV_PCM_FORMAT_S24_3LE:
  836. ucontrol->value.integer.value[0] = 2;
  837. break;
  838. case SNDRV_PCM_FORMAT_S24_LE:
  839. ucontrol->value.integer.value[0] = 1;
  840. break;
  841. case SNDRV_PCM_FORMAT_S16_LE:
  842. default:
  843. ucontrol->value.integer.value[0] = 0;
  844. break;
  845. }
  846. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  847. __func__, usb_tx_cfg.bit_format,
  848. ucontrol->value.integer.value[0]);
  849. return 0;
  850. }
  851. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  852. struct snd_ctl_elem_value *ucontrol)
  853. {
  854. int rc = 0;
  855. switch (ucontrol->value.integer.value[0]) {
  856. case 3:
  857. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  858. break;
  859. case 2:
  860. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  861. break;
  862. case 1:
  863. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  864. break;
  865. case 0:
  866. default:
  867. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  868. break;
  869. }
  870. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  871. __func__, usb_tx_cfg.bit_format,
  872. ucontrol->value.integer.value[0]);
  873. return rc;
  874. }
  875. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  876. struct snd_ctl_elem_value *ucontrol)
  877. {
  878. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  879. usb_rx_cfg.channels);
  880. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  881. return 0;
  882. }
  883. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  884. struct snd_ctl_elem_value *ucontrol)
  885. {
  886. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  887. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  888. return 1;
  889. }
  890. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  891. struct snd_ctl_elem_value *ucontrol)
  892. {
  893. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  894. usb_tx_cfg.channels);
  895. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  896. return 0;
  897. }
  898. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  899. struct snd_ctl_elem_value *ucontrol)
  900. {
  901. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  902. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  903. return 1;
  904. }
  905. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  906. struct snd_ctl_elem_value *ucontrol)
  907. {
  908. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  909. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  910. ucontrol->value.integer.value[0]);
  911. return 0;
  912. }
  913. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  914. struct snd_ctl_elem_value *ucontrol)
  915. {
  916. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  917. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  918. return 1;
  919. }
  920. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  921. {
  922. int idx = 0;
  923. if (strnstr(kcontrol->id.name, "Display Port RX",
  924. sizeof("Display Port RX"))) {
  925. idx = EXT_DISP_RX_IDX_DP;
  926. } else {
  927. pr_err("%s: unsupported BE: %s\n",
  928. __func__, kcontrol->id.name);
  929. idx = -EINVAL;
  930. }
  931. return idx;
  932. }
  933. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  934. struct snd_ctl_elem_value *ucontrol)
  935. {
  936. int idx = ext_disp_get_port_idx(kcontrol);
  937. if (idx < 0)
  938. return idx;
  939. switch (ext_disp_rx_cfg[idx].bit_format) {
  940. case SNDRV_PCM_FORMAT_S24_3LE:
  941. ucontrol->value.integer.value[0] = 2;
  942. break;
  943. case SNDRV_PCM_FORMAT_S24_LE:
  944. ucontrol->value.integer.value[0] = 1;
  945. break;
  946. case SNDRV_PCM_FORMAT_S16_LE:
  947. default:
  948. ucontrol->value.integer.value[0] = 0;
  949. break;
  950. }
  951. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  952. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  953. ucontrol->value.integer.value[0]);
  954. return 0;
  955. }
  956. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  957. struct snd_ctl_elem_value *ucontrol)
  958. {
  959. int idx = ext_disp_get_port_idx(kcontrol);
  960. if (idx < 0)
  961. return idx;
  962. switch (ucontrol->value.integer.value[0]) {
  963. case 2:
  964. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  965. break;
  966. case 1:
  967. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  968. break;
  969. case 0:
  970. default:
  971. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  972. break;
  973. }
  974. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  975. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  976. ucontrol->value.integer.value[0]);
  977. return 0;
  978. }
  979. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  980. struct snd_ctl_elem_value *ucontrol)
  981. {
  982. int idx = ext_disp_get_port_idx(kcontrol);
  983. if (idx < 0)
  984. return idx;
  985. ucontrol->value.integer.value[0] =
  986. ext_disp_rx_cfg[idx].channels - 2;
  987. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  988. idx, ext_disp_rx_cfg[idx].channels);
  989. return 0;
  990. }
  991. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  992. struct snd_ctl_elem_value *ucontrol)
  993. {
  994. int idx = ext_disp_get_port_idx(kcontrol);
  995. if (idx < 0)
  996. return idx;
  997. ext_disp_rx_cfg[idx].channels =
  998. ucontrol->value.integer.value[0] + 2;
  999. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1000. idx, ext_disp_rx_cfg[idx].channels);
  1001. return 1;
  1002. }
  1003. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1004. struct snd_ctl_elem_value *ucontrol)
  1005. {
  1006. int sample_rate_val;
  1007. int idx = ext_disp_get_port_idx(kcontrol);
  1008. if (idx < 0)
  1009. return idx;
  1010. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1011. case SAMPLING_RATE_176P4KHZ:
  1012. sample_rate_val = 6;
  1013. break;
  1014. case SAMPLING_RATE_88P2KHZ:
  1015. sample_rate_val = 5;
  1016. break;
  1017. case SAMPLING_RATE_44P1KHZ:
  1018. sample_rate_val = 4;
  1019. break;
  1020. case SAMPLING_RATE_32KHZ:
  1021. sample_rate_val = 3;
  1022. break;
  1023. case SAMPLING_RATE_192KHZ:
  1024. sample_rate_val = 2;
  1025. break;
  1026. case SAMPLING_RATE_96KHZ:
  1027. sample_rate_val = 1;
  1028. break;
  1029. case SAMPLING_RATE_48KHZ:
  1030. default:
  1031. sample_rate_val = 0;
  1032. break;
  1033. }
  1034. ucontrol->value.integer.value[0] = sample_rate_val;
  1035. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1036. idx, ext_disp_rx_cfg[idx].sample_rate);
  1037. return 0;
  1038. }
  1039. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1040. struct snd_ctl_elem_value *ucontrol)
  1041. {
  1042. int idx = ext_disp_get_port_idx(kcontrol);
  1043. if (idx < 0)
  1044. return idx;
  1045. switch (ucontrol->value.integer.value[0]) {
  1046. case 6:
  1047. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1048. break;
  1049. case 5:
  1050. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1051. break;
  1052. case 4:
  1053. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1054. break;
  1055. case 3:
  1056. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1057. break;
  1058. case 2:
  1059. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1060. break;
  1061. case 1:
  1062. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1063. break;
  1064. case 0:
  1065. default:
  1066. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1067. break;
  1068. }
  1069. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1070. __func__, ucontrol->value.integer.value[0], idx,
  1071. ext_disp_rx_cfg[idx].sample_rate);
  1072. return 0;
  1073. }
  1074. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1075. struct snd_ctl_elem_value *ucontrol)
  1076. {
  1077. pr_debug("%s: proxy_rx channels = %d\n",
  1078. __func__, proxy_rx_cfg.channels);
  1079. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1080. return 0;
  1081. }
  1082. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1083. struct snd_ctl_elem_value *ucontrol)
  1084. {
  1085. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1086. pr_debug("%s: proxy_rx channels = %d\n",
  1087. __func__, proxy_rx_cfg.channels);
  1088. return 1;
  1089. }
  1090. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1091. struct tdm_port *port)
  1092. {
  1093. if (port) {
  1094. if (strnstr(kcontrol->id.name, "PRI",
  1095. sizeof(kcontrol->id.name))) {
  1096. port->mode = TDM_PRI;
  1097. } else if (strnstr(kcontrol->id.name, "SEC",
  1098. sizeof(kcontrol->id.name))) {
  1099. port->mode = TDM_SEC;
  1100. } else if (strnstr(kcontrol->id.name, "TERT",
  1101. sizeof(kcontrol->id.name))) {
  1102. port->mode = TDM_TERT;
  1103. } else {
  1104. pr_err("%s: unsupported mode in: %s\n",
  1105. __func__, kcontrol->id.name);
  1106. return -EINVAL;
  1107. }
  1108. if (strnstr(kcontrol->id.name, "RX_0",
  1109. sizeof(kcontrol->id.name)) ||
  1110. strnstr(kcontrol->id.name, "TX_0",
  1111. sizeof(kcontrol->id.name))) {
  1112. port->channel = TDM_0;
  1113. } else if (strnstr(kcontrol->id.name, "RX_1",
  1114. sizeof(kcontrol->id.name)) ||
  1115. strnstr(kcontrol->id.name, "TX_1",
  1116. sizeof(kcontrol->id.name))) {
  1117. port->channel = TDM_1;
  1118. } else if (strnstr(kcontrol->id.name, "RX_2",
  1119. sizeof(kcontrol->id.name)) ||
  1120. strnstr(kcontrol->id.name, "TX_2",
  1121. sizeof(kcontrol->id.name))) {
  1122. port->channel = TDM_2;
  1123. } else if (strnstr(kcontrol->id.name, "RX_3",
  1124. sizeof(kcontrol->id.name)) ||
  1125. strnstr(kcontrol->id.name, "TX_3",
  1126. sizeof(kcontrol->id.name))) {
  1127. port->channel = TDM_3;
  1128. } else if (strnstr(kcontrol->id.name, "RX_4",
  1129. sizeof(kcontrol->id.name)) ||
  1130. strnstr(kcontrol->id.name, "TX_4",
  1131. sizeof(kcontrol->id.name))) {
  1132. port->channel = TDM_4;
  1133. } else if (strnstr(kcontrol->id.name, "RX_5",
  1134. sizeof(kcontrol->id.name)) ||
  1135. strnstr(kcontrol->id.name, "TX_5",
  1136. sizeof(kcontrol->id.name))) {
  1137. port->channel = TDM_5;
  1138. } else if (strnstr(kcontrol->id.name, "RX_6",
  1139. sizeof(kcontrol->id.name)) ||
  1140. strnstr(kcontrol->id.name, "TX_6",
  1141. sizeof(kcontrol->id.name))) {
  1142. port->channel = TDM_6;
  1143. } else if (strnstr(kcontrol->id.name, "RX_7",
  1144. sizeof(kcontrol->id.name)) ||
  1145. strnstr(kcontrol->id.name, "TX_7",
  1146. sizeof(kcontrol->id.name))) {
  1147. port->channel = TDM_7;
  1148. } else {
  1149. pr_err("%s: unsupported channel in: %s\n",
  1150. __func__, kcontrol->id.name);
  1151. return -EINVAL;
  1152. }
  1153. } else {
  1154. return -EINVAL;
  1155. }
  1156. return 0;
  1157. }
  1158. static int tdm_get_sample_rate(int value)
  1159. {
  1160. int sample_rate = 0;
  1161. switch (value) {
  1162. case 0:
  1163. sample_rate = SAMPLING_RATE_8KHZ;
  1164. break;
  1165. case 1:
  1166. sample_rate = SAMPLING_RATE_16KHZ;
  1167. break;
  1168. case 2:
  1169. sample_rate = SAMPLING_RATE_32KHZ;
  1170. break;
  1171. case 3:
  1172. sample_rate = SAMPLING_RATE_48KHZ;
  1173. break;
  1174. case 4:
  1175. sample_rate = SAMPLING_RATE_176P4KHZ;
  1176. break;
  1177. case 5:
  1178. sample_rate = SAMPLING_RATE_352P8KHZ;
  1179. break;
  1180. default:
  1181. sample_rate = SAMPLING_RATE_48KHZ;
  1182. break;
  1183. }
  1184. return sample_rate;
  1185. }
  1186. static int tdm_get_sample_rate_val(int sample_rate)
  1187. {
  1188. int sample_rate_val = 0;
  1189. switch (sample_rate) {
  1190. case SAMPLING_RATE_8KHZ:
  1191. sample_rate_val = 0;
  1192. break;
  1193. case SAMPLING_RATE_16KHZ:
  1194. sample_rate_val = 1;
  1195. break;
  1196. case SAMPLING_RATE_32KHZ:
  1197. sample_rate_val = 2;
  1198. break;
  1199. case SAMPLING_RATE_48KHZ:
  1200. sample_rate_val = 3;
  1201. break;
  1202. case SAMPLING_RATE_176P4KHZ:
  1203. sample_rate_val = 4;
  1204. break;
  1205. case SAMPLING_RATE_352P8KHZ:
  1206. sample_rate_val = 5;
  1207. break;
  1208. default:
  1209. sample_rate_val = 3;
  1210. break;
  1211. }
  1212. return sample_rate_val;
  1213. }
  1214. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1215. struct snd_ctl_elem_value *ucontrol)
  1216. {
  1217. struct tdm_port port;
  1218. int ret = tdm_get_port_idx(kcontrol, &port);
  1219. if (ret) {
  1220. pr_err("%s: unsupported control: %s\n",
  1221. __func__, kcontrol->id.name);
  1222. } else {
  1223. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1224. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1225. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1226. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1227. ucontrol->value.enumerated.item[0]);
  1228. }
  1229. return ret;
  1230. }
  1231. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1232. struct snd_ctl_elem_value *ucontrol)
  1233. {
  1234. struct tdm_port port;
  1235. int ret = tdm_get_port_idx(kcontrol, &port);
  1236. if (ret) {
  1237. pr_err("%s: unsupported control: %s\n",
  1238. __func__, kcontrol->id.name);
  1239. } else {
  1240. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1241. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1242. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1243. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1244. ucontrol->value.enumerated.item[0]);
  1245. }
  1246. return ret;
  1247. }
  1248. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1249. struct snd_ctl_elem_value *ucontrol)
  1250. {
  1251. struct tdm_port port;
  1252. int ret = tdm_get_port_idx(kcontrol, &port);
  1253. if (ret) {
  1254. pr_err("%s: unsupported control: %s\n",
  1255. __func__, kcontrol->id.name);
  1256. } else {
  1257. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1258. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1259. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1260. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1261. ucontrol->value.enumerated.item[0]);
  1262. }
  1263. return ret;
  1264. }
  1265. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1266. struct snd_ctl_elem_value *ucontrol)
  1267. {
  1268. struct tdm_port port;
  1269. int ret = tdm_get_port_idx(kcontrol, &port);
  1270. if (ret) {
  1271. pr_err("%s: unsupported control: %s\n",
  1272. __func__, kcontrol->id.name);
  1273. } else {
  1274. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1275. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1276. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1277. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1278. ucontrol->value.enumerated.item[0]);
  1279. }
  1280. return ret;
  1281. }
  1282. static int tdm_get_format(int value)
  1283. {
  1284. int format = 0;
  1285. switch (value) {
  1286. case 0:
  1287. format = SNDRV_PCM_FORMAT_S16_LE;
  1288. break;
  1289. case 1:
  1290. format = SNDRV_PCM_FORMAT_S24_LE;
  1291. break;
  1292. case 2:
  1293. format = SNDRV_PCM_FORMAT_S32_LE;
  1294. break;
  1295. default:
  1296. format = SNDRV_PCM_FORMAT_S16_LE;
  1297. break;
  1298. }
  1299. return format;
  1300. }
  1301. static int tdm_get_format_val(int format)
  1302. {
  1303. int value = 0;
  1304. switch (format) {
  1305. case SNDRV_PCM_FORMAT_S16_LE:
  1306. value = 0;
  1307. break;
  1308. case SNDRV_PCM_FORMAT_S24_LE:
  1309. value = 1;
  1310. break;
  1311. case SNDRV_PCM_FORMAT_S32_LE:
  1312. value = 2;
  1313. break;
  1314. default:
  1315. value = 0;
  1316. break;
  1317. }
  1318. return value;
  1319. }
  1320. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1321. struct snd_ctl_elem_value *ucontrol)
  1322. {
  1323. struct tdm_port port;
  1324. int ret = tdm_get_port_idx(kcontrol, &port);
  1325. if (ret) {
  1326. pr_err("%s: unsupported control: %s\n",
  1327. __func__, kcontrol->id.name);
  1328. } else {
  1329. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1330. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1331. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1332. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1333. ucontrol->value.enumerated.item[0]);
  1334. }
  1335. return ret;
  1336. }
  1337. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1338. struct snd_ctl_elem_value *ucontrol)
  1339. {
  1340. struct tdm_port port;
  1341. int ret = tdm_get_port_idx(kcontrol, &port);
  1342. if (ret) {
  1343. pr_err("%s: unsupported control: %s\n",
  1344. __func__, kcontrol->id.name);
  1345. } else {
  1346. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1347. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1348. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1349. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1350. ucontrol->value.enumerated.item[0]);
  1351. }
  1352. return ret;
  1353. }
  1354. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1355. struct snd_ctl_elem_value *ucontrol)
  1356. {
  1357. struct tdm_port port;
  1358. int ret = tdm_get_port_idx(kcontrol, &port);
  1359. if (ret) {
  1360. pr_err("%s: unsupported control: %s\n",
  1361. __func__, kcontrol->id.name);
  1362. } else {
  1363. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1364. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1365. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1366. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1367. ucontrol->value.enumerated.item[0]);
  1368. }
  1369. return ret;
  1370. }
  1371. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1372. struct snd_ctl_elem_value *ucontrol)
  1373. {
  1374. struct tdm_port port;
  1375. int ret = tdm_get_port_idx(kcontrol, &port);
  1376. if (ret) {
  1377. pr_err("%s: unsupported control: %s\n",
  1378. __func__, kcontrol->id.name);
  1379. } else {
  1380. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1381. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1382. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1383. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1384. ucontrol->value.enumerated.item[0]);
  1385. }
  1386. return ret;
  1387. }
  1388. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1389. struct snd_ctl_elem_value *ucontrol)
  1390. {
  1391. struct tdm_port port;
  1392. int ret = tdm_get_port_idx(kcontrol, &port);
  1393. if (ret) {
  1394. pr_err("%s: unsupported control: %s\n",
  1395. __func__, kcontrol->id.name);
  1396. } else {
  1397. ucontrol->value.enumerated.item[0] =
  1398. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1399. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1400. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1401. ucontrol->value.enumerated.item[0]);
  1402. }
  1403. return ret;
  1404. }
  1405. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1406. struct snd_ctl_elem_value *ucontrol)
  1407. {
  1408. struct tdm_port port;
  1409. int ret = tdm_get_port_idx(kcontrol, &port);
  1410. if (ret) {
  1411. pr_err("%s: unsupported control: %s\n",
  1412. __func__, kcontrol->id.name);
  1413. } else {
  1414. tdm_rx_cfg[port.mode][port.channel].channels =
  1415. ucontrol->value.enumerated.item[0] + 1;
  1416. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1417. tdm_rx_cfg[port.mode][port.channel].channels,
  1418. ucontrol->value.enumerated.item[0] + 1);
  1419. }
  1420. return ret;
  1421. }
  1422. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1423. struct snd_ctl_elem_value *ucontrol)
  1424. {
  1425. struct tdm_port port;
  1426. int ret = tdm_get_port_idx(kcontrol, &port);
  1427. if (ret) {
  1428. pr_err("%s: unsupported control: %s\n",
  1429. __func__, kcontrol->id.name);
  1430. } else {
  1431. ucontrol->value.enumerated.item[0] =
  1432. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1433. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1434. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1435. ucontrol->value.enumerated.item[0]);
  1436. }
  1437. return ret;
  1438. }
  1439. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1440. struct snd_ctl_elem_value *ucontrol)
  1441. {
  1442. struct tdm_port port;
  1443. int ret = tdm_get_port_idx(kcontrol, &port);
  1444. if (ret) {
  1445. pr_err("%s: unsupported control: %s\n",
  1446. __func__, kcontrol->id.name);
  1447. } else {
  1448. tdm_tx_cfg[port.mode][port.channel].channels =
  1449. ucontrol->value.enumerated.item[0] + 1;
  1450. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1451. tdm_tx_cfg[port.mode][port.channel].channels,
  1452. ucontrol->value.enumerated.item[0] + 1);
  1453. }
  1454. return ret;
  1455. }
  1456. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1457. {
  1458. int idx = 0;
  1459. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1460. sizeof("PRIM_AUX_PCM"))) {
  1461. idx = PRIM_AUX_PCM;
  1462. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1463. sizeof("SEC_AUX_PCM"))) {
  1464. idx = SEC_AUX_PCM;
  1465. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1466. sizeof("TERT_AUX_PCM"))) {
  1467. idx = TERT_AUX_PCM;
  1468. } else {
  1469. pr_err("%s: unsupported port: %s\n",
  1470. __func__, kcontrol->id.name);
  1471. idx = -EINVAL;
  1472. }
  1473. return idx;
  1474. }
  1475. static int aux_pcm_get_sample_rate(int value)
  1476. {
  1477. int sample_rate = 0;
  1478. switch (value) {
  1479. case 1:
  1480. sample_rate = SAMPLING_RATE_16KHZ;
  1481. break;
  1482. case 0:
  1483. default:
  1484. sample_rate = SAMPLING_RATE_8KHZ;
  1485. break;
  1486. }
  1487. return sample_rate;
  1488. }
  1489. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1490. {
  1491. int sample_rate_val = 0;
  1492. switch (sample_rate) {
  1493. case SAMPLING_RATE_16KHZ:
  1494. sample_rate_val = 1;
  1495. break;
  1496. case SAMPLING_RATE_8KHZ:
  1497. default:
  1498. sample_rate_val = 0;
  1499. break;
  1500. }
  1501. return sample_rate_val;
  1502. }
  1503. static int mi2s_auxpcm_get_format(int value)
  1504. {
  1505. int format = 0;
  1506. switch (value) {
  1507. case 0:
  1508. format = SNDRV_PCM_FORMAT_S16_LE;
  1509. break;
  1510. case 1:
  1511. format = SNDRV_PCM_FORMAT_S24_LE;
  1512. break;
  1513. case 2:
  1514. format = SNDRV_PCM_FORMAT_S24_3LE;
  1515. break;
  1516. case 3:
  1517. format = SNDRV_PCM_FORMAT_S32_LE;
  1518. break;
  1519. default:
  1520. format = SNDRV_PCM_FORMAT_S16_LE;
  1521. break;
  1522. }
  1523. return format;
  1524. }
  1525. static int mi2s_auxpcm_get_format_value(int format)
  1526. {
  1527. int value = 0;
  1528. switch (format) {
  1529. case SNDRV_PCM_FORMAT_S16_LE:
  1530. value = 0;
  1531. break;
  1532. case SNDRV_PCM_FORMAT_S24_LE:
  1533. value = 1;
  1534. break;
  1535. case SNDRV_PCM_FORMAT_S24_3LE:
  1536. value = 2;
  1537. break;
  1538. case SNDRV_PCM_FORMAT_S32_LE:
  1539. value = 3;
  1540. break;
  1541. default:
  1542. value = 0;
  1543. break;
  1544. }
  1545. return value;
  1546. }
  1547. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1548. struct snd_ctl_elem_value *ucontrol)
  1549. {
  1550. int idx = aux_pcm_get_port_idx(kcontrol);
  1551. if (idx < 0)
  1552. return idx;
  1553. ucontrol->value.enumerated.item[0] =
  1554. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1555. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1556. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1557. ucontrol->value.enumerated.item[0]);
  1558. return 0;
  1559. }
  1560. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1561. struct snd_ctl_elem_value *ucontrol)
  1562. {
  1563. int idx = aux_pcm_get_port_idx(kcontrol);
  1564. if (idx < 0)
  1565. return idx;
  1566. aux_pcm_rx_cfg[idx].sample_rate =
  1567. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1568. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1569. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1570. ucontrol->value.enumerated.item[0]);
  1571. return 0;
  1572. }
  1573. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1574. struct snd_ctl_elem_value *ucontrol)
  1575. {
  1576. int idx = aux_pcm_get_port_idx(kcontrol);
  1577. if (idx < 0)
  1578. return idx;
  1579. ucontrol->value.enumerated.item[0] =
  1580. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1581. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1582. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1583. ucontrol->value.enumerated.item[0]);
  1584. return 0;
  1585. }
  1586. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1587. struct snd_ctl_elem_value *ucontrol)
  1588. {
  1589. int idx = aux_pcm_get_port_idx(kcontrol);
  1590. if (idx < 0)
  1591. return idx;
  1592. aux_pcm_tx_cfg[idx].sample_rate =
  1593. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1594. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1595. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1596. ucontrol->value.enumerated.item[0]);
  1597. return 0;
  1598. }
  1599. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1600. struct snd_ctl_elem_value *ucontrol)
  1601. {
  1602. int idx = aux_pcm_get_port_idx(kcontrol);
  1603. if (idx < 0)
  1604. return idx;
  1605. ucontrol->value.enumerated.item[0] =
  1606. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1607. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1608. idx, aux_pcm_rx_cfg[idx].bit_format,
  1609. ucontrol->value.enumerated.item[0]);
  1610. return 0;
  1611. }
  1612. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1613. struct snd_ctl_elem_value *ucontrol)
  1614. {
  1615. int idx = aux_pcm_get_port_idx(kcontrol);
  1616. if (idx < 0)
  1617. return idx;
  1618. aux_pcm_rx_cfg[idx].bit_format =
  1619. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1620. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1621. idx, aux_pcm_rx_cfg[idx].bit_format,
  1622. ucontrol->value.enumerated.item[0]);
  1623. return 0;
  1624. }
  1625. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1626. struct snd_ctl_elem_value *ucontrol)
  1627. {
  1628. int idx = aux_pcm_get_port_idx(kcontrol);
  1629. if (idx < 0)
  1630. return idx;
  1631. ucontrol->value.enumerated.item[0] =
  1632. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1633. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1634. idx, aux_pcm_tx_cfg[idx].bit_format,
  1635. ucontrol->value.enumerated.item[0]);
  1636. return 0;
  1637. }
  1638. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1639. struct snd_ctl_elem_value *ucontrol)
  1640. {
  1641. int idx = aux_pcm_get_port_idx(kcontrol);
  1642. if (idx < 0)
  1643. return idx;
  1644. aux_pcm_tx_cfg[idx].bit_format =
  1645. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1646. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1647. idx, aux_pcm_tx_cfg[idx].bit_format,
  1648. ucontrol->value.enumerated.item[0]);
  1649. return 0;
  1650. }
  1651. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1652. {
  1653. int idx = 0;
  1654. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1655. sizeof("PRIM_MI2S_RX"))) {
  1656. idx = PRIM_MI2S;
  1657. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1658. sizeof("SEC_MI2S_RX"))) {
  1659. idx = SEC_MI2S;
  1660. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1661. sizeof("TERT_MI2S_RX"))) {
  1662. idx = TERT_MI2S;
  1663. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1664. sizeof("PRIM_MI2S_TX"))) {
  1665. idx = PRIM_MI2S;
  1666. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1667. sizeof("SEC_MI2S_TX"))) {
  1668. idx = SEC_MI2S;
  1669. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1670. sizeof("TERT_MI2S_TX"))) {
  1671. idx = TERT_MI2S;
  1672. } else {
  1673. pr_err("%s: unsupported channel: %s\n",
  1674. __func__, kcontrol->id.name);
  1675. idx = -EINVAL;
  1676. }
  1677. return idx;
  1678. }
  1679. static int mi2s_get_sample_rate(int value)
  1680. {
  1681. int sample_rate = 0;
  1682. switch (value) {
  1683. case 0:
  1684. sample_rate = SAMPLING_RATE_8KHZ;
  1685. break;
  1686. case 1:
  1687. sample_rate = SAMPLING_RATE_11P025KHZ;
  1688. break;
  1689. case 2:
  1690. sample_rate = SAMPLING_RATE_16KHZ;
  1691. break;
  1692. case 3:
  1693. sample_rate = SAMPLING_RATE_22P05KHZ;
  1694. break;
  1695. case 4:
  1696. sample_rate = SAMPLING_RATE_32KHZ;
  1697. break;
  1698. case 5:
  1699. sample_rate = SAMPLING_RATE_44P1KHZ;
  1700. break;
  1701. case 6:
  1702. sample_rate = SAMPLING_RATE_48KHZ;
  1703. break;
  1704. case 7:
  1705. sample_rate = SAMPLING_RATE_96KHZ;
  1706. break;
  1707. case 8:
  1708. sample_rate = SAMPLING_RATE_192KHZ;
  1709. break;
  1710. default:
  1711. sample_rate = SAMPLING_RATE_48KHZ;
  1712. break;
  1713. }
  1714. return sample_rate;
  1715. }
  1716. static int mi2s_get_sample_rate_val(int sample_rate)
  1717. {
  1718. int sample_rate_val = 0;
  1719. switch (sample_rate) {
  1720. case SAMPLING_RATE_8KHZ:
  1721. sample_rate_val = 0;
  1722. break;
  1723. case SAMPLING_RATE_11P025KHZ:
  1724. sample_rate_val = 1;
  1725. break;
  1726. case SAMPLING_RATE_16KHZ:
  1727. sample_rate_val = 2;
  1728. break;
  1729. case SAMPLING_RATE_22P05KHZ:
  1730. sample_rate_val = 3;
  1731. break;
  1732. case SAMPLING_RATE_32KHZ:
  1733. sample_rate_val = 4;
  1734. break;
  1735. case SAMPLING_RATE_44P1KHZ:
  1736. sample_rate_val = 5;
  1737. break;
  1738. case SAMPLING_RATE_48KHZ:
  1739. sample_rate_val = 6;
  1740. break;
  1741. case SAMPLING_RATE_96KHZ:
  1742. sample_rate_val = 7;
  1743. break;
  1744. case SAMPLING_RATE_192KHZ:
  1745. sample_rate_val = 8;
  1746. break;
  1747. default:
  1748. sample_rate_val = 6;
  1749. break;
  1750. }
  1751. return sample_rate_val;
  1752. }
  1753. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1754. struct snd_ctl_elem_value *ucontrol)
  1755. {
  1756. int idx = mi2s_get_port_idx(kcontrol);
  1757. if (idx < 0)
  1758. return idx;
  1759. ucontrol->value.enumerated.item[0] =
  1760. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1761. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1762. idx, mi2s_rx_cfg[idx].sample_rate,
  1763. ucontrol->value.enumerated.item[0]);
  1764. return 0;
  1765. }
  1766. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1767. struct snd_ctl_elem_value *ucontrol)
  1768. {
  1769. int idx = mi2s_get_port_idx(kcontrol);
  1770. if (idx < 0)
  1771. return idx;
  1772. mi2s_rx_cfg[idx].sample_rate =
  1773. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1774. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1775. idx, mi2s_rx_cfg[idx].sample_rate,
  1776. ucontrol->value.enumerated.item[0]);
  1777. return 0;
  1778. }
  1779. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1780. struct snd_ctl_elem_value *ucontrol)
  1781. {
  1782. int idx = mi2s_get_port_idx(kcontrol);
  1783. if (idx < 0)
  1784. return idx;
  1785. ucontrol->value.enumerated.item[0] =
  1786. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1787. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1788. idx, mi2s_tx_cfg[idx].sample_rate,
  1789. ucontrol->value.enumerated.item[0]);
  1790. return 0;
  1791. }
  1792. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1793. struct snd_ctl_elem_value *ucontrol)
  1794. {
  1795. int idx = mi2s_get_port_idx(kcontrol);
  1796. if (idx < 0)
  1797. return idx;
  1798. mi2s_tx_cfg[idx].sample_rate =
  1799. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1800. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1801. idx, mi2s_tx_cfg[idx].sample_rate,
  1802. ucontrol->value.enumerated.item[0]);
  1803. return 0;
  1804. }
  1805. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1806. struct snd_ctl_elem_value *ucontrol)
  1807. {
  1808. int idx = mi2s_get_port_idx(kcontrol);
  1809. if (idx < 0)
  1810. return idx;
  1811. ucontrol->value.enumerated.item[0] =
  1812. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1813. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1814. idx, mi2s_rx_cfg[idx].bit_format,
  1815. ucontrol->value.enumerated.item[0]);
  1816. return 0;
  1817. }
  1818. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1819. struct snd_ctl_elem_value *ucontrol)
  1820. {
  1821. int idx = mi2s_get_port_idx(kcontrol);
  1822. if (idx < 0)
  1823. return idx;
  1824. mi2s_rx_cfg[idx].bit_format =
  1825. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1826. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1827. idx, mi2s_rx_cfg[idx].bit_format,
  1828. ucontrol->value.enumerated.item[0]);
  1829. return 0;
  1830. }
  1831. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1832. struct snd_ctl_elem_value *ucontrol)
  1833. {
  1834. int idx = mi2s_get_port_idx(kcontrol);
  1835. if (idx < 0)
  1836. return idx;
  1837. ucontrol->value.enumerated.item[0] =
  1838. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1839. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1840. idx, mi2s_tx_cfg[idx].bit_format,
  1841. ucontrol->value.enumerated.item[0]);
  1842. return 0;
  1843. }
  1844. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1845. struct snd_ctl_elem_value *ucontrol)
  1846. {
  1847. int idx = mi2s_get_port_idx(kcontrol);
  1848. if (idx < 0)
  1849. return idx;
  1850. mi2s_tx_cfg[idx].bit_format =
  1851. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1852. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1853. idx, mi2s_tx_cfg[idx].bit_format,
  1854. ucontrol->value.enumerated.item[0]);
  1855. return 0;
  1856. }
  1857. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1858. struct snd_ctl_elem_value *ucontrol)
  1859. {
  1860. int idx = mi2s_get_port_idx(kcontrol);
  1861. if (idx < 0)
  1862. return idx;
  1863. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1864. idx, mi2s_rx_cfg[idx].channels);
  1865. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1866. return 0;
  1867. }
  1868. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1869. struct snd_ctl_elem_value *ucontrol)
  1870. {
  1871. int idx = mi2s_get_port_idx(kcontrol);
  1872. if (idx < 0)
  1873. return idx;
  1874. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1875. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1876. idx, mi2s_rx_cfg[idx].channels);
  1877. return 1;
  1878. }
  1879. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1880. struct snd_ctl_elem_value *ucontrol)
  1881. {
  1882. int idx = mi2s_get_port_idx(kcontrol);
  1883. if (idx < 0)
  1884. return idx;
  1885. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1886. idx, mi2s_tx_cfg[idx].channels);
  1887. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1888. return 0;
  1889. }
  1890. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1891. struct snd_ctl_elem_value *ucontrol)
  1892. {
  1893. int idx = mi2s_get_port_idx(kcontrol);
  1894. if (idx < 0)
  1895. return idx;
  1896. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1897. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1898. idx, mi2s_tx_cfg[idx].channels);
  1899. return 1;
  1900. }
  1901. static int msm_get_port_id(int be_id)
  1902. {
  1903. int afe_port_id = 0;
  1904. switch (be_id) {
  1905. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  1906. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  1907. break;
  1908. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  1909. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  1910. break;
  1911. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  1912. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  1913. break;
  1914. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  1915. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  1916. break;
  1917. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  1918. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  1919. break;
  1920. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  1921. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  1922. break;
  1923. default:
  1924. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  1925. afe_port_id = -EINVAL;
  1926. }
  1927. return afe_port_id;
  1928. }
  1929. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  1930. {
  1931. u32 bit_per_sample = 0;
  1932. switch (bit_format) {
  1933. case SNDRV_PCM_FORMAT_S32_LE:
  1934. case SNDRV_PCM_FORMAT_S24_3LE:
  1935. case SNDRV_PCM_FORMAT_S24_LE:
  1936. bit_per_sample = 32;
  1937. break;
  1938. case SNDRV_PCM_FORMAT_S16_LE:
  1939. default:
  1940. bit_per_sample = 16;
  1941. break;
  1942. }
  1943. return bit_per_sample;
  1944. }
  1945. static void update_mi2s_clk_val(int dai_id, int stream)
  1946. {
  1947. u32 bit_per_sample = 0;
  1948. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1949. bit_per_sample =
  1950. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  1951. mi2s_clk[dai_id].clk_freq_in_hz =
  1952. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1953. } else {
  1954. bit_per_sample =
  1955. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  1956. mi2s_clk[dai_id].clk_freq_in_hz =
  1957. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1958. }
  1959. }
  1960. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  1961. {
  1962. int ret = 0;
  1963. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1964. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  1965. int port_id = 0;
  1966. int index = cpu_dai->id;
  1967. port_id = msm_get_port_id(rtd->dai_link->id);
  1968. if (port_id < 0) {
  1969. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  1970. ret = port_id;
  1971. goto err;
  1972. }
  1973. if (enable) {
  1974. update_mi2s_clk_val(index, substream->stream);
  1975. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  1976. mi2s_clk[index].clk_freq_in_hz);
  1977. }
  1978. mi2s_clk[index].enable = enable;
  1979. ret = afe_set_lpass_clock_v2(port_id,
  1980. &mi2s_clk[index]);
  1981. if (ret < 0) {
  1982. dev_err(rtd->card->dev,
  1983. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  1984. __func__, port_id, ret);
  1985. goto err;
  1986. }
  1987. err:
  1988. return ret;
  1989. }
  1990. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1991. {
  1992. int idx = 0;
  1993. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1994. sizeof("WSA_CDC_DMA_RX_0")))
  1995. idx = WSA_CDC_DMA_RX_0;
  1996. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1997. sizeof("WSA_CDC_DMA_RX_0")))
  1998. idx = WSA_CDC_DMA_RX_1;
  1999. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2000. sizeof("RX_CDC_DMA_RX_0")))
  2001. idx = RX_CDC_DMA_RX_0;
  2002. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2003. sizeof("RX_CDC_DMA_RX_1")))
  2004. idx = RX_CDC_DMA_RX_1;
  2005. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2006. sizeof("RX_CDC_DMA_RX_2")))
  2007. idx = RX_CDC_DMA_RX_2;
  2008. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2009. sizeof("RX_CDC_DMA_RX_3")))
  2010. idx = RX_CDC_DMA_RX_3;
  2011. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2012. sizeof("RX_CDC_DMA_RX_5")))
  2013. idx = RX_CDC_DMA_RX_5;
  2014. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2015. sizeof("WSA_CDC_DMA_TX_0")))
  2016. idx = WSA_CDC_DMA_TX_0;
  2017. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2018. sizeof("WSA_CDC_DMA_TX_1")))
  2019. idx = WSA_CDC_DMA_TX_1;
  2020. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2021. sizeof("WSA_CDC_DMA_TX_2")))
  2022. idx = WSA_CDC_DMA_TX_2;
  2023. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2024. sizeof("TX_CDC_DMA_TX_0")))
  2025. idx = TX_CDC_DMA_TX_0;
  2026. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2027. sizeof("TX_CDC_DMA_TX_3")))
  2028. idx = TX_CDC_DMA_TX_3;
  2029. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2030. sizeof("TX_CDC_DMA_TX_4")))
  2031. idx = TX_CDC_DMA_TX_4;
  2032. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2033. sizeof("VA_CDC_DMA_TX_0")))
  2034. idx = VA_CDC_DMA_TX_0;
  2035. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2036. sizeof("VA_CDC_DMA_TX_1")))
  2037. idx = VA_CDC_DMA_TX_1;
  2038. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2039. sizeof("VA_CDC_DMA_TX_2")))
  2040. idx = VA_CDC_DMA_TX_2;
  2041. else {
  2042. pr_err("%s: unsupported channel: %s\n",
  2043. __func__, kcontrol->id.name);
  2044. return -EINVAL;
  2045. }
  2046. return idx;
  2047. }
  2048. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2049. struct snd_ctl_elem_value *ucontrol)
  2050. {
  2051. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2052. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2053. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2054. return ch_num;
  2055. }
  2056. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2057. cdc_dma_rx_cfg[ch_num].channels - 1);
  2058. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2059. return 0;
  2060. }
  2061. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2062. struct snd_ctl_elem_value *ucontrol)
  2063. {
  2064. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2065. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2066. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2067. return ch_num;
  2068. }
  2069. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2070. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2071. cdc_dma_rx_cfg[ch_num].channels);
  2072. return 1;
  2073. }
  2074. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2075. struct snd_ctl_elem_value *ucontrol)
  2076. {
  2077. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2078. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2079. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2080. return ch_num;
  2081. }
  2082. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2083. case SNDRV_PCM_FORMAT_S32_LE:
  2084. ucontrol->value.integer.value[0] = 3;
  2085. break;
  2086. case SNDRV_PCM_FORMAT_S24_3LE:
  2087. ucontrol->value.integer.value[0] = 2;
  2088. break;
  2089. case SNDRV_PCM_FORMAT_S24_LE:
  2090. ucontrol->value.integer.value[0] = 1;
  2091. break;
  2092. case SNDRV_PCM_FORMAT_S16_LE:
  2093. default:
  2094. ucontrol->value.integer.value[0] = 0;
  2095. break;
  2096. }
  2097. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2098. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2099. ucontrol->value.integer.value[0]);
  2100. return 0;
  2101. }
  2102. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2103. struct snd_ctl_elem_value *ucontrol)
  2104. {
  2105. int rc = 0;
  2106. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2107. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2108. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2109. return ch_num;
  2110. }
  2111. switch (ucontrol->value.integer.value[0]) {
  2112. case 3:
  2113. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2114. break;
  2115. case 2:
  2116. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2117. break;
  2118. case 1:
  2119. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2120. break;
  2121. case 0:
  2122. default:
  2123. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2124. break;
  2125. }
  2126. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2127. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2128. ucontrol->value.integer.value[0]);
  2129. return rc;
  2130. }
  2131. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2132. {
  2133. int sample_rate_val = 0;
  2134. switch (sample_rate) {
  2135. case SAMPLING_RATE_8KHZ:
  2136. sample_rate_val = 0;
  2137. break;
  2138. case SAMPLING_RATE_11P025KHZ:
  2139. sample_rate_val = 1;
  2140. break;
  2141. case SAMPLING_RATE_16KHZ:
  2142. sample_rate_val = 2;
  2143. break;
  2144. case SAMPLING_RATE_22P05KHZ:
  2145. sample_rate_val = 3;
  2146. break;
  2147. case SAMPLING_RATE_32KHZ:
  2148. sample_rate_val = 4;
  2149. break;
  2150. case SAMPLING_RATE_44P1KHZ:
  2151. sample_rate_val = 5;
  2152. break;
  2153. case SAMPLING_RATE_48KHZ:
  2154. sample_rate_val = 6;
  2155. break;
  2156. case SAMPLING_RATE_88P2KHZ:
  2157. sample_rate_val = 7;
  2158. break;
  2159. case SAMPLING_RATE_96KHZ:
  2160. sample_rate_val = 8;
  2161. break;
  2162. case SAMPLING_RATE_176P4KHZ:
  2163. sample_rate_val = 9;
  2164. break;
  2165. case SAMPLING_RATE_192KHZ:
  2166. sample_rate_val = 10;
  2167. break;
  2168. case SAMPLING_RATE_352P8KHZ:
  2169. sample_rate_val = 11;
  2170. break;
  2171. case SAMPLING_RATE_384KHZ:
  2172. sample_rate_val = 12;
  2173. break;
  2174. default:
  2175. sample_rate_val = 6;
  2176. break;
  2177. }
  2178. return sample_rate_val;
  2179. }
  2180. static int cdc_dma_get_sample_rate(int value)
  2181. {
  2182. int sample_rate = 0;
  2183. switch (value) {
  2184. case 0:
  2185. sample_rate = SAMPLING_RATE_8KHZ;
  2186. break;
  2187. case 1:
  2188. sample_rate = SAMPLING_RATE_11P025KHZ;
  2189. break;
  2190. case 2:
  2191. sample_rate = SAMPLING_RATE_16KHZ;
  2192. break;
  2193. case 3:
  2194. sample_rate = SAMPLING_RATE_22P05KHZ;
  2195. break;
  2196. case 4:
  2197. sample_rate = SAMPLING_RATE_32KHZ;
  2198. break;
  2199. case 5:
  2200. sample_rate = SAMPLING_RATE_44P1KHZ;
  2201. break;
  2202. case 6:
  2203. sample_rate = SAMPLING_RATE_48KHZ;
  2204. break;
  2205. case 7:
  2206. sample_rate = SAMPLING_RATE_88P2KHZ;
  2207. break;
  2208. case 8:
  2209. sample_rate = SAMPLING_RATE_96KHZ;
  2210. break;
  2211. case 9:
  2212. sample_rate = SAMPLING_RATE_176P4KHZ;
  2213. break;
  2214. case 10:
  2215. sample_rate = SAMPLING_RATE_192KHZ;
  2216. break;
  2217. case 11:
  2218. sample_rate = SAMPLING_RATE_352P8KHZ;
  2219. break;
  2220. case 12:
  2221. sample_rate = SAMPLING_RATE_384KHZ;
  2222. break;
  2223. default:
  2224. sample_rate = SAMPLING_RATE_48KHZ;
  2225. break;
  2226. }
  2227. return sample_rate;
  2228. }
  2229. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2230. struct snd_ctl_elem_value *ucontrol)
  2231. {
  2232. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2233. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2234. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2235. return ch_num;
  2236. }
  2237. ucontrol->value.enumerated.item[0] =
  2238. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2239. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2240. cdc_dma_rx_cfg[ch_num].sample_rate);
  2241. return 0;
  2242. }
  2243. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2244. struct snd_ctl_elem_value *ucontrol)
  2245. {
  2246. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2247. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2248. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2249. return ch_num;
  2250. }
  2251. cdc_dma_rx_cfg[ch_num].sample_rate =
  2252. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2253. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2254. __func__, ucontrol->value.enumerated.item[0],
  2255. cdc_dma_rx_cfg[ch_num].sample_rate);
  2256. return 0;
  2257. }
  2258. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2259. struct snd_ctl_elem_value *ucontrol)
  2260. {
  2261. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2262. if (ch_num < 0) {
  2263. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2264. return ch_num;
  2265. }
  2266. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2267. cdc_dma_tx_cfg[ch_num].channels);
  2268. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2269. return 0;
  2270. }
  2271. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2272. struct snd_ctl_elem_value *ucontrol)
  2273. {
  2274. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2275. if (ch_num < 0) {
  2276. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2277. return ch_num;
  2278. }
  2279. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2280. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2281. cdc_dma_tx_cfg[ch_num].channels);
  2282. return 1;
  2283. }
  2284. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2285. struct snd_ctl_elem_value *ucontrol)
  2286. {
  2287. int sample_rate_val;
  2288. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2289. if (ch_num < 0) {
  2290. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2291. return ch_num;
  2292. }
  2293. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2294. case SAMPLING_RATE_384KHZ:
  2295. sample_rate_val = 12;
  2296. break;
  2297. case SAMPLING_RATE_352P8KHZ:
  2298. sample_rate_val = 11;
  2299. break;
  2300. case SAMPLING_RATE_192KHZ:
  2301. sample_rate_val = 10;
  2302. break;
  2303. case SAMPLING_RATE_176P4KHZ:
  2304. sample_rate_val = 9;
  2305. break;
  2306. case SAMPLING_RATE_96KHZ:
  2307. sample_rate_val = 8;
  2308. break;
  2309. case SAMPLING_RATE_88P2KHZ:
  2310. sample_rate_val = 7;
  2311. break;
  2312. case SAMPLING_RATE_48KHZ:
  2313. sample_rate_val = 6;
  2314. break;
  2315. case SAMPLING_RATE_44P1KHZ:
  2316. sample_rate_val = 5;
  2317. break;
  2318. case SAMPLING_RATE_32KHZ:
  2319. sample_rate_val = 4;
  2320. break;
  2321. case SAMPLING_RATE_22P05KHZ:
  2322. sample_rate_val = 3;
  2323. break;
  2324. case SAMPLING_RATE_16KHZ:
  2325. sample_rate_val = 2;
  2326. break;
  2327. case SAMPLING_RATE_11P025KHZ:
  2328. sample_rate_val = 1;
  2329. break;
  2330. case SAMPLING_RATE_8KHZ:
  2331. sample_rate_val = 0;
  2332. break;
  2333. default:
  2334. sample_rate_val = 6;
  2335. break;
  2336. }
  2337. ucontrol->value.integer.value[0] = sample_rate_val;
  2338. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2339. cdc_dma_tx_cfg[ch_num].sample_rate);
  2340. return 0;
  2341. }
  2342. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2343. struct snd_ctl_elem_value *ucontrol)
  2344. {
  2345. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2346. if (ch_num < 0) {
  2347. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2348. return ch_num;
  2349. }
  2350. switch (ucontrol->value.integer.value[0]) {
  2351. case 12:
  2352. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2353. break;
  2354. case 11:
  2355. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2356. break;
  2357. case 10:
  2358. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2359. break;
  2360. case 9:
  2361. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2362. break;
  2363. case 8:
  2364. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2365. break;
  2366. case 7:
  2367. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2368. break;
  2369. case 6:
  2370. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2371. break;
  2372. case 5:
  2373. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2374. break;
  2375. case 4:
  2376. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2377. break;
  2378. case 3:
  2379. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2380. break;
  2381. case 2:
  2382. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2383. break;
  2384. case 1:
  2385. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2386. break;
  2387. case 0:
  2388. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2389. break;
  2390. default:
  2391. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2392. break;
  2393. }
  2394. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2395. __func__, ucontrol->value.integer.value[0],
  2396. cdc_dma_tx_cfg[ch_num].sample_rate);
  2397. return 0;
  2398. }
  2399. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2400. struct snd_ctl_elem_value *ucontrol)
  2401. {
  2402. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2403. if (ch_num < 0) {
  2404. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2405. return ch_num;
  2406. }
  2407. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2408. case SNDRV_PCM_FORMAT_S32_LE:
  2409. ucontrol->value.integer.value[0] = 3;
  2410. break;
  2411. case SNDRV_PCM_FORMAT_S24_3LE:
  2412. ucontrol->value.integer.value[0] = 2;
  2413. break;
  2414. case SNDRV_PCM_FORMAT_S24_LE:
  2415. ucontrol->value.integer.value[0] = 1;
  2416. break;
  2417. case SNDRV_PCM_FORMAT_S16_LE:
  2418. default:
  2419. ucontrol->value.integer.value[0] = 0;
  2420. break;
  2421. }
  2422. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2423. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2424. ucontrol->value.integer.value[0]);
  2425. return 0;
  2426. }
  2427. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2428. struct snd_ctl_elem_value *ucontrol)
  2429. {
  2430. int rc = 0;
  2431. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2432. if (ch_num < 0) {
  2433. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2434. return ch_num;
  2435. }
  2436. switch (ucontrol->value.integer.value[0]) {
  2437. case 3:
  2438. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2439. break;
  2440. case 2:
  2441. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2442. break;
  2443. case 1:
  2444. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2445. break;
  2446. case 0:
  2447. default:
  2448. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2449. break;
  2450. }
  2451. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2452. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2453. ucontrol->value.integer.value[0]);
  2454. return rc;
  2455. }
  2456. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2457. {
  2458. int idx = 0;
  2459. switch (be_id) {
  2460. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2461. idx = WSA_CDC_DMA_RX_0;
  2462. break;
  2463. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2464. idx = WSA_CDC_DMA_TX_0;
  2465. break;
  2466. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2467. idx = WSA_CDC_DMA_RX_1;
  2468. break;
  2469. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2470. idx = WSA_CDC_DMA_TX_1;
  2471. break;
  2472. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2473. idx = WSA_CDC_DMA_TX_2;
  2474. break;
  2475. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2476. idx = RX_CDC_DMA_RX_0;
  2477. break;
  2478. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2479. idx = RX_CDC_DMA_RX_1;
  2480. break;
  2481. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2482. idx = RX_CDC_DMA_RX_2;
  2483. break;
  2484. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2485. idx = RX_CDC_DMA_RX_3;
  2486. break;
  2487. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2488. idx = RX_CDC_DMA_RX_5;
  2489. break;
  2490. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2491. idx = TX_CDC_DMA_TX_0;
  2492. break;
  2493. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2494. idx = TX_CDC_DMA_TX_3;
  2495. break;
  2496. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2497. idx = TX_CDC_DMA_TX_4;
  2498. break;
  2499. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2500. idx = VA_CDC_DMA_TX_0;
  2501. break;
  2502. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2503. idx = VA_CDC_DMA_TX_1;
  2504. break;
  2505. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2506. idx = VA_CDC_DMA_TX_2;
  2507. break;
  2508. default:
  2509. idx = RX_CDC_DMA_RX_0;
  2510. break;
  2511. }
  2512. return idx;
  2513. }
  2514. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2515. struct snd_ctl_elem_value *ucontrol)
  2516. {
  2517. /*
  2518. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2519. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2520. * value.
  2521. */
  2522. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2523. case SAMPLING_RATE_96KHZ:
  2524. ucontrol->value.integer.value[0] = 5;
  2525. break;
  2526. case SAMPLING_RATE_88P2KHZ:
  2527. ucontrol->value.integer.value[0] = 4;
  2528. break;
  2529. case SAMPLING_RATE_48KHZ:
  2530. ucontrol->value.integer.value[0] = 3;
  2531. break;
  2532. case SAMPLING_RATE_44P1KHZ:
  2533. ucontrol->value.integer.value[0] = 2;
  2534. break;
  2535. case SAMPLING_RATE_16KHZ:
  2536. ucontrol->value.integer.value[0] = 1;
  2537. break;
  2538. case SAMPLING_RATE_8KHZ:
  2539. default:
  2540. ucontrol->value.integer.value[0] = 0;
  2541. break;
  2542. }
  2543. pr_debug("%s: sample rate = %d\n", __func__,
  2544. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2545. return 0;
  2546. }
  2547. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2548. struct snd_ctl_elem_value *ucontrol)
  2549. {
  2550. switch (ucontrol->value.integer.value[0]) {
  2551. case 1:
  2552. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2553. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2554. break;
  2555. case 2:
  2556. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2557. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2558. break;
  2559. case 3:
  2560. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2561. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2562. break;
  2563. case 4:
  2564. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2565. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2566. break;
  2567. case 5:
  2568. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2569. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2570. break;
  2571. case 0:
  2572. default:
  2573. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2574. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2575. break;
  2576. }
  2577. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2578. __func__,
  2579. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2580. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2581. ucontrol->value.enumerated.item[0]);
  2582. return 0;
  2583. }
  2584. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2585. struct snd_ctl_elem_value *ucontrol)
  2586. {
  2587. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2588. case SAMPLING_RATE_96KHZ:
  2589. ucontrol->value.integer.value[0] = 5;
  2590. break;
  2591. case SAMPLING_RATE_88P2KHZ:
  2592. ucontrol->value.integer.value[0] = 4;
  2593. break;
  2594. case SAMPLING_RATE_48KHZ:
  2595. ucontrol->value.integer.value[0] = 3;
  2596. break;
  2597. case SAMPLING_RATE_44P1KHZ:
  2598. ucontrol->value.integer.value[0] = 2;
  2599. break;
  2600. case SAMPLING_RATE_16KHZ:
  2601. ucontrol->value.integer.value[0] = 1;
  2602. break;
  2603. case SAMPLING_RATE_8KHZ:
  2604. default:
  2605. ucontrol->value.integer.value[0] = 0;
  2606. break;
  2607. }
  2608. pr_debug("%s: sample rate rx = %d\n", __func__,
  2609. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2610. return 0;
  2611. }
  2612. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2613. struct snd_ctl_elem_value *ucontrol)
  2614. {
  2615. switch (ucontrol->value.integer.value[0]) {
  2616. case 1:
  2617. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2618. break;
  2619. case 2:
  2620. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2621. break;
  2622. case 3:
  2623. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2624. break;
  2625. case 4:
  2626. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2627. break;
  2628. case 5:
  2629. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2630. break;
  2631. case 0:
  2632. default:
  2633. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2634. break;
  2635. }
  2636. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2637. __func__,
  2638. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2639. ucontrol->value.enumerated.item[0]);
  2640. return 0;
  2641. }
  2642. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2643. struct snd_ctl_elem_value *ucontrol)
  2644. {
  2645. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2646. case SAMPLING_RATE_96KHZ:
  2647. ucontrol->value.integer.value[0] = 5;
  2648. break;
  2649. case SAMPLING_RATE_88P2KHZ:
  2650. ucontrol->value.integer.value[0] = 4;
  2651. break;
  2652. case SAMPLING_RATE_48KHZ:
  2653. ucontrol->value.integer.value[0] = 3;
  2654. break;
  2655. case SAMPLING_RATE_44P1KHZ:
  2656. ucontrol->value.integer.value[0] = 2;
  2657. break;
  2658. case SAMPLING_RATE_16KHZ:
  2659. ucontrol->value.integer.value[0] = 1;
  2660. break;
  2661. case SAMPLING_RATE_8KHZ:
  2662. default:
  2663. ucontrol->value.integer.value[0] = 0;
  2664. break;
  2665. }
  2666. pr_debug("%s: sample rate tx = %d\n", __func__,
  2667. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2668. return 0;
  2669. }
  2670. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2671. struct snd_ctl_elem_value *ucontrol)
  2672. {
  2673. switch (ucontrol->value.integer.value[0]) {
  2674. case 1:
  2675. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2676. break;
  2677. case 2:
  2678. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2679. break;
  2680. case 3:
  2681. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2682. break;
  2683. case 4:
  2684. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2685. break;
  2686. case 5:
  2687. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2688. break;
  2689. case 0:
  2690. default:
  2691. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2692. break;
  2693. }
  2694. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2695. __func__,
  2696. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2697. ucontrol->value.enumerated.item[0]);
  2698. return 0;
  2699. }
  2700. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2701. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2702. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2703. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2704. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2705. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2706. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2707. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2708. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2709. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2710. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2711. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2712. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2713. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2714. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2715. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2716. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2717. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2718. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2719. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2720. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2721. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2722. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2723. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2724. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2725. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2726. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2727. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2728. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2729. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2730. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2731. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2732. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2733. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2734. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2735. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2736. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2737. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2738. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2739. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2740. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2741. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2742. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2743. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2744. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2745. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2746. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2747. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2748. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2749. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2750. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2751. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2752. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2753. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2754. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2755. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2756. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2757. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2758. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2759. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2760. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2761. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2762. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2763. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2764. wsa_cdc_dma_rx_0_sample_rate,
  2765. cdc_dma_rx_sample_rate_get,
  2766. cdc_dma_rx_sample_rate_put),
  2767. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2768. wsa_cdc_dma_rx_1_sample_rate,
  2769. cdc_dma_rx_sample_rate_get,
  2770. cdc_dma_rx_sample_rate_put),
  2771. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2772. rx_cdc_dma_rx_0_sample_rate,
  2773. cdc_dma_rx_sample_rate_get,
  2774. cdc_dma_rx_sample_rate_put),
  2775. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2776. rx_cdc_dma_rx_1_sample_rate,
  2777. cdc_dma_rx_sample_rate_get,
  2778. cdc_dma_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2780. rx_cdc_dma_rx_2_sample_rate,
  2781. cdc_dma_rx_sample_rate_get,
  2782. cdc_dma_rx_sample_rate_put),
  2783. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2784. rx_cdc_dma_rx_3_sample_rate,
  2785. cdc_dma_rx_sample_rate_get,
  2786. cdc_dma_rx_sample_rate_put),
  2787. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2788. rx_cdc_dma_rx_5_sample_rate,
  2789. cdc_dma_rx_sample_rate_get,
  2790. cdc_dma_rx_sample_rate_put),
  2791. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2792. wsa_cdc_dma_tx_0_sample_rate,
  2793. cdc_dma_tx_sample_rate_get,
  2794. cdc_dma_tx_sample_rate_put),
  2795. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2796. wsa_cdc_dma_tx_1_sample_rate,
  2797. cdc_dma_tx_sample_rate_get,
  2798. cdc_dma_tx_sample_rate_put),
  2799. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2800. wsa_cdc_dma_tx_2_sample_rate,
  2801. cdc_dma_tx_sample_rate_get,
  2802. cdc_dma_tx_sample_rate_put),
  2803. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2804. tx_cdc_dma_tx_0_sample_rate,
  2805. cdc_dma_tx_sample_rate_get,
  2806. cdc_dma_tx_sample_rate_put),
  2807. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2808. tx_cdc_dma_tx_3_sample_rate,
  2809. cdc_dma_tx_sample_rate_get,
  2810. cdc_dma_tx_sample_rate_put),
  2811. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2812. tx_cdc_dma_tx_4_sample_rate,
  2813. cdc_dma_tx_sample_rate_get,
  2814. cdc_dma_tx_sample_rate_put),
  2815. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2816. va_cdc_dma_tx_0_sample_rate,
  2817. cdc_dma_tx_sample_rate_get,
  2818. cdc_dma_tx_sample_rate_put),
  2819. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2820. va_cdc_dma_tx_1_sample_rate,
  2821. cdc_dma_tx_sample_rate_get,
  2822. cdc_dma_tx_sample_rate_put),
  2823. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2824. va_cdc_dma_tx_2_sample_rate,
  2825. cdc_dma_tx_sample_rate_get,
  2826. cdc_dma_tx_sample_rate_put),
  2827. };
  2828. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  2829. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2830. usb_audio_rx_sample_rate_get,
  2831. usb_audio_rx_sample_rate_put),
  2832. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2833. usb_audio_tx_sample_rate_get,
  2834. usb_audio_tx_sample_rate_put),
  2835. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2836. tdm_rx_sample_rate_get,
  2837. tdm_rx_sample_rate_put),
  2838. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2839. tdm_rx_sample_rate_get,
  2840. tdm_rx_sample_rate_put),
  2841. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2842. tdm_rx_sample_rate_get,
  2843. tdm_rx_sample_rate_put),
  2844. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2845. tdm_tx_sample_rate_get,
  2846. tdm_tx_sample_rate_put),
  2847. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2848. tdm_tx_sample_rate_get,
  2849. tdm_tx_sample_rate_put),
  2850. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2851. tdm_tx_sample_rate_get,
  2852. tdm_tx_sample_rate_put),
  2853. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2854. aux_pcm_rx_sample_rate_get,
  2855. aux_pcm_rx_sample_rate_put),
  2856. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2857. aux_pcm_rx_sample_rate_get,
  2858. aux_pcm_rx_sample_rate_put),
  2859. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2860. aux_pcm_rx_sample_rate_get,
  2861. aux_pcm_rx_sample_rate_put),
  2862. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2863. aux_pcm_tx_sample_rate_get,
  2864. aux_pcm_tx_sample_rate_put),
  2865. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2866. aux_pcm_tx_sample_rate_get,
  2867. aux_pcm_tx_sample_rate_put),
  2868. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2869. aux_pcm_tx_sample_rate_get,
  2870. aux_pcm_tx_sample_rate_put),
  2871. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2872. mi2s_rx_sample_rate_get,
  2873. mi2s_rx_sample_rate_put),
  2874. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2875. mi2s_rx_sample_rate_get,
  2876. mi2s_rx_sample_rate_put),
  2877. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2878. mi2s_rx_sample_rate_get,
  2879. mi2s_rx_sample_rate_put),
  2880. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2881. mi2s_tx_sample_rate_get,
  2882. mi2s_tx_sample_rate_put),
  2883. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2884. mi2s_tx_sample_rate_get,
  2885. mi2s_tx_sample_rate_put),
  2886. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2887. mi2s_tx_sample_rate_get,
  2888. mi2s_tx_sample_rate_put),
  2889. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2890. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2891. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2892. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2893. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2894. tdm_rx_format_get,
  2895. tdm_rx_format_put),
  2896. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2897. tdm_rx_format_get,
  2898. tdm_rx_format_put),
  2899. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2900. tdm_rx_format_get,
  2901. tdm_rx_format_put),
  2902. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2903. tdm_tx_format_get,
  2904. tdm_tx_format_put),
  2905. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2906. tdm_tx_format_get,
  2907. tdm_tx_format_put),
  2908. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2909. tdm_tx_format_get,
  2910. tdm_tx_format_put),
  2911. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2912. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2913. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2914. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2915. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2916. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2917. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2918. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2919. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2920. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2921. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2922. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2923. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2924. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2925. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2926. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2927. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2928. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2929. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2930. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2931. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2932. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2933. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2934. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2935. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2936. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2937. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2938. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2939. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2940. proxy_rx_ch_get, proxy_rx_ch_put),
  2941. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2942. tdm_rx_ch_get,
  2943. tdm_rx_ch_put),
  2944. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2945. tdm_rx_ch_get,
  2946. tdm_rx_ch_put),
  2947. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2948. tdm_rx_ch_get,
  2949. tdm_rx_ch_put),
  2950. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2951. tdm_tx_ch_get,
  2952. tdm_tx_ch_put),
  2953. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2954. tdm_tx_ch_get,
  2955. tdm_tx_ch_put),
  2956. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2957. tdm_tx_ch_get,
  2958. tdm_tx_ch_put),
  2959. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2960. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2961. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2962. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2963. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2964. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2965. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2966. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2967. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2968. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2969. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2970. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2971. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  2972. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  2973. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  2974. ext_disp_rx_format_get, ext_disp_rx_format_put),
  2975. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  2976. ext_disp_rx_sample_rate_get,
  2977. ext_disp_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2979. msm_bt_sample_rate_get,
  2980. msm_bt_sample_rate_put),
  2981. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  2982. msm_bt_sample_rate_rx_get,
  2983. msm_bt_sample_rate_rx_put),
  2984. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  2985. msm_bt_sample_rate_tx_get,
  2986. msm_bt_sample_rate_tx_put),
  2987. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  2988. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  2989. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2990. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2991. };
  2992. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2993. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2994. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2995. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2996. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2997. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2998. aux_pcm_rx_sample_rate_get,
  2999. aux_pcm_rx_sample_rate_put),
  3000. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3001. aux_pcm_tx_sample_rate_get,
  3002. aux_pcm_tx_sample_rate_put),
  3003. };
  3004. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3005. {
  3006. int idx;
  3007. switch (be_id) {
  3008. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3009. idx = EXT_DISP_RX_IDX_DP;
  3010. break;
  3011. default:
  3012. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3013. idx = -EINVAL;
  3014. break;
  3015. }
  3016. return idx;
  3017. }
  3018. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3019. struct snd_pcm_hw_params *params)
  3020. {
  3021. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3022. struct snd_interval *rate = hw_param_interval(params,
  3023. SNDRV_PCM_HW_PARAM_RATE);
  3024. struct snd_interval *channels = hw_param_interval(params,
  3025. SNDRV_PCM_HW_PARAM_CHANNELS);
  3026. int idx = 0, rc = 0;
  3027. pr_debug("%s: format = %d, rate = %d\n",
  3028. __func__, params_format(params), params_rate(params));
  3029. switch (dai_link->id) {
  3030. case MSM_BACKEND_DAI_USB_RX:
  3031. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3032. usb_rx_cfg.bit_format);
  3033. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3034. channels->min = channels->max = usb_rx_cfg.channels;
  3035. break;
  3036. case MSM_BACKEND_DAI_USB_TX:
  3037. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3038. usb_tx_cfg.bit_format);
  3039. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3040. channels->min = channels->max = usb_tx_cfg.channels;
  3041. break;
  3042. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3043. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3044. if (idx < 0) {
  3045. pr_err("%s: Incorrect ext disp idx %d\n",
  3046. __func__, idx);
  3047. rc = idx;
  3048. goto done;
  3049. }
  3050. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3051. ext_disp_rx_cfg[idx].bit_format);
  3052. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3053. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3054. break;
  3055. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3056. channels->min = channels->max = proxy_rx_cfg.channels;
  3057. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3058. break;
  3059. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3060. channels->min = channels->max =
  3061. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3062. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3063. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3064. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3065. break;
  3066. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3067. channels->min = channels->max =
  3068. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3069. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3070. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3071. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3072. break;
  3073. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3074. channels->min = channels->max =
  3075. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3076. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3077. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3078. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3079. break;
  3080. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3081. channels->min = channels->max =
  3082. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3083. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3084. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3085. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3086. break;
  3087. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3088. channels->min = channels->max =
  3089. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3090. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3091. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3092. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3093. break;
  3094. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3095. channels->min = channels->max =
  3096. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3097. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3098. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3099. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3100. break;
  3101. case MSM_BACKEND_DAI_AUXPCM_RX:
  3102. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3103. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3104. rate->min = rate->max =
  3105. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3106. channels->min = channels->max =
  3107. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3108. break;
  3109. case MSM_BACKEND_DAI_AUXPCM_TX:
  3110. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3111. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3112. rate->min = rate->max =
  3113. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3114. channels->min = channels->max =
  3115. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3116. break;
  3117. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3118. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3119. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3120. rate->min = rate->max =
  3121. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3122. channels->min = channels->max =
  3123. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3124. break;
  3125. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3126. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3127. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3128. rate->min = rate->max =
  3129. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3130. channels->min = channels->max =
  3131. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3132. break;
  3133. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3134. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3135. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3136. rate->min = rate->max =
  3137. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3138. channels->min = channels->max =
  3139. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3140. break;
  3141. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3142. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3143. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3144. rate->min = rate->max =
  3145. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3146. channels->min = channels->max =
  3147. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3148. break;
  3149. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3150. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3151. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3152. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3153. channels->min = channels->max =
  3154. mi2s_rx_cfg[PRIM_MI2S].channels;
  3155. break;
  3156. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3157. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3158. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3159. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3160. channels->min = channels->max =
  3161. mi2s_tx_cfg[PRIM_MI2S].channels;
  3162. break;
  3163. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3164. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3165. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3166. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3167. channels->min = channels->max =
  3168. mi2s_rx_cfg[SEC_MI2S].channels;
  3169. break;
  3170. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3171. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3172. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3173. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3174. channels->min = channels->max =
  3175. mi2s_tx_cfg[SEC_MI2S].channels;
  3176. break;
  3177. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3178. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3179. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3180. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3181. channels->min = channels->max =
  3182. mi2s_rx_cfg[TERT_MI2S].channels;
  3183. break;
  3184. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3185. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3186. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3187. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3188. channels->min = channels->max =
  3189. mi2s_tx_cfg[TERT_MI2S].channels;
  3190. break;
  3191. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3192. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3193. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3194. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3195. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3196. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3197. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3198. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3199. cdc_dma_rx_cfg[idx].bit_format);
  3200. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3201. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3202. break;
  3203. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3204. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3205. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3206. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3207. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3208. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3209. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3210. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3211. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3212. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3213. cdc_dma_tx_cfg[idx].bit_format);
  3214. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3215. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3216. break;
  3217. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3218. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3219. SNDRV_PCM_FORMAT_S32_LE);
  3220. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3221. channels->min = channels->max = msm_vi_feed_tx_ch;
  3222. break;
  3223. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3224. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3225. slim_rx_cfg[SLIM_RX_7].bit_format);
  3226. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3227. channels->min = channels->max =
  3228. slim_rx_cfg[SLIM_RX_7].channels;
  3229. break;
  3230. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3231. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3232. channels->min = channels->max =
  3233. slim_tx_cfg[SLIM_TX_7].channels;
  3234. break;
  3235. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3236. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3237. afe_loopback_tx_cfg[idx].bit_format);
  3238. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3239. channels->min = channels->max =
  3240. afe_loopback_tx_cfg[idx].channels;
  3241. break;
  3242. default:
  3243. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3244. break;
  3245. }
  3246. done:
  3247. return rc;
  3248. }
  3249. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3250. {
  3251. struct snd_soc_card *card = component->card;
  3252. struct msm_asoc_mach_data *pdata =
  3253. snd_soc_card_get_drvdata(card);
  3254. if (!pdata->fsa_handle)
  3255. return false;
  3256. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3257. }
  3258. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3259. {
  3260. int value = 0;
  3261. bool ret = false;
  3262. struct snd_soc_card *card;
  3263. struct msm_asoc_mach_data *pdata;
  3264. if (!component) {
  3265. pr_err("%s component is NULL\n", __func__);
  3266. return false;
  3267. }
  3268. card = component->card;
  3269. pdata = snd_soc_card_get_drvdata(card);
  3270. if (!pdata)
  3271. return false;
  3272. if (wcd_mbhc_cfg.enable_usbc_analog)
  3273. return msm_usbc_swap_gnd_mic(component, active);
  3274. /* if usbc is not defined, swap using us_euro_gpio_p */
  3275. if (pdata->us_euro_gpio_p) {
  3276. value = msm_cdc_pinctrl_get_state(
  3277. pdata->us_euro_gpio_p);
  3278. if (value)
  3279. msm_cdc_pinctrl_select_sleep_state(
  3280. pdata->us_euro_gpio_p);
  3281. else
  3282. msm_cdc_pinctrl_select_active_state(
  3283. pdata->us_euro_gpio_p);
  3284. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3285. __func__, value, !value);
  3286. ret = true;
  3287. }
  3288. return ret;
  3289. }
  3290. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3291. struct snd_pcm_hw_params *params)
  3292. {
  3293. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3294. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3295. int ret = 0;
  3296. int slot_width = 32;
  3297. int channels, slots;
  3298. unsigned int slot_mask, rate, clk_freq;
  3299. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3300. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3301. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3302. switch (cpu_dai->id) {
  3303. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3304. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3305. break;
  3306. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3307. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3308. break;
  3309. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3310. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3311. break;
  3312. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3313. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3314. break;
  3315. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3316. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3317. break;
  3318. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3319. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3320. break;
  3321. default:
  3322. pr_err("%s: dai id 0x%x not supported\n",
  3323. __func__, cpu_dai->id);
  3324. return -EINVAL;
  3325. }
  3326. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3327. /*2 slot config - bits 0 and 1 set for the first two slots */
  3328. slot_mask = 0x0000FFFF >> (16 - slots);
  3329. channels = slots;
  3330. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3331. __func__, slot_width, slots);
  3332. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3333. slots, slot_width);
  3334. if (ret < 0) {
  3335. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3336. __func__, ret);
  3337. goto end;
  3338. }
  3339. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3340. 0, NULL, channels, slot_offset);
  3341. if (ret < 0) {
  3342. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3343. __func__, ret);
  3344. goto end;
  3345. }
  3346. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3347. /*2 slot config - bits 0 and 1 set for the first two slots */
  3348. slot_mask = 0x0000FFFF >> (16 - slots);
  3349. channels = slots;
  3350. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3351. __func__, slot_width, slots);
  3352. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3353. slots, slot_width);
  3354. if (ret < 0) {
  3355. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3356. __func__, ret);
  3357. goto end;
  3358. }
  3359. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3360. channels, slot_offset, 0, NULL);
  3361. if (ret < 0) {
  3362. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3363. __func__, ret);
  3364. goto end;
  3365. }
  3366. } else {
  3367. ret = -EINVAL;
  3368. pr_err("%s: invalid use case, err:%d\n",
  3369. __func__, ret);
  3370. goto end;
  3371. }
  3372. rate = params_rate(params);
  3373. clk_freq = rate * slot_width * slots;
  3374. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3375. if (ret < 0)
  3376. pr_err("%s: failed to set tdm clk, err:%d\n",
  3377. __func__, ret);
  3378. end:
  3379. return ret;
  3380. }
  3381. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3382. struct snd_pcm_hw_params *params)
  3383. {
  3384. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3385. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3386. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3387. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3388. int ret = 0;
  3389. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3390. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3391. u32 user_set_tx_ch = 0;
  3392. u32 user_set_rx_ch = 0;
  3393. u32 ch_id;
  3394. ret = snd_soc_dai_get_channel_map(codec_dai,
  3395. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3396. &rx_ch_cdc_dma);
  3397. if (ret < 0) {
  3398. pr_err("%s: failed to get codec chan map, err:%d\n",
  3399. __func__, ret);
  3400. goto err;
  3401. }
  3402. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3403. switch (dai_link->id) {
  3404. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3405. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3406. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3407. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3408. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3409. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3410. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3411. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3412. {
  3413. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3414. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3415. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3416. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3417. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3418. user_set_rx_ch, &rx_ch_cdc_dma);
  3419. if (ret < 0) {
  3420. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3421. __func__, ret);
  3422. goto err;
  3423. }
  3424. }
  3425. break;
  3426. }
  3427. } else {
  3428. switch (dai_link->id) {
  3429. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3430. {
  3431. user_set_tx_ch = msm_vi_feed_tx_ch;
  3432. }
  3433. break;
  3434. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3435. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3436. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3437. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3438. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3439. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3440. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3441. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3442. {
  3443. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3444. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3445. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3446. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3447. }
  3448. break;
  3449. }
  3450. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3451. &tx_ch_cdc_dma, 0, 0);
  3452. if (ret < 0) {
  3453. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3454. __func__, ret);
  3455. goto err;
  3456. }
  3457. }
  3458. err:
  3459. return ret;
  3460. }
  3461. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3462. {
  3463. cpumask_t mask;
  3464. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  3465. pm_qos_remove_request(&substream->latency_pm_qos_req);
  3466. cpumask_clear(&mask);
  3467. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  3468. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  3469. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  3470. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  3471. pm_qos_add_request(&substream->latency_pm_qos_req,
  3472. PM_QOS_CPU_DMA_LATENCY,
  3473. MSM_LL_QOS_VALUE);
  3474. return 0;
  3475. }
  3476. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3477. {
  3478. int ret = 0;
  3479. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3480. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3481. int index = cpu_dai->id;
  3482. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3483. dev_dbg(rtd->card->dev,
  3484. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3485. __func__, substream->name, substream->stream,
  3486. cpu_dai->name, cpu_dai->id);
  3487. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3488. ret = -EINVAL;
  3489. dev_err(rtd->card->dev,
  3490. "%s: CPU DAI id (%d) out of range\n",
  3491. __func__, cpu_dai->id);
  3492. goto err;
  3493. }
  3494. /*
  3495. * Mutex protection in case the same MI2S
  3496. * interface using for both TX and RX so
  3497. * that the same clock won't be enable twice.
  3498. */
  3499. mutex_lock(&mi2s_intf_conf[index].lock);
  3500. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3501. /* Check if msm needs to provide the clock to the interface */
  3502. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3503. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3504. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3505. }
  3506. ret = msm_mi2s_set_sclk(substream, true);
  3507. if (ret < 0) {
  3508. dev_err(rtd->card->dev,
  3509. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3510. __func__, ret);
  3511. goto clean_up;
  3512. }
  3513. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3514. if (ret < 0) {
  3515. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  3516. __func__, index, ret);
  3517. goto clk_off;
  3518. }
  3519. }
  3520. clk_off:
  3521. if (ret < 0)
  3522. msm_mi2s_set_sclk(substream, false);
  3523. clean_up:
  3524. if (ret < 0)
  3525. mi2s_intf_conf[index].ref_cnt--;
  3526. mutex_unlock(&mi2s_intf_conf[index].lock);
  3527. err:
  3528. return ret;
  3529. }
  3530. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  3531. {
  3532. int ret = 0;
  3533. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3534. int index = rtd->cpu_dai->id;
  3535. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  3536. substream->name, substream->stream);
  3537. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3538. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  3539. return;
  3540. }
  3541. mutex_lock(&mi2s_intf_conf[index].lock);
  3542. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  3543. ret = msm_mi2s_set_sclk(substream, false);
  3544. if (ret < 0)
  3545. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  3546. __func__, index, ret);
  3547. }
  3548. mutex_unlock(&mi2s_intf_conf[index].lock);
  3549. }
  3550. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3551. struct snd_pcm_hw_params *params)
  3552. {
  3553. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3554. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3555. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3556. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3557. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3558. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3559. int ret = 0;
  3560. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3561. codec_dai->name, codec_dai->id);
  3562. ret = snd_soc_dai_get_channel_map(codec_dai,
  3563. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3564. if (ret) {
  3565. dev_err(rtd->dev,
  3566. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3567. __func__, ret);
  3568. goto err;
  3569. }
  3570. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3571. __func__, tx_ch_cnt, dai_link->id);
  3572. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3573. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3574. if (ret)
  3575. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3576. __func__, ret);
  3577. err:
  3578. return ret;
  3579. }
  3580. static struct snd_soc_ops kona_tdm_be_ops = {
  3581. .hw_params = kona_tdm_snd_hw_params,
  3582. };
  3583. static struct snd_soc_ops msm_mi2s_be_ops = {
  3584. .startup = msm_mi2s_snd_startup,
  3585. .shutdown = msm_mi2s_snd_shutdown,
  3586. };
  3587. static struct snd_soc_ops msm_fe_qos_ops = {
  3588. .prepare = msm_fe_qos_prepare,
  3589. };
  3590. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  3591. .hw_params = msm_snd_cdc_dma_hw_params,
  3592. };
  3593. static struct snd_soc_ops msm_wcn_ops = {
  3594. .hw_params = msm_wcn_hw_params,
  3595. };
  3596. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3597. struct snd_kcontrol *kcontrol, int event)
  3598. {
  3599. struct msm_asoc_mach_data *pdata = NULL;
  3600. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  3601. int ret = 0;
  3602. u32 dmic_idx;
  3603. int *dmic_gpio_cnt;
  3604. struct device_node *dmic_gpio;
  3605. char *wname;
  3606. wname = strpbrk(w->name, "012345");
  3607. if (!wname) {
  3608. dev_err(component->dev, "%s: widget not found\n", __func__);
  3609. return -EINVAL;
  3610. }
  3611. ret = kstrtouint(wname, 10, &dmic_idx);
  3612. if (ret < 0) {
  3613. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3614. __func__);
  3615. return -EINVAL;
  3616. }
  3617. pdata = snd_soc_card_get_drvdata(component->card);
  3618. switch (dmic_idx) {
  3619. case 0:
  3620. case 1:
  3621. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  3622. dmic_gpio = pdata->dmic01_gpio_p;
  3623. break;
  3624. case 2:
  3625. case 3:
  3626. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  3627. dmic_gpio = pdata->dmic23_gpio_p;
  3628. break;
  3629. case 4:
  3630. case 5:
  3631. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  3632. dmic_gpio = pdata->dmic45_gpio_p;
  3633. break;
  3634. default:
  3635. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3636. __func__);
  3637. return -EINVAL;
  3638. }
  3639. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3640. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3641. switch (event) {
  3642. case SND_SOC_DAPM_PRE_PMU:
  3643. (*dmic_gpio_cnt)++;
  3644. if (*dmic_gpio_cnt == 1) {
  3645. ret = msm_cdc_pinctrl_select_active_state(
  3646. dmic_gpio);
  3647. if (ret < 0) {
  3648. pr_err("%s: gpio set cannot be activated %sd",
  3649. __func__, "dmic_gpio");
  3650. return ret;
  3651. }
  3652. }
  3653. break;
  3654. case SND_SOC_DAPM_POST_PMD:
  3655. (*dmic_gpio_cnt)--;
  3656. if (*dmic_gpio_cnt == 0) {
  3657. ret = msm_cdc_pinctrl_select_sleep_state(
  3658. dmic_gpio);
  3659. if (ret < 0) {
  3660. pr_err("%s: gpio set cannot be de-activated %sd",
  3661. __func__, "dmic_gpio");
  3662. return ret;
  3663. }
  3664. }
  3665. break;
  3666. default:
  3667. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  3668. return -EINVAL;
  3669. }
  3670. return 0;
  3671. }
  3672. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  3673. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  3674. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  3675. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3676. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3677. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  3678. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3679. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3680. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3681. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3682. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3683. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3684. };
  3685. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3686. {
  3687. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3688. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  3689. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3690. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3691. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3692. }
  3693. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3694. {
  3695. int ret = -EINVAL;
  3696. struct snd_soc_component *component;
  3697. struct snd_soc_dapm_context *dapm;
  3698. struct snd_card *card;
  3699. struct snd_info_entry *entry;
  3700. struct snd_soc_component *aux_comp;
  3701. struct msm_asoc_mach_data *pdata =
  3702. snd_soc_card_get_drvdata(rtd->card);
  3703. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  3704. if (!component) {
  3705. pr_err("%s: could not find component for bolero_codec\n",
  3706. __func__);
  3707. return ret;
  3708. }
  3709. dapm = snd_soc_component_get_dapm(component);
  3710. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  3711. ARRAY_SIZE(msm_int_snd_controls));
  3712. if (ret < 0) {
  3713. pr_err("%s: add_component_controls failed: %d\n",
  3714. __func__, ret);
  3715. return ret;
  3716. }
  3717. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  3718. ARRAY_SIZE(msm_common_snd_controls));
  3719. if (ret < 0) {
  3720. pr_err("%s: add common snd controls failed: %d\n",
  3721. __func__, ret);
  3722. return ret;
  3723. }
  3724. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  3725. ARRAY_SIZE(msm_int_dapm_widgets));
  3726. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3727. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3728. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3729. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3730. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  3731. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  3732. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3733. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3734. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  3735. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3736. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3737. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3738. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3739. snd_soc_dapm_sync(dapm);
  3740. /*
  3741. * Send speaker configuration only for WSA8810.
  3742. * Default configuration is for WSA8815.
  3743. */
  3744. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  3745. __func__, rtd->card->num_aux_devs);
  3746. if (rtd->card->num_aux_devs &&
  3747. !list_empty(&rtd->card->component_dev_list)) {
  3748. aux_comp = list_first_entry(
  3749. &rtd->card->component_dev_list,
  3750. struct snd_soc_component,
  3751. card_aux_list);
  3752. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  3753. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  3754. wsa_macro_set_spkr_mode(component,
  3755. WSA_MACRO_SPKR_MODE_1);
  3756. wsa_macro_set_spkr_gain_offset(component,
  3757. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  3758. }
  3759. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  3760. sm_port_map);
  3761. }
  3762. card = rtd->card->snd_card;
  3763. if (!pdata->codec_root) {
  3764. entry = snd_info_create_subdir(card->module, "codecs",
  3765. card->proc_root);
  3766. if (!entry) {
  3767. pr_debug("%s: Cannot create codecs module entry\n",
  3768. __func__);
  3769. ret = 0;
  3770. goto err;
  3771. }
  3772. pdata->codec_root = entry;
  3773. }
  3774. bolero_info_create_codec_entry(pdata->codec_root, component);
  3775. bolero_register_wake_irq(component, false);
  3776. codec_reg_done = true;
  3777. return 0;
  3778. err:
  3779. return ret;
  3780. }
  3781. static void *def_wcd_mbhc_cal(void)
  3782. {
  3783. void *wcd_mbhc_cal;
  3784. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  3785. u16 *btn_high;
  3786. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  3787. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  3788. if (!wcd_mbhc_cal)
  3789. return NULL;
  3790. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  3791. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  3792. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  3793. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  3794. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  3795. btn_high[0] = 75;
  3796. btn_high[1] = 150;
  3797. btn_high[2] = 237;
  3798. btn_high[3] = 500;
  3799. btn_high[4] = 500;
  3800. btn_high[5] = 500;
  3801. btn_high[6] = 500;
  3802. btn_high[7] = 500;
  3803. return wcd_mbhc_cal;
  3804. }
  3805. /* Digital audio interface glue - connects codec <---> CPU */
  3806. static struct snd_soc_dai_link msm_common_dai_links[] = {
  3807. /* FrontEnd DAI Links */
  3808. {/* hw:x,0 */
  3809. .name = MSM_DAILINK_NAME(Media1),
  3810. .stream_name = "MultiMedia1",
  3811. .cpu_dai_name = "MultiMedia1",
  3812. .platform_name = "msm-pcm-dsp.0",
  3813. .dynamic = 1,
  3814. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3815. .dpcm_playback = 1,
  3816. .dpcm_capture = 1,
  3817. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3818. SND_SOC_DPCM_TRIGGER_POST},
  3819. .codec_dai_name = "snd-soc-dummy-dai",
  3820. .codec_name = "snd-soc-dummy",
  3821. .ignore_suspend = 1,
  3822. /* this dainlink has playback support */
  3823. .ignore_pmdown_time = 1,
  3824. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  3825. },
  3826. {/* hw:x,1 */
  3827. .name = MSM_DAILINK_NAME(Media2),
  3828. .stream_name = "MultiMedia2",
  3829. .cpu_dai_name = "MultiMedia2",
  3830. .platform_name = "msm-pcm-dsp.0",
  3831. .dynamic = 1,
  3832. .dpcm_playback = 1,
  3833. .dpcm_capture = 1,
  3834. .codec_dai_name = "snd-soc-dummy-dai",
  3835. .codec_name = "snd-soc-dummy",
  3836. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3837. SND_SOC_DPCM_TRIGGER_POST},
  3838. .ignore_suspend = 1,
  3839. /* this dainlink has playback support */
  3840. .ignore_pmdown_time = 1,
  3841. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  3842. },
  3843. {/* hw:x,2 */
  3844. .name = "VoiceMMode1",
  3845. .stream_name = "VoiceMMode1",
  3846. .cpu_dai_name = "VoiceMMode1",
  3847. .platform_name = "msm-pcm-voice",
  3848. .dynamic = 1,
  3849. .dpcm_playback = 1,
  3850. .dpcm_capture = 1,
  3851. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3852. SND_SOC_DPCM_TRIGGER_POST},
  3853. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3854. .ignore_suspend = 1,
  3855. .ignore_pmdown_time = 1,
  3856. .codec_dai_name = "snd-soc-dummy-dai",
  3857. .codec_name = "snd-soc-dummy",
  3858. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  3859. },
  3860. {/* hw:x,3 */
  3861. .name = "MSM VoIP",
  3862. .stream_name = "VoIP",
  3863. .cpu_dai_name = "VoIP",
  3864. .platform_name = "msm-voip-dsp",
  3865. .dynamic = 1,
  3866. .dpcm_playback = 1,
  3867. .dpcm_capture = 1,
  3868. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3869. SND_SOC_DPCM_TRIGGER_POST},
  3870. .codec_dai_name = "snd-soc-dummy-dai",
  3871. .codec_name = "snd-soc-dummy",
  3872. .ignore_suspend = 1,
  3873. /* this dainlink has playback support */
  3874. .ignore_pmdown_time = 1,
  3875. .id = MSM_FRONTEND_DAI_VOIP,
  3876. },
  3877. {/* hw:x,4 */
  3878. .name = MSM_DAILINK_NAME(ULL),
  3879. .stream_name = "MultiMedia3",
  3880. .cpu_dai_name = "MultiMedia3",
  3881. .platform_name = "msm-pcm-dsp.2",
  3882. .dynamic = 1,
  3883. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3884. .dpcm_playback = 1,
  3885. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3886. SND_SOC_DPCM_TRIGGER_POST},
  3887. .codec_dai_name = "snd-soc-dummy-dai",
  3888. .codec_name = "snd-soc-dummy",
  3889. .ignore_suspend = 1,
  3890. /* this dainlink has playback support */
  3891. .ignore_pmdown_time = 1,
  3892. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  3893. },
  3894. {/* hw:x,5 */
  3895. .name = "MSM AFE-PCM RX",
  3896. .stream_name = "AFE-PROXY RX",
  3897. .cpu_dai_name = "msm-dai-q6-dev.241",
  3898. .codec_name = "msm-stub-codec.1",
  3899. .codec_dai_name = "msm-stub-rx",
  3900. .platform_name = "msm-pcm-afe",
  3901. .dpcm_playback = 1,
  3902. .ignore_suspend = 1,
  3903. /* this dainlink has playback support */
  3904. .ignore_pmdown_time = 1,
  3905. },
  3906. {/* hw:x,6 */
  3907. .name = "MSM AFE-PCM TX",
  3908. .stream_name = "AFE-PROXY TX",
  3909. .cpu_dai_name = "msm-dai-q6-dev.240",
  3910. .codec_name = "msm-stub-codec.1",
  3911. .codec_dai_name = "msm-stub-tx",
  3912. .platform_name = "msm-pcm-afe",
  3913. .dpcm_capture = 1,
  3914. .ignore_suspend = 1,
  3915. },
  3916. {/* hw:x,7 */
  3917. .name = MSM_DAILINK_NAME(Compress1),
  3918. .stream_name = "Compress1",
  3919. .cpu_dai_name = "MultiMedia4",
  3920. .platform_name = "msm-compress-dsp",
  3921. .dynamic = 1,
  3922. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  3923. .dpcm_playback = 1,
  3924. .dpcm_capture = 1,
  3925. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3926. SND_SOC_DPCM_TRIGGER_POST},
  3927. .codec_dai_name = "snd-soc-dummy-dai",
  3928. .codec_name = "snd-soc-dummy",
  3929. .ignore_suspend = 1,
  3930. .ignore_pmdown_time = 1,
  3931. /* this dainlink has playback support */
  3932. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  3933. },
  3934. /* Hostless PCM purpose */
  3935. {/* hw:x,8 */
  3936. .name = "AUXPCM Hostless",
  3937. .stream_name = "AUXPCM Hostless",
  3938. .cpu_dai_name = "AUXPCM_HOSTLESS",
  3939. .platform_name = "msm-pcm-hostless",
  3940. .dynamic = 1,
  3941. .dpcm_playback = 1,
  3942. .dpcm_capture = 1,
  3943. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3944. SND_SOC_DPCM_TRIGGER_POST},
  3945. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3946. .ignore_suspend = 1,
  3947. /* this dainlink has playback support */
  3948. .ignore_pmdown_time = 1,
  3949. .codec_dai_name = "snd-soc-dummy-dai",
  3950. .codec_name = "snd-soc-dummy",
  3951. },
  3952. {/* hw:x,9 */
  3953. .name = MSM_DAILINK_NAME(LowLatency),
  3954. .stream_name = "MultiMedia5",
  3955. .cpu_dai_name = "MultiMedia5",
  3956. .platform_name = "msm-pcm-dsp.1",
  3957. .dynamic = 1,
  3958. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3959. .dpcm_playback = 1,
  3960. .dpcm_capture = 1,
  3961. .codec_dai_name = "snd-soc-dummy-dai",
  3962. .codec_name = "snd-soc-dummy",
  3963. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3964. SND_SOC_DPCM_TRIGGER_POST},
  3965. .ignore_suspend = 1,
  3966. /* this dainlink has playback support */
  3967. .ignore_pmdown_time = 1,
  3968. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  3969. .ops = &msm_fe_qos_ops,
  3970. },
  3971. {/* hw:x,10 */
  3972. .name = "Listen 1 Audio Service",
  3973. .stream_name = "Listen 1 Audio Service",
  3974. .cpu_dai_name = "LSM1",
  3975. .platform_name = "msm-lsm-client",
  3976. .dynamic = 1,
  3977. .dpcm_capture = 1,
  3978. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  3979. SND_SOC_DPCM_TRIGGER_POST },
  3980. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3981. .ignore_suspend = 1,
  3982. .codec_dai_name = "snd-soc-dummy-dai",
  3983. .codec_name = "snd-soc-dummy",
  3984. .id = MSM_FRONTEND_DAI_LSM1,
  3985. },
  3986. /* Multiple Tunnel instances */
  3987. {/* hw:x,11 */
  3988. .name = MSM_DAILINK_NAME(Compress2),
  3989. .stream_name = "Compress2",
  3990. .cpu_dai_name = "MultiMedia7",
  3991. .platform_name = "msm-compress-dsp",
  3992. .dynamic = 1,
  3993. .dpcm_playback = 1,
  3994. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3995. SND_SOC_DPCM_TRIGGER_POST},
  3996. .codec_dai_name = "snd-soc-dummy-dai",
  3997. .codec_name = "snd-soc-dummy",
  3998. .ignore_suspend = 1,
  3999. .ignore_pmdown_time = 1,
  4000. /* this dainlink has playback support */
  4001. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4002. },
  4003. {/* hw:x,12 */
  4004. .name = MSM_DAILINK_NAME(MultiMedia10),
  4005. .stream_name = "MultiMedia10",
  4006. .cpu_dai_name = "MultiMedia10",
  4007. .platform_name = "msm-pcm-dsp.1",
  4008. .dynamic = 1,
  4009. .dpcm_playback = 1,
  4010. .dpcm_capture = 1,
  4011. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4012. SND_SOC_DPCM_TRIGGER_POST},
  4013. .codec_dai_name = "snd-soc-dummy-dai",
  4014. .codec_name = "snd-soc-dummy",
  4015. .ignore_suspend = 1,
  4016. .ignore_pmdown_time = 1,
  4017. /* this dainlink has playback support */
  4018. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4019. },
  4020. {/* hw:x,13 */
  4021. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4022. .stream_name = "MM_NOIRQ",
  4023. .cpu_dai_name = "MultiMedia8",
  4024. .platform_name = "msm-pcm-dsp-noirq",
  4025. .dynamic = 1,
  4026. .dpcm_playback = 1,
  4027. .dpcm_capture = 1,
  4028. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4029. SND_SOC_DPCM_TRIGGER_POST},
  4030. .codec_dai_name = "snd-soc-dummy-dai",
  4031. .codec_name = "snd-soc-dummy",
  4032. .ignore_suspend = 1,
  4033. .ignore_pmdown_time = 1,
  4034. /* this dainlink has playback support */
  4035. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4036. .ops = &msm_fe_qos_ops,
  4037. },
  4038. /* HDMI Hostless */
  4039. {/* hw:x,14 */
  4040. .name = "HDMI_RX_HOSTLESS",
  4041. .stream_name = "HDMI_RX_HOSTLESS",
  4042. .cpu_dai_name = "HDMI_HOSTLESS",
  4043. .platform_name = "msm-pcm-hostless",
  4044. .dynamic = 1,
  4045. .dpcm_playback = 1,
  4046. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4047. SND_SOC_DPCM_TRIGGER_POST},
  4048. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4049. .ignore_suspend = 1,
  4050. .ignore_pmdown_time = 1,
  4051. .codec_dai_name = "snd-soc-dummy-dai",
  4052. .codec_name = "snd-soc-dummy",
  4053. },
  4054. {/* hw:x,15 */
  4055. .name = "VoiceMMode2",
  4056. .stream_name = "VoiceMMode2",
  4057. .cpu_dai_name = "VoiceMMode2",
  4058. .platform_name = "msm-pcm-voice",
  4059. .dynamic = 1,
  4060. .dpcm_playback = 1,
  4061. .dpcm_capture = 1,
  4062. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4063. SND_SOC_DPCM_TRIGGER_POST},
  4064. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4065. .ignore_suspend = 1,
  4066. .ignore_pmdown_time = 1,
  4067. .codec_dai_name = "snd-soc-dummy-dai",
  4068. .codec_name = "snd-soc-dummy",
  4069. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4070. },
  4071. /* LSM FE */
  4072. {/* hw:x,16 */
  4073. .name = "Listen 2 Audio Service",
  4074. .stream_name = "Listen 2 Audio Service",
  4075. .cpu_dai_name = "LSM2",
  4076. .platform_name = "msm-lsm-client",
  4077. .dynamic = 1,
  4078. .dpcm_capture = 1,
  4079. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4080. SND_SOC_DPCM_TRIGGER_POST },
  4081. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4082. .ignore_suspend = 1,
  4083. .codec_dai_name = "snd-soc-dummy-dai",
  4084. .codec_name = "snd-soc-dummy",
  4085. .id = MSM_FRONTEND_DAI_LSM2,
  4086. },
  4087. {/* hw:x,17 */
  4088. .name = "Listen 3 Audio Service",
  4089. .stream_name = "Listen 3 Audio Service",
  4090. .cpu_dai_name = "LSM3",
  4091. .platform_name = "msm-lsm-client",
  4092. .dynamic = 1,
  4093. .dpcm_capture = 1,
  4094. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4095. SND_SOC_DPCM_TRIGGER_POST },
  4096. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4097. .ignore_suspend = 1,
  4098. .codec_dai_name = "snd-soc-dummy-dai",
  4099. .codec_name = "snd-soc-dummy",
  4100. .id = MSM_FRONTEND_DAI_LSM3,
  4101. },
  4102. {/* hw:x,18 */
  4103. .name = "Listen 4 Audio Service",
  4104. .stream_name = "Listen 4 Audio Service",
  4105. .cpu_dai_name = "LSM4",
  4106. .platform_name = "msm-lsm-client",
  4107. .dynamic = 1,
  4108. .dpcm_capture = 1,
  4109. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4110. SND_SOC_DPCM_TRIGGER_POST },
  4111. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4112. .ignore_suspend = 1,
  4113. .codec_dai_name = "snd-soc-dummy-dai",
  4114. .codec_name = "snd-soc-dummy",
  4115. .id = MSM_FRONTEND_DAI_LSM4,
  4116. },
  4117. {/* hw:x,19 */
  4118. .name = "Listen 5 Audio Service",
  4119. .stream_name = "Listen 5 Audio Service",
  4120. .cpu_dai_name = "LSM5",
  4121. .platform_name = "msm-lsm-client",
  4122. .dynamic = 1,
  4123. .dpcm_capture = 1,
  4124. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4125. SND_SOC_DPCM_TRIGGER_POST },
  4126. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4127. .ignore_suspend = 1,
  4128. .codec_dai_name = "snd-soc-dummy-dai",
  4129. .codec_name = "snd-soc-dummy",
  4130. .id = MSM_FRONTEND_DAI_LSM5,
  4131. },
  4132. {/* hw:x,20 */
  4133. .name = "Listen 6 Audio Service",
  4134. .stream_name = "Listen 6 Audio Service",
  4135. .cpu_dai_name = "LSM6",
  4136. .platform_name = "msm-lsm-client",
  4137. .dynamic = 1,
  4138. .dpcm_capture = 1,
  4139. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4140. SND_SOC_DPCM_TRIGGER_POST },
  4141. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4142. .ignore_suspend = 1,
  4143. .codec_dai_name = "snd-soc-dummy-dai",
  4144. .codec_name = "snd-soc-dummy",
  4145. .id = MSM_FRONTEND_DAI_LSM6,
  4146. },
  4147. {/* hw:x,21 */
  4148. .name = "Listen 7 Audio Service",
  4149. .stream_name = "Listen 7 Audio Service",
  4150. .cpu_dai_name = "LSM7",
  4151. .platform_name = "msm-lsm-client",
  4152. .dynamic = 1,
  4153. .dpcm_capture = 1,
  4154. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4155. SND_SOC_DPCM_TRIGGER_POST },
  4156. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4157. .ignore_suspend = 1,
  4158. .codec_dai_name = "snd-soc-dummy-dai",
  4159. .codec_name = "snd-soc-dummy",
  4160. .id = MSM_FRONTEND_DAI_LSM7,
  4161. },
  4162. {/* hw:x,22 */
  4163. .name = "Listen 8 Audio Service",
  4164. .stream_name = "Listen 8 Audio Service",
  4165. .cpu_dai_name = "LSM8",
  4166. .platform_name = "msm-lsm-client",
  4167. .dynamic = 1,
  4168. .dpcm_capture = 1,
  4169. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4170. SND_SOC_DPCM_TRIGGER_POST },
  4171. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4172. .ignore_suspend = 1,
  4173. .codec_dai_name = "snd-soc-dummy-dai",
  4174. .codec_name = "snd-soc-dummy",
  4175. .id = MSM_FRONTEND_DAI_LSM8,
  4176. },
  4177. {/* hw:x,23 */
  4178. .name = MSM_DAILINK_NAME(Media9),
  4179. .stream_name = "MultiMedia9",
  4180. .cpu_dai_name = "MultiMedia9",
  4181. .platform_name = "msm-pcm-dsp.0",
  4182. .dynamic = 1,
  4183. .dpcm_playback = 1,
  4184. .dpcm_capture = 1,
  4185. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4186. SND_SOC_DPCM_TRIGGER_POST},
  4187. .codec_dai_name = "snd-soc-dummy-dai",
  4188. .codec_name = "snd-soc-dummy",
  4189. .ignore_suspend = 1,
  4190. /* this dainlink has playback support */
  4191. .ignore_pmdown_time = 1,
  4192. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4193. },
  4194. {/* hw:x,24 */
  4195. .name = MSM_DAILINK_NAME(Compress4),
  4196. .stream_name = "Compress4",
  4197. .cpu_dai_name = "MultiMedia11",
  4198. .platform_name = "msm-compress-dsp",
  4199. .dynamic = 1,
  4200. .dpcm_playback = 1,
  4201. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4202. SND_SOC_DPCM_TRIGGER_POST},
  4203. .codec_dai_name = "snd-soc-dummy-dai",
  4204. .codec_name = "snd-soc-dummy",
  4205. .ignore_suspend = 1,
  4206. .ignore_pmdown_time = 1,
  4207. /* this dainlink has playback support */
  4208. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4209. },
  4210. {/* hw:x,25 */
  4211. .name = MSM_DAILINK_NAME(Compress5),
  4212. .stream_name = "Compress5",
  4213. .cpu_dai_name = "MultiMedia12",
  4214. .platform_name = "msm-compress-dsp",
  4215. .dynamic = 1,
  4216. .dpcm_playback = 1,
  4217. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4218. SND_SOC_DPCM_TRIGGER_POST},
  4219. .codec_dai_name = "snd-soc-dummy-dai",
  4220. .codec_name = "snd-soc-dummy",
  4221. .ignore_suspend = 1,
  4222. .ignore_pmdown_time = 1,
  4223. /* this dainlink has playback support */
  4224. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4225. },
  4226. {/* hw:x,26 */
  4227. .name = MSM_DAILINK_NAME(Compress6),
  4228. .stream_name = "Compress6",
  4229. .cpu_dai_name = "MultiMedia13",
  4230. .platform_name = "msm-compress-dsp",
  4231. .dynamic = 1,
  4232. .dpcm_playback = 1,
  4233. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4234. SND_SOC_DPCM_TRIGGER_POST},
  4235. .codec_dai_name = "snd-soc-dummy-dai",
  4236. .codec_name = "snd-soc-dummy",
  4237. .ignore_suspend = 1,
  4238. .ignore_pmdown_time = 1,
  4239. /* this dainlink has playback support */
  4240. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4241. },
  4242. {/* hw:x,27 */
  4243. .name = MSM_DAILINK_NAME(Compress7),
  4244. .stream_name = "Compress7",
  4245. .cpu_dai_name = "MultiMedia14",
  4246. .platform_name = "msm-compress-dsp",
  4247. .dynamic = 1,
  4248. .dpcm_playback = 1,
  4249. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4250. SND_SOC_DPCM_TRIGGER_POST},
  4251. .codec_dai_name = "snd-soc-dummy-dai",
  4252. .codec_name = "snd-soc-dummy",
  4253. .ignore_suspend = 1,
  4254. .ignore_pmdown_time = 1,
  4255. /* this dainlink has playback support */
  4256. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4257. },
  4258. {/* hw:x,28 */
  4259. .name = MSM_DAILINK_NAME(Compress8),
  4260. .stream_name = "Compress8",
  4261. .cpu_dai_name = "MultiMedia15",
  4262. .platform_name = "msm-compress-dsp",
  4263. .dynamic = 1,
  4264. .dpcm_playback = 1,
  4265. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4266. SND_SOC_DPCM_TRIGGER_POST},
  4267. .codec_dai_name = "snd-soc-dummy-dai",
  4268. .codec_name = "snd-soc-dummy",
  4269. .ignore_suspend = 1,
  4270. .ignore_pmdown_time = 1,
  4271. /* this dainlink has playback support */
  4272. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4273. },
  4274. {/* hw:x,29 */
  4275. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4276. .stream_name = "MM_NOIRQ_2",
  4277. .cpu_dai_name = "MultiMedia16",
  4278. .platform_name = "msm-pcm-dsp-noirq",
  4279. .dynamic = 1,
  4280. .dpcm_playback = 1,
  4281. .dpcm_capture = 1,
  4282. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4283. SND_SOC_DPCM_TRIGGER_POST},
  4284. .codec_dai_name = "snd-soc-dummy-dai",
  4285. .codec_name = "snd-soc-dummy",
  4286. .ignore_suspend = 1,
  4287. .ignore_pmdown_time = 1,
  4288. /* this dainlink has playback support */
  4289. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4290. },
  4291. {/* hw:x,30 */
  4292. .name = "CDC_DMA Hostless",
  4293. .stream_name = "CDC_DMA Hostless",
  4294. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  4295. .platform_name = "msm-pcm-hostless",
  4296. .dynamic = 1,
  4297. .dpcm_playback = 1,
  4298. .dpcm_capture = 1,
  4299. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4300. SND_SOC_DPCM_TRIGGER_POST},
  4301. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4302. .ignore_suspend = 1,
  4303. /* this dailink has playback support */
  4304. .ignore_pmdown_time = 1,
  4305. .codec_dai_name = "snd-soc-dummy-dai",
  4306. .codec_name = "snd-soc-dummy",
  4307. },
  4308. {/* hw:x,31 */
  4309. .name = "TX3_CDC_DMA Hostless",
  4310. .stream_name = "TX3_CDC_DMA Hostless",
  4311. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  4312. .platform_name = "msm-pcm-hostless",
  4313. .dynamic = 1,
  4314. .dpcm_capture = 1,
  4315. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4316. SND_SOC_DPCM_TRIGGER_POST},
  4317. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4318. .ignore_suspend = 1,
  4319. .codec_dai_name = "snd-soc-dummy-dai",
  4320. .codec_name = "snd-soc-dummy",
  4321. },
  4322. {/* hw:x,32 */
  4323. .name = "Tertiary MI2S TX_Hostless",
  4324. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4325. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  4326. .platform_name = "msm-pcm-hostless",
  4327. .dynamic = 1,
  4328. .dpcm_capture = 1,
  4329. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4330. SND_SOC_DPCM_TRIGGER_POST},
  4331. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4332. .ignore_suspend = 1,
  4333. .ignore_pmdown_time = 1,
  4334. .codec_dai_name = "snd-soc-dummy-dai",
  4335. .codec_name = "snd-soc-dummy",
  4336. },
  4337. };
  4338. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  4339. {/* hw:x,33 */
  4340. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  4341. .stream_name = "WSA CDC DMA0 Capture",
  4342. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  4343. .platform_name = "msm-pcm-hostless",
  4344. .codec_name = "bolero_codec",
  4345. .codec_dai_name = "wsa_macro_vifeedback",
  4346. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  4347. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4348. .ignore_suspend = 1,
  4349. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4350. .ops = &msm_cdc_dma_be_ops,
  4351. },
  4352. };
  4353. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4354. {/* hw:x,34 */
  4355. .name = MSM_DAILINK_NAME(ASM Loopback),
  4356. .stream_name = "MultiMedia6",
  4357. .cpu_dai_name = "MultiMedia6",
  4358. .platform_name = "msm-pcm-loopback",
  4359. .dynamic = 1,
  4360. .dpcm_playback = 1,
  4361. .dpcm_capture = 1,
  4362. .codec_dai_name = "snd-soc-dummy-dai",
  4363. .codec_name = "snd-soc-dummy",
  4364. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4365. SND_SOC_DPCM_TRIGGER_POST},
  4366. .ignore_suspend = 1,
  4367. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4368. .ignore_pmdown_time = 1,
  4369. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4370. },
  4371. {/* hw:x,35 */
  4372. .name = "USB Audio Hostless",
  4373. .stream_name = "USB Audio Hostless",
  4374. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  4375. .platform_name = "msm-pcm-hostless",
  4376. .dynamic = 1,
  4377. .dpcm_playback = 1,
  4378. .dpcm_capture = 1,
  4379. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4380. SND_SOC_DPCM_TRIGGER_POST},
  4381. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4382. .ignore_suspend = 1,
  4383. .ignore_pmdown_time = 1,
  4384. .codec_dai_name = "snd-soc-dummy-dai",
  4385. .codec_name = "snd-soc-dummy",
  4386. },
  4387. {/* hw:x,36 */
  4388. .name = "SLIMBUS_7 Hostless",
  4389. .stream_name = "SLIMBUS_7 Hostless",
  4390. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  4391. .platform_name = "msm-pcm-hostless",
  4392. .dynamic = 1,
  4393. .dpcm_capture = 1,
  4394. .dpcm_playback = 1,
  4395. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4396. SND_SOC_DPCM_TRIGGER_POST},
  4397. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4398. .ignore_suspend = 1,
  4399. .ignore_pmdown_time = 1,
  4400. .codec_dai_name = "snd-soc-dummy-dai",
  4401. .codec_name = "snd-soc-dummy",
  4402. },
  4403. {/* hw:x,37 */
  4404. .name = "Compress Capture",
  4405. .stream_name = "Compress9",
  4406. .cpu_dai_name = "MultiMedia17",
  4407. .platform_name = "msm-compress-dsp",
  4408. .dynamic = 1,
  4409. .dpcm_capture = 1,
  4410. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4411. SND_SOC_DPCM_TRIGGER_POST},
  4412. .codec_dai_name = "snd-soc-dummy-dai",
  4413. .codec_name = "snd-soc-dummy",
  4414. .ignore_suspend = 1,
  4415. .ignore_pmdown_time = 1,
  4416. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4417. },
  4418. };
  4419. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4420. /* Backend AFE DAI Links */
  4421. {
  4422. .name = LPASS_BE_AFE_PCM_RX,
  4423. .stream_name = "AFE Playback",
  4424. .cpu_dai_name = "msm-dai-q6-dev.224",
  4425. .platform_name = "msm-pcm-routing",
  4426. .codec_name = "msm-stub-codec.1",
  4427. .codec_dai_name = "msm-stub-rx",
  4428. .no_pcm = 1,
  4429. .dpcm_playback = 1,
  4430. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4431. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4432. /* this dainlink has playback support */
  4433. .ignore_pmdown_time = 1,
  4434. .ignore_suspend = 1,
  4435. },
  4436. {
  4437. .name = LPASS_BE_AFE_PCM_TX,
  4438. .stream_name = "AFE Capture",
  4439. .cpu_dai_name = "msm-dai-q6-dev.225",
  4440. .platform_name = "msm-pcm-routing",
  4441. .codec_name = "msm-stub-codec.1",
  4442. .codec_dai_name = "msm-stub-tx",
  4443. .no_pcm = 1,
  4444. .dpcm_capture = 1,
  4445. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4447. .ignore_suspend = 1,
  4448. },
  4449. /* Incall Record Uplink BACK END DAI Link */
  4450. {
  4451. .name = LPASS_BE_INCALL_RECORD_TX,
  4452. .stream_name = "Voice Uplink Capture",
  4453. .cpu_dai_name = "msm-dai-q6-dev.32772",
  4454. .platform_name = "msm-pcm-routing",
  4455. .codec_name = "msm-stub-codec.1",
  4456. .codec_dai_name = "msm-stub-tx",
  4457. .no_pcm = 1,
  4458. .dpcm_capture = 1,
  4459. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4460. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4461. .ignore_suspend = 1,
  4462. },
  4463. /* Incall Record Downlink BACK END DAI Link */
  4464. {
  4465. .name = LPASS_BE_INCALL_RECORD_RX,
  4466. .stream_name = "Voice Downlink Capture",
  4467. .cpu_dai_name = "msm-dai-q6-dev.32771",
  4468. .platform_name = "msm-pcm-routing",
  4469. .codec_name = "msm-stub-codec.1",
  4470. .codec_dai_name = "msm-stub-tx",
  4471. .no_pcm = 1,
  4472. .dpcm_capture = 1,
  4473. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4474. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4475. .ignore_suspend = 1,
  4476. },
  4477. /* Incall Music BACK END DAI Link */
  4478. {
  4479. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4480. .stream_name = "Voice Farend Playback",
  4481. .cpu_dai_name = "msm-dai-q6-dev.32773",
  4482. .platform_name = "msm-pcm-routing",
  4483. .codec_name = "msm-stub-codec.1",
  4484. .codec_dai_name = "msm-stub-rx",
  4485. .no_pcm = 1,
  4486. .dpcm_playback = 1,
  4487. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4488. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4489. .ignore_suspend = 1,
  4490. .ignore_pmdown_time = 1,
  4491. },
  4492. /* Incall Music 2 BACK END DAI Link */
  4493. {
  4494. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4495. .stream_name = "Voice2 Farend Playback",
  4496. .cpu_dai_name = "msm-dai-q6-dev.32770",
  4497. .platform_name = "msm-pcm-routing",
  4498. .codec_name = "msm-stub-codec.1",
  4499. .codec_dai_name = "msm-stub-rx",
  4500. .no_pcm = 1,
  4501. .dpcm_playback = 1,
  4502. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4503. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4504. .ignore_suspend = 1,
  4505. .ignore_pmdown_time = 1,
  4506. },
  4507. {
  4508. .name = LPASS_BE_USB_AUDIO_RX,
  4509. .stream_name = "USB Audio Playback",
  4510. .cpu_dai_name = "msm-dai-q6-dev.28672",
  4511. .platform_name = "msm-pcm-routing",
  4512. .codec_name = "msm-stub-codec.1",
  4513. .codec_dai_name = "msm-stub-rx",
  4514. .no_pcm = 1,
  4515. .dpcm_playback = 1,
  4516. .id = MSM_BACKEND_DAI_USB_RX,
  4517. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4518. .ignore_pmdown_time = 1,
  4519. .ignore_suspend = 1,
  4520. },
  4521. {
  4522. .name = LPASS_BE_USB_AUDIO_TX,
  4523. .stream_name = "USB Audio Capture",
  4524. .cpu_dai_name = "msm-dai-q6-dev.28673",
  4525. .platform_name = "msm-pcm-routing",
  4526. .codec_name = "msm-stub-codec.1",
  4527. .codec_dai_name = "msm-stub-tx",
  4528. .no_pcm = 1,
  4529. .dpcm_capture = 1,
  4530. .id = MSM_BACKEND_DAI_USB_TX,
  4531. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4532. .ignore_suspend = 1,
  4533. },
  4534. {
  4535. .name = LPASS_BE_PRI_TDM_RX_0,
  4536. .stream_name = "Primary TDM0 Playback",
  4537. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  4538. .platform_name = "msm-pcm-routing",
  4539. .codec_name = "msm-stub-codec.1",
  4540. .codec_dai_name = "msm-stub-rx",
  4541. .no_pcm = 1,
  4542. .dpcm_playback = 1,
  4543. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4544. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4545. .ops = &kona_tdm_be_ops,
  4546. .ignore_suspend = 1,
  4547. .ignore_pmdown_time = 1,
  4548. },
  4549. {
  4550. .name = LPASS_BE_PRI_TDM_TX_0,
  4551. .stream_name = "Primary TDM0 Capture",
  4552. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  4553. .platform_name = "msm-pcm-routing",
  4554. .codec_name = "msm-stub-codec.1",
  4555. .codec_dai_name = "msm-stub-tx",
  4556. .no_pcm = 1,
  4557. .dpcm_capture = 1,
  4558. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4559. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4560. .ops = &kona_tdm_be_ops,
  4561. .ignore_suspend = 1,
  4562. },
  4563. {
  4564. .name = LPASS_BE_SEC_TDM_RX_0,
  4565. .stream_name = "Secondary TDM0 Playback",
  4566. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  4567. .platform_name = "msm-pcm-routing",
  4568. .codec_name = "msm-stub-codec.1",
  4569. .codec_dai_name = "msm-stub-rx",
  4570. .no_pcm = 1,
  4571. .dpcm_playback = 1,
  4572. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4573. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4574. .ops = &kona_tdm_be_ops,
  4575. .ignore_suspend = 1,
  4576. .ignore_pmdown_time = 1,
  4577. },
  4578. {
  4579. .name = LPASS_BE_SEC_TDM_TX_0,
  4580. .stream_name = "Secondary TDM0 Capture",
  4581. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  4582. .platform_name = "msm-pcm-routing",
  4583. .codec_name = "msm-stub-codec.1",
  4584. .codec_dai_name = "msm-stub-tx",
  4585. .no_pcm = 1,
  4586. .dpcm_capture = 1,
  4587. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4588. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4589. .ops = &kona_tdm_be_ops,
  4590. .ignore_suspend = 1,
  4591. },
  4592. {
  4593. .name = LPASS_BE_TERT_TDM_RX_0,
  4594. .stream_name = "Tertiary TDM0 Playback",
  4595. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  4596. .platform_name = "msm-pcm-routing",
  4597. .codec_name = "msm-stub-codec.1",
  4598. .codec_dai_name = "msm-stub-rx",
  4599. .no_pcm = 1,
  4600. .dpcm_playback = 1,
  4601. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4602. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4603. .ops = &kona_tdm_be_ops,
  4604. .ignore_suspend = 1,
  4605. .ignore_pmdown_time = 1,
  4606. },
  4607. {
  4608. .name = LPASS_BE_TERT_TDM_TX_0,
  4609. .stream_name = "Tertiary TDM0 Capture",
  4610. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  4611. .platform_name = "msm-pcm-routing",
  4612. .codec_name = "msm-stub-codec.1",
  4613. .codec_dai_name = "msm-stub-tx",
  4614. .no_pcm = 1,
  4615. .dpcm_capture = 1,
  4616. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4617. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4618. .ops = &kona_tdm_be_ops,
  4619. .ignore_suspend = 1,
  4620. },
  4621. };
  4622. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  4623. {
  4624. .name = LPASS_BE_SLIMBUS_7_RX,
  4625. .stream_name = "Slimbus7 Playback",
  4626. .cpu_dai_name = "msm-dai-q6-dev.16398",
  4627. .platform_name = "msm-pcm-routing",
  4628. .codec_name = "btfmslim_slave",
  4629. /* BT codec driver determines capabilities based on
  4630. * dai name, bt codecdai name should always contains
  4631. * supported usecase information
  4632. */
  4633. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  4634. .no_pcm = 1,
  4635. .dpcm_playback = 1,
  4636. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  4637. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4638. .init = &msm_wcn_init,
  4639. .ops = &msm_wcn_ops,
  4640. /* dai link has playback support */
  4641. .ignore_pmdown_time = 1,
  4642. .ignore_suspend = 1,
  4643. },
  4644. {
  4645. .name = LPASS_BE_SLIMBUS_7_TX,
  4646. .stream_name = "Slimbus7 Capture",
  4647. .cpu_dai_name = "msm-dai-q6-dev.16399",
  4648. .platform_name = "msm-pcm-routing",
  4649. .codec_name = "btfmslim_slave",
  4650. .codec_dai_name = "btfm_bt_sco_slim_tx",
  4651. .no_pcm = 1,
  4652. .dpcm_capture = 1,
  4653. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  4654. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4655. .ops = &msm_wcn_ops,
  4656. .ignore_suspend = 1,
  4657. },
  4658. };
  4659. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  4660. /* DISP PORT BACK END DAI Link */
  4661. {
  4662. .name = LPASS_BE_DISPLAY_PORT,
  4663. .stream_name = "Display Port Playback",
  4664. .cpu_dai_name = "msm-dai-q6-dp.24608",
  4665. .platform_name = "msm-pcm-routing",
  4666. .codec_name = "msm-ext-disp-audio-codec-rx",
  4667. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  4668. .no_pcm = 1,
  4669. .dpcm_playback = 1,
  4670. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  4671. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4672. .ignore_pmdown_time = 1,
  4673. .ignore_suspend = 1,
  4674. },
  4675. /* DISP PORT 1 BACK END DAI Link */
  4676. {
  4677. .name = LPASS_BE_DISPLAY_PORT1,
  4678. .stream_name = "Display Port1 Playback",
  4679. .cpu_dai_name = "msm-dai-q6-dp.24608",
  4680. .platform_name = "msm-pcm-routing",
  4681. .codec_name = "msm-ext-disp-audio-codec-rx",
  4682. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  4683. .no_pcm = 1,
  4684. .dpcm_playback = 1,
  4685. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  4686. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4687. .ignore_pmdown_time = 1,
  4688. .ignore_suspend = 1,
  4689. },
  4690. };
  4691. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  4692. {
  4693. .name = LPASS_BE_PRI_MI2S_RX,
  4694. .stream_name = "Primary MI2S Playback",
  4695. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4696. .platform_name = "msm-pcm-routing",
  4697. .codec_name = "msm-stub-codec.1",
  4698. .codec_dai_name = "msm-stub-rx",
  4699. .no_pcm = 1,
  4700. .dpcm_playback = 1,
  4701. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  4702. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4703. .ops = &msm_mi2s_be_ops,
  4704. .ignore_suspend = 1,
  4705. .ignore_pmdown_time = 1,
  4706. },
  4707. {
  4708. .name = LPASS_BE_PRI_MI2S_TX,
  4709. .stream_name = "Primary MI2S Capture",
  4710. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4711. .platform_name = "msm-pcm-routing",
  4712. .codec_name = "msm-stub-codec.1",
  4713. .codec_dai_name = "msm-stub-tx",
  4714. .no_pcm = 1,
  4715. .dpcm_capture = 1,
  4716. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  4717. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4718. .ops = &msm_mi2s_be_ops,
  4719. .ignore_suspend = 1,
  4720. },
  4721. {
  4722. .name = LPASS_BE_SEC_MI2S_RX,
  4723. .stream_name = "Secondary MI2S Playback",
  4724. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4725. .platform_name = "msm-pcm-routing",
  4726. .codec_name = "msm-stub-codec.1",
  4727. .codec_dai_name = "msm-stub-rx",
  4728. .no_pcm = 1,
  4729. .dpcm_playback = 1,
  4730. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  4731. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4732. .ops = &msm_mi2s_be_ops,
  4733. .ignore_suspend = 1,
  4734. .ignore_pmdown_time = 1,
  4735. },
  4736. {
  4737. .name = LPASS_BE_SEC_MI2S_TX,
  4738. .stream_name = "Secondary MI2S Capture",
  4739. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4740. .platform_name = "msm-pcm-routing",
  4741. .codec_name = "msm-stub-codec.1",
  4742. .codec_dai_name = "msm-stub-tx",
  4743. .no_pcm = 1,
  4744. .dpcm_capture = 1,
  4745. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  4746. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4747. .ops = &msm_mi2s_be_ops,
  4748. .ignore_suspend = 1,
  4749. },
  4750. {
  4751. .name = LPASS_BE_TERT_MI2S_RX,
  4752. .stream_name = "Tertiary MI2S Playback",
  4753. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4754. .platform_name = "msm-pcm-routing",
  4755. .codec_name = "msm-stub-codec.1",
  4756. .codec_dai_name = "msm-stub-rx",
  4757. .no_pcm = 1,
  4758. .dpcm_playback = 1,
  4759. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  4760. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4761. .ops = &msm_mi2s_be_ops,
  4762. .ignore_suspend = 1,
  4763. .ignore_pmdown_time = 1,
  4764. },
  4765. {
  4766. .name = LPASS_BE_TERT_MI2S_TX,
  4767. .stream_name = "Tertiary MI2S Capture",
  4768. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4769. .platform_name = "msm-pcm-routing",
  4770. .codec_name = "msm-stub-codec.1",
  4771. .codec_dai_name = "msm-stub-tx",
  4772. .no_pcm = 1,
  4773. .dpcm_capture = 1,
  4774. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  4775. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4776. .ops = &msm_mi2s_be_ops,
  4777. .ignore_suspend = 1,
  4778. },
  4779. };
  4780. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  4781. /* Primary AUX PCM Backend DAI Links */
  4782. {
  4783. .name = LPASS_BE_AUXPCM_RX,
  4784. .stream_name = "AUX PCM Playback",
  4785. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4786. .platform_name = "msm-pcm-routing",
  4787. .codec_name = "msm-stub-codec.1",
  4788. .codec_dai_name = "msm-stub-rx",
  4789. .no_pcm = 1,
  4790. .dpcm_playback = 1,
  4791. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  4792. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4793. .ignore_pmdown_time = 1,
  4794. .ignore_suspend = 1,
  4795. },
  4796. {
  4797. .name = LPASS_BE_AUXPCM_TX,
  4798. .stream_name = "AUX PCM Capture",
  4799. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4800. .platform_name = "msm-pcm-routing",
  4801. .codec_name = "msm-stub-codec.1",
  4802. .codec_dai_name = "msm-stub-tx",
  4803. .no_pcm = 1,
  4804. .dpcm_capture = 1,
  4805. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  4806. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4807. .ignore_suspend = 1,
  4808. },
  4809. /* Secondary AUX PCM Backend DAI Links */
  4810. {
  4811. .name = LPASS_BE_SEC_AUXPCM_RX,
  4812. .stream_name = "Sec AUX PCM Playback",
  4813. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4814. .platform_name = "msm-pcm-routing",
  4815. .codec_name = "msm-stub-codec.1",
  4816. .codec_dai_name = "msm-stub-rx",
  4817. .no_pcm = 1,
  4818. .dpcm_playback = 1,
  4819. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  4820. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4821. .ignore_pmdown_time = 1,
  4822. .ignore_suspend = 1,
  4823. },
  4824. {
  4825. .name = LPASS_BE_SEC_AUXPCM_TX,
  4826. .stream_name = "Sec AUX PCM Capture",
  4827. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4828. .platform_name = "msm-pcm-routing",
  4829. .codec_name = "msm-stub-codec.1",
  4830. .codec_dai_name = "msm-stub-tx",
  4831. .no_pcm = 1,
  4832. .dpcm_capture = 1,
  4833. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  4834. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4835. .ignore_suspend = 1,
  4836. },
  4837. /* Tertiary AUX PCM Backend DAI Links */
  4838. {
  4839. .name = LPASS_BE_TERT_AUXPCM_RX,
  4840. .stream_name = "Tert AUX PCM Playback",
  4841. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4842. .platform_name = "msm-pcm-routing",
  4843. .codec_name = "msm-stub-codec.1",
  4844. .codec_dai_name = "msm-stub-rx",
  4845. .no_pcm = 1,
  4846. .dpcm_playback = 1,
  4847. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  4848. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4849. .ignore_suspend = 1,
  4850. },
  4851. {
  4852. .name = LPASS_BE_TERT_AUXPCM_TX,
  4853. .stream_name = "Tert AUX PCM Capture",
  4854. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4855. .platform_name = "msm-pcm-routing",
  4856. .codec_name = "msm-stub-codec.1",
  4857. .codec_dai_name = "msm-stub-tx",
  4858. .no_pcm = 1,
  4859. .dpcm_capture = 1,
  4860. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  4861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4862. .ignore_suspend = 1,
  4863. },
  4864. };
  4865. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  4866. /* WSA CDC DMA Backend DAI Links */
  4867. {
  4868. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  4869. .stream_name = "WSA CDC DMA0 Playback",
  4870. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  4871. .platform_name = "msm-pcm-routing",
  4872. .codec_name = "bolero_codec",
  4873. .codec_dai_name = "wsa_macro_rx1",
  4874. .no_pcm = 1,
  4875. .dpcm_playback = 1,
  4876. .init = &msm_int_audrx_init,
  4877. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  4878. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4879. .ignore_pmdown_time = 1,
  4880. .ignore_suspend = 1,
  4881. .ops = &msm_cdc_dma_be_ops,
  4882. },
  4883. {
  4884. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  4885. .stream_name = "WSA CDC DMA1 Playback",
  4886. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  4887. .platform_name = "msm-pcm-routing",
  4888. .codec_name = "bolero_codec",
  4889. .codec_dai_name = "wsa_macro_rx_mix",
  4890. .no_pcm = 1,
  4891. .dpcm_playback = 1,
  4892. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  4893. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4894. .ignore_pmdown_time = 1,
  4895. .ignore_suspend = 1,
  4896. .ops = &msm_cdc_dma_be_ops,
  4897. },
  4898. {
  4899. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  4900. .stream_name = "WSA CDC DMA1 Capture",
  4901. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  4902. .platform_name = "msm-pcm-routing",
  4903. .codec_name = "bolero_codec",
  4904. .codec_dai_name = "wsa_macro_echo",
  4905. .no_pcm = 1,
  4906. .dpcm_capture = 1,
  4907. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  4908. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4909. .ignore_suspend = 1,
  4910. .ops = &msm_cdc_dma_be_ops,
  4911. },
  4912. };
  4913. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  4914. /* RX CDC DMA Backend DAI Links */
  4915. {
  4916. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  4917. .stream_name = "RX CDC DMA0 Playback",
  4918. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  4919. .platform_name = "msm-pcm-routing",
  4920. .codec_name = "bolero_codec",
  4921. .codec_dai_name = "rx_macro_rx1",
  4922. .no_pcm = 1,
  4923. .dpcm_playback = 1,
  4924. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  4925. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4926. .ignore_pmdown_time = 1,
  4927. .ignore_suspend = 1,
  4928. .ops = &msm_cdc_dma_be_ops,
  4929. },
  4930. {
  4931. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  4932. .stream_name = "RX CDC DMA1 Playback",
  4933. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  4934. .platform_name = "msm-pcm-routing",
  4935. .codec_name = "bolero_codec",
  4936. .codec_dai_name = "rx_macro_rx2",
  4937. .no_pcm = 1,
  4938. .dpcm_playback = 1,
  4939. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  4940. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4941. .ignore_pmdown_time = 1,
  4942. .ignore_suspend = 1,
  4943. .ops = &msm_cdc_dma_be_ops,
  4944. },
  4945. {
  4946. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  4947. .stream_name = "RX CDC DMA2 Playback",
  4948. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  4949. .platform_name = "msm-pcm-routing",
  4950. .codec_name = "bolero_codec",
  4951. .codec_dai_name = "rx_macro_rx3",
  4952. .no_pcm = 1,
  4953. .dpcm_playback = 1,
  4954. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  4955. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4956. .ignore_pmdown_time = 1,
  4957. .ignore_suspend = 1,
  4958. .ops = &msm_cdc_dma_be_ops,
  4959. },
  4960. {
  4961. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  4962. .stream_name = "RX CDC DMA3 Playback",
  4963. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  4964. .platform_name = "msm-pcm-routing",
  4965. .codec_name = "bolero_codec",
  4966. .codec_dai_name = "rx_macro_rx4",
  4967. .no_pcm = 1,
  4968. .dpcm_playback = 1,
  4969. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  4970. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4971. .ignore_pmdown_time = 1,
  4972. .ignore_suspend = 1,
  4973. .ops = &msm_cdc_dma_be_ops,
  4974. },
  4975. /* TX CDC DMA Backend DAI Links */
  4976. {
  4977. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  4978. .stream_name = "TX CDC DMA3 Capture",
  4979. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  4980. .platform_name = "msm-pcm-routing",
  4981. .codec_name = "bolero_codec",
  4982. .codec_dai_name = "tx_macro_tx1",
  4983. .no_pcm = 1,
  4984. .dpcm_capture = 1,
  4985. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  4986. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4987. .ignore_suspend = 1,
  4988. .ops = &msm_cdc_dma_be_ops,
  4989. },
  4990. {
  4991. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  4992. .stream_name = "TX CDC DMA4 Capture",
  4993. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  4994. .platform_name = "msm-pcm-routing",
  4995. .codec_name = "bolero_codec",
  4996. .codec_dai_name = "tx_macro_tx2",
  4997. .no_pcm = 1,
  4998. .dpcm_capture = 1,
  4999. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5000. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5001. .ignore_suspend = 1,
  5002. .ops = &msm_cdc_dma_be_ops,
  5003. },
  5004. };
  5005. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5006. {
  5007. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5008. .stream_name = "VA CDC DMA0 Capture",
  5009. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  5010. .platform_name = "msm-pcm-routing",
  5011. .codec_name = "bolero_codec",
  5012. .codec_dai_name = "va_macro_tx1",
  5013. .no_pcm = 1,
  5014. .dpcm_capture = 1,
  5015. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5016. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5017. .ignore_suspend = 1,
  5018. .ops = &msm_cdc_dma_be_ops,
  5019. },
  5020. {
  5021. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5022. .stream_name = "VA CDC DMA1 Capture",
  5023. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  5024. .platform_name = "msm-pcm-routing",
  5025. .codec_name = "bolero_codec",
  5026. .codec_dai_name = "va_macro_tx2",
  5027. .no_pcm = 1,
  5028. .dpcm_capture = 1,
  5029. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5030. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5031. .ignore_suspend = 1,
  5032. .ops = &msm_cdc_dma_be_ops,
  5033. },
  5034. {
  5035. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5036. .stream_name = "VA CDC DMA2 Capture",
  5037. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  5038. .platform_name = "msm-pcm-routing",
  5039. .codec_name = "bolero_codec",
  5040. .codec_dai_name = "va_macro_tx3",
  5041. .no_pcm = 1,
  5042. .dpcm_capture = 1,
  5043. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5044. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5045. .ignore_suspend = 1,
  5046. .ops = &msm_cdc_dma_be_ops,
  5047. },
  5048. };
  5049. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5050. {
  5051. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5052. .stream_name = "AFE Loopback Capture",
  5053. .cpu_dai_name = "msm-dai-q6-dev.24577",
  5054. .platform_name = "msm-pcm-routing",
  5055. .codec_name = "msm-stub-codec.1",
  5056. .codec_dai_name = "msm-stub-tx",
  5057. .no_pcm = 1,
  5058. .dpcm_capture = 1,
  5059. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5060. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5061. .ignore_pmdown_time = 1,
  5062. .ignore_suspend = 1,
  5063. },
  5064. };
  5065. static struct snd_soc_dai_link msm_kona_dai_links[
  5066. ARRAY_SIZE(msm_common_dai_links) +
  5067. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  5068. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5069. ARRAY_SIZE(msm_common_be_dai_links) +
  5070. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5071. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5072. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  5073. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5074. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5075. ARRAY_SIZE(ext_disp_be_dai_link) +
  5076. ARRAY_SIZE(msm_wcn_be_dai_links) +
  5077. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link)];
  5078. static int msm_populate_dai_link_component_of_node(
  5079. struct snd_soc_card *card)
  5080. {
  5081. int i, index, ret = 0;
  5082. struct device *cdev = card->dev;
  5083. struct snd_soc_dai_link *dai_link = card->dai_link;
  5084. struct device_node *np;
  5085. if (!cdev) {
  5086. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5087. return -ENODEV;
  5088. }
  5089. for (i = 0; i < card->num_links; i++) {
  5090. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  5091. continue;
  5092. /* populate platform_of_node for snd card dai links */
  5093. if (dai_link[i].platform_name &&
  5094. !dai_link[i].platform_of_node) {
  5095. index = of_property_match_string(cdev->of_node,
  5096. "asoc-platform-names",
  5097. dai_link[i].platform_name);
  5098. if (index < 0) {
  5099. dev_err(cdev, "%s: No match found for platform name: %s\n",
  5100. __func__, dai_link[i].platform_name);
  5101. ret = index;
  5102. goto err;
  5103. }
  5104. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5105. index);
  5106. if (!np) {
  5107. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  5108. __func__, dai_link[i].platform_name,
  5109. index);
  5110. ret = -ENODEV;
  5111. goto err;
  5112. }
  5113. dai_link[i].platform_of_node = np;
  5114. dai_link[i].platform_name = NULL;
  5115. }
  5116. /* populate cpu_of_node for snd card dai links */
  5117. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  5118. index = of_property_match_string(cdev->of_node,
  5119. "asoc-cpu-names",
  5120. dai_link[i].cpu_dai_name);
  5121. if (index >= 0) {
  5122. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5123. index);
  5124. if (!np) {
  5125. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  5126. __func__,
  5127. dai_link[i].cpu_dai_name);
  5128. ret = -ENODEV;
  5129. goto err;
  5130. }
  5131. dai_link[i].cpu_of_node = np;
  5132. dai_link[i].cpu_dai_name = NULL;
  5133. }
  5134. }
  5135. /* populate codec_of_node for snd card dai links */
  5136. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  5137. index = of_property_match_string(cdev->of_node,
  5138. "asoc-codec-names",
  5139. dai_link[i].codec_name);
  5140. if (index < 0)
  5141. continue;
  5142. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  5143. index);
  5144. if (!np) {
  5145. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  5146. __func__, dai_link[i].codec_name);
  5147. ret = -ENODEV;
  5148. goto err;
  5149. }
  5150. dai_link[i].codec_of_node = np;
  5151. dai_link[i].codec_name = NULL;
  5152. }
  5153. }
  5154. err:
  5155. return ret;
  5156. }
  5157. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5158. {
  5159. int ret = -EINVAL;
  5160. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5161. if (!component) {
  5162. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  5163. return ret;
  5164. }
  5165. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5166. ARRAY_SIZE(msm_snd_controls));
  5167. if (ret < 0) {
  5168. dev_err(component->dev,
  5169. "%s: add_codec_controls failed, err = %d\n",
  5170. __func__, ret);
  5171. return ret;
  5172. }
  5173. return ret;
  5174. }
  5175. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5176. struct snd_pcm_hw_params *params)
  5177. {
  5178. return 0;
  5179. }
  5180. static struct snd_soc_ops msm_stub_be_ops = {
  5181. .hw_params = msm_snd_stub_hw_params,
  5182. };
  5183. struct snd_soc_card snd_soc_card_stub_msm = {
  5184. .name = "kona-stub-snd-card",
  5185. };
  5186. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5187. /* FrontEnd DAI Links */
  5188. {
  5189. .name = "MSMSTUB Media1",
  5190. .stream_name = "MultiMedia1",
  5191. .cpu_dai_name = "MultiMedia1",
  5192. .platform_name = "msm-pcm-dsp.0",
  5193. .dynamic = 1,
  5194. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5195. .dpcm_playback = 1,
  5196. .dpcm_capture = 1,
  5197. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5198. SND_SOC_DPCM_TRIGGER_POST},
  5199. .codec_dai_name = "snd-soc-dummy-dai",
  5200. .codec_name = "snd-soc-dummy",
  5201. .ignore_suspend = 1,
  5202. /* this dainlink has playback support */
  5203. .ignore_pmdown_time = 1,
  5204. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5205. },
  5206. };
  5207. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5208. /* Backend DAI Links */
  5209. {
  5210. .name = LPASS_BE_AUXPCM_RX,
  5211. .stream_name = "AUX PCM Playback",
  5212. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5213. .platform_name = "msm-pcm-routing",
  5214. .codec_name = "msm-stub-codec.1",
  5215. .codec_dai_name = "msm-stub-rx",
  5216. .no_pcm = 1,
  5217. .dpcm_playback = 1,
  5218. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5219. .init = &msm_audrx_stub_init,
  5220. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5221. .ignore_pmdown_time = 1,
  5222. .ignore_suspend = 1,
  5223. .ops = &msm_stub_be_ops,
  5224. },
  5225. {
  5226. .name = LPASS_BE_AUXPCM_TX,
  5227. .stream_name = "AUX PCM Capture",
  5228. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5229. .platform_name = "msm-pcm-routing",
  5230. .codec_name = "msm-stub-codec.1",
  5231. .codec_dai_name = "msm-stub-tx",
  5232. .no_pcm = 1,
  5233. .dpcm_capture = 1,
  5234. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5235. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5236. .ignore_suspend = 1,
  5237. .ops = &msm_stub_be_ops,
  5238. },
  5239. };
  5240. static struct snd_soc_dai_link msm_stub_dai_links[
  5241. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5242. ARRAY_SIZE(msm_stub_be_dai_links)];
  5243. static const struct of_device_id kona_asoc_machine_of_match[] = {
  5244. { .compatible = "qcom,kona-asoc-snd",
  5245. .data = "codec"},
  5246. { .compatible = "qcom,kona-asoc-snd-stub",
  5247. .data = "stub_codec"},
  5248. {},
  5249. };
  5250. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5251. {
  5252. struct snd_soc_card *card = NULL;
  5253. struct snd_soc_dai_link *dailink = NULL;
  5254. int len_1 = 0;
  5255. int len_2 = 0;
  5256. int total_links = 0;
  5257. int rc = 0;
  5258. u32 mi2s_audio_intf = 0;
  5259. u32 auxpcm_audio_intf = 0;
  5260. u32 val = 0;
  5261. const struct of_device_id *match;
  5262. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  5263. if (!match) {
  5264. dev_err(dev, "%s: No DT match found for sound card\n",
  5265. __func__);
  5266. return NULL;
  5267. }
  5268. if (!strcmp(match->data, "codec")) {
  5269. card = &snd_soc_card_kona_msm;
  5270. memcpy(msm_kona_dai_links + total_links,
  5271. msm_common_dai_links,
  5272. sizeof(msm_common_dai_links));
  5273. total_links += ARRAY_SIZE(msm_common_dai_links);
  5274. memcpy(msm_kona_dai_links + total_links,
  5275. msm_bolero_fe_dai_links,
  5276. sizeof(msm_bolero_fe_dai_links));
  5277. total_links +=
  5278. ARRAY_SIZE(msm_bolero_fe_dai_links);
  5279. memcpy(msm_kona_dai_links + total_links,
  5280. msm_common_misc_fe_dai_links,
  5281. sizeof(msm_common_misc_fe_dai_links));
  5282. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5283. memcpy(msm_kona_dai_links + total_links,
  5284. msm_common_be_dai_links,
  5285. sizeof(msm_common_be_dai_links));
  5286. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5287. memcpy(msm_kona_dai_links + total_links,
  5288. msm_wsa_cdc_dma_be_dai_links,
  5289. sizeof(msm_wsa_cdc_dma_be_dai_links));
  5290. total_links +=
  5291. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  5292. memcpy(msm_kona_dai_links + total_links,
  5293. msm_rx_tx_cdc_dma_be_dai_links,
  5294. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5295. total_links +=
  5296. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  5297. memcpy(msm_kona_dai_links + total_links,
  5298. msm_va_cdc_dma_be_dai_links,
  5299. sizeof(msm_va_cdc_dma_be_dai_links));
  5300. total_links +=
  5301. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5302. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5303. &mi2s_audio_intf);
  5304. if (rc) {
  5305. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5306. __func__);
  5307. } else {
  5308. if (mi2s_audio_intf) {
  5309. memcpy(msm_kona_dai_links + total_links,
  5310. msm_mi2s_be_dai_links,
  5311. sizeof(msm_mi2s_be_dai_links));
  5312. total_links +=
  5313. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5314. }
  5315. }
  5316. rc = of_property_read_u32(dev->of_node,
  5317. "qcom,auxpcm-audio-intf",
  5318. &auxpcm_audio_intf);
  5319. if (rc) {
  5320. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5321. __func__);
  5322. } else {
  5323. if (auxpcm_audio_intf) {
  5324. memcpy(msm_kona_dai_links + total_links,
  5325. msm_auxpcm_be_dai_links,
  5326. sizeof(msm_auxpcm_be_dai_links));
  5327. total_links +=
  5328. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5329. }
  5330. }
  5331. rc = of_property_read_u32(dev->of_node,
  5332. "qcom,ext-disp-audio-rx", &val);
  5333. if (!rc && val) {
  5334. dev_dbg(dev, "%s(): ext disp audio support present\n",
  5335. __func__);
  5336. memcpy(msm_kona_dai_links + total_links,
  5337. ext_disp_be_dai_link,
  5338. sizeof(ext_disp_be_dai_link));
  5339. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  5340. }
  5341. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  5342. if (!rc && val) {
  5343. dev_dbg(dev, "%s(): WCN BT support present\n",
  5344. __func__);
  5345. memcpy(msm_kona_dai_links + total_links,
  5346. msm_wcn_be_dai_links,
  5347. sizeof(msm_wcn_be_dai_links));
  5348. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  5349. }
  5350. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5351. &val);
  5352. if (!rc && val) {
  5353. memcpy(msm_kona_dai_links + total_links,
  5354. msm_afe_rxtx_lb_be_dai_link,
  5355. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5356. total_links +=
  5357. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5358. }
  5359. dailink = msm_kona_dai_links;
  5360. } else if(!strcmp(match->data, "stub_codec")) {
  5361. card = &snd_soc_card_stub_msm;
  5362. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5363. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5364. memcpy(msm_stub_dai_links,
  5365. msm_stub_fe_dai_links,
  5366. sizeof(msm_stub_fe_dai_links));
  5367. memcpy(msm_stub_dai_links + len_1,
  5368. msm_stub_be_dai_links,
  5369. sizeof(msm_stub_be_dai_links));
  5370. dailink = msm_stub_dai_links;
  5371. total_links = len_2;
  5372. }
  5373. if (card) {
  5374. card->dai_link = dailink;
  5375. card->num_links = total_links;
  5376. }
  5377. return card;
  5378. }
  5379. static int msm_wsa881x_init(struct snd_soc_component *component)
  5380. {
  5381. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  5382. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  5383. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  5384. SPKR_L_BOOST, SPKR_L_VI};
  5385. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  5386. SPKR_R_BOOST, SPKR_R_VI};
  5387. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  5388. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  5389. struct msm_asoc_mach_data *pdata;
  5390. struct snd_soc_dapm_context *dapm;
  5391. struct snd_card *card;
  5392. struct snd_info_entry *entry;
  5393. int ret = 0;
  5394. if (!component) {
  5395. pr_err("%s component is NULL\n", __func__);
  5396. return -EINVAL;
  5397. }
  5398. card = component->card->snd_card;
  5399. dapm = snd_soc_component_get_dapm(component);
  5400. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  5401. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  5402. __func__, component->name);
  5403. wsa881x_set_channel_map(component, &spkleft_ports[0],
  5404. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  5405. &ch_rate[0], &spkleft_port_types[0]);
  5406. if (dapm->component) {
  5407. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  5408. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  5409. }
  5410. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  5411. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  5412. __func__, component->name);
  5413. wsa881x_set_channel_map(component, &spkright_ports[0],
  5414. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  5415. &ch_rate[0], &spkright_port_types[0]);
  5416. if (dapm->component) {
  5417. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  5418. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  5419. }
  5420. } else {
  5421. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  5422. component->name);
  5423. ret = -EINVAL;
  5424. goto err;
  5425. }
  5426. pdata = snd_soc_card_get_drvdata(component->card);
  5427. if (!pdata->codec_root) {
  5428. entry = snd_info_create_subdir(card->module, "codecs",
  5429. card->proc_root);
  5430. if (!entry) {
  5431. pr_err("%s: Cannot create codecs module entry\n",
  5432. __func__);
  5433. ret = 0;
  5434. goto err;
  5435. }
  5436. pdata->codec_root = entry;
  5437. }
  5438. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  5439. component);
  5440. err:
  5441. return ret;
  5442. }
  5443. static int msm_aux_codec_init(struct snd_soc_component *component)
  5444. {
  5445. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  5446. int ret = 0;
  5447. void *mbhc_calibration;
  5448. struct snd_info_entry *entry;
  5449. struct snd_card *card = component->card->snd_card;
  5450. struct msm_asoc_mach_data *pdata;
  5451. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5452. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5453. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5454. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5455. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5456. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5457. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5458. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5459. snd_soc_dapm_sync(dapm);
  5460. pdata = snd_soc_card_get_drvdata(component->card);
  5461. if (!pdata->codec_root) {
  5462. entry = snd_info_create_subdir(card->module, "codecs",
  5463. card->proc_root);
  5464. if (!entry) {
  5465. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5466. __func__);
  5467. ret = 0;
  5468. goto mbhc_cfg_cal;
  5469. }
  5470. pdata->codec_root = entry;
  5471. }
  5472. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  5473. mbhc_cfg_cal:
  5474. mbhc_calibration = def_wcd_mbhc_cal();
  5475. if (!mbhc_calibration)
  5476. return -ENOMEM;
  5477. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5478. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5479. if (ret) {
  5480. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5481. __func__, ret);
  5482. goto err_hs_detect;
  5483. }
  5484. return 0;
  5485. err_hs_detect:
  5486. kfree(mbhc_calibration);
  5487. return ret;
  5488. }
  5489. static int msm_init_aux_dev(struct platform_device *pdev,
  5490. struct snd_soc_card *card)
  5491. {
  5492. struct device_node *wsa_of_node;
  5493. struct device_node *aux_codec_of_node;
  5494. u32 wsa_max_devs;
  5495. u32 wsa_dev_cnt;
  5496. u32 codec_aux_dev_cnt = 0;
  5497. int i;
  5498. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  5499. struct aux_codec_dev_info *aux_cdc_dev_info;
  5500. const char *auxdev_name_prefix[1];
  5501. char *dev_name_str = NULL;
  5502. int found = 0;
  5503. int codecs_found = 0;
  5504. int ret = 0;
  5505. /* Get maximum WSA device count for this platform */
  5506. ret = of_property_read_u32(pdev->dev.of_node,
  5507. "qcom,wsa-max-devs", &wsa_max_devs);
  5508. if (ret) {
  5509. dev_info(&pdev->dev,
  5510. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  5511. __func__, pdev->dev.of_node->full_name, ret);
  5512. wsa_max_devs = 0;
  5513. goto codec_aux_dev;
  5514. }
  5515. if (wsa_max_devs == 0) {
  5516. dev_warn(&pdev->dev,
  5517. "%s: Max WSA devices is 0 for this target?\n",
  5518. __func__);
  5519. goto codec_aux_dev;
  5520. }
  5521. /* Get count of WSA device phandles for this platform */
  5522. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  5523. "qcom,wsa-devs", NULL);
  5524. if (wsa_dev_cnt == -ENOENT) {
  5525. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  5526. __func__);
  5527. goto err;
  5528. } else if (wsa_dev_cnt <= 0) {
  5529. dev_err(&pdev->dev,
  5530. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  5531. __func__, wsa_dev_cnt);
  5532. ret = -EINVAL;
  5533. goto err;
  5534. }
  5535. /*
  5536. * Expect total phandles count to be NOT less than maximum possible
  5537. * WSA count. However, if it is less, then assign same value to
  5538. * max count as well.
  5539. */
  5540. if (wsa_dev_cnt < wsa_max_devs) {
  5541. dev_dbg(&pdev->dev,
  5542. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  5543. __func__, wsa_max_devs, wsa_dev_cnt);
  5544. wsa_max_devs = wsa_dev_cnt;
  5545. }
  5546. /* Make sure prefix string passed for each WSA device */
  5547. ret = of_property_count_strings(pdev->dev.of_node,
  5548. "qcom,wsa-aux-dev-prefix");
  5549. if (ret != wsa_dev_cnt) {
  5550. dev_err(&pdev->dev,
  5551. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  5552. __func__, wsa_dev_cnt, ret);
  5553. ret = -EINVAL;
  5554. goto err;
  5555. }
  5556. /*
  5557. * Alloc mem to store phandle and index info of WSA device, if already
  5558. * registered with ALSA core
  5559. */
  5560. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  5561. sizeof(struct msm_wsa881x_dev_info),
  5562. GFP_KERNEL);
  5563. if (!wsa881x_dev_info) {
  5564. ret = -ENOMEM;
  5565. goto err;
  5566. }
  5567. /*
  5568. * search and check whether all WSA devices are already
  5569. * registered with ALSA core or not. If found a node, store
  5570. * the node and the index in a local array of struct for later
  5571. * use.
  5572. */
  5573. for (i = 0; i < wsa_dev_cnt; i++) {
  5574. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  5575. "qcom,wsa-devs", i);
  5576. if (unlikely(!wsa_of_node)) {
  5577. /* we should not be here */
  5578. dev_err(&pdev->dev,
  5579. "%s: wsa dev node is not present\n",
  5580. __func__);
  5581. ret = -EINVAL;
  5582. goto err;
  5583. }
  5584. if (soc_find_component(wsa_of_node, NULL)) {
  5585. /* WSA device registered with ALSA core */
  5586. wsa881x_dev_info[found].of_node = wsa_of_node;
  5587. wsa881x_dev_info[found].index = i;
  5588. found++;
  5589. if (found == wsa_max_devs)
  5590. break;
  5591. }
  5592. }
  5593. if (found < wsa_max_devs) {
  5594. dev_dbg(&pdev->dev,
  5595. "%s: failed to find %d components. Found only %d\n",
  5596. __func__, wsa_max_devs, found);
  5597. return -EPROBE_DEFER;
  5598. }
  5599. dev_info(&pdev->dev,
  5600. "%s: found %d wsa881x devices registered with ALSA core\n",
  5601. __func__, found);
  5602. codec_aux_dev:
  5603. /* Get count of aux codec device phandles for this platform */
  5604. codec_aux_dev_cnt = of_count_phandle_with_args(
  5605. pdev->dev.of_node,
  5606. "qcom,codec-aux-devs", NULL);
  5607. if (codec_aux_dev_cnt == -ENOENT) {
  5608. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  5609. __func__);
  5610. goto err;
  5611. } else if (codec_aux_dev_cnt <= 0) {
  5612. dev_err(&pdev->dev,
  5613. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  5614. __func__, codec_aux_dev_cnt);
  5615. ret = -EINVAL;
  5616. goto err;
  5617. }
  5618. /*
  5619. * Alloc mem to store phandle and index info of aux codec
  5620. * if already registered with ALSA core
  5621. */
  5622. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  5623. sizeof(struct aux_codec_dev_info),
  5624. GFP_KERNEL);
  5625. if (!aux_cdc_dev_info) {
  5626. ret = -ENOMEM;
  5627. goto err;
  5628. }
  5629. /*
  5630. * search and check whether all aux codecs are already
  5631. * registered with ALSA core or not. If found a node, store
  5632. * the node and the index in a local array of struct for later
  5633. * use.
  5634. */
  5635. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5636. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  5637. "qcom,codec-aux-devs", i);
  5638. if (unlikely(!aux_codec_of_node)) {
  5639. /* we should not be here */
  5640. dev_err(&pdev->dev,
  5641. "%s: aux codec dev node is not present\n",
  5642. __func__);
  5643. ret = -EINVAL;
  5644. goto err;
  5645. }
  5646. if (soc_find_component(aux_codec_of_node, NULL)) {
  5647. /* AUX codec registered with ALSA core */
  5648. aux_cdc_dev_info[codecs_found].of_node =
  5649. aux_codec_of_node;
  5650. aux_cdc_dev_info[codecs_found].index = i;
  5651. codecs_found++;
  5652. }
  5653. }
  5654. if (codecs_found < codec_aux_dev_cnt) {
  5655. dev_dbg(&pdev->dev,
  5656. "%s: failed to find %d components. Found only %d\n",
  5657. __func__, codec_aux_dev_cnt, codecs_found);
  5658. return -EPROBE_DEFER;
  5659. }
  5660. dev_info(&pdev->dev,
  5661. "%s: found %d AUX codecs registered with ALSA core\n",
  5662. __func__, codecs_found);
  5663. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  5664. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  5665. /* Alloc array of AUX devs struct */
  5666. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  5667. sizeof(struct snd_soc_aux_dev),
  5668. GFP_KERNEL);
  5669. if (!msm_aux_dev) {
  5670. ret = -ENOMEM;
  5671. goto err;
  5672. }
  5673. /* Alloc array of codec conf struct */
  5674. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  5675. sizeof(struct snd_soc_codec_conf),
  5676. GFP_KERNEL);
  5677. if (!msm_codec_conf) {
  5678. ret = -ENOMEM;
  5679. goto err;
  5680. }
  5681. for (i = 0; i < wsa_max_devs; i++) {
  5682. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  5683. GFP_KERNEL);
  5684. if (!dev_name_str) {
  5685. ret = -ENOMEM;
  5686. goto err;
  5687. }
  5688. ret = of_property_read_string_index(pdev->dev.of_node,
  5689. "qcom,wsa-aux-dev-prefix",
  5690. wsa881x_dev_info[i].index,
  5691. auxdev_name_prefix);
  5692. if (ret) {
  5693. dev_err(&pdev->dev,
  5694. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  5695. __func__, ret);
  5696. ret = -EINVAL;
  5697. goto err;
  5698. }
  5699. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  5700. msm_aux_dev[i].name = dev_name_str;
  5701. msm_aux_dev[i].codec_name = NULL;
  5702. msm_aux_dev[i].codec_of_node =
  5703. wsa881x_dev_info[i].of_node;
  5704. msm_aux_dev[i].init = msm_wsa881x_init;
  5705. msm_codec_conf[i].dev_name = NULL;
  5706. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  5707. msm_codec_conf[i].of_node =
  5708. wsa881x_dev_info[i].of_node;
  5709. }
  5710. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5711. msm_aux_dev[wsa_max_devs + i].name = NULL;
  5712. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  5713. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  5714. aux_cdc_dev_info[i].of_node;
  5715. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  5716. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  5717. msm_codec_conf[wsa_max_devs + i].name_prefix =
  5718. NULL;
  5719. msm_codec_conf[wsa_max_devs + i].of_node =
  5720. aux_cdc_dev_info[i].of_node;
  5721. }
  5722. card->codec_conf = msm_codec_conf;
  5723. card->aux_dev = msm_aux_dev;
  5724. err:
  5725. return ret;
  5726. }
  5727. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5728. {
  5729. int count = 0;
  5730. u32 mi2s_master_slave[MI2S_MAX];
  5731. int ret = 0;
  5732. for (count = 0; count < MI2S_MAX; count++) {
  5733. mutex_init(&mi2s_intf_conf[count].lock);
  5734. mi2s_intf_conf[count].ref_cnt = 0;
  5735. }
  5736. ret = of_property_read_u32_array(pdev->dev.of_node,
  5737. "qcom,msm-mi2s-master",
  5738. mi2s_master_slave, MI2S_MAX);
  5739. if (ret) {
  5740. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5741. __func__);
  5742. } else {
  5743. for (count = 0; count < MI2S_MAX; count++) {
  5744. mi2s_intf_conf[count].msm_is_mi2s_master =
  5745. mi2s_master_slave[count];
  5746. }
  5747. }
  5748. }
  5749. static void msm_i2s_auxpcm_deinit(void)
  5750. {
  5751. int count = 0;
  5752. for (count = 0; count < MI2S_MAX; count++) {
  5753. mutex_destroy(&mi2s_intf_conf[count].lock);
  5754. mi2s_intf_conf[count].ref_cnt = 0;
  5755. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5756. }
  5757. }
  5758. static int kona_ssr_enable(struct device *dev, void *data)
  5759. {
  5760. struct platform_device *pdev = to_platform_device(dev);
  5761. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5762. int ret = 0;
  5763. if (!card) {
  5764. dev_err(dev, "%s: card is NULL\n", __func__);
  5765. ret = -EINVAL;
  5766. goto err;
  5767. }
  5768. if (!strcmp(card->name, "kona-stub-snd-card")) {
  5769. /* TODO */
  5770. dev_dbg(dev, "%s: TODO \n", __func__);
  5771. }
  5772. snd_soc_card_change_online_state(card, 1);
  5773. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5774. err:
  5775. return ret;
  5776. }
  5777. static void kona_ssr_disable(struct device *dev, void *data)
  5778. {
  5779. struct platform_device *pdev = to_platform_device(dev);
  5780. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5781. if (!card) {
  5782. dev_err(dev, "%s: card is NULL\n", __func__);
  5783. return;
  5784. }
  5785. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5786. snd_soc_card_change_online_state(card, 0);
  5787. if (!strcmp(card->name, "kona-stub-snd-card")) {
  5788. /* TODO */
  5789. dev_dbg(dev, "%s: TODO \n", __func__);
  5790. }
  5791. }
  5792. static const struct snd_event_ops kona_ssr_ops = {
  5793. .enable = kona_ssr_enable,
  5794. .disable = kona_ssr_disable,
  5795. };
  5796. static int msm_audio_ssr_compare(struct device *dev, void *data)
  5797. {
  5798. struct device_node *node = data;
  5799. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  5800. __func__, dev->of_node, node);
  5801. return (dev->of_node && dev->of_node == node);
  5802. }
  5803. static int msm_audio_ssr_register(struct device *dev)
  5804. {
  5805. struct device_node *np = dev->of_node;
  5806. struct snd_event_clients *ssr_clients = NULL;
  5807. struct device_node *node = NULL;
  5808. int ret = 0;
  5809. int i = 0;
  5810. for (i = 0; ; i++) {
  5811. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  5812. if (!node)
  5813. break;
  5814. snd_event_mstr_add_client(&ssr_clients,
  5815. msm_audio_ssr_compare, node);
  5816. }
  5817. ret = snd_event_master_register(dev, &kona_ssr_ops,
  5818. ssr_clients, NULL);
  5819. if (!ret)
  5820. snd_event_notify(dev, SND_EVENT_UP);
  5821. return ret;
  5822. }
  5823. static int msm_asoc_machine_probe(struct platform_device *pdev)
  5824. {
  5825. struct snd_soc_card *card = NULL;
  5826. struct msm_asoc_mach_data *pdata = NULL;
  5827. const char *mbhc_audio_jack_type = NULL;
  5828. int ret = 0;
  5829. if (!pdev->dev.of_node) {
  5830. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  5831. return -EINVAL;
  5832. }
  5833. pdata = devm_kzalloc(&pdev->dev,
  5834. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  5835. if (!pdata)
  5836. return -ENOMEM;
  5837. card = populate_snd_card_dailinks(&pdev->dev);
  5838. if (!card) {
  5839. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  5840. ret = -EINVAL;
  5841. goto err;
  5842. }
  5843. card->dev = &pdev->dev;
  5844. platform_set_drvdata(pdev, card);
  5845. snd_soc_card_set_drvdata(card, pdata);
  5846. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  5847. if (ret) {
  5848. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  5849. __func__, ret);
  5850. goto err;
  5851. }
  5852. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  5853. if (ret) {
  5854. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  5855. __func__, ret);
  5856. goto err;
  5857. }
  5858. ret = msm_populate_dai_link_component_of_node(card);
  5859. if (ret) {
  5860. ret = -EPROBE_DEFER;
  5861. goto err;
  5862. }
  5863. ret = msm_init_aux_dev(pdev, card);
  5864. if (ret)
  5865. goto err;
  5866. ret = devm_snd_soc_register_card(&pdev->dev, card);
  5867. if (ret == -EPROBE_DEFER) {
  5868. if (codec_reg_done)
  5869. ret = -EINVAL;
  5870. goto err;
  5871. } else if (ret) {
  5872. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  5873. __func__, ret);
  5874. goto err;
  5875. }
  5876. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  5877. __func__, card->name);
  5878. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5879. "qcom,hph-en1-gpio", 0);
  5880. if (!pdata->hph_en1_gpio_p) {
  5881. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  5882. __func__, "qcom,hph-en1-gpio",
  5883. pdev->dev.of_node->full_name);
  5884. }
  5885. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5886. "qcom,hph-en0-gpio", 0);
  5887. if (!pdata->hph_en0_gpio_p) {
  5888. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  5889. __func__, "qcom,hph-en0-gpio",
  5890. pdev->dev.of_node->full_name);
  5891. }
  5892. ret = of_property_read_string(pdev->dev.of_node,
  5893. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  5894. if (ret) {
  5895. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  5896. __func__, "qcom,mbhc-audio-jack-type",
  5897. pdev->dev.of_node->full_name);
  5898. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  5899. } else {
  5900. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  5901. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  5902. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  5903. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  5904. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  5905. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  5906. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  5907. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  5908. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  5909. } else {
  5910. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  5911. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  5912. }
  5913. }
  5914. /*
  5915. * Parse US-Euro gpio info from DT. Report no error if us-euro
  5916. * entry is not found in DT file as some targets do not support
  5917. * US-Euro detection
  5918. */
  5919. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5920. "qcom,us-euro-gpios", 0);
  5921. if (!pdata->us_euro_gpio_p) {
  5922. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  5923. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  5924. } else {
  5925. dev_dbg(&pdev->dev, "%s detected\n",
  5926. "qcom,us-euro-gpios");
  5927. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  5928. }
  5929. if (wcd_mbhc_cfg.enable_usbc_analog)
  5930. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  5931. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  5932. "fsa4480-i2c-handle", 0);
  5933. if (!pdata->fsa_handle)
  5934. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  5935. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  5936. msm_i2s_auxpcm_init(pdev);
  5937. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5938. "qcom,cdc-dmic01-gpios",
  5939. 0);
  5940. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5941. "qcom,cdc-dmic23-gpios",
  5942. 0);
  5943. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5944. "qcom,cdc-dmic45-gpios",
  5945. 0);
  5946. ret = msm_audio_ssr_register(&pdev->dev);
  5947. if (ret)
  5948. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  5949. __func__, ret);
  5950. is_initial_boot = true;
  5951. return 0;
  5952. err:
  5953. devm_kfree(&pdev->dev, pdata);
  5954. return ret;
  5955. }
  5956. static int msm_asoc_machine_remove(struct platform_device *pdev)
  5957. {
  5958. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5959. snd_event_master_deregister(&pdev->dev);
  5960. snd_soc_unregister_card(card);
  5961. msm_i2s_auxpcm_deinit();
  5962. return 0;
  5963. }
  5964. static struct platform_driver kona_asoc_machine_driver = {
  5965. .driver = {
  5966. .name = DRV_NAME,
  5967. .owner = THIS_MODULE,
  5968. .pm = &snd_soc_pm_ops,
  5969. .of_match_table = kona_asoc_machine_of_match,
  5970. },
  5971. .probe = msm_asoc_machine_probe,
  5972. .remove = msm_asoc_machine_remove,
  5973. };
  5974. module_platform_driver(kona_asoc_machine_driver);
  5975. MODULE_DESCRIPTION("ALSA SoC msm");
  5976. MODULE_LICENSE("GPL v2");
  5977. MODULE_ALIAS("platform:" DRV_NAME);
  5978. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);