dp_catalog.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/iopoll.h>
  7. #include "dp_catalog.h"
  8. #include "dp_reg.h"
  9. #include "dp_debug.h"
  10. #define DP_GET_MSB(x) (x >> 8)
  11. #define DP_GET_LSB(x) (x & 0xff)
  12. #define DP_PHY_READY BIT(1)
  13. #define dp_catalog_get_priv(x) ({ \
  14. struct dp_catalog *dp_catalog; \
  15. dp_catalog = container_of(x, struct dp_catalog, x); \
  16. container_of(dp_catalog, struct dp_catalog_private, \
  17. dp_catalog); \
  18. })
  19. #define DP_INTERRUPT_STATUS1 \
  20. (DP_INTR_AUX_I2C_DONE| \
  21. DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
  22. DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
  23. DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
  24. DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
  25. #define DP_INTR_MASK1 (DP_INTERRUPT_STATUS1 << 2)
  26. #define DP_INTERRUPT_STATUS2 \
  27. (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
  28. DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
  29. #define DP_INTR_MASK2 (DP_INTERRUPT_STATUS2 << 2)
  30. #define DP_INTERRUPT_STATUS5 \
  31. (DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
  32. #define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
  33. #define dp_catalog_fill_io(x) { \
  34. catalog->io.x = parser->get_io(parser, #x); \
  35. }
  36. #define dp_catalog_fill_io_buf(x) { \
  37. parser->get_io_buf(parser, #x); \
  38. }
  39. #define dp_read(x) ({ \
  40. catalog->read(catalog, io_data, x); \
  41. })
  42. #define dp_write(x, y) ({ \
  43. catalog->write(catalog, io_data, x, y); \
  44. })
  45. static u8 const vm_pre_emphasis[4][4] = {
  46. {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */
  47. {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */
  48. {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
  49. {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
  50. };
  51. /* voltage swing, 0.2v and 1.0v are not support */
  52. static u8 const vm_voltage_swing[4][4] = {
  53. {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */
  54. {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
  55. {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
  56. {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
  57. };
  58. enum dp_flush_bit {
  59. DP_PPS_FLUSH,
  60. DP_DHDR_FLUSH,
  61. };
  62. /* audio related catalog functions */
  63. struct dp_catalog_private {
  64. struct device *dev;
  65. struct dp_catalog_io io;
  66. struct dp_parser *parser;
  67. u32 (*read)(struct dp_catalog_private *catalog,
  68. struct dp_io_data *io_data, u32 offset);
  69. void (*write)(struct dp_catalog_private *catlog,
  70. struct dp_io_data *io_data, u32 offset, u32 data);
  71. u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
  72. struct dp_catalog dp_catalog;
  73. char exe_mode[SZ_4];
  74. };
  75. static u32 dp_read_sw(struct dp_catalog_private *catalog,
  76. struct dp_io_data *io_data, u32 offset)
  77. {
  78. u32 data = 0;
  79. if (io_data->buf)
  80. memcpy(&data, io_data->buf + offset, sizeof(offset));
  81. return data;
  82. }
  83. static void dp_write_sw(struct dp_catalog_private *catalog,
  84. struct dp_io_data *io_data, u32 offset, u32 data)
  85. {
  86. if (io_data->buf)
  87. memcpy(io_data->buf + offset, &data, sizeof(data));
  88. }
  89. static u32 dp_read_hw(struct dp_catalog_private *catalog,
  90. struct dp_io_data *io_data, u32 offset)
  91. {
  92. u32 data = 0;
  93. data = readl_relaxed(io_data->io.base + offset);
  94. return data;
  95. }
  96. static void dp_write_hw(struct dp_catalog_private *catalog,
  97. struct dp_io_data *io_data, u32 offset, u32 data)
  98. {
  99. writel_relaxed(data, io_data->io.base + offset);
  100. }
  101. static u32 dp_read_sub_sw(struct dp_catalog *dp_catalog,
  102. struct dp_io_data *io_data, u32 offset)
  103. {
  104. struct dp_catalog_private *catalog = container_of(dp_catalog,
  105. struct dp_catalog_private, dp_catalog);
  106. return dp_read_sw(catalog, io_data, offset);
  107. }
  108. static void dp_write_sub_sw(struct dp_catalog *dp_catalog,
  109. struct dp_io_data *io_data, u32 offset, u32 data)
  110. {
  111. struct dp_catalog_private *catalog = container_of(dp_catalog,
  112. struct dp_catalog_private, dp_catalog);
  113. dp_write_sw(catalog, io_data, offset, data);
  114. }
  115. static u32 dp_read_sub_hw(struct dp_catalog *dp_catalog,
  116. struct dp_io_data *io_data, u32 offset)
  117. {
  118. struct dp_catalog_private *catalog = container_of(dp_catalog,
  119. struct dp_catalog_private, dp_catalog);
  120. return dp_read_hw(catalog, io_data, offset);
  121. }
  122. static void dp_write_sub_hw(struct dp_catalog *dp_catalog,
  123. struct dp_io_data *io_data, u32 offset, u32 data)
  124. {
  125. struct dp_catalog_private *catalog = container_of(dp_catalog,
  126. struct dp_catalog_private, dp_catalog);
  127. dp_write_hw(catalog, io_data, offset, data);
  128. }
  129. /* aux related catalog functions */
  130. static u32 dp_catalog_aux_read_data(struct dp_catalog_aux *aux)
  131. {
  132. struct dp_catalog_private *catalog;
  133. struct dp_io_data *io_data;
  134. if (!aux) {
  135. DP_ERR("invalid input\n");
  136. goto end;
  137. }
  138. catalog = dp_catalog_get_priv(aux);
  139. io_data = catalog->io.dp_aux;
  140. return dp_read(DP_AUX_DATA);
  141. end:
  142. return 0;
  143. }
  144. static int dp_catalog_aux_write_data(struct dp_catalog_aux *aux)
  145. {
  146. int rc = 0;
  147. struct dp_catalog_private *catalog;
  148. struct dp_io_data *io_data;
  149. if (!aux) {
  150. DP_ERR("invalid input\n");
  151. rc = -EINVAL;
  152. goto end;
  153. }
  154. catalog = dp_catalog_get_priv(aux);
  155. io_data = catalog->io.dp_aux;
  156. dp_write(DP_AUX_DATA, aux->data);
  157. end:
  158. return rc;
  159. }
  160. static int dp_catalog_aux_write_trans(struct dp_catalog_aux *aux)
  161. {
  162. int rc = 0;
  163. struct dp_catalog_private *catalog;
  164. struct dp_io_data *io_data;
  165. if (!aux) {
  166. DP_ERR("invalid input\n");
  167. rc = -EINVAL;
  168. goto end;
  169. }
  170. catalog = dp_catalog_get_priv(aux);
  171. io_data = catalog->io.dp_aux;
  172. dp_write(DP_AUX_TRANS_CTRL, aux->data);
  173. end:
  174. return rc;
  175. }
  176. static int dp_catalog_aux_clear_trans(struct dp_catalog_aux *aux, bool read)
  177. {
  178. int rc = 0;
  179. u32 data = 0;
  180. struct dp_catalog_private *catalog;
  181. struct dp_io_data *io_data;
  182. if (!aux) {
  183. DP_ERR("invalid input\n");
  184. rc = -EINVAL;
  185. goto end;
  186. }
  187. catalog = dp_catalog_get_priv(aux);
  188. io_data = catalog->io.dp_aux;
  189. if (read) {
  190. data = dp_read(DP_AUX_TRANS_CTRL);
  191. data &= ~BIT(9);
  192. dp_write(DP_AUX_TRANS_CTRL, data);
  193. } else {
  194. dp_write(DP_AUX_TRANS_CTRL, 0);
  195. }
  196. end:
  197. return rc;
  198. }
  199. static void dp_catalog_aux_clear_hw_interrupts(struct dp_catalog_aux *aux)
  200. {
  201. struct dp_catalog_private *catalog;
  202. struct dp_io_data *io_data;
  203. u32 data = 0;
  204. if (!aux) {
  205. DP_ERR("invalid input\n");
  206. return;
  207. }
  208. catalog = dp_catalog_get_priv(aux);
  209. io_data = catalog->io.dp_phy;
  210. data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS);
  211. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
  212. wmb(); /* make sure 0x1f is written before next write */
  213. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
  214. wmb(); /* make sure 0x9f is written before next write */
  215. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0);
  216. wmb(); /* make sure register is cleared */
  217. }
  218. static void dp_catalog_aux_reset(struct dp_catalog_aux *aux)
  219. {
  220. u32 aux_ctrl;
  221. struct dp_catalog_private *catalog;
  222. struct dp_io_data *io_data;
  223. if (!aux) {
  224. DP_ERR("invalid input\n");
  225. return;
  226. }
  227. catalog = dp_catalog_get_priv(aux);
  228. io_data = catalog->io.dp_aux;
  229. aux_ctrl = dp_read(DP_AUX_CTRL);
  230. aux_ctrl |= BIT(1);
  231. dp_write(DP_AUX_CTRL, aux_ctrl);
  232. usleep_range(1000, 1010); /* h/w recommended delay */
  233. aux_ctrl &= ~BIT(1);
  234. dp_write(DP_AUX_CTRL, aux_ctrl);
  235. wmb(); /* make sure AUX reset is done here */
  236. }
  237. static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable)
  238. {
  239. u32 aux_ctrl;
  240. struct dp_catalog_private *catalog;
  241. struct dp_io_data *io_data;
  242. if (!aux) {
  243. DP_ERR("invalid input\n");
  244. return;
  245. }
  246. catalog = dp_catalog_get_priv(aux);
  247. io_data = catalog->io.dp_aux;
  248. aux_ctrl = dp_read(DP_AUX_CTRL);
  249. if (enable) {
  250. aux_ctrl |= BIT(0);
  251. dp_write(DP_AUX_CTRL, aux_ctrl);
  252. wmb(); /* make sure AUX module is enabled */
  253. dp_write(DP_TIMEOUT_COUNT, 0xffff);
  254. dp_write(DP_AUX_LIMITS, 0xffff);
  255. } else {
  256. aux_ctrl &= ~BIT(0);
  257. dp_write(DP_AUX_CTRL, aux_ctrl);
  258. }
  259. }
  260. static void dp_catalog_aux_update_cfg(struct dp_catalog_aux *aux,
  261. struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
  262. {
  263. struct dp_catalog_private *catalog;
  264. u32 new_index = 0, current_index = 0;
  265. struct dp_io_data *io_data;
  266. if (!aux || !cfg || (type >= PHY_AUX_CFG_MAX)) {
  267. DP_ERR("invalid input\n");
  268. return;
  269. }
  270. catalog = dp_catalog_get_priv(aux);
  271. io_data = catalog->io.dp_phy;
  272. current_index = cfg[type].current_index;
  273. new_index = (current_index + 1) % cfg[type].cfg_cnt;
  274. DP_DEBUG("Updating %s from 0x%08x to 0x%08x\n",
  275. dp_phy_aux_config_type_to_string(type),
  276. cfg[type].lut[current_index], cfg[type].lut[new_index]);
  277. dp_write(cfg[type].offset, cfg[type].lut[new_index]);
  278. cfg[type].current_index = new_index;
  279. }
  280. static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,
  281. struct dp_aux_cfg *cfg)
  282. {
  283. struct dp_catalog_private *catalog;
  284. struct dp_io_data *io_data;
  285. int i = 0;
  286. if (!aux || !cfg) {
  287. DP_ERR("invalid input\n");
  288. return;
  289. }
  290. catalog = dp_catalog_get_priv(aux);
  291. io_data = catalog->io.dp_phy;
  292. dp_write(DP_PHY_PD_CTL, 0x65);
  293. wmb(); /* make sure PD programming happened */
  294. /* Turn on BIAS current for PHY/PLL */
  295. io_data = catalog->io.dp_pll;
  296. dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1b);
  297. io_data = catalog->io.dp_phy;
  298. dp_write(DP_PHY_PD_CTL, 0x02);
  299. wmb(); /* make sure PD programming happened */
  300. dp_write(DP_PHY_PD_CTL, 0x7d);
  301. /* Turn on BIAS current for PHY/PLL */
  302. io_data = catalog->io.dp_pll;
  303. dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f);
  304. /* DP AUX CFG register programming */
  305. io_data = catalog->io.dp_phy;
  306. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  307. dp_write(cfg[i].offset, cfg[i].lut[cfg[i].current_index]);
  308. dp_write(DP_PHY_AUX_INTERRUPT_MASK, 0x1F);
  309. wmb(); /* make sure AUX configuration is done before enabling it */
  310. }
  311. static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
  312. {
  313. u32 ack;
  314. struct dp_catalog_private *catalog;
  315. struct dp_io_data *io_data;
  316. if (!aux) {
  317. DP_ERR("invalid input\n");
  318. return;
  319. }
  320. catalog = dp_catalog_get_priv(aux);
  321. io_data = catalog->io.dp_ahb;
  322. aux->isr = dp_read(DP_INTR_STATUS);
  323. aux->isr &= ~DP_INTR_MASK1;
  324. ack = aux->isr & DP_INTERRUPT_STATUS1;
  325. ack <<= 1;
  326. ack |= DP_INTR_MASK1;
  327. dp_write(DP_INTR_STATUS, ack);
  328. }
  329. static bool dp_catalog_ctrl_wait_for_phy_ready(
  330. struct dp_catalog_private *catalog)
  331. {
  332. u32 reg = DP_PHY_STATUS, state;
  333. void __iomem *base = catalog->io.dp_phy->io.base;
  334. bool success = true;
  335. u32 const poll_sleep_us = 500;
  336. u32 const pll_timeout_us = 10000;
  337. if (readl_poll_timeout_atomic((base + reg), state,
  338. ((state & DP_PHY_READY) > 0),
  339. poll_sleep_us, pll_timeout_us)) {
  340. DP_ERR("PHY status failed, status=%x\n", state);
  341. success = false;
  342. }
  343. return success;
  344. }
  345. /* controller related catalog functions */
  346. static int dp_catalog_ctrl_late_phy_init(struct dp_catalog_ctrl *ctrl,
  347. u8 lane_cnt, bool flipped)
  348. {
  349. int rc = 0;
  350. u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
  351. struct dp_catalog_private *catalog;
  352. struct dp_io_data *io_data;
  353. if (!ctrl) {
  354. DP_ERR("invalid input\n");
  355. return -EINVAL;
  356. }
  357. catalog = dp_catalog_get_priv(ctrl);
  358. switch (lane_cnt) {
  359. case 1:
  360. drvr0_en = flipped ? 0x13 : 0x10;
  361. bias0_en = flipped ? 0x3E : 0x15;
  362. drvr1_en = flipped ? 0x10 : 0x13;
  363. bias1_en = flipped ? 0x15 : 0x3E;
  364. break;
  365. case 2:
  366. drvr0_en = flipped ? 0x10 : 0x10;
  367. bias0_en = flipped ? 0x3F : 0x15;
  368. drvr1_en = flipped ? 0x10 : 0x10;
  369. bias1_en = flipped ? 0x15 : 0x3F;
  370. break;
  371. case 4:
  372. default:
  373. drvr0_en = 0x10;
  374. bias0_en = 0x3F;
  375. drvr1_en = 0x10;
  376. bias1_en = 0x3F;
  377. break;
  378. }
  379. io_data = catalog->io.dp_ln_tx0;
  380. dp_write(TXn_HIGHZ_DRVR_EN_V420, drvr0_en);
  381. dp_write(TXn_TRANSCEIVER_BIAS_EN_V420, bias0_en);
  382. io_data = catalog->io.dp_ln_tx1;
  383. dp_write(TXn_HIGHZ_DRVR_EN_V420, drvr1_en);
  384. dp_write(TXn_TRANSCEIVER_BIAS_EN_V420, bias1_en);
  385. io_data = catalog->io.dp_phy;
  386. dp_write(DP_PHY_CFG, 0x18);
  387. /* add hardware recommended delay */
  388. udelay(2000);
  389. dp_write(DP_PHY_CFG, 0x19);
  390. /*
  391. * Make sure all the register writes are completed before
  392. * doing any other operation
  393. */
  394. wmb();
  395. if (!dp_catalog_ctrl_wait_for_phy_ready(catalog)) {
  396. rc = -EINVAL;
  397. goto lock_err;
  398. }
  399. io_data = catalog->io.dp_ln_tx0;
  400. dp_write(TXn_TX_POL_INV_V420, 0x0a);
  401. io_data = catalog->io.dp_ln_tx1;
  402. dp_write(TXn_TX_POL_INV_V420, 0x0a);
  403. io_data = catalog->io.dp_ln_tx0;
  404. dp_write(TXn_TX_DRV_LVL_V420, 0x27);
  405. io_data = catalog->io.dp_ln_tx1;
  406. dp_write(TXn_TX_DRV_LVL_V420, 0x27);
  407. io_data = catalog->io.dp_ln_tx0;
  408. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  409. io_data = catalog->io.dp_ln_tx1;
  410. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  411. /* Make sure the PHY register writes are done */
  412. wmb();
  413. lock_err:
  414. return rc;
  415. }
  416. static u32 dp_catalog_ctrl_read_hdcp_status(struct dp_catalog_ctrl *ctrl)
  417. {
  418. struct dp_catalog_private *catalog;
  419. struct dp_io_data *io_data;
  420. if (!ctrl) {
  421. DP_ERR("invalid input\n");
  422. return -EINVAL;
  423. }
  424. catalog = dp_catalog_get_priv(ctrl);
  425. io_data = catalog->io.dp_ahb;
  426. return dp_read(DP_HDCP_STATUS);
  427. }
  428. static void dp_catalog_panel_sdp_update(struct dp_catalog_panel *panel)
  429. {
  430. struct dp_catalog_private *catalog;
  431. struct dp_io_data *io_data;
  432. u32 sdp_cfg3_off = 0;
  433. if (panel->stream_id >= DP_STREAM_MAX) {
  434. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  435. return;
  436. }
  437. if (panel->stream_id == DP_STREAM_1)
  438. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  439. catalog = dp_catalog_get_priv(panel);
  440. io_data = catalog->io.dp_link;
  441. dp_write(MMSS_DP_SDP_CFG3 + sdp_cfg3_off, 0x01);
  442. dp_write(MMSS_DP_SDP_CFG3 + sdp_cfg3_off, 0x00);
  443. }
  444. static void dp_catalog_panel_setup_vsif_infoframe_sdp(
  445. struct dp_catalog_panel *panel)
  446. {
  447. struct dp_catalog_private *catalog;
  448. struct drm_msm_ext_hdr_metadata *hdr;
  449. struct dp_io_data *io_data;
  450. u32 header, parity, data, mst_offset = 0;
  451. u8 buf[SZ_64], off = 0;
  452. if (panel->stream_id >= DP_STREAM_MAX) {
  453. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  454. return;
  455. }
  456. if (panel->stream_id == DP_STREAM_1)
  457. mst_offset = MMSS_DP1_VSCEXT_0 - MMSS_DP_VSCEXT_0;
  458. catalog = dp_catalog_get_priv(panel);
  459. hdr = &panel->hdr_meta;
  460. io_data = catalog->io.dp_link;
  461. /* HEADER BYTE 1 */
  462. header = panel->dhdr_vsif_sdp.HB1;
  463. parity = dp_header_get_parity(header);
  464. data = ((header << HEADER_BYTE_1_BIT)
  465. | (parity << PARITY_BYTE_1_BIT));
  466. dp_write(MMSS_DP_VSCEXT_0 + mst_offset, data);
  467. memcpy(buf + off, &data, sizeof(data));
  468. off += sizeof(data);
  469. /* HEADER BYTE 2 */
  470. header = panel->dhdr_vsif_sdp.HB2;
  471. parity = dp_header_get_parity(header);
  472. data = ((header << HEADER_BYTE_2_BIT)
  473. | (parity << PARITY_BYTE_2_BIT));
  474. dp_write(MMSS_DP_VSCEXT_1 + mst_offset, data);
  475. /* HEADER BYTE 3 */
  476. header = panel->dhdr_vsif_sdp.HB3;
  477. parity = dp_header_get_parity(header);
  478. data = ((header << HEADER_BYTE_3_BIT)
  479. | (parity << PARITY_BYTE_3_BIT));
  480. data |= dp_read(MMSS_DP_VSCEXT_1 + mst_offset);
  481. dp_write(MMSS_DP_VSCEXT_1 + mst_offset, data);
  482. memcpy(buf + off, &data, sizeof(data));
  483. off += sizeof(data);
  484. print_hex_dump(KERN_DEBUG, "[drm-dp] VSCEXT: ",
  485. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  486. }
  487. static void dp_catalog_panel_setup_hdr_infoframe_sdp(
  488. struct dp_catalog_panel *panel)
  489. {
  490. struct dp_catalog_private *catalog;
  491. struct drm_msm_ext_hdr_metadata *hdr;
  492. struct dp_io_data *io_data;
  493. u32 header, parity, data, mst_offset = 0;
  494. u8 buf[SZ_64], off = 0;
  495. u32 const version = 0x01;
  496. u32 const length = 0x1a;
  497. if (panel->stream_id >= DP_STREAM_MAX) {
  498. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  499. return;
  500. }
  501. if (panel->stream_id == DP_STREAM_1)
  502. mst_offset = MMSS_DP1_GENERIC2_0 - MMSS_DP_GENERIC2_0;
  503. catalog = dp_catalog_get_priv(panel);
  504. hdr = &panel->hdr_meta;
  505. io_data = catalog->io.dp_link;
  506. /* HEADER BYTE 1 */
  507. header = panel->shdr_if_sdp.HB1;
  508. parity = dp_header_get_parity(header);
  509. data = ((header << HEADER_BYTE_1_BIT)
  510. | (parity << PARITY_BYTE_1_BIT));
  511. dp_write(MMSS_DP_GENERIC2_0 + mst_offset,
  512. data);
  513. memcpy(buf + off, &data, sizeof(data));
  514. off += sizeof(data);
  515. /* HEADER BYTE 2 */
  516. header = panel->shdr_if_sdp.HB2;
  517. parity = dp_header_get_parity(header);
  518. data = ((header << HEADER_BYTE_2_BIT)
  519. | (parity << PARITY_BYTE_2_BIT));
  520. dp_write(MMSS_DP_GENERIC2_1 + mst_offset, data);
  521. /* HEADER BYTE 3 */
  522. header = panel->shdr_if_sdp.HB3;
  523. parity = dp_header_get_parity(header);
  524. data = ((header << HEADER_BYTE_3_BIT)
  525. | (parity << PARITY_BYTE_3_BIT));
  526. data |= dp_read(MMSS_DP_VSCEXT_1 + mst_offset);
  527. dp_write(MMSS_DP_GENERIC2_1 + mst_offset,
  528. data);
  529. memcpy(buf + off, &data, sizeof(data));
  530. off += sizeof(data);
  531. data = version;
  532. data |= length << 8;
  533. data |= hdr->eotf << 16;
  534. dp_write(MMSS_DP_GENERIC2_2 + mst_offset, data);
  535. memcpy(buf + off, &data, sizeof(data));
  536. off += sizeof(data);
  537. data = (DP_GET_LSB(hdr->display_primaries_x[0]) |
  538. (DP_GET_MSB(hdr->display_primaries_x[0]) << 8) |
  539. (DP_GET_LSB(hdr->display_primaries_y[0]) << 16) |
  540. (DP_GET_MSB(hdr->display_primaries_y[0]) << 24));
  541. dp_write(MMSS_DP_GENERIC2_3 + mst_offset, data);
  542. memcpy(buf + off, &data, sizeof(data));
  543. off += sizeof(data);
  544. data = (DP_GET_LSB(hdr->display_primaries_x[1]) |
  545. (DP_GET_MSB(hdr->display_primaries_x[1]) << 8) |
  546. (DP_GET_LSB(hdr->display_primaries_y[1]) << 16) |
  547. (DP_GET_MSB(hdr->display_primaries_y[1]) << 24));
  548. dp_write(MMSS_DP_GENERIC2_4 + mst_offset, data);
  549. memcpy(buf + off, &data, sizeof(data));
  550. off += sizeof(data);
  551. data = (DP_GET_LSB(hdr->display_primaries_x[2]) |
  552. (DP_GET_MSB(hdr->display_primaries_x[2]) << 8) |
  553. (DP_GET_LSB(hdr->display_primaries_y[2]) << 16) |
  554. (DP_GET_MSB(hdr->display_primaries_y[2]) << 24));
  555. dp_write(MMSS_DP_GENERIC2_5 + mst_offset, data);
  556. memcpy(buf + off, &data, sizeof(data));
  557. off += sizeof(data);
  558. data = (DP_GET_LSB(hdr->white_point_x) |
  559. (DP_GET_MSB(hdr->white_point_x) << 8) |
  560. (DP_GET_LSB(hdr->white_point_y) << 16) |
  561. (DP_GET_MSB(hdr->white_point_y) << 24));
  562. dp_write(MMSS_DP_GENERIC2_6 + mst_offset, data);
  563. memcpy(buf + off, &data, sizeof(data));
  564. off += sizeof(data);
  565. data = (DP_GET_LSB(hdr->max_luminance) |
  566. (DP_GET_MSB(hdr->max_luminance) << 8) |
  567. (DP_GET_LSB(hdr->min_luminance) << 16) |
  568. (DP_GET_MSB(hdr->min_luminance) << 24));
  569. dp_write(MMSS_DP_GENERIC2_7 + mst_offset, data);
  570. memcpy(buf + off, &data, sizeof(data));
  571. off += sizeof(data);
  572. data = (DP_GET_LSB(hdr->max_content_light_level) |
  573. (DP_GET_MSB(hdr->max_content_light_level) << 8) |
  574. (DP_GET_LSB(hdr->max_average_light_level) << 16) |
  575. (DP_GET_MSB(hdr->max_average_light_level) << 24));
  576. dp_write(MMSS_DP_GENERIC2_8 + mst_offset, data);
  577. memcpy(buf + off, &data, sizeof(data));
  578. off += sizeof(data);
  579. data = 0;
  580. dp_write(MMSS_DP_GENERIC2_9 + mst_offset, data);
  581. memcpy(buf + off, &data, sizeof(data));
  582. off += sizeof(data);
  583. print_hex_dump(KERN_DEBUG, "[drm-dp] HDR: ",
  584. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  585. }
  586. static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel)
  587. {
  588. struct dp_catalog_private *catalog;
  589. struct dp_io_data *io_data;
  590. u32 header, parity, data, mst_offset = 0;
  591. u8 off = 0;
  592. u8 buf[SZ_128];
  593. if (!panel) {
  594. DP_ERR("invalid input\n");
  595. return;
  596. }
  597. if (panel->stream_id >= DP_STREAM_MAX) {
  598. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  599. return;
  600. }
  601. if (panel->stream_id == DP_STREAM_1)
  602. mst_offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  603. catalog = dp_catalog_get_priv(panel);
  604. io_data = catalog->io.dp_link;
  605. /* HEADER BYTE 1 */
  606. header = panel->vsc_colorimetry.header.HB1;
  607. parity = dp_header_get_parity(header);
  608. data = ((header << HEADER_BYTE_1_BIT)
  609. | (parity << PARITY_BYTE_1_BIT));
  610. dp_write(MMSS_DP_GENERIC0_0 + mst_offset, data);
  611. memcpy(buf + off, &data, sizeof(data));
  612. off += sizeof(data);
  613. /* HEADER BYTE 2 */
  614. header = panel->vsc_colorimetry.header.HB2;
  615. parity = dp_header_get_parity(header);
  616. data = ((header << HEADER_BYTE_2_BIT)
  617. | (parity << PARITY_BYTE_2_BIT));
  618. dp_write(MMSS_DP_GENERIC0_1 + mst_offset, data);
  619. /* HEADER BYTE 3 */
  620. header = panel->vsc_colorimetry.header.HB3;
  621. parity = dp_header_get_parity(header);
  622. data = ((header << HEADER_BYTE_3_BIT)
  623. | (parity << PARITY_BYTE_3_BIT));
  624. data |= dp_read(MMSS_DP_GENERIC0_1 + mst_offset);
  625. dp_write(MMSS_DP_GENERIC0_1 + mst_offset, data);
  626. memcpy(buf + off, &data, sizeof(data));
  627. off += sizeof(data);
  628. data = 0;
  629. dp_write(MMSS_DP_GENERIC0_2 + mst_offset, data);
  630. memcpy(buf + off, &data, sizeof(data));
  631. off += sizeof(data);
  632. dp_write(MMSS_DP_GENERIC0_3 + mst_offset, data);
  633. memcpy(buf + off, &data, sizeof(data));
  634. off += sizeof(data);
  635. dp_write(MMSS_DP_GENERIC0_4 + mst_offset, data);
  636. memcpy(buf + off, &data, sizeof(data));
  637. off += sizeof(data);
  638. dp_write(MMSS_DP_GENERIC0_5 + mst_offset, data);
  639. memcpy(buf + off, &data, sizeof(data));
  640. off += sizeof(data);
  641. data = (panel->vsc_colorimetry.data[16] & 0xFF) |
  642. ((panel->vsc_colorimetry.data[17] & 0xFF) << 8) |
  643. ((panel->vsc_colorimetry.data[18] & 0x7) << 16);
  644. dp_write(MMSS_DP_GENERIC0_6 + mst_offset, data);
  645. memcpy(buf + off, &data, sizeof(data));
  646. off += sizeof(data);
  647. data = 0;
  648. dp_write(MMSS_DP_GENERIC0_7 + mst_offset, data);
  649. memcpy(buf + off, &data, sizeof(data));
  650. off += sizeof(data);
  651. dp_write(MMSS_DP_GENERIC0_8 + mst_offset, data);
  652. memcpy(buf + off, &data, sizeof(data));
  653. off += sizeof(data);
  654. dp_write(MMSS_DP_GENERIC0_9 + mst_offset, data);
  655. memcpy(buf + off, &data, sizeof(data));
  656. off += sizeof(data);
  657. print_hex_dump(KERN_DEBUG, "[drm-dp] VSC: ",
  658. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  659. }
  660. static void dp_catalog_panel_config_sdp(struct dp_catalog_panel *panel,
  661. bool en)
  662. {
  663. struct dp_catalog_private *catalog;
  664. struct dp_io_data *io_data;
  665. u32 cfg, cfg2;
  666. u32 sdp_cfg_off = 0;
  667. u32 sdp_cfg2_off = 0;
  668. if (panel->stream_id >= DP_STREAM_MAX) {
  669. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  670. return;
  671. }
  672. catalog = dp_catalog_get_priv(panel);
  673. io_data = catalog->io.dp_link;
  674. if (panel->stream_id == DP_STREAM_1) {
  675. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  676. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  677. }
  678. cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  679. cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  680. if (en) {
  681. /* GEN0_SDP_EN */
  682. cfg |= BIT(17);
  683. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  684. /* GENERIC0_SDPSIZE */
  685. cfg2 |= BIT(16);
  686. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  687. /* setup the GENERIC0 in case of en = true */
  688. dp_catalog_panel_setup_vsc_sdp(panel);
  689. } else {
  690. /* GEN0_SDP_EN */
  691. cfg &= ~BIT(17);
  692. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  693. /* GENERIC0_SDPSIZE */
  694. cfg2 &= ~BIT(16);
  695. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  696. }
  697. dp_catalog_panel_sdp_update(panel);
  698. }
  699. static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
  700. {
  701. struct dp_catalog_private *catalog;
  702. struct dp_io_data *io_data;
  703. u32 reg_offset = 0;
  704. if (!panel) {
  705. DP_ERR("invalid input\n");
  706. return;
  707. }
  708. if (panel->stream_id >= DP_STREAM_MAX) {
  709. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  710. return;
  711. }
  712. catalog = dp_catalog_get_priv(panel);
  713. io_data = catalog->io.dp_link;
  714. if (panel->stream_id == DP_STREAM_1)
  715. reg_offset = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  716. DP_DEBUG("misc settings = 0x%x\n", panel->misc_val);
  717. dp_write(DP_MISC1_MISC0 + reg_offset, panel->misc_val);
  718. }
  719. static int dp_catalog_panel_set_colorspace(struct dp_catalog_panel *panel,
  720. bool vsc_supported)
  721. {
  722. struct dp_catalog_private *catalog;
  723. struct dp_io_data *io_data;
  724. if (!panel) {
  725. DP_ERR("invalid input\n");
  726. return -EINVAL;
  727. }
  728. if (panel->stream_id >= DP_STREAM_MAX) {
  729. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  730. return -EINVAL;
  731. }
  732. catalog = dp_catalog_get_priv(panel);
  733. io_data = catalog->io.dp_link;
  734. if (vsc_supported) {
  735. dp_catalog_panel_setup_vsc_sdp(panel);
  736. dp_catalog_panel_sdp_update(panel);
  737. } else
  738. dp_catalog_panel_config_misc(panel);
  739. return 0;
  740. }
  741. static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en,
  742. u32 dhdr_max_pkts, bool flush)
  743. {
  744. struct dp_catalog_private *catalog;
  745. struct dp_io_data *io_data;
  746. u32 cfg, cfg2, cfg4, misc;
  747. u32 sdp_cfg_off = 0;
  748. u32 sdp_cfg2_off = 0;
  749. u32 sdp_cfg4_off = 0;
  750. u32 misc1_misc0_off = 0;
  751. if (!panel) {
  752. DP_ERR("invalid input\n");
  753. return;
  754. }
  755. if (panel->stream_id >= DP_STREAM_MAX) {
  756. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  757. return;
  758. }
  759. catalog = dp_catalog_get_priv(panel);
  760. io_data = catalog->io.dp_link;
  761. if (panel->stream_id == DP_STREAM_1) {
  762. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  763. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  764. sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4;
  765. misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  766. }
  767. cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  768. cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  769. misc = dp_read(DP_MISC1_MISC0 + misc1_misc0_off);
  770. if (en) {
  771. if (dhdr_max_pkts) {
  772. /* VSCEXT_SDP_EN */
  773. cfg |= BIT(16);
  774. /* DHDR_EN, DHDR_PACKET_LIMIT */
  775. cfg4 = (dhdr_max_pkts << 1) | BIT(0);
  776. dp_write(MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4);
  777. dp_catalog_panel_setup_vsif_infoframe_sdp(panel);
  778. }
  779. /* GEN2_SDP_EN */
  780. cfg |= BIT(19);
  781. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  782. /* GENERIC2_SDPSIZE */
  783. cfg2 |= BIT(20);
  784. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  785. dp_catalog_panel_setup_hdr_infoframe_sdp(panel);
  786. if (panel->hdr_meta.eotf)
  787. DP_DEBUG("Enabled\n");
  788. else
  789. DP_DEBUG("Reset\n");
  790. } else {
  791. /* VSCEXT_SDP_ENG */
  792. cfg &= ~BIT(16) & ~BIT(19);
  793. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  794. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  795. cfg2 &= ~BIT(20);
  796. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  797. /* DHDR_EN, DHDR_PACKET_LIMIT */
  798. cfg4 = 0;
  799. dp_write(MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4);
  800. DP_DEBUG("Disabled\n");
  801. }
  802. if (flush) {
  803. DP_DEBUG("flushing HDR metadata\n");
  804. dp_catalog_panel_sdp_update(panel);
  805. }
  806. }
  807. static void dp_catalog_panel_update_transfer_unit(
  808. struct dp_catalog_panel *panel)
  809. {
  810. struct dp_catalog_private *catalog;
  811. struct dp_io_data *io_data;
  812. if (!panel || panel->stream_id >= DP_STREAM_MAX) {
  813. DP_ERR("invalid input\n");
  814. return;
  815. }
  816. catalog = dp_catalog_get_priv(panel);
  817. io_data = catalog->io.dp_link;
  818. dp_write(DP_VALID_BOUNDARY, panel->valid_boundary);
  819. dp_write(DP_TU, panel->dp_tu);
  820. dp_write(DP_VALID_BOUNDARY_2, panel->valid_boundary2);
  821. }
  822. static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state)
  823. {
  824. struct dp_catalog_private *catalog;
  825. struct dp_io_data *io_data;
  826. if (!ctrl) {
  827. DP_ERR("invalid input\n");
  828. return;
  829. }
  830. catalog = dp_catalog_get_priv(ctrl);
  831. io_data = catalog->io.dp_link;
  832. dp_write(DP_STATE_CTRL, state);
  833. /* make sure to change the hw state */
  834. wmb();
  835. }
  836. static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
  837. {
  838. struct dp_catalog_private *catalog;
  839. struct dp_io_data *io_data;
  840. u32 cfg;
  841. if (!ctrl) {
  842. DP_ERR("invalid input\n");
  843. return;
  844. }
  845. catalog = dp_catalog_get_priv(ctrl);
  846. io_data = catalog->io.dp_link;
  847. cfg = dp_read(DP_CONFIGURATION_CTRL);
  848. cfg &= ~(BIT(4) | BIT(5));
  849. cfg |= (ln_cnt - 1) << 4;
  850. dp_write(DP_CONFIGURATION_CTRL, cfg);
  851. cfg = dp_read(DP_MAINLINK_CTRL);
  852. cfg |= 0x02000000;
  853. dp_write(DP_MAINLINK_CTRL, cfg);
  854. DP_DEBUG("DP_MAINLINK_CTRL=0x%x\n", cfg);
  855. }
  856. static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
  857. u32 cfg)
  858. {
  859. struct dp_catalog_private *catalog;
  860. struct dp_io_data *io_data;
  861. u32 strm_reg_off = 0, mainlink_ctrl;
  862. if (!panel) {
  863. DP_ERR("invalid input\n");
  864. return;
  865. }
  866. if (panel->stream_id >= DP_STREAM_MAX) {
  867. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  868. return;
  869. }
  870. catalog = dp_catalog_get_priv(panel);
  871. io_data = catalog->io.dp_link;
  872. if (panel->stream_id == DP_STREAM_1)
  873. strm_reg_off = DP1_CONFIGURATION_CTRL - DP_CONFIGURATION_CTRL;
  874. DP_DEBUG("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
  875. dp_write(DP_CONFIGURATION_CTRL + strm_reg_off, cfg);
  876. mainlink_ctrl = dp_read(DP_MAINLINK_CTRL);
  877. if (panel->stream_id == DP_STREAM_0)
  878. io_data = catalog->io.dp_p0;
  879. else if (panel->stream_id == DP_STREAM_1)
  880. io_data = catalog->io.dp_p1;
  881. if (mainlink_ctrl & BIT(8))
  882. dp_write(MMSS_DP_ASYNC_FIFO_CONFIG, 0x01);
  883. else
  884. dp_write(MMSS_DP_ASYNC_FIFO_CONFIG, 0x00);
  885. }
  886. static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
  887. bool ack)
  888. {
  889. struct dp_catalog_private *catalog;
  890. struct dp_io_data *io_data;
  891. u32 dsc_dto;
  892. if (!panel) {
  893. DP_ERR("invalid input\n");
  894. return;
  895. }
  896. if (panel->stream_id >= DP_STREAM_MAX) {
  897. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  898. return;
  899. }
  900. catalog = dp_catalog_get_priv(panel);
  901. io_data = catalog->io.dp_link;
  902. switch (panel->stream_id) {
  903. case DP_STREAM_0:
  904. io_data = catalog->io.dp_p0;
  905. break;
  906. case DP_STREAM_1:
  907. io_data = catalog->io.dp_p1;
  908. break;
  909. default:
  910. DP_ERR("invalid stream id\n");
  911. return;
  912. }
  913. dsc_dto = dp_read(MMSS_DP_DSC_DTO);
  914. if (ack)
  915. dsc_dto = BIT(1);
  916. else
  917. dsc_dto &= ~BIT(1);
  918. dp_write(MMSS_DP_DSC_DTO, dsc_dto);
  919. }
  920. static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl,
  921. bool flipped, char *lane_map)
  922. {
  923. struct dp_catalog_private *catalog;
  924. struct dp_io_data *io_data;
  925. if (!ctrl) {
  926. DP_ERR("invalid input\n");
  927. return;
  928. }
  929. catalog = dp_catalog_get_priv(ctrl);
  930. io_data = catalog->io.dp_link;
  931. dp_write(DP_LOGICAL2PHYSICAL_LANE_MAPPING, 0xe4);
  932. }
  933. static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,
  934. u8 ln_pnswap)
  935. {
  936. struct dp_catalog_private *catalog;
  937. struct dp_io_data *io_data;
  938. u32 cfg0, cfg1;
  939. catalog = dp_catalog_get_priv(ctrl);
  940. cfg0 = 0x0a;
  941. cfg1 = 0x0a;
  942. cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
  943. cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
  944. cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
  945. cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
  946. io_data = catalog->io.dp_ln_tx0;
  947. dp_write(TXn_TX_POL_INV, cfg0);
  948. io_data = catalog->io.dp_ln_tx1;
  949. dp_write(TXn_TX_POL_INV, cfg1);
  950. }
  951. static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,
  952. bool enable)
  953. {
  954. u32 mainlink_ctrl, reg;
  955. struct dp_catalog_private *catalog;
  956. struct dp_io_data *io_data;
  957. if (!ctrl) {
  958. DP_ERR("invalid input\n");
  959. return;
  960. }
  961. catalog = dp_catalog_get_priv(ctrl);
  962. io_data = catalog->io.dp_link;
  963. if (enable) {
  964. reg = dp_read(DP_MAINLINK_CTRL);
  965. mainlink_ctrl = reg & ~(0x03);
  966. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  967. wmb(); /* make sure mainlink is turned off before reset */
  968. mainlink_ctrl = reg | 0x02;
  969. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  970. wmb(); /* make sure mainlink entered reset */
  971. mainlink_ctrl = reg & ~(0x03);
  972. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  973. wmb(); /* make sure mainlink reset done */
  974. mainlink_ctrl = reg | 0x01;
  975. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  976. wmb(); /* make sure mainlink turned on */
  977. } else {
  978. mainlink_ctrl = dp_read(DP_MAINLINK_CTRL);
  979. mainlink_ctrl &= ~BIT(0);
  980. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  981. }
  982. }
  983. static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
  984. u32 rate, u32 stream_rate_khz)
  985. {
  986. u32 pixel_m, pixel_n;
  987. u32 mvid, nvid;
  988. u32 const nvid_fixed = 0x8000;
  989. u32 const link_rate_hbr2 = 540000;
  990. u32 const link_rate_hbr3 = 810000;
  991. struct dp_catalog_private *catalog;
  992. struct dp_io_data *io_data;
  993. u32 strm_reg_off = 0;
  994. u32 mvid_reg_off = 0, nvid_reg_off = 0;
  995. if (!panel) {
  996. DP_ERR("invalid input\n");
  997. return;
  998. }
  999. if (panel->stream_id >= DP_STREAM_MAX) {
  1000. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1001. return;
  1002. }
  1003. catalog = dp_catalog_get_priv(panel);
  1004. io_data = catalog->io.dp_mmss_cc;
  1005. if (panel->stream_id == DP_STREAM_1)
  1006. strm_reg_off = MMSS_DP_PIXEL1_M - MMSS_DP_PIXEL_M;
  1007. pixel_m = dp_read(MMSS_DP_PIXEL_M + strm_reg_off);
  1008. pixel_n = dp_read(MMSS_DP_PIXEL_N + strm_reg_off);
  1009. DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
  1010. mvid = (pixel_m & 0xFFFF) * 5;
  1011. nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
  1012. if (nvid < nvid_fixed) {
  1013. u32 temp;
  1014. temp = (nvid_fixed / nvid) * nvid;
  1015. mvid = (nvid_fixed / nvid) * mvid;
  1016. nvid = temp;
  1017. }
  1018. DP_DEBUG("rate = %d\n", rate);
  1019. if (panel->widebus_en)
  1020. mvid <<= 1;
  1021. if (link_rate_hbr2 == rate)
  1022. nvid *= 2;
  1023. if (link_rate_hbr3 == rate)
  1024. nvid *= 3;
  1025. io_data = catalog->io.dp_link;
  1026. if (panel->stream_id == DP_STREAM_1) {
  1027. mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
  1028. nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
  1029. }
  1030. DP_DEBUG("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
  1031. dp_write(DP_SOFTWARE_MVID + mvid_reg_off, mvid);
  1032. dp_write(DP_SOFTWARE_NVID + nvid_reg_off, nvid);
  1033. }
  1034. static void dp_catalog_ctrl_set_pattern(struct dp_catalog_ctrl *ctrl,
  1035. u32 pattern)
  1036. {
  1037. int bit, cnt = 10;
  1038. u32 data;
  1039. const u32 link_training_offset = 3;
  1040. struct dp_catalog_private *catalog;
  1041. struct dp_io_data *io_data;
  1042. if (!ctrl) {
  1043. DP_ERR("invalid input\n");
  1044. return;
  1045. }
  1046. catalog = dp_catalog_get_priv(ctrl);
  1047. io_data = catalog->io.dp_link;
  1048. switch (pattern) {
  1049. case DP_TRAINING_PATTERN_4:
  1050. bit = 3;
  1051. break;
  1052. case DP_TRAINING_PATTERN_3:
  1053. case DP_TRAINING_PATTERN_2:
  1054. case DP_TRAINING_PATTERN_1:
  1055. bit = pattern - 1;
  1056. break;
  1057. default:
  1058. DP_ERR("invalid pattern\n");
  1059. return;
  1060. }
  1061. DP_DEBUG("hw: bit=%d train=%d\n", bit, pattern);
  1062. dp_write(DP_STATE_CTRL, BIT(bit));
  1063. bit += link_training_offset;
  1064. while (cnt--) {
  1065. data = dp_read(DP_MAINLINK_READY);
  1066. if (data & BIT(bit))
  1067. break;
  1068. }
  1069. if (cnt == 0)
  1070. DP_ERR("set link_train=%d failed\n", pattern);
  1071. }
  1072. static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
  1073. {
  1074. struct dp_catalog_private *catalog;
  1075. struct dp_io_data *io_data;
  1076. if (!ctrl) {
  1077. DP_ERR("invalid input\n");
  1078. return;
  1079. }
  1080. catalog = dp_catalog_get_priv(ctrl);
  1081. io_data = catalog->io.usb3_dp_com;
  1082. dp_write(USB3_DP_COM_RESET_OVRD_CTRL, 0x0a);
  1083. dp_write(USB3_DP_COM_PHY_MODE_CTRL, 0x02);
  1084. dp_write(USB3_DP_COM_SW_RESET, 0x01);
  1085. /* make sure usb3 com phy software reset is done */
  1086. wmb();
  1087. if (!flip) /* CC1 */
  1088. dp_write(USB3_DP_COM_TYPEC_CTRL, 0x02);
  1089. else /* CC2 */
  1090. dp_write(USB3_DP_COM_TYPEC_CTRL, 0x03);
  1091. dp_write(USB3_DP_COM_SWI_CTRL, 0x00);
  1092. dp_write(USB3_DP_COM_SW_RESET, 0x00);
  1093. /* make sure the software reset is done */
  1094. wmb();
  1095. dp_write(USB3_DP_COM_POWER_DOWN_CTRL, 0x01);
  1096. dp_write(USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
  1097. /* make sure phy is brought out of reset */
  1098. wmb();
  1099. }
  1100. static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
  1101. bool enable)
  1102. {
  1103. struct dp_catalog_private *catalog;
  1104. struct dp_io_data *io_data;
  1105. if (!panel) {
  1106. DP_ERR("invalid input\n");
  1107. return;
  1108. }
  1109. if (panel->stream_id >= DP_STREAM_MAX) {
  1110. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1111. return;
  1112. }
  1113. catalog = dp_catalog_get_priv(panel);
  1114. if (panel->stream_id == DP_STREAM_0)
  1115. io_data = catalog->io.dp_p0;
  1116. else if (panel->stream_id == DP_STREAM_1)
  1117. io_data = catalog->io.dp_p1;
  1118. if (!enable) {
  1119. dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x0);
  1120. dp_write(MMSS_DP_BIST_ENABLE, 0x0);
  1121. dp_write(MMSS_DP_TIMING_ENGINE_EN, 0x0);
  1122. wmb(); /* ensure Timing generator is turned off */
  1123. return;
  1124. }
  1125. dp_write(MMSS_DP_INTF_CONFIG, 0x0);
  1126. dp_write(MMSS_DP_INTF_HSYNC_CTL,
  1127. panel->hsync_ctl);
  1128. dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F0,
  1129. panel->vsync_period * panel->hsync_period);
  1130. dp_write(MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
  1131. panel->v_sync_width * panel->hsync_period);
  1132. dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
  1133. dp_write(MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
  1134. dp_write(MMSS_DP_INTF_DISPLAY_HCTL, panel->display_hctl);
  1135. dp_write(MMSS_DP_INTF_ACTIVE_HCTL, 0);
  1136. dp_write(MMSS_INTF_DISPLAY_V_START_F0, panel->display_v_start);
  1137. dp_write(MMSS_DP_INTF_DISPLAY_V_END_F0, panel->display_v_end);
  1138. dp_write(MMSS_INTF_DISPLAY_V_START_F1, 0);
  1139. dp_write(MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
  1140. dp_write(MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
  1141. dp_write(MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
  1142. dp_write(MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
  1143. dp_write(MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
  1144. dp_write(MMSS_DP_INTF_POLARITY_CTL, 0);
  1145. wmb(); /* ensure TPG registers are programmed */
  1146. dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x100);
  1147. dp_write(MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
  1148. wmb(); /* ensure TPG config is programmed */
  1149. dp_write(MMSS_DP_BIST_ENABLE, 0x1);
  1150. dp_write(MMSS_DP_TIMING_ENGINE_EN, 0x1);
  1151. wmb(); /* ensure Timing generator is turned on */
  1152. }
  1153. static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel)
  1154. {
  1155. struct dp_catalog_private *catalog;
  1156. struct dp_io_data *io_data;
  1157. u32 reg, offset;
  1158. int i;
  1159. if (!panel) {
  1160. DP_ERR("invalid input\n");
  1161. return;
  1162. }
  1163. if (panel->stream_id >= DP_STREAM_MAX) {
  1164. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1165. return;
  1166. }
  1167. catalog = dp_catalog_get_priv(panel);
  1168. if (panel->stream_id == DP_STREAM_0)
  1169. io_data = catalog->io.dp_p0;
  1170. else
  1171. io_data = catalog->io.dp_p1;
  1172. dp_write(MMSS_DP_DSC_DTO_COUNT, panel->dsc.dto_count);
  1173. reg = dp_read(MMSS_DP_DSC_DTO);
  1174. if (panel->dsc.dto_en) {
  1175. reg |= BIT(0);
  1176. reg |= (panel->dsc.dto_n << 8);
  1177. reg |= (panel->dsc.dto_d << 16);
  1178. }
  1179. dp_write(MMSS_DP_DSC_DTO, reg);
  1180. io_data = catalog->io.dp_link;
  1181. if (panel->stream_id == DP_STREAM_0)
  1182. offset = 0;
  1183. else
  1184. offset = DP1_COMPRESSION_MODE_CTRL - DP_COMPRESSION_MODE_CTRL;
  1185. dp_write(DP_PPS_HB_0_3 + offset, 0x7F1000);
  1186. dp_write(DP_PPS_PB_0_3 + offset, 0xA22300);
  1187. for (i = 0; i < panel->dsc.parity_word_len; i++)
  1188. dp_write(DP_PPS_PB_4_7 + (i << 2) + offset,
  1189. panel->dsc.parity_word[i]);
  1190. for (i = 0; i < panel->dsc.pps_word_len; i++)
  1191. dp_write(DP_PPS_PPS_0_3 + (i << 2) + offset,
  1192. panel->dsc.pps_word[i]);
  1193. reg = 0;
  1194. if (panel->dsc.dsc_en) {
  1195. reg = BIT(0);
  1196. reg |= (panel->dsc.eol_byte_num << 3);
  1197. reg |= (panel->dsc.slice_per_pkt << 5);
  1198. reg |= (panel->dsc.bytes_per_pkt << 16);
  1199. reg |= (panel->dsc.be_in_lane << 10);
  1200. }
  1201. dp_write(DP_COMPRESSION_MODE_CTRL + offset, reg);
  1202. DP_DEBUG("compression:0x%x for stream:%d\n",
  1203. reg, panel->stream_id);
  1204. }
  1205. static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel,
  1206. enum dp_flush_bit flush_bit)
  1207. {
  1208. struct dp_catalog_private *catalog;
  1209. struct dp_io_data *io_data;
  1210. u32 dp_flush, offset;
  1211. if (!panel) {
  1212. DP_ERR("invalid input\n");
  1213. return;
  1214. }
  1215. if (panel->stream_id >= DP_STREAM_MAX) {
  1216. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1217. return;
  1218. }
  1219. catalog = dp_catalog_get_priv(panel);
  1220. io_data = catalog->io.dp_link;
  1221. if (panel->stream_id == DP_STREAM_0)
  1222. offset = 0;
  1223. else
  1224. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1225. dp_flush = dp_read(MMSS_DP_FLUSH + offset);
  1226. dp_flush |= BIT(flush_bit);
  1227. dp_write(MMSS_DP_FLUSH + offset, dp_flush);
  1228. }
  1229. static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel)
  1230. {
  1231. dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH);
  1232. DP_DEBUG("pps flush for stream:%d\n", panel->stream_id);
  1233. }
  1234. static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel)
  1235. {
  1236. dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH);
  1237. DP_DEBUG("dhdr flush for stream:%d\n", panel->stream_id);
  1238. }
  1239. static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel)
  1240. {
  1241. struct dp_catalog_private *catalog;
  1242. struct dp_io_data *io_data;
  1243. u32 dp_flush, offset;
  1244. if (panel->stream_id >= DP_STREAM_MAX) {
  1245. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1246. return false;
  1247. }
  1248. catalog = dp_catalog_get_priv(panel);
  1249. io_data = catalog->io.dp_link;
  1250. if (panel->stream_id == DP_STREAM_0)
  1251. offset = 0;
  1252. else
  1253. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1254. dp_flush = dp_read(MMSS_DP_FLUSH + offset);
  1255. return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false;
  1256. }
  1257. static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
  1258. {
  1259. u32 sw_reset;
  1260. struct dp_catalog_private *catalog;
  1261. struct dp_io_data *io_data;
  1262. if (!ctrl) {
  1263. DP_ERR("invalid input\n");
  1264. return;
  1265. }
  1266. catalog = dp_catalog_get_priv(ctrl);
  1267. io_data = catalog->io.dp_ahb;
  1268. sw_reset = dp_read(DP_SW_RESET);
  1269. sw_reset |= BIT(0);
  1270. dp_write(DP_SW_RESET, sw_reset);
  1271. usleep_range(1000, 1010); /* h/w recommended delay */
  1272. sw_reset &= ~BIT(0);
  1273. dp_write(DP_SW_RESET, sw_reset);
  1274. }
  1275. static bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog_ctrl *ctrl)
  1276. {
  1277. u32 data;
  1278. int cnt = 10;
  1279. struct dp_catalog_private *catalog;
  1280. struct dp_io_data *io_data;
  1281. if (!ctrl) {
  1282. DP_ERR("invalid input\n");
  1283. goto end;
  1284. }
  1285. catalog = dp_catalog_get_priv(ctrl);
  1286. io_data = catalog->io.dp_link;
  1287. while (--cnt) {
  1288. /* DP_MAINLINK_READY */
  1289. data = dp_read(DP_MAINLINK_READY);
  1290. if (data & BIT(0))
  1291. return true;
  1292. usleep_range(1000, 1010); /* 1ms wait before next reg read */
  1293. }
  1294. DP_ERR("mainlink not ready\n");
  1295. end:
  1296. return false;
  1297. }
  1298. static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
  1299. bool enable)
  1300. {
  1301. struct dp_catalog_private *catalog;
  1302. struct dp_io_data *io_data;
  1303. if (!ctrl) {
  1304. DP_ERR("invalid input\n");
  1305. return;
  1306. }
  1307. catalog = dp_catalog_get_priv(ctrl);
  1308. io_data = catalog->io.dp_ahb;
  1309. if (enable) {
  1310. dp_write(DP_INTR_STATUS, DP_INTR_MASK1);
  1311. dp_write(DP_INTR_STATUS2, DP_INTR_MASK2);
  1312. dp_write(DP_INTR_STATUS5, DP_INTR_MASK5);
  1313. } else {
  1314. dp_write(DP_INTR_STATUS, 0x00);
  1315. dp_write(DP_INTR_STATUS2, 0x00);
  1316. dp_write(DP_INTR_STATUS5, 0x00);
  1317. }
  1318. }
  1319. static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
  1320. {
  1321. u32 ack = 0;
  1322. struct dp_catalog_private *catalog;
  1323. struct dp_io_data *io_data;
  1324. if (!ctrl) {
  1325. DP_ERR("invalid input\n");
  1326. return;
  1327. }
  1328. catalog = dp_catalog_get_priv(ctrl);
  1329. io_data = catalog->io.dp_ahb;
  1330. ctrl->isr = dp_read(DP_INTR_STATUS2);
  1331. ctrl->isr &= ~DP_INTR_MASK2;
  1332. ack = ctrl->isr & DP_INTERRUPT_STATUS2;
  1333. ack <<= 1;
  1334. ack |= DP_INTR_MASK2;
  1335. dp_write(DP_INTR_STATUS2, ack);
  1336. ctrl->isr5 = dp_read(DP_INTR_STATUS5);
  1337. ctrl->isr5 &= ~DP_INTR_MASK5;
  1338. ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
  1339. ack <<= 1;
  1340. ack |= DP_INTR_MASK5;
  1341. dp_write(DP_INTR_STATUS5, ack);
  1342. }
  1343. static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)
  1344. {
  1345. struct dp_catalog_private *catalog;
  1346. struct dp_io_data *io_data;
  1347. if (!ctrl) {
  1348. DP_ERR("invalid input\n");
  1349. return;
  1350. }
  1351. catalog = dp_catalog_get_priv(ctrl);
  1352. io_data = catalog->io.dp_ahb;
  1353. dp_write(DP_PHY_CTRL, 0x5); /* bit 0 & 2 */
  1354. usleep_range(1000, 1010); /* h/w recommended delay */
  1355. dp_write(DP_PHY_CTRL, 0x0);
  1356. wmb(); /* make sure PHY reset done */
  1357. }
  1358. static void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog_ctrl *ctrl,
  1359. bool flipped, u8 ln_cnt)
  1360. {
  1361. u32 info = 0x0;
  1362. struct dp_catalog_private *catalog;
  1363. struct dp_io_data *io_data;
  1364. u8 orientation = BIT(!!flipped);
  1365. if (!ctrl) {
  1366. DP_ERR("invalid input\n");
  1367. return;
  1368. }
  1369. catalog = dp_catalog_get_priv(ctrl);
  1370. io_data = catalog->io.dp_phy;
  1371. info |= (ln_cnt & 0x0F);
  1372. info |= ((orientation & 0x0F) << 4);
  1373. DP_DEBUG("Shared Info = 0x%x\n", info);
  1374. dp_write(DP_PHY_SPARE0, info);
  1375. }
  1376. static void dp_catalog_ctrl_update_vx_px(struct dp_catalog_ctrl *ctrl,
  1377. u8 v_level, u8 p_level, bool high)
  1378. {
  1379. struct dp_catalog_private *catalog;
  1380. struct dp_io_data *io_data;
  1381. u8 value0, value1;
  1382. if (!ctrl) {
  1383. DP_ERR("invalid input\n");
  1384. return;
  1385. }
  1386. catalog = dp_catalog_get_priv(ctrl);
  1387. DP_DEBUG("hw: v=%d p=%d\n", v_level, p_level);
  1388. value0 = vm_voltage_swing[v_level][p_level];
  1389. value1 = vm_pre_emphasis[v_level][p_level];
  1390. /* program default setting first */
  1391. io_data = catalog->io.dp_ln_tx0;
  1392. dp_write(TXn_TX_DRV_LVL, 0x2A);
  1393. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  1394. io_data = catalog->io.dp_ln_tx1;
  1395. dp_write(TXn_TX_DRV_LVL, 0x2A);
  1396. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  1397. /* Enable MUX to use Cursor values from these registers */
  1398. value0 |= BIT(5);
  1399. value1 |= BIT(5);
  1400. /* Configure host and panel only if both values are allowed */
  1401. if (value0 != 0xFF && value1 != 0xFF) {
  1402. io_data = catalog->io.dp_ln_tx0;
  1403. dp_write(TXn_TX_DRV_LVL, value0);
  1404. dp_write(TXn_TX_EMP_POST1_LVL, value1);
  1405. io_data = catalog->io.dp_ln_tx1;
  1406. dp_write(TXn_TX_DRV_LVL, value0);
  1407. dp_write(TXn_TX_EMP_POST1_LVL, value1);
  1408. DP_DEBUG("hw: vx_value=0x%x px_value=0x%x\n",
  1409. value0, value1);
  1410. } else {
  1411. DP_ERR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
  1412. v_level, value0, p_level, value1);
  1413. }
  1414. }
  1415. static void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog_ctrl *ctrl,
  1416. u32 pattern)
  1417. {
  1418. struct dp_catalog_private *catalog;
  1419. u32 value = 0x0;
  1420. struct dp_io_data *io_data = NULL;
  1421. if (!ctrl) {
  1422. DP_ERR("invalid input\n");
  1423. return;
  1424. }
  1425. catalog = dp_catalog_get_priv(ctrl);
  1426. io_data = catalog->io.dp_link;
  1427. dp_write(DP_STATE_CTRL, 0x0);
  1428. switch (pattern) {
  1429. case DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING:
  1430. dp_write(DP_STATE_CTRL, 0x1);
  1431. break;
  1432. case DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT:
  1433. value &= ~(1 << 16);
  1434. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1435. value |= 0xFC;
  1436. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1437. dp_write(DP_MAINLINK_LEVELS, 0x2);
  1438. dp_write(DP_STATE_CTRL, 0x10);
  1439. break;
  1440. case DP_TEST_PHY_PATTERN_PRBS7:
  1441. dp_write(DP_STATE_CTRL, 0x20);
  1442. break;
  1443. case DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN:
  1444. dp_write(DP_STATE_CTRL, 0x40);
  1445. /* 00111110000011111000001111100000 */
  1446. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0);
  1447. /* 00001111100000111110000011111000 */
  1448. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8);
  1449. /* 1111100000111110 */
  1450. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E);
  1451. break;
  1452. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_1:
  1453. value = dp_read(DP_MAINLINK_CTRL);
  1454. value &= ~BIT(4);
  1455. dp_write(DP_MAINLINK_CTRL, value);
  1456. value = BIT(16);
  1457. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1458. value |= 0xFC;
  1459. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1460. dp_write(DP_MAINLINK_LEVELS, 0x2);
  1461. dp_write(DP_STATE_CTRL, 0x10);
  1462. value = dp_read(DP_MAINLINK_CTRL);
  1463. value |= BIT(0);
  1464. dp_write(DP_MAINLINK_CTRL, value);
  1465. break;
  1466. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_3:
  1467. dp_write(DP_MAINLINK_CTRL, 0x11);
  1468. dp_write(DP_STATE_CTRL, 0x8);
  1469. break;
  1470. default:
  1471. DP_DEBUG("No valid test pattern requested: 0x%x\n", pattern);
  1472. return;
  1473. }
  1474. /* Make sure the test pattern is programmed in the hardware */
  1475. wmb();
  1476. }
  1477. static u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog_ctrl *ctrl)
  1478. {
  1479. struct dp_catalog_private *catalog;
  1480. struct dp_io_data *io_data = NULL;
  1481. if (!ctrl) {
  1482. DP_ERR("invalid input\n");
  1483. return 0;
  1484. }
  1485. catalog = dp_catalog_get_priv(ctrl);
  1486. io_data = catalog->io.dp_link;
  1487. return dp_read(DP_MAINLINK_READY);
  1488. }
  1489. static void dp_catalog_ctrl_fec_config(struct dp_catalog_ctrl *ctrl,
  1490. bool enable)
  1491. {
  1492. struct dp_catalog_private *catalog;
  1493. struct dp_io_data *io_data = NULL;
  1494. u32 reg;
  1495. if (!ctrl) {
  1496. DP_ERR("invalid input\n");
  1497. return;
  1498. }
  1499. catalog = dp_catalog_get_priv(ctrl);
  1500. io_data = catalog->io.dp_link;
  1501. reg = dp_read(DP_MAINLINK_CTRL);
  1502. /*
  1503. * fec_en = BIT(12)
  1504. * fec_seq_mode = BIT(22)
  1505. * sde_flush = BIT(23) | BIT(24)
  1506. * fb_boundary_sel = BIT(25)
  1507. */
  1508. if (enable)
  1509. reg |= BIT(12) | BIT(22) | BIT(23) | BIT(24) | BIT(25);
  1510. else
  1511. reg &= ~BIT(12);
  1512. dp_write(DP_MAINLINK_CTRL, reg);
  1513. /* make sure mainlink configuration is updated with fec sequence */
  1514. wmb();
  1515. }
  1516. static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
  1517. char *name, u8 **out_buf, u32 *out_buf_len)
  1518. {
  1519. int ret = 0;
  1520. u8 *buf;
  1521. u32 len;
  1522. struct dp_io_data *io_data;
  1523. struct dp_catalog_private *catalog;
  1524. struct dp_parser *parser;
  1525. if (!dp_catalog) {
  1526. DP_ERR("invalid input\n");
  1527. return -EINVAL;
  1528. }
  1529. catalog = container_of(dp_catalog, struct dp_catalog_private,
  1530. dp_catalog);
  1531. parser = catalog->parser;
  1532. parser->get_io_buf(parser, name);
  1533. io_data = parser->get_io(parser, name);
  1534. if (!io_data) {
  1535. DP_ERR("IO %s not found\n", name);
  1536. ret = -EINVAL;
  1537. goto end;
  1538. }
  1539. buf = io_data->buf;
  1540. len = io_data->io.len;
  1541. if (!buf || !len) {
  1542. DP_ERR("no buffer available\n");
  1543. ret = -ENOMEM;
  1544. goto end;
  1545. }
  1546. if (!strcmp(catalog->exe_mode, "hw") ||
  1547. !strcmp(catalog->exe_mode, "all")) {
  1548. u32 i, data;
  1549. u32 const rowsize = 4;
  1550. void __iomem *addr = io_data->io.base;
  1551. memset(buf, 0, len);
  1552. for (i = 0; i < len / rowsize; i++) {
  1553. data = readl_relaxed(addr);
  1554. memcpy(buf + (rowsize * i), &data, sizeof(u32));
  1555. addr += rowsize;
  1556. }
  1557. }
  1558. *out_buf = buf;
  1559. *out_buf_len = len;
  1560. end:
  1561. if (ret)
  1562. parser->clear_io_buf(parser);
  1563. return ret;
  1564. }
  1565. static void dp_catalog_ctrl_mst_config(struct dp_catalog_ctrl *ctrl,
  1566. bool enable)
  1567. {
  1568. struct dp_catalog_private *catalog;
  1569. struct dp_io_data *io_data = NULL;
  1570. u32 reg;
  1571. if (!ctrl) {
  1572. DP_ERR("invalid input\n");
  1573. return;
  1574. }
  1575. catalog = dp_catalog_get_priv(ctrl);
  1576. io_data = catalog->io.dp_link;
  1577. reg = dp_read(DP_MAINLINK_CTRL);
  1578. if (enable)
  1579. reg |= (0x04000100);
  1580. else
  1581. reg &= ~(0x04000100);
  1582. dp_write(DP_MAINLINK_CTRL, reg);
  1583. /* make sure mainlink MST configuration is updated */
  1584. wmb();
  1585. }
  1586. static void dp_catalog_ctrl_trigger_act(struct dp_catalog_ctrl *ctrl)
  1587. {
  1588. struct dp_catalog_private *catalog;
  1589. struct dp_io_data *io_data = NULL;
  1590. if (!ctrl) {
  1591. DP_ERR("invalid input\n");
  1592. return;
  1593. }
  1594. catalog = dp_catalog_get_priv(ctrl);
  1595. io_data = catalog->io.dp_link;
  1596. dp_write(DP_MST_ACT, 0x1);
  1597. /* make sure ACT signal is performed */
  1598. wmb();
  1599. }
  1600. static void dp_catalog_ctrl_read_act_complete_sts(struct dp_catalog_ctrl *ctrl,
  1601. bool *sts)
  1602. {
  1603. struct dp_catalog_private *catalog;
  1604. struct dp_io_data *io_data = NULL;
  1605. u32 reg;
  1606. if (!ctrl || !sts) {
  1607. DP_ERR("invalid input\n");
  1608. return;
  1609. }
  1610. *sts = false;
  1611. catalog = dp_catalog_get_priv(ctrl);
  1612. io_data = catalog->io.dp_link;
  1613. reg = dp_read(DP_MST_ACT);
  1614. if (!reg)
  1615. *sts = true;
  1616. }
  1617. static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
  1618. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1619. {
  1620. struct dp_catalog_private *catalog;
  1621. struct dp_io_data *io_data = NULL;
  1622. u32 i, slot_reg_1, slot_reg_2, slot;
  1623. u32 reg_off = 0;
  1624. int const num_slots_per_reg = 32;
  1625. if (!ctrl || ch >= DP_STREAM_MAX) {
  1626. DP_ERR("invalid input. ch %d\n", ch);
  1627. return;
  1628. }
  1629. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1630. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1631. DP_ERR("invalid slots start %d, tot %d\n",
  1632. ch_start_slot, tot_slot_cnt);
  1633. return;
  1634. }
  1635. catalog = dp_catalog_get_priv(ctrl);
  1636. io_data = catalog->io.dp_link;
  1637. DP_DEBUG("ch %d, start_slot %d, tot_slot %d\n",
  1638. ch, ch_start_slot, tot_slot_cnt);
  1639. if (ch == DP_STREAM_1)
  1640. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1641. slot_reg_1 = 0;
  1642. slot_reg_2 = 0;
  1643. if (ch_start_slot && tot_slot_cnt) {
  1644. ch_start_slot--;
  1645. for (i = 0; i < tot_slot_cnt; i++) {
  1646. if (ch_start_slot < num_slots_per_reg) {
  1647. slot_reg_1 |= BIT(ch_start_slot);
  1648. } else {
  1649. slot = ch_start_slot - num_slots_per_reg;
  1650. slot_reg_2 |= BIT(slot);
  1651. }
  1652. ch_start_slot++;
  1653. }
  1654. }
  1655. DP_DEBUG("ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1656. slot_reg_1, slot_reg_2);
  1657. dp_write(DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
  1658. dp_write(DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
  1659. }
  1660. static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
  1661. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1662. {
  1663. struct dp_catalog_private *catalog;
  1664. struct dp_io_data *io_data = NULL;
  1665. u32 i, slot_reg_1, slot_reg_2, slot;
  1666. u32 reg_off = 0;
  1667. if (!ctrl || ch >= DP_STREAM_MAX) {
  1668. DP_ERR("invalid input. ch %d\n", ch);
  1669. return;
  1670. }
  1671. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1672. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1673. DP_ERR("invalid slots start %d, tot %d\n",
  1674. ch_start_slot, tot_slot_cnt);
  1675. return;
  1676. }
  1677. catalog = dp_catalog_get_priv(ctrl);
  1678. io_data = catalog->io.dp_link;
  1679. DP_DEBUG("dealloc ch %d, start_slot %d, tot_slot %d\n",
  1680. ch, ch_start_slot, tot_slot_cnt);
  1681. if (ch == DP_STREAM_1)
  1682. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1683. slot_reg_1 = dp_read(DP_DP0_TIMESLOT_1_32 + reg_off);
  1684. slot_reg_2 = dp_read(DP_DP0_TIMESLOT_33_63 + reg_off);
  1685. ch_start_slot = ch_start_slot - 1;
  1686. for (i = 0; i < tot_slot_cnt; i++) {
  1687. if (ch_start_slot < 33) {
  1688. slot_reg_1 &= ~BIT(ch_start_slot);
  1689. } else {
  1690. slot = ch_start_slot - 33;
  1691. slot_reg_2 &= ~BIT(slot);
  1692. }
  1693. ch_start_slot++;
  1694. }
  1695. DP_DEBUG("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1696. slot_reg_1, slot_reg_2);
  1697. dp_write(DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
  1698. dp_write(DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
  1699. }
  1700. static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
  1701. u32 x_int, u32 y_frac_enum)
  1702. {
  1703. struct dp_catalog_private *catalog;
  1704. struct dp_io_data *io_data = NULL;
  1705. u32 rg, reg_off = 0;
  1706. if (!ctrl || ch >= DP_STREAM_MAX) {
  1707. DP_ERR("invalid input. ch %d\n", ch);
  1708. return;
  1709. }
  1710. catalog = dp_catalog_get_priv(ctrl);
  1711. io_data = catalog->io.dp_link;
  1712. rg = y_frac_enum;
  1713. rg |= (x_int << 16);
  1714. DP_DEBUG("ch: %d x_int:%d y_frac_enum:%d rg:%d\n", ch, x_int,
  1715. y_frac_enum, rg);
  1716. if (ch == DP_STREAM_1)
  1717. reg_off = DP_DP1_RG - DP_DP0_RG;
  1718. dp_write(DP_DP0_RG + reg_off, rg);
  1719. }
  1720. static void dp_catalog_ctrl_mainlink_levels(struct dp_catalog_ctrl *ctrl,
  1721. u8 lane_cnt)
  1722. {
  1723. struct dp_catalog_private *catalog;
  1724. struct dp_io_data *io_data;
  1725. u32 mainlink_levels, safe_to_exit_level = 14;
  1726. catalog = dp_catalog_get_priv(ctrl);
  1727. io_data = catalog->io.dp_link;
  1728. switch (lane_cnt) {
  1729. case 1:
  1730. safe_to_exit_level = 14;
  1731. break;
  1732. case 2:
  1733. safe_to_exit_level = 8;
  1734. break;
  1735. case 4:
  1736. safe_to_exit_level = 5;
  1737. break;
  1738. default:
  1739. DP_DEBUG("setting the default safe_to_exit_level = %u\n",
  1740. safe_to_exit_level);
  1741. break;
  1742. }
  1743. mainlink_levels = dp_read(DP_MAINLINK_LEVELS);
  1744. mainlink_levels &= 0xFE0;
  1745. mainlink_levels |= safe_to_exit_level;
  1746. DP_DEBUG("mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
  1747. mainlink_levels, safe_to_exit_level);
  1748. dp_write(DP_MAINLINK_LEVELS, mainlink_levels);
  1749. }
  1750. /* panel related catalog functions */
  1751. static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel)
  1752. {
  1753. struct dp_catalog_private *catalog;
  1754. struct dp_io_data *io_data;
  1755. u32 offset = 0, reg;
  1756. if (!panel) {
  1757. DP_ERR("invalid input\n");
  1758. goto end;
  1759. }
  1760. if (panel->stream_id >= DP_STREAM_MAX) {
  1761. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1762. goto end;
  1763. }
  1764. catalog = dp_catalog_get_priv(panel);
  1765. io_data = catalog->io.dp_link;
  1766. if (panel->stream_id == DP_STREAM_1)
  1767. offset = DP1_TOTAL_HOR_VER - DP_TOTAL_HOR_VER;
  1768. dp_write(DP_TOTAL_HOR_VER + offset, panel->total);
  1769. dp_write(DP_START_HOR_VER_FROM_SYNC + offset, panel->sync_start);
  1770. dp_write(DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);
  1771. dp_write(DP_ACTIVE_HOR_VER + offset, panel->dp_active);
  1772. if (panel->stream_id == DP_STREAM_0)
  1773. io_data = catalog->io.dp_p0;
  1774. else
  1775. io_data = catalog->io.dp_p1;
  1776. reg = dp_read(MMSS_DP_INTF_CONFIG);
  1777. if (panel->widebus_en)
  1778. reg |= BIT(4);
  1779. else
  1780. reg &= ~BIT(4);
  1781. dp_write(MMSS_DP_INTF_CONFIG, reg);
  1782. end:
  1783. return 0;
  1784. }
  1785. static void dp_catalog_hpd_config_hpd(struct dp_catalog_hpd *hpd, bool en)
  1786. {
  1787. struct dp_catalog_private *catalog;
  1788. struct dp_io_data *io_data;
  1789. if (!hpd) {
  1790. DP_ERR("invalid input\n");
  1791. return;
  1792. }
  1793. catalog = dp_catalog_get_priv(hpd);
  1794. io_data = catalog->io.dp_aux;
  1795. if (en) {
  1796. u32 reftimer = dp_read(DP_DP_HPD_REFTIMER);
  1797. /* Arm only the UNPLUG and HPD_IRQ interrupts */
  1798. dp_write(DP_DP_HPD_INT_ACK, 0xF);
  1799. dp_write(DP_DP_HPD_INT_MASK, 0xA);
  1800. /* Enable REFTIMER to count 1ms */
  1801. reftimer |= BIT(16);
  1802. dp_write(DP_DP_HPD_REFTIMER, reftimer);
  1803. /* Connect_time is 250us & disconnect_time is 2ms */
  1804. dp_write(DP_DP_HPD_EVENT_TIME_0, 0x3E800FA);
  1805. dp_write(DP_DP_HPD_EVENT_TIME_1, 0x1F407D0);
  1806. /* Enable HPD */
  1807. dp_write(DP_DP_HPD_CTRL, 0x1);
  1808. } else {
  1809. /* Disable HPD */
  1810. dp_write(DP_DP_HPD_CTRL, 0x0);
  1811. }
  1812. }
  1813. static u32 dp_catalog_hpd_get_interrupt(struct dp_catalog_hpd *hpd)
  1814. {
  1815. u32 isr = 0;
  1816. struct dp_catalog_private *catalog;
  1817. struct dp_io_data *io_data;
  1818. if (!hpd) {
  1819. DP_ERR("invalid input\n");
  1820. return isr;
  1821. }
  1822. catalog = dp_catalog_get_priv(hpd);
  1823. io_data = catalog->io.dp_aux;
  1824. isr = dp_read(DP_DP_HPD_INT_STATUS);
  1825. dp_write(DP_DP_HPD_INT_ACK, (isr & 0xf));
  1826. return isr;
  1827. }
  1828. static void dp_catalog_audio_init(struct dp_catalog_audio *audio)
  1829. {
  1830. struct dp_catalog_private *catalog;
  1831. static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
  1832. {
  1833. MMSS_DP_AUDIO_STREAM_0,
  1834. MMSS_DP_AUDIO_STREAM_1,
  1835. MMSS_DP_AUDIO_STREAM_1,
  1836. },
  1837. {
  1838. MMSS_DP_AUDIO_TIMESTAMP_0,
  1839. MMSS_DP_AUDIO_TIMESTAMP_1,
  1840. MMSS_DP_AUDIO_TIMESTAMP_1,
  1841. },
  1842. {
  1843. MMSS_DP_AUDIO_INFOFRAME_0,
  1844. MMSS_DP_AUDIO_INFOFRAME_1,
  1845. MMSS_DP_AUDIO_INFOFRAME_1,
  1846. },
  1847. {
  1848. MMSS_DP_AUDIO_COPYMANAGEMENT_0,
  1849. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1850. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1851. },
  1852. {
  1853. MMSS_DP_AUDIO_ISRC_0,
  1854. MMSS_DP_AUDIO_ISRC_1,
  1855. MMSS_DP_AUDIO_ISRC_1,
  1856. },
  1857. };
  1858. if (!audio)
  1859. return;
  1860. catalog = dp_catalog_get_priv(audio);
  1861. catalog->audio_map = sdp_map;
  1862. }
  1863. static void dp_catalog_audio_config_sdp(struct dp_catalog_audio *audio)
  1864. {
  1865. struct dp_catalog_private *catalog;
  1866. struct dp_io_data *io_data;
  1867. u32 sdp_cfg = 0, sdp_cfg_off = 0;
  1868. u32 sdp_cfg2 = 0, sdp_cfg2_off = 0;
  1869. if (!audio)
  1870. return;
  1871. if (audio->stream_id >= DP_STREAM_MAX) {
  1872. DP_ERR("invalid stream id:%d\n", audio->stream_id);
  1873. return;
  1874. }
  1875. if (audio->stream_id == DP_STREAM_1) {
  1876. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1877. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1878. }
  1879. catalog = dp_catalog_get_priv(audio);
  1880. io_data = catalog->io.dp_link;
  1881. sdp_cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  1882. /* AUDIO_TIMESTAMP_SDP_EN */
  1883. sdp_cfg |= BIT(1);
  1884. /* AUDIO_STREAM_SDP_EN */
  1885. sdp_cfg |= BIT(2);
  1886. /* AUDIO_COPY_MANAGEMENT_SDP_EN */
  1887. sdp_cfg |= BIT(5);
  1888. /* AUDIO_ISRC_SDP_EN */
  1889. sdp_cfg |= BIT(6);
  1890. /* AUDIO_INFOFRAME_SDP_EN */
  1891. sdp_cfg |= BIT(20);
  1892. DP_DEBUG("sdp_cfg = 0x%x\n", sdp_cfg);
  1893. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, sdp_cfg);
  1894. sdp_cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg_off);
  1895. /* IFRM_REGSRC -> Do not use reg values */
  1896. sdp_cfg2 &= ~BIT(0);
  1897. /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
  1898. sdp_cfg2 &= ~BIT(1);
  1899. DP_DEBUG("sdp_cfg2 = 0x%x\n", sdp_cfg2);
  1900. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg_off, sdp_cfg2);
  1901. }
  1902. static void dp_catalog_audio_get_header(struct dp_catalog_audio *audio)
  1903. {
  1904. struct dp_catalog_private *catalog;
  1905. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1906. struct dp_io_data *io_data;
  1907. enum dp_catalog_audio_sdp_type sdp;
  1908. enum dp_catalog_audio_header_type header;
  1909. if (!audio)
  1910. return;
  1911. catalog = dp_catalog_get_priv(audio);
  1912. io_data = catalog->io.dp_link;
  1913. sdp_map = catalog->audio_map;
  1914. sdp = audio->sdp_type;
  1915. header = audio->sdp_header;
  1916. audio->data = dp_read(sdp_map[sdp][header]);
  1917. }
  1918. static void dp_catalog_audio_set_header(struct dp_catalog_audio *audio)
  1919. {
  1920. struct dp_catalog_private *catalog;
  1921. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1922. struct dp_io_data *io_data;
  1923. enum dp_catalog_audio_sdp_type sdp;
  1924. enum dp_catalog_audio_header_type header;
  1925. u32 data;
  1926. if (!audio)
  1927. return;
  1928. catalog = dp_catalog_get_priv(audio);
  1929. io_data = catalog->io.dp_link;
  1930. sdp_map = catalog->audio_map;
  1931. sdp = audio->sdp_type;
  1932. header = audio->sdp_header;
  1933. data = audio->data;
  1934. dp_write(sdp_map[sdp][header], data);
  1935. }
  1936. static void dp_catalog_audio_config_acr(struct dp_catalog_audio *audio)
  1937. {
  1938. struct dp_catalog_private *catalog;
  1939. struct dp_io_data *io_data;
  1940. u32 acr_ctrl, select;
  1941. catalog = dp_catalog_get_priv(audio);
  1942. select = audio->data;
  1943. io_data = catalog->io.dp_link;
  1944. acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
  1945. DP_DEBUG("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl);
  1946. dp_write(MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
  1947. }
  1948. static void dp_catalog_audio_enable(struct dp_catalog_audio *audio)
  1949. {
  1950. struct dp_catalog_private *catalog;
  1951. struct dp_io_data *io_data;
  1952. bool enable;
  1953. u32 audio_ctrl;
  1954. catalog = dp_catalog_get_priv(audio);
  1955. io_data = catalog->io.dp_link;
  1956. enable = !!audio->data;
  1957. audio_ctrl = dp_read(MMSS_DP_AUDIO_CFG);
  1958. if (enable)
  1959. audio_ctrl |= BIT(0);
  1960. else
  1961. audio_ctrl &= ~BIT(0);
  1962. DP_DEBUG("dp_audio_cfg = 0x%x\n", audio_ctrl);
  1963. dp_write(MMSS_DP_AUDIO_CFG, audio_ctrl);
  1964. /* make sure audio engine is disabled */
  1965. wmb();
  1966. }
  1967. static void dp_catalog_config_spd_header(struct dp_catalog_panel *panel)
  1968. {
  1969. struct dp_catalog_private *catalog;
  1970. struct dp_io_data *io_data;
  1971. u32 value, new_value, offset = 0;
  1972. u8 parity_byte;
  1973. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  1974. return;
  1975. catalog = dp_catalog_get_priv(panel);
  1976. io_data = catalog->io.dp_link;
  1977. if (panel->stream_id == DP_STREAM_1)
  1978. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  1979. /* Config header and parity byte 1 */
  1980. value = dp_read(MMSS_DP_GENERIC1_0 + offset);
  1981. new_value = 0x83;
  1982. parity_byte = dp_header_get_parity(new_value);
  1983. value |= ((new_value << HEADER_BYTE_1_BIT)
  1984. | (parity_byte << PARITY_BYTE_1_BIT));
  1985. DP_DEBUG("Header Byte 1: value = 0x%x, parity_byte = 0x%x\n",
  1986. value, parity_byte);
  1987. dp_write(MMSS_DP_GENERIC1_0 + offset, value);
  1988. /* Config header and parity byte 2 */
  1989. value = dp_read(MMSS_DP_GENERIC1_1 + offset);
  1990. new_value = 0x1b;
  1991. parity_byte = dp_header_get_parity(new_value);
  1992. value |= ((new_value << HEADER_BYTE_2_BIT)
  1993. | (parity_byte << PARITY_BYTE_2_BIT));
  1994. DP_DEBUG("Header Byte 2: value = 0x%x, parity_byte = 0x%x\n",
  1995. value, parity_byte);
  1996. dp_write(MMSS_DP_GENERIC1_1 + offset, value);
  1997. /* Config header and parity byte 3 */
  1998. value = dp_read(MMSS_DP_GENERIC1_1 + offset);
  1999. new_value = (0x0 | (0x12 << 2));
  2000. parity_byte = dp_header_get_parity(new_value);
  2001. value |= ((new_value << HEADER_BYTE_3_BIT)
  2002. | (parity_byte << PARITY_BYTE_3_BIT));
  2003. DP_DEBUG("Header Byte 3: value = 0x%x, parity_byte = 0x%x\n",
  2004. new_value, parity_byte);
  2005. dp_write(MMSS_DP_GENERIC1_1 + offset, value);
  2006. }
  2007. static void dp_catalog_panel_config_spd(struct dp_catalog_panel *panel)
  2008. {
  2009. struct dp_catalog_private *catalog;
  2010. struct dp_io_data *io_data;
  2011. u32 spd_cfg = 0, spd_cfg2 = 0;
  2012. u8 *vendor = NULL, *product = NULL;
  2013. u32 offset = 0;
  2014. u32 sdp_cfg_off = 0;
  2015. u32 sdp_cfg2_off = 0;
  2016. /*
  2017. * Source Device Information
  2018. * 00h unknown
  2019. * 01h Digital STB
  2020. * 02h DVD
  2021. * 03h D-VHS
  2022. * 04h HDD Video
  2023. * 05h DVC
  2024. * 06h DSC
  2025. * 07h Video CD
  2026. * 08h Game
  2027. * 09h PC general
  2028. * 0ah Bluray-Disc
  2029. * 0bh Super Audio CD
  2030. * 0ch HD DVD
  2031. * 0dh PMP
  2032. * 0eh-ffh reserved
  2033. */
  2034. u32 device_type = 0;
  2035. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2036. return;
  2037. catalog = dp_catalog_get_priv(panel);
  2038. io_data = catalog->io.dp_link;
  2039. if (panel->stream_id == DP_STREAM_1)
  2040. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2041. dp_catalog_config_spd_header(panel);
  2042. vendor = panel->spd_vendor_name;
  2043. product = panel->spd_product_description;
  2044. dp_write(MMSS_DP_GENERIC1_2 + offset,
  2045. ((vendor[0] & 0x7f) |
  2046. ((vendor[1] & 0x7f) << 8) |
  2047. ((vendor[2] & 0x7f) << 16) |
  2048. ((vendor[3] & 0x7f) << 24)));
  2049. dp_write(MMSS_DP_GENERIC1_3 + offset,
  2050. ((vendor[4] & 0x7f) |
  2051. ((vendor[5] & 0x7f) << 8) |
  2052. ((vendor[6] & 0x7f) << 16) |
  2053. ((vendor[7] & 0x7f) << 24)));
  2054. dp_write(MMSS_DP_GENERIC1_4 + offset,
  2055. ((product[0] & 0x7f) |
  2056. ((product[1] & 0x7f) << 8) |
  2057. ((product[2] & 0x7f) << 16) |
  2058. ((product[3] & 0x7f) << 24)));
  2059. dp_write(MMSS_DP_GENERIC1_5 + offset,
  2060. ((product[4] & 0x7f) |
  2061. ((product[5] & 0x7f) << 8) |
  2062. ((product[6] & 0x7f) << 16) |
  2063. ((product[7] & 0x7f) << 24)));
  2064. dp_write(MMSS_DP_GENERIC1_6 + offset,
  2065. ((product[8] & 0x7f) |
  2066. ((product[9] & 0x7f) << 8) |
  2067. ((product[10] & 0x7f) << 16) |
  2068. ((product[11] & 0x7f) << 24)));
  2069. dp_write(MMSS_DP_GENERIC1_7 + offset,
  2070. ((product[12] & 0x7f) |
  2071. ((product[13] & 0x7f) << 8) |
  2072. ((product[14] & 0x7f) << 16) |
  2073. ((product[15] & 0x7f) << 24)));
  2074. dp_write(MMSS_DP_GENERIC1_8 + offset, device_type);
  2075. dp_write(MMSS_DP_GENERIC1_9 + offset, 0x00);
  2076. if (panel->stream_id == DP_STREAM_1) {
  2077. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  2078. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  2079. }
  2080. spd_cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  2081. /* GENERIC1_SDP for SPD Infoframe */
  2082. spd_cfg |= BIT(18);
  2083. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, spd_cfg);
  2084. spd_cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  2085. /* 28 data bytes for SPD Infoframe with GENERIC1 set */
  2086. spd_cfg2 |= BIT(17);
  2087. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, spd_cfg2);
  2088. dp_catalog_panel_sdp_update(panel);
  2089. }
  2090. static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog)
  2091. {
  2092. struct dp_parser *parser = catalog->parser;
  2093. dp_catalog_fill_io_buf(dp_ahb);
  2094. dp_catalog_fill_io_buf(dp_aux);
  2095. dp_catalog_fill_io_buf(dp_link);
  2096. dp_catalog_fill_io_buf(dp_p0);
  2097. dp_catalog_fill_io_buf(dp_phy);
  2098. dp_catalog_fill_io_buf(dp_ln_tx0);
  2099. dp_catalog_fill_io_buf(dp_ln_tx1);
  2100. dp_catalog_fill_io_buf(dp_pll);
  2101. dp_catalog_fill_io_buf(usb3_dp_com);
  2102. dp_catalog_fill_io_buf(dp_mmss_cc);
  2103. dp_catalog_fill_io_buf(hdcp_physical);
  2104. dp_catalog_fill_io_buf(dp_p1);
  2105. dp_catalog_fill_io_buf(dp_tcsr);
  2106. }
  2107. static void dp_catalog_get_io(struct dp_catalog_private *catalog)
  2108. {
  2109. struct dp_parser *parser = catalog->parser;
  2110. dp_catalog_fill_io(dp_ahb);
  2111. dp_catalog_fill_io(dp_aux);
  2112. dp_catalog_fill_io(dp_link);
  2113. dp_catalog_fill_io(dp_p0);
  2114. dp_catalog_fill_io(dp_phy);
  2115. dp_catalog_fill_io(dp_ln_tx0);
  2116. dp_catalog_fill_io(dp_ln_tx1);
  2117. dp_catalog_fill_io(dp_pll);
  2118. dp_catalog_fill_io(usb3_dp_com);
  2119. dp_catalog_fill_io(dp_mmss_cc);
  2120. dp_catalog_fill_io(hdcp_physical);
  2121. dp_catalog_fill_io(dp_p1);
  2122. dp_catalog_fill_io(dp_tcsr);
  2123. }
  2124. static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode)
  2125. {
  2126. struct dp_catalog_private *catalog;
  2127. if (!dp_catalog) {
  2128. DP_ERR("invalid input\n");
  2129. return;
  2130. }
  2131. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2132. dp_catalog);
  2133. strlcpy(catalog->exe_mode, mode, sizeof(catalog->exe_mode));
  2134. if (!strcmp(catalog->exe_mode, "hw"))
  2135. catalog->parser->clear_io_buf(catalog->parser);
  2136. else
  2137. dp_catalog_get_io_buf(catalog);
  2138. if (!strcmp(catalog->exe_mode, "hw") ||
  2139. !strcmp(catalog->exe_mode, "all")) {
  2140. catalog->read = dp_read_hw;
  2141. catalog->write = dp_write_hw;
  2142. dp_catalog->sub->read = dp_read_sub_hw;
  2143. dp_catalog->sub->write = dp_write_sub_hw;
  2144. } else {
  2145. catalog->read = dp_read_sw;
  2146. catalog->write = dp_write_sw;
  2147. dp_catalog->sub->read = dp_read_sub_sw;
  2148. dp_catalog->sub->write = dp_write_sub_sw;
  2149. }
  2150. }
  2151. static int dp_catalog_init(struct device *dev, struct dp_catalog *dp_catalog,
  2152. struct dp_parser *parser)
  2153. {
  2154. int rc = 0;
  2155. struct dp_catalog_private *catalog = container_of(dp_catalog,
  2156. struct dp_catalog_private, dp_catalog);
  2157. switch (parser->hw_cfg.phy_version) {
  2158. case DP_PHY_VERSION_4_2_0:
  2159. dp_catalog->sub = dp_catalog_get_v420(dev, dp_catalog,
  2160. &catalog->io);
  2161. break;
  2162. case DP_PHY_VERSION_2_0_0:
  2163. dp_catalog->sub = dp_catalog_get_v200(dev, dp_catalog,
  2164. &catalog->io);
  2165. break;
  2166. default:
  2167. goto end;
  2168. }
  2169. if (IS_ERR(dp_catalog->sub)) {
  2170. rc = PTR_ERR(dp_catalog->sub);
  2171. dp_catalog->sub = NULL;
  2172. } else {
  2173. dp_catalog->sub->read = dp_read_sub_hw;
  2174. dp_catalog->sub->write = dp_write_sub_hw;
  2175. }
  2176. end:
  2177. return rc;
  2178. }
  2179. void dp_catalog_put(struct dp_catalog *dp_catalog)
  2180. {
  2181. struct dp_catalog_private *catalog;
  2182. if (!dp_catalog)
  2183. return;
  2184. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2185. dp_catalog);
  2186. if (dp_catalog->sub && dp_catalog->sub->put)
  2187. dp_catalog->sub->put(dp_catalog);
  2188. catalog->parser->clear_io_buf(catalog->parser);
  2189. devm_kfree(catalog->dev, catalog);
  2190. }
  2191. struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
  2192. {
  2193. int rc = 0;
  2194. struct dp_catalog *dp_catalog;
  2195. struct dp_catalog_private *catalog;
  2196. struct dp_catalog_aux aux = {
  2197. .read_data = dp_catalog_aux_read_data,
  2198. .write_data = dp_catalog_aux_write_data,
  2199. .write_trans = dp_catalog_aux_write_trans,
  2200. .clear_trans = dp_catalog_aux_clear_trans,
  2201. .reset = dp_catalog_aux_reset,
  2202. .update_aux_cfg = dp_catalog_aux_update_cfg,
  2203. .enable = dp_catalog_aux_enable,
  2204. .setup = dp_catalog_aux_setup,
  2205. .get_irq = dp_catalog_aux_get_irq,
  2206. .clear_hw_interrupts = dp_catalog_aux_clear_hw_interrupts,
  2207. };
  2208. struct dp_catalog_ctrl ctrl = {
  2209. .state_ctrl = dp_catalog_ctrl_state_ctrl,
  2210. .config_ctrl = dp_catalog_ctrl_config_ctrl,
  2211. .lane_mapping = dp_catalog_ctrl_lane_mapping,
  2212. .lane_pnswap = dp_catalog_ctrl_lane_pnswap,
  2213. .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl,
  2214. .set_pattern = dp_catalog_ctrl_set_pattern,
  2215. .reset = dp_catalog_ctrl_reset,
  2216. .usb_reset = dp_catalog_ctrl_usb_reset,
  2217. .mainlink_ready = dp_catalog_ctrl_mainlink_ready,
  2218. .enable_irq = dp_catalog_ctrl_enable_irq,
  2219. .phy_reset = dp_catalog_ctrl_phy_reset,
  2220. .phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg,
  2221. .update_vx_px = dp_catalog_ctrl_update_vx_px,
  2222. .get_interrupt = dp_catalog_ctrl_get_interrupt,
  2223. .read_hdcp_status = dp_catalog_ctrl_read_hdcp_status,
  2224. .send_phy_pattern = dp_catalog_ctrl_send_phy_pattern,
  2225. .read_phy_pattern = dp_catalog_ctrl_read_phy_pattern,
  2226. .mst_config = dp_catalog_ctrl_mst_config,
  2227. .trigger_act = dp_catalog_ctrl_trigger_act,
  2228. .read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
  2229. .channel_alloc = dp_catalog_ctrl_channel_alloc,
  2230. .update_rg = dp_catalog_ctrl_update_rg,
  2231. .channel_dealloc = dp_catalog_ctrl_channel_dealloc,
  2232. .fec_config = dp_catalog_ctrl_fec_config,
  2233. .mainlink_levels = dp_catalog_ctrl_mainlink_levels,
  2234. .late_phy_init = dp_catalog_ctrl_late_phy_init,
  2235. };
  2236. struct dp_catalog_hpd hpd = {
  2237. .config_hpd = dp_catalog_hpd_config_hpd,
  2238. .get_interrupt = dp_catalog_hpd_get_interrupt,
  2239. };
  2240. struct dp_catalog_audio audio = {
  2241. .init = dp_catalog_audio_init,
  2242. .config_acr = dp_catalog_audio_config_acr,
  2243. .enable = dp_catalog_audio_enable,
  2244. .config_sdp = dp_catalog_audio_config_sdp,
  2245. .set_header = dp_catalog_audio_set_header,
  2246. .get_header = dp_catalog_audio_get_header,
  2247. };
  2248. struct dp_catalog_panel panel = {
  2249. .timing_cfg = dp_catalog_panel_timing_cfg,
  2250. .config_hdr = dp_catalog_panel_config_hdr,
  2251. .config_sdp = dp_catalog_panel_config_sdp,
  2252. .tpg_config = dp_catalog_panel_tpg_cfg,
  2253. .config_spd = dp_catalog_panel_config_spd,
  2254. .config_misc = dp_catalog_panel_config_misc,
  2255. .set_colorspace = dp_catalog_panel_set_colorspace,
  2256. .config_msa = dp_catalog_panel_config_msa,
  2257. .update_transfer_unit = dp_catalog_panel_update_transfer_unit,
  2258. .config_ctrl = dp_catalog_panel_config_ctrl,
  2259. .config_dto = dp_catalog_panel_config_dto,
  2260. .dsc_cfg = dp_catalog_panel_dsc_cfg,
  2261. .pps_flush = dp_catalog_panel_pps_flush,
  2262. .dhdr_flush = dp_catalog_panel_dhdr_flush,
  2263. .dhdr_busy = dp_catalog_panel_dhdr_busy,
  2264. };
  2265. if (!dev || !parser) {
  2266. DP_ERR("invalid input\n");
  2267. rc = -EINVAL;
  2268. goto error;
  2269. }
  2270. catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
  2271. if (!catalog) {
  2272. rc = -ENOMEM;
  2273. goto error;
  2274. }
  2275. catalog->dev = dev;
  2276. catalog->parser = parser;
  2277. catalog->read = dp_read_hw;
  2278. catalog->write = dp_write_hw;
  2279. dp_catalog_get_io(catalog);
  2280. strlcpy(catalog->exe_mode, "hw", sizeof(catalog->exe_mode));
  2281. dp_catalog = &catalog->dp_catalog;
  2282. dp_catalog->aux = aux;
  2283. dp_catalog->ctrl = ctrl;
  2284. dp_catalog->hpd = hpd;
  2285. dp_catalog->audio = audio;
  2286. dp_catalog->panel = panel;
  2287. rc = dp_catalog_init(dev, dp_catalog, parser);
  2288. if (rc) {
  2289. dp_catalog_put(dp_catalog);
  2290. goto error;
  2291. }
  2292. dp_catalog->set_exe_mode = dp_catalog_set_exe_mode;
  2293. dp_catalog->get_reg_dump = dp_catalog_reg_dump;
  2294. return dp_catalog;
  2295. error:
  2296. return ERR_PTR(rc);
  2297. }