dp_main.c 149 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <hal_api.h>
  23. #include <hif.h>
  24. #include <htt.h>
  25. #include <wdi_event.h>
  26. #include <queue.h>
  27. #include "dp_htt.h"
  28. #include "dp_types.h"
  29. #include "dp_internal.h"
  30. #include "dp_tx.h"
  31. #include "dp_tx_desc.h"
  32. #include "dp_rx.h"
  33. #include <cdp_txrx_handle.h>
  34. #include <wlan_cfg.h>
  35. #include "cdp_txrx_cmn_struct.h"
  36. #include <qdf_util.h>
  37. #include "dp_peer.h"
  38. #include "dp_rx_mon.h"
  39. #include "htt_stats.h"
  40. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  41. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  42. #include "cdp_txrx_flow_ctrl_v2.h"
  43. #else
  44. static inline void
  45. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  46. {
  47. return;
  48. }
  49. #endif
  50. #include <ol_cfg.h>
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  57. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  58. #define DP_MAX_MCS_STRING_LEN 30
  59. #define DP_CURR_FW_STATS_AVAIL 19
  60. #define DP_HTT_DBG_EXT_STATS_MAX 256
  61. #ifdef IPA_OFFLOAD
  62. /* Exclude IPA rings from the interrupt context */
  63. #define TX_RING_MASK_VAL 0x7
  64. #define RX_RING_MASK_VAL 0x7
  65. #else
  66. #define TX_RING_MASK_VAL 0xF
  67. #define RX_RING_MASK_VAL 0xF
  68. #endif
  69. /**
  70. * default_dscp_tid_map - Default DSCP-TID mapping
  71. *
  72. * DSCP TID AC
  73. * 000000 0 WME_AC_BE
  74. * 001000 1 WME_AC_BK
  75. * 010000 1 WME_AC_BK
  76. * 011000 0 WME_AC_BE
  77. * 100000 5 WME_AC_VI
  78. * 101000 5 WME_AC_VI
  79. * 110000 6 WME_AC_VO
  80. * 111000 6 WME_AC_VO
  81. */
  82. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  83. 0, 0, 0, 0, 0, 0, 0, 0,
  84. 1, 1, 1, 1, 1, 1, 1, 1,
  85. 1, 1, 1, 1, 1, 1, 1, 1,
  86. 0, 0, 0, 0, 0, 0, 0, 0,
  87. 5, 5, 5, 5, 5, 5, 5, 5,
  88. 5, 5, 5, 5, 5, 5, 5, 5,
  89. 6, 6, 6, 6, 6, 6, 6, 6,
  90. 6, 6, 6, 6, 6, 6, 6, 6,
  91. };
  92. /*
  93. * struct dp_rate_debug
  94. *
  95. * @mcs_type: print string for a given mcs
  96. * @valid: valid mcs rate?
  97. */
  98. struct dp_rate_debug {
  99. char mcs_type[DP_MAX_MCS_STRING_LEN];
  100. uint8_t valid;
  101. };
  102. #define MCS_VALID 1
  103. #define MCS_INVALID 0
  104. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  105. {
  106. {"CCK 11 Mbps Long ", MCS_VALID},
  107. {"CCK 5.5 Mbps Long ", MCS_VALID},
  108. {"CCK 2 Mbps Long ", MCS_VALID},
  109. {"CCK 1 Mbps Long ", MCS_VALID},
  110. {"CCK 11 Mbps Short ", MCS_VALID},
  111. {"CCK 5.5 Mbps Short", MCS_VALID},
  112. {"CCK 2 Mbps Short ", MCS_VALID},
  113. {"INVALID ", MCS_INVALID},
  114. {"INVALID ", MCS_INVALID},
  115. {"INVALID ", MCS_INVALID},
  116. {"INVALID ", MCS_INVALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_VALID},
  119. },
  120. {
  121. {"OFDM 48 Mbps", MCS_VALID},
  122. {"OFDM 24 Mbps", MCS_VALID},
  123. {"OFDM 12 Mbps", MCS_VALID},
  124. {"OFDM 6 Mbps ", MCS_VALID},
  125. {"OFDM 54 Mbps", MCS_VALID},
  126. {"OFDM 36 Mbps", MCS_VALID},
  127. {"OFDM 18 Mbps", MCS_VALID},
  128. {"OFDM 9 Mbps ", MCS_VALID},
  129. {"INVALID ", MCS_INVALID},
  130. {"INVALID ", MCS_INVALID},
  131. {"INVALID ", MCS_INVALID},
  132. {"INVALID ", MCS_INVALID},
  133. {"INVALID ", MCS_VALID},
  134. },
  135. {
  136. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  137. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  138. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  139. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  140. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  141. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  142. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  143. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  144. {"INVALID ", MCS_INVALID},
  145. {"INVALID ", MCS_INVALID},
  146. {"INVALID ", MCS_INVALID},
  147. {"INVALID ", MCS_INVALID},
  148. {"INVALID ", MCS_VALID},
  149. },
  150. {
  151. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  152. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  153. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  154. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  155. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  156. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  157. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  158. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  159. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  161. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  162. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  163. {"INVALID ", MCS_VALID},
  164. },
  165. {
  166. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  167. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  168. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  169. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  170. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  171. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  172. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  173. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  174. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  176. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  177. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  178. {"INVALID ", MCS_VALID},
  179. }
  180. };
  181. /**
  182. * @brief Cpu ring map types
  183. */
  184. enum dp_cpu_ring_map_types {
  185. DP_DEFAULT_MAP,
  186. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  187. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  188. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  189. DP_CPU_RING_MAP_MAX
  190. };
  191. /**
  192. * @brief Cpu to tx ring map
  193. */
  194. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  195. {0x0, 0x1, 0x2, 0x0},
  196. {0x1, 0x2, 0x1, 0x2},
  197. {0x0, 0x2, 0x0, 0x2},
  198. {0x2, 0x2, 0x2, 0x2}
  199. };
  200. /**
  201. * @brief Select the type of statistics
  202. */
  203. enum dp_stats_type {
  204. STATS_FW = 0,
  205. STATS_HOST = 1,
  206. STATS_TYPE_MAX = 2,
  207. };
  208. /**
  209. * @brief General Firmware statistics options
  210. *
  211. */
  212. enum dp_fw_stats {
  213. TXRX_FW_STATS_INVALID = -1,
  214. };
  215. /**
  216. * dp_stats_mapping_table - Firmware and Host statistics
  217. * currently supported
  218. */
  219. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  220. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  221. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  222. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  223. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  224. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  231. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  239. /* Last ENUM for HTT FW STATS */
  240. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  241. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  242. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  243. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  244. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  245. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  247. };
  248. /**
  249. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  250. * @ring_num: ring num of the ring being queried
  251. * @grp_mask: the grp_mask array for the ring type in question.
  252. *
  253. * The grp_mask array is indexed by group number and the bit fields correspond
  254. * to ring numbers. We are finding which interrupt group a ring belongs to.
  255. *
  256. * Return: the index in the grp_mask array with the ring number.
  257. * -QDF_STATUS_E_NOENT if no entry is found
  258. */
  259. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  260. {
  261. int ext_group_num;
  262. int mask = 1 << ring_num;
  263. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  264. ext_group_num++) {
  265. if (mask & grp_mask[ext_group_num])
  266. return ext_group_num;
  267. }
  268. return -QDF_STATUS_E_NOENT;
  269. }
  270. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  271. enum hal_ring_type ring_type,
  272. int ring_num)
  273. {
  274. int *grp_mask;
  275. switch (ring_type) {
  276. case WBM2SW_RELEASE:
  277. /* dp_tx_comp_handler - soc->tx_comp_ring */
  278. if (ring_num < 3)
  279. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  280. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  281. else if (ring_num == 3) {
  282. /* sw treats this as a separate ring type */
  283. grp_mask = &soc->wlan_cfg_ctx->
  284. int_rx_wbm_rel_ring_mask[0];
  285. ring_num = 0;
  286. } else {
  287. qdf_assert(0);
  288. return -QDF_STATUS_E_NOENT;
  289. }
  290. break;
  291. case REO_EXCEPTION:
  292. /* dp_rx_err_process - &soc->reo_exception_ring */
  293. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  294. break;
  295. case REO_DST:
  296. /* dp_rx_process - soc->reo_dest_ring */
  297. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  298. break;
  299. case REO_STATUS:
  300. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  301. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  302. break;
  303. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  304. case RXDMA_MONITOR_STATUS:
  305. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  306. case RXDMA_MONITOR_DST:
  307. /* dp_mon_process */
  308. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  309. break;
  310. case RXDMA_MONITOR_BUF:
  311. case RXDMA_BUF:
  312. /* TODO: support low_thresh interrupt */
  313. return -QDF_STATUS_E_NOENT;
  314. break;
  315. case TCL_DATA:
  316. case TCL_CMD:
  317. case REO_CMD:
  318. case SW2WBM_RELEASE:
  319. case WBM_IDLE_LINK:
  320. /* normally empty SW_TO_HW rings */
  321. return -QDF_STATUS_E_NOENT;
  322. break;
  323. case TCL_STATUS:
  324. case REO_REINJECT:
  325. case RXDMA_DST:
  326. /* misc unused rings */
  327. return -QDF_STATUS_E_NOENT;
  328. break;
  329. case CE_SRC:
  330. case CE_DST:
  331. case CE_DST_STATUS:
  332. /* CE_rings - currently handled by hif */
  333. default:
  334. return -QDF_STATUS_E_NOENT;
  335. break;
  336. }
  337. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  338. }
  339. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  340. *ring_params, int ring_type, int ring_num)
  341. {
  342. int msi_group_number;
  343. int msi_data_count;
  344. int ret;
  345. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  346. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  347. &msi_data_count, &msi_data_start,
  348. &msi_irq_start);
  349. if (ret)
  350. return;
  351. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  352. ring_num);
  353. if (msi_group_number < 0) {
  354. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  355. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  356. ring_type, ring_num);
  357. ring_params->msi_addr = 0;
  358. ring_params->msi_data = 0;
  359. return;
  360. }
  361. if (msi_group_number > msi_data_count) {
  362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  363. FL("2 msi_groups will share an msi; msi_group_num %d"),
  364. msi_group_number);
  365. QDF_ASSERT(0);
  366. }
  367. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  368. ring_params->msi_addr = addr_low;
  369. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  370. ring_params->msi_data = (msi_group_number % msi_data_count)
  371. + msi_data_start;
  372. ring_params->flags |= HAL_SRNG_MSI_INTR;
  373. }
  374. /**
  375. * dp_print_ast_stats() - Dump AST table contents
  376. * @soc: Datapath soc handle
  377. *
  378. * return void
  379. */
  380. #ifdef FEATURE_WDS
  381. static void dp_print_ast_stats(struct dp_soc *soc)
  382. {
  383. uint8_t i;
  384. uint8_t num_entries = 0;
  385. struct dp_vdev *vdev;
  386. struct dp_pdev *pdev;
  387. struct dp_peer *peer;
  388. struct dp_ast_entry *ase, *tmp_ase;
  389. DP_PRINT_STATS("AST Stats:");
  390. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  391. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  392. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  393. DP_PRINT_STATS("AST Table:");
  394. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  395. pdev = soc->pdev_list[i];
  396. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  397. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  398. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  399. DP_PRINT_STATS("%6d mac_addr = %pM"
  400. " peer_mac_addr = %pM"
  401. " type = %d"
  402. " next_hop = %d"
  403. " is_active = %d"
  404. " is_bss = %d",
  405. ++num_entries,
  406. ase->mac_addr.raw,
  407. ase->peer->mac_addr.raw,
  408. ase->type,
  409. ase->next_hop,
  410. ase->is_active,
  411. ase->is_bss);
  412. }
  413. }
  414. }
  415. }
  416. }
  417. #else
  418. static void dp_print_ast_stats(struct dp_soc *soc)
  419. {
  420. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  421. return;
  422. }
  423. #endif
  424. /*
  425. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  426. */
  427. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  428. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  429. {
  430. void *hal_soc = soc->hal_soc;
  431. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  432. /* TODO: See if we should get align size from hal */
  433. uint32_t ring_base_align = 8;
  434. struct hal_srng_params ring_params;
  435. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  436. /* TODO: Currently hal layer takes care of endianness related settings.
  437. * See if these settings need to passed from DP layer
  438. */
  439. ring_params.flags = 0;
  440. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  441. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  442. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  443. srng->hal_srng = NULL;
  444. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  445. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  446. soc->osdev, soc->osdev->dev, srng->alloc_size,
  447. &(srng->base_paddr_unaligned));
  448. if (!srng->base_vaddr_unaligned) {
  449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  450. FL("alloc failed - ring_type: %d, ring_num %d"),
  451. ring_type, ring_num);
  452. return QDF_STATUS_E_NOMEM;
  453. }
  454. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  455. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  456. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  457. ((unsigned long)(ring_params.ring_base_vaddr) -
  458. (unsigned long)srng->base_vaddr_unaligned);
  459. ring_params.num_entries = num_entries;
  460. if (soc->intr_mode == DP_INTR_MSI) {
  461. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  462. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  463. FL("Using MSI for ring_type: %d, ring_num %d"),
  464. ring_type, ring_num);
  465. } else {
  466. ring_params.msi_data = 0;
  467. ring_params.msi_addr = 0;
  468. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  469. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  470. ring_type, ring_num);
  471. }
  472. /*
  473. * Setup interrupt timer and batch counter thresholds for
  474. * interrupt mitigation based on ring type
  475. */
  476. if (ring_type == REO_DST) {
  477. ring_params.intr_timer_thres_us =
  478. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  479. ring_params.intr_batch_cntr_thres_entries =
  480. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  481. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  482. ring_params.intr_timer_thres_us =
  483. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  484. ring_params.intr_batch_cntr_thres_entries =
  485. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  486. } else {
  487. ring_params.intr_timer_thres_us =
  488. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  489. ring_params.intr_batch_cntr_thres_entries =
  490. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  491. }
  492. /* Enable low threshold interrupts for rx buffer rings (regular and
  493. * monitor buffer rings.
  494. * TODO: See if this is required for any other ring
  495. */
  496. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  497. /* TODO: Setting low threshold to 1/8th of ring size
  498. * see if this needs to be configurable
  499. */
  500. ring_params.low_threshold = num_entries >> 3;
  501. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  502. ring_params.intr_timer_thres_us = 0x1000;
  503. }
  504. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  505. mac_id, &ring_params);
  506. return 0;
  507. }
  508. /**
  509. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  510. * Any buffers allocated and attached to ring entries are expected to be freed
  511. * before calling this function.
  512. */
  513. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  514. int ring_type, int ring_num)
  515. {
  516. if (!srng->hal_srng) {
  517. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  518. FL("Ring type: %d, num:%d not setup"),
  519. ring_type, ring_num);
  520. return;
  521. }
  522. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  523. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  524. srng->alloc_size,
  525. srng->base_vaddr_unaligned,
  526. srng->base_paddr_unaligned, 0);
  527. }
  528. #ifdef IPA_OFFLOAD
  529. /**
  530. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  531. * @soc: data path instance
  532. * @pdev: core txrx pdev context
  533. *
  534. * Free allocated TX buffers with WBM SRNG
  535. *
  536. * Return: none
  537. */
  538. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  539. {
  540. int idx;
  541. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  542. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  543. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  544. }
  545. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  546. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  547. }
  548. /**
  549. * dp_rx_ipa_uc_detach - free autonomy RX resources
  550. * @soc: data path instance
  551. * @pdev: core txrx pdev context
  552. *
  553. * This function will detach DP RX into main device context
  554. * will free DP Rx resources.
  555. *
  556. * Return: none
  557. */
  558. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  559. {
  560. }
  561. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  562. {
  563. /* TX resource detach */
  564. dp_tx_ipa_uc_detach(soc, pdev);
  565. /* RX resource detach */
  566. dp_rx_ipa_uc_detach(soc, pdev);
  567. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  568. return QDF_STATUS_SUCCESS; /* success */
  569. }
  570. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  571. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  572. /**
  573. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  574. * @soc: data path instance
  575. * @pdev: Physical device handle
  576. *
  577. * Allocate TX buffer from non-cacheable memory
  578. * Attache allocated TX buffers with WBM SRNG
  579. *
  580. * Return: int
  581. */
  582. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  583. {
  584. uint32_t tx_buffer_count;
  585. uint32_t ring_base_align = 8;
  586. void *buffer_vaddr_unaligned;
  587. void *buffer_vaddr;
  588. qdf_dma_addr_t buffer_paddr_unaligned;
  589. qdf_dma_addr_t buffer_paddr;
  590. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  591. uint32_t paddr_lo;
  592. uint32_t paddr_hi;
  593. void *ring_entry;
  594. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  595. int retval = QDF_STATUS_SUCCESS;
  596. /*
  597. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  598. * unsigned int uc_tx_buf_sz =
  599. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  600. */
  601. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  602. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  603. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  604. "requested %d buffers to be posted to wbm ring",
  605. ring_size);
  606. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  607. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  608. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  610. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  611. return -ENOMEM;
  612. }
  613. hal_srng_access_start(soc->hal_soc, wbm_srng);
  614. /* Allocate TX buffers as many as possible */
  615. for (tx_buffer_count = 0;
  616. tx_buffer_count < ring_size; tx_buffer_count++) {
  617. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  618. if (!ring_entry) {
  619. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  620. "Failed to get WBM ring entry\n");
  621. goto fail;
  622. }
  623. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  624. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  625. if (!buffer_vaddr_unaligned) {
  626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  627. "IPA WDI TX buffer alloc fail %d allocated\n",
  628. tx_buffer_count);
  629. break;
  630. }
  631. buffer_vaddr = buffer_vaddr_unaligned +
  632. ((unsigned long)buffer_vaddr_unaligned %
  633. ring_base_align);
  634. buffer_paddr = buffer_paddr_unaligned +
  635. ((unsigned long)(buffer_vaddr) -
  636. (unsigned long)buffer_vaddr_unaligned);
  637. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  638. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  639. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  640. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  641. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  642. buffer_vaddr;
  643. }
  644. hal_srng_access_end(soc->hal_soc, wbm_srng);
  645. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  646. return retval;
  647. fail:
  648. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  649. return retval;
  650. }
  651. /**
  652. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  653. * @soc: data path instance
  654. * @pdev: core txrx pdev context
  655. *
  656. * This function will attach a DP RX instance into the main
  657. * device (SOC) context.
  658. *
  659. * Return: QDF_STATUS_SUCCESS: success
  660. * QDF_STATUS_E_RESOURCES: Error return
  661. */
  662. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  663. {
  664. return QDF_STATUS_SUCCESS;
  665. }
  666. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  667. {
  668. int error;
  669. /* TX resource attach */
  670. error = dp_tx_ipa_uc_attach(soc, pdev);
  671. if (error) {
  672. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  673. "DP IPA UC TX attach fail code %d\n", error);
  674. return error;
  675. }
  676. /* RX resource attach */
  677. error = dp_rx_ipa_uc_attach(soc, pdev);
  678. if (error) {
  679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  680. "DP IPA UC RX attach fail code %d\n", error);
  681. dp_tx_ipa_uc_detach(soc, pdev);
  682. return error;
  683. }
  684. return QDF_STATUS_SUCCESS; /* success */
  685. }
  686. #else
  687. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  688. {
  689. return QDF_STATUS_SUCCESS;
  690. }
  691. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  692. {
  693. return QDF_STATUS_SUCCESS;
  694. }
  695. #endif
  696. /* TODO: Need this interface from HIF */
  697. void *hif_get_hal_handle(void *hif_handle);
  698. /*
  699. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  700. * @dp_ctx: DP SOC handle
  701. * @budget: Number of frames/descriptors that can be processed in one shot
  702. *
  703. * Return: remaining budget/quota for the soc device
  704. */
  705. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  706. {
  707. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  708. struct dp_soc *soc = int_ctx->soc;
  709. int ring = 0;
  710. uint32_t work_done = 0;
  711. int budget = dp_budget;
  712. uint8_t tx_mask = int_ctx->tx_ring_mask;
  713. uint8_t rx_mask = int_ctx->rx_ring_mask;
  714. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  715. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  716. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  717. uint32_t remaining_quota = dp_budget;
  718. /* Process Tx completion interrupts first to return back buffers */
  719. while (tx_mask) {
  720. if (tx_mask & 0x1) {
  721. work_done =
  722. dp_tx_comp_handler(soc,
  723. soc->tx_comp_ring[ring].hal_srng,
  724. remaining_quota);
  725. QDF_TRACE(QDF_MODULE_ID_DP,
  726. QDF_TRACE_LEVEL_INFO,
  727. "tx mask 0x%x ring %d,"
  728. "budget %d, work_done %d",
  729. tx_mask, ring, budget, work_done);
  730. budget -= work_done;
  731. if (budget <= 0)
  732. goto budget_done;
  733. remaining_quota = budget;
  734. }
  735. tx_mask = tx_mask >> 1;
  736. ring++;
  737. }
  738. /* Process REO Exception ring interrupt */
  739. if (rx_err_mask) {
  740. work_done = dp_rx_err_process(soc,
  741. soc->reo_exception_ring.hal_srng,
  742. remaining_quota);
  743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  744. "REO Exception Ring: work_done %d budget %d",
  745. work_done, budget);
  746. budget -= work_done;
  747. if (budget <= 0) {
  748. goto budget_done;
  749. }
  750. remaining_quota = budget;
  751. }
  752. /* Process Rx WBM release ring interrupt */
  753. if (rx_wbm_rel_mask) {
  754. work_done = dp_rx_wbm_err_process(soc,
  755. soc->rx_rel_ring.hal_srng, remaining_quota);
  756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  757. "WBM Release Ring: work_done %d budget %d",
  758. work_done, budget);
  759. budget -= work_done;
  760. if (budget <= 0) {
  761. goto budget_done;
  762. }
  763. remaining_quota = budget;
  764. }
  765. /* Process Rx interrupts */
  766. if (rx_mask) {
  767. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  768. if (rx_mask & (1 << ring)) {
  769. work_done =
  770. dp_rx_process(int_ctx,
  771. soc->reo_dest_ring[ring].hal_srng,
  772. remaining_quota);
  773. QDF_TRACE(QDF_MODULE_ID_DP,
  774. QDF_TRACE_LEVEL_INFO,
  775. "rx mask 0x%x ring %d,"
  776. "work_done %d budget %d",
  777. rx_mask, ring, work_done,
  778. budget);
  779. budget -= work_done;
  780. if (budget <= 0)
  781. goto budget_done;
  782. remaining_quota = budget;
  783. }
  784. }
  785. }
  786. if (reo_status_mask)
  787. dp_reo_status_ring_handler(soc);
  788. /* Process LMAC interrupts */
  789. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  790. if (soc->pdev_list[ring] == NULL)
  791. continue;
  792. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  793. work_done =
  794. dp_mon_process(soc, ring, remaining_quota);
  795. budget -= work_done;
  796. remaining_quota = budget;
  797. }
  798. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  799. work_done =
  800. dp_rxdma_err_process(soc, ring,
  801. remaining_quota);
  802. budget -= work_done;
  803. }
  804. }
  805. qdf_lro_flush(int_ctx->lro_ctx);
  806. budget_done:
  807. return dp_budget - budget;
  808. }
  809. #ifdef DP_INTR_POLL_BASED
  810. /* dp_interrupt_timer()- timer poll for interrupts
  811. *
  812. * @arg: SoC Handle
  813. *
  814. * Return:
  815. *
  816. */
  817. static void dp_interrupt_timer(void *arg)
  818. {
  819. struct dp_soc *soc = (struct dp_soc *) arg;
  820. int i;
  821. if (qdf_atomic_read(&soc->cmn_init_done)) {
  822. for (i = 0;
  823. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  824. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  825. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  826. }
  827. }
  828. /*
  829. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  830. * @txrx_soc: DP SOC handle
  831. *
  832. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  833. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  834. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  835. *
  836. * Return: 0 for success. nonzero for failure.
  837. */
  838. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  839. {
  840. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  841. int i;
  842. soc->intr_mode = DP_INTR_POLL;
  843. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  844. soc->intr_ctx[i].dp_intr_id = i;
  845. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  846. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  847. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  848. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  849. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  850. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  851. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  852. soc->intr_ctx[i].soc = soc;
  853. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  854. }
  855. qdf_timer_init(soc->osdev, &soc->int_timer,
  856. dp_interrupt_timer, (void *)soc,
  857. QDF_TIMER_TYPE_WAKE_APPS);
  858. return QDF_STATUS_SUCCESS;
  859. }
  860. #ifdef CONFIG_MCL
  861. extern int con_mode_monitor;
  862. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  863. /*
  864. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  865. * @txrx_soc: DP SOC handle
  866. *
  867. * Call the appropriate attach function based on the mode of operation.
  868. * This is a WAR for enabling monitor mode.
  869. *
  870. * Return: 0 for success. nonzero for failure.
  871. */
  872. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  873. {
  874. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  876. FL("Attach interrupts in Poll mode"));
  877. return dp_soc_interrupt_attach_poll(txrx_soc);
  878. } else {
  879. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  880. FL("Attach interrupts in MSI mode"));
  881. return dp_soc_interrupt_attach(txrx_soc);
  882. }
  883. }
  884. #else
  885. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  886. {
  887. return dp_soc_interrupt_attach_poll(txrx_soc);
  888. }
  889. #endif
  890. #endif
  891. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  892. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  893. {
  894. int j;
  895. int num_irq = 0;
  896. int tx_mask =
  897. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  898. int rx_mask =
  899. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  900. int rx_mon_mask =
  901. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  902. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  903. soc->wlan_cfg_ctx, intr_ctx_num);
  904. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  905. soc->wlan_cfg_ctx, intr_ctx_num);
  906. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  907. soc->wlan_cfg_ctx, intr_ctx_num);
  908. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  909. if (tx_mask & (1 << j)) {
  910. irq_id_map[num_irq++] =
  911. (wbm2host_tx_completions_ring1 - j);
  912. }
  913. if (rx_mask & (1 << j)) {
  914. irq_id_map[num_irq++] =
  915. (reo2host_destination_ring1 - j);
  916. }
  917. if (rx_mon_mask & (1 << j)) {
  918. irq_id_map[num_irq++] =
  919. (ppdu_end_interrupts_mac1 - j);
  920. }
  921. if (rx_wbm_rel_ring_mask & (1 << j))
  922. irq_id_map[num_irq++] = wbm2host_rx_release;
  923. if (rx_err_ring_mask & (1 << j))
  924. irq_id_map[num_irq++] = reo2host_exception;
  925. if (reo_status_ring_mask & (1 << j))
  926. irq_id_map[num_irq++] = reo2host_status;
  927. }
  928. *num_irq_r = num_irq;
  929. }
  930. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  931. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  932. int msi_vector_count, int msi_vector_start)
  933. {
  934. int tx_mask = wlan_cfg_get_tx_ring_mask(
  935. soc->wlan_cfg_ctx, intr_ctx_num);
  936. int rx_mask = wlan_cfg_get_rx_ring_mask(
  937. soc->wlan_cfg_ctx, intr_ctx_num);
  938. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  939. soc->wlan_cfg_ctx, intr_ctx_num);
  940. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  941. soc->wlan_cfg_ctx, intr_ctx_num);
  942. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  943. soc->wlan_cfg_ctx, intr_ctx_num);
  944. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  945. soc->wlan_cfg_ctx, intr_ctx_num);
  946. unsigned int vector =
  947. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  948. int num_irq = 0;
  949. soc->intr_mode = DP_INTR_MSI;
  950. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  951. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  952. irq_id_map[num_irq++] =
  953. pld_get_msi_irq(soc->osdev->dev, vector);
  954. *num_irq_r = num_irq;
  955. }
  956. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  957. int *irq_id_map, int *num_irq)
  958. {
  959. int msi_vector_count, ret;
  960. uint32_t msi_base_data, msi_vector_start;
  961. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  962. &msi_vector_count,
  963. &msi_base_data,
  964. &msi_vector_start);
  965. if (ret)
  966. return dp_soc_interrupt_map_calculate_integrated(soc,
  967. intr_ctx_num, irq_id_map, num_irq);
  968. else
  969. dp_soc_interrupt_map_calculate_msi(soc,
  970. intr_ctx_num, irq_id_map, num_irq,
  971. msi_vector_count, msi_vector_start);
  972. }
  973. /*
  974. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  975. * @txrx_soc: DP SOC handle
  976. *
  977. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  978. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  979. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  980. *
  981. * Return: 0 for success. nonzero for failure.
  982. */
  983. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  984. {
  985. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  986. int i = 0;
  987. int num_irq = 0;
  988. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  989. int ret = 0;
  990. /* Map of IRQ ids registered with one interrupt context */
  991. int irq_id_map[HIF_MAX_GRP_IRQ];
  992. int tx_mask =
  993. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  994. int rx_mask =
  995. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  996. int rx_mon_mask =
  997. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  998. int rx_err_ring_mask =
  999. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1000. int rx_wbm_rel_ring_mask =
  1001. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1002. int reo_status_ring_mask =
  1003. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1004. int rxdma2host_ring_mask =
  1005. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1006. soc->intr_ctx[i].dp_intr_id = i;
  1007. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1008. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1009. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1010. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1011. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1012. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1013. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1014. soc->intr_ctx[i].soc = soc;
  1015. num_irq = 0;
  1016. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1017. &num_irq);
  1018. ret = hif_register_ext_group(soc->hif_handle,
  1019. num_irq, irq_id_map, dp_service_srngs,
  1020. &soc->intr_ctx[i], "dp_intr",
  1021. HIF_EXEC_NAPI_TYPE);
  1022. if (ret) {
  1023. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1024. FL("failed, ret = %d"), ret);
  1025. return QDF_STATUS_E_FAILURE;
  1026. }
  1027. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1028. }
  1029. hif_configure_ext_group_interrupts(soc->hif_handle);
  1030. return QDF_STATUS_SUCCESS;
  1031. }
  1032. /*
  1033. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1034. * @txrx_soc: DP SOC handle
  1035. *
  1036. * Return: void
  1037. */
  1038. static void dp_soc_interrupt_detach(void *txrx_soc)
  1039. {
  1040. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1041. int i;
  1042. if (soc->intr_mode == DP_INTR_POLL) {
  1043. qdf_timer_stop(&soc->int_timer);
  1044. qdf_timer_free(&soc->int_timer);
  1045. }
  1046. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1047. soc->intr_ctx[i].tx_ring_mask = 0;
  1048. soc->intr_ctx[i].rx_ring_mask = 0;
  1049. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1050. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1051. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1052. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1053. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1054. }
  1055. }
  1056. #define AVG_MAX_MPDUS_PER_TID 128
  1057. #define AVG_TIDS_PER_CLIENT 2
  1058. #define AVG_FLOWS_PER_TID 2
  1059. #define AVG_MSDUS_PER_FLOW 128
  1060. #define AVG_MSDUS_PER_MPDU 4
  1061. /*
  1062. * Allocate and setup link descriptor pool that will be used by HW for
  1063. * various link and queue descriptors and managed by WBM
  1064. */
  1065. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1066. {
  1067. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1068. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1069. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1070. uint32_t num_mpdus_per_link_desc =
  1071. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1072. uint32_t num_msdus_per_link_desc =
  1073. hal_num_msdus_per_link_desc(soc->hal_soc);
  1074. uint32_t num_mpdu_links_per_queue_desc =
  1075. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1076. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1077. uint32_t total_link_descs, total_mem_size;
  1078. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1079. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1080. uint32_t num_link_desc_banks;
  1081. uint32_t last_bank_size = 0;
  1082. uint32_t entry_size, num_entries;
  1083. int i;
  1084. uint32_t desc_id = 0;
  1085. /* Only Tx queue descriptors are allocated from common link descriptor
  1086. * pool Rx queue descriptors are not included in this because (REO queue
  1087. * extension descriptors) they are expected to be allocated contiguously
  1088. * with REO queue descriptors
  1089. */
  1090. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1091. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1092. num_mpdu_queue_descs = num_mpdu_link_descs /
  1093. num_mpdu_links_per_queue_desc;
  1094. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1095. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1096. num_msdus_per_link_desc;
  1097. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1098. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1099. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1100. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1101. /* Round up to power of 2 */
  1102. total_link_descs = 1;
  1103. while (total_link_descs < num_entries)
  1104. total_link_descs <<= 1;
  1105. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1106. FL("total_link_descs: %u, link_desc_size: %d"),
  1107. total_link_descs, link_desc_size);
  1108. total_mem_size = total_link_descs * link_desc_size;
  1109. total_mem_size += link_desc_align;
  1110. if (total_mem_size <= max_alloc_size) {
  1111. num_link_desc_banks = 0;
  1112. last_bank_size = total_mem_size;
  1113. } else {
  1114. num_link_desc_banks = (total_mem_size) /
  1115. (max_alloc_size - link_desc_align);
  1116. last_bank_size = total_mem_size %
  1117. (max_alloc_size - link_desc_align);
  1118. }
  1119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1120. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1121. total_mem_size, num_link_desc_banks);
  1122. for (i = 0; i < num_link_desc_banks; i++) {
  1123. soc->link_desc_banks[i].base_vaddr_unaligned =
  1124. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1125. max_alloc_size,
  1126. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1127. soc->link_desc_banks[i].size = max_alloc_size;
  1128. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1129. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1130. ((unsigned long)(
  1131. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1132. link_desc_align));
  1133. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1134. soc->link_desc_banks[i].base_paddr_unaligned) +
  1135. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1136. (unsigned long)(
  1137. soc->link_desc_banks[i].base_vaddr_unaligned));
  1138. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1140. FL("Link descriptor memory alloc failed"));
  1141. goto fail;
  1142. }
  1143. }
  1144. if (last_bank_size) {
  1145. /* Allocate last bank in case total memory required is not exact
  1146. * multiple of max_alloc_size
  1147. */
  1148. soc->link_desc_banks[i].base_vaddr_unaligned =
  1149. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1150. last_bank_size,
  1151. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1152. soc->link_desc_banks[i].size = last_bank_size;
  1153. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1154. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1155. ((unsigned long)(
  1156. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1157. link_desc_align));
  1158. soc->link_desc_banks[i].base_paddr =
  1159. (unsigned long)(
  1160. soc->link_desc_banks[i].base_paddr_unaligned) +
  1161. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1162. (unsigned long)(
  1163. soc->link_desc_banks[i].base_vaddr_unaligned));
  1164. }
  1165. /* Allocate and setup link descriptor idle list for HW internal use */
  1166. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1167. total_mem_size = entry_size * total_link_descs;
  1168. if (total_mem_size <= max_alloc_size) {
  1169. void *desc;
  1170. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1171. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1172. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1173. FL("Link desc idle ring setup failed"));
  1174. goto fail;
  1175. }
  1176. hal_srng_access_start_unlocked(soc->hal_soc,
  1177. soc->wbm_idle_link_ring.hal_srng);
  1178. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1179. soc->link_desc_banks[i].base_paddr; i++) {
  1180. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1181. ((unsigned long)(
  1182. soc->link_desc_banks[i].base_vaddr) -
  1183. (unsigned long)(
  1184. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1185. / link_desc_size;
  1186. unsigned long paddr = (unsigned long)(
  1187. soc->link_desc_banks[i].base_paddr);
  1188. while (num_entries && (desc = hal_srng_src_get_next(
  1189. soc->hal_soc,
  1190. soc->wbm_idle_link_ring.hal_srng))) {
  1191. hal_set_link_desc_addr(desc,
  1192. LINK_DESC_COOKIE(desc_id, i), paddr);
  1193. num_entries--;
  1194. desc_id++;
  1195. paddr += link_desc_size;
  1196. }
  1197. }
  1198. hal_srng_access_end_unlocked(soc->hal_soc,
  1199. soc->wbm_idle_link_ring.hal_srng);
  1200. } else {
  1201. uint32_t num_scatter_bufs;
  1202. uint32_t num_entries_per_buf;
  1203. uint32_t rem_entries;
  1204. uint8_t *scatter_buf_ptr;
  1205. uint16_t scatter_buf_num;
  1206. soc->wbm_idle_scatter_buf_size =
  1207. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1208. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1209. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1210. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1211. soc->hal_soc, total_mem_size,
  1212. soc->wbm_idle_scatter_buf_size);
  1213. for (i = 0; i < num_scatter_bufs; i++) {
  1214. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1215. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1216. soc->wbm_idle_scatter_buf_size,
  1217. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1218. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1219. QDF_TRACE(QDF_MODULE_ID_DP,
  1220. QDF_TRACE_LEVEL_ERROR,
  1221. FL("Scatter list memory alloc failed"));
  1222. goto fail;
  1223. }
  1224. }
  1225. /* Populate idle list scatter buffers with link descriptor
  1226. * pointers
  1227. */
  1228. scatter_buf_num = 0;
  1229. scatter_buf_ptr = (uint8_t *)(
  1230. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1231. rem_entries = num_entries_per_buf;
  1232. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1233. soc->link_desc_banks[i].base_paddr; i++) {
  1234. uint32_t num_link_descs =
  1235. (soc->link_desc_banks[i].size -
  1236. ((unsigned long)(
  1237. soc->link_desc_banks[i].base_vaddr) -
  1238. (unsigned long)(
  1239. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1240. / link_desc_size;
  1241. unsigned long paddr = (unsigned long)(
  1242. soc->link_desc_banks[i].base_paddr);
  1243. while (num_link_descs) {
  1244. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1245. LINK_DESC_COOKIE(desc_id, i), paddr);
  1246. num_link_descs--;
  1247. desc_id++;
  1248. paddr += link_desc_size;
  1249. rem_entries--;
  1250. if (rem_entries) {
  1251. scatter_buf_ptr += entry_size;
  1252. } else {
  1253. rem_entries = num_entries_per_buf;
  1254. scatter_buf_num++;
  1255. if (scatter_buf_num >= num_scatter_bufs)
  1256. break;
  1257. scatter_buf_ptr = (uint8_t *)(
  1258. soc->wbm_idle_scatter_buf_base_vaddr[
  1259. scatter_buf_num]);
  1260. }
  1261. }
  1262. }
  1263. /* Setup link descriptor idle list in HW */
  1264. hal_setup_link_idle_list(soc->hal_soc,
  1265. soc->wbm_idle_scatter_buf_base_paddr,
  1266. soc->wbm_idle_scatter_buf_base_vaddr,
  1267. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1268. (uint32_t)(scatter_buf_ptr -
  1269. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1270. scatter_buf_num-1])), total_link_descs);
  1271. }
  1272. return 0;
  1273. fail:
  1274. if (soc->wbm_idle_link_ring.hal_srng) {
  1275. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1276. WBM_IDLE_LINK, 0);
  1277. }
  1278. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1279. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1280. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1281. soc->wbm_idle_scatter_buf_size,
  1282. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1283. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1284. }
  1285. }
  1286. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1287. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1288. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1289. soc->link_desc_banks[i].size,
  1290. soc->link_desc_banks[i].base_vaddr_unaligned,
  1291. soc->link_desc_banks[i].base_paddr_unaligned,
  1292. 0);
  1293. }
  1294. }
  1295. return QDF_STATUS_E_FAILURE;
  1296. }
  1297. #ifdef notused
  1298. /*
  1299. * Free link descriptor pool that was setup HW
  1300. */
  1301. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1302. {
  1303. int i;
  1304. if (soc->wbm_idle_link_ring.hal_srng) {
  1305. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1306. WBM_IDLE_LINK, 0);
  1307. }
  1308. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1309. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1310. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1311. soc->wbm_idle_scatter_buf_size,
  1312. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1313. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1314. }
  1315. }
  1316. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1317. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1318. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1319. soc->link_desc_banks[i].size,
  1320. soc->link_desc_banks[i].base_vaddr_unaligned,
  1321. soc->link_desc_banks[i].base_paddr_unaligned,
  1322. 0);
  1323. }
  1324. }
  1325. }
  1326. #endif /* notused */
  1327. /* TODO: Following should be configurable */
  1328. #define WBM_RELEASE_RING_SIZE 64
  1329. #define TCL_CMD_RING_SIZE 32
  1330. #define TCL_STATUS_RING_SIZE 32
  1331. #if defined(QCA_WIFI_QCA6290)
  1332. #define REO_DST_RING_SIZE 1024
  1333. #else
  1334. #define REO_DST_RING_SIZE 2048
  1335. #endif
  1336. #define REO_REINJECT_RING_SIZE 32
  1337. #define RX_RELEASE_RING_SIZE 1024
  1338. #define REO_EXCEPTION_RING_SIZE 128
  1339. #define REO_CMD_RING_SIZE 32
  1340. #define REO_STATUS_RING_SIZE 32
  1341. #define RXDMA_BUF_RING_SIZE 1024
  1342. #define RXDMA_REFILL_RING_SIZE 2048
  1343. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  1344. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  1345. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1346. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  1347. #define RXDMA_ERR_DST_RING_SIZE 1024
  1348. /*
  1349. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1350. * @soc: Datapath SOC handle
  1351. *
  1352. * This is a timer function used to age out stale WDS nodes from
  1353. * AST table
  1354. */
  1355. #ifdef FEATURE_WDS
  1356. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1357. {
  1358. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1359. struct dp_pdev *pdev;
  1360. struct dp_vdev *vdev;
  1361. struct dp_peer *peer;
  1362. struct dp_ast_entry *ase, *temp_ase;
  1363. int i;
  1364. qdf_spin_lock_bh(&soc->ast_lock);
  1365. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1366. pdev = soc->pdev_list[i];
  1367. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1368. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1369. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1370. /*
  1371. * Do not expire static ast entries
  1372. */
  1373. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1374. continue;
  1375. if (ase->is_active) {
  1376. ase->is_active = FALSE;
  1377. continue;
  1378. }
  1379. DP_STATS_INC(soc, ast.aged_out, 1);
  1380. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1381. pdev->osif_pdev,
  1382. ase->mac_addr.raw);
  1383. dp_peer_del_ast(soc, ase);
  1384. }
  1385. }
  1386. }
  1387. }
  1388. qdf_spin_unlock_bh(&soc->ast_lock);
  1389. if (qdf_atomic_read(&soc->cmn_init_done))
  1390. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1391. }
  1392. /*
  1393. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1394. * @soc: Datapath SOC handle
  1395. *
  1396. * Return: None
  1397. */
  1398. static void dp_soc_wds_attach(struct dp_soc *soc)
  1399. {
  1400. qdf_spinlock_create(&soc->ast_lock);
  1401. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1402. dp_wds_aging_timer_fn, (void *)soc,
  1403. QDF_TIMER_TYPE_WAKE_APPS);
  1404. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1405. }
  1406. /*
  1407. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1408. * @txrx_soc: DP SOC handle
  1409. *
  1410. * Return: None
  1411. */
  1412. static void dp_soc_wds_detach(struct dp_soc *soc)
  1413. {
  1414. qdf_timer_stop(&soc->wds_aging_timer);
  1415. qdf_timer_free(&soc->wds_aging_timer);
  1416. qdf_spinlock_destroy(&soc->ast_lock);
  1417. }
  1418. #else
  1419. static void dp_soc_wds_attach(struct dp_soc *soc)
  1420. {
  1421. }
  1422. static void dp_soc_wds_detach(struct dp_soc *soc)
  1423. {
  1424. }
  1425. #endif
  1426. /*
  1427. * dp_soc_reset_ring_map() - Reset cpu ring map
  1428. * @soc: Datapath soc handler
  1429. *
  1430. * This api resets the default cpu ring map
  1431. */
  1432. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1433. {
  1434. uint8_t i;
  1435. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1436. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1437. if (nss_config == 1) {
  1438. /*
  1439. * Setting Tx ring map for one nss offloaded radio
  1440. */
  1441. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1442. } else if (nss_config == 2) {
  1443. /*
  1444. * Setting Tx ring for two nss offloaded radios
  1445. */
  1446. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1447. } else {
  1448. /*
  1449. * Setting Tx ring map for all nss offloaded radios
  1450. */
  1451. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1452. }
  1453. }
  1454. }
  1455. #ifdef IPA_OFFLOAD
  1456. /**
  1457. * dp_reo_remap_config() - configure reo remap register value based
  1458. * nss configuration.
  1459. * based on offload_radio value below remap configuration
  1460. * get applied.
  1461. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1462. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1463. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1464. * 3 - both Radios handled by NSS (remap not required)
  1465. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1466. *
  1467. * @remap1: output parameter indicates reo remap 1 register value
  1468. * @remap2: output parameter indicates reo remap 2 register value
  1469. * Return: bool type, true if remap is configured else false.
  1470. */
  1471. static bool dp_reo_remap_config(struct dp_soc *soc,
  1472. uint32_t *remap1,
  1473. uint32_t *remap2)
  1474. {
  1475. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1476. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1477. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1478. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1479. return true;
  1480. }
  1481. #else
  1482. static bool dp_reo_remap_config(struct dp_soc *soc,
  1483. uint32_t *remap1,
  1484. uint32_t *remap2)
  1485. {
  1486. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1487. switch (offload_radio) {
  1488. case 0:
  1489. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1490. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1491. (0x3 << 18) | (0x4 << 21)) << 8;
  1492. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1493. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1494. (0x3 << 18) | (0x4 << 21)) << 8;
  1495. break;
  1496. case 1:
  1497. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1498. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1499. (0x2 << 18) | (0x3 << 21)) << 8;
  1500. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1501. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1502. (0x4 << 18) | (0x2 << 21)) << 8;
  1503. break;
  1504. case 2:
  1505. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1506. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1507. (0x1 << 18) | (0x3 << 21)) << 8;
  1508. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1509. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1510. (0x4 << 18) | (0x1 << 21)) << 8;
  1511. break;
  1512. case 3:
  1513. /* return false if both radios are offloaded to NSS */
  1514. return false;
  1515. }
  1516. return true;
  1517. }
  1518. #endif
  1519. /*
  1520. * dp_soc_cmn_setup() - Common SoC level initializion
  1521. * @soc: Datapath SOC handle
  1522. *
  1523. * This is an internal function used to setup common SOC data structures,
  1524. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1525. */
  1526. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1527. {
  1528. int i;
  1529. struct hal_reo_params reo_params;
  1530. int tx_ring_size;
  1531. int tx_comp_ring_size;
  1532. if (qdf_atomic_read(&soc->cmn_init_done))
  1533. return 0;
  1534. if (dp_peer_find_attach(soc))
  1535. goto fail0;
  1536. if (dp_hw_link_desc_pool_setup(soc))
  1537. goto fail1;
  1538. /* Setup SRNG rings */
  1539. /* Common rings */
  1540. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1541. WBM_RELEASE_RING_SIZE)) {
  1542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1543. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1544. goto fail1;
  1545. }
  1546. soc->num_tcl_data_rings = 0;
  1547. /* Tx data rings */
  1548. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1549. soc->num_tcl_data_rings =
  1550. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1551. tx_comp_ring_size =
  1552. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1553. tx_ring_size =
  1554. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1555. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1556. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1557. TCL_DATA, i, 0, tx_ring_size)) {
  1558. QDF_TRACE(QDF_MODULE_ID_DP,
  1559. QDF_TRACE_LEVEL_ERROR,
  1560. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1561. goto fail1;
  1562. }
  1563. /*
  1564. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1565. * count
  1566. */
  1567. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1568. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1569. QDF_TRACE(QDF_MODULE_ID_DP,
  1570. QDF_TRACE_LEVEL_ERROR,
  1571. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1572. goto fail1;
  1573. }
  1574. }
  1575. } else {
  1576. /* This will be incremented during per pdev ring setup */
  1577. soc->num_tcl_data_rings = 0;
  1578. }
  1579. if (dp_tx_soc_attach(soc)) {
  1580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1581. FL("dp_tx_soc_attach failed"));
  1582. goto fail1;
  1583. }
  1584. /* TCL command and status rings */
  1585. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1586. TCL_CMD_RING_SIZE)) {
  1587. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1588. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1589. goto fail1;
  1590. }
  1591. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1592. TCL_STATUS_RING_SIZE)) {
  1593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1594. FL("dp_srng_setup failed for tcl_status_ring"));
  1595. goto fail1;
  1596. }
  1597. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1598. * descriptors
  1599. */
  1600. /* Rx data rings */
  1601. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1602. soc->num_reo_dest_rings =
  1603. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1604. QDF_TRACE(QDF_MODULE_ID_DP,
  1605. QDF_TRACE_LEVEL_ERROR,
  1606. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1607. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1608. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1609. i, 0, REO_DST_RING_SIZE)) {
  1610. QDF_TRACE(QDF_MODULE_ID_DP,
  1611. QDF_TRACE_LEVEL_ERROR,
  1612. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1613. goto fail1;
  1614. }
  1615. }
  1616. } else {
  1617. /* This will be incremented during per pdev ring setup */
  1618. soc->num_reo_dest_rings = 0;
  1619. }
  1620. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1621. /* REO reinjection ring */
  1622. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1623. REO_REINJECT_RING_SIZE)) {
  1624. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1625. FL("dp_srng_setup failed for reo_reinject_ring"));
  1626. goto fail1;
  1627. }
  1628. /* Rx release ring */
  1629. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1630. RX_RELEASE_RING_SIZE)) {
  1631. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1632. FL("dp_srng_setup failed for rx_rel_ring"));
  1633. goto fail1;
  1634. }
  1635. /* Rx exception ring */
  1636. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1637. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1638. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1639. FL("dp_srng_setup failed for reo_exception_ring"));
  1640. goto fail1;
  1641. }
  1642. /* REO command and status rings */
  1643. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1644. REO_CMD_RING_SIZE)) {
  1645. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1646. FL("dp_srng_setup failed for reo_cmd_ring"));
  1647. goto fail1;
  1648. }
  1649. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1650. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1651. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1652. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1653. REO_STATUS_RING_SIZE)) {
  1654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1655. FL("dp_srng_setup failed for reo_status_ring"));
  1656. goto fail1;
  1657. }
  1658. dp_soc_wds_attach(soc);
  1659. /* Reset the cpu ring map if radio is NSS offloaded */
  1660. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1661. dp_soc_reset_cpu_ring_map(soc);
  1662. }
  1663. /* Setup HW REO */
  1664. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1665. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1666. /*
  1667. * Reo ring remap is not required if both radios
  1668. * are offloaded to NSS
  1669. */
  1670. if (!dp_reo_remap_config(soc,
  1671. &reo_params.remap1,
  1672. &reo_params.remap2))
  1673. goto out;
  1674. reo_params.rx_hash_enabled = true;
  1675. }
  1676. out:
  1677. hal_reo_setup(soc->hal_soc, &reo_params);
  1678. qdf_atomic_set(&soc->cmn_init_done, 1);
  1679. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1680. return 0;
  1681. fail1:
  1682. /*
  1683. * Cleanup will be done as part of soc_detach, which will
  1684. * be called on pdev attach failure
  1685. */
  1686. fail0:
  1687. return QDF_STATUS_E_FAILURE;
  1688. }
  1689. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1690. static void dp_lro_hash_setup(struct dp_soc *soc)
  1691. {
  1692. struct cdp_lro_hash_config lro_hash;
  1693. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1694. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1695. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1696. FL("LRO disabled RX hash disabled"));
  1697. return;
  1698. }
  1699. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1700. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1701. lro_hash.lro_enable = 1;
  1702. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1703. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1704. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1705. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1706. }
  1707. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1708. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1709. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1710. LRO_IPV4_SEED_ARR_SZ));
  1711. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1712. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1713. LRO_IPV6_SEED_ARR_SZ));
  1714. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1715. "lro_hash: lro_enable: 0x%x"
  1716. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1717. lro_hash.lro_enable, lro_hash.tcp_flag,
  1718. lro_hash.tcp_flag_mask);
  1719. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1720. FL("lro_hash: toeplitz_hash_ipv4:"));
  1721. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1722. QDF_TRACE_LEVEL_ERROR,
  1723. (void *)lro_hash.toeplitz_hash_ipv4,
  1724. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1725. LRO_IPV4_SEED_ARR_SZ));
  1726. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1727. FL("lro_hash: toeplitz_hash_ipv6:"));
  1728. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1729. QDF_TRACE_LEVEL_ERROR,
  1730. (void *)lro_hash.toeplitz_hash_ipv6,
  1731. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1732. LRO_IPV6_SEED_ARR_SZ));
  1733. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1734. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1735. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1736. (soc->osif_soc, &lro_hash);
  1737. }
  1738. /*
  1739. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1740. * @soc: data path SoC handle
  1741. * @pdev: Physical device handle
  1742. *
  1743. * Return: 0 - success, > 0 - failure
  1744. */
  1745. #ifdef QCA_HOST2FW_RXBUF_RING
  1746. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1747. struct dp_pdev *pdev)
  1748. {
  1749. int max_mac_rings =
  1750. wlan_cfg_get_num_mac_rings
  1751. (pdev->wlan_cfg_ctx);
  1752. int i;
  1753. for (i = 0; i < max_mac_rings; i++) {
  1754. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1755. "%s: pdev_id %d mac_id %d\n",
  1756. __func__, pdev->pdev_id, i);
  1757. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1758. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1759. QDF_TRACE(QDF_MODULE_ID_DP,
  1760. QDF_TRACE_LEVEL_ERROR,
  1761. FL("failed rx mac ring setup"));
  1762. return QDF_STATUS_E_FAILURE;
  1763. }
  1764. }
  1765. return QDF_STATUS_SUCCESS;
  1766. }
  1767. #else
  1768. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1769. struct dp_pdev *pdev)
  1770. {
  1771. return QDF_STATUS_SUCCESS;
  1772. }
  1773. #endif
  1774. /**
  1775. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1776. * @pdev - DP_PDEV handle
  1777. *
  1778. * Return: void
  1779. */
  1780. static inline void
  1781. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1782. {
  1783. uint8_t map_id;
  1784. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1785. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1786. sizeof(default_dscp_tid_map));
  1787. }
  1788. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1789. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1790. pdev->dscp_tid_map[map_id],
  1791. map_id);
  1792. }
  1793. }
  1794. /*
  1795. * dp_reset_intr_mask() - reset interrupt mask
  1796. * @dp_soc - DP Soc handle
  1797. * @dp_pdev - DP pdev handle
  1798. *
  1799. * Return: Return void
  1800. */
  1801. static inline
  1802. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1803. {
  1804. /*
  1805. * We will set the interrupt mask to zero for NSS offloaded radio
  1806. */
  1807. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1808. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1809. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1810. }
  1811. /*
  1812. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1813. * @soc: data path SoC handle
  1814. *
  1815. * Return: none
  1816. */
  1817. #ifdef IPA_OFFLOAD
  1818. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1819. struct dp_pdev *pdev)
  1820. {
  1821. void *hal_srng;
  1822. struct hal_srng_params srng_params;
  1823. qdf_dma_addr_t hp_addr, tp_addr;
  1824. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1825. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1826. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1827. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1828. srng_params.ring_base_paddr;
  1829. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1830. srng_params.ring_base_vaddr;
  1831. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1832. srng_params.num_entries * srng_params.entry_size;
  1833. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1834. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1835. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1836. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1837. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1838. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1839. srng_params.ring_base_paddr;
  1840. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1841. srng_params.ring_base_vaddr;
  1842. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1843. srng_params.num_entries * srng_params.entry_size;
  1844. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1845. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1846. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1847. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1848. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1849. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1850. srng_params.ring_base_paddr;
  1851. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1852. srng_params.ring_base_vaddr;
  1853. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1854. srng_params.num_entries * srng_params.entry_size;
  1855. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1856. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1857. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1858. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1859. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1860. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1861. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1862. __func__);
  1863. return -EFAULT;
  1864. }
  1865. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1866. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1867. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1868. srng_params.ring_base_paddr;
  1869. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1870. srng_params.ring_base_vaddr;
  1871. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1872. srng_params.num_entries * srng_params.entry_size;
  1873. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1874. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1875. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1876. "%s: ring_base_paddr:%p, ring_base_vaddr:%p"
  1877. "_entries:%d, hp_addr:%p\n",
  1878. __func__,
  1879. (void *)srng_params.ring_base_paddr,
  1880. (void *)srng_params.ring_base_vaddr,
  1881. srng_params.num_entries,
  1882. (void *)hp_addr);
  1883. return 0;
  1884. }
  1885. #else
  1886. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1887. struct dp_pdev *pdev)
  1888. {
  1889. return 0;
  1890. }
  1891. #endif
  1892. /*
  1893. * dp_pdev_attach_wifi3() - attach txrx pdev
  1894. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1895. * @txrx_soc: Datapath SOC handle
  1896. * @htc_handle: HTC handle for host-target interface
  1897. * @qdf_osdev: QDF OS device
  1898. * @pdev_id: PDEV ID
  1899. *
  1900. * Return: DP PDEV handle on success, NULL on failure
  1901. */
  1902. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1903. struct cdp_cfg *ctrl_pdev,
  1904. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1905. {
  1906. int tx_ring_size;
  1907. int tx_comp_ring_size;
  1908. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1909. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1910. if (!pdev) {
  1911. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1912. FL("DP PDEV memory allocation failed"));
  1913. goto fail0;
  1914. }
  1915. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1916. if (!pdev->wlan_cfg_ctx) {
  1917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1918. FL("pdev cfg_attach failed"));
  1919. qdf_mem_free(pdev);
  1920. goto fail0;
  1921. }
  1922. /*
  1923. * set nss pdev config based on soc config
  1924. */
  1925. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1926. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1927. pdev->soc = soc;
  1928. pdev->osif_pdev = ctrl_pdev;
  1929. pdev->pdev_id = pdev_id;
  1930. soc->pdev_list[pdev_id] = pdev;
  1931. soc->pdev_count++;
  1932. TAILQ_INIT(&pdev->vdev_list);
  1933. pdev->vdev_count = 0;
  1934. qdf_spinlock_create(&pdev->tx_mutex);
  1935. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1936. TAILQ_INIT(&pdev->neighbour_peers_list);
  1937. if (dp_soc_cmn_setup(soc)) {
  1938. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1939. FL("dp_soc_cmn_setup failed"));
  1940. goto fail1;
  1941. }
  1942. /* Setup per PDEV TCL rings if configured */
  1943. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1944. tx_ring_size =
  1945. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1946. tx_comp_ring_size =
  1947. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1948. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1949. pdev_id, pdev_id, tx_ring_size)) {
  1950. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1951. FL("dp_srng_setup failed for tcl_data_ring"));
  1952. goto fail1;
  1953. }
  1954. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1955. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1956. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1957. FL("dp_srng_setup failed for tx_comp_ring"));
  1958. goto fail1;
  1959. }
  1960. soc->num_tcl_data_rings++;
  1961. }
  1962. /* Tx specific init */
  1963. if (dp_tx_pdev_attach(pdev)) {
  1964. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1965. FL("dp_tx_pdev_attach failed"));
  1966. goto fail1;
  1967. }
  1968. /* Setup per PDEV REO rings if configured */
  1969. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1970. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1971. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1972. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1973. FL("dp_srng_setup failed for reo_dest_ringn"));
  1974. goto fail1;
  1975. }
  1976. soc->num_reo_dest_rings++;
  1977. }
  1978. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1979. RXDMA_REFILL_RING_SIZE)) {
  1980. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1981. FL("dp_srng_setup failed rx refill ring"));
  1982. goto fail1;
  1983. }
  1984. if (dp_rxdma_ring_setup(soc, pdev)) {
  1985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1986. FL("RXDMA ring config failed"));
  1987. goto fail1;
  1988. }
  1989. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1990. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1992. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1993. goto fail1;
  1994. }
  1995. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1996. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1998. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1999. goto fail1;
  2000. }
  2001. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2002. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2003. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2004. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2005. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2006. goto fail1;
  2007. }
  2008. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2009. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2010. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2011. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2012. goto fail1;
  2013. }
  2014. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2015. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2016. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2017. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2018. goto fail1;
  2019. }
  2020. if (dp_ipa_ring_resource_setup(soc, pdev))
  2021. goto fail1;
  2022. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2023. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2024. "%s: dp_ipa_uc_attach failed\n", __func__);
  2025. goto fail1;
  2026. }
  2027. /* Rx specific init */
  2028. if (dp_rx_pdev_attach(pdev)) {
  2029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2030. FL("dp_rx_pdev_attach failed "));
  2031. goto fail0;
  2032. }
  2033. DP_STATS_INIT(pdev);
  2034. #ifndef CONFIG_WIN
  2035. /* MCL */
  2036. dp_local_peer_id_pool_init(pdev);
  2037. #endif
  2038. dp_dscp_tid_map_setup(pdev);
  2039. /* Rx monitor mode specific init */
  2040. if (dp_rx_pdev_mon_attach(pdev)) {
  2041. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2042. "dp_rx_pdev_attach failed\n");
  2043. goto fail1;
  2044. }
  2045. if (dp_wdi_event_attach(pdev)) {
  2046. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2047. "dp_wdi_evet_attach failed\n");
  2048. goto fail1;
  2049. }
  2050. /* set the reo destination during initialization */
  2051. pdev->reo_dest = pdev->pdev_id + 1;
  2052. /*
  2053. * reset the interrupt mask for offloaded radio
  2054. */
  2055. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2056. dp_soc_reset_intr_mask(soc, pdev);
  2057. }
  2058. return (struct cdp_pdev *)pdev;
  2059. fail1:
  2060. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2061. fail0:
  2062. return NULL;
  2063. }
  2064. /*
  2065. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2066. * @soc: data path SoC handle
  2067. * @pdev: Physical device handle
  2068. *
  2069. * Return: void
  2070. */
  2071. #ifdef QCA_HOST2FW_RXBUF_RING
  2072. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2073. struct dp_pdev *pdev)
  2074. {
  2075. int max_mac_rings =
  2076. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2077. int i;
  2078. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2079. max_mac_rings : MAX_RX_MAC_RINGS;
  2080. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2081. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2082. RXDMA_BUF, 1);
  2083. }
  2084. #else
  2085. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2086. struct dp_pdev *pdev)
  2087. {
  2088. }
  2089. #endif
  2090. /*
  2091. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2092. * @pdev: device object
  2093. *
  2094. * Return: void
  2095. */
  2096. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2097. {
  2098. struct dp_neighbour_peer *peer = NULL;
  2099. struct dp_neighbour_peer *temp_peer = NULL;
  2100. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2101. neighbour_peer_list_elem, temp_peer) {
  2102. /* delete this peer from the list */
  2103. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2104. peer, neighbour_peer_list_elem);
  2105. qdf_mem_free(peer);
  2106. }
  2107. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2108. }
  2109. /*
  2110. * dp_pdev_detach_wifi3() - detach txrx pdev
  2111. * @txrx_pdev: Datapath PDEV handle
  2112. * @force: Force detach
  2113. *
  2114. */
  2115. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2116. {
  2117. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2118. struct dp_soc *soc = pdev->soc;
  2119. dp_wdi_event_detach(pdev);
  2120. dp_tx_pdev_detach(pdev);
  2121. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2122. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2123. TCL_DATA, pdev->pdev_id);
  2124. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2125. WBM2SW_RELEASE, pdev->pdev_id);
  2126. }
  2127. dp_rx_pdev_detach(pdev);
  2128. dp_rx_pdev_mon_detach(pdev);
  2129. dp_neighbour_peers_detach(pdev);
  2130. qdf_spinlock_destroy(&pdev->tx_mutex);
  2131. dp_ipa_uc_detach(soc, pdev);
  2132. /* Cleanup per PDEV REO rings if configured */
  2133. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2134. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2135. REO_DST, pdev->pdev_id);
  2136. }
  2137. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2138. dp_rxdma_ring_cleanup(soc, pdev);
  2139. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2140. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2141. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2142. RXDMA_MONITOR_STATUS, 0);
  2143. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2144. RXDMA_MONITOR_DESC, 0);
  2145. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2146. soc->pdev_list[pdev->pdev_id] = NULL;
  2147. soc->pdev_count--;
  2148. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2149. qdf_mem_free(pdev);
  2150. }
  2151. /*
  2152. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2153. * @soc: DP SOC handle
  2154. */
  2155. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2156. {
  2157. struct reo_desc_list_node *desc;
  2158. struct dp_rx_tid *rx_tid;
  2159. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2160. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2161. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2162. rx_tid = &desc->rx_tid;
  2163. qdf_mem_unmap_nbytes_single(soc->osdev,
  2164. rx_tid->hw_qdesc_paddr,
  2165. QDF_DMA_BIDIRECTIONAL,
  2166. rx_tid->hw_qdesc_alloc_size);
  2167. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2168. qdf_mem_free(desc);
  2169. }
  2170. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2171. qdf_list_destroy(&soc->reo_desc_freelist);
  2172. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2173. }
  2174. /*
  2175. * dp_soc_detach_wifi3() - Detach txrx SOC
  2176. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2177. */
  2178. static void dp_soc_detach_wifi3(void *txrx_soc)
  2179. {
  2180. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2181. int i;
  2182. qdf_atomic_set(&soc->cmn_init_done, 0);
  2183. qdf_flush_work(0, &soc->htt_stats.work);
  2184. qdf_disable_work(0, &soc->htt_stats.work);
  2185. /* Free pending htt stats messages */
  2186. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2187. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2188. if (soc->pdev_list[i])
  2189. dp_pdev_detach_wifi3(
  2190. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2191. }
  2192. dp_peer_find_detach(soc);
  2193. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2194. * SW descriptors
  2195. */
  2196. /* Free the ring memories */
  2197. /* Common rings */
  2198. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2199. dp_tx_soc_detach(soc);
  2200. /* Tx data rings */
  2201. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2202. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2203. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2204. TCL_DATA, i);
  2205. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2206. WBM2SW_RELEASE, i);
  2207. }
  2208. }
  2209. /* TCL command and status rings */
  2210. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2211. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2212. /* Rx data rings */
  2213. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2214. soc->num_reo_dest_rings =
  2215. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2216. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2217. /* TODO: Get number of rings and ring sizes
  2218. * from wlan_cfg
  2219. */
  2220. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2221. REO_DST, i);
  2222. }
  2223. }
  2224. /* REO reinjection ring */
  2225. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2226. /* Rx release ring */
  2227. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2228. /* Rx exception ring */
  2229. /* TODO: Better to store ring_type and ring_num in
  2230. * dp_srng during setup
  2231. */
  2232. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2233. /* REO command and status rings */
  2234. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2235. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2236. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2237. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2238. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2239. htt_soc_detach(soc->htt_handle);
  2240. dp_reo_cmdlist_destroy(soc);
  2241. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2242. dp_reo_desc_freelist_destroy(soc);
  2243. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2244. dp_soc_wds_detach(soc);
  2245. qdf_mem_free(soc);
  2246. }
  2247. /*
  2248. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2249. * @soc: data path SoC handle
  2250. * @pdev: physical device handle
  2251. *
  2252. * Return: void
  2253. */
  2254. #ifdef IPA_OFFLOAD
  2255. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2256. struct dp_pdev *pdev)
  2257. {
  2258. htt_srng_setup(soc->htt_handle, 0,
  2259. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2260. }
  2261. #else
  2262. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2263. struct dp_pdev *pdev)
  2264. {
  2265. }
  2266. #endif
  2267. /*
  2268. * dp_rxdma_ring_config() - configure the RX DMA rings
  2269. *
  2270. * This function is used to configure the MAC rings.
  2271. * On MCL host provides buffers in Host2FW ring
  2272. * FW refills (copies) buffers to the ring and updates
  2273. * ring_idx in register
  2274. *
  2275. * @soc: data path SoC handle
  2276. *
  2277. * Return: void
  2278. */
  2279. #ifdef QCA_HOST2FW_RXBUF_RING
  2280. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2281. {
  2282. int i;
  2283. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2284. struct dp_pdev *pdev = soc->pdev_list[i];
  2285. if (pdev) {
  2286. int mac_id = 0;
  2287. int j;
  2288. bool dbs_enable = 0;
  2289. int max_mac_rings =
  2290. wlan_cfg_get_num_mac_rings
  2291. (pdev->wlan_cfg_ctx);
  2292. htt_srng_setup(soc->htt_handle, 0,
  2293. pdev->rx_refill_buf_ring.hal_srng,
  2294. RXDMA_BUF);
  2295. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2296. if (soc->cdp_soc.ol_ops->
  2297. is_hw_dbs_2x2_capable) {
  2298. dbs_enable = soc->cdp_soc.ol_ops->
  2299. is_hw_dbs_2x2_capable(soc->psoc);
  2300. }
  2301. if (dbs_enable) {
  2302. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2303. QDF_TRACE_LEVEL_ERROR,
  2304. FL("DBS enabled max_mac_rings %d\n"),
  2305. max_mac_rings);
  2306. } else {
  2307. max_mac_rings = 1;
  2308. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2309. QDF_TRACE_LEVEL_ERROR,
  2310. FL("DBS disabled, max_mac_rings %d\n"),
  2311. max_mac_rings);
  2312. }
  2313. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2314. FL("pdev_id %d max_mac_rings %d\n"),
  2315. pdev->pdev_id, max_mac_rings);
  2316. for (j = 0; j < max_mac_rings; j++) {
  2317. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2318. QDF_TRACE_LEVEL_ERROR,
  2319. FL("mac_id %d\n"), mac_id);
  2320. htt_srng_setup(soc->htt_handle, mac_id,
  2321. pdev->rx_mac_buf_ring[j]
  2322. .hal_srng,
  2323. RXDMA_BUF);
  2324. mac_id++;
  2325. }
  2326. /* Configure monitor mode rings */
  2327. htt_srng_setup(soc->htt_handle, i,
  2328. pdev->rxdma_mon_buf_ring.hal_srng,
  2329. RXDMA_MONITOR_BUF);
  2330. htt_srng_setup(soc->htt_handle, i,
  2331. pdev->rxdma_mon_dst_ring.hal_srng,
  2332. RXDMA_MONITOR_DST);
  2333. htt_srng_setup(soc->htt_handle, i,
  2334. pdev->rxdma_mon_status_ring.hal_srng,
  2335. RXDMA_MONITOR_STATUS);
  2336. htt_srng_setup(soc->htt_handle, i,
  2337. pdev->rxdma_mon_desc_ring.hal_srng,
  2338. RXDMA_MONITOR_DESC);
  2339. htt_srng_setup(soc->htt_handle, i,
  2340. pdev->rxdma_err_dst_ring.hal_srng,
  2341. RXDMA_DST);
  2342. }
  2343. }
  2344. }
  2345. #else
  2346. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2347. {
  2348. int i;
  2349. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2350. struct dp_pdev *pdev = soc->pdev_list[i];
  2351. if (pdev) {
  2352. htt_srng_setup(soc->htt_handle, i,
  2353. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2354. htt_srng_setup(soc->htt_handle, i,
  2355. pdev->rxdma_mon_buf_ring.hal_srng,
  2356. RXDMA_MONITOR_BUF);
  2357. htt_srng_setup(soc->htt_handle, i,
  2358. pdev->rxdma_mon_dst_ring.hal_srng,
  2359. RXDMA_MONITOR_DST);
  2360. htt_srng_setup(soc->htt_handle, i,
  2361. pdev->rxdma_mon_status_ring.hal_srng,
  2362. RXDMA_MONITOR_STATUS);
  2363. htt_srng_setup(soc->htt_handle, i,
  2364. pdev->rxdma_mon_desc_ring.hal_srng,
  2365. RXDMA_MONITOR_DESC);
  2366. htt_srng_setup(soc->htt_handle, i,
  2367. pdev->rxdma_err_dst_ring.hal_srng,
  2368. RXDMA_DST);
  2369. }
  2370. }
  2371. }
  2372. #endif
  2373. /*
  2374. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2375. * @txrx_soc: Datapath SOC handle
  2376. */
  2377. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2378. {
  2379. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2380. htt_soc_attach_target(soc->htt_handle);
  2381. dp_rxdma_ring_config(soc);
  2382. DP_STATS_INIT(soc);
  2383. /* initialize work queue for stats processing */
  2384. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2385. return 0;
  2386. }
  2387. /*
  2388. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2389. * @txrx_soc: Datapath SOC handle
  2390. */
  2391. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2392. {
  2393. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2394. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2395. }
  2396. /*
  2397. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2398. * @txrx_soc: Datapath SOC handle
  2399. * @nss_cfg: nss config
  2400. */
  2401. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2402. {
  2403. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2404. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2406. FL("nss-wifi<0> nss config is enabled"));
  2407. }
  2408. /*
  2409. * dp_vdev_attach_wifi3() - attach txrx vdev
  2410. * @txrx_pdev: Datapath PDEV handle
  2411. * @vdev_mac_addr: MAC address of the virtual interface
  2412. * @vdev_id: VDEV Id
  2413. * @wlan_op_mode: VDEV operating mode
  2414. *
  2415. * Return: DP VDEV handle on success, NULL on failure
  2416. */
  2417. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2418. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2419. {
  2420. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2421. struct dp_soc *soc = pdev->soc;
  2422. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2423. int tx_ring_size;
  2424. if (!vdev) {
  2425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2426. FL("DP VDEV memory allocation failed"));
  2427. goto fail0;
  2428. }
  2429. vdev->pdev = pdev;
  2430. vdev->vdev_id = vdev_id;
  2431. vdev->opmode = op_mode;
  2432. vdev->osdev = soc->osdev;
  2433. vdev->osif_rx = NULL;
  2434. vdev->osif_rsim_rx_decap = NULL;
  2435. vdev->osif_get_key = NULL;
  2436. vdev->osif_rx_mon = NULL;
  2437. vdev->osif_tx_free_ext = NULL;
  2438. vdev->osif_vdev = NULL;
  2439. vdev->delete.pending = 0;
  2440. vdev->safemode = 0;
  2441. vdev->drop_unenc = 1;
  2442. #ifdef notyet
  2443. vdev->filters_num = 0;
  2444. #endif
  2445. qdf_mem_copy(
  2446. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2447. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2448. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2449. vdev->dscp_tid_map_id = 0;
  2450. vdev->mcast_enhancement_en = 0;
  2451. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2452. /* TODO: Initialize default HTT meta data that will be used in
  2453. * TCL descriptors for packets transmitted from this VDEV
  2454. */
  2455. TAILQ_INIT(&vdev->peer_list);
  2456. /* add this vdev into the pdev's list */
  2457. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2458. pdev->vdev_count++;
  2459. dp_tx_vdev_attach(vdev);
  2460. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2461. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2462. goto fail1;
  2463. if ((soc->intr_mode == DP_INTR_POLL) &&
  2464. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2465. if (pdev->vdev_count == 1)
  2466. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2467. }
  2468. dp_lro_hash_setup(soc);
  2469. /* LRO */
  2470. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2471. wlan_op_mode_sta == vdev->opmode)
  2472. vdev->lro_enable = true;
  2473. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2474. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2476. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  2477. DP_STATS_INIT(vdev);
  2478. return (struct cdp_vdev *)vdev;
  2479. fail1:
  2480. dp_tx_vdev_detach(vdev);
  2481. qdf_mem_free(vdev);
  2482. fail0:
  2483. return NULL;
  2484. }
  2485. /**
  2486. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2487. * @vdev: Datapath VDEV handle
  2488. * @osif_vdev: OSIF vdev handle
  2489. * @txrx_ops: Tx and Rx operations
  2490. *
  2491. * Return: DP VDEV handle on success, NULL on failure
  2492. */
  2493. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2494. void *osif_vdev,
  2495. struct ol_txrx_ops *txrx_ops)
  2496. {
  2497. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2498. vdev->osif_vdev = osif_vdev;
  2499. vdev->osif_rx = txrx_ops->rx.rx;
  2500. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2501. vdev->osif_get_key = txrx_ops->get_key;
  2502. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2503. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2504. #ifdef notyet
  2505. #if ATH_SUPPORT_WAPI
  2506. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2507. #endif
  2508. #endif
  2509. #ifdef UMAC_SUPPORT_PROXY_ARP
  2510. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2511. #endif
  2512. vdev->me_convert = txrx_ops->me_convert;
  2513. /* TODO: Enable the following once Tx code is integrated */
  2514. txrx_ops->tx.tx = dp_tx_send;
  2515. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2516. "DP Vdev Register success");
  2517. }
  2518. /*
  2519. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2520. * @txrx_vdev: Datapath VDEV handle
  2521. * @callback: Callback OL_IF on completion of detach
  2522. * @cb_context: Callback context
  2523. *
  2524. */
  2525. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2526. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2527. {
  2528. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2529. struct dp_pdev *pdev = vdev->pdev;
  2530. struct dp_soc *soc = pdev->soc;
  2531. /* preconditions */
  2532. qdf_assert(vdev);
  2533. /* remove the vdev from its parent pdev's list */
  2534. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2535. /*
  2536. * Use peer_ref_mutex while accessing peer_list, in case
  2537. * a peer is in the process of being removed from the list.
  2538. */
  2539. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2540. /* check that the vdev has no peers allocated */
  2541. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2542. /* debug print - will be removed later */
  2543. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2544. FL("not deleting vdev object %p (%pM)"
  2545. "until deletion finishes for all its peers"),
  2546. vdev, vdev->mac_addr.raw);
  2547. /* indicate that the vdev needs to be deleted */
  2548. vdev->delete.pending = 1;
  2549. vdev->delete.callback = callback;
  2550. vdev->delete.context = cb_context;
  2551. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2552. return;
  2553. }
  2554. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2555. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2556. vdev->vdev_id);
  2557. dp_tx_vdev_detach(vdev);
  2558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2559. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  2560. qdf_mem_free(vdev);
  2561. if (callback)
  2562. callback(cb_context);
  2563. }
  2564. /*
  2565. * dp_peer_create_wifi3() - attach txrx peer
  2566. * @txrx_vdev: Datapath VDEV handle
  2567. * @peer_mac_addr: Peer MAC address
  2568. *
  2569. * Return: DP peeer handle on success, NULL on failure
  2570. */
  2571. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2572. uint8_t *peer_mac_addr)
  2573. {
  2574. struct dp_peer *peer;
  2575. int i;
  2576. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2577. struct dp_pdev *pdev;
  2578. struct dp_soc *soc;
  2579. /* preconditions */
  2580. qdf_assert(vdev);
  2581. qdf_assert(peer_mac_addr);
  2582. pdev = vdev->pdev;
  2583. soc = pdev->soc;
  2584. #ifdef notyet
  2585. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2586. soc->mempool_ol_ath_peer);
  2587. #else
  2588. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2589. #endif
  2590. if (!peer)
  2591. return NULL; /* failure */
  2592. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2593. TAILQ_INIT(&peer->ast_entry_list);
  2594. /* store provided params */
  2595. peer->vdev = vdev;
  2596. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2597. qdf_spinlock_create(&peer->peer_info_lock);
  2598. qdf_mem_copy(
  2599. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2600. /* TODO: See of rx_opt_proc is really required */
  2601. peer->rx_opt_proc = soc->rx_opt_proc;
  2602. /* initialize the peer_id */
  2603. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2604. peer->peer_ids[i] = HTT_INVALID_PEER;
  2605. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2606. qdf_atomic_init(&peer->ref_cnt);
  2607. /* keep one reference for attach */
  2608. qdf_atomic_inc(&peer->ref_cnt);
  2609. /* add this peer into the vdev's list */
  2610. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2611. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2612. /* TODO: See if hash based search is required */
  2613. dp_peer_find_hash_add(soc, peer);
  2614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2615. "vdev %p created peer %p (%pM) ref_cnt: %d",
  2616. vdev, peer, peer->mac_addr.raw,
  2617. qdf_atomic_read(&peer->ref_cnt));
  2618. /*
  2619. * For every peer MAp message search and set if bss_peer
  2620. */
  2621. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2622. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2623. "vdev bss_peer!!!!");
  2624. peer->bss_peer = 1;
  2625. vdev->vap_bss_peer = peer;
  2626. }
  2627. #ifndef CONFIG_WIN
  2628. dp_local_peer_id_alloc(pdev, peer);
  2629. #endif
  2630. DP_STATS_INIT(peer);
  2631. return (void *)peer;
  2632. }
  2633. /*
  2634. * dp_peer_setup_wifi3() - initialize the peer
  2635. * @vdev_hdl: virtual device object
  2636. * @peer: Peer object
  2637. *
  2638. * Return: void
  2639. */
  2640. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2641. {
  2642. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2643. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2644. struct dp_pdev *pdev;
  2645. struct dp_soc *soc;
  2646. bool hash_based = 0;
  2647. enum cdp_host_reo_dest_ring reo_dest;
  2648. /* preconditions */
  2649. qdf_assert(vdev);
  2650. qdf_assert(peer);
  2651. pdev = vdev->pdev;
  2652. soc = pdev->soc;
  2653. dp_peer_rx_init(pdev, peer);
  2654. peer->last_assoc_rcvd = 0;
  2655. peer->last_disassoc_rcvd = 0;
  2656. peer->last_deauth_rcvd = 0;
  2657. /*
  2658. * hash based steering is disabled for Radios which are offloaded
  2659. * to NSS
  2660. */
  2661. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2662. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2664. FL("hash based steering for pdev: %d is %d\n"),
  2665. pdev->pdev_id, hash_based);
  2666. if (!hash_based)
  2667. reo_dest = pdev->reo_dest;
  2668. else
  2669. reo_dest = 1;
  2670. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2671. /* TODO: Check the destination ring number to be passed to FW */
  2672. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2673. pdev->osif_pdev, peer->mac_addr.raw,
  2674. peer->vdev->vdev_id, hash_based, reo_dest);
  2675. }
  2676. return;
  2677. }
  2678. /*
  2679. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2680. * @vdev_handle: virtual device object
  2681. * @htt_pkt_type: type of pkt
  2682. *
  2683. * Return: void
  2684. */
  2685. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2686. enum htt_cmn_pkt_type val)
  2687. {
  2688. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2689. vdev->tx_encap_type = val;
  2690. }
  2691. /*
  2692. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2693. * @vdev_handle: virtual device object
  2694. * @htt_pkt_type: type of pkt
  2695. *
  2696. * Return: void
  2697. */
  2698. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2699. enum htt_cmn_pkt_type val)
  2700. {
  2701. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2702. vdev->rx_decap_type = val;
  2703. }
  2704. /*
  2705. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2706. * @pdev_handle: physical device object
  2707. * @val: reo destination ring index (1 - 4)
  2708. *
  2709. * Return: void
  2710. */
  2711. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2712. enum cdp_host_reo_dest_ring val)
  2713. {
  2714. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2715. if (pdev)
  2716. pdev->reo_dest = val;
  2717. }
  2718. /*
  2719. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2720. * @pdev_handle: physical device object
  2721. *
  2722. * Return: reo destination ring index
  2723. */
  2724. static enum cdp_host_reo_dest_ring
  2725. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2726. {
  2727. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2728. if (pdev)
  2729. return pdev->reo_dest;
  2730. else
  2731. return cdp_host_reo_dest_ring_unknown;
  2732. }
  2733. #ifdef QCA_SUPPORT_SON
  2734. static void dp_son_peer_authorize(struct dp_peer *peer)
  2735. {
  2736. struct dp_soc *soc;
  2737. soc = peer->vdev->pdev->soc;
  2738. peer->peer_bs_inact_flag = 0;
  2739. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2740. return;
  2741. }
  2742. #else
  2743. static void dp_son_peer_authorize(struct dp_peer *peer)
  2744. {
  2745. return;
  2746. }
  2747. #endif
  2748. /*
  2749. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2750. * @pdev_handle: device object
  2751. * @val: value to be set
  2752. *
  2753. * Return: void
  2754. */
  2755. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2756. uint32_t val)
  2757. {
  2758. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2759. /* Enable/Disable smart mesh filtering. This flag will be checked
  2760. * during rx processing to check if packets are from NAC clients.
  2761. */
  2762. pdev->filter_neighbour_peers = val;
  2763. return 0;
  2764. }
  2765. /*
  2766. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2767. * address for smart mesh filtering
  2768. * @pdev_handle: device object
  2769. * @cmd: Add/Del command
  2770. * @macaddr: nac client mac address
  2771. *
  2772. * Return: void
  2773. */
  2774. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2775. uint32_t cmd, uint8_t *macaddr)
  2776. {
  2777. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2778. struct dp_neighbour_peer *peer = NULL;
  2779. if (!macaddr)
  2780. goto fail0;
  2781. /* Store address of NAC (neighbour peer) which will be checked
  2782. * against TA of received packets.
  2783. */
  2784. if (cmd == DP_NAC_PARAM_ADD) {
  2785. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2786. sizeof(*peer));
  2787. if (!peer) {
  2788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2789. FL("DP neighbour peer node memory allocation failed"));
  2790. goto fail0;
  2791. }
  2792. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2793. macaddr, DP_MAC_ADDR_LEN);
  2794. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2795. /* add this neighbour peer into the list */
  2796. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2797. neighbour_peer_list_elem);
  2798. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2799. return 1;
  2800. } else if (cmd == DP_NAC_PARAM_DEL) {
  2801. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2802. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2803. neighbour_peer_list_elem) {
  2804. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2805. macaddr, DP_MAC_ADDR_LEN)) {
  2806. /* delete this peer from the list */
  2807. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2808. peer, neighbour_peer_list_elem);
  2809. qdf_mem_free(peer);
  2810. break;
  2811. }
  2812. }
  2813. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2814. return 1;
  2815. }
  2816. fail0:
  2817. return 0;
  2818. }
  2819. /*
  2820. * dp_get_sec_type() - Get the security type
  2821. * @peer: Datapath peer handle
  2822. * @sec_idx: Security id (mcast, ucast)
  2823. *
  2824. * return sec_type: Security type
  2825. */
  2826. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2827. {
  2828. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2829. return dpeer->security[sec_idx].sec_type;
  2830. }
  2831. /*
  2832. * dp_peer_authorize() - authorize txrx peer
  2833. * @peer_handle: Datapath peer handle
  2834. * @authorize
  2835. *
  2836. */
  2837. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2838. {
  2839. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2840. struct dp_soc *soc;
  2841. if (peer != NULL) {
  2842. soc = peer->vdev->pdev->soc;
  2843. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2844. dp_son_peer_authorize(peer);
  2845. peer->authorize = authorize ? 1 : 0;
  2846. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2847. }
  2848. }
  2849. /*
  2850. * dp_peer_unref_delete() - unref and delete peer
  2851. * @peer_handle: Datapath peer handle
  2852. *
  2853. */
  2854. void dp_peer_unref_delete(void *peer_handle)
  2855. {
  2856. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2857. struct dp_vdev *vdev = peer->vdev;
  2858. struct dp_pdev *pdev = vdev->pdev;
  2859. struct dp_soc *soc = pdev->soc;
  2860. struct dp_peer *tmppeer;
  2861. int found = 0;
  2862. uint16_t peer_id;
  2863. /*
  2864. * Hold the lock all the way from checking if the peer ref count
  2865. * is zero until the peer references are removed from the hash
  2866. * table and vdev list (if the peer ref count is zero).
  2867. * This protects against a new HL tx operation starting to use the
  2868. * peer object just after this function concludes it's done being used.
  2869. * Furthermore, the lock needs to be held while checking whether the
  2870. * vdev's list of peers is empty, to make sure that list is not modified
  2871. * concurrently with the empty check.
  2872. */
  2873. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2874. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2875. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  2876. peer, qdf_atomic_read(&peer->ref_cnt));
  2877. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2878. peer_id = peer->peer_ids[0];
  2879. /*
  2880. * Make sure that the reference to the peer in
  2881. * peer object map is removed
  2882. */
  2883. if (peer_id != HTT_INVALID_PEER)
  2884. soc->peer_id_to_obj_map[peer_id] = NULL;
  2885. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2886. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  2887. /* remove the reference to the peer from the hash table */
  2888. dp_peer_find_hash_remove(soc, peer);
  2889. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2890. if (tmppeer == peer) {
  2891. found = 1;
  2892. break;
  2893. }
  2894. }
  2895. if (found) {
  2896. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2897. peer_list_elem);
  2898. } else {
  2899. /*Ignoring the remove operation as peer not found*/
  2900. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2901. "peer %p not found in vdev (%p)->peer_list:%p",
  2902. peer, vdev, &peer->vdev->peer_list);
  2903. }
  2904. /* cleanup the peer data */
  2905. dp_peer_cleanup(vdev, peer);
  2906. /* check whether the parent vdev has no peers left */
  2907. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2908. /*
  2909. * Now that there are no references to the peer, we can
  2910. * release the peer reference lock.
  2911. */
  2912. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2913. /*
  2914. * Check if the parent vdev was waiting for its peers
  2915. * to be deleted, in order for it to be deleted too.
  2916. */
  2917. if (vdev->delete.pending) {
  2918. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2919. vdev->delete.callback;
  2920. void *vdev_delete_context =
  2921. vdev->delete.context;
  2922. QDF_TRACE(QDF_MODULE_ID_DP,
  2923. QDF_TRACE_LEVEL_INFO_HIGH,
  2924. FL("deleting vdev object %p (%pM)"
  2925. " - its last peer is done"),
  2926. vdev, vdev->mac_addr.raw);
  2927. /* all peers are gone, go ahead and delete it */
  2928. qdf_mem_free(vdev);
  2929. if (vdev_delete_cb)
  2930. vdev_delete_cb(vdev_delete_context);
  2931. }
  2932. } else {
  2933. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2934. }
  2935. #ifdef notyet
  2936. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2937. #else
  2938. qdf_mem_free(peer);
  2939. #endif
  2940. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2941. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2942. vdev->vdev_id, peer->mac_addr.raw);
  2943. }
  2944. } else {
  2945. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2946. }
  2947. }
  2948. /*
  2949. * dp_peer_detach_wifi3() – Detach txrx peer
  2950. * @peer_handle: Datapath peer handle
  2951. *
  2952. */
  2953. static void dp_peer_delete_wifi3(void *peer_handle)
  2954. {
  2955. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2956. /* redirect the peer's rx delivery function to point to a
  2957. * discard func
  2958. */
  2959. peer->rx_opt_proc = dp_rx_discard;
  2960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2961. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  2962. #ifndef CONFIG_WIN
  2963. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2964. #endif
  2965. qdf_spinlock_destroy(&peer->peer_info_lock);
  2966. /*
  2967. * Remove the reference added during peer_attach.
  2968. * The peer will still be left allocated until the
  2969. * PEER_UNMAP message arrives to remove the other
  2970. * reference, added by the PEER_MAP message.
  2971. */
  2972. dp_peer_unref_delete(peer_handle);
  2973. }
  2974. /*
  2975. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2976. * @peer_handle: Datapath peer handle
  2977. *
  2978. */
  2979. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2980. {
  2981. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2982. return vdev->mac_addr.raw;
  2983. }
  2984. /*
  2985. * dp_vdev_set_wds() - Enable per packet stats
  2986. * @vdev_handle: DP VDEV handle
  2987. * @val: value
  2988. *
  2989. * Return: none
  2990. */
  2991. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2992. {
  2993. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2994. vdev->wds_enabled = val;
  2995. return 0;
  2996. }
  2997. /*
  2998. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2999. * @peer_handle: Datapath peer handle
  3000. *
  3001. */
  3002. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3003. uint8_t vdev_id)
  3004. {
  3005. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3006. struct dp_vdev *vdev = NULL;
  3007. if (qdf_unlikely(!pdev))
  3008. return NULL;
  3009. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3010. if (vdev->vdev_id == vdev_id)
  3011. break;
  3012. }
  3013. return (struct cdp_vdev *)vdev;
  3014. }
  3015. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3016. {
  3017. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3018. return vdev->opmode;
  3019. }
  3020. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3021. {
  3022. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3023. struct dp_pdev *pdev = vdev->pdev;
  3024. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3025. }
  3026. /**
  3027. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3028. * @vdev_handle: Datapath VDEV handle
  3029. * @smart_monitor: Flag to denote if its smart monitor mode
  3030. *
  3031. * Return: 0 on success, not 0 on failure
  3032. */
  3033. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3034. uint8_t smart_monitor)
  3035. {
  3036. /* Many monitor VAPs can exists in a system but only one can be up at
  3037. * anytime
  3038. */
  3039. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3040. struct dp_pdev *pdev;
  3041. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3042. struct dp_soc *soc;
  3043. uint8_t pdev_id;
  3044. qdf_assert(vdev);
  3045. pdev = vdev->pdev;
  3046. pdev_id = pdev->pdev_id;
  3047. soc = pdev->soc;
  3048. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3049. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  3050. pdev, pdev_id, soc, vdev);
  3051. /*Check if current pdev's monitor_vdev exists */
  3052. if (pdev->monitor_vdev) {
  3053. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3054. "vdev=%p\n", vdev);
  3055. qdf_assert(vdev);
  3056. }
  3057. pdev->monitor_vdev = vdev;
  3058. /* If smart monitor mode, do not configure monitor ring */
  3059. if (smart_monitor)
  3060. return QDF_STATUS_SUCCESS;
  3061. htt_tlv_filter.mpdu_start = 1;
  3062. htt_tlv_filter.msdu_start = 1;
  3063. htt_tlv_filter.packet = 1;
  3064. htt_tlv_filter.msdu_end = 1;
  3065. htt_tlv_filter.mpdu_end = 1;
  3066. htt_tlv_filter.packet_header = 1;
  3067. htt_tlv_filter.attention = 1;
  3068. htt_tlv_filter.ppdu_start = 0;
  3069. htt_tlv_filter.ppdu_end = 0;
  3070. htt_tlv_filter.ppdu_end_user_stats = 0;
  3071. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3072. htt_tlv_filter.ppdu_end_status_done = 0;
  3073. htt_tlv_filter.enable_fp = 1;
  3074. htt_tlv_filter.enable_md = 0;
  3075. htt_tlv_filter.enable_mo = 1;
  3076. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3077. pdev->rxdma_mon_buf_ring.hal_srng,
  3078. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3079. htt_tlv_filter.mpdu_start = 1;
  3080. htt_tlv_filter.msdu_start = 1;
  3081. htt_tlv_filter.packet = 0;
  3082. htt_tlv_filter.msdu_end = 1;
  3083. htt_tlv_filter.mpdu_end = 1;
  3084. htt_tlv_filter.packet_header = 1;
  3085. htt_tlv_filter.attention = 1;
  3086. htt_tlv_filter.ppdu_start = 1;
  3087. htt_tlv_filter.ppdu_end = 1;
  3088. htt_tlv_filter.ppdu_end_user_stats = 1;
  3089. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3090. htt_tlv_filter.ppdu_end_status_done = 1;
  3091. htt_tlv_filter.enable_fp = 1;
  3092. htt_tlv_filter.enable_md = 0;
  3093. htt_tlv_filter.enable_mo = 1;
  3094. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3095. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3096. RX_BUFFER_SIZE, &htt_tlv_filter);
  3097. return QDF_STATUS_SUCCESS;
  3098. }
  3099. #ifdef MESH_MODE_SUPPORT
  3100. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3101. {
  3102. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3103. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3104. FL("val %d"), val);
  3105. vdev->mesh_vdev = val;
  3106. }
  3107. /*
  3108. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3109. * @vdev_hdl: virtual device object
  3110. * @val: value to be set
  3111. *
  3112. * Return: void
  3113. */
  3114. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3115. {
  3116. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3117. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3118. FL("val %d"), val);
  3119. vdev->mesh_rx_filter = val;
  3120. }
  3121. #endif
  3122. /**
  3123. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3124. * @vdev: DP VDEV handle
  3125. *
  3126. * return: void
  3127. */
  3128. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3129. {
  3130. struct dp_peer *peer = NULL;
  3131. struct dp_soc *soc = vdev->pdev->soc;
  3132. int i;
  3133. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3134. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3135. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3136. if (!peer)
  3137. return;
  3138. for (i = 0; i < MAX_MCS; i++) {
  3139. DP_STATS_AGGR(vdev, peer, tx.pkt_type[0].mcs_count[i]);
  3140. DP_STATS_AGGR(vdev, peer, tx.pkt_type[1].mcs_count[i]);
  3141. DP_STATS_AGGR(vdev, peer, tx.pkt_type[2].mcs_count[i]);
  3142. DP_STATS_AGGR(vdev, peer, tx.pkt_type[3].mcs_count[i]);
  3143. DP_STATS_AGGR(vdev, peer, tx.pkt_type[4].mcs_count[i]);
  3144. DP_STATS_AGGR(vdev, peer, rx.pkt_type[0].mcs_count[i]);
  3145. DP_STATS_AGGR(vdev, peer, rx.pkt_type[1].mcs_count[i]);
  3146. DP_STATS_AGGR(vdev, peer, rx.pkt_type[2].mcs_count[i]);
  3147. DP_STATS_AGGR(vdev, peer, rx.pkt_type[3].mcs_count[i]);
  3148. DP_STATS_AGGR(vdev, peer, rx.pkt_type[4].mcs_count[i]);
  3149. }
  3150. for (i = 0; i < MAX_BW; i++) {
  3151. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3152. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3153. }
  3154. for (i = 0; i < SS_COUNT; i++)
  3155. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3156. for (i = 0; i < WME_AC_MAX; i++) {
  3157. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3158. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3159. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3160. }
  3161. for (i = 0; i < MAX_GI; i++) {
  3162. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3163. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3164. }
  3165. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3166. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3167. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3168. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3169. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3170. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3171. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3172. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3173. DP_STATS_AGGR(vdev, peer, tx.retries);
  3174. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3175. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3176. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3177. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3178. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3179. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3180. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3181. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3182. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3183. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3184. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3185. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3186. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3187. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3188. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3189. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3190. peer->stats.rx.multicast.num;
  3191. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3192. peer->stats.rx.multicast.bytes;
  3193. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3194. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3195. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3196. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3197. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3198. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3199. vdev->stats.tx.last_ack_rssi =
  3200. peer->stats.tx.last_ack_rssi;
  3201. }
  3202. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3203. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3204. }
  3205. /**
  3206. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3207. * @pdev: DP PDEV handle
  3208. *
  3209. * return: void
  3210. */
  3211. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3212. {
  3213. struct dp_vdev *vdev = NULL;
  3214. uint8_t i;
  3215. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3216. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3217. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3218. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3219. if (!vdev)
  3220. return;
  3221. dp_aggregate_vdev_stats(vdev);
  3222. for (i = 0; i < MAX_MCS; i++) {
  3223. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[0].mcs_count[i]);
  3224. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[1].mcs_count[i]);
  3225. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[2].mcs_count[i]);
  3226. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[3].mcs_count[i]);
  3227. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[4].mcs_count[i]);
  3228. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[0].mcs_count[i]);
  3229. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[1].mcs_count[i]);
  3230. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[2].mcs_count[i]);
  3231. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[3].mcs_count[i]);
  3232. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[4].mcs_count[i]);
  3233. }
  3234. for (i = 0; i < MAX_BW; i++) {
  3235. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3236. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3237. }
  3238. for (i = 0; i < SS_COUNT; i++)
  3239. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3240. for (i = 0; i < WME_AC_MAX; i++) {
  3241. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3242. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3243. DP_STATS_AGGR(pdev, vdev,
  3244. tx.excess_retries_ac[i]);
  3245. }
  3246. for (i = 0; i < MAX_GI; i++) {
  3247. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3248. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3249. }
  3250. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3251. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3252. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3253. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3254. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3255. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3256. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3257. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3258. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3259. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3260. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3261. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3262. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3263. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3264. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3265. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3266. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3267. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3268. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3269. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3270. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3271. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3272. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3273. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3274. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3275. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3276. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3277. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3278. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3279. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3280. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3281. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3282. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3283. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3284. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3285. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3286. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3287. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3288. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3289. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3290. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3291. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3292. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3293. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3294. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3295. DP_STATS_AGGR(pdev, vdev,
  3296. tx_i.mcast_en.dropped_map_error);
  3297. DP_STATS_AGGR(pdev, vdev,
  3298. tx_i.mcast_en.dropped_self_mac);
  3299. DP_STATS_AGGR(pdev, vdev,
  3300. tx_i.mcast_en.dropped_send_fail);
  3301. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3302. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3303. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3304. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3305. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3306. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3307. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3308. pdev->stats.tx_i.dropped.dma_error +
  3309. pdev->stats.tx_i.dropped.ring_full +
  3310. pdev->stats.tx_i.dropped.enqueue_fail +
  3311. pdev->stats.tx_i.dropped.desc_na +
  3312. pdev->stats.tx_i.dropped.res_full;
  3313. pdev->stats.tx.last_ack_rssi =
  3314. vdev->stats.tx.last_ack_rssi;
  3315. pdev->stats.tx_i.tso.num_seg =
  3316. vdev->stats.tx_i.tso.num_seg;
  3317. }
  3318. }
  3319. /**
  3320. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3321. * @pdev: DP_PDEV Handle
  3322. *
  3323. * Return:void
  3324. */
  3325. static inline void
  3326. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3327. {
  3328. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3329. DP_PRINT_STATS("Received From Stack:");
  3330. DP_PRINT_STATS(" Packets = %d",
  3331. pdev->stats.tx_i.rcvd.num);
  3332. DP_PRINT_STATS(" Bytes = %d",
  3333. pdev->stats.tx_i.rcvd.bytes);
  3334. DP_PRINT_STATS("Processed:");
  3335. DP_PRINT_STATS(" Packets = %d",
  3336. pdev->stats.tx_i.processed.num);
  3337. DP_PRINT_STATS(" Bytes = %d",
  3338. pdev->stats.tx_i.processed.bytes);
  3339. DP_PRINT_STATS("Completions:");
  3340. DP_PRINT_STATS(" Packets = %d",
  3341. pdev->stats.tx.comp_pkt.num);
  3342. DP_PRINT_STATS(" Bytes = %d",
  3343. pdev->stats.tx.comp_pkt.bytes);
  3344. DP_PRINT_STATS("Dropped:");
  3345. DP_PRINT_STATS(" Total = %d",
  3346. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3347. DP_PRINT_STATS(" Dma_map_error = %d",
  3348. pdev->stats.tx_i.dropped.dma_error);
  3349. DP_PRINT_STATS(" Ring Full = %d",
  3350. pdev->stats.tx_i.dropped.ring_full);
  3351. DP_PRINT_STATS(" Descriptor Not available = %d",
  3352. pdev->stats.tx_i.dropped.desc_na);
  3353. DP_PRINT_STATS(" HW enqueue failed= %d",
  3354. pdev->stats.tx_i.dropped.enqueue_fail);
  3355. DP_PRINT_STATS(" Resources Full = %d",
  3356. pdev->stats.tx_i.dropped.res_full);
  3357. DP_PRINT_STATS(" FW removed = %d",
  3358. pdev->stats.tx.dropped.fw_rem);
  3359. DP_PRINT_STATS(" FW removed transmitted = %d",
  3360. pdev->stats.tx.dropped.fw_rem_tx);
  3361. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3362. pdev->stats.tx.dropped.fw_rem_notx);
  3363. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3364. pdev->stats.tx.dropped.age_out);
  3365. DP_PRINT_STATS("Scatter Gather:");
  3366. DP_PRINT_STATS(" Packets = %d",
  3367. pdev->stats.tx_i.sg.sg_pkt.num);
  3368. DP_PRINT_STATS(" Bytes = %d",
  3369. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3370. DP_PRINT_STATS(" Dropped By Host = %d",
  3371. pdev->stats.tx_i.sg.dropped_host);
  3372. DP_PRINT_STATS(" Dropped By Target = %d",
  3373. pdev->stats.tx_i.sg.dropped_target);
  3374. DP_PRINT_STATS("TSO:");
  3375. DP_PRINT_STATS(" Number of Segments = %d",
  3376. pdev->stats.tx_i.tso.num_seg);
  3377. DP_PRINT_STATS(" Packets = %d",
  3378. pdev->stats.tx_i.tso.tso_pkt.num);
  3379. DP_PRINT_STATS(" Bytes = %d",
  3380. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3381. DP_PRINT_STATS(" Dropped By Host = %d",
  3382. pdev->stats.tx_i.tso.dropped_host);
  3383. DP_PRINT_STATS("Mcast Enhancement:");
  3384. DP_PRINT_STATS(" Packets = %d",
  3385. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3386. DP_PRINT_STATS(" Bytes = %d",
  3387. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3388. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3389. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3390. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3391. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3392. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3393. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3394. DP_PRINT_STATS(" Unicast sent = %d",
  3395. pdev->stats.tx_i.mcast_en.ucast);
  3396. DP_PRINT_STATS("Raw:");
  3397. DP_PRINT_STATS(" Packets = %d",
  3398. pdev->stats.tx_i.raw.raw_pkt.num);
  3399. DP_PRINT_STATS(" Bytes = %d",
  3400. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3401. DP_PRINT_STATS(" DMA map error = %d",
  3402. pdev->stats.tx_i.raw.dma_map_error);
  3403. DP_PRINT_STATS("Reinjected:");
  3404. DP_PRINT_STATS(" Packets = %d",
  3405. pdev->stats.tx_i.reinject_pkts.num);
  3406. DP_PRINT_STATS("Bytes = %d\n",
  3407. pdev->stats.tx_i.reinject_pkts.bytes);
  3408. DP_PRINT_STATS("Inspected:");
  3409. DP_PRINT_STATS(" Packets = %d",
  3410. pdev->stats.tx_i.inspect_pkts.num);
  3411. DP_PRINT_STATS(" Bytes = %d",
  3412. pdev->stats.tx_i.inspect_pkts.bytes);
  3413. }
  3414. /**
  3415. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3416. * @pdev: DP_PDEV Handle
  3417. *
  3418. * Return: void
  3419. */
  3420. static inline void
  3421. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3422. {
  3423. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3424. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3425. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3426. pdev->stats.rx.rcvd_reo[0].num,
  3427. pdev->stats.rx.rcvd_reo[1].num,
  3428. pdev->stats.rx.rcvd_reo[2].num,
  3429. pdev->stats.rx.rcvd_reo[3].num);
  3430. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3431. pdev->stats.rx.rcvd_reo[0].bytes,
  3432. pdev->stats.rx.rcvd_reo[1].bytes,
  3433. pdev->stats.rx.rcvd_reo[2].bytes,
  3434. pdev->stats.rx.rcvd_reo[3].bytes);
  3435. DP_PRINT_STATS("Replenished:");
  3436. DP_PRINT_STATS(" Packets = %d",
  3437. pdev->stats.replenish.pkts.num);
  3438. DP_PRINT_STATS(" Bytes = %d",
  3439. pdev->stats.replenish.pkts.bytes);
  3440. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3441. pdev->stats.buf_freelist);
  3442. DP_PRINT_STATS("Dropped:");
  3443. DP_PRINT_STATS(" msdu_not_done = %d",
  3444. pdev->stats.dropped.msdu_not_done);
  3445. DP_PRINT_STATS("Sent To Stack:");
  3446. DP_PRINT_STATS(" Packets = %d",
  3447. pdev->stats.rx.to_stack.num);
  3448. DP_PRINT_STATS(" Bytes = %d",
  3449. pdev->stats.rx.to_stack.bytes);
  3450. DP_PRINT_STATS("Multicast/Broadcast:");
  3451. DP_PRINT_STATS(" Packets = %d",
  3452. pdev->stats.rx.multicast.num);
  3453. DP_PRINT_STATS(" Bytes = %d",
  3454. pdev->stats.rx.multicast.bytes);
  3455. DP_PRINT_STATS("Errors:");
  3456. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3457. pdev->stats.replenish.rxdma_err);
  3458. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3459. pdev->stats.err.desc_alloc_fail);
  3460. }
  3461. /**
  3462. * dp_print_soc_tx_stats(): Print SOC level stats
  3463. * @soc DP_SOC Handle
  3464. *
  3465. * Return: void
  3466. */
  3467. static inline void
  3468. dp_print_soc_tx_stats(struct dp_soc *soc)
  3469. {
  3470. DP_PRINT_STATS("SOC Tx Stats:\n");
  3471. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3472. soc->stats.tx.desc_in_use);
  3473. DP_PRINT_STATS("Invalid peer:");
  3474. DP_PRINT_STATS(" Packets = %d",
  3475. soc->stats.tx.tx_invalid_peer.num);
  3476. DP_PRINT_STATS(" Bytes = %d",
  3477. soc->stats.tx.tx_invalid_peer.bytes);
  3478. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3479. soc->stats.tx.tcl_ring_full[0],
  3480. soc->stats.tx.tcl_ring_full[1],
  3481. soc->stats.tx.tcl_ring_full[2]);
  3482. }
  3483. /**
  3484. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3485. * @soc: DP_SOC Handle
  3486. *
  3487. * Return:void
  3488. */
  3489. static inline void
  3490. dp_print_soc_rx_stats(struct dp_soc *soc)
  3491. {
  3492. uint32_t i;
  3493. char reo_error[DP_REO_ERR_LENGTH];
  3494. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3495. uint8_t index = 0;
  3496. DP_PRINT_STATS("SOC Rx Stats:\n");
  3497. DP_PRINT_STATS("Errors:\n");
  3498. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3499. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3500. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3501. DP_PRINT_STATS("Invalid RBM = %d",
  3502. soc->stats.rx.err.invalid_rbm);
  3503. DP_PRINT_STATS("Invalid Vdev = %d",
  3504. soc->stats.rx.err.invalid_vdev);
  3505. DP_PRINT_STATS("Invalid Pdev = %d",
  3506. soc->stats.rx.err.invalid_pdev);
  3507. DP_PRINT_STATS("Invalid Peer = %d",
  3508. soc->stats.rx.err.rx_invalid_peer.num);
  3509. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3510. soc->stats.rx.err.hal_ring_access_fail);
  3511. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3512. index += qdf_snprint(&rxdma_error[index],
  3513. DP_RXDMA_ERR_LENGTH - index,
  3514. " %d", soc->stats.rx.err.rxdma_error[i]);
  3515. }
  3516. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3517. rxdma_error);
  3518. index = 0;
  3519. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3520. index += qdf_snprint(&reo_error[index],
  3521. DP_REO_ERR_LENGTH - index,
  3522. " %d", soc->stats.rx.err.reo_error[i]);
  3523. }
  3524. DP_PRINT_STATS("REO Error(0-14):%s",
  3525. reo_error);
  3526. }
  3527. /**
  3528. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3529. * @vdev: DP_VDEV handle
  3530. *
  3531. * Return:void
  3532. */
  3533. static inline void
  3534. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3535. {
  3536. struct dp_peer *peer = NULL;
  3537. DP_STATS_CLR(vdev->pdev);
  3538. DP_STATS_CLR(vdev->pdev->soc);
  3539. DP_STATS_CLR(vdev);
  3540. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3541. if (!peer)
  3542. return;
  3543. DP_STATS_CLR(peer);
  3544. }
  3545. }
  3546. /**
  3547. * dp_print_rx_rates(): Print Rx rate stats
  3548. * @vdev: DP_VDEV handle
  3549. *
  3550. * Return:void
  3551. */
  3552. static inline void
  3553. dp_print_rx_rates(struct dp_vdev *vdev)
  3554. {
  3555. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3556. uint8_t i, mcs, pkt_type;
  3557. uint8_t index = 0;
  3558. char nss[DP_NSS_LENGTH];
  3559. DP_PRINT_STATS("Rx Rate Info:\n");
  3560. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3561. index = 0;
  3562. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3563. if (!dp_rate_string[pkt_type][mcs].valid)
  3564. continue;
  3565. DP_PRINT_STATS(" %s = %d",
  3566. dp_rate_string[pkt_type][mcs].mcs_type,
  3567. pdev->stats.rx.pkt_type[pkt_type].
  3568. mcs_count[mcs]);
  3569. }
  3570. DP_PRINT_STATS("\n");
  3571. }
  3572. index = 0;
  3573. for (i = 0; i < SS_COUNT; i++) {
  3574. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3575. " %d", pdev->stats.rx.nss[i]);
  3576. }
  3577. DP_PRINT_STATS("NSS(0-7) = %s",
  3578. nss);
  3579. DP_PRINT_STATS("SGI ="
  3580. " 0.8us %d,"
  3581. " 0.4us %d,"
  3582. " 1.6us %d,"
  3583. " 3.2us %d,",
  3584. pdev->stats.rx.sgi_count[0],
  3585. pdev->stats.rx.sgi_count[1],
  3586. pdev->stats.rx.sgi_count[2],
  3587. pdev->stats.rx.sgi_count[3]);
  3588. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3589. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3590. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3591. DP_PRINT_STATS("Reception Type ="
  3592. " SU: %d,"
  3593. " MU_MIMO:%d,"
  3594. " MU_OFDMA:%d,"
  3595. " MU_OFDMA_MIMO:%d\n",
  3596. pdev->stats.rx.reception_type[0],
  3597. pdev->stats.rx.reception_type[1],
  3598. pdev->stats.rx.reception_type[2],
  3599. pdev->stats.rx.reception_type[3]);
  3600. DP_PRINT_STATS("Aggregation:\n");
  3601. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3602. pdev->stats.rx.ampdu_cnt);
  3603. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3604. pdev->stats.rx.non_ampdu_cnt);
  3605. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3606. pdev->stats.rx.amsdu_cnt);
  3607. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3608. pdev->stats.rx.non_amsdu_cnt);
  3609. }
  3610. /**
  3611. * dp_print_tx_rates(): Print tx rates
  3612. * @vdev: DP_VDEV handle
  3613. *
  3614. * Return:void
  3615. */
  3616. static inline void
  3617. dp_print_tx_rates(struct dp_vdev *vdev)
  3618. {
  3619. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3620. uint8_t mcs, pkt_type;
  3621. uint32_t index;
  3622. DP_PRINT_STATS("Tx Rate Info:\n");
  3623. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3624. index = 0;
  3625. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3626. if (!dp_rate_string[pkt_type][mcs].valid)
  3627. continue;
  3628. DP_PRINT_STATS(" %s = %d",
  3629. dp_rate_string[pkt_type][mcs].mcs_type,
  3630. pdev->stats.tx.pkt_type[pkt_type].
  3631. mcs_count[mcs]);
  3632. }
  3633. DP_PRINT_STATS("\n");
  3634. }
  3635. DP_PRINT_STATS("SGI ="
  3636. " 0.8us %d"
  3637. " 0.4us %d"
  3638. " 1.6us %d"
  3639. " 3.2us %d",
  3640. pdev->stats.tx.sgi_count[0],
  3641. pdev->stats.tx.sgi_count[1],
  3642. pdev->stats.tx.sgi_count[2],
  3643. pdev->stats.tx.sgi_count[3]);
  3644. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3645. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3646. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3647. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3648. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3649. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3650. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3651. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3652. DP_PRINT_STATS("Aggregation:\n");
  3653. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3654. pdev->stats.tx.amsdu_cnt);
  3655. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3656. pdev->stats.tx.non_amsdu_cnt);
  3657. }
  3658. /**
  3659. * dp_print_peer_stats():print peer stats
  3660. * @peer: DP_PEER handle
  3661. *
  3662. * return void
  3663. */
  3664. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3665. {
  3666. uint8_t i, mcs, pkt_type;
  3667. uint32_t index;
  3668. char nss[DP_NSS_LENGTH];
  3669. DP_PRINT_STATS("Node Tx Stats:\n");
  3670. DP_PRINT_STATS("Total Packet Completions = %d",
  3671. peer->stats.tx.comp_pkt.num);
  3672. DP_PRINT_STATS("Total Bytes Completions = %d",
  3673. peer->stats.tx.comp_pkt.bytes);
  3674. DP_PRINT_STATS("Success Packets = %d",
  3675. peer->stats.tx.tx_success.num);
  3676. DP_PRINT_STATS("Success Bytes = %d",
  3677. peer->stats.tx.tx_success.bytes);
  3678. DP_PRINT_STATS("Packets Failed = %d",
  3679. peer->stats.tx.tx_failed);
  3680. DP_PRINT_STATS("Packets In OFDMA = %d",
  3681. peer->stats.tx.ofdma);
  3682. DP_PRINT_STATS("Packets In STBC = %d",
  3683. peer->stats.tx.stbc);
  3684. DP_PRINT_STATS("Packets In LDPC = %d",
  3685. peer->stats.tx.ldpc);
  3686. DP_PRINT_STATS("Packet Retries = %d",
  3687. peer->stats.tx.retries);
  3688. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3689. peer->stats.tx.amsdu_cnt);
  3690. DP_PRINT_STATS("Last Packet RSSI = %d",
  3691. peer->stats.tx.last_ack_rssi);
  3692. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3693. peer->stats.tx.dropped.fw_rem);
  3694. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3695. peer->stats.tx.dropped.fw_rem_tx);
  3696. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3697. peer->stats.tx.dropped.fw_rem_notx);
  3698. DP_PRINT_STATS("Dropped : Age Out = %d",
  3699. peer->stats.tx.dropped.age_out);
  3700. DP_PRINT_STATS("Rate Info:");
  3701. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3702. index = 0;
  3703. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3704. if (!dp_rate_string[pkt_type][mcs].valid)
  3705. continue;
  3706. DP_PRINT_STATS(" %s = %d",
  3707. dp_rate_string[pkt_type][mcs].mcs_type,
  3708. peer->stats.tx.pkt_type[pkt_type].
  3709. mcs_count[mcs]);
  3710. }
  3711. DP_PRINT_STATS("\n");
  3712. }
  3713. DP_PRINT_STATS("SGI = "
  3714. " 0.8us %d"
  3715. " 0.4us %d"
  3716. " 1.6us %d"
  3717. " 3.2us %d",
  3718. peer->stats.tx.sgi_count[0],
  3719. peer->stats.tx.sgi_count[1],
  3720. peer->stats.tx.sgi_count[2],
  3721. peer->stats.tx.sgi_count[3]);
  3722. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3723. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3724. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3725. DP_PRINT_STATS("Aggregation:");
  3726. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3727. peer->stats.tx.amsdu_cnt);
  3728. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3729. peer->stats.tx.non_amsdu_cnt);
  3730. DP_PRINT_STATS("Node Rx Stats:");
  3731. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3732. peer->stats.rx.to_stack.num);
  3733. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3734. peer->stats.rx.to_stack.bytes);
  3735. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3736. DP_PRINT_STATS("Packets Received = %d",
  3737. peer->stats.rx.rcvd_reo[i].num);
  3738. DP_PRINT_STATS("Bytes Received = %d",
  3739. peer->stats.rx.rcvd_reo[i].bytes);
  3740. }
  3741. DP_PRINT_STATS("Multicast Packets Received = %d",
  3742. peer->stats.rx.multicast.num);
  3743. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3744. peer->stats.rx.multicast.bytes);
  3745. DP_PRINT_STATS("WDS Packets Received = %d",
  3746. peer->stats.rx.wds.num);
  3747. DP_PRINT_STATS("WDS Bytes Received = %d",
  3748. peer->stats.rx.wds.bytes);
  3749. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3750. peer->stats.rx.intra_bss.pkts.num);
  3751. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3752. peer->stats.rx.intra_bss.pkts.bytes);
  3753. DP_PRINT_STATS("Raw Packets Received = %d",
  3754. peer->stats.rx.raw.num);
  3755. DP_PRINT_STATS("Raw Bytes Received = %d",
  3756. peer->stats.rx.raw.bytes);
  3757. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3758. peer->stats.rx.err.mic_err);
  3759. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3760. peer->stats.rx.err.decrypt_err);
  3761. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3762. peer->stats.rx.non_ampdu_cnt);
  3763. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3764. peer->stats.rx.ampdu_cnt);
  3765. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3766. peer->stats.rx.non_amsdu_cnt);
  3767. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3768. peer->stats.rx.amsdu_cnt);
  3769. DP_PRINT_STATS("SGI ="
  3770. " 0.8us %d"
  3771. " 0.4us %d"
  3772. " 1.6us %d"
  3773. " 3.2us %d",
  3774. peer->stats.rx.sgi_count[0],
  3775. peer->stats.rx.sgi_count[1],
  3776. peer->stats.rx.sgi_count[2],
  3777. peer->stats.rx.sgi_count[3]);
  3778. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3779. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3780. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3781. DP_PRINT_STATS("Reception Type ="
  3782. " SU %d,"
  3783. " MU_MIMO %d,"
  3784. " MU_OFDMA %d,"
  3785. " MU_OFDMA_MIMO %d",
  3786. peer->stats.rx.reception_type[0],
  3787. peer->stats.rx.reception_type[1],
  3788. peer->stats.rx.reception_type[2],
  3789. peer->stats.rx.reception_type[3]);
  3790. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3791. index = 0;
  3792. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3793. if (!dp_rate_string[pkt_type][mcs].valid)
  3794. continue;
  3795. DP_PRINT_STATS(" %s = %d",
  3796. dp_rate_string[pkt_type][mcs].mcs_type,
  3797. peer->stats.rx.pkt_type[pkt_type].
  3798. mcs_count[mcs]);
  3799. }
  3800. DP_PRINT_STATS("\n");
  3801. }
  3802. index = 0;
  3803. for (i = 0; i < SS_COUNT; i++) {
  3804. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3805. " %d", peer->stats.rx.nss[i]);
  3806. }
  3807. DP_PRINT_STATS("NSS(0-7) = %s",
  3808. nss);
  3809. DP_PRINT_STATS("Aggregation:");
  3810. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3811. peer->stats.rx.ampdu_cnt);
  3812. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3813. peer->stats.rx.non_ampdu_cnt);
  3814. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3815. peer->stats.rx.amsdu_cnt);
  3816. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3817. peer->stats.rx.non_amsdu_cnt);
  3818. }
  3819. /**
  3820. * dp_print_host_stats()- Function to print the stats aggregated at host
  3821. * @vdev_handle: DP_VDEV handle
  3822. * @type: host stats type
  3823. *
  3824. * Available Stat types
  3825. * TXRX_CLEAR_STATS : Clear the stats
  3826. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3827. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3828. * TXRX_TX_HOST_STATS: Print Tx Stats
  3829. * TXRX_RX_HOST_STATS: Print Rx Stats
  3830. * TXRX_AST_STATS: Print AST Stats
  3831. *
  3832. * Return: 0 on success, print error message in case of failure
  3833. */
  3834. static int
  3835. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3836. {
  3837. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3838. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3839. dp_aggregate_pdev_stats(pdev);
  3840. switch (type) {
  3841. case TXRX_CLEAR_STATS:
  3842. dp_txrx_host_stats_clr(vdev);
  3843. break;
  3844. case TXRX_RX_RATE_STATS:
  3845. dp_print_rx_rates(vdev);
  3846. break;
  3847. case TXRX_TX_RATE_STATS:
  3848. dp_print_tx_rates(vdev);
  3849. break;
  3850. case TXRX_TX_HOST_STATS:
  3851. dp_print_pdev_tx_stats(pdev);
  3852. dp_print_soc_tx_stats(pdev->soc);
  3853. break;
  3854. case TXRX_RX_HOST_STATS:
  3855. dp_print_pdev_rx_stats(pdev);
  3856. dp_print_soc_rx_stats(pdev->soc);
  3857. break;
  3858. case TXRX_AST_STATS:
  3859. dp_print_ast_stats(pdev->soc);
  3860. break;
  3861. default:
  3862. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3863. break;
  3864. }
  3865. return 0;
  3866. }
  3867. /*
  3868. * dp_get_host_peer_stats()- function to print peer stats
  3869. * @pdev_handle: DP_PDEV handle
  3870. * @mac_addr: mac address of the peer
  3871. *
  3872. * Return: void
  3873. */
  3874. static void
  3875. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3876. {
  3877. struct dp_peer *peer;
  3878. uint8_t local_id;
  3879. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3880. &local_id);
  3881. if (!peer) {
  3882. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3883. "%s: Invalid peer\n", __func__);
  3884. return;
  3885. }
  3886. dp_print_peer_stats(peer);
  3887. dp_peer_rxtid_stats(peer);
  3888. return;
  3889. }
  3890. /*
  3891. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3892. * @pdev_handle: DP_PDEV handle
  3893. *
  3894. * Return: void
  3895. */
  3896. static void
  3897. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3898. {
  3899. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3900. pdev->enhanced_stats_en = 1;
  3901. }
  3902. /*
  3903. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3904. * @pdev_handle: DP_PDEV handle
  3905. *
  3906. * Return: void
  3907. */
  3908. static void
  3909. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3910. {
  3911. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3912. pdev->enhanced_stats_en = 0;
  3913. }
  3914. /*
  3915. * dp_get_fw_peer_stats()- function to print peer stats
  3916. * @pdev_handle: DP_PDEV handle
  3917. * @mac_addr: mac address of the peer
  3918. * @cap: Type of htt stats requested
  3919. *
  3920. * Currently Supporting only MAC ID based requests Only
  3921. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3922. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3923. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3924. *
  3925. * Return: void
  3926. */
  3927. static void
  3928. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3929. uint32_t cap)
  3930. {
  3931. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3932. uint32_t config_param0 = 0;
  3933. uint32_t config_param1 = 0;
  3934. uint32_t config_param2 = 0;
  3935. uint32_t config_param3 = 0;
  3936. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3937. config_param0 |= (1 << (cap + 1));
  3938. config_param1 = 0x8f;
  3939. config_param2 |= (mac_addr[0] & 0x000000ff);
  3940. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3941. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3942. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3943. config_param3 |= (mac_addr[4] & 0x000000ff);
  3944. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3945. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3946. config_param0, config_param1, config_param2,
  3947. config_param3);
  3948. }
  3949. /*
  3950. * dp_set_vdev_param: function to set parameters in vdev
  3951. * @param: parameter type to be set
  3952. * @val: value of parameter to be set
  3953. *
  3954. * return: void
  3955. */
  3956. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3957. enum cdp_vdev_param_type param, uint32_t val)
  3958. {
  3959. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3960. switch (param) {
  3961. case CDP_ENABLE_WDS:
  3962. vdev->wds_enabled = val;
  3963. break;
  3964. case CDP_ENABLE_NAWDS:
  3965. vdev->nawds_enabled = val;
  3966. break;
  3967. case CDP_ENABLE_MCAST_EN:
  3968. vdev->mcast_enhancement_en = val;
  3969. break;
  3970. case CDP_ENABLE_PROXYSTA:
  3971. vdev->proxysta_vdev = val;
  3972. break;
  3973. case CDP_UPDATE_TDLS_FLAGS:
  3974. vdev->tdls_link_connected = val;
  3975. break;
  3976. case CDP_CFG_WDS_AGING_TIMER:
  3977. if (val == 0)
  3978. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  3979. else if (val != vdev->wds_aging_timer_val)
  3980. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  3981. vdev->wds_aging_timer_val = val;
  3982. break;
  3983. default:
  3984. break;
  3985. }
  3986. dp_tx_vdev_update_search_flags(vdev);
  3987. }
  3988. /**
  3989. * dp_peer_set_nawds: set nawds bit in peer
  3990. * @peer_handle: pointer to peer
  3991. * @value: enable/disable nawds
  3992. *
  3993. * return: void
  3994. */
  3995. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  3996. {
  3997. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3998. peer->nawds_enabled = value;
  3999. }
  4000. /*
  4001. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4002. * @vdev_handle: DP_VDEV handle
  4003. * @map_id:ID of map that needs to be updated
  4004. *
  4005. * Return: void
  4006. */
  4007. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4008. uint8_t map_id)
  4009. {
  4010. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4011. vdev->dscp_tid_map_id = map_id;
  4012. return;
  4013. }
  4014. /**
  4015. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4016. * @pdev: DP_PDEV handle
  4017. * @map_id: ID of map that needs to be updated
  4018. * @tos: index value in map
  4019. * @tid: tid value passed by the user
  4020. *
  4021. * Return: void
  4022. */
  4023. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4024. uint8_t map_id, uint8_t tos, uint8_t tid)
  4025. {
  4026. uint8_t dscp;
  4027. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4028. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4029. pdev->dscp_tid_map[map_id][dscp] = tid;
  4030. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4031. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4032. map_id, dscp);
  4033. return;
  4034. }
  4035. /**
  4036. * dp_fw_stats_process(): Process TxRX FW stats request
  4037. * @vdev_handle: DP VDEV handle
  4038. * @val: value passed by user
  4039. *
  4040. * return: int
  4041. */
  4042. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4043. {
  4044. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4045. struct dp_pdev *pdev = NULL;
  4046. if (!vdev) {
  4047. DP_TRACE(NONE, "VDEV not found");
  4048. return 1;
  4049. }
  4050. pdev = vdev->pdev;
  4051. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4052. }
  4053. /*
  4054. * dp_txrx_stats() - function to map to firmware and host stats
  4055. * @vdev: virtual handle
  4056. * @stats: type of statistics requested
  4057. *
  4058. * Return: integer
  4059. */
  4060. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4061. {
  4062. int host_stats;
  4063. int fw_stats;
  4064. if (stats >= CDP_TXRX_MAX_STATS)
  4065. return 0;
  4066. /*
  4067. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4068. * has to be updated if new FW HTT stats added
  4069. */
  4070. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4071. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4072. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4073. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4074. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4075. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4076. stats, fw_stats, host_stats);
  4077. if (fw_stats != TXRX_FW_STATS_INVALID)
  4078. return dp_fw_stats_process(vdev, fw_stats);
  4079. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4080. (host_stats <= TXRX_HOST_STATS_MAX))
  4081. return dp_print_host_stats(vdev, host_stats);
  4082. else
  4083. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4084. "Wrong Input for TxRx Stats");
  4085. return 0;
  4086. }
  4087. /*
  4088. * dp_print_napi_stats(): NAPI stats
  4089. * @soc - soc handle
  4090. */
  4091. static void dp_print_napi_stats(struct dp_soc *soc)
  4092. {
  4093. hif_print_napi_stats(soc->hif_handle);
  4094. }
  4095. /*
  4096. * dp_print_per_ring_stats(): Packet count per ring
  4097. * @soc - soc handle
  4098. */
  4099. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4100. {
  4101. uint8_t core, ring;
  4102. uint64_t total_packets;
  4103. DP_TRACE(FATAL, "Reo packets per ring:");
  4104. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4105. total_packets = 0;
  4106. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4107. for (core = 0; core < NR_CPUS; core++) {
  4108. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4109. core, soc->stats.rx.ring_packets[core][ring]);
  4110. total_packets += soc->stats.rx.ring_packets[core][ring];
  4111. }
  4112. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4113. ring, total_packets);
  4114. }
  4115. }
  4116. /*
  4117. * dp_txrx_path_stats() - Function to display dump stats
  4118. * @soc - soc handle
  4119. *
  4120. * return: none
  4121. */
  4122. static void dp_txrx_path_stats(struct dp_soc *soc)
  4123. {
  4124. uint8_t error_code;
  4125. uint8_t loop_pdev;
  4126. struct dp_pdev *pdev;
  4127. uint8_t i;
  4128. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4129. pdev = soc->pdev_list[loop_pdev];
  4130. dp_aggregate_pdev_stats(pdev);
  4131. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4132. "Tx path Statistics:");
  4133. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4134. pdev->stats.tx_i.rcvd.num,
  4135. pdev->stats.tx_i.rcvd.bytes);
  4136. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4137. pdev->stats.tx_i.processed.num,
  4138. pdev->stats.tx_i.processed.bytes);
  4139. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4140. pdev->stats.tx.tx_success.num,
  4141. pdev->stats.tx.tx_success.bytes);
  4142. DP_TRACE(FATAL, "Dropped in host:");
  4143. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4144. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4145. DP_TRACE(FATAL, "Descriptor not available: %u",
  4146. pdev->stats.tx_i.dropped.desc_na);
  4147. DP_TRACE(FATAL, "Ring full: %u",
  4148. pdev->stats.tx_i.dropped.ring_full);
  4149. DP_TRACE(FATAL, "Enqueue fail: %u",
  4150. pdev->stats.tx_i.dropped.enqueue_fail);
  4151. DP_TRACE(FATAL, "DMA Error: %u",
  4152. pdev->stats.tx_i.dropped.dma_error);
  4153. DP_TRACE(FATAL, "Dropped in hardware:");
  4154. DP_TRACE(FATAL, "total packets dropped: %u",
  4155. pdev->stats.tx.tx_failed);
  4156. DP_TRACE(FATAL, "mpdu age out: %u",
  4157. pdev->stats.tx.dropped.age_out);
  4158. DP_TRACE(FATAL, "firmware removed: %u",
  4159. pdev->stats.tx.dropped.fw_rem);
  4160. DP_TRACE(FATAL, "firmware removed tx: %u",
  4161. pdev->stats.tx.dropped.fw_rem_tx);
  4162. DP_TRACE(FATAL, "firmware removed notx %u",
  4163. pdev->stats.tx.dropped.fw_rem_notx);
  4164. DP_TRACE(FATAL, "peer_invalid: %u",
  4165. pdev->soc->stats.tx.tx_invalid_peer.num);
  4166. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4167. DP_TRACE(FATAL, "Single Packet: %u",
  4168. pdev->stats.tx_comp_histogram.pkts_1);
  4169. DP_TRACE(FATAL, "2-20 Packets: %u",
  4170. pdev->stats.tx_comp_histogram.pkts_2_20);
  4171. DP_TRACE(FATAL, "21-40 Packets: %u",
  4172. pdev->stats.tx_comp_histogram.pkts_21_40);
  4173. DP_TRACE(FATAL, "41-60 Packets: %u",
  4174. pdev->stats.tx_comp_histogram.pkts_41_60);
  4175. DP_TRACE(FATAL, "61-80 Packets: %u",
  4176. pdev->stats.tx_comp_histogram.pkts_61_80);
  4177. DP_TRACE(FATAL, "81-100 Packets: %u",
  4178. pdev->stats.tx_comp_histogram.pkts_81_100);
  4179. DP_TRACE(FATAL, "101-200 Packets: %u",
  4180. pdev->stats.tx_comp_histogram.pkts_101_200);
  4181. DP_TRACE(FATAL, " 201+ Packets: %u",
  4182. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4183. DP_TRACE(FATAL, "Rx path statistics");
  4184. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4185. pdev->stats.rx.to_stack.num,
  4186. pdev->stats.rx.to_stack.bytes);
  4187. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4188. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4189. i, pdev->stats.rx.rcvd_reo[i].num,
  4190. pdev->stats.rx.rcvd_reo[i].bytes);
  4191. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4192. pdev->stats.rx.intra_bss.pkts.num,
  4193. pdev->stats.rx.intra_bss.pkts.bytes);
  4194. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4195. pdev->stats.rx.raw.num,
  4196. pdev->stats.rx.raw.bytes);
  4197. DP_TRACE(FATAL, "dropped: error %u msdus",
  4198. pdev->stats.rx.err.mic_err);
  4199. DP_TRACE(FATAL, "peer invalid %u",
  4200. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4201. DP_TRACE(FATAL, "Reo Statistics");
  4202. DP_TRACE(FATAL, "rbm error: %u msdus",
  4203. pdev->soc->stats.rx.err.invalid_rbm);
  4204. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4205. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4206. DP_TRACE(FATAL, "Reo errors");
  4207. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4208. error_code++) {
  4209. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4210. error_code,
  4211. pdev->soc->stats.rx.err.reo_error[error_code]);
  4212. }
  4213. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4214. error_code++) {
  4215. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4216. error_code,
  4217. pdev->soc->stats.rx.err
  4218. .rxdma_error[error_code]);
  4219. }
  4220. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4221. DP_TRACE(FATAL, "Single Packet: %u",
  4222. pdev->stats.rx_ind_histogram.pkts_1);
  4223. DP_TRACE(FATAL, "2-20 Packets: %u",
  4224. pdev->stats.rx_ind_histogram.pkts_2_20);
  4225. DP_TRACE(FATAL, "21-40 Packets: %u",
  4226. pdev->stats.rx_ind_histogram.pkts_21_40);
  4227. DP_TRACE(FATAL, "41-60 Packets: %u",
  4228. pdev->stats.rx_ind_histogram.pkts_41_60);
  4229. DP_TRACE(FATAL, "61-80 Packets: %u",
  4230. pdev->stats.rx_ind_histogram.pkts_61_80);
  4231. DP_TRACE(FATAL, "81-100 Packets: %u",
  4232. pdev->stats.rx_ind_histogram.pkts_81_100);
  4233. DP_TRACE(FATAL, "101-200 Packets: %u",
  4234. pdev->stats.rx_ind_histogram.pkts_101_200);
  4235. DP_TRACE(FATAL, " 201+ Packets: %u",
  4236. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4237. }
  4238. }
  4239. /*
  4240. * dp_txrx_dump_stats() - Dump statistics
  4241. * @value - Statistics option
  4242. */
  4243. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4244. {
  4245. struct dp_soc *soc =
  4246. (struct dp_soc *)psoc;
  4247. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4248. if (!soc) {
  4249. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4250. "%s: soc is NULL", __func__);
  4251. return QDF_STATUS_E_INVAL;
  4252. }
  4253. switch (value) {
  4254. case CDP_TXRX_PATH_STATS:
  4255. dp_txrx_path_stats(soc);
  4256. break;
  4257. case CDP_RX_RING_STATS:
  4258. dp_print_per_ring_stats(soc);
  4259. break;
  4260. case CDP_TXRX_TSO_STATS:
  4261. /* TODO: NOT IMPLEMENTED */
  4262. break;
  4263. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4264. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4265. break;
  4266. case CDP_DP_NAPI_STATS:
  4267. dp_print_napi_stats(soc);
  4268. break;
  4269. case CDP_TXRX_DESC_STATS:
  4270. /* TODO: NOT IMPLEMENTED */
  4271. break;
  4272. default:
  4273. status = QDF_STATUS_E_INVAL;
  4274. break;
  4275. }
  4276. return status;
  4277. }
  4278. static struct cdp_wds_ops dp_ops_wds = {
  4279. .vdev_set_wds = dp_vdev_set_wds,
  4280. };
  4281. /*
  4282. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4283. * @soc - datapath soc handle
  4284. * @peer - datapath peer handle
  4285. *
  4286. * Delete the AST entries belonging to a peer
  4287. */
  4288. #ifdef FEATURE_WDS
  4289. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4290. struct dp_peer *peer)
  4291. {
  4292. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4293. qdf_spin_lock_bh(&soc->ast_lock);
  4294. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4295. if (ast_entry->next_hop) {
  4296. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4297. peer->vdev->pdev->osif_pdev,
  4298. ast_entry->mac_addr.raw);
  4299. }
  4300. dp_peer_del_ast(soc, ast_entry);
  4301. }
  4302. qdf_spin_unlock_bh(&soc->ast_lock);
  4303. }
  4304. #else
  4305. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4306. struct dp_peer *peer)
  4307. {
  4308. }
  4309. #endif
  4310. #ifdef CONFIG_WIN
  4311. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4312. {
  4313. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4314. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4315. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4316. dp_peer_delete_ast_entries(soc, peer);
  4317. }
  4318. #endif
  4319. static struct cdp_cmn_ops dp_ops_cmn = {
  4320. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4321. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4322. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4323. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4324. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4325. .txrx_peer_create = dp_peer_create_wifi3,
  4326. .txrx_peer_setup = dp_peer_setup_wifi3,
  4327. #ifdef CONFIG_WIN
  4328. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4329. #else
  4330. .txrx_peer_teardown = NULL,
  4331. #endif
  4332. .txrx_peer_delete = dp_peer_delete_wifi3,
  4333. .txrx_vdev_register = dp_vdev_register_wifi3,
  4334. .txrx_soc_detach = dp_soc_detach_wifi3,
  4335. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4336. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4337. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4338. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4339. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4340. .delba_process = dp_delba_process_wifi3,
  4341. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4342. .flush_cache_rx_queue = NULL,
  4343. /* TODO: get API's for dscp-tid need to be added*/
  4344. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4345. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4346. .txrx_stats = dp_txrx_stats,
  4347. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4348. .display_stats = dp_txrx_dump_stats,
  4349. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4350. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4351. #ifdef DP_INTR_POLL_BASED
  4352. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4353. #else
  4354. .txrx_intr_attach = dp_soc_interrupt_attach,
  4355. #endif
  4356. .txrx_intr_detach = dp_soc_interrupt_detach,
  4357. .set_pn_check = dp_set_pn_check_wifi3,
  4358. /* TODO: Add other functions */
  4359. };
  4360. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4361. .txrx_peer_authorize = dp_peer_authorize,
  4362. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4363. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4364. #ifdef MESH_MODE_SUPPORT
  4365. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4366. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4367. #endif
  4368. .txrx_set_vdev_param = dp_set_vdev_param,
  4369. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4370. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4371. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4372. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4373. .txrx_update_filter_neighbour_peers =
  4374. dp_update_filter_neighbour_peers,
  4375. .txrx_get_sec_type = dp_get_sec_type,
  4376. /* TODO: Add other functions */
  4377. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4378. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4379. };
  4380. static struct cdp_me_ops dp_ops_me = {
  4381. #ifdef ATH_SUPPORT_IQUE
  4382. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4383. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4384. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4385. #endif
  4386. };
  4387. static struct cdp_mon_ops dp_ops_mon = {
  4388. .txrx_monitor_set_filter_ucast_data = NULL,
  4389. .txrx_monitor_set_filter_mcast_data = NULL,
  4390. .txrx_monitor_set_filter_non_data = NULL,
  4391. .txrx_monitor_get_filter_ucast_data = NULL,
  4392. .txrx_monitor_get_filter_mcast_data = NULL,
  4393. .txrx_monitor_get_filter_non_data = NULL,
  4394. .txrx_reset_monitor_mode = NULL,
  4395. };
  4396. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4397. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4398. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4399. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4400. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4401. /* TODO */
  4402. };
  4403. static struct cdp_raw_ops dp_ops_raw = {
  4404. /* TODO */
  4405. };
  4406. #ifdef CONFIG_WIN
  4407. static struct cdp_pflow_ops dp_ops_pflow = {
  4408. /* TODO */
  4409. };
  4410. #endif /* CONFIG_WIN */
  4411. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4412. {
  4413. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4414. struct dp_soc *soc = pdev->soc;
  4415. if (soc->intr_mode == DP_INTR_POLL)
  4416. qdf_timer_stop(&soc->int_timer);
  4417. return QDF_STATUS_SUCCESS;
  4418. }
  4419. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4420. {
  4421. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4422. struct dp_soc *soc = pdev->soc;
  4423. if (soc->intr_mode == DP_INTR_POLL)
  4424. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4425. return QDF_STATUS_SUCCESS;
  4426. }
  4427. #ifndef CONFIG_WIN
  4428. static struct cdp_misc_ops dp_ops_misc = {
  4429. .get_opmode = dp_get_opmode,
  4430. #ifdef FEATURE_RUNTIME_PM
  4431. .runtime_suspend = dp_bus_suspend,
  4432. .runtime_resume = dp_bus_resume,
  4433. #endif
  4434. };
  4435. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4436. /* WIFI 3.0 DP implement as required. */
  4437. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4438. .register_pause_cb = dp_txrx_register_pause_cb,
  4439. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4440. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4441. };
  4442. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4443. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4444. };
  4445. #ifdef IPA_OFFLOAD
  4446. static struct cdp_ipa_ops dp_ops_ipa = {
  4447. .ipa_get_resource = dp_ipa_get_resource,
  4448. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4449. .ipa_op_response = dp_ipa_op_response,
  4450. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4451. .ipa_get_stat = dp_ipa_get_stat,
  4452. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4453. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4454. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4455. .ipa_setup = dp_ipa_setup,
  4456. .ipa_cleanup = dp_ipa_cleanup,
  4457. .ipa_setup_iface = dp_ipa_setup_iface,
  4458. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4459. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4460. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4461. .ipa_set_perf_level = dp_ipa_set_perf_level
  4462. };
  4463. #endif
  4464. static struct cdp_bus_ops dp_ops_bus = {
  4465. .bus_suspend = dp_bus_suspend,
  4466. .bus_resume = dp_bus_resume
  4467. };
  4468. static struct cdp_ocb_ops dp_ops_ocb = {
  4469. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4470. };
  4471. static struct cdp_throttle_ops dp_ops_throttle = {
  4472. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4473. };
  4474. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4475. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4476. };
  4477. static struct cdp_cfg_ops dp_ops_cfg = {
  4478. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4479. };
  4480. static struct cdp_peer_ops dp_ops_peer = {
  4481. .register_peer = dp_register_peer,
  4482. .clear_peer = dp_clear_peer,
  4483. .find_peer_by_addr = dp_find_peer_by_addr,
  4484. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4485. .local_peer_id = dp_local_peer_id,
  4486. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4487. .peer_state_update = dp_peer_state_update,
  4488. .get_vdevid = dp_get_vdevid,
  4489. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4490. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4491. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4492. .get_peer_state = dp_get_peer_state,
  4493. .last_assoc_received = dp_get_last_assoc_received,
  4494. .last_disassoc_received = dp_get_last_disassoc_received,
  4495. .last_deauth_received = dp_get_last_deauth_received,
  4496. };
  4497. #endif
  4498. static struct cdp_ops dp_txrx_ops = {
  4499. .cmn_drv_ops = &dp_ops_cmn,
  4500. .ctrl_ops = &dp_ops_ctrl,
  4501. .me_ops = &dp_ops_me,
  4502. .mon_ops = &dp_ops_mon,
  4503. .host_stats_ops = &dp_ops_host_stats,
  4504. .wds_ops = &dp_ops_wds,
  4505. .raw_ops = &dp_ops_raw,
  4506. #ifdef CONFIG_WIN
  4507. .pflow_ops = &dp_ops_pflow,
  4508. #endif /* CONFIG_WIN */
  4509. #ifndef CONFIG_WIN
  4510. .misc_ops = &dp_ops_misc,
  4511. .cfg_ops = &dp_ops_cfg,
  4512. .flowctl_ops = &dp_ops_flowctl,
  4513. .l_flowctl_ops = &dp_ops_l_flowctl,
  4514. #ifdef IPA_OFFLOAD
  4515. .ipa_ops = &dp_ops_ipa,
  4516. #endif
  4517. .bus_ops = &dp_ops_bus,
  4518. .ocb_ops = &dp_ops_ocb,
  4519. .peer_ops = &dp_ops_peer,
  4520. .throttle_ops = &dp_ops_throttle,
  4521. .mob_stats_ops = &dp_ops_mob_stats,
  4522. #endif
  4523. };
  4524. /*
  4525. * dp_soc_set_txrx_ring_map()
  4526. * @dp_soc: DP handler for soc
  4527. *
  4528. * Return: Void
  4529. */
  4530. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4531. {
  4532. uint32_t i;
  4533. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4534. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4535. }
  4536. }
  4537. /*
  4538. * dp_soc_attach_wifi3() - Attach txrx SOC
  4539. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4540. * @htc_handle: Opaque HTC handle
  4541. * @hif_handle: Opaque HIF handle
  4542. * @qdf_osdev: QDF device
  4543. *
  4544. * Return: DP SOC handle on success, NULL on failure
  4545. */
  4546. /*
  4547. * Local prototype added to temporarily address warning caused by
  4548. * -Wmissing-prototypes. A more correct solution, namely to expose
  4549. * a prototype in an appropriate header file, will come later.
  4550. */
  4551. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4552. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4553. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4554. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4555. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4556. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4557. {
  4558. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4559. if (!soc) {
  4560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4561. FL("DP SOC memory allocation failed"));
  4562. goto fail0;
  4563. }
  4564. soc->cdp_soc.ops = &dp_txrx_ops;
  4565. soc->cdp_soc.ol_ops = ol_ops;
  4566. soc->osif_soc = osif_soc;
  4567. soc->osdev = qdf_osdev;
  4568. soc->hif_handle = hif_handle;
  4569. soc->psoc = psoc;
  4570. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4571. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4572. soc->hal_soc, qdf_osdev);
  4573. if (!soc->htt_handle) {
  4574. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4575. FL("HTT attach failed"));
  4576. goto fail1;
  4577. }
  4578. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4579. if (!soc->wlan_cfg_ctx) {
  4580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4581. FL("wlan_cfg_soc_attach failed"));
  4582. goto fail2;
  4583. }
  4584. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4585. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4586. CDP_CFG_MAX_PEER_ID);
  4587. if (ret != -EINVAL) {
  4588. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4589. }
  4590. }
  4591. qdf_spinlock_create(&soc->peer_ref_mutex);
  4592. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4593. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4594. /* fill the tx/rx cpu ring map*/
  4595. dp_soc_set_txrx_ring_map(soc);
  4596. qdf_spinlock_create(&soc->htt_stats.lock);
  4597. /* initialize work queue for stats processing */
  4598. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4599. return (void *)soc;
  4600. fail2:
  4601. htt_soc_detach(soc->htt_handle);
  4602. fail1:
  4603. qdf_mem_free(soc);
  4604. fail0:
  4605. return NULL;
  4606. }
  4607. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4608. /*
  4609. * dp_set_pktlog_wifi3() - attach txrx vdev
  4610. * @pdev: Datapath PDEV handle
  4611. * @event: which event's notifications are being subscribed to
  4612. * @enable: WDI event subscribe or not. (True or False)
  4613. *
  4614. * Return: Success, NULL on failure
  4615. */
  4616. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4617. bool enable)
  4618. {
  4619. struct dp_soc *soc = pdev->soc;
  4620. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4621. if (enable) {
  4622. switch (event) {
  4623. case WDI_EVENT_RX_DESC:
  4624. if (pdev->monitor_vdev) {
  4625. /* Nothing needs to be done if monitor mode is
  4626. * enabled
  4627. */
  4628. return 0;
  4629. }
  4630. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4631. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4632. htt_tlv_filter.mpdu_start = 1;
  4633. htt_tlv_filter.msdu_start = 1;
  4634. htt_tlv_filter.msdu_end = 1;
  4635. htt_tlv_filter.mpdu_end = 1;
  4636. htt_tlv_filter.packet_header = 1;
  4637. htt_tlv_filter.attention = 1;
  4638. htt_tlv_filter.ppdu_start = 1;
  4639. htt_tlv_filter.ppdu_end = 1;
  4640. htt_tlv_filter.ppdu_end_user_stats = 1;
  4641. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4642. htt_tlv_filter.ppdu_end_status_done = 1;
  4643. htt_tlv_filter.enable_fp = 1;
  4644. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4645. pdev->pdev_id,
  4646. pdev->rxdma_mon_status_ring.hal_srng,
  4647. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4648. &htt_tlv_filter);
  4649. }
  4650. break;
  4651. case WDI_EVENT_LITE_RX:
  4652. if (pdev->monitor_vdev) {
  4653. /* Nothing needs to be done if monitor mode is
  4654. * enabled
  4655. */
  4656. return 0;
  4657. }
  4658. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4659. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4660. htt_tlv_filter.ppdu_start = 1;
  4661. htt_tlv_filter.ppdu_end = 1;
  4662. htt_tlv_filter.ppdu_end_user_stats = 1;
  4663. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4664. htt_tlv_filter.ppdu_end_status_done = 1;
  4665. htt_tlv_filter.enable_fp = 1;
  4666. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4667. pdev->pdev_id,
  4668. pdev->rxdma_mon_status_ring.hal_srng,
  4669. RXDMA_MONITOR_STATUS,
  4670. RX_BUFFER_SIZE_PKTLOG_LITE,
  4671. &htt_tlv_filter);
  4672. }
  4673. break;
  4674. case WDI_EVENT_LITE_T2H:
  4675. if (pdev->monitor_vdev) {
  4676. /* Nothing needs to be done if monitor mode is
  4677. * enabled
  4678. */
  4679. return 0;
  4680. }
  4681. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4682. * passing value 0xffff. Once these macros will define in htt
  4683. * header file will use proper macros
  4684. */
  4685. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4686. break;
  4687. default:
  4688. /* Nothing needs to be done for other pktlog types */
  4689. break;
  4690. }
  4691. } else {
  4692. switch (event) {
  4693. case WDI_EVENT_RX_DESC:
  4694. case WDI_EVENT_LITE_RX:
  4695. if (pdev->monitor_vdev) {
  4696. /* Nothing needs to be done if monitor mode is
  4697. * enabled
  4698. */
  4699. return 0;
  4700. }
  4701. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4702. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4703. /* htt_tlv_filter is initialized to 0 */
  4704. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4705. pdev->pdev_id,
  4706. pdev->rxdma_mon_status_ring.hal_srng,
  4707. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4708. &htt_tlv_filter);
  4709. }
  4710. break;
  4711. case WDI_EVENT_LITE_T2H:
  4712. if (pdev->monitor_vdev) {
  4713. /* Nothing needs to be done if monitor mode is
  4714. * enabled
  4715. */
  4716. return 0;
  4717. }
  4718. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4719. * passing value 0. Once these macros will define in htt
  4720. * header file will use proper macros
  4721. */
  4722. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4723. break;
  4724. default:
  4725. /* Nothing needs to be done for other pktlog types */
  4726. break;
  4727. }
  4728. }
  4729. return 0;
  4730. }
  4731. #endif