msm_drv.h 44 KB

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  1. /*
  2. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #ifndef __MSM_DRV_H__
  19. #define __MSM_DRV_H__
  20. #include <linux/kernel.h>
  21. #include <linux/clk.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/module.h>
  24. #include <linux/component.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pm.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/slab.h>
  29. #include <linux/list.h>
  30. #include <linux/iommu.h>
  31. #include <linux/types.h>
  32. #include <linux/of_graph.h>
  33. #include <linux/of_device.h>
  34. #include <linux/sde_io_util.h>
  35. #include <linux/sde_vm_event.h>
  36. #include <linux/sizes.h>
  37. #include <linux/kthread.h>
  38. #include <drm/drm_atomic.h>
  39. #include <drm/drm_atomic_helper.h>
  40. #include <drm/drm_plane_helper.h>
  41. #include <drm/drm_fb_helper.h>
  42. #include <drm/msm_drm.h>
  43. #include <drm/sde_drm.h>
  44. #include <drm/drm_file.h>
  45. #include <drm/drm_gem.h>
  46. #include <drm/drm_dsc.h>
  47. #include <drm/drm_bridge.h>
  48. #include "sde_power_handle.h"
  49. #define GET_MAJOR_REV(rev) ((rev) >> 28)
  50. #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF)
  51. #define GET_STEP_REV(rev) ((rev) & 0xFFFF)
  52. struct msm_kms;
  53. struct msm_gpu;
  54. struct msm_mmu;
  55. struct msm_mdss;
  56. struct msm_rd_state;
  57. struct msm_perf_state;
  58. struct msm_gem_submit;
  59. struct msm_fence_context;
  60. struct msm_fence_cb;
  61. struct msm_gem_address_space;
  62. struct msm_gem_vma;
  63. #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */
  64. #define MAX_CRTCS 16
  65. #define MAX_PLANES 20
  66. #define MAX_ENCODERS 16
  67. #define MAX_BRIDGES 16
  68. #define MAX_CONNECTORS 16
  69. #define MSM_RGB 0x0
  70. #define MSM_YUV 0x1
  71. #define MSM_CHROMA_444 0x0
  72. #define MSM_CHROMA_422 0x1
  73. #define MSM_CHROMA_420 0x2
  74. #define TEARDOWN_DEADLOCK_RETRY_MAX 5
  75. struct msm_file_private {
  76. rwlock_t queuelock;
  77. struct list_head submitqueues;
  78. int queueid;
  79. /* update the refcount when user driver calls power_ctrl IOCTL */
  80. unsigned short enable_refcnt;
  81. /* protects enable_refcnt */
  82. struct mutex power_lock;
  83. };
  84. enum msm_mdp_plane_property {
  85. /* blob properties, always put these first */
  86. PLANE_PROP_CSC_V1,
  87. PLANE_PROP_CSC_DMA_V1,
  88. PLANE_PROP_INFO,
  89. PLANE_PROP_SCALER_LUT_ED,
  90. PLANE_PROP_SCALER_LUT_CIR,
  91. PLANE_PROP_SCALER_LUT_SEP,
  92. PLANE_PROP_SKIN_COLOR,
  93. PLANE_PROP_SKY_COLOR,
  94. PLANE_PROP_FOLIAGE_COLOR,
  95. PLANE_PROP_VIG_GAMUT,
  96. PLANE_PROP_VIG_IGC,
  97. PLANE_PROP_DMA_IGC,
  98. PLANE_PROP_DMA_GC,
  99. PLANE_PROP_FP16_GC,
  100. PLANE_PROP_FP16_CSC,
  101. /* # of blob properties */
  102. PLANE_PROP_BLOBCOUNT,
  103. /* range properties */
  104. PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
  105. PLANE_PROP_ALPHA,
  106. PLANE_PROP_COLOR_FILL,
  107. PLANE_PROP_H_DECIMATE,
  108. PLANE_PROP_V_DECIMATE,
  109. PLANE_PROP_INPUT_FENCE,
  110. PLANE_PROP_HUE_ADJUST,
  111. PLANE_PROP_SATURATION_ADJUST,
  112. PLANE_PROP_VALUE_ADJUST,
  113. PLANE_PROP_CONTRAST_ADJUST,
  114. PLANE_PROP_EXCL_RECT_V1,
  115. PLANE_PROP_PREFILL_SIZE,
  116. PLANE_PROP_PREFILL_TIME,
  117. PLANE_PROP_SCALER_V1,
  118. PLANE_PROP_SCALER_V2,
  119. PLANE_PROP_INVERSE_PMA,
  120. PLANE_PROP_FP16_IGC,
  121. PLANE_PROP_FP16_UNMULT,
  122. /* enum/bitmask properties */
  123. PLANE_PROP_BLEND_OP,
  124. PLANE_PROP_SRC_CONFIG,
  125. PLANE_PROP_FB_TRANSLATION_MODE,
  126. PLANE_PROP_MULTIRECT_MODE,
  127. /* total # of properties */
  128. PLANE_PROP_COUNT
  129. };
  130. enum msm_mdp_crtc_property {
  131. CRTC_PROP_INFO,
  132. CRTC_PROP_DEST_SCALER_LUT_ED,
  133. CRTC_PROP_DEST_SCALER_LUT_CIR,
  134. CRTC_PROP_DEST_SCALER_LUT_SEP,
  135. CRTC_PROP_DSPP_INFO,
  136. /* # of blob properties */
  137. CRTC_PROP_BLOBCOUNT,
  138. /* range properties */
  139. CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
  140. CRTC_PROP_OUTPUT_FENCE,
  141. CRTC_PROP_OUTPUT_FENCE_OFFSET,
  142. CRTC_PROP_DIM_LAYER_V1,
  143. CRTC_PROP_CORE_CLK,
  144. CRTC_PROP_CORE_AB,
  145. CRTC_PROP_CORE_IB,
  146. CRTC_PROP_LLCC_AB,
  147. CRTC_PROP_LLCC_IB,
  148. CRTC_PROP_DRAM_AB,
  149. CRTC_PROP_DRAM_IB,
  150. CRTC_PROP_ROT_PREFILL_BW,
  151. CRTC_PROP_ROT_CLK,
  152. CRTC_PROP_ROI_V1,
  153. CRTC_PROP_SECURITY_LEVEL,
  154. CRTC_PROP_IDLE_TIMEOUT,
  155. CRTC_PROP_DEST_SCALER,
  156. CRTC_PROP_CAPTURE_OUTPUT,
  157. CRTC_PROP_IDLE_PC_STATE,
  158. CRTC_PROP_CACHE_STATE,
  159. CRTC_PROP_VM_REQ_STATE,
  160. CRTC_PROP_NOISE_LAYER_V1,
  161. /* total # of properties */
  162. CRTC_PROP_COUNT
  163. };
  164. enum msm_mdp_conn_property {
  165. /* blob properties, always put these first */
  166. CONNECTOR_PROP_SDE_INFO,
  167. CONNECTOR_PROP_MODE_INFO,
  168. CONNECTOR_PROP_HDR_INFO,
  169. CONNECTOR_PROP_EXT_HDR_INFO,
  170. CONNECTOR_PROP_PP_DITHER,
  171. CONNECTOR_PROP_HDR_METADATA,
  172. CONNECTOR_PROP_DEMURA_PANEL_ID,
  173. /* # of blob properties */
  174. CONNECTOR_PROP_BLOBCOUNT,
  175. /* range properties */
  176. CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
  177. CONNECTOR_PROP_RETIRE_FENCE,
  178. CONN_PROP_RETIRE_FENCE_OFFSET,
  179. CONNECTOR_PROP_DST_X,
  180. CONNECTOR_PROP_DST_Y,
  181. CONNECTOR_PROP_DST_W,
  182. CONNECTOR_PROP_DST_H,
  183. CONNECTOR_PROP_ROI_V1,
  184. CONNECTOR_PROP_BL_SCALE,
  185. CONNECTOR_PROP_SV_BL_SCALE,
  186. CONNECTOR_PROP_SUPPORTED_COLORSPACES,
  187. CONNECTOR_PROP_DYN_BIT_CLK,
  188. /* enum/bitmask properties */
  189. CONNECTOR_PROP_TOPOLOGY_NAME,
  190. CONNECTOR_PROP_TOPOLOGY_CONTROL,
  191. CONNECTOR_PROP_AUTOREFRESH,
  192. CONNECTOR_PROP_LP,
  193. CONNECTOR_PROP_FB_TRANSLATION_MODE,
  194. CONNECTOR_PROP_QSYNC_MODE,
  195. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE,
  196. CONNECTOR_PROP_SET_PANEL_MODE,
  197. /* total # of properties */
  198. CONNECTOR_PROP_COUNT
  199. };
  200. #define MSM_GPU_MAX_RINGS 4
  201. #define MAX_H_TILES_PER_DISPLAY 2
  202. /**
  203. * enum msm_display_compression_type - compression method used for pixel stream
  204. * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed
  205. * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used
  206. * @MSM_DISPLAY_COMPRESSION_VDC: VDC compresison is used
  207. */
  208. enum msm_display_compression_type {
  209. MSM_DISPLAY_COMPRESSION_NONE,
  210. MSM_DISPLAY_COMPRESSION_DSC,
  211. MSM_DISPLAY_COMPRESSION_VDC
  212. };
  213. #define MSM_DISPLAY_COMPRESSION_RATIO_NONE 1
  214. #define MSM_DISPLAY_COMPRESSION_RATIO_MAX 5
  215. /**
  216. * enum msm_display_spr_pack_type - sub pixel rendering pack patterns supported
  217. * @MSM_DISPLAY_SPR_TYPE_NONE: Bypass, no special packing
  218. * @MSM_DISPLAY_SPR_TYPE_PENTILE: pentile pack pattern
  219. * @MSM_DISPLAY_SPR_TYPE_RGBW: RGBW pack pattern
  220. * @MSM_DISPLAY_SPR_TYPE_YYGM: YYGM pack pattern
  221. * @MSM_DISPLAY_SPR_TYPE_YYGW: YYGW pack patterm
  222. * @MSM_DISPLAY_SPR_TYPE_MAX: max and invalid
  223. */
  224. enum msm_display_spr_pack_type {
  225. MSM_DISPLAY_SPR_TYPE_NONE,
  226. MSM_DISPLAY_SPR_TYPE_PENTILE,
  227. MSM_DISPLAY_SPR_TYPE_RGBW,
  228. MSM_DISPLAY_SPR_TYPE_YYGM,
  229. MSM_DISPLAY_SPR_TYPE_YYGW,
  230. MSM_DISPLAY_SPR_TYPE_MAX
  231. };
  232. static const char *msm_spr_pack_type_str[MSM_DISPLAY_SPR_TYPE_MAX] = {
  233. [MSM_DISPLAY_SPR_TYPE_NONE] = "",
  234. [MSM_DISPLAY_SPR_TYPE_PENTILE] = "pentile",
  235. [MSM_DISPLAY_SPR_TYPE_RGBW] = "rgbw",
  236. [MSM_DISPLAY_SPR_TYPE_YYGM] = "yygm",
  237. [MSM_DISPLAY_SPR_TYPE_YYGW] = "yygw",
  238. };
  239. /**
  240. * enum msm_display_caps - features/capabilities supported by displays
  241. * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
  242. * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
  243. * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
  244. * @MSM_DISPLAY_CAP_EDID: EDID supported
  245. * @MSM_DISPLAY_ESD_ENABLED: ESD feature enabled
  246. * @MSM_DISPLAY_CAP_MST_MODE: Display with MST support
  247. * @MSM_DISPLAY_SPLIT_LINK: Split Link enabled
  248. */
  249. enum msm_display_caps {
  250. MSM_DISPLAY_CAP_VID_MODE = BIT(0),
  251. MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
  252. MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
  253. MSM_DISPLAY_CAP_EDID = BIT(3),
  254. MSM_DISPLAY_ESD_ENABLED = BIT(4),
  255. MSM_DISPLAY_CAP_MST_MODE = BIT(5),
  256. MSM_DISPLAY_SPLIT_LINK = BIT(6),
  257. };
  258. /**
  259. * enum panel_mode - panel operation mode
  260. * @MSM_DISPLAY_VIDEO_MODE: video mode panel
  261. * @MSM_DISPLAY_CMD_MODE: Command mode panel
  262. * @MODE_MAX:
  263. */
  264. enum panel_op_mode {
  265. MSM_DISPLAY_VIDEO_MODE = BIT(0),
  266. MSM_DISPLAY_CMD_MODE = BIT(1),
  267. MSM_DISPLAY_MODE_MAX = BIT(2)
  268. };
  269. /**
  270. * struct msm_display_mode - wrapper for drm_display_mode
  271. * @base: drm_display_mode attached to this msm_mode
  272. * @private_flags: integer holding private driver mode flags
  273. * @private: pointer to private driver information
  274. */
  275. struct msm_display_mode {
  276. struct drm_display_mode *base;
  277. u32 private_flags;
  278. u32 *private;
  279. };
  280. /**
  281. * struct msm_ratio - integer ratio
  282. * @numer: numerator
  283. * @denom: denominator
  284. */
  285. struct msm_ratio {
  286. uint32_t numer;
  287. uint32_t denom;
  288. };
  289. /**
  290. * enum msm_event_wait - type of HW events to wait for
  291. * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  292. * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
  293. * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  294. * @MSM_ENC_ACTIVE_REGION - wait for the TG to be in active pixel region
  295. */
  296. enum msm_event_wait {
  297. MSM_ENC_COMMIT_DONE = 0,
  298. MSM_ENC_TX_COMPLETE,
  299. MSM_ENC_VBLANK,
  300. MSM_ENC_ACTIVE_REGION,
  301. };
  302. /**
  303. * struct msm_roi_alignment - region of interest alignment restrictions
  304. * @xstart_pix_align: left x offset alignment restriction
  305. * @width_pix_align: width alignment restriction
  306. * @ystart_pix_align: top y offset alignment restriction
  307. * @height_pix_align: height alignment restriction
  308. * @min_width: minimum width restriction
  309. * @min_height: minimum height restriction
  310. */
  311. struct msm_roi_alignment {
  312. uint32_t xstart_pix_align;
  313. uint32_t width_pix_align;
  314. uint32_t ystart_pix_align;
  315. uint32_t height_pix_align;
  316. uint32_t min_width;
  317. uint32_t min_height;
  318. };
  319. /**
  320. * struct msm_roi_caps - display's region of interest capabilities
  321. * @enabled: true if some region of interest is supported
  322. * @merge_rois: merge rois before sending to display
  323. * @num_roi: maximum number of rois supported
  324. * @align: roi alignment restrictions
  325. */
  326. struct msm_roi_caps {
  327. bool enabled;
  328. bool merge_rois;
  329. uint32_t num_roi;
  330. struct msm_roi_alignment align;
  331. };
  332. /**
  333. * struct msm_display_dsc_info - defines dsc configuration
  334. * @config DSC encoder configuration
  335. * @scr_rev: DSC revision.
  336. * @initial_lines: Number of initial lines stored in encoder.
  337. * @pkt_per_line: Number of packets per line.
  338. * @bytes_in_slice: Number of bytes in slice.
  339. * @eol_byte_num: Valid bytes at the end of line.
  340. * @bytes_per_pkt Number of bytes in DSI packet
  341. * @pclk_per_line: Compressed width.
  342. * @slice_last_group_size: Size of last group in pixels.
  343. * @slice_per_pkt: Number of slices per packet.
  344. * @source_color_space: Source color space of DSC encoder
  345. * @chroma_format: Chroma_format of DSC encoder.
  346. * @det_thresh_flatness: Flatness threshold.
  347. * @extra_width: Extra width required in timing calculations.
  348. * @pps_delay_ms: Post PPS command delay in milliseconds.
  349. * @dsc_4hsmerge_en: Using DSC 4HS merge topology
  350. * @dsc_4hsmerge_padding 4HS merge DSC pair padding value in bytes
  351. * @dsc_4hsmerge_alignment 4HS merge DSC alignment value in bytes
  352. * @half_panel_pu True for single and dual dsc encoders if partial
  353. * update sets the roi width to half of mode width
  354. * False in all other cases
  355. */
  356. struct msm_display_dsc_info {
  357. struct drm_dsc_config config;
  358. u8 scr_rev;
  359. int initial_lines;
  360. int pkt_per_line;
  361. int bytes_in_slice;
  362. int bytes_per_pkt;
  363. int eol_byte_num;
  364. int pclk_per_line;
  365. int slice_last_group_size;
  366. int slice_per_pkt;
  367. int source_color_space;
  368. int chroma_format;
  369. int det_thresh_flatness;
  370. u32 extra_width;
  371. u32 pps_delay_ms;
  372. bool dsc_4hsmerge_en;
  373. u32 dsc_4hsmerge_padding;
  374. u32 dsc_4hsmerge_alignment;
  375. bool half_panel_pu;
  376. };
  377. /**
  378. * struct msm_display_vdc_info - defines vdc configuration
  379. * @version_major: major version number of VDC encoder.
  380. * @version_minor: minor version number of VDC encoder.
  381. * @source_color_space: source color space of VDC encoder
  382. * @chroma_format: chroma_format of VDC encoder.
  383. * @mppf_bpc_r_y: MPPF bpc for R/Y color component
  384. * @mppf_bpc_g_cb: MPPF bpc for G/Cb color component
  385. * @mppf_bpc_b_cr: MPPF bpc for B/Cr color component
  386. * @mppf_bpc_y: MPPF bpc for Y color component
  387. * @mppf_bpc_co: MPPF bpc for Co color component
  388. * @mppf_bpc_cg: MPPF bpc for Cg color component
  389. * @flatqp_vf_fbls: flatness qp very flat FBLs
  390. * @flatqp_vf_nbls: flatness qp very flat NBLs
  391. * @flatqp_sw_fbls: flatness qp somewhat flat FBLs
  392. * @flatqp_sw_nbls: flatness qp somewhat flat NBLs
  393. * @chroma_samples: number of chroma samples
  394. * @split_panel_enable: indicates whether split panel is enabled
  395. * @traffic_mode: indicates burst/non-burst mode
  396. * @flatness_qp_lut: LUT used to determine flatness QP
  397. * @max_qp_lut: LUT used to determine maximum QP
  398. * @tar_del_lut: LUT used to calculate RC target rate
  399. * @lbda_brate_lut: lambda bitrate LUT for encoder
  400. * @lbda_bf_lut: lambda buffer fullness lut for encoder
  401. * @lbda_brate_lut_interp: interpolated lambda bitrate LUT
  402. * @lbda_bf_lut_interp: interpolated lambda buffer fullness lut
  403. * @num_of_active_ss: number of active soft slices
  404. * @bits_per_component: number of bits per component.
  405. * @max_pixels_per_line: maximum pixels per line
  406. * @max_pixels_per_hs_line: maximum pixels per hs line
  407. * @max_lines_per_frame: maximum lines per frame
  408. * @max_lines_per_slice: maximum lines per slice
  409. * @chunk_size: chunk size for encoder
  410. * @chunk_size_bits: number of bits in the chunk
  411. * @avg_block_bits: average block bits
  412. * @per_chunk_pad_bits: number of bits per chunk pad
  413. * @tot_pad_bits: total padding bits
  414. * @rc_stuffing_bits: rate control stuffing bits
  415. * @chunk_adj_bits: number of adjacent bits in the chunk
  416. * @rc_buf_init_size_temp: temporary rate control buffer init size
  417. * @init_tx_delay_temp: initial tx delay
  418. * @rc_buffer_init_size: rate control buffer init size
  419. * @rc_init_tx_delay: rate control buffer init tx delay
  420. * @rc_init_tx_delay_px_times: rate control buffer init tx
  421. * delay times pixels
  422. * @rc_buffer_max_size: max size of rate control buffer
  423. * @rc_tar_rate_scale_temp_a: rate control target rate scale parameter
  424. * @rc_tar_rate_scale_temp_b: rate control target rate scale parameter
  425. * @rc_tar_rate_scale: rate control target rate scale
  426. * @block_max_bits: max bits in the block
  427. * @rc_lambda_bitrate_scale: rate control lambda bitrate scale
  428. * @rc_buffer_fullness_scale: rate control lambda fullness scale
  429. * @rc_fullness_offset_thresh: rate control lambda fullness threshold
  430. * @ramp_blocks: number of ramp blocks
  431. * @bits_per_pixel: number of bits per pixel.
  432. * @num_extra_mux_bits_init: initial value of number of extra mux bits
  433. * @extra_crop_bits: number of extra crop bits
  434. * @num_extra_mux_bits: value of number of extra mux bits
  435. * @mppf_bits_comp_0: mppf bits in color component 0
  436. * @mppf_bits_comp_1: mppf bits in color component 1
  437. * @mppf_bits_comp_2: mppf bits in color component 2
  438. * @min_block_bits: min number of block bits
  439. * @slice_height: slice height configuration of encoder.
  440. * @slice_width: slice width configuration of encoder.
  441. * @frame_width: frame width configuration of encoder
  442. * @frame_height: frame height configuration of encoder
  443. * @bytes_in_slice: Number of bytes in slice.
  444. * @bytes_per_pkt: Number of bytes in packet.
  445. * @eol_byte_num: Valid bytes at the end of line.
  446. * @pclk_per_line: Compressed width.
  447. * @slice_per_pkt: Number of slices per packet.
  448. * @pkt_per_line: Number of packets per line.
  449. * @min_ssm_delay: Min Sub-stream multiplexing delay
  450. * @max_ssm_delay: Max Sub-stream multiplexing delay
  451. * @input_ssm_out_latency: input Sub-stream multiplexing output latency
  452. * @input_ssm_out_latency_min: min input Sub-stream multiplexing output latency
  453. * @obuf_latency: Output buffer latency
  454. * @base_hs_latency: base hard-slice latency
  455. * @base_hs_latency_min: base hard-slice min latency
  456. * @base_hs_latency_pixels: base hard-slice latency pixels
  457. * @base_hs_latency_pixels_min: base hard-slice latency pixels(min)
  458. * @base_initial_lines: base initial lines
  459. * @base_top_up: base top up
  460. * @output_rate: output rate
  461. * @output_rate_ratio_100: output rate times 100
  462. * @burst_accum_pixels: burst accumulated pixels
  463. * @ss_initial_lines: soft-slice initial lines
  464. * @burst_initial_lines: burst mode initial lines
  465. * @initial_lines: initial lines
  466. * @obuf_base: output buffer base
  467. * @obuf_extra_ss0: output buffer extra ss0
  468. * @obuf_extra_ss1: output buffer extra ss1
  469. * @obuf_extra_burst: output buffer extra burst
  470. * @obuf_ss0: output buffer ss0
  471. * @obuf_ss1: output buffer ss1
  472. * @obuf_margin_words: output buffer margin words
  473. * @ob0_max_addr: output buffer 0 max address
  474. * @ob1_max_addr: output buffer 1 max address
  475. * @slice_width_orig: original slice width
  476. * @r2b0_max_addr: r2b0 max addr
  477. * @r2b1_max_addr: r1b1 max addr
  478. * @slice_num_px: number of pixels per slice
  479. * @rc_target_rate_threshold: rate control target rate threshold
  480. * @rc_fullness_offset_slope: rate control fullness offset slop
  481. * @pps_delay_ms: Post PPS command delay in milliseconds.
  482. * @version_release: release version of VDC encoder.
  483. * @slice_num_bits: number of bits per slice
  484. * @ramp_bits: number of ramp bits
  485. */
  486. struct msm_display_vdc_info {
  487. u8 version_major;
  488. u8 version_minor;
  489. u8 source_color_space;
  490. u8 chroma_format;
  491. u8 mppf_bpc_r_y;
  492. u8 mppf_bpc_g_cb;
  493. u8 mppf_bpc_b_cr;
  494. u8 mppf_bpc_y;
  495. u8 mppf_bpc_co;
  496. u8 mppf_bpc_cg;
  497. u8 flatqp_vf_fbls;
  498. u8 flatqp_vf_nbls;
  499. u8 flatqp_sw_fbls;
  500. u8 flatqp_sw_nbls;
  501. u8 chroma_samples;
  502. u8 split_panel_enable;
  503. u8 traffic_mode;
  504. u16 flatness_qp_lut[8];
  505. u16 max_qp_lut[8];
  506. u16 tar_del_lut[16];
  507. u16 lbda_brate_lut[16];
  508. u16 lbda_bf_lut[16];
  509. u16 lbda_brate_lut_interp[64];
  510. u16 lbda_bf_lut_interp[64];
  511. u8 num_of_active_ss;
  512. u8 bits_per_component;
  513. u16 max_pixels_per_line;
  514. u16 max_pixels_per_hs_line;
  515. u16 max_lines_per_frame;
  516. u16 max_lines_per_slice;
  517. u16 chunk_size;
  518. u16 chunk_size_bits;
  519. u16 avg_block_bits;
  520. u16 per_chunk_pad_bits;
  521. u16 tot_pad_bits;
  522. u16 rc_stuffing_bits;
  523. u16 chunk_adj_bits;
  524. u16 rc_buf_init_size_temp;
  525. u16 init_tx_delay_temp;
  526. u16 rc_buffer_init_size;
  527. u16 rc_init_tx_delay;
  528. u16 rc_init_tx_delay_px_times;
  529. u16 rc_buffer_max_size;
  530. u16 rc_tar_rate_scale_temp_a;
  531. u16 rc_tar_rate_scale_temp_b;
  532. u16 rc_tar_rate_scale;
  533. u16 block_max_bits;
  534. u16 rc_lambda_bitrate_scale;
  535. u16 rc_buffer_fullness_scale;
  536. u16 rc_fullness_offset_thresh;
  537. u16 ramp_blocks;
  538. u16 bits_per_pixel;
  539. u16 num_extra_mux_bits_init;
  540. u16 extra_crop_bits;
  541. u16 num_extra_mux_bits;
  542. u16 mppf_bits_comp_0;
  543. u16 mppf_bits_comp_1;
  544. u16 mppf_bits_comp_2;
  545. u16 min_block_bits;
  546. int slice_height;
  547. int slice_width;
  548. int frame_width;
  549. int frame_height;
  550. int bytes_in_slice;
  551. int bytes_per_pkt;
  552. int eol_byte_num;
  553. int pclk_per_line;
  554. int slice_per_pkt;
  555. int pkt_per_line;
  556. int min_ssm_delay;
  557. int max_ssm_delay;
  558. int input_ssm_out_latency;
  559. int input_ssm_out_latency_min;
  560. int obuf_latency;
  561. int base_hs_latency;
  562. int base_hs_latency_min;
  563. int base_hs_latency_pixels;
  564. int base_hs_latency_pixels_min;
  565. int base_initial_lines;
  566. int base_top_up;
  567. int output_rate;
  568. int output_rate_ratio_100;
  569. int burst_accum_pixels;
  570. int ss_initial_lines;
  571. int burst_initial_lines;
  572. int initial_lines;
  573. int obuf_base;
  574. int obuf_extra_ss0;
  575. int obuf_extra_ss1;
  576. int obuf_extra_burst;
  577. int obuf_ss0;
  578. int obuf_ss1;
  579. int obuf_margin_words;
  580. int ob0_max_addr;
  581. int ob1_max_addr;
  582. int slice_width_orig;
  583. int r2b0_max_addr;
  584. int r2b1_max_addr;
  585. u32 slice_num_px;
  586. u32 rc_target_rate_threshold;
  587. u32 rc_fullness_offset_slope;
  588. u32 pps_delay_ms;
  589. u32 version_release;
  590. u64 slice_num_bits;
  591. u64 ramp_bits;
  592. };
  593. /**
  594. * Bits/pixel target >> 4 (removing the fractional bits)
  595. * returns the integer bpp value from the drm_dsc_config struct
  596. */
  597. #define DSC_BPP(config) ((config).bits_per_pixel >> 4)
  598. /**
  599. * struct msm_compression_info - defined panel compression
  600. * @comp_type: type of compression supported
  601. * @comp_ratio: compression ratio
  602. * @dsc_info: dsc configuration if the compression
  603. * supported is DSC
  604. * @vdc_info: vdc configuration if the compression
  605. * supported is VDC
  606. */
  607. struct msm_compression_info {
  608. enum msm_display_compression_type comp_type;
  609. u32 comp_ratio;
  610. union{
  611. struct msm_display_dsc_info dsc_info;
  612. struct msm_display_vdc_info vdc_info;
  613. };
  614. };
  615. /**
  616. * struct msm_display_topology - defines a display topology pipeline
  617. * @num_lm: number of layer mixers used
  618. * @num_enc: number of compression encoder blocks used
  619. * @num_intf: number of interfaces the panel is mounted on
  620. * @comp_type: type of compression supported
  621. */
  622. struct msm_display_topology {
  623. u32 num_lm;
  624. u32 num_enc;
  625. u32 num_intf;
  626. enum msm_display_compression_type comp_type;
  627. };
  628. /**
  629. * struct msm_mode_info - defines all msm custom mode info
  630. * @frame_rate: frame_rate of the mode
  631. * @vtotal: vtotal calculated for the mode
  632. * @prefill_lines: prefill lines based on porches.
  633. * @jitter_numer: display panel jitter numerator configuration
  634. * @jitter_denom: display panel jitter denominator configuration
  635. * @clk_rate: DSI bit clock per lane in HZ.
  636. * @dfps_maxfps: max FPS of dynamic FPS
  637. * @topology: supported topology for the mode
  638. * @comp_info: compression info supported
  639. * @roi_caps: panel roi capabilities
  640. * @wide_bus_en: wide-bus mode cfg for interface module
  641. * @panel_mode_caps panel mode capabilities
  642. * @mdp_transfer_time_us Specifies the mdp transfer time for command mode
  643. * panels in microseconds.
  644. * @allowed_mode_switches: bit mask to indicate supported mode switch.
  645. * @bit_clk_rates: list of supported bit clock rates
  646. * @bit_clk_count: number of supported bit clock rates
  647. */
  648. struct msm_mode_info {
  649. uint32_t frame_rate;
  650. uint32_t vtotal;
  651. uint32_t prefill_lines;
  652. uint32_t jitter_numer;
  653. uint32_t jitter_denom;
  654. uint64_t clk_rate;
  655. uint32_t dfps_maxfps;
  656. struct msm_display_topology topology;
  657. struct msm_compression_info comp_info;
  658. struct msm_roi_caps roi_caps;
  659. bool wide_bus_en;
  660. u32 panel_mode_caps;
  661. u32 mdp_transfer_time_us;
  662. u32 allowed_mode_switches;
  663. u32 *bit_clk_rates;
  664. u32 bit_clk_count;
  665. };
  666. /**
  667. * struct msm_resource_caps_info - defines hw resources
  668. * @num_lm number of layer mixers available
  669. * @num_dsc number of dsc available
  670. * @num_vdc number of vdc available
  671. * @num_ctl number of ctl available
  672. * @num_3dmux number of 3d mux available
  673. * @max_mixer_width: max width supported by layer mixer
  674. */
  675. struct msm_resource_caps_info {
  676. uint32_t num_lm;
  677. uint32_t num_dsc;
  678. uint32_t num_vdc;
  679. uint32_t num_ctl;
  680. uint32_t num_3dmux;
  681. uint32_t max_mixer_width;
  682. };
  683. /**
  684. * struct msm_display_info - defines display properties
  685. * @intf_type: DRM_MODE_CONNECTOR_ display type
  686. * @capabilities: Bitmask of display flags
  687. * @num_of_h_tiles: Number of horizontal tiles in case of split interface
  688. * @h_tile_instance: Controller instance used per tile. Number of elements is
  689. * based on num_of_h_tiles
  690. * @is_connected: Set to true if display is connected
  691. * @width_mm: Physical width
  692. * @height_mm: Physical height
  693. * @max_width: Max width of display. In case of hot pluggable display
  694. * this is max width supported by controller
  695. * @max_height: Max height of display. In case of hot pluggable display
  696. * this is max height supported by controller
  697. * @clk_rate: DSI bit clock per lane in HZ.
  698. * @display_type: Enum for type of display
  699. * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
  700. * used instead of panel TE in cmd mode panels
  701. * @poms_align_vsync: poms with vsync aligned
  702. * @roi_caps: Region of interest capability info
  703. * @qsync_min_fps Minimum fps supported by Qsync feature
  704. * @has_qsync_min_fps_list True if dsi-supported-qsync-min-fps-list exits
  705. * @te_source vsync source pin information
  706. * @dsc_count: max dsc hw blocks used by display (only available
  707. * for dsi display)
  708. * @lm_count: max layer mixer blocks used by display (only available
  709. * for dsi display)
  710. */
  711. struct msm_display_info {
  712. int intf_type;
  713. uint32_t capabilities;
  714. enum panel_op_mode curr_panel_mode;
  715. uint32_t num_of_h_tiles;
  716. uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
  717. bool is_connected;
  718. unsigned int width_mm;
  719. unsigned int height_mm;
  720. uint32_t max_width;
  721. uint32_t max_height;
  722. uint64_t clk_rate;
  723. uint32_t display_type;
  724. bool is_te_using_watchdog_timer;
  725. bool poms_align_vsync;
  726. struct msm_roi_caps roi_caps;
  727. uint32_t qsync_min_fps;
  728. bool has_qsync_min_fps_list;
  729. uint32_t te_source;
  730. uint32_t dsc_count;
  731. uint32_t lm_count;
  732. };
  733. #define MSM_MAX_ROI 4
  734. /**
  735. * struct msm_roi_list - list of regions of interest for a drm object
  736. * @num_rects: number of valid rectangles in the roi array
  737. * @roi: list of roi rectangles
  738. */
  739. struct msm_roi_list {
  740. uint32_t num_rects;
  741. struct drm_clip_rect roi[MSM_MAX_ROI];
  742. };
  743. /**
  744. * struct - msm_display_kickoff_params - info for display features at kickoff
  745. * @rois: Regions of interest structure for mapping CRTC to Connector output
  746. */
  747. struct msm_display_kickoff_params {
  748. struct msm_roi_list *rois;
  749. struct drm_msm_ext_hdr_metadata *hdr_meta;
  750. };
  751. /**
  752. * struct - msm_display_conn_params - info of dpu display features
  753. * @qsync_mode: Qsync mode, where 0: disabled 1: continuous mode 2: oneshot
  754. * @qsync_update: Qsync settings were changed/updated
  755. */
  756. struct msm_display_conn_params {
  757. uint32_t qsync_mode;
  758. bool qsync_update;
  759. };
  760. /**
  761. * struct msm_drm_event - defines custom event notification struct
  762. * @base: base object required for event notification by DRM framework.
  763. * @event: event object required for event notification by DRM framework.
  764. */
  765. struct msm_drm_event {
  766. struct drm_pending_event base;
  767. struct drm_msm_event_resp event;
  768. };
  769. /* Commit/Event thread specific structure */
  770. struct msm_drm_thread {
  771. struct drm_device *dev;
  772. struct task_struct *thread;
  773. unsigned int crtc_id;
  774. struct kthread_worker worker;
  775. };
  776. struct msm_drm_private {
  777. struct drm_device *dev;
  778. struct msm_kms *kms;
  779. struct sde_power_handle phandle;
  780. /* subordinate devices, if present: */
  781. struct platform_device *gpu_pdev;
  782. /* top level MDSS wrapper device (for MDP5 only) */
  783. struct msm_mdss *mdss;
  784. /* possibly this should be in the kms component, but it is
  785. * shared by both mdp4 and mdp5..
  786. */
  787. struct hdmi *hdmi;
  788. /* eDP is for mdp5 only, but kms has not been created
  789. * when edp_bind() and edp_init() are called. Here is the only
  790. * place to keep the edp instance.
  791. */
  792. struct msm_edp *edp;
  793. /* DSI is shared by mdp4 and mdp5 */
  794. struct msm_dsi *dsi[2];
  795. /* when we have more than one 'msm_gpu' these need to be an array: */
  796. struct msm_gpu *gpu;
  797. struct msm_file_private *lastctx;
  798. struct drm_fb_helper *fbdev;
  799. struct msm_rd_state *rd; /* debugfs to dump all submits */
  800. struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
  801. struct msm_perf_state *perf;
  802. /*
  803. * List of inactive GEM objects. Every bo is either in the inactive_list
  804. * or gpu->active_list (for the gpu it is active on[1])
  805. *
  806. * These lists are protected by mm_lock. If struct_mutex is involved, it
  807. * should be aquired prior to mm_lock. One should *not* hold mm_lock in
  808. * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
  809. *
  810. * [1] if someone ever added support for the old 2d cores, there could be
  811. * more than one gpu object
  812. */
  813. struct list_head inactive_list;
  814. struct mutex mm_lock;
  815. struct workqueue_struct *wq;
  816. /* crtcs pending async atomic updates: */
  817. uint32_t pending_crtcs;
  818. uint32_t pending_planes;
  819. wait_queue_head_t pending_crtcs_event;
  820. unsigned int num_planes;
  821. struct drm_plane *planes[MAX_PLANES];
  822. unsigned int num_crtcs;
  823. struct drm_crtc *crtcs[MAX_CRTCS];
  824. struct msm_drm_thread disp_thread[MAX_CRTCS];
  825. struct msm_drm_thread event_thread[MAX_CRTCS];
  826. struct task_struct *pp_event_thread;
  827. struct kthread_worker pp_event_worker;
  828. unsigned int num_encoders;
  829. struct drm_encoder *encoders[MAX_ENCODERS];
  830. unsigned int num_bridges;
  831. struct drm_bridge *bridges[MAX_BRIDGES];
  832. unsigned int num_connectors;
  833. struct drm_connector *connectors[MAX_CONNECTORS];
  834. /* Properties */
  835. struct drm_property *plane_property[PLANE_PROP_COUNT];
  836. struct drm_property *crtc_property[CRTC_PROP_COUNT];
  837. struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
  838. /* Color processing properties for the crtc */
  839. struct drm_property **cp_property;
  840. /* VRAM carveout, used when no IOMMU: */
  841. struct {
  842. unsigned long size;
  843. dma_addr_t paddr;
  844. /* NOTE: mm managed at the page level, size is in # of pages
  845. * and position mm_node->start is in # of pages:
  846. */
  847. struct drm_mm mm;
  848. spinlock_t lock; /* Protects drm_mm node allocation/removal */
  849. } vram;
  850. struct notifier_block vmap_notifier;
  851. struct shrinker shrinker;
  852. struct drm_atomic_state *pm_state;
  853. /* task holding struct_mutex.. currently only used in submit path
  854. * to detect and reject faults from copy_from_user() for submit
  855. * ioctl.
  856. */
  857. struct task_struct *struct_mutex_task;
  858. /* list of clients waiting for events */
  859. struct list_head client_event_list;
  860. /* whether registered and drm_dev_unregister should be called */
  861. bool registered;
  862. /* msm drv debug root node */
  863. struct dentry *debug_root;
  864. /* update the flag when msm driver receives shutdown notification */
  865. bool shutdown_in_progress;
  866. struct mutex vm_client_lock;
  867. struct list_head vm_client_list;
  868. };
  869. /* get struct msm_kms * from drm_device * */
  870. #define ddev_to_msm_kms(D) ((D) && (D)->dev_private ? \
  871. ((struct msm_drm_private *)((D)->dev_private))->kms : NULL)
  872. struct msm_format {
  873. uint32_t pixel_format;
  874. };
  875. int msm_atomic_prepare_fb(struct drm_plane *plane,
  876. struct drm_plane_state *new_state);
  877. void msm_atomic_commit_tail(struct drm_atomic_state *state);
  878. int msm_atomic_commit(struct drm_device *dev,
  879. struct drm_atomic_state *state, bool nonblock);
  880. /* callback from wq once fence has passed: */
  881. struct msm_fence_cb {
  882. struct work_struct work;
  883. uint32_t fence;
  884. void (*func)(struct msm_fence_cb *cb);
  885. };
  886. void __msm_fence_worker(struct work_struct *work);
  887. #define INIT_FENCE_CB(_cb, _func) do { \
  888. INIT_WORK(&(_cb)->work, __msm_fence_worker); \
  889. (_cb)->func = _func; \
  890. } while (0)
  891. struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
  892. void msm_atomic_state_clear(struct drm_atomic_state *state);
  893. void msm_atomic_state_free(struct drm_atomic_state *state);
  894. int msm_gem_init_vma(struct msm_gem_address_space *aspace,
  895. struct msm_gem_vma *vma, int npages);
  896. void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
  897. struct msm_gem_vma *vma, struct sg_table *sgt,
  898. unsigned int flags);
  899. int msm_gem_map_vma(struct msm_gem_address_space *aspace,
  900. struct msm_gem_vma *vma, struct sg_table *sgt, int npages,
  901. unsigned int flags);
  902. struct device *msm_gem_get_aspace_device(struct msm_gem_address_space *aspace);
  903. void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
  904. struct msm_gem_address_space *
  905. msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
  906. const char *name);
  907. /* For SDE display */
  908. struct msm_gem_address_space *
  909. msm_gem_smmu_address_space_create(struct drm_device *dev, struct msm_mmu *mmu,
  910. const char *name);
  911. /**
  912. * msm_gem_add_obj_to_aspace_active_list: adds obj to active obj list in aspace
  913. */
  914. void msm_gem_add_obj_to_aspace_active_list(
  915. struct msm_gem_address_space *aspace,
  916. struct drm_gem_object *obj);
  917. /**
  918. * msm_gem_remove_obj_from_aspace_active_list: removes obj from active obj
  919. * list in aspace
  920. */
  921. void msm_gem_remove_obj_from_aspace_active_list(
  922. struct msm_gem_address_space *aspace,
  923. struct drm_gem_object *obj);
  924. /**
  925. * msm_gem_smmu_address_space_get: returns the aspace pointer for the requested
  926. * domain
  927. */
  928. struct msm_gem_address_space *
  929. msm_gem_smmu_address_space_get(struct drm_device *dev,
  930. unsigned int domain);
  931. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  932. void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  933. /**
  934. * msm_gem_aspace_domain_attach_detach: function to inform the attach/detach
  935. * of the domain for this aspace
  936. */
  937. void msm_gem_aspace_domain_attach_detach_update(
  938. struct msm_gem_address_space *aspace,
  939. bool is_detach);
  940. /**
  941. * msm_gem_address_space_register_cb: function to register callback for attach
  942. * and detach of the domain
  943. */
  944. int msm_gem_address_space_register_cb(
  945. struct msm_gem_address_space *aspace,
  946. void (*cb)(void *, bool),
  947. void *cb_data);
  948. /**
  949. * msm_gem_address_space_register_cb: function to unregister callback
  950. */
  951. int msm_gem_address_space_unregister_cb(
  952. struct msm_gem_address_space *aspace,
  953. void (*cb)(void *, bool),
  954. void *cb_data);
  955. void msm_gem_submit_free(struct msm_gem_submit *submit);
  956. int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
  957. struct drm_file *file);
  958. void msm_gem_shrinker_init(struct drm_device *dev);
  959. void msm_gem_shrinker_cleanup(struct drm_device *dev);
  960. void msm_gem_sync(struct drm_gem_object *obj);
  961. int msm_gem_mmap_obj(struct drm_gem_object *obj,
  962. struct vm_area_struct *vma);
  963. int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
  964. vm_fault_t msm_gem_fault(struct vm_fault *vmf);
  965. uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
  966. int msm_gem_get_iova(struct drm_gem_object *obj,
  967. struct msm_gem_address_space *aspace, uint64_t *iova);
  968. int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
  969. struct msm_gem_address_space *aspace, uint64_t *iova);
  970. uint64_t msm_gem_iova(struct drm_gem_object *obj,
  971. struct msm_gem_address_space *aspace);
  972. void msm_gem_unpin_iova(struct drm_gem_object *obj,
  973. struct msm_gem_address_space *aspace);
  974. struct page **msm_gem_get_pages(struct drm_gem_object *obj);
  975. void msm_gem_put_pages(struct drm_gem_object *obj);
  976. void msm_gem_put_iova(struct drm_gem_object *obj,
  977. struct msm_gem_address_space *aspace);
  978. dma_addr_t msm_gem_get_dma_addr(struct drm_gem_object *obj);
  979. int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
  980. struct drm_mode_create_dumb *args);
  981. int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
  982. uint32_t handle, uint64_t *offset);
  983. struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
  984. void *msm_gem_prime_vmap(struct drm_gem_object *obj);
  985. void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  986. int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
  987. struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
  988. struct dma_buf_attachment *attach, struct sg_table *sg);
  989. int msm_gem_prime_pin(struct drm_gem_object *obj);
  990. void msm_gem_prime_unpin(struct drm_gem_object *obj);
  991. struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev,
  992. struct dma_buf *dma_buf);
  993. void *msm_gem_get_vaddr(struct drm_gem_object *obj);
  994. void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
  995. void msm_gem_put_vaddr(struct drm_gem_object *obj);
  996. int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
  997. int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
  998. int msm_gem_cpu_fini(struct drm_gem_object *obj);
  999. void msm_gem_free_object(struct drm_gem_object *obj);
  1000. int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
  1001. uint32_t size, uint32_t flags, uint32_t *handle, char *name);
  1002. struct drm_gem_object *msm_gem_new(struct drm_device *dev,
  1003. uint32_t size, uint32_t flags);
  1004. struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
  1005. uint32_t size, uint32_t flags);
  1006. void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
  1007. uint32_t flags, struct msm_gem_address_space *aspace,
  1008. struct drm_gem_object **bo, uint64_t *iova);
  1009. void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
  1010. uint32_t flags, struct msm_gem_address_space *aspace,
  1011. struct drm_gem_object **bo, uint64_t *iova);
  1012. struct drm_gem_object *msm_gem_import(struct drm_device *dev,
  1013. struct dma_buf *dmabuf, struct sg_table *sgt);
  1014. __printf(2, 3)
  1015. void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
  1016. int msm_gem_delayed_import(struct drm_gem_object *obj);
  1017. void msm_framebuffer_set_keepattrs(struct drm_framebuffer *fb, bool enable);
  1018. int msm_framebuffer_prepare(struct drm_framebuffer *fb,
  1019. struct msm_gem_address_space *aspace);
  1020. void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
  1021. struct msm_gem_address_space *aspace);
  1022. uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
  1023. struct msm_gem_address_space *aspace, int plane);
  1024. uint32_t msm_framebuffer_phys(struct drm_framebuffer *fb, int plane);
  1025. struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
  1026. const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
  1027. struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
  1028. const struct drm_mode_fb_cmd2 *mode_cmd,
  1029. struct drm_gem_object **bos);
  1030. struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
  1031. struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
  1032. struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
  1033. int w, int h, int p, uint32_t format);
  1034. struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
  1035. void msm_fbdev_free(struct drm_device *dev);
  1036. struct hdmi;
  1037. #if IS_ENABLED(CONFIG_DRM_MSM_HDMI)
  1038. int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
  1039. struct drm_encoder *encoder);
  1040. void __init msm_hdmi_register(void);
  1041. void __exit msm_hdmi_unregister(void);
  1042. #else
  1043. static inline void __init msm_hdmi_register(void)
  1044. {
  1045. }
  1046. static inline void __exit msm_hdmi_unregister(void)
  1047. {
  1048. }
  1049. #endif /* CONFIG_DRM_MSM_HDMI */
  1050. struct msm_edp;
  1051. #if IS_ENABLED(CONFIG_DRM_MSM_EDP)
  1052. void __init msm_edp_register(void);
  1053. void __exit msm_edp_unregister(void);
  1054. int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
  1055. struct drm_encoder *encoder);
  1056. #else
  1057. static inline void __init msm_edp_register(void)
  1058. {
  1059. }
  1060. static inline void __exit msm_edp_unregister(void)
  1061. {
  1062. }
  1063. static inline int msm_edp_modeset_init(struct msm_edp *edp,
  1064. struct drm_device *dev, struct drm_encoder *encoder)
  1065. {
  1066. return -EINVAL;
  1067. }
  1068. #endif /* CONFIG_DRM_MSM_EDP */
  1069. struct msm_dsi;
  1070. /* *
  1071. * msm_mode_object_event_notify - notify user-space clients of drm object
  1072. * events.
  1073. * @obj: mode object (crtc/connector) that is generating the event.
  1074. * @event: event that needs to be notified.
  1075. * @payload: payload for the event.
  1076. */
  1077. void msm_mode_object_event_notify(struct drm_mode_object *obj,
  1078. struct drm_device *dev, struct drm_event *event, u8 *payload);
  1079. #if IS_ENABLED(CONFIG_DRM_MSM_DSI)
  1080. static inline void __init msm_dsi_register(void)
  1081. {
  1082. }
  1083. static inline void __exit msm_dsi_unregister(void)
  1084. {
  1085. }
  1086. static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
  1087. struct drm_device *dev,
  1088. struct drm_encoder *encoder)
  1089. {
  1090. return -EINVAL;
  1091. }
  1092. #else
  1093. void __init msm_dsi_register(void);
  1094. void __exit msm_dsi_unregister(void);
  1095. int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
  1096. struct drm_encoder *encoder);
  1097. #endif /* CONFIG_DRM_MSM_DSI */
  1098. #if IS_ENABLED(CONFIG_DRM_MSM_MDP5)
  1099. void __init msm_mdp_register(void);
  1100. void __exit msm_mdp_unregister(void);
  1101. #else
  1102. static inline void __init msm_mdp_register(void)
  1103. {
  1104. }
  1105. static inline void __exit msm_mdp_unregister(void)
  1106. {
  1107. }
  1108. #endif /* CONFIG_DRM_MSM_MDP5 */
  1109. #ifdef CONFIG_DEBUG_FS
  1110. void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
  1111. void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
  1112. void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
  1113. int msm_debugfs_late_init(struct drm_device *dev);
  1114. int msm_rd_debugfs_init(struct drm_minor *minor);
  1115. void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
  1116. __printf(3, 4)
  1117. void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  1118. const char *fmt, ...);
  1119. int msm_perf_debugfs_init(struct drm_minor *minor);
  1120. void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
  1121. #else
  1122. static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
  1123. __printf(3, 4)
  1124. static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  1125. const char *fmt, ...) {}
  1126. static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
  1127. static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
  1128. #endif
  1129. #if IS_ENABLED(CONFIG_DRM_MSM_DSI)
  1130. void __init dsi_display_register(void);
  1131. void __exit dsi_display_unregister(void);
  1132. #else
  1133. static inline void __init dsi_display_register(void)
  1134. {
  1135. }
  1136. static inline void __exit dsi_display_unregister(void)
  1137. {
  1138. }
  1139. #endif /* CONFIG_DRM_MSM_DSI */
  1140. #if IS_ENABLED(CONFIG_HDCP_QSEECOM)
  1141. void __init msm_hdcp_register(void);
  1142. void __exit msm_hdcp_unregister(void);
  1143. #else
  1144. static inline void __init msm_hdcp_register(void)
  1145. {
  1146. }
  1147. static inline void __exit msm_hdcp_unregister(void)
  1148. {
  1149. }
  1150. #endif /* CONFIG_HDCP_QSEECOM */
  1151. #if IS_ENABLED(CONFIG_DRM_MSM_DP)
  1152. void __init dp_display_register(void);
  1153. void __exit dp_display_unregister(void);
  1154. #else
  1155. static inline void __init dp_display_register(void)
  1156. {
  1157. }
  1158. static inline void __exit dp_display_unregister(void)
  1159. {
  1160. }
  1161. #endif /* CONFIG_DRM_MSM_DP */
  1162. #if IS_ENABLED(CONFIG_DRM_SDE_RSC)
  1163. void __init sde_rsc_register(void);
  1164. void __exit sde_rsc_unregister(void);
  1165. void __init sde_rsc_rpmh_register(void);
  1166. #else
  1167. static inline void __init sde_rsc_register(void)
  1168. {
  1169. }
  1170. static inline void __exit sde_rsc_unregister(void)
  1171. {
  1172. }
  1173. static inline void __init sde_rsc_rpmh_register(void)
  1174. {
  1175. }
  1176. #endif /* CONFIG_DRM_SDE_RSC */
  1177. #if IS_ENABLED(CONFIG_DRM_SDE_WB)
  1178. void __init sde_wb_register(void);
  1179. void __exit sde_wb_unregister(void);
  1180. #else
  1181. static inline void __init sde_wb_register(void)
  1182. {
  1183. }
  1184. static inline void __exit sde_wb_unregister(void)
  1185. {
  1186. }
  1187. #endif /* CONFIG_DRM_SDE_WB */
  1188. #if IS_ENABLED(CONFIG_MSM_SDE_ROTATOR)
  1189. void sde_rotator_register(void);
  1190. void sde_rotator_unregister(void);
  1191. #else
  1192. static inline void sde_rotator_register(void)
  1193. {
  1194. }
  1195. static inline void sde_rotator_unregister(void)
  1196. {
  1197. }
  1198. #endif /* CONFIG_MSM_SDE_ROTATOR */
  1199. #if IS_ENABLED(CONFIG_MSM_SDE_ROTATOR)
  1200. void sde_rotator_smmu_driver_register(void);
  1201. void sde_rotator_smmu_driver_unregister(void);
  1202. #else
  1203. static inline void sde_rotator_smmu_driver_register(void)
  1204. {
  1205. }
  1206. static inline void sde_rotator_smmu_driver_unregister(void)
  1207. {
  1208. }
  1209. #endif /* CONFIG_MSM_SDE_ROTATOR */
  1210. struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
  1211. int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);
  1212. struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
  1213. const char *name);
  1214. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  1215. const char *dbgname);
  1216. unsigned long msm_iomap_size(struct platform_device *pdev, const char *name);
  1217. void msm_iounmap(struct platform_device *dev, void __iomem *addr);
  1218. void msm_writel(u32 data, void __iomem *addr);
  1219. u32 msm_readl(const void __iomem *addr);
  1220. #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  1221. #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  1222. static inline int align_pitch(int width, int bpp)
  1223. {
  1224. int bytespp = (bpp + 7) / 8;
  1225. /* adreno needs pitch aligned to 32 pixels: */
  1226. return bytespp * ALIGN(width, 32);
  1227. }
  1228. /* for the generated headers: */
  1229. #define INVALID_IDX(idx) ({BUG(); 0;})
  1230. #define fui(x) ({BUG(); 0;})
  1231. #define util_float_to_half(x) ({BUG(); 0;})
  1232. #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
  1233. /* for conditionally setting boolean flag(s): */
  1234. #define COND(bool, val) ((bool) ? (val) : 0)
  1235. static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
  1236. {
  1237. ktime_t now = ktime_get();
  1238. unsigned long remaining_jiffies;
  1239. if (ktime_compare(*timeout, now) < 0) {
  1240. remaining_jiffies = 0;
  1241. } else {
  1242. ktime_t rem = ktime_sub(*timeout, now);
  1243. remaining_jiffies = nsecs_to_jiffies(ktime_to_ns(rem));
  1244. }
  1245. return remaining_jiffies;
  1246. }
  1247. int msm_get_mixer_count(struct msm_drm_private *priv,
  1248. const struct drm_display_mode *mode,
  1249. const struct msm_resource_caps_info *res, u32 *num_lm);
  1250. int msm_get_dsc_count(struct msm_drm_private *priv,
  1251. u32 hdisplay, u32 *num_dsc);
  1252. int msm_get_src_bpc(int chroma_format, int bpc);
  1253. #endif /* __MSM_DRV_H__ */