hfi.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/random.h>
  9. #include <asm/errno.h>
  10. #include <linux/timer.h>
  11. #include <media/cam_icp.h>
  12. #include <linux/iopoll.h>
  13. #include "cam_io_util.h"
  14. #include "hfi_reg.h"
  15. #include "hfi_sys_defs.h"
  16. #include "hfi_session_defs.h"
  17. #include "hfi_intf.h"
  18. #include "cam_icp_hw_mgr_intf.h"
  19. #include "cam_debug_util.h"
  20. #include "cam_compat.h"
  21. #define HFI_VERSION_INFO_MAJOR_VAL 1
  22. #define HFI_VERSION_INFO_MINOR_VAL 1
  23. #define HFI_VERSION_INFO_STEP_VAL 0
  24. #define HFI_VERSION_INFO_STEP_VAL 0
  25. #define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000
  26. #define HFI_VERSION_INFO_MAJOR_SHFT 24
  27. #define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00
  28. #define HFI_VERSION_INFO_MINOR_SHFT 8
  29. #define HFI_VERSION_INFO_STEP_BMSK 0xFF
  30. #define HFI_VERSION_INFO_STEP_SHFT 0
  31. #define HFI_POLL_DELAY_US 100
  32. #define HFI_POLL_TIMEOUT_US 10000
  33. static struct hfi_info *g_hfi;
  34. unsigned int g_icp_mmu_hdl;
  35. static DEFINE_MUTEX(hfi_cmd_q_mutex);
  36. static DEFINE_MUTEX(hfi_msg_q_mutex);
  37. static void hfi_irq_raise(struct hfi_info *hfi)
  38. {
  39. if (hfi->ops.irq_raise)
  40. hfi->ops.irq_raise(hfi->priv);
  41. }
  42. static void hfi_irq_enable(struct hfi_info *hfi)
  43. {
  44. if (hfi->ops.irq_enable)
  45. hfi->ops.irq_enable(hfi->priv);
  46. }
  47. static void __iomem *hfi_iface_addr(struct hfi_info *hfi)
  48. {
  49. void __iomem *ret = NULL;
  50. if (hfi->ops.iface_addr)
  51. ret = hfi->ops.iface_addr(hfi->priv);
  52. return IS_ERR_OR_NULL(ret) ? NULL : ret;
  53. }
  54. static void hfi_queue_dump(uint32_t *dwords, int count)
  55. {
  56. int i;
  57. int rows;
  58. int remaining;
  59. rows = count / 4;
  60. remaining = count % 4;
  61. for (i = 0; i < rows; i++, dwords += 4)
  62. CAM_DBG(CAM_HFI,
  63. "word[%04d]: 0x%08x 0x%08x 0x%08x 0x%08x",
  64. i * 4, dwords[0], dwords[1], dwords[2], dwords[3]);
  65. if (remaining == 1)
  66. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x", rows * 4, dwords[0]);
  67. else if (remaining == 2)
  68. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x",
  69. rows * 4, dwords[0], dwords[1]);
  70. else if (remaining == 3)
  71. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x 0x%08x",
  72. rows * 4, dwords[0], dwords[1], dwords[2]);
  73. }
  74. void cam_hfi_queue_dump(void)
  75. {
  76. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  77. struct hfi_qtbl *qtbl;
  78. struct hfi_q_hdr *q_hdr;
  79. uint32_t *dwords;
  80. int num_dwords;
  81. if (!hfi_mem) {
  82. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  83. return;
  84. }
  85. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  86. CAM_DBG(CAM_HFI,
  87. "qtbl header: version=0x%08x tbl_size=%u numq=%u qhdr_size=%u",
  88. qtbl->q_tbl_hdr.qtbl_version,
  89. qtbl->q_tbl_hdr.qtbl_size,
  90. qtbl->q_tbl_hdr.qtbl_num_q,
  91. qtbl->q_tbl_hdr.qtbl_qhdr_size);
  92. q_hdr = &qtbl->q_hdr[Q_CMD];
  93. CAM_DBG(CAM_HFI,
  94. "cmd_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  95. hfi_mem->cmd_q.iova,
  96. q_hdr->qhdr_q_size,
  97. q_hdr->qhdr_read_idx,
  98. q_hdr->qhdr_write_idx);
  99. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  100. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  101. hfi_queue_dump(dwords, num_dwords);
  102. q_hdr = &qtbl->q_hdr[Q_MSG];
  103. CAM_DBG(CAM_HFI,
  104. "msg_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  105. hfi_mem->msg_q.iova,
  106. q_hdr->qhdr_q_size,
  107. q_hdr->qhdr_read_idx,
  108. q_hdr->qhdr_write_idx);
  109. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  110. num_dwords = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  111. hfi_queue_dump(dwords, num_dwords);
  112. }
  113. int hfi_write_cmd(void *cmd_ptr)
  114. {
  115. uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp;
  116. uint32_t *write_q, *write_ptr;
  117. struct hfi_qtbl *q_tbl;
  118. struct hfi_q_hdr *q;
  119. int rc = 0;
  120. if (!cmd_ptr) {
  121. CAM_ERR(CAM_HFI, "command is null");
  122. return -EINVAL;
  123. }
  124. mutex_lock(&hfi_cmd_q_mutex);
  125. if (!g_hfi) {
  126. CAM_ERR(CAM_HFI, "HFI interface not setup");
  127. rc = -ENODEV;
  128. goto err;
  129. }
  130. if (g_hfi->hfi_state != HFI_READY ||
  131. !g_hfi->cmd_q_state) {
  132. CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u",
  133. g_hfi->hfi_state, g_hfi->cmd_q_state);
  134. rc = -ENODEV;
  135. goto err;
  136. }
  137. q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  138. q = &q_tbl->q_hdr[Q_CMD];
  139. write_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  140. size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT;
  141. if (!size_in_words) {
  142. CAM_DBG(CAM_HFI, "failed");
  143. rc = -EINVAL;
  144. goto err;
  145. }
  146. read_idx = q->qhdr_read_idx;
  147. empty_space = (q->qhdr_write_idx >= read_idx) ?
  148. (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) :
  149. (read_idx - q->qhdr_write_idx);
  150. if (empty_space <= size_in_words) {
  151. CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u",
  152. empty_space, size_in_words);
  153. rc = -EIO;
  154. goto err;
  155. }
  156. new_write_idx = q->qhdr_write_idx + size_in_words;
  157. write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx);
  158. if (new_write_idx < q->qhdr_q_size) {
  159. memcpy(write_ptr, (uint8_t *)cmd_ptr,
  160. size_in_words << BYTE_WORD_SHIFT);
  161. } else {
  162. new_write_idx -= q->qhdr_q_size;
  163. temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT;
  164. memcpy(write_ptr, (uint8_t *)cmd_ptr, temp);
  165. memcpy(write_q, (uint8_t *)cmd_ptr + temp,
  166. new_write_idx << BYTE_WORD_SHIFT);
  167. }
  168. /*
  169. * To make sure command data in a command queue before
  170. * updating write index
  171. */
  172. wmb();
  173. q->qhdr_write_idx = new_write_idx;
  174. /*
  175. * Before raising interrupt make sure command data is ready for
  176. * firmware to process
  177. */
  178. wmb();
  179. hfi_irq_raise(g_hfi);
  180. err:
  181. mutex_unlock(&hfi_cmd_q_mutex);
  182. return rc;
  183. }
  184. int hfi_read_message(uint32_t *pmsg, uint8_t q_id,
  185. uint32_t *words_read)
  186. {
  187. struct hfi_qtbl *q_tbl_ptr;
  188. struct hfi_q_hdr *q;
  189. uint32_t new_read_idx, size_in_words, word_diff, temp;
  190. uint32_t *read_q, *read_ptr, *write_ptr;
  191. uint32_t size_upper_bound = 0;
  192. int rc = 0;
  193. if (!pmsg) {
  194. CAM_ERR(CAM_HFI, "Invalid msg");
  195. return -EINVAL;
  196. }
  197. if (q_id > Q_DBG) {
  198. CAM_ERR(CAM_HFI, "Invalid q :%u", q_id);
  199. return -EINVAL;
  200. }
  201. mutex_lock(&hfi_msg_q_mutex);
  202. if (!g_hfi) {
  203. CAM_ERR(CAM_HFI, "hfi not set up yet");
  204. rc = -ENODEV;
  205. goto err;
  206. }
  207. if ((g_hfi->hfi_state != HFI_READY) ||
  208. !g_hfi->msg_q_state) {
  209. CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u",
  210. g_hfi->hfi_state, g_hfi->msg_q_state);
  211. rc = -ENODEV;
  212. goto err;
  213. }
  214. q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  215. q = &q_tbl_ptr->q_hdr[q_id];
  216. if (q->qhdr_read_idx == q->qhdr_write_idx) {
  217. CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u",
  218. g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx);
  219. rc = -EIO;
  220. goto err;
  221. }
  222. if (q_id == Q_MSG) {
  223. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  224. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS;
  225. } else {
  226. read_q = (uint32_t *)g_hfi->map.dbg_q.kva;
  227. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS;
  228. }
  229. read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx);
  230. write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx);
  231. if (write_ptr > read_ptr)
  232. size_in_words = write_ptr - read_ptr;
  233. else {
  234. word_diff = read_ptr - write_ptr;
  235. if (q_id == Q_MSG)
  236. size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >>
  237. BYTE_WORD_SHIFT) - word_diff;
  238. else
  239. size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >>
  240. BYTE_WORD_SHIFT) - word_diff;
  241. }
  242. if ((size_in_words == 0) ||
  243. (size_in_words > size_upper_bound)) {
  244. CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x",
  245. size_in_words << BYTE_WORD_SHIFT);
  246. q->qhdr_read_idx = q->qhdr_write_idx;
  247. rc = -EIO;
  248. goto err;
  249. }
  250. new_read_idx = q->qhdr_read_idx + size_in_words;
  251. if (new_read_idx < q->qhdr_q_size) {
  252. memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT);
  253. } else {
  254. new_read_idx -= q->qhdr_q_size;
  255. temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT;
  256. memcpy(pmsg, read_ptr, temp);
  257. memcpy((uint8_t *)pmsg + temp, read_q,
  258. new_read_idx << BYTE_WORD_SHIFT);
  259. }
  260. q->qhdr_read_idx = new_read_idx;
  261. *words_read = size_in_words;
  262. /* Memory Barrier to make sure message
  263. * queue parameters are updated after read
  264. */
  265. wmb();
  266. err:
  267. mutex_unlock(&hfi_msg_q_mutex);
  268. return rc;
  269. }
  270. int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg)
  271. {
  272. uint8_t *prop;
  273. struct hfi_cmd_prop *dbg_prop;
  274. uint32_t size = 0;
  275. size = sizeof(struct hfi_cmd_prop) +
  276. sizeof(struct hfi_cmd_ubwc_cfg);
  277. CAM_DBG(CAM_HFI,
  278. "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]",
  279. size, ubwc_cfg[0], ubwc_cfg[1]);
  280. prop = kzalloc(size, GFP_KERNEL);
  281. if (!prop)
  282. return -ENOMEM;
  283. dbg_prop = (struct hfi_cmd_prop *)prop;
  284. dbg_prop->size = size;
  285. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  286. dbg_prop->num_prop = 1;
  287. dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG;
  288. dbg_prop->prop_data[1] = ubwc_cfg[0];
  289. dbg_prop->prop_data[2] = ubwc_cfg[1];
  290. hfi_write_cmd(prop);
  291. kfree(prop);
  292. return 0;
  293. }
  294. int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg,
  295. uint32_t *ubwc_bps_cfg)
  296. {
  297. uint8_t *prop;
  298. struct hfi_cmd_prop *dbg_prop;
  299. uint32_t size = 0;
  300. size = sizeof(struct hfi_cmd_prop) +
  301. sizeof(struct hfi_cmd_ubwc_cfg_ext);
  302. CAM_DBG(CAM_HFI,
  303. "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]",
  304. size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1],
  305. ubwc_bps_cfg[0], ubwc_bps_cfg[1]);
  306. prop = kzalloc(size, GFP_KERNEL);
  307. if (!prop)
  308. return -ENOMEM;
  309. dbg_prop = (struct hfi_cmd_prop *)prop;
  310. dbg_prop->size = size;
  311. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  312. dbg_prop->num_prop = 1;
  313. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX;
  314. dbg_prop->prop_data[1] = ubwc_bps_cfg[0];
  315. dbg_prop->prop_data[2] = ubwc_bps_cfg[1];
  316. dbg_prop->prop_data[3] = ubwc_ipe_cfg[0];
  317. dbg_prop->prop_data[4] = ubwc_ipe_cfg[1];
  318. hfi_write_cmd(prop);
  319. kfree(prop);
  320. return 0;
  321. }
  322. int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info)
  323. {
  324. uint8_t *prop;
  325. struct hfi_cmd_prop *dbg_prop;
  326. uint32_t size = 0;
  327. size = sizeof(struct hfi_cmd_prop) +
  328. sizeof(struct hfi_ipe_bps_pc);
  329. prop = kzalloc(size, GFP_KERNEL);
  330. if (!prop)
  331. return -ENOMEM;
  332. dbg_prop = (struct hfi_cmd_prop *)prop;
  333. dbg_prop->size = size;
  334. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  335. dbg_prop->num_prop = 1;
  336. dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC;
  337. dbg_prop->prop_data[1] = enable;
  338. dbg_prop->prop_data[2] = core_info;
  339. hfi_write_cmd(prop);
  340. kfree(prop);
  341. return 0;
  342. }
  343. int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl)
  344. {
  345. uint8_t *prop;
  346. struct hfi_cmd_prop *dbg_prop;
  347. uint32_t size = 0, val;
  348. val = HFI_DEBUG_MSG_LOW |
  349. HFI_DEBUG_MSG_MEDIUM |
  350. HFI_DEBUG_MSG_HIGH |
  351. HFI_DEBUG_MSG_ERROR |
  352. HFI_DEBUG_MSG_FATAL |
  353. HFI_DEBUG_MSG_PERF |
  354. HFI_DEBUG_CFG_WFI |
  355. HFI_DEBUG_CFG_ARM9WD;
  356. if (lvl > val)
  357. return -EINVAL;
  358. size = sizeof(struct hfi_cmd_prop) +
  359. sizeof(struct hfi_debug);
  360. prop = kzalloc(size, GFP_KERNEL);
  361. if (!prop)
  362. return -ENOMEM;
  363. dbg_prop = (struct hfi_cmd_prop *)prop;
  364. dbg_prop->size = size;
  365. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  366. dbg_prop->num_prop = 1;
  367. dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  368. dbg_prop->prop_data[1] = lvl;
  369. dbg_prop->prop_data[2] = icp_dbg_type;
  370. hfi_write_cmd(prop);
  371. kfree(prop);
  372. return 0;
  373. }
  374. int hfi_set_fw_dump_level(uint32_t lvl)
  375. {
  376. uint8_t *prop = NULL;
  377. struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL;
  378. uint32_t size = 0;
  379. CAM_DBG(CAM_HFI, "fw dump ENTER");
  380. size = sizeof(struct hfi_cmd_prop) + sizeof(lvl);
  381. prop = kzalloc(size, GFP_KERNEL);
  382. if (!prop)
  383. return -ENOMEM;
  384. fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop;
  385. fw_dump_level_switch_prop->size = size;
  386. fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  387. fw_dump_level_switch_prop->num_prop = 1;
  388. fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG;
  389. fw_dump_level_switch_prop->prop_data[1] = lvl;
  390. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  391. "prop->pkt_type = %d\n"
  392. "prop->num_prop = %d\n"
  393. "prop->prop_data[0] = %d\n"
  394. "prop->prop_data[1] = %d\n",
  395. fw_dump_level_switch_prop->size,
  396. fw_dump_level_switch_prop->pkt_type,
  397. fw_dump_level_switch_prop->num_prop,
  398. fw_dump_level_switch_prop->prop_data[0],
  399. fw_dump_level_switch_prop->prop_data[1]);
  400. hfi_write_cmd(prop);
  401. kfree(prop);
  402. return 0;
  403. }
  404. void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
  405. {
  406. switch (type) {
  407. case HFI_CMD_SYS_INIT: {
  408. struct hfi_cmd_sys_init init;
  409. memset(&init, 0, sizeof(init));
  410. init.size = sizeof(struct hfi_cmd_sys_init);
  411. init.pkt_type = type;
  412. hfi_write_cmd(&init);
  413. }
  414. break;
  415. case HFI_CMD_SYS_PC_PREP: {
  416. struct hfi_cmd_pc_prep prep;
  417. prep.size = sizeof(struct hfi_cmd_pc_prep);
  418. prep.pkt_type = type;
  419. hfi_write_cmd(&prep);
  420. }
  421. break;
  422. case HFI_CMD_SYS_SET_PROPERTY: {
  423. struct hfi_cmd_prop prop;
  424. if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) {
  425. prop.size = sizeof(struct hfi_cmd_prop);
  426. prop.pkt_type = type;
  427. prop.num_prop = 1;
  428. prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  429. hfi_write_cmd(&prop);
  430. }
  431. }
  432. break;
  433. case HFI_CMD_SYS_GET_PROPERTY:
  434. break;
  435. case HFI_CMD_SYS_PING: {
  436. struct hfi_cmd_ping_pkt ping;
  437. ping.size = sizeof(struct hfi_cmd_ping_pkt);
  438. ping.pkt_type = type;
  439. ping.user_data = (uint64_t)data;
  440. hfi_write_cmd(&ping);
  441. }
  442. break;
  443. case HFI_CMD_SYS_RESET: {
  444. struct hfi_cmd_sys_reset_pkt reset;
  445. reset.size = sizeof(struct hfi_cmd_sys_reset_pkt);
  446. reset.pkt_type = type;
  447. reset.user_data = (uint64_t)data;
  448. hfi_write_cmd(&reset);
  449. }
  450. break;
  451. case HFI_CMD_IPEBPS_CREATE_HANDLE: {
  452. struct hfi_cmd_create_handle handle;
  453. handle.size = sizeof(struct hfi_cmd_create_handle);
  454. handle.pkt_type = type;
  455. handle.handle_type = (uint32_t)data;
  456. handle.user_data1 = 0;
  457. hfi_write_cmd(&handle);
  458. }
  459. break;
  460. case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT:
  461. break;
  462. default:
  463. CAM_ERR(CAM_HFI, "command not supported :%d", type);
  464. break;
  465. }
  466. }
  467. int hfi_get_hw_caps(void *query_buf)
  468. {
  469. int i = 0;
  470. struct cam_icp_query_cap_cmd *query_cmd = NULL;
  471. if (!query_buf) {
  472. CAM_ERR(CAM_HFI, "query buf is NULL");
  473. return -EINVAL;
  474. }
  475. query_cmd = (struct cam_icp_query_cap_cmd *)query_buf;
  476. query_cmd->fw_version.major = 0x12;
  477. query_cmd->fw_version.minor = 0x12;
  478. query_cmd->fw_version.revision = 0x12;
  479. query_cmd->api_version.major = 0x13;
  480. query_cmd->api_version.minor = 0x13;
  481. query_cmd->api_version.revision = 0x13;
  482. query_cmd->num_ipe = 2;
  483. query_cmd->num_bps = 1;
  484. for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) {
  485. query_cmd->dev_ver[i].dev_type = i;
  486. query_cmd->dev_ver[i].hw_ver.major = 0x34 + i;
  487. query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i;
  488. query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i;
  489. }
  490. return 0;
  491. }
  492. int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
  493. {
  494. int rc = 0;
  495. uint32_t fw_version, status = 0;
  496. void __iomem *icp_base = hfi_iface_addr(g_hfi);
  497. if (!icp_base) {
  498. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  499. return -EINVAL;
  500. }
  501. if (readl_poll_timeout(icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE,
  502. status, status == ICP_INIT_RESP_SUCCESS,
  503. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US)) {
  504. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  505. status);
  506. return -ETIMEDOUT;
  507. }
  508. hfi_irq_enable(g_hfi);
  509. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  510. CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version);
  511. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR);
  512. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  513. icp_base + HFI_REG_SFR_PTR);
  514. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  515. icp_base + HFI_REG_SHARED_MEM_PTR);
  516. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  517. icp_base + HFI_REG_SHARED_MEM_SIZE);
  518. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  519. icp_base + HFI_REG_UNCACHED_HEAP_PTR);
  520. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  521. icp_base + HFI_REG_UNCACHED_HEAP_SIZE);
  522. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  523. icp_base + HFI_REG_QDSS_IOVA);
  524. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  525. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  526. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  527. icp_base + HFI_REG_IO_REGION_IOVA);
  528. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  529. icp_base + HFI_REG_IO_REGION_SIZE);
  530. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  531. icp_base + HFI_REG_IO2_REGION_IOVA);
  532. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  533. icp_base + HFI_REG_IO2_REGION_SIZE);
  534. CAM_INFO(CAM_HFI, "Resume IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  535. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  536. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  537. return rc;
  538. }
  539. int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
  540. void *priv, uint8_t event_driven_mode)
  541. {
  542. int rc = 0;
  543. uint32_t status = 0;
  544. struct hfi_qtbl *qtbl;
  545. struct hfi_qtbl_hdr *qtbl_hdr;
  546. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
  547. struct sfr_buf *sfr_buffer;
  548. void __iomem *icp_base;
  549. if (!hfi_mem || !hfi_ops || !priv) {
  550. CAM_ERR(CAM_HFI,
  551. "invalid arg: hfi_mem=%pK hfi_ops=%pK priv=%pK",
  552. hfi_mem, hfi_ops, priv);
  553. return -EINVAL;
  554. }
  555. mutex_lock(&hfi_cmd_q_mutex);
  556. mutex_lock(&hfi_msg_q_mutex);
  557. if (!g_hfi) {
  558. g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL);
  559. if (!g_hfi) {
  560. rc = -ENOMEM;
  561. goto alloc_fail;
  562. }
  563. }
  564. if (g_hfi->hfi_state != HFI_DEINIT) {
  565. CAM_ERR(CAM_HFI, "hfi_init: invalid state");
  566. rc = -EINVAL;
  567. goto regions_fail;
  568. }
  569. memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
  570. g_hfi->hfi_state = HFI_DEINIT;
  571. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  572. qtbl_hdr = &qtbl->q_tbl_hdr;
  573. qtbl_hdr->qtbl_version = 0xFFFFFFFF;
  574. qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl);
  575. qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr);
  576. qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr);
  577. qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS;
  578. qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS;
  579. /* setup host-to-firmware command queue */
  580. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  581. cmd_q_hdr->qhdr_status = QHDR_ACTIVE;
  582. cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova;
  583. cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  584. cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  585. cmd_q_hdr->qhdr_pkt_drop_cnt = RESET;
  586. cmd_q_hdr->qhdr_read_idx = RESET;
  587. cmd_q_hdr->qhdr_write_idx = RESET;
  588. /* setup firmware-to-Host message queue */
  589. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  590. msg_q_hdr->qhdr_status = QHDR_ACTIVE;
  591. msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova;
  592. msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  593. msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  594. msg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  595. msg_q_hdr->qhdr_read_idx = RESET;
  596. msg_q_hdr->qhdr_write_idx = RESET;
  597. /* setup firmware-to-Host message queue */
  598. dbg_q_hdr = &qtbl->q_hdr[Q_DBG];
  599. dbg_q_hdr->qhdr_status = QHDR_ACTIVE;
  600. dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova;
  601. dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  602. dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  603. dbg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  604. dbg_q_hdr->qhdr_read_idx = RESET;
  605. dbg_q_hdr->qhdr_write_idx = RESET;
  606. sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva;
  607. sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES;
  608. switch (event_driven_mode) {
  609. case INTR_MODE:
  610. cmd_q_hdr->qhdr_type = Q_CMD;
  611. cmd_q_hdr->qhdr_rx_wm = SET;
  612. cmd_q_hdr->qhdr_tx_wm = SET;
  613. cmd_q_hdr->qhdr_rx_req = SET;
  614. cmd_q_hdr->qhdr_tx_req = RESET;
  615. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  616. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  617. msg_q_hdr->qhdr_type = Q_MSG;
  618. msg_q_hdr->qhdr_rx_wm = SET;
  619. msg_q_hdr->qhdr_tx_wm = SET;
  620. msg_q_hdr->qhdr_rx_req = SET;
  621. msg_q_hdr->qhdr_tx_req = RESET;
  622. msg_q_hdr->qhdr_rx_irq_status = RESET;
  623. msg_q_hdr->qhdr_tx_irq_status = RESET;
  624. dbg_q_hdr->qhdr_type = Q_DBG;
  625. dbg_q_hdr->qhdr_rx_wm = SET;
  626. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  627. dbg_q_hdr->qhdr_rx_req = RESET;
  628. dbg_q_hdr->qhdr_tx_req = RESET;
  629. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  630. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  631. break;
  632. case POLL_MODE:
  633. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 |
  634. RX_EVENT_POLL_MODE_2;
  635. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 |
  636. RX_EVENT_POLL_MODE_2;
  637. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 |
  638. RX_EVENT_POLL_MODE_2;
  639. break;
  640. case WM_MODE:
  641. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 |
  642. RX_EVENT_DRIVEN_MODE_2;
  643. cmd_q_hdr->qhdr_rx_wm = SET;
  644. cmd_q_hdr->qhdr_tx_wm = SET;
  645. cmd_q_hdr->qhdr_rx_req = RESET;
  646. cmd_q_hdr->qhdr_tx_req = SET;
  647. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  648. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  649. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 |
  650. RX_EVENT_DRIVEN_MODE_2;
  651. msg_q_hdr->qhdr_rx_wm = SET;
  652. msg_q_hdr->qhdr_tx_wm = SET;
  653. msg_q_hdr->qhdr_rx_req = SET;
  654. msg_q_hdr->qhdr_tx_req = RESET;
  655. msg_q_hdr->qhdr_rx_irq_status = RESET;
  656. msg_q_hdr->qhdr_tx_irq_status = RESET;
  657. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 |
  658. RX_EVENT_DRIVEN_MODE_2;
  659. dbg_q_hdr->qhdr_rx_wm = SET;
  660. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  661. dbg_q_hdr->qhdr_rx_req = RESET;
  662. dbg_q_hdr->qhdr_tx_req = RESET;
  663. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  664. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  665. break;
  666. default:
  667. CAM_ERR(CAM_HFI, "Invalid event driven mode :%u",
  668. event_driven_mode);
  669. break;
  670. }
  671. g_hfi->ops = *hfi_ops;
  672. g_hfi->priv = priv;
  673. icp_base = hfi_iface_addr(g_hfi);
  674. if (!icp_base) {
  675. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  676. rc = -EINVAL;
  677. goto regions_fail;
  678. }
  679. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova,
  680. icp_base + HFI_REG_QTBL_PTR);
  681. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  682. icp_base + HFI_REG_SFR_PTR);
  683. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  684. icp_base + HFI_REG_SHARED_MEM_PTR);
  685. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  686. icp_base + HFI_REG_SHARED_MEM_SIZE);
  687. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  688. icp_base + HFI_REG_UNCACHED_HEAP_PTR);
  689. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  690. icp_base + HFI_REG_UNCACHED_HEAP_SIZE);
  691. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
  692. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  693. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  694. icp_base + HFI_REG_QDSS_IOVA);
  695. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  696. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  697. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  698. icp_base + HFI_REG_IO_REGION_IOVA);
  699. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  700. icp_base + HFI_REG_IO_REGION_SIZE);
  701. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  702. icp_base + HFI_REG_IO2_REGION_IOVA);
  703. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  704. icp_base + HFI_REG_IO2_REGION_SIZE);
  705. CAM_INFO(CAM_HFI, "Init IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  706. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  707. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  708. if (readl_poll_timeout(icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE,
  709. status, status == ICP_INIT_RESP_SUCCESS,
  710. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US)) {
  711. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  712. status);
  713. rc = -ETIMEDOUT;
  714. goto regions_fail;
  715. }
  716. CAM_DBG(CAM_HFI, "ICP fw version: 0x%x",
  717. cam_io_r(icp_base + HFI_REG_FW_VERSION));
  718. g_hfi->hfi_state = HFI_READY;
  719. g_hfi->cmd_q_state = true;
  720. g_hfi->msg_q_state = true;
  721. hfi_irq_enable(g_hfi);
  722. mutex_unlock(&hfi_cmd_q_mutex);
  723. mutex_unlock(&hfi_msg_q_mutex);
  724. return rc;
  725. regions_fail:
  726. kfree(g_hfi);
  727. g_hfi = NULL;
  728. alloc_fail:
  729. mutex_unlock(&hfi_cmd_q_mutex);
  730. mutex_unlock(&hfi_msg_q_mutex);
  731. return rc;
  732. }
  733. void cam_hfi_deinit(void)
  734. {
  735. mutex_lock(&hfi_cmd_q_mutex);
  736. mutex_lock(&hfi_msg_q_mutex);
  737. if (!g_hfi) {
  738. CAM_ERR(CAM_HFI, "hfi path not established yet");
  739. goto err;
  740. }
  741. g_hfi->cmd_q_state = false;
  742. g_hfi->msg_q_state = false;
  743. cam_free_clear((void *)g_hfi);
  744. g_hfi = NULL;
  745. err:
  746. mutex_unlock(&hfi_cmd_q_mutex);
  747. mutex_unlock(&hfi_msg_q_mutex);
  748. }