wcd938x.c 123 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. WCD_SUPPLIES_LPM_MODE,
  65. };
  66. enum {
  67. ADC_MODE_INVALID = 0,
  68. ADC_MODE_HIFI,
  69. ADC_MODE_LO_HIF,
  70. ADC_MODE_NORMAL,
  71. ADC_MODE_LP,
  72. ADC_MODE_ULP1,
  73. ADC_MODE_ULP2,
  74. };
  75. static u8 tx_mode_bit[] = {
  76. [ADC_MODE_INVALID] = 0x00,
  77. [ADC_MODE_HIFI] = 0x01,
  78. [ADC_MODE_LO_HIF] = 0x02,
  79. [ADC_MODE_NORMAL] = 0x04,
  80. [ADC_MODE_LP] = 0x08,
  81. [ADC_MODE_ULP1] = 0x10,
  82. [ADC_MODE_ULP2] = 0x20,
  83. };
  84. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  85. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  86. static int wcd938x_handle_post_irq(void *data);
  87. static int wcd938x_reset(struct device *dev);
  88. static int wcd938x_reset_low(struct device *dev);
  89. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  90. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  91. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  92. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  93. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  94. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  110. };
  111. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  112. .name = "wcd938x",
  113. .irqs = wcd938x_irqs,
  114. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  115. .num_regs = 3,
  116. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  117. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  118. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  119. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  120. .use_ack = 1,
  121. .runtime_pm = false,
  122. .handle_post_irq = wcd938x_handle_post_irq,
  123. .irq_drv_data = NULL,
  124. };
  125. static int wcd938x_handle_post_irq(void *data)
  126. {
  127. struct wcd938x_priv *wcd938x = data;
  128. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  129. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  130. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  131. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  132. wcd938x->tx_swr_dev->slave_irq_pending =
  133. ((sts1 || sts2 || sts3) ? true : false);
  134. return IRQ_HANDLED;
  135. }
  136. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  137. {
  138. int ret = 0;
  139. int bank = 0;
  140. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  141. if (ret)
  142. return -EINVAL;
  143. return ((bank & 0x40) ? 1: 0);
  144. }
  145. static int wcd938x_get_clk_rate(int mode)
  146. {
  147. int rate;
  148. switch (mode) {
  149. case ADC_MODE_ULP2:
  150. rate = SWR_CLK_RATE_0P6MHZ;
  151. break;
  152. case ADC_MODE_ULP1:
  153. rate = SWR_CLK_RATE_1P2MHZ;
  154. break;
  155. case ADC_MODE_LP:
  156. rate = SWR_CLK_RATE_4P8MHZ;
  157. break;
  158. case ADC_MODE_NORMAL:
  159. case ADC_MODE_LO_HIF:
  160. case ADC_MODE_HIFI:
  161. case ADC_MODE_INVALID:
  162. default:
  163. rate = SWR_CLK_RATE_9P6MHZ;
  164. break;
  165. }
  166. return rate;
  167. }
  168. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  169. int rate, int bank)
  170. {
  171. u8 mask = (bank ? 0xF0 : 0x0F);
  172. u8 val = 0;
  173. switch (rate) {
  174. case SWR_CLK_RATE_0P6MHZ:
  175. val = (bank ? 0x60 : 0x06);
  176. break;
  177. case SWR_CLK_RATE_1P2MHZ:
  178. val = (bank ? 0x50 : 0x05);
  179. break;
  180. case SWR_CLK_RATE_2P4MHZ:
  181. val = (bank ? 0x30 : 0x03);
  182. break;
  183. case SWR_CLK_RATE_4P8MHZ:
  184. val = (bank ? 0x10 : 0x01);
  185. break;
  186. case SWR_CLK_RATE_9P6MHZ:
  187. default:
  188. val = 0x00;
  189. break;
  190. }
  191. snd_soc_component_update_bits(component,
  192. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  193. mask, val);
  194. return 0;
  195. }
  196. static int wcd938x_init_reg(struct snd_soc_component *component)
  197. {
  198. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  199. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  200. /* 1 msec delay as per HW requirement */
  201. usleep_range(1000, 1010);
  202. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  203. /* 1 msec delay as per HW requirement */
  204. usleep_range(1000, 1010);
  205. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  206. 0x10, 0x00);
  207. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  208. 0xF0, 0x80);
  209. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  210. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  211. /* 10 msec delay as per HW requirement */
  212. usleep_range(10000, 10010);
  213. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  214. snd_soc_component_update_bits(component,
  215. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  216. 0xF0, 0x00);
  217. snd_soc_component_update_bits(component,
  218. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  219. 0x1F, 0x15);
  220. snd_soc_component_update_bits(component,
  221. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  222. 0x1F, 0x15);
  223. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  224. 0xC0, 0x80);
  225. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  226. 0x02, 0x02);
  227. snd_soc_component_update_bits(component,
  228. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  229. 0xFF, 0x14);
  230. snd_soc_component_update_bits(component,
  231. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  232. 0x1F, 0x08);
  233. snd_soc_component_update_bits(component,
  234. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  235. snd_soc_component_update_bits(component,
  236. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  237. snd_soc_component_update_bits(component,
  238. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  239. snd_soc_component_update_bits(component,
  240. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  241. snd_soc_component_update_bits(component,
  242. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  253. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  254. ((snd_soc_component_read32(component,
  255. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  256. snd_soc_component_update_bits(component,
  257. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  258. return 0;
  259. }
  260. static int wcd938x_set_port_params(struct snd_soc_component *component,
  261. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  262. u8 *ch_mask, u32 *ch_rate,
  263. u8 *port_type, u8 path)
  264. {
  265. int i, j;
  266. u8 num_ports = 0;
  267. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  268. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  269. switch (path) {
  270. case CODEC_RX:
  271. map = &wcd938x->rx_port_mapping;
  272. num_ports = wcd938x->num_rx_ports;
  273. break;
  274. case CODEC_TX:
  275. map = &wcd938x->tx_port_mapping;
  276. num_ports = wcd938x->num_tx_ports;
  277. break;
  278. default:
  279. dev_err(component->dev, "%s Invalid path selected %u\n",
  280. __func__, path);
  281. return -EINVAL;
  282. }
  283. for (i = 0; i <= num_ports; i++) {
  284. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  285. if ((*map)[i][j].slave_port_type == slv_prt_type)
  286. goto found;
  287. }
  288. }
  289. found:
  290. if (i > num_ports || j == MAX_CH_PER_PORT) {
  291. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  292. __func__, slv_prt_type);
  293. return -EINVAL;
  294. }
  295. *port_id = i;
  296. *num_ch = (*map)[i][j].num_ch;
  297. *ch_mask = (*map)[i][j].ch_mask;
  298. *ch_rate = (*map)[i][j].ch_rate;
  299. *port_type = (*map)[i][j].master_port_type;
  300. return 0;
  301. }
  302. static int wcd938x_parse_port_mapping(struct device *dev,
  303. char *prop, u8 path)
  304. {
  305. u32 *dt_array, map_size, map_length;
  306. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  307. u32 slave_port_type, master_port_type;
  308. u32 i, ch_iter = 0;
  309. int ret = 0;
  310. u8 *num_ports = NULL;
  311. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  312. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  313. switch (path) {
  314. case CODEC_RX:
  315. map = &wcd938x->rx_port_mapping;
  316. num_ports = &wcd938x->num_rx_ports;
  317. break;
  318. case CODEC_TX:
  319. map = &wcd938x->tx_port_mapping;
  320. num_ports = &wcd938x->num_tx_ports;
  321. break;
  322. default:
  323. dev_err(dev, "%s Invalid path selected %u\n",
  324. __func__, path);
  325. return -EINVAL;
  326. }
  327. if (!of_find_property(dev->of_node, prop,
  328. &map_size)) {
  329. dev_err(dev, "missing port mapping prop %s\n", prop);
  330. ret = -EINVAL;
  331. goto err_port_map;
  332. }
  333. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  334. dt_array = kzalloc(map_size, GFP_KERNEL);
  335. if (!dt_array) {
  336. ret = -ENOMEM;
  337. goto err_alloc;
  338. }
  339. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  340. NUM_SWRS_DT_PARAMS * map_length);
  341. if (ret) {
  342. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  343. __func__, prop);
  344. goto err_pdata_fail;
  345. }
  346. for (i = 0; i < map_length; i++) {
  347. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  348. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  349. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  350. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  351. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  352. if (port_num != old_port_num)
  353. ch_iter = 0;
  354. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  355. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  356. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  357. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  358. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  359. old_port_num = port_num;
  360. }
  361. *num_ports = port_num;
  362. kfree(dt_array);
  363. return 0;
  364. err_pdata_fail:
  365. kfree(dt_array);
  366. err_alloc:
  367. err_port_map:
  368. return ret;
  369. }
  370. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  371. u8 slv_port_type, int clk_rate,
  372. u8 enable)
  373. {
  374. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  375. u8 port_id, num_ch, ch_mask;
  376. u8 ch_type = 0;
  377. u32 ch_rate;
  378. int slave_ch_idx;
  379. u8 num_port = 1;
  380. int ret = 0;
  381. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  382. &num_ch, &ch_mask, &ch_rate,
  383. &ch_type, CODEC_TX);
  384. if (ret)
  385. return ret;
  386. if (clk_rate)
  387. ch_rate = clk_rate;
  388. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  389. if (slave_ch_idx != -EINVAL)
  390. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  391. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  392. __func__, slave_ch_idx, ch_type);
  393. if (enable)
  394. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  395. num_port, &ch_mask, &ch_rate,
  396. &num_ch, &ch_type);
  397. else
  398. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  399. num_port, &ch_mask, &ch_type);
  400. return ret;
  401. }
  402. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  403. u8 slv_port_type, u8 enable)
  404. {
  405. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  406. u8 port_id, num_ch, ch_mask, port_type;
  407. u32 ch_rate;
  408. u8 num_port = 1;
  409. int ret = 0;
  410. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  411. &num_ch, &ch_mask, &ch_rate,
  412. &port_type, CODEC_RX);
  413. if (ret)
  414. return ret;
  415. if (enable)
  416. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  417. num_port, &ch_mask, &ch_rate,
  418. &num_ch, &port_type);
  419. else
  420. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  421. num_port, &ch_mask, &port_type);
  422. return ret;
  423. }
  424. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  425. {
  426. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  427. if (wcd938x->rx_clk_cnt == 0) {
  428. snd_soc_component_update_bits(component,
  429. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  430. snd_soc_component_update_bits(component,
  431. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  432. snd_soc_component_update_bits(component,
  433. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  434. snd_soc_component_update_bits(component,
  435. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  436. snd_soc_component_update_bits(component,
  437. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  440. snd_soc_component_update_bits(component,
  441. WCD938X_AUX_AUXPA, 0x10, 0x10);
  442. }
  443. wcd938x->rx_clk_cnt++;
  444. return 0;
  445. }
  446. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  447. {
  448. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  449. wcd938x->rx_clk_cnt--;
  450. if (wcd938x->rx_clk_cnt == 0) {
  451. snd_soc_component_update_bits(component,
  452. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  453. snd_soc_component_update_bits(component,
  454. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  455. snd_soc_component_update_bits(component,
  456. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  457. snd_soc_component_update_bits(component,
  458. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  459. snd_soc_component_update_bits(component,
  460. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  461. }
  462. return 0;
  463. }
  464. /*
  465. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  466. * @component: handle to snd_soc_component *
  467. *
  468. * return wcd938x_mbhc handle or error code in case of failure
  469. */
  470. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  471. {
  472. struct wcd938x_priv *wcd938x;
  473. if (!component) {
  474. pr_err("%s: Invalid params, NULL component\n", __func__);
  475. return NULL;
  476. }
  477. wcd938x = snd_soc_component_get_drvdata(component);
  478. if (!wcd938x) {
  479. pr_err("%s: wcd938x is NULL\n", __func__);
  480. return NULL;
  481. }
  482. return wcd938x->mbhc;
  483. }
  484. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  485. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  486. struct snd_kcontrol *kcontrol,
  487. int event)
  488. {
  489. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  490. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  491. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  492. w->name, event);
  493. switch (event) {
  494. case SND_SOC_DAPM_PRE_PMU:
  495. wcd938x_rx_clk_enable(component);
  496. snd_soc_component_update_bits(component,
  497. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  498. snd_soc_component_update_bits(component,
  499. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  500. snd_soc_component_update_bits(component,
  501. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  502. break;
  503. case SND_SOC_DAPM_POST_PMU:
  504. snd_soc_component_update_bits(component,
  505. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  506. if (wcd938x->comp1_enable) {
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  509. /* 5msec compander delay as per HW requirement */
  510. if (!wcd938x->comp2_enable ||
  511. (snd_soc_component_read32(component,
  512. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  513. usleep_range(5000, 5010);
  514. snd_soc_component_update_bits(component,
  515. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  516. } else {
  517. snd_soc_component_update_bits(component,
  518. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  519. 0x02, 0x00);
  520. snd_soc_component_update_bits(component,
  521. WCD938X_HPH_L_EN, 0x20, 0x20);
  522. }
  523. break;
  524. case SND_SOC_DAPM_POST_PMD:
  525. snd_soc_component_update_bits(component,
  526. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  527. 0x0F, 0x01);
  528. break;
  529. }
  530. return 0;
  531. }
  532. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  533. struct snd_kcontrol *kcontrol,
  534. int event)
  535. {
  536. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  537. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  538. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  539. w->name, event);
  540. switch (event) {
  541. case SND_SOC_DAPM_PRE_PMU:
  542. wcd938x_rx_clk_enable(component);
  543. snd_soc_component_update_bits(component,
  544. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  545. snd_soc_component_update_bits(component,
  546. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  547. snd_soc_component_update_bits(component,
  548. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  549. break;
  550. case SND_SOC_DAPM_POST_PMU:
  551. snd_soc_component_update_bits(component,
  552. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  553. if (wcd938x->comp2_enable) {
  554. snd_soc_component_update_bits(component,
  555. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  556. /* 5msec compander delay as per HW requirement */
  557. if (!wcd938x->comp1_enable ||
  558. (snd_soc_component_read32(component,
  559. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  560. usleep_range(5000, 5010);
  561. snd_soc_component_update_bits(component,
  562. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  563. } else {
  564. snd_soc_component_update_bits(component,
  565. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  566. 0x01, 0x00);
  567. snd_soc_component_update_bits(component,
  568. WCD938X_HPH_R_EN, 0x20, 0x20);
  569. }
  570. break;
  571. case SND_SOC_DAPM_POST_PMD:
  572. snd_soc_component_update_bits(component,
  573. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  574. 0x0F, 0x01);
  575. break;
  576. }
  577. return 0;
  578. }
  579. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  580. struct snd_kcontrol *kcontrol,
  581. int event)
  582. {
  583. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  584. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  585. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  586. w->name, event);
  587. switch (event) {
  588. case SND_SOC_DAPM_PRE_PMU:
  589. wcd938x_rx_clk_enable(component);
  590. wcd938x->ear_rx_path =
  591. snd_soc_component_read32(
  592. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  593. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  594. snd_soc_component_update_bits(component,
  595. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  596. snd_soc_component_update_bits(component,
  597. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  598. snd_soc_component_update_bits(component,
  599. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  600. snd_soc_component_update_bits(component,
  601. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  602. } else {
  603. snd_soc_component_update_bits(component,
  604. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  605. snd_soc_component_update_bits(component,
  606. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  607. if (wcd938x->comp1_enable)
  608. snd_soc_component_update_bits(component,
  609. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  610. 0x02, 0x02);
  611. }
  612. /* 5 msec delay as per HW requirement */
  613. usleep_range(5000, 5010);
  614. if (wcd938x->flyback_cur_det_disable == 0)
  615. snd_soc_component_update_bits(component,
  616. WCD938X_FLYBACK_EN,
  617. 0x04, 0x00);
  618. wcd938x->flyback_cur_det_disable++;
  619. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  620. WCD_CLSH_EVENT_PRE_DAC,
  621. WCD_CLSH_STATE_EAR,
  622. wcd938x->hph_mode);
  623. break;
  624. case SND_SOC_DAPM_POST_PMD:
  625. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  626. snd_soc_component_update_bits(component,
  627. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  628. snd_soc_component_update_bits(component,
  629. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  630. } else {
  631. snd_soc_component_update_bits(component,
  632. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  633. snd_soc_component_update_bits(component,
  634. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  635. if (wcd938x->comp1_enable)
  636. snd_soc_component_update_bits(component,
  637. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  638. 0x02, 0x00);
  639. }
  640. snd_soc_component_update_bits(component,
  641. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  642. snd_soc_component_update_bits(component,
  643. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  644. break;
  645. };
  646. return 0;
  647. }
  648. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  649. struct snd_kcontrol *kcontrol,
  650. int event)
  651. {
  652. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  653. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  654. int ret = 0;
  655. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  656. w->name, event);
  657. switch (event) {
  658. case SND_SOC_DAPM_PRE_PMU:
  659. wcd938x_rx_clk_enable(component);
  660. snd_soc_component_update_bits(component,
  661. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  662. snd_soc_component_update_bits(component,
  663. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  664. snd_soc_component_update_bits(component,
  665. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  666. if (wcd938x->flyback_cur_det_disable == 0)
  667. snd_soc_component_update_bits(component,
  668. WCD938X_FLYBACK_EN,
  669. 0x04, 0x00);
  670. wcd938x->flyback_cur_det_disable++;
  671. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  672. WCD_CLSH_EVENT_PRE_DAC,
  673. WCD_CLSH_STATE_AUX,
  674. wcd938x->hph_mode);
  675. break;
  676. case SND_SOC_DAPM_POST_PMD:
  677. snd_soc_component_update_bits(component,
  678. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  679. break;
  680. };
  681. return ret;
  682. }
  683. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  684. struct snd_kcontrol *kcontrol,
  685. int event)
  686. {
  687. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  688. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  689. int ret = 0;
  690. int hph_mode = wcd938x->hph_mode;
  691. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  692. w->name, event);
  693. switch (event) {
  694. case SND_SOC_DAPM_PRE_PMU:
  695. if (wcd938x->ldoh)
  696. snd_soc_component_update_bits(component,
  697. WCD938X_LDOH_MODE,
  698. 0x80, 0x80);
  699. if (wcd938x->update_wcd_event)
  700. wcd938x->update_wcd_event(wcd938x->handle,
  701. WCD_BOLERO_EVT_RX_MUTE,
  702. (WCD_RX2 << 0x10 | 0x1));
  703. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  704. wcd938x->rx_swr_dev->dev_num,
  705. true);
  706. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  707. WCD_CLSH_EVENT_PRE_DAC,
  708. WCD_CLSH_STATE_HPHR,
  709. hph_mode);
  710. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  711. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  712. hph_mode == CLS_H_ULP) {
  713. snd_soc_component_update_bits(component,
  714. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  715. }
  716. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  717. 0x10, 0x10);
  718. wcd_clsh_set_hph_mode(component, hph_mode);
  719. /* 100 usec delay as per HW requirement */
  720. usleep_range(100, 110);
  721. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  722. snd_soc_component_update_bits(component,
  723. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  724. break;
  725. case SND_SOC_DAPM_POST_PMU:
  726. /*
  727. * 7ms sleep is required if compander is enabled as per
  728. * HW requirement. If compander is disabled, then
  729. * 20ms delay is required.
  730. */
  731. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  732. if (!wcd938x->comp2_enable)
  733. usleep_range(20000, 20100);
  734. else
  735. usleep_range(7000, 7100);
  736. if (hph_mode == CLS_H_LP ||
  737. hph_mode == CLS_H_LOHIFI ||
  738. hph_mode == CLS_H_ULP)
  739. snd_soc_component_update_bits(component,
  740. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  741. 0x00);
  742. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  743. }
  744. snd_soc_component_update_bits(component,
  745. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  746. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  747. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  748. snd_soc_component_update_bits(component,
  749. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  750. if (wcd938x->update_wcd_event)
  751. wcd938x->update_wcd_event(wcd938x->handle,
  752. WCD_BOLERO_EVT_RX_MUTE,
  753. (WCD_RX2 << 0x10));
  754. wcd_enable_irq(&wcd938x->irq_info,
  755. WCD938X_IRQ_HPHR_PDM_WD_INT);
  756. break;
  757. case SND_SOC_DAPM_PRE_PMD:
  758. if (wcd938x->update_wcd_event)
  759. wcd938x->update_wcd_event(wcd938x->handle,
  760. WCD_BOLERO_EVT_RX_MUTE,
  761. (WCD_RX2 << 0x10 | 0x1));
  762. wcd_disable_irq(&wcd938x->irq_info,
  763. WCD938X_IRQ_HPHR_PDM_WD_INT);
  764. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  765. wcd938x->update_wcd_event(wcd938x->handle,
  766. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  767. (WCD_RX2 << 0x10));
  768. /*
  769. * 7ms sleep is required if compander is enabled as per
  770. * HW requirement. If compander is disabled, then
  771. * 20ms delay is required.
  772. */
  773. if (!wcd938x->comp2_enable)
  774. usleep_range(20000, 20100);
  775. else
  776. usleep_range(7000, 7100);
  777. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  778. 0x40, 0x00);
  779. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  780. WCD_EVENT_PRE_HPHR_PA_OFF,
  781. &wcd938x->mbhc->wcd_mbhc);
  782. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  783. break;
  784. case SND_SOC_DAPM_POST_PMD:
  785. /*
  786. * 7ms sleep is required if compander is enabled as per
  787. * HW requirement. If compander is disabled, then
  788. * 20ms delay is required.
  789. */
  790. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  791. if (!wcd938x->comp2_enable)
  792. usleep_range(20000, 20100);
  793. else
  794. usleep_range(7000, 7100);
  795. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  796. }
  797. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  798. WCD_EVENT_POST_HPHR_PA_OFF,
  799. &wcd938x->mbhc->wcd_mbhc);
  800. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  801. 0x10, 0x00);
  802. snd_soc_component_update_bits(component,
  803. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  804. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  805. WCD_CLSH_EVENT_POST_PA,
  806. WCD_CLSH_STATE_HPHR,
  807. hph_mode);
  808. if (wcd938x->ldoh)
  809. snd_soc_component_update_bits(component,
  810. WCD938X_LDOH_MODE,
  811. 0x80, 0x00);
  812. break;
  813. };
  814. return ret;
  815. }
  816. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  817. struct snd_kcontrol *kcontrol,
  818. int event)
  819. {
  820. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  821. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  822. int ret = 0;
  823. int hph_mode = wcd938x->hph_mode;
  824. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  825. w->name, event);
  826. switch (event) {
  827. case SND_SOC_DAPM_PRE_PMU:
  828. if (wcd938x->ldoh)
  829. snd_soc_component_update_bits(component,
  830. WCD938X_LDOH_MODE,
  831. 0x80, 0x80);
  832. if (wcd938x->update_wcd_event)
  833. wcd938x->update_wcd_event(wcd938x->handle,
  834. WCD_BOLERO_EVT_RX_MUTE,
  835. (WCD_RX1 << 0x10 | 0x01));
  836. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  837. wcd938x->rx_swr_dev->dev_num,
  838. true);
  839. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  840. WCD_CLSH_EVENT_PRE_DAC,
  841. WCD_CLSH_STATE_HPHL,
  842. hph_mode);
  843. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  844. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  845. hph_mode == CLS_H_ULP) {
  846. snd_soc_component_update_bits(component,
  847. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  848. }
  849. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  850. 0x20, 0x20);
  851. wcd_clsh_set_hph_mode(component, hph_mode);
  852. /* 100 usec delay as per HW requirement */
  853. usleep_range(100, 110);
  854. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  855. snd_soc_component_update_bits(component,
  856. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  857. break;
  858. case SND_SOC_DAPM_POST_PMU:
  859. /*
  860. * 7ms sleep is required if compander is enabled as per
  861. * HW requirement. If compander is disabled, then
  862. * 20ms delay is required.
  863. */
  864. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  865. if (!wcd938x->comp1_enable)
  866. usleep_range(20000, 20100);
  867. else
  868. usleep_range(7000, 7100);
  869. if (hph_mode == CLS_H_LP ||
  870. hph_mode == CLS_H_LOHIFI ||
  871. hph_mode == CLS_H_ULP)
  872. snd_soc_component_update_bits(component,
  873. WCD938X_HPH_REFBUFF_LP_CTL,
  874. 0x01, 0x00);
  875. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  876. }
  877. snd_soc_component_update_bits(component,
  878. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  879. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  880. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  881. snd_soc_component_update_bits(component,
  882. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  883. if (wcd938x->update_wcd_event)
  884. wcd938x->update_wcd_event(wcd938x->handle,
  885. WCD_BOLERO_EVT_RX_MUTE,
  886. (WCD_RX1 << 0x10));
  887. wcd_enable_irq(&wcd938x->irq_info,
  888. WCD938X_IRQ_HPHL_PDM_WD_INT);
  889. break;
  890. case SND_SOC_DAPM_PRE_PMD:
  891. if (wcd938x->update_wcd_event)
  892. wcd938x->update_wcd_event(wcd938x->handle,
  893. WCD_BOLERO_EVT_RX_MUTE,
  894. (WCD_RX1 << 0x10 | 0x1));
  895. wcd_disable_irq(&wcd938x->irq_info,
  896. WCD938X_IRQ_HPHL_PDM_WD_INT);
  897. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  898. wcd938x->update_wcd_event(wcd938x->handle,
  899. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  900. (WCD_RX1 << 0x10));
  901. /*
  902. * 7ms sleep is required if compander is enabled as per
  903. * HW requirement. If compander is disabled, then
  904. * 20ms delay is required.
  905. */
  906. if (!wcd938x->comp1_enable)
  907. usleep_range(20000, 20100);
  908. else
  909. usleep_range(7000, 7100);
  910. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  911. 0x80, 0x00);
  912. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  913. WCD_EVENT_PRE_HPHL_PA_OFF,
  914. &wcd938x->mbhc->wcd_mbhc);
  915. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  916. break;
  917. case SND_SOC_DAPM_POST_PMD:
  918. /*
  919. * 7ms sleep is required if compander is enabled as per
  920. * HW requirement. If compander is disabled, then
  921. * 20ms delay is required.
  922. */
  923. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  924. if (!wcd938x->comp1_enable)
  925. usleep_range(21000, 21100);
  926. else
  927. usleep_range(7000, 7100);
  928. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  929. }
  930. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  931. WCD_EVENT_POST_HPHL_PA_OFF,
  932. &wcd938x->mbhc->wcd_mbhc);
  933. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  934. 0x20, 0x00);
  935. snd_soc_component_update_bits(component,
  936. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  937. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  938. WCD_CLSH_EVENT_POST_PA,
  939. WCD_CLSH_STATE_HPHL,
  940. hph_mode);
  941. if (wcd938x->ldoh)
  942. snd_soc_component_update_bits(component,
  943. WCD938X_LDOH_MODE,
  944. 0x80, 0x00);
  945. break;
  946. };
  947. return ret;
  948. }
  949. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  950. struct snd_kcontrol *kcontrol,
  951. int event)
  952. {
  953. struct snd_soc_component *component =
  954. snd_soc_dapm_to_component(w->dapm);
  955. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  956. int hph_mode = wcd938x->hph_mode;
  957. int ret = 0;
  958. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  959. w->name, event);
  960. switch (event) {
  961. case SND_SOC_DAPM_PRE_PMU:
  962. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  963. wcd938x->rx_swr_dev->dev_num,
  964. true);
  965. snd_soc_component_update_bits(component,
  966. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  967. break;
  968. case SND_SOC_DAPM_POST_PMU:
  969. /* 1 msec delay as per HW requirement */
  970. usleep_range(1000, 1010);
  971. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  972. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  973. snd_soc_component_update_bits(component,
  974. WCD938X_ANA_RX_SUPPLIES,
  975. 0x02, 0x02);
  976. if (wcd938x->update_wcd_event)
  977. wcd938x->update_wcd_event(wcd938x->handle,
  978. WCD_BOLERO_EVT_RX_MUTE,
  979. (WCD_RX3 << 0x10));
  980. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  981. break;
  982. case SND_SOC_DAPM_PRE_PMD:
  983. wcd_disable_irq(&wcd938x->irq_info,
  984. WCD938X_IRQ_AUX_PDM_WD_INT);
  985. if (wcd938x->update_wcd_event)
  986. wcd938x->update_wcd_event(wcd938x->handle,
  987. WCD_BOLERO_EVT_RX_MUTE,
  988. (WCD_RX3 << 0x10 | 0x1));
  989. break;
  990. case SND_SOC_DAPM_POST_PMD:
  991. /* 1 msec delay as per HW requirement */
  992. usleep_range(1000, 1010);
  993. snd_soc_component_update_bits(component,
  994. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  995. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  996. WCD_CLSH_EVENT_POST_PA,
  997. WCD_CLSH_STATE_AUX,
  998. hph_mode);
  999. wcd938x->flyback_cur_det_disable--;
  1000. if (wcd938x->flyback_cur_det_disable == 0)
  1001. snd_soc_component_update_bits(component,
  1002. WCD938X_FLYBACK_EN,
  1003. 0x04, 0x04);
  1004. break;
  1005. };
  1006. return ret;
  1007. }
  1008. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1009. struct snd_kcontrol *kcontrol,
  1010. int event)
  1011. {
  1012. struct snd_soc_component *component =
  1013. snd_soc_dapm_to_component(w->dapm);
  1014. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1015. int hph_mode = wcd938x->hph_mode;
  1016. int ret = 0;
  1017. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1018. w->name, event);
  1019. switch (event) {
  1020. case SND_SOC_DAPM_PRE_PMU:
  1021. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1022. wcd938x->rx_swr_dev->dev_num,
  1023. true);
  1024. /*
  1025. * Enable watchdog interrupt for HPHL or AUX
  1026. * depending on mux value
  1027. */
  1028. wcd938x->ear_rx_path =
  1029. snd_soc_component_read32(
  1030. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1031. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1032. snd_soc_component_update_bits(component,
  1033. WCD938X_DIGITAL_PDM_WD_CTL2,
  1034. 0x01, 0x01);
  1035. else
  1036. snd_soc_component_update_bits(component,
  1037. WCD938X_DIGITAL_PDM_WD_CTL0,
  1038. 0x07, 0x03);
  1039. if (!wcd938x->comp1_enable)
  1040. snd_soc_component_update_bits(component,
  1041. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1042. break;
  1043. case SND_SOC_DAPM_POST_PMU:
  1044. /* 6 msec delay as per HW requirement */
  1045. usleep_range(6000, 6010);
  1046. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1047. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1048. snd_soc_component_update_bits(component,
  1049. WCD938X_ANA_RX_SUPPLIES,
  1050. 0x02, 0x02);
  1051. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1052. if (wcd938x->update_wcd_event)
  1053. wcd938x->update_wcd_event(wcd938x->handle,
  1054. WCD_BOLERO_EVT_RX_MUTE,
  1055. (WCD_RX3 << 0x10));
  1056. wcd_enable_irq(&wcd938x->irq_info,
  1057. WCD938X_IRQ_AUX_PDM_WD_INT);
  1058. } else {
  1059. if (wcd938x->update_wcd_event)
  1060. wcd938x->update_wcd_event(wcd938x->handle,
  1061. WCD_BOLERO_EVT_RX_MUTE,
  1062. (WCD_RX1 << 0x10));
  1063. wcd_enable_irq(&wcd938x->irq_info,
  1064. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1065. }
  1066. break;
  1067. case SND_SOC_DAPM_PRE_PMD:
  1068. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1069. wcd_disable_irq(&wcd938x->irq_info,
  1070. WCD938X_IRQ_AUX_PDM_WD_INT);
  1071. if (wcd938x->update_wcd_event)
  1072. wcd938x->update_wcd_event(wcd938x->handle,
  1073. WCD_BOLERO_EVT_RX_MUTE,
  1074. (WCD_RX3 << 0x10 | 0x1));
  1075. } else {
  1076. wcd_disable_irq(&wcd938x->irq_info,
  1077. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1078. if (wcd938x->update_wcd_event)
  1079. wcd938x->update_wcd_event(wcd938x->handle,
  1080. WCD_BOLERO_EVT_RX_MUTE,
  1081. (WCD_RX1 << 0x10 | 0x1));
  1082. }
  1083. break;
  1084. case SND_SOC_DAPM_POST_PMD:
  1085. if (!wcd938x->comp1_enable)
  1086. snd_soc_component_update_bits(component,
  1087. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1088. /* 7 msec delay as per HW requirement */
  1089. usleep_range(7000, 7010);
  1090. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1091. snd_soc_component_update_bits(component,
  1092. WCD938X_DIGITAL_PDM_WD_CTL2,
  1093. 0x01, 0x00);
  1094. else
  1095. snd_soc_component_update_bits(component,
  1096. WCD938X_DIGITAL_PDM_WD_CTL0,
  1097. 0x07, 0x00);
  1098. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1099. WCD_CLSH_EVENT_POST_PA,
  1100. WCD_CLSH_STATE_EAR,
  1101. hph_mode);
  1102. wcd938x->flyback_cur_det_disable--;
  1103. if (wcd938x->flyback_cur_det_disable == 0)
  1104. snd_soc_component_update_bits(component,
  1105. WCD938X_FLYBACK_EN,
  1106. 0x04, 0x04);
  1107. break;
  1108. };
  1109. return ret;
  1110. }
  1111. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1112. struct snd_kcontrol *kcontrol,
  1113. int event)
  1114. {
  1115. struct snd_soc_component *component =
  1116. snd_soc_dapm_to_component(w->dapm);
  1117. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1118. int mode = wcd938x->hph_mode;
  1119. int ret = 0;
  1120. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1121. w->name, event);
  1122. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1123. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1124. wcd938x_rx_connect_port(component, CLSH,
  1125. SND_SOC_DAPM_EVENT_ON(event));
  1126. }
  1127. if (SND_SOC_DAPM_EVENT_OFF(event))
  1128. ret = swr_slvdev_datapath_control(
  1129. wcd938x->rx_swr_dev,
  1130. wcd938x->rx_swr_dev->dev_num,
  1131. false);
  1132. return ret;
  1133. }
  1134. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1135. struct snd_kcontrol *kcontrol,
  1136. int event)
  1137. {
  1138. struct snd_soc_component *component =
  1139. snd_soc_dapm_to_component(w->dapm);
  1140. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1141. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1142. w->name, event);
  1143. switch (event) {
  1144. case SND_SOC_DAPM_PRE_PMU:
  1145. wcd938x_rx_connect_port(component, HPH_L, true);
  1146. if (wcd938x->comp1_enable)
  1147. wcd938x_rx_connect_port(component, COMP_L, true);
  1148. break;
  1149. case SND_SOC_DAPM_POST_PMD:
  1150. wcd938x_rx_connect_port(component, HPH_L, false);
  1151. if (wcd938x->comp1_enable)
  1152. wcd938x_rx_connect_port(component, COMP_L, false);
  1153. wcd938x_rx_clk_disable(component);
  1154. snd_soc_component_update_bits(component,
  1155. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1156. 0x01, 0x00);
  1157. break;
  1158. };
  1159. return 0;
  1160. }
  1161. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1162. struct snd_kcontrol *kcontrol, int event)
  1163. {
  1164. struct snd_soc_component *component =
  1165. snd_soc_dapm_to_component(w->dapm);
  1166. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1167. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1168. w->name, event);
  1169. switch (event) {
  1170. case SND_SOC_DAPM_PRE_PMU:
  1171. wcd938x_rx_connect_port(component, HPH_R, true);
  1172. if (wcd938x->comp2_enable)
  1173. wcd938x_rx_connect_port(component, COMP_R, true);
  1174. break;
  1175. case SND_SOC_DAPM_POST_PMD:
  1176. wcd938x_rx_connect_port(component, HPH_R, false);
  1177. if (wcd938x->comp2_enable)
  1178. wcd938x_rx_connect_port(component, COMP_R, false);
  1179. wcd938x_rx_clk_disable(component);
  1180. snd_soc_component_update_bits(component,
  1181. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1182. 0x02, 0x00);
  1183. break;
  1184. };
  1185. return 0;
  1186. }
  1187. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1188. struct snd_kcontrol *kcontrol,
  1189. int event)
  1190. {
  1191. struct snd_soc_component *component =
  1192. snd_soc_dapm_to_component(w->dapm);
  1193. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1194. w->name, event);
  1195. switch (event) {
  1196. case SND_SOC_DAPM_PRE_PMU:
  1197. wcd938x_rx_connect_port(component, LO, true);
  1198. break;
  1199. case SND_SOC_DAPM_POST_PMD:
  1200. wcd938x_rx_connect_port(component, LO, false);
  1201. /* 6 msec delay as per HW requirement */
  1202. usleep_range(6000, 6010);
  1203. wcd938x_rx_clk_disable(component);
  1204. snd_soc_component_update_bits(component,
  1205. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1206. break;
  1207. }
  1208. return 0;
  1209. }
  1210. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1211. struct snd_kcontrol *kcontrol,
  1212. int event)
  1213. {
  1214. struct snd_soc_component *component =
  1215. snd_soc_dapm_to_component(w->dapm);
  1216. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1217. u16 dmic_clk_reg, dmic_clk_en_reg;
  1218. s32 *dmic_clk_cnt;
  1219. u8 dmic_ctl_shift = 0;
  1220. u8 dmic_clk_shift = 0;
  1221. u8 dmic_clk_mask = 0;
  1222. u16 dmic2_left_en = 0;
  1223. int ret = 0;
  1224. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1225. w->name, event);
  1226. switch (w->shift) {
  1227. case 0:
  1228. case 1:
  1229. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1230. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1231. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1232. dmic_clk_mask = 0x0F;
  1233. dmic_clk_shift = 0x00;
  1234. dmic_ctl_shift = 0x00;
  1235. break;
  1236. case 2:
  1237. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1238. case 3:
  1239. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1240. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1241. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1242. dmic_clk_mask = 0xF0;
  1243. dmic_clk_shift = 0x04;
  1244. dmic_ctl_shift = 0x01;
  1245. break;
  1246. case 4:
  1247. case 5:
  1248. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1249. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1250. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1251. dmic_clk_mask = 0x0F;
  1252. dmic_clk_shift = 0x00;
  1253. dmic_ctl_shift = 0x02;
  1254. break;
  1255. case 6:
  1256. case 7:
  1257. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1258. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1259. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1260. dmic_clk_mask = 0xF0;
  1261. dmic_clk_shift = 0x04;
  1262. dmic_ctl_shift = 0x03;
  1263. break;
  1264. default:
  1265. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1266. __func__);
  1267. return -EINVAL;
  1268. };
  1269. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1270. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1271. switch (event) {
  1272. case SND_SOC_DAPM_PRE_PMU:
  1273. snd_soc_component_update_bits(component,
  1274. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1275. (0x01 << dmic_ctl_shift), 0x00);
  1276. /* 250us sleep as per HW requirement */
  1277. usleep_range(250, 260);
  1278. if (dmic2_left_en)
  1279. snd_soc_component_update_bits(component,
  1280. dmic2_left_en, 0x80, 0x80);
  1281. /* Setting DMIC clock rate to 2.4MHz */
  1282. snd_soc_component_update_bits(component,
  1283. dmic_clk_reg, dmic_clk_mask,
  1284. (0x03 << dmic_clk_shift));
  1285. snd_soc_component_update_bits(component,
  1286. dmic_clk_en_reg, 0x08, 0x08);
  1287. /* enable clock scaling */
  1288. snd_soc_component_update_bits(component,
  1289. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1290. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1291. wcd938x->tx_swr_dev->dev_num,
  1292. true);
  1293. break;
  1294. case SND_SOC_DAPM_POST_PMD:
  1295. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1296. wcd938x->tx_swr_dev->dev_num,
  1297. false);
  1298. snd_soc_component_update_bits(component,
  1299. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1300. (0x01 << dmic_ctl_shift),
  1301. (0x01 << dmic_ctl_shift));
  1302. if (dmic2_left_en)
  1303. snd_soc_component_update_bits(component,
  1304. dmic2_left_en, 0x80, 0x00);
  1305. snd_soc_component_update_bits(component,
  1306. dmic_clk_en_reg, 0x08, 0x00);
  1307. break;
  1308. };
  1309. return ret;
  1310. }
  1311. /*
  1312. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1313. * @micb_mv: micbias in mv
  1314. *
  1315. * return register value converted
  1316. */
  1317. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1318. {
  1319. /* min micbias voltage is 1V and maximum is 2.85V */
  1320. if (micb_mv < 1000 || micb_mv > 2850) {
  1321. pr_err("%s: unsupported micbias voltage\n", __func__);
  1322. return -EINVAL;
  1323. }
  1324. return (micb_mv - 1000) / 50;
  1325. }
  1326. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1327. /*
  1328. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1329. * @component: handle to snd_soc_component *
  1330. * @req_volt: micbias voltage to be set
  1331. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1332. *
  1333. * return 0 if adjustment is success or error code in case of failure
  1334. */
  1335. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1336. int req_volt, int micb_num)
  1337. {
  1338. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1339. int cur_vout_ctl, req_vout_ctl;
  1340. int micb_reg, micb_val, micb_en;
  1341. int ret = 0;
  1342. switch (micb_num) {
  1343. case MIC_BIAS_1:
  1344. micb_reg = WCD938X_ANA_MICB1;
  1345. break;
  1346. case MIC_BIAS_2:
  1347. micb_reg = WCD938X_ANA_MICB2;
  1348. break;
  1349. case MIC_BIAS_3:
  1350. micb_reg = WCD938X_ANA_MICB3;
  1351. break;
  1352. case MIC_BIAS_4:
  1353. micb_reg = WCD938X_ANA_MICB4;
  1354. break;
  1355. default:
  1356. return -EINVAL;
  1357. }
  1358. mutex_lock(&wcd938x->micb_lock);
  1359. /*
  1360. * If requested micbias voltage is same as current micbias
  1361. * voltage, then just return. Otherwise, adjust voltage as
  1362. * per requested value. If micbias is already enabled, then
  1363. * to avoid slow micbias ramp-up or down enable pull-up
  1364. * momentarily, change the micbias value and then re-enable
  1365. * micbias.
  1366. */
  1367. micb_val = snd_soc_component_read32(component, micb_reg);
  1368. micb_en = (micb_val & 0xC0) >> 6;
  1369. cur_vout_ctl = micb_val & 0x3F;
  1370. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1371. if (req_vout_ctl < 0) {
  1372. ret = -EINVAL;
  1373. goto exit;
  1374. }
  1375. if (cur_vout_ctl == req_vout_ctl) {
  1376. ret = 0;
  1377. goto exit;
  1378. }
  1379. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1380. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1381. req_volt, micb_en);
  1382. if (micb_en == 0x1)
  1383. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1384. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1385. if (micb_en == 0x1) {
  1386. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1387. /*
  1388. * Add 2ms delay as per HW requirement after enabling
  1389. * micbias
  1390. */
  1391. usleep_range(2000, 2100);
  1392. }
  1393. exit:
  1394. mutex_unlock(&wcd938x->micb_lock);
  1395. return ret;
  1396. }
  1397. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1398. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1399. struct snd_kcontrol *kcontrol,
  1400. int event)
  1401. {
  1402. struct snd_soc_component *component =
  1403. snd_soc_dapm_to_component(w->dapm);
  1404. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1405. int ret = 0;
  1406. int bank = 0;
  1407. u8 mode = 0;
  1408. int i = 0;
  1409. int rate = 0;
  1410. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1411. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1412. switch (event) {
  1413. case SND_SOC_DAPM_PRE_PMU:
  1414. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1415. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1416. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1417. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1418. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1419. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1420. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1421. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1422. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1423. if (mode != 0) {
  1424. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1425. if (mode & (1 << i)) {
  1426. i++;
  1427. break;
  1428. }
  1429. }
  1430. }
  1431. rate = wcd938x_get_clk_rate(i);
  1432. wcd938x_set_swr_clk_rate(component, rate, bank);
  1433. }
  1434. if (w->shift == ADC2 && !(snd_soc_component_read32(component,
  1435. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1436. if (!wcd938x->bcs_dis)
  1437. wcd938x_tx_connect_port(component, MBHC,
  1438. SWR_CLK_RATE_4P8MHZ, true);
  1439. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1440. }
  1441. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1442. wcd938x_tx_connect_port(component, w->shift, rate,
  1443. true);
  1444. /* Copy clk settings to active bank */
  1445. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1446. } else {
  1447. wcd938x_tx_connect_port(component, w->shift,
  1448. SWR_CLK_RATE_2P4MHZ, true);
  1449. }
  1450. break;
  1451. case SND_SOC_DAPM_POST_PMD:
  1452. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1453. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1454. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1455. }
  1456. wcd938x_tx_connect_port(component, w->shift, 0, false);
  1457. if (w->shift == ADC2 &&
  1458. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1459. if (!wcd938x->bcs_dis)
  1460. wcd938x_tx_connect_port(component, MBHC, 0,
  1461. false);
  1462. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1463. }
  1464. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1465. wcd938x_set_swr_clk_rate(component, rate, bank);
  1466. break;
  1467. };
  1468. return ret;
  1469. }
  1470. static int wcd938x_get_adc_mode(int val)
  1471. {
  1472. int ret = 0;
  1473. switch (val) {
  1474. case ADC_MODE_INVALID:
  1475. ret = ADC_MODE_VAL_NORMAL;
  1476. break;
  1477. case ADC_MODE_HIFI:
  1478. ret = ADC_MODE_VAL_HIFI;
  1479. break;
  1480. case ADC_MODE_LO_HIF:
  1481. ret = ADC_MODE_VAL_LO_HIF;
  1482. break;
  1483. case ADC_MODE_NORMAL:
  1484. ret = ADC_MODE_VAL_NORMAL;
  1485. break;
  1486. case ADC_MODE_LP:
  1487. ret = ADC_MODE_VAL_LP;
  1488. break;
  1489. case ADC_MODE_ULP1:
  1490. ret = ADC_MODE_VAL_ULP1;
  1491. break;
  1492. case ADC_MODE_ULP2:
  1493. ret = ADC_MODE_VAL_ULP2;
  1494. break;
  1495. default:
  1496. ret = -EINVAL;
  1497. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1498. break;
  1499. }
  1500. return ret;
  1501. }
  1502. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1503. struct snd_kcontrol *kcontrol,
  1504. int event){
  1505. struct snd_soc_component *component =
  1506. snd_soc_dapm_to_component(w->dapm);
  1507. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1508. int clk_rate = 0, ret = 0;
  1509. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1510. w->name, event);
  1511. switch (event) {
  1512. case SND_SOC_DAPM_PRE_PMU:
  1513. snd_soc_component_update_bits(component,
  1514. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1515. snd_soc_component_update_bits(component,
  1516. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1517. set_bit(w->shift, &wcd938x->status_mask);
  1518. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1519. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1520. wcd938x->tx_swr_dev->dev_num,
  1521. true);
  1522. break;
  1523. case SND_SOC_DAPM_POST_PMD:
  1524. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1525. wcd938x->tx_swr_dev->dev_num,
  1526. false);
  1527. snd_soc_component_update_bits(component,
  1528. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1529. clear_bit(w->shift, &wcd938x->status_mask);
  1530. break;
  1531. };
  1532. return ret;
  1533. }
  1534. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1535. bool bcs_disable)
  1536. {
  1537. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1538. if (wcd938x->update_wcd_event) {
  1539. if (bcs_disable)
  1540. wcd938x->update_wcd_event(wcd938x->handle,
  1541. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1542. else
  1543. wcd938x->update_wcd_event(wcd938x->handle,
  1544. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1545. }
  1546. }
  1547. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1548. int channel, int mode)
  1549. {
  1550. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1551. int ret = 0;
  1552. switch (channel) {
  1553. case 0:
  1554. reg = WCD938X_ANA_TX_CH2;
  1555. mask = 0x40;
  1556. break;
  1557. case 1:
  1558. reg = WCD938X_ANA_TX_CH2;
  1559. mask = 0x20;
  1560. break;
  1561. case 2:
  1562. reg = WCD938X_ANA_TX_CH4;
  1563. mask = 0x40;
  1564. break;
  1565. case 3:
  1566. reg = WCD938X_ANA_TX_CH4;
  1567. mask = 0x20;
  1568. break;
  1569. default:
  1570. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1571. ret = -EINVAL;
  1572. break;
  1573. }
  1574. if (!mode)
  1575. val = 0x00;
  1576. else
  1577. val = mask;
  1578. if (!ret)
  1579. snd_soc_component_update_bits(component, reg, mask, val);
  1580. return ret;
  1581. }
  1582. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1583. struct snd_kcontrol *kcontrol, int event)
  1584. {
  1585. struct snd_soc_component *component =
  1586. snd_soc_dapm_to_component(w->dapm);
  1587. int mode;
  1588. int ret = 0;
  1589. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1590. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1591. w->name, event);
  1592. switch (event) {
  1593. case SND_SOC_DAPM_PRE_PMU:
  1594. snd_soc_component_update_bits(component,
  1595. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1596. snd_soc_component_update_bits(component,
  1597. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1598. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1599. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1600. if (mode < 0) {
  1601. dev_info(component->dev,
  1602. "%s: invalid mode, setting to normal mode\n",
  1603. __func__);
  1604. mode = ADC_MODE_VAL_NORMAL;
  1605. }
  1606. switch (w->shift) {
  1607. case 0:
  1608. snd_soc_component_update_bits(component,
  1609. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1610. mode);
  1611. snd_soc_component_update_bits(component,
  1612. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1613. break;
  1614. case 1:
  1615. snd_soc_component_update_bits(component,
  1616. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1617. mode << 4);
  1618. snd_soc_component_update_bits(component,
  1619. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1620. break;
  1621. case 2:
  1622. snd_soc_component_update_bits(component,
  1623. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1624. mode);
  1625. snd_soc_component_update_bits(component,
  1626. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1627. break;
  1628. case 3:
  1629. snd_soc_component_update_bits(component,
  1630. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1631. mode << 4);
  1632. snd_soc_component_update_bits(component,
  1633. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1634. break;
  1635. default:
  1636. break;
  1637. }
  1638. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1639. break;
  1640. case SND_SOC_DAPM_POST_PMD:
  1641. switch (w->shift) {
  1642. case 0:
  1643. snd_soc_component_update_bits(component,
  1644. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1645. 0x00);
  1646. snd_soc_component_update_bits(component,
  1647. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1648. break;
  1649. case 1:
  1650. snd_soc_component_update_bits(component,
  1651. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1652. 0x00);
  1653. snd_soc_component_update_bits(component,
  1654. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1655. break;
  1656. case 2:
  1657. snd_soc_component_update_bits(component,
  1658. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1659. 0x00);
  1660. snd_soc_component_update_bits(component,
  1661. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1662. break;
  1663. case 3:
  1664. snd_soc_component_update_bits(component,
  1665. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1666. 0x00);
  1667. snd_soc_component_update_bits(component,
  1668. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1669. break;
  1670. default:
  1671. break;
  1672. }
  1673. snd_soc_component_update_bits(component,
  1674. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1675. break;
  1676. };
  1677. return ret;
  1678. }
  1679. int wcd938x_micbias_control(struct snd_soc_component *component,
  1680. int micb_num, int req, bool is_dapm)
  1681. {
  1682. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1683. int micb_index = micb_num - 1;
  1684. u16 micb_reg;
  1685. int pre_off_event = 0, post_off_event = 0;
  1686. int post_on_event = 0, post_dapm_off = 0;
  1687. int post_dapm_on = 0;
  1688. int ret = 0;
  1689. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1690. dev_err(component->dev,
  1691. "%s: Invalid micbias index, micb_ind:%d\n",
  1692. __func__, micb_index);
  1693. return -EINVAL;
  1694. }
  1695. if (NULL == wcd938x) {
  1696. dev_err(component->dev,
  1697. "%s: wcd938x private data is NULL\n", __func__);
  1698. return -EINVAL;
  1699. }
  1700. switch (micb_num) {
  1701. case MIC_BIAS_1:
  1702. micb_reg = WCD938X_ANA_MICB1;
  1703. break;
  1704. case MIC_BIAS_2:
  1705. micb_reg = WCD938X_ANA_MICB2;
  1706. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1707. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1708. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1709. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1710. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1711. break;
  1712. case MIC_BIAS_3:
  1713. micb_reg = WCD938X_ANA_MICB3;
  1714. break;
  1715. case MIC_BIAS_4:
  1716. micb_reg = WCD938X_ANA_MICB4;
  1717. break;
  1718. default:
  1719. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1720. __func__, micb_num);
  1721. return -EINVAL;
  1722. };
  1723. mutex_lock(&wcd938x->micb_lock);
  1724. switch (req) {
  1725. case MICB_PULLUP_ENABLE:
  1726. if (!wcd938x->dev_up) {
  1727. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1728. __func__, req);
  1729. ret = -ENODEV;
  1730. goto done;
  1731. }
  1732. wcd938x->pullup_ref[micb_index]++;
  1733. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1734. (wcd938x->micb_ref[micb_index] == 0))
  1735. snd_soc_component_update_bits(component, micb_reg,
  1736. 0xC0, 0x80);
  1737. break;
  1738. case MICB_PULLUP_DISABLE:
  1739. if (wcd938x->pullup_ref[micb_index] > 0)
  1740. wcd938x->pullup_ref[micb_index]--;
  1741. if (!wcd938x->dev_up) {
  1742. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1743. __func__, req);
  1744. ret = -ENODEV;
  1745. goto done;
  1746. }
  1747. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1748. (wcd938x->micb_ref[micb_index] == 0))
  1749. snd_soc_component_update_bits(component, micb_reg,
  1750. 0xC0, 0x00);
  1751. break;
  1752. case MICB_ENABLE:
  1753. if (!wcd938x->dev_up) {
  1754. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1755. __func__, req);
  1756. ret = -ENODEV;
  1757. goto done;
  1758. }
  1759. wcd938x->micb_ref[micb_index]++;
  1760. if (wcd938x->micb_ref[micb_index] == 1) {
  1761. snd_soc_component_update_bits(component,
  1762. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1763. snd_soc_component_update_bits(component,
  1764. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1765. snd_soc_component_update_bits(component,
  1766. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1767. snd_soc_component_update_bits(component,
  1768. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1769. snd_soc_component_update_bits(component,
  1770. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1771. snd_soc_component_update_bits(component,
  1772. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1773. snd_soc_component_update_bits(component,
  1774. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1775. snd_soc_component_update_bits(component,
  1776. micb_reg, 0xC0, 0x40);
  1777. if (post_on_event)
  1778. blocking_notifier_call_chain(
  1779. &wcd938x->mbhc->notifier,
  1780. post_on_event,
  1781. &wcd938x->mbhc->wcd_mbhc);
  1782. }
  1783. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1784. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1785. post_dapm_on,
  1786. &wcd938x->mbhc->wcd_mbhc);
  1787. break;
  1788. case MICB_DISABLE:
  1789. if (wcd938x->micb_ref[micb_index] > 0)
  1790. wcd938x->micb_ref[micb_index]--;
  1791. if (!wcd938x->dev_up) {
  1792. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1793. __func__, req);
  1794. ret = -ENODEV;
  1795. goto done;
  1796. }
  1797. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1798. (wcd938x->pullup_ref[micb_index] > 0))
  1799. snd_soc_component_update_bits(component, micb_reg,
  1800. 0xC0, 0x80);
  1801. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1802. (wcd938x->pullup_ref[micb_index] == 0)) {
  1803. if (pre_off_event && wcd938x->mbhc)
  1804. blocking_notifier_call_chain(
  1805. &wcd938x->mbhc->notifier,
  1806. pre_off_event,
  1807. &wcd938x->mbhc->wcd_mbhc);
  1808. snd_soc_component_update_bits(component, micb_reg,
  1809. 0xC0, 0x00);
  1810. if (post_off_event && wcd938x->mbhc)
  1811. blocking_notifier_call_chain(
  1812. &wcd938x->mbhc->notifier,
  1813. post_off_event,
  1814. &wcd938x->mbhc->wcd_mbhc);
  1815. }
  1816. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1817. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1818. post_dapm_off,
  1819. &wcd938x->mbhc->wcd_mbhc);
  1820. break;
  1821. };
  1822. dev_dbg(component->dev,
  1823. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1824. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1825. wcd938x->pullup_ref[micb_index]);
  1826. done:
  1827. mutex_unlock(&wcd938x->micb_lock);
  1828. return ret;
  1829. }
  1830. EXPORT_SYMBOL(wcd938x_micbias_control);
  1831. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1832. {
  1833. int ret = 0;
  1834. uint8_t devnum = 0;
  1835. int num_retry = NUM_ATTEMPTS;
  1836. do {
  1837. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1838. if (ret) {
  1839. dev_err(&swr_dev->dev,
  1840. "%s get devnum %d for dev addr %lx failed\n",
  1841. __func__, devnum, swr_dev->addr);
  1842. /* retry after 1ms */
  1843. usleep_range(1000, 1010);
  1844. }
  1845. } while (ret && --num_retry);
  1846. swr_dev->dev_num = devnum;
  1847. return 0;
  1848. }
  1849. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1850. struct wcd_mbhc_config *mbhc_cfg)
  1851. {
  1852. if (mbhc_cfg->enable_usbc_analog) {
  1853. if (!(snd_soc_component_read32(component, WCD938X_ANA_MBHC_MECH)
  1854. & 0x20))
  1855. return true;
  1856. }
  1857. return false;
  1858. }
  1859. static int wcd938x_event_notify(struct notifier_block *block,
  1860. unsigned long val,
  1861. void *data)
  1862. {
  1863. u16 event = (val & 0xffff);
  1864. int ret = 0;
  1865. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1866. struct snd_soc_component *component = wcd938x->component;
  1867. struct wcd_mbhc *mbhc;
  1868. switch (event) {
  1869. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1870. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1871. snd_soc_component_update_bits(component,
  1872. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1873. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1874. }
  1875. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1876. snd_soc_component_update_bits(component,
  1877. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1878. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1879. }
  1880. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1881. snd_soc_component_update_bits(component,
  1882. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1883. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1884. }
  1885. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1886. snd_soc_component_update_bits(component,
  1887. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1888. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1889. }
  1890. break;
  1891. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1892. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1893. 0xC0, 0x00);
  1894. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1895. 0x80, 0x00);
  1896. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1897. 0x80, 0x00);
  1898. break;
  1899. case BOLERO_WCD_EVT_SSR_DOWN:
  1900. wcd938x->dev_up = false;
  1901. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1902. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1903. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  1904. mbhc->mbhc_cfg);
  1905. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1906. wcd938x_reset_low(wcd938x->dev);
  1907. break;
  1908. case BOLERO_WCD_EVT_SSR_UP:
  1909. wcd938x_reset(wcd938x->dev);
  1910. /* allow reset to take effect */
  1911. usleep_range(10000, 10010);
  1912. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1913. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1914. wcd938x_init_reg(component);
  1915. regcache_mark_dirty(wcd938x->regmap);
  1916. regcache_sync(wcd938x->regmap);
  1917. /* Initialize MBHC module */
  1918. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1919. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1920. if (ret) {
  1921. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1922. __func__);
  1923. } else {
  1924. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1925. if (wcd938x->usbc_hs_status)
  1926. mdelay(500);
  1927. }
  1928. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1929. wcd938x->dev_up = true;
  1930. break;
  1931. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1932. snd_soc_component_update_bits(component,
  1933. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1934. ((val >> 0x10) << 0x01));
  1935. break;
  1936. default:
  1937. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1938. break;
  1939. }
  1940. return 0;
  1941. }
  1942. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1943. int event)
  1944. {
  1945. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1946. int micb_num;
  1947. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1948. __func__, w->name, event);
  1949. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1950. micb_num = MIC_BIAS_1;
  1951. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1952. micb_num = MIC_BIAS_2;
  1953. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1954. micb_num = MIC_BIAS_3;
  1955. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1956. micb_num = MIC_BIAS_4;
  1957. else
  1958. return -EINVAL;
  1959. switch (event) {
  1960. case SND_SOC_DAPM_PRE_PMU:
  1961. wcd938x_micbias_control(component, micb_num,
  1962. MICB_ENABLE, true);
  1963. break;
  1964. case SND_SOC_DAPM_POST_PMU:
  1965. /* 1 msec delay as per HW requirement */
  1966. usleep_range(1000, 1100);
  1967. break;
  1968. case SND_SOC_DAPM_POST_PMD:
  1969. wcd938x_micbias_control(component, micb_num,
  1970. MICB_DISABLE, true);
  1971. break;
  1972. };
  1973. return 0;
  1974. }
  1975. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1976. struct snd_kcontrol *kcontrol,
  1977. int event)
  1978. {
  1979. return __wcd938x_codec_enable_micbias(w, event);
  1980. }
  1981. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1982. int event)
  1983. {
  1984. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1985. int micb_num;
  1986. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1987. __func__, w->name, event);
  1988. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1989. micb_num = MIC_BIAS_1;
  1990. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1991. micb_num = MIC_BIAS_2;
  1992. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1993. micb_num = MIC_BIAS_3;
  1994. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1995. micb_num = MIC_BIAS_4;
  1996. else
  1997. return -EINVAL;
  1998. switch (event) {
  1999. case SND_SOC_DAPM_PRE_PMU:
  2000. wcd938x_micbias_control(component, micb_num,
  2001. MICB_PULLUP_ENABLE, true);
  2002. break;
  2003. case SND_SOC_DAPM_POST_PMU:
  2004. /* 1 msec delay as per HW requirement */
  2005. usleep_range(1000, 1100);
  2006. break;
  2007. case SND_SOC_DAPM_POST_PMD:
  2008. wcd938x_micbias_control(component, micb_num,
  2009. MICB_PULLUP_DISABLE, true);
  2010. break;
  2011. };
  2012. return 0;
  2013. }
  2014. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2015. struct snd_kcontrol *kcontrol,
  2016. int event)
  2017. {
  2018. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2019. }
  2020. static int wcd938x_wakeup(void *handle, bool enable)
  2021. {
  2022. struct wcd938x_priv *priv;
  2023. int ret = 0;
  2024. if (!handle) {
  2025. pr_err("%s: NULL handle\n", __func__);
  2026. return -EINVAL;
  2027. }
  2028. priv = (struct wcd938x_priv *)handle;
  2029. if (!priv->tx_swr_dev) {
  2030. pr_err("%s: tx swr dev is NULL\n", __func__);
  2031. return -EINVAL;
  2032. }
  2033. mutex_lock(&priv->wakeup_lock);
  2034. if (enable)
  2035. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2036. else
  2037. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2038. mutex_unlock(&priv->wakeup_lock);
  2039. return ret;
  2040. }
  2041. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2042. struct snd_kcontrol *kcontrol,
  2043. int event)
  2044. {
  2045. int ret = 0;
  2046. struct snd_soc_component *component =
  2047. snd_soc_dapm_to_component(w->dapm);
  2048. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2049. switch (event) {
  2050. case SND_SOC_DAPM_PRE_PMU:
  2051. wcd938x_wakeup(wcd938x, true);
  2052. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2053. wcd938x_wakeup(wcd938x, false);
  2054. break;
  2055. case SND_SOC_DAPM_POST_PMD:
  2056. wcd938x_wakeup(wcd938x, true);
  2057. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2058. wcd938x_wakeup(wcd938x, false);
  2059. break;
  2060. }
  2061. return ret;
  2062. }
  2063. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2064. int micb_num, int req)
  2065. {
  2066. int micb_index = micb_num - 1;
  2067. u16 micb_reg;
  2068. if (NULL == wcd938x) {
  2069. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2070. return -EINVAL;
  2071. }
  2072. switch (micb_num) {
  2073. case MIC_BIAS_1:
  2074. micb_reg = WCD938X_ANA_MICB1;
  2075. break;
  2076. case MIC_BIAS_2:
  2077. micb_reg = WCD938X_ANA_MICB2;
  2078. break;
  2079. case MIC_BIAS_3:
  2080. micb_reg = WCD938X_ANA_MICB3;
  2081. break;
  2082. case MIC_BIAS_4:
  2083. micb_reg = WCD938X_ANA_MICB4;
  2084. break;
  2085. default:
  2086. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2087. return -EINVAL;
  2088. };
  2089. mutex_lock(&wcd938x->micb_lock);
  2090. switch (req) {
  2091. case MICB_ENABLE:
  2092. wcd938x->micb_ref[micb_index]++;
  2093. if (wcd938x->micb_ref[micb_index] == 1) {
  2094. regmap_update_bits(wcd938x->regmap,
  2095. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2096. regmap_update_bits(wcd938x->regmap,
  2097. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2098. regmap_update_bits(wcd938x->regmap,
  2099. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2100. regmap_update_bits(wcd938x->regmap,
  2101. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2102. regmap_update_bits(wcd938x->regmap,
  2103. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2104. regmap_update_bits(wcd938x->regmap,
  2105. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2106. regmap_update_bits(wcd938x->regmap,
  2107. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2108. regmap_update_bits(wcd938x->regmap,
  2109. micb_reg, 0xC0, 0x40);
  2110. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2111. }
  2112. break;
  2113. case MICB_PULLUP_ENABLE:
  2114. wcd938x->pullup_ref[micb_index]++;
  2115. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2116. (wcd938x->micb_ref[micb_index] == 0))
  2117. regmap_update_bits(wcd938x->regmap, micb_reg,
  2118. 0xC0, 0x80);
  2119. break;
  2120. case MICB_PULLUP_DISABLE:
  2121. if (wcd938x->pullup_ref[micb_index] > 0)
  2122. wcd938x->pullup_ref[micb_index]--;
  2123. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2124. (wcd938x->micb_ref[micb_index] == 0))
  2125. regmap_update_bits(wcd938x->regmap, micb_reg,
  2126. 0xC0, 0x00);
  2127. break;
  2128. case MICB_DISABLE:
  2129. if (wcd938x->micb_ref[micb_index] > 0)
  2130. wcd938x->micb_ref[micb_index]--;
  2131. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2132. (wcd938x->pullup_ref[micb_index] > 0))
  2133. regmap_update_bits(wcd938x->regmap, micb_reg,
  2134. 0xC0, 0x80);
  2135. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2136. (wcd938x->pullup_ref[micb_index] == 0))
  2137. regmap_update_bits(wcd938x->regmap, micb_reg,
  2138. 0xC0, 0x00);
  2139. break;
  2140. };
  2141. mutex_unlock(&wcd938x->micb_lock);
  2142. return 0;
  2143. }
  2144. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2145. int event, int micb_num)
  2146. {
  2147. struct wcd938x_priv *wcd938x_priv = NULL;
  2148. if(NULL == component) {
  2149. pr_err("%s: wcd938x component is NULL\n", __func__);
  2150. return -EINVAL;
  2151. }
  2152. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2153. pr_err("%s: invalid event: %d\n", __func__, event);
  2154. return -EINVAL;
  2155. }
  2156. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2157. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2158. return -EINVAL;
  2159. }
  2160. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2161. switch (event) {
  2162. case SND_SOC_DAPM_PRE_PMU:
  2163. wcd938x_wakeup(wcd938x_priv, true);
  2164. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2165. wcd938x_wakeup(wcd938x_priv, false);
  2166. break;
  2167. case SND_SOC_DAPM_POST_PMD:
  2168. wcd938x_wakeup(wcd938x_priv, true);
  2169. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2170. wcd938x_wakeup(wcd938x_priv, false);
  2171. break;
  2172. }
  2173. return 0;
  2174. }
  2175. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2176. static inline int wcd938x_tx_path_get(const char *wname,
  2177. unsigned int *path_num)
  2178. {
  2179. int ret = 0;
  2180. char *widget_name = NULL;
  2181. char *w_name = NULL;
  2182. char *path_num_char = NULL;
  2183. char *path_name = NULL;
  2184. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2185. if (!widget_name)
  2186. return -EINVAL;
  2187. w_name = widget_name;
  2188. path_name = strsep(&widget_name, " ");
  2189. if (!path_name) {
  2190. pr_err("%s: Invalid widget name = %s\n",
  2191. __func__, widget_name);
  2192. ret = -EINVAL;
  2193. goto err;
  2194. }
  2195. path_num_char = strpbrk(path_name, "0123");
  2196. if (!path_num_char) {
  2197. pr_err("%s: tx path index not found\n",
  2198. __func__);
  2199. ret = -EINVAL;
  2200. goto err;
  2201. }
  2202. ret = kstrtouint(path_num_char, 10, path_num);
  2203. if (ret < 0)
  2204. pr_err("%s: Invalid tx path = %s\n",
  2205. __func__, w_name);
  2206. err:
  2207. kfree(w_name);
  2208. return ret;
  2209. }
  2210. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2211. struct snd_ctl_elem_value *ucontrol)
  2212. {
  2213. struct snd_soc_component *component =
  2214. snd_soc_kcontrol_component(kcontrol);
  2215. struct wcd938x_priv *wcd938x = NULL;
  2216. int ret = 0;
  2217. unsigned int path = 0;
  2218. if (!component)
  2219. return -EINVAL;
  2220. wcd938x = snd_soc_component_get_drvdata(component);
  2221. if (!wcd938x)
  2222. return -EINVAL;
  2223. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2224. if (ret < 0)
  2225. return ret;
  2226. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2227. return 0;
  2228. }
  2229. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2230. struct snd_ctl_elem_value *ucontrol)
  2231. {
  2232. struct snd_soc_component *component =
  2233. snd_soc_kcontrol_component(kcontrol);
  2234. struct wcd938x_priv *wcd938x = NULL;
  2235. u32 mode_val;
  2236. unsigned int path = 0;
  2237. int ret = 0;
  2238. if (!component)
  2239. return -EINVAL;
  2240. wcd938x = snd_soc_component_get_drvdata(component);
  2241. if (!wcd938x)
  2242. return -EINVAL;
  2243. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2244. if (ret)
  2245. return ret;
  2246. mode_val = ucontrol->value.enumerated.item[0];
  2247. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2248. wcd938x->tx_mode[path] = mode_val;
  2249. return 0;
  2250. }
  2251. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2252. struct snd_ctl_elem_value *ucontrol)
  2253. {
  2254. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2255. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2256. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2257. return 0;
  2258. }
  2259. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2260. struct snd_ctl_elem_value *ucontrol)
  2261. {
  2262. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2263. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2264. u32 mode_val;
  2265. mode_val = ucontrol->value.enumerated.item[0];
  2266. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2267. if (wcd938x->variant == WCD9380) {
  2268. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2269. dev_info(component->dev,
  2270. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2271. __func__);
  2272. mode_val = CLS_H_ULP;
  2273. }
  2274. }
  2275. if (mode_val == CLS_H_NORMAL) {
  2276. dev_info(component->dev,
  2277. "%s:Invalid HPH Mode, default to class_AB\n",
  2278. __func__);
  2279. mode_val = CLS_H_ULP;
  2280. }
  2281. wcd938x->hph_mode = mode_val;
  2282. return 0;
  2283. }
  2284. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2285. struct snd_ctl_elem_value *ucontrol)
  2286. {
  2287. u8 ear_pa_gain = 0;
  2288. struct snd_soc_component *component =
  2289. snd_soc_kcontrol_component(kcontrol);
  2290. ear_pa_gain = snd_soc_component_read32(component,
  2291. WCD938X_ANA_EAR_COMPANDER_CTL);
  2292. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2293. ucontrol->value.integer.value[0] = ear_pa_gain;
  2294. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2295. ear_pa_gain);
  2296. return 0;
  2297. }
  2298. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2299. struct snd_ctl_elem_value *ucontrol)
  2300. {
  2301. u8 ear_pa_gain = 0;
  2302. struct snd_soc_component *component =
  2303. snd_soc_kcontrol_component(kcontrol);
  2304. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2305. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2306. __func__, ucontrol->value.integer.value[0]);
  2307. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2308. if (!wcd938x->comp1_enable) {
  2309. snd_soc_component_update_bits(component,
  2310. WCD938X_ANA_EAR_COMPANDER_CTL,
  2311. 0x7C, ear_pa_gain);
  2312. }
  2313. return 0;
  2314. }
  2315. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2316. struct snd_ctl_elem_value *ucontrol)
  2317. {
  2318. struct snd_soc_component *component =
  2319. snd_soc_kcontrol_component(kcontrol);
  2320. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2321. bool hphr;
  2322. struct soc_multi_mixer_control *mc;
  2323. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2324. hphr = mc->shift;
  2325. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2326. wcd938x->comp1_enable;
  2327. return 0;
  2328. }
  2329. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2330. struct snd_ctl_elem_value *ucontrol)
  2331. {
  2332. struct snd_soc_component *component =
  2333. snd_soc_kcontrol_component(kcontrol);
  2334. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2335. int value = ucontrol->value.integer.value[0];
  2336. bool hphr;
  2337. struct soc_multi_mixer_control *mc;
  2338. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2339. hphr = mc->shift;
  2340. if (hphr)
  2341. wcd938x->comp2_enable = value;
  2342. else
  2343. wcd938x->comp1_enable = value;
  2344. return 0;
  2345. }
  2346. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2347. struct snd_kcontrol *kcontrol,
  2348. int event)
  2349. {
  2350. struct snd_soc_component *component =
  2351. snd_soc_dapm_to_component(w->dapm);
  2352. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2353. struct wcd938x_pdata *pdata = NULL;
  2354. int ret = 0;
  2355. pdata = dev_get_platdata(wcd938x->dev);
  2356. if (!pdata) {
  2357. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2358. return -EINVAL;
  2359. }
  2360. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2361. wcd938x->supplies,
  2362. pdata->regulator,
  2363. pdata->num_supplies,
  2364. "cdc-vdd-buck"))
  2365. return 0;
  2366. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2367. w->name, event);
  2368. switch (event) {
  2369. case SND_SOC_DAPM_PRE_PMU:
  2370. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2371. dev_dbg(component->dev,
  2372. "%s: buck already in enabled state\n",
  2373. __func__);
  2374. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2375. return 0;
  2376. }
  2377. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2378. wcd938x->supplies,
  2379. pdata->regulator,
  2380. pdata->num_supplies,
  2381. "cdc-vdd-buck");
  2382. if (ret == -EINVAL) {
  2383. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2384. __func__);
  2385. return ret;
  2386. }
  2387. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2388. /*
  2389. * 200us sleep is required after LDO is enabled as per
  2390. * HW requirement
  2391. */
  2392. usleep_range(200, 250);
  2393. break;
  2394. case SND_SOC_DAPM_POST_PMD:
  2395. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2396. break;
  2397. }
  2398. return 0;
  2399. }
  2400. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2401. struct snd_ctl_elem_value *ucontrol)
  2402. {
  2403. struct snd_soc_component *component =
  2404. snd_soc_kcontrol_component(kcontrol);
  2405. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2406. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2407. return 0;
  2408. }
  2409. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2410. struct snd_ctl_elem_value *ucontrol)
  2411. {
  2412. struct snd_soc_component *component =
  2413. snd_soc_kcontrol_component(kcontrol);
  2414. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2415. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2416. return 0;
  2417. }
  2418. const char * const tx_master_ch_text[] = {
  2419. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2420. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2421. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2422. "SWRM_PCM_IN",
  2423. };
  2424. const struct soc_enum tx_master_ch_enum =
  2425. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2426. tx_master_ch_text);
  2427. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2428. {
  2429. u8 ch_type = 0;
  2430. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2431. ch_type = ADC1;
  2432. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2433. ch_type = ADC2;
  2434. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2435. ch_type = ADC3;
  2436. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2437. ch_type = ADC4;
  2438. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2439. ch_type = DMIC0;
  2440. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2441. ch_type = DMIC1;
  2442. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2443. ch_type = MBHC;
  2444. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2445. ch_type = DMIC2;
  2446. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2447. ch_type = DMIC3;
  2448. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2449. ch_type = DMIC4;
  2450. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2451. ch_type = DMIC5;
  2452. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2453. ch_type = DMIC6;
  2454. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2455. ch_type = DMIC7;
  2456. else
  2457. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2458. if (ch_type)
  2459. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2460. else
  2461. *ch_idx = -EINVAL;
  2462. }
  2463. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. struct snd_soc_component *component =
  2467. snd_soc_kcontrol_component(kcontrol);
  2468. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2469. int slave_ch_idx;
  2470. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2471. if (slave_ch_idx != -EINVAL)
  2472. ucontrol->value.integer.value[0] =
  2473. wcd938x_slave_get_master_ch_val(
  2474. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2475. return 0;
  2476. }
  2477. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2478. struct snd_ctl_elem_value *ucontrol)
  2479. {
  2480. struct snd_soc_component *component =
  2481. snd_soc_kcontrol_component(kcontrol);
  2482. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2483. int slave_ch_idx;
  2484. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2485. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2486. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2487. __func__, ucontrol->value.enumerated.item[0]);
  2488. if (slave_ch_idx != -EINVAL)
  2489. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2490. wcd938x_slave_get_master_ch(
  2491. ucontrol->value.enumerated.item[0]);
  2492. return 0;
  2493. }
  2494. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2495. struct snd_ctl_elem_value *ucontrol)
  2496. {
  2497. struct snd_soc_component *component =
  2498. snd_soc_kcontrol_component(kcontrol);
  2499. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2500. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2501. return 0;
  2502. }
  2503. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2504. struct snd_ctl_elem_value *ucontrol)
  2505. {
  2506. struct snd_soc_component *component =
  2507. snd_soc_kcontrol_component(kcontrol);
  2508. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2509. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2510. return 0;
  2511. }
  2512. static const char * const tx_mode_mux_text_wcd9380[] = {
  2513. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2514. };
  2515. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2516. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2517. tx_mode_mux_text_wcd9380);
  2518. static const char * const tx_mode_mux_text[] = {
  2519. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2520. "ADC_ULP1", "ADC_ULP2",
  2521. };
  2522. static const struct soc_enum tx_mode_mux_enum =
  2523. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2524. tx_mode_mux_text);
  2525. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2526. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2527. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2528. "CLS_AB_LOHIFI",
  2529. };
  2530. static const char * const wcd938x_ear_pa_gain_text[] = {
  2531. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2532. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2533. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2534. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2535. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2536. };
  2537. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2538. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2539. rx_hph_mode_mux_text_wcd9380);
  2540. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2541. wcd938x_ear_pa_gain_text);
  2542. static const char * const rx_hph_mode_mux_text[] = {
  2543. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2544. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2545. };
  2546. static const struct soc_enum rx_hph_mode_mux_enum =
  2547. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2548. rx_hph_mode_mux_text);
  2549. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2550. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2551. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2552. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2553. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2554. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2555. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2556. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2557. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2558. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2559. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2560. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2561. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2562. };
  2563. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2564. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2565. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2566. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2567. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2568. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2569. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2570. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2571. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2572. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2573. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2574. };
  2575. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2576. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2577. wcd938x_get_compander, wcd938x_set_compander),
  2578. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2579. wcd938x_get_compander, wcd938x_set_compander),
  2580. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2581. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2582. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2583. wcd938x_bcs_get, wcd938x_bcs_put),
  2584. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2585. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2586. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2587. analog_gain),
  2588. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2589. analog_gain),
  2590. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2591. analog_gain),
  2592. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2593. analog_gain),
  2594. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2595. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2596. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2597. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2598. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2599. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2600. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2601. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2602. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2603. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2604. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2605. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2606. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2607. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2608. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2609. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2610. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2611. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2612. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2613. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2614. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2615. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2616. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2617. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2618. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2619. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2620. };
  2621. static const struct snd_kcontrol_new adc1_switch[] = {
  2622. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2623. };
  2624. static const struct snd_kcontrol_new adc2_switch[] = {
  2625. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2626. };
  2627. static const struct snd_kcontrol_new adc3_switch[] = {
  2628. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2629. };
  2630. static const struct snd_kcontrol_new adc4_switch[] = {
  2631. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2632. };
  2633. static const struct snd_kcontrol_new dmic1_switch[] = {
  2634. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2635. };
  2636. static const struct snd_kcontrol_new dmic2_switch[] = {
  2637. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2638. };
  2639. static const struct snd_kcontrol_new dmic3_switch[] = {
  2640. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2641. };
  2642. static const struct snd_kcontrol_new dmic4_switch[] = {
  2643. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2644. };
  2645. static const struct snd_kcontrol_new dmic5_switch[] = {
  2646. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2647. };
  2648. static const struct snd_kcontrol_new dmic6_switch[] = {
  2649. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2650. };
  2651. static const struct snd_kcontrol_new dmic7_switch[] = {
  2652. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2653. };
  2654. static const struct snd_kcontrol_new dmic8_switch[] = {
  2655. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2656. };
  2657. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2658. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2659. };
  2660. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2661. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2662. };
  2663. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2664. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2665. };
  2666. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2667. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2668. };
  2669. static const char * const adc2_mux_text[] = {
  2670. "INP2", "INP3"
  2671. };
  2672. static const struct soc_enum adc2_enum =
  2673. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2674. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2675. static const struct snd_kcontrol_new tx_adc2_mux =
  2676. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2677. static const char * const adc3_mux_text[] = {
  2678. "INP4", "INP6"
  2679. };
  2680. static const struct soc_enum adc3_enum =
  2681. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2682. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2683. static const struct snd_kcontrol_new tx_adc3_mux =
  2684. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2685. static const char * const adc4_mux_text[] = {
  2686. "INP5", "INP7"
  2687. };
  2688. static const struct soc_enum adc4_enum =
  2689. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2690. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2691. static const struct snd_kcontrol_new tx_adc4_mux =
  2692. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2693. static const char * const rdac3_mux_text[] = {
  2694. "RX1", "RX3"
  2695. };
  2696. static const char * const hdr12_mux_text[] = {
  2697. "NO_HDR12", "HDR12"
  2698. };
  2699. static const struct soc_enum hdr12_enum =
  2700. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2701. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2702. static const struct snd_kcontrol_new tx_hdr12_mux =
  2703. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2704. static const char * const hdr34_mux_text[] = {
  2705. "NO_HDR34", "HDR34"
  2706. };
  2707. static const struct soc_enum hdr34_enum =
  2708. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2709. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2710. static const struct snd_kcontrol_new tx_hdr34_mux =
  2711. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2712. static const struct soc_enum rdac3_enum =
  2713. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2714. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2715. static const struct snd_kcontrol_new rx_rdac3_mux =
  2716. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2717. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2718. /*input widgets*/
  2719. SND_SOC_DAPM_INPUT("AMIC1"),
  2720. SND_SOC_DAPM_INPUT("AMIC2"),
  2721. SND_SOC_DAPM_INPUT("AMIC3"),
  2722. SND_SOC_DAPM_INPUT("AMIC4"),
  2723. SND_SOC_DAPM_INPUT("AMIC5"),
  2724. SND_SOC_DAPM_INPUT("AMIC6"),
  2725. SND_SOC_DAPM_INPUT("AMIC7"),
  2726. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2727. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2728. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2729. /*tx widgets*/
  2730. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2731. wcd938x_codec_enable_adc,
  2732. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2733. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2734. wcd938x_codec_enable_adc,
  2735. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2736. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2737. wcd938x_codec_enable_adc,
  2738. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2739. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2740. wcd938x_codec_enable_adc,
  2741. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2742. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2743. wcd938x_codec_enable_dmic,
  2744. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2745. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2746. wcd938x_codec_enable_dmic,
  2747. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2748. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2749. wcd938x_codec_enable_dmic,
  2750. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2751. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2752. wcd938x_codec_enable_dmic,
  2753. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2754. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2755. wcd938x_codec_enable_dmic,
  2756. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2757. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2758. wcd938x_codec_enable_dmic,
  2759. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2760. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2761. wcd938x_codec_enable_dmic,
  2762. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2763. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2764. wcd938x_codec_enable_dmic,
  2765. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2766. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2767. NULL, 0, wcd938x_enable_req,
  2768. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2769. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2770. NULL, 0, wcd938x_enable_req,
  2771. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2772. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2773. NULL, 0, wcd938x_enable_req,
  2774. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2775. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2776. NULL, 0, wcd938x_enable_req,
  2777. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2778. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2779. &tx_adc2_mux),
  2780. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2781. &tx_adc3_mux),
  2782. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2783. &tx_adc4_mux),
  2784. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2785. &tx_hdr12_mux),
  2786. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2787. &tx_hdr34_mux),
  2788. /*tx mixers*/
  2789. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  2790. adc1_switch, ARRAY_SIZE(adc1_switch),
  2791. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2792. SND_SOC_DAPM_POST_PMD),
  2793. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  2794. adc2_switch, ARRAY_SIZE(adc2_switch),
  2795. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2796. SND_SOC_DAPM_POST_PMD),
  2797. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  2798. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2799. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2800. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  2801. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2802. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2803. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2804. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2805. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2806. SND_SOC_DAPM_POST_PMD),
  2807. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2808. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2809. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2810. SND_SOC_DAPM_POST_PMD),
  2811. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2812. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2813. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2814. SND_SOC_DAPM_POST_PMD),
  2815. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2816. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2817. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2818. SND_SOC_DAPM_POST_PMD),
  2819. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2820. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2821. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2822. SND_SOC_DAPM_POST_PMD),
  2823. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  2824. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2825. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2826. SND_SOC_DAPM_POST_PMD),
  2827. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  2828. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2829. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2830. SND_SOC_DAPM_POST_PMD),
  2831. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  2832. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2833. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2834. SND_SOC_DAPM_POST_PMD),
  2835. /* micbias widgets*/
  2836. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2837. wcd938x_codec_enable_micbias,
  2838. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2839. SND_SOC_DAPM_POST_PMD),
  2840. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2841. wcd938x_codec_enable_micbias,
  2842. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2843. SND_SOC_DAPM_POST_PMD),
  2844. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2845. wcd938x_codec_enable_micbias,
  2846. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2847. SND_SOC_DAPM_POST_PMD),
  2848. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2849. wcd938x_codec_enable_micbias,
  2850. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2851. SND_SOC_DAPM_POST_PMD),
  2852. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2853. wcd938x_codec_force_enable_micbias,
  2854. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2855. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2856. wcd938x_codec_force_enable_micbias,
  2857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2858. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2859. wcd938x_codec_force_enable_micbias,
  2860. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2861. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2862. wcd938x_codec_force_enable_micbias,
  2863. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2864. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2865. wcd938x_codec_enable_vdd_buck,
  2866. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2867. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2868. wcd938x_enable_clsh,
  2869. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2870. /*rx widgets*/
  2871. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2872. wcd938x_codec_enable_ear_pa,
  2873. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2874. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2875. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2876. wcd938x_codec_enable_aux_pa,
  2877. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2878. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2879. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2880. wcd938x_codec_enable_hphl_pa,
  2881. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2882. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2883. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2884. wcd938x_codec_enable_hphr_pa,
  2885. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2886. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2887. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2888. wcd938x_codec_hphl_dac_event,
  2889. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2890. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2891. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2892. wcd938x_codec_hphr_dac_event,
  2893. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2894. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2895. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2896. wcd938x_codec_ear_dac_event,
  2897. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2898. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2899. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2900. wcd938x_codec_aux_dac_event,
  2901. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2902. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2903. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2904. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2905. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2906. SND_SOC_DAPM_POST_PMD),
  2907. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2908. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2909. SND_SOC_DAPM_POST_PMD),
  2910. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2911. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2912. SND_SOC_DAPM_POST_PMD),
  2913. /* rx mixer widgets*/
  2914. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2915. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2916. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2917. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2918. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2919. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2920. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2921. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2922. /*output widgets tx*/
  2923. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2924. /*output widgets rx*/
  2925. SND_SOC_DAPM_OUTPUT("EAR"),
  2926. SND_SOC_DAPM_OUTPUT("AUX"),
  2927. SND_SOC_DAPM_OUTPUT("HPHL"),
  2928. SND_SOC_DAPM_OUTPUT("HPHR"),
  2929. /* micbias pull up widgets*/
  2930. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2931. wcd938x_codec_enable_micbias_pullup,
  2932. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2933. SND_SOC_DAPM_POST_PMD),
  2934. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2935. wcd938x_codec_enable_micbias_pullup,
  2936. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2937. SND_SOC_DAPM_POST_PMD),
  2938. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2939. wcd938x_codec_enable_micbias_pullup,
  2940. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2941. SND_SOC_DAPM_POST_PMD),
  2942. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2943. wcd938x_codec_enable_micbias_pullup,
  2944. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2945. SND_SOC_DAPM_POST_PMD),
  2946. };
  2947. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2948. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2949. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2950. {"ADC1 REQ", NULL, "ADC1"},
  2951. {"ADC1", NULL, "AMIC1"},
  2952. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2953. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2954. {"ADC2 REQ", NULL, "ADC2"},
  2955. {"ADC2", NULL, "HDR12 MUX"},
  2956. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2957. {"HDR12 MUX", "HDR12", "AMIC1"},
  2958. {"ADC2 MUX", "INP3", "AMIC3"},
  2959. {"ADC2 MUX", "INP2", "AMIC2"},
  2960. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2961. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2962. {"ADC3 REQ", NULL, "ADC3"},
  2963. {"ADC3", NULL, "HDR34 MUX"},
  2964. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2965. {"HDR34 MUX", "HDR34", "AMIC5"},
  2966. {"ADC3 MUX", "INP4", "AMIC4"},
  2967. {"ADC3 MUX", "INP6", "AMIC6"},
  2968. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2969. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2970. {"ADC4 REQ", NULL, "ADC4"},
  2971. {"ADC4", NULL, "ADC4 MUX"},
  2972. {"ADC4 MUX", "INP5", "AMIC5"},
  2973. {"ADC4 MUX", "INP7", "AMIC7"},
  2974. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2975. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2976. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2977. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2978. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2979. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2980. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2981. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2982. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2983. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2984. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2985. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2986. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2987. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2988. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2989. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2990. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2991. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2992. {"RX1", NULL, "IN1_HPHL"},
  2993. {"RDAC1", NULL, "RX1"},
  2994. {"HPHL_RDAC", "Switch", "RDAC1"},
  2995. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2996. {"HPHL", NULL, "HPHL PGA"},
  2997. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2998. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2999. {"RX2", NULL, "IN2_HPHR"},
  3000. {"RDAC2", NULL, "RX2"},
  3001. {"HPHR_RDAC", "Switch", "RDAC2"},
  3002. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3003. {"HPHR", NULL, "HPHR PGA"},
  3004. {"IN3_AUX", NULL, "VDD_BUCK"},
  3005. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3006. {"RX3", NULL, "IN3_AUX"},
  3007. {"RDAC4", NULL, "RX3"},
  3008. {"AUX_RDAC", "Switch", "RDAC4"},
  3009. {"AUX PGA", NULL, "AUX_RDAC"},
  3010. {"AUX", NULL, "AUX PGA"},
  3011. {"RDAC3_MUX", "RX3", "RX3"},
  3012. {"RDAC3_MUX", "RX1", "RX1"},
  3013. {"RDAC3", NULL, "RDAC3_MUX"},
  3014. {"EAR_RDAC", "Switch", "RDAC3"},
  3015. {"EAR PGA", NULL, "EAR_RDAC"},
  3016. {"EAR", NULL, "EAR PGA"},
  3017. };
  3018. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3019. void *file_private_data,
  3020. struct file *file,
  3021. char __user *buf, size_t count,
  3022. loff_t pos)
  3023. {
  3024. struct wcd938x_priv *priv;
  3025. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3026. int len = 0;
  3027. priv = (struct wcd938x_priv *) entry->private_data;
  3028. if (!priv) {
  3029. pr_err("%s: wcd938x priv is null\n", __func__);
  3030. return -EINVAL;
  3031. }
  3032. switch (priv->version) {
  3033. case WCD938X_VERSION_1_0:
  3034. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3035. break;
  3036. default:
  3037. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3038. }
  3039. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3040. }
  3041. static struct snd_info_entry_ops wcd938x_info_ops = {
  3042. .read = wcd938x_version_read,
  3043. };
  3044. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3045. void *file_private_data,
  3046. struct file *file,
  3047. char __user *buf, size_t count,
  3048. loff_t pos)
  3049. {
  3050. struct wcd938x_priv *priv;
  3051. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3052. int len = 0;
  3053. priv = (struct wcd938x_priv *) entry->private_data;
  3054. if (!priv) {
  3055. pr_err("%s: wcd938x priv is null\n", __func__);
  3056. return -EINVAL;
  3057. }
  3058. switch (priv->variant) {
  3059. case WCD9380:
  3060. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3061. break;
  3062. case WCD9385:
  3063. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3064. break;
  3065. default:
  3066. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3067. }
  3068. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3069. }
  3070. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3071. .read = wcd938x_variant_read,
  3072. };
  3073. /*
  3074. * wcd938x_get_codec_variant
  3075. * @component: component instance
  3076. *
  3077. * Return: codec variant or -EINVAL in error.
  3078. */
  3079. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3080. {
  3081. struct wcd938x_priv *priv = NULL;
  3082. if (!component)
  3083. return -EINVAL;
  3084. priv = snd_soc_component_get_drvdata(component);
  3085. if (!priv) {
  3086. dev_err(component->dev,
  3087. "%s:wcd938x not probed\n", __func__);
  3088. return 0;
  3089. }
  3090. return priv->variant;
  3091. }
  3092. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3093. /*
  3094. * wcd938x_info_create_codec_entry - creates wcd938x module
  3095. * @codec_root: The parent directory
  3096. * @component: component instance
  3097. *
  3098. * Creates wcd938x module, variant and version entry under the given
  3099. * parent directory.
  3100. *
  3101. * Return: 0 on success or negative error code on failure.
  3102. */
  3103. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3104. struct snd_soc_component *component)
  3105. {
  3106. struct snd_info_entry *version_entry;
  3107. struct snd_info_entry *variant_entry;
  3108. struct wcd938x_priv *priv;
  3109. struct snd_soc_card *card;
  3110. if (!codec_root || !component)
  3111. return -EINVAL;
  3112. priv = snd_soc_component_get_drvdata(component);
  3113. if (priv->entry) {
  3114. dev_dbg(priv->dev,
  3115. "%s:wcd938x module already created\n", __func__);
  3116. return 0;
  3117. }
  3118. card = component->card;
  3119. priv->entry = snd_info_create_module_entry(codec_root->module,
  3120. "wcd938x", codec_root);
  3121. if (!priv->entry) {
  3122. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3123. __func__);
  3124. return -ENOMEM;
  3125. }
  3126. priv->entry->mode = S_IFDIR | 0555;
  3127. if (snd_info_register(priv->entry) < 0) {
  3128. snd_info_free_entry(priv->entry);
  3129. return -ENOMEM;
  3130. }
  3131. version_entry = snd_info_create_card_entry(card->snd_card,
  3132. "version",
  3133. priv->entry);
  3134. if (!version_entry) {
  3135. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3136. __func__);
  3137. snd_info_free_entry(priv->entry);
  3138. return -ENOMEM;
  3139. }
  3140. version_entry->private_data = priv;
  3141. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3142. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3143. version_entry->c.ops = &wcd938x_info_ops;
  3144. if (snd_info_register(version_entry) < 0) {
  3145. snd_info_free_entry(version_entry);
  3146. snd_info_free_entry(priv->entry);
  3147. return -ENOMEM;
  3148. }
  3149. priv->version_entry = version_entry;
  3150. variant_entry = snd_info_create_card_entry(card->snd_card,
  3151. "variant",
  3152. priv->entry);
  3153. if (!variant_entry) {
  3154. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3155. __func__);
  3156. snd_info_free_entry(version_entry);
  3157. snd_info_free_entry(priv->entry);
  3158. return -ENOMEM;
  3159. }
  3160. variant_entry->private_data = priv;
  3161. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3162. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3163. variant_entry->c.ops = &wcd938x_variant_ops;
  3164. if (snd_info_register(variant_entry) < 0) {
  3165. snd_info_free_entry(variant_entry);
  3166. snd_info_free_entry(version_entry);
  3167. snd_info_free_entry(priv->entry);
  3168. return -ENOMEM;
  3169. }
  3170. priv->variant_entry = variant_entry;
  3171. return 0;
  3172. }
  3173. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3174. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3175. struct wcd938x_pdata *pdata)
  3176. {
  3177. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3178. int rc = 0;
  3179. if (!pdata) {
  3180. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3181. return -ENODEV;
  3182. }
  3183. /* set micbias voltage */
  3184. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3185. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3186. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3187. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3188. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3189. vout_ctl_4 < 0) {
  3190. rc = -EINVAL;
  3191. goto done;
  3192. }
  3193. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3194. vout_ctl_1);
  3195. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3196. vout_ctl_2);
  3197. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3198. vout_ctl_3);
  3199. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3200. vout_ctl_4);
  3201. done:
  3202. return rc;
  3203. }
  3204. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3205. {
  3206. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3207. struct snd_soc_dapm_context *dapm =
  3208. snd_soc_component_get_dapm(component);
  3209. int variant;
  3210. int ret = -EINVAL;
  3211. dev_info(component->dev, "%s()\n", __func__);
  3212. wcd938x = snd_soc_component_get_drvdata(component);
  3213. if (!wcd938x)
  3214. return -EINVAL;
  3215. wcd938x->component = component;
  3216. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3217. variant = (snd_soc_component_read32(component,
  3218. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3219. wcd938x->variant = variant;
  3220. wcd938x->fw_data = devm_kzalloc(component->dev,
  3221. sizeof(*(wcd938x->fw_data)),
  3222. GFP_KERNEL);
  3223. if (!wcd938x->fw_data) {
  3224. dev_err(component->dev, "Failed to allocate fw_data\n");
  3225. ret = -ENOMEM;
  3226. goto err;
  3227. }
  3228. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3229. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3230. WCD9XXX_CODEC_HWDEP_NODE, component);
  3231. if (ret < 0) {
  3232. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3233. goto err_hwdep;
  3234. }
  3235. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3236. if (ret) {
  3237. pr_err("%s: mbhc initialization failed\n", __func__);
  3238. goto err_hwdep;
  3239. }
  3240. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3241. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3242. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3243. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3244. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3245. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3246. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3247. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3248. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3249. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3250. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3251. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3252. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3253. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3254. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3255. snd_soc_dapm_sync(dapm);
  3256. wcd_cls_h_init(&wcd938x->clsh_info);
  3257. wcd938x_init_reg(component);
  3258. if (wcd938x->variant == WCD9380) {
  3259. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3260. ARRAY_SIZE(wcd9380_snd_controls));
  3261. if (ret < 0) {
  3262. dev_err(component->dev,
  3263. "%s: Failed to add snd ctrls for variant: %d\n",
  3264. __func__, wcd938x->variant);
  3265. goto err_hwdep;
  3266. }
  3267. }
  3268. if (wcd938x->variant == WCD9385) {
  3269. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3270. ARRAY_SIZE(wcd9385_snd_controls));
  3271. if (ret < 0) {
  3272. dev_err(component->dev,
  3273. "%s: Failed to add snd ctrls for variant: %d\n",
  3274. __func__, wcd938x->variant);
  3275. goto err_hwdep;
  3276. }
  3277. }
  3278. wcd938x->version = WCD938X_VERSION_1_0;
  3279. /* Register event notifier */
  3280. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3281. if (wcd938x->register_notifier) {
  3282. ret = wcd938x->register_notifier(wcd938x->handle,
  3283. &wcd938x->nblock,
  3284. true);
  3285. if (ret) {
  3286. dev_err(component->dev,
  3287. "%s: Failed to register notifier %d\n",
  3288. __func__, ret);
  3289. return ret;
  3290. }
  3291. }
  3292. wcd938x->dev_up = true;
  3293. return ret;
  3294. err_hwdep:
  3295. wcd938x->fw_data = NULL;
  3296. err:
  3297. return ret;
  3298. }
  3299. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3300. {
  3301. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3302. if (!wcd938x) {
  3303. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3304. __func__);
  3305. return;
  3306. }
  3307. if (wcd938x->register_notifier)
  3308. wcd938x->register_notifier(wcd938x->handle,
  3309. &wcd938x->nblock,
  3310. false);
  3311. }
  3312. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3313. {
  3314. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3315. if (!wcd938x)
  3316. return 0;
  3317. wcd938x->dapm_bias_off = true;
  3318. return 0;
  3319. }
  3320. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3321. {
  3322. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3323. if (!wcd938x)
  3324. return 0;
  3325. wcd938x->dapm_bias_off = false;
  3326. return 0;
  3327. }
  3328. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3329. .name = WCD938X_DRV_NAME,
  3330. .probe = wcd938x_soc_codec_probe,
  3331. .remove = wcd938x_soc_codec_remove,
  3332. .controls = wcd938x_snd_controls,
  3333. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3334. .dapm_widgets = wcd938x_dapm_widgets,
  3335. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3336. .dapm_routes = wcd938x_audio_map,
  3337. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3338. .suspend = wcd938x_soc_codec_suspend,
  3339. .resume = wcd938x_soc_codec_resume,
  3340. };
  3341. static int wcd938x_reset(struct device *dev)
  3342. {
  3343. struct wcd938x_priv *wcd938x = NULL;
  3344. int rc = 0;
  3345. int value = 0;
  3346. if (!dev)
  3347. return -ENODEV;
  3348. wcd938x = dev_get_drvdata(dev);
  3349. if (!wcd938x)
  3350. return -EINVAL;
  3351. if (!wcd938x->rst_np) {
  3352. dev_err(dev, "%s: reset gpio device node not specified\n",
  3353. __func__);
  3354. return -EINVAL;
  3355. }
  3356. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3357. if (value > 0)
  3358. return 0;
  3359. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3360. if (rc) {
  3361. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3362. __func__);
  3363. return rc;
  3364. }
  3365. /* 20us sleep required after pulling the reset gpio to LOW */
  3366. usleep_range(20, 30);
  3367. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3368. if (rc) {
  3369. dev_err(dev, "%s: wcd active state request fail!\n",
  3370. __func__);
  3371. return rc;
  3372. }
  3373. /* 20us sleep required after pulling the reset gpio to HIGH */
  3374. usleep_range(20, 30);
  3375. return rc;
  3376. }
  3377. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3378. u32 *val)
  3379. {
  3380. int rc = 0;
  3381. rc = of_property_read_u32(dev->of_node, name, val);
  3382. if (rc)
  3383. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3384. __func__, name, dev->of_node->full_name);
  3385. return rc;
  3386. }
  3387. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3388. struct wcd938x_micbias_setting *mb)
  3389. {
  3390. u32 prop_val = 0;
  3391. int rc = 0;
  3392. /* MB1 */
  3393. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3394. NULL)) {
  3395. rc = wcd938x_read_of_property_u32(dev,
  3396. "qcom,cdc-micbias1-mv",
  3397. &prop_val);
  3398. if (!rc)
  3399. mb->micb1_mv = prop_val;
  3400. } else {
  3401. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3402. __func__);
  3403. }
  3404. /* MB2 */
  3405. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3406. NULL)) {
  3407. rc = wcd938x_read_of_property_u32(dev,
  3408. "qcom,cdc-micbias2-mv",
  3409. &prop_val);
  3410. if (!rc)
  3411. mb->micb2_mv = prop_val;
  3412. } else {
  3413. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3414. __func__);
  3415. }
  3416. /* MB3 */
  3417. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3418. NULL)) {
  3419. rc = wcd938x_read_of_property_u32(dev,
  3420. "qcom,cdc-micbias3-mv",
  3421. &prop_val);
  3422. if (!rc)
  3423. mb->micb3_mv = prop_val;
  3424. } else {
  3425. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3426. __func__);
  3427. }
  3428. /* MB4 */
  3429. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3430. NULL)) {
  3431. rc = wcd938x_read_of_property_u32(dev,
  3432. "qcom,cdc-micbias4-mv",
  3433. &prop_val);
  3434. if (!rc)
  3435. mb->micb4_mv = prop_val;
  3436. } else {
  3437. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3438. __func__);
  3439. }
  3440. }
  3441. static int wcd938x_reset_low(struct device *dev)
  3442. {
  3443. struct wcd938x_priv *wcd938x = NULL;
  3444. int rc = 0;
  3445. if (!dev)
  3446. return -ENODEV;
  3447. wcd938x = dev_get_drvdata(dev);
  3448. if (!wcd938x)
  3449. return -EINVAL;
  3450. if (!wcd938x->rst_np) {
  3451. dev_err(dev, "%s: reset gpio device node not specified\n",
  3452. __func__);
  3453. return -EINVAL;
  3454. }
  3455. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3456. if (rc) {
  3457. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3458. __func__);
  3459. return rc;
  3460. }
  3461. /* 20us sleep required after pulling the reset gpio to LOW */
  3462. usleep_range(20, 30);
  3463. return rc;
  3464. }
  3465. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3466. {
  3467. struct wcd938x_pdata *pdata = NULL;
  3468. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3469. GFP_KERNEL);
  3470. if (!pdata)
  3471. return NULL;
  3472. pdata->rst_np = of_parse_phandle(dev->of_node,
  3473. "qcom,wcd-rst-gpio-node", 0);
  3474. if (!pdata->rst_np) {
  3475. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3476. __func__, "qcom,wcd-rst-gpio-node",
  3477. dev->of_node->full_name);
  3478. return NULL;
  3479. }
  3480. /* Parse power supplies */
  3481. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3482. &pdata->num_supplies);
  3483. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3484. dev_err(dev, "%s: no power supplies defined for codec\n",
  3485. __func__);
  3486. return NULL;
  3487. }
  3488. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3489. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3490. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3491. return pdata;
  3492. }
  3493. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3494. {
  3495. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3496. __func__, irq);
  3497. return IRQ_HANDLED;
  3498. }
  3499. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3500. {
  3501. .name = "wcd938x_cdc",
  3502. .playback = {
  3503. .stream_name = "WCD938X_AIF Playback",
  3504. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3505. .formats = WCD938X_FORMATS,
  3506. .rate_max = 192000,
  3507. .rate_min = 8000,
  3508. .channels_min = 1,
  3509. .channels_max = 4,
  3510. },
  3511. .capture = {
  3512. .stream_name = "WCD938X_AIF Capture",
  3513. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3514. .formats = WCD938X_FORMATS,
  3515. .rate_max = 192000,
  3516. .rate_min = 8000,
  3517. .channels_min = 1,
  3518. .channels_max = 4,
  3519. },
  3520. },
  3521. };
  3522. static int wcd938x_bind(struct device *dev)
  3523. {
  3524. int ret = 0, i = 0;
  3525. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3526. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3527. /*
  3528. * Add 5msec delay to provide sufficient time for
  3529. * soundwire auto enumeration of slave devices as
  3530. * as per HW requirement.
  3531. */
  3532. usleep_range(5000, 5010);
  3533. ret = component_bind_all(dev, wcd938x);
  3534. if (ret) {
  3535. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3536. __func__, ret);
  3537. return ret;
  3538. }
  3539. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3540. if (!wcd938x->rx_swr_dev) {
  3541. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3542. __func__);
  3543. ret = -ENODEV;
  3544. goto err;
  3545. }
  3546. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3547. if (!wcd938x->tx_swr_dev) {
  3548. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3549. __func__);
  3550. ret = -ENODEV;
  3551. goto err;
  3552. }
  3553. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3554. &wcd938x_regmap_config);
  3555. if (!wcd938x->regmap) {
  3556. dev_err(dev, "%s: Regmap init failed\n",
  3557. __func__);
  3558. goto err;
  3559. }
  3560. /* Set all interupts as edge triggered */
  3561. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3562. regmap_write(wcd938x->regmap,
  3563. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3564. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3565. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3566. wcd938x->irq_info.codec_name = "WCD938X";
  3567. wcd938x->irq_info.regmap = wcd938x->regmap;
  3568. wcd938x->irq_info.dev = dev;
  3569. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3570. if (ret) {
  3571. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3572. __func__, ret);
  3573. goto err;
  3574. }
  3575. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3576. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3577. if (ret < 0) {
  3578. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3579. goto err_irq;
  3580. }
  3581. /* Request for watchdog interrupt */
  3582. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3583. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3584. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3585. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3586. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3587. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3588. /* Disable watchdog interrupt for HPH and AUX */
  3589. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3590. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3591. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3592. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3593. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3594. if (ret) {
  3595. dev_err(dev, "%s: Codec registration failed\n",
  3596. __func__);
  3597. goto err_irq;
  3598. }
  3599. return ret;
  3600. err_irq:
  3601. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3602. err:
  3603. component_unbind_all(dev, wcd938x);
  3604. return ret;
  3605. }
  3606. static void wcd938x_unbind(struct device *dev)
  3607. {
  3608. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3609. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3610. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3611. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3612. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3613. snd_soc_unregister_component(dev);
  3614. component_unbind_all(dev, wcd938x);
  3615. }
  3616. static const struct of_device_id wcd938x_dt_match[] = {
  3617. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3618. {}
  3619. };
  3620. static const struct component_master_ops wcd938x_comp_ops = {
  3621. .bind = wcd938x_bind,
  3622. .unbind = wcd938x_unbind,
  3623. };
  3624. static int wcd938x_compare_of(struct device *dev, void *data)
  3625. {
  3626. return dev->of_node == data;
  3627. }
  3628. static void wcd938x_release_of(struct device *dev, void *data)
  3629. {
  3630. of_node_put(data);
  3631. }
  3632. static int wcd938x_add_slave_components(struct device *dev,
  3633. struct component_match **matchptr)
  3634. {
  3635. struct device_node *np, *rx_node, *tx_node;
  3636. np = dev->of_node;
  3637. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3638. if (!rx_node) {
  3639. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3640. return -ENODEV;
  3641. }
  3642. of_node_get(rx_node);
  3643. component_match_add_release(dev, matchptr,
  3644. wcd938x_release_of,
  3645. wcd938x_compare_of,
  3646. rx_node);
  3647. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3648. if (!tx_node) {
  3649. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3650. return -ENODEV;
  3651. }
  3652. of_node_get(tx_node);
  3653. component_match_add_release(dev, matchptr,
  3654. wcd938x_release_of,
  3655. wcd938x_compare_of,
  3656. tx_node);
  3657. return 0;
  3658. }
  3659. static int wcd938x_probe(struct platform_device *pdev)
  3660. {
  3661. struct component_match *match = NULL;
  3662. struct wcd938x_priv *wcd938x = NULL;
  3663. struct wcd938x_pdata *pdata = NULL;
  3664. struct wcd_ctrl_platform_data *plat_data = NULL;
  3665. struct device *dev = &pdev->dev;
  3666. int ret;
  3667. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3668. GFP_KERNEL);
  3669. if (!wcd938x)
  3670. return -ENOMEM;
  3671. dev_set_drvdata(dev, wcd938x);
  3672. wcd938x->dev = dev;
  3673. pdata = wcd938x_populate_dt_data(dev);
  3674. if (!pdata) {
  3675. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3676. return -EINVAL;
  3677. }
  3678. dev->platform_data = pdata;
  3679. wcd938x->rst_np = pdata->rst_np;
  3680. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3681. pdata->regulator, pdata->num_supplies);
  3682. if (!wcd938x->supplies) {
  3683. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3684. __func__);
  3685. return ret;
  3686. }
  3687. plat_data = dev_get_platdata(dev->parent);
  3688. if (!plat_data) {
  3689. dev_err(dev, "%s: platform data from parent is NULL\n",
  3690. __func__);
  3691. return -EINVAL;
  3692. }
  3693. wcd938x->handle = (void *)plat_data->handle;
  3694. if (!wcd938x->handle) {
  3695. dev_err(dev, "%s: handle is NULL\n", __func__);
  3696. return -EINVAL;
  3697. }
  3698. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3699. if (!wcd938x->update_wcd_event) {
  3700. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3701. __func__);
  3702. return -EINVAL;
  3703. }
  3704. wcd938x->register_notifier = plat_data->register_notifier;
  3705. if (!wcd938x->register_notifier) {
  3706. dev_err(dev, "%s: register_notifier api is null!\n",
  3707. __func__);
  3708. return -EINVAL;
  3709. }
  3710. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3711. pdata->regulator,
  3712. pdata->num_supplies);
  3713. if (ret) {
  3714. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3715. __func__);
  3716. return ret;
  3717. }
  3718. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3719. CODEC_RX);
  3720. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3721. CODEC_TX);
  3722. if (ret) {
  3723. dev_err(dev, "Failed to read port mapping\n");
  3724. goto err;
  3725. }
  3726. mutex_init(&wcd938x->wakeup_lock);
  3727. mutex_init(&wcd938x->micb_lock);
  3728. ret = wcd938x_add_slave_components(dev, &match);
  3729. if (ret)
  3730. goto err_lock_init;
  3731. wcd938x_reset(dev);
  3732. wcd938x->wakeup = wcd938x_wakeup;
  3733. return component_master_add_with_match(dev,
  3734. &wcd938x_comp_ops, match);
  3735. err_lock_init:
  3736. mutex_destroy(&wcd938x->micb_lock);
  3737. mutex_destroy(&wcd938x->wakeup_lock);
  3738. err:
  3739. return ret;
  3740. }
  3741. static int wcd938x_remove(struct platform_device *pdev)
  3742. {
  3743. struct wcd938x_priv *wcd938x = NULL;
  3744. wcd938x = platform_get_drvdata(pdev);
  3745. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3746. mutex_destroy(&wcd938x->micb_lock);
  3747. mutex_destroy(&wcd938x->wakeup_lock);
  3748. dev_set_drvdata(&pdev->dev, NULL);
  3749. return 0;
  3750. }
  3751. #ifdef CONFIG_PM_SLEEP
  3752. static int wcd938x_suspend(struct device *dev)
  3753. {
  3754. struct wcd938x_priv *wcd938x = NULL;
  3755. int ret = 0;
  3756. struct wcd938x_pdata *pdata = NULL;
  3757. if (!dev)
  3758. return -ENODEV;
  3759. wcd938x = dev_get_drvdata(dev);
  3760. if (!wcd938x)
  3761. return -EINVAL;
  3762. pdata = dev_get_platdata(wcd938x->dev);
  3763. if (!pdata) {
  3764. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3765. return -EINVAL;
  3766. }
  3767. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  3768. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  3769. wcd938x->supplies,
  3770. pdata->regulator,
  3771. pdata->num_supplies,
  3772. "cdc-vdd-buck");
  3773. if (ret == -EINVAL) {
  3774. dev_err(dev, "%s: vdd buck is not disabled\n",
  3775. __func__);
  3776. return 0;
  3777. }
  3778. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  3779. }
  3780. if (wcd938x->dapm_bias_off) {
  3781. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3782. wcd938x->supplies,
  3783. pdata->regulator,
  3784. pdata->num_supplies,
  3785. true);
  3786. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3787. }
  3788. return 0;
  3789. }
  3790. static int wcd938x_resume(struct device *dev)
  3791. {
  3792. struct wcd938x_priv *wcd938x = NULL;
  3793. struct wcd938x_pdata *pdata = NULL;
  3794. if (!dev)
  3795. return -ENODEV;
  3796. wcd938x = dev_get_drvdata(dev);
  3797. if (!wcd938x)
  3798. return -EINVAL;
  3799. pdata = dev_get_platdata(wcd938x->dev);
  3800. if (!pdata) {
  3801. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3802. return -EINVAL;
  3803. }
  3804. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  3805. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3806. wcd938x->supplies,
  3807. pdata->regulator,
  3808. pdata->num_supplies,
  3809. false);
  3810. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3811. }
  3812. return 0;
  3813. }
  3814. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3815. .suspend_late = wcd938x_suspend,
  3816. .resume_early = wcd938x_resume,
  3817. };
  3818. #endif
  3819. static struct platform_driver wcd938x_codec_driver = {
  3820. .probe = wcd938x_probe,
  3821. .remove = wcd938x_remove,
  3822. .driver = {
  3823. .name = "wcd938x_codec",
  3824. .owner = THIS_MODULE,
  3825. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3826. #ifdef CONFIG_PM_SLEEP
  3827. .pm = &wcd938x_dev_pm_ops,
  3828. #endif
  3829. .suppress_bind_attrs = true,
  3830. },
  3831. };
  3832. module_platform_driver(wcd938x_codec_driver);
  3833. MODULE_DESCRIPTION("WCD938X Codec driver");
  3834. MODULE_LICENSE("GPL v2");