hal_8074v2_rx.h 15 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_hw_headers.h"
  19. #include "hal_internal.h"
  20. #include "cdp_txrx_mon_struct.h"
  21. #include "qdf_trace.h"
  22. #include "hal_rx.h"
  23. #include "hal_tx.h"
  24. #include "dp_types.h"
  25. #include "hal_api_mon.h"
  26. #ifndef QCA_WIFI_QCA6018
  27. #include "phyrx_other_receive_info_su_evm_details.h"
  28. #endif
  29. #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
  30. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  31. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
  32. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
  33. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
  34. #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
  35. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  36. RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
  37. RX_MSDU_END_5_DA_IS_MCBC_MASK, \
  38. RX_MSDU_END_5_DA_IS_MCBC_LSB))
  39. #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
  40. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  41. RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
  42. RX_MSDU_END_5_SA_IS_VALID_MASK, \
  43. RX_MSDU_END_5_SA_IS_VALID_LSB))
  44. #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
  45. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  46. RX_MSDU_END_13_SA_IDX_OFFSET)), \
  47. RX_MSDU_END_13_SA_IDX_MASK, \
  48. RX_MSDU_END_13_SA_IDX_LSB))
  49. #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
  50. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  51. RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
  52. RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
  53. RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
  54. #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
  55. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  56. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
  57. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
  58. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
  59. #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
  60. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  61. RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
  62. RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
  63. RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
  64. /*
  65. * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
  66. * Interval from rx_msdu_start
  67. *
  68. * @buf: pointer to the start of RX PKT TLV header
  69. * Return: uint32_t(nss)
  70. */
  71. static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf)
  72. {
  73. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  74. struct rx_msdu_start *msdu_start =
  75. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  76. uint8_t mimo_ss_bitmap;
  77. mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
  78. return qdf_get_hweight8(mimo_ss_bitmap);
  79. }
  80. /**
  81. * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status
  82. *
  83. * @ hw_desc_addr: Start address of Rx HW TLVs
  84. * @ rs: Status for monitor mode
  85. *
  86. * Return: void
  87. */
  88. static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr,
  89. struct mon_rx_status *rs)
  90. {
  91. struct rx_msdu_start *rx_msdu_start;
  92. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  93. uint32_t reg_value;
  94. const uint32_t sgi_hw_to_cdp[] = {
  95. CDP_SGI_0_8_US,
  96. CDP_SGI_0_4_US,
  97. CDP_SGI_1_6_US,
  98. CDP_SGI_3_2_US,
  99. };
  100. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  101. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  102. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  103. RX_MSDU_START_5, USER_RSSI);
  104. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  105. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  106. rs->sgi = sgi_hw_to_cdp[reg_value];
  107. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  108. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  109. /* TODO: rs->beamformed should be set for SU beamforming also */
  110. }
  111. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  112. static uint32_t hal_get_link_desc_size_8074v2(void)
  113. {
  114. return LINK_DESC_SIZE;
  115. }
  116. /*
  117. * hal_rx_get_tlv_8074v2(): API to get the tlv
  118. *
  119. * @rx_tlv: TLV data extracted from the rx packet
  120. * Return: uint8_t
  121. */
  122. static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv)
  123. {
  124. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  125. }
  126. #ifndef QCA_WIFI_QCA6018
  127. #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \
  128. (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \
  129. PHYRX_OTHER_RECEIVE_INFO, \
  130. SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM)
  131. static inline void
  132. hal_rx_update_su_evm_info(void *rx_tlv,
  133. void *ppdu_info_hdl)
  134. {
  135. struct hal_rx_ppdu_info *ppdu_info =
  136. (struct hal_rx_ppdu_info *)ppdu_info_hdl;
  137. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0);
  138. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1);
  139. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2);
  140. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3);
  141. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4);
  142. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5);
  143. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6);
  144. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7);
  145. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8);
  146. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9);
  147. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10);
  148. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11);
  149. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12);
  150. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13);
  151. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14);
  152. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15);
  153. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16);
  154. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17);
  155. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18);
  156. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19);
  157. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20);
  158. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21);
  159. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22);
  160. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23);
  161. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24);
  162. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25);
  163. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26);
  164. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27);
  165. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28);
  166. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29);
  167. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30);
  168. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31);
  169. }
  170. /**
  171. * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2()
  172. * -process other receive info TLV
  173. * @rx_tlv_hdr: pointer to TLV header
  174. * @ppdu_info: pointer to ppdu_info
  175. *
  176. * Return: None
  177. */
  178. static
  179. void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
  180. void *ppdu_info_hdl)
  181. {
  182. uint16_t tlv_tag;
  183. void *rx_tlv;
  184. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  185. /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the
  186. * embedded TLVs inside
  187. */
  188. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  189. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  190. switch (tlv_tag) {
  191. case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E:
  192. /* Skip TLV length to get TLV content */
  193. rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  194. ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv,
  195. PHYRX_OTHER_RECEIVE_INFO,
  196. SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS);
  197. ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv,
  198. PHYRX_OTHER_RECEIVE_INFO,
  199. SU_EVM_DETAILS_0_PILOT_COUNT);
  200. ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv,
  201. PHYRX_OTHER_RECEIVE_INFO,
  202. SU_EVM_DETAILS_0_NSS_COUNT);
  203. hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl);
  204. break;
  205. }
  206. }
  207. #else
  208. static inline
  209. void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
  210. void *ppdu_info_hdl)
  211. {
  212. }
  213. #endif
  214. /**
  215. * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured
  216. * human readable format.
  217. * @ msdu_start: pointer the msdu_start TLV in pkt.
  218. * @ dbg_level: log level.
  219. *
  220. * Return: void
  221. */
  222. static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart,
  223. uint8_t dbg_level)
  224. {
  225. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  226. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  227. "rx_msdu_start tlv - "
  228. "rxpcu_mpdu_filter_in_category: %d "
  229. "sw_frame_group_id: %d "
  230. "phy_ppdu_id: %d "
  231. "msdu_length: %d "
  232. "ipsec_esp: %d "
  233. "l3_offset: %d "
  234. "ipsec_ah: %d "
  235. "l4_offset: %d "
  236. "msdu_number: %d "
  237. "decap_format: %d "
  238. "ipv4_proto: %d "
  239. "ipv6_proto: %d "
  240. "tcp_proto: %d "
  241. "udp_proto: %d "
  242. "ip_frag: %d "
  243. "tcp_only_ack: %d "
  244. "da_is_bcast_mcast: %d "
  245. "ip4_protocol_ip6_next_header: %d "
  246. "toeplitz_hash_2_or_4: %d "
  247. "flow_id_toeplitz: %d "
  248. "user_rssi: %d "
  249. "pkt_type: %d "
  250. "stbc: %d "
  251. "sgi: %d "
  252. "rate_mcs: %d "
  253. "receive_bandwidth: %d "
  254. "reception_type: %d "
  255. "ppdu_start_timestamp: %d "
  256. "sw_phy_meta_data: %d ",
  257. msdu_start->rxpcu_mpdu_filter_in_category,
  258. msdu_start->sw_frame_group_id,
  259. msdu_start->phy_ppdu_id,
  260. msdu_start->msdu_length,
  261. msdu_start->ipsec_esp,
  262. msdu_start->l3_offset,
  263. msdu_start->ipsec_ah,
  264. msdu_start->l4_offset,
  265. msdu_start->msdu_number,
  266. msdu_start->decap_format,
  267. msdu_start->ipv4_proto,
  268. msdu_start->ipv6_proto,
  269. msdu_start->tcp_proto,
  270. msdu_start->udp_proto,
  271. msdu_start->ip_frag,
  272. msdu_start->tcp_only_ack,
  273. msdu_start->da_is_bcast_mcast,
  274. msdu_start->ip4_protocol_ip6_next_header,
  275. msdu_start->toeplitz_hash_2_or_4,
  276. msdu_start->flow_id_toeplitz,
  277. msdu_start->user_rssi,
  278. msdu_start->pkt_type,
  279. msdu_start->stbc,
  280. msdu_start->sgi,
  281. msdu_start->rate_mcs,
  282. msdu_start->receive_bandwidth,
  283. msdu_start->reception_type,
  284. msdu_start->ppdu_start_timestamp,
  285. msdu_start->sw_phy_meta_data);
  286. }
  287. /**
  288. * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured
  289. * human readable format.
  290. * @ msdu_end: pointer the msdu_end TLV in pkt.
  291. * @ dbg_level: log level.
  292. *
  293. * Return: void
  294. */
  295. static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend,
  296. uint8_t dbg_level)
  297. {
  298. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  299. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  300. "rx_msdu_end tlv - "
  301. "rxpcu_mpdu_filter_in_category: %d "
  302. "sw_frame_group_id: %d "
  303. "phy_ppdu_id: %d "
  304. "ip_hdr_chksum: %d "
  305. "tcp_udp_chksum: %d "
  306. "key_id_octet: %d "
  307. "cce_super_rule: %d "
  308. "cce_classify_not_done_truncat: %d "
  309. "cce_classify_not_done_cce_dis: %d "
  310. "ext_wapi_pn_63_48: %d "
  311. "ext_wapi_pn_95_64: %d "
  312. "ext_wapi_pn_127_96: %d "
  313. "reported_mpdu_length: %d "
  314. "first_msdu: %d "
  315. "last_msdu: %d "
  316. "sa_idx_timeout: %d "
  317. "da_idx_timeout: %d "
  318. "msdu_limit_error: %d "
  319. "flow_idx_timeout: %d "
  320. "flow_idx_invalid: %d "
  321. "wifi_parser_error: %d "
  322. "amsdu_parser_error: %d "
  323. "sa_is_valid: %d "
  324. "da_is_valid: %d "
  325. "da_is_mcbc: %d "
  326. "l3_header_padding: %d "
  327. "ipv6_options_crc: %d "
  328. "tcp_seq_number: %d "
  329. "tcp_ack_number: %d "
  330. "tcp_flag: %d "
  331. "lro_eligible: %d "
  332. "window_size: %d "
  333. "da_offset: %d "
  334. "sa_offset: %d "
  335. "da_offset_valid: %d "
  336. "sa_offset_valid: %d "
  337. "rule_indication_31_0: %d "
  338. "rule_indication_63_32: %d "
  339. "sa_idx: %d "
  340. "msdu_drop: %d "
  341. "reo_destination_indication: %d "
  342. "flow_idx: %d "
  343. "fse_metadata: %d "
  344. "cce_metadata: %d "
  345. "sa_sw_peer_id: %d ",
  346. msdu_end->rxpcu_mpdu_filter_in_category,
  347. msdu_end->sw_frame_group_id,
  348. msdu_end->phy_ppdu_id,
  349. msdu_end->ip_hdr_chksum,
  350. msdu_end->tcp_udp_chksum,
  351. msdu_end->key_id_octet,
  352. msdu_end->cce_super_rule,
  353. msdu_end->cce_classify_not_done_truncate,
  354. msdu_end->cce_classify_not_done_cce_dis,
  355. msdu_end->ext_wapi_pn_63_48,
  356. msdu_end->ext_wapi_pn_95_64,
  357. msdu_end->ext_wapi_pn_127_96,
  358. msdu_end->reported_mpdu_length,
  359. msdu_end->first_msdu,
  360. msdu_end->last_msdu,
  361. msdu_end->sa_idx_timeout,
  362. msdu_end->da_idx_timeout,
  363. msdu_end->msdu_limit_error,
  364. msdu_end->flow_idx_timeout,
  365. msdu_end->flow_idx_invalid,
  366. msdu_end->wifi_parser_error,
  367. msdu_end->amsdu_parser_error,
  368. msdu_end->sa_is_valid,
  369. msdu_end->da_is_valid,
  370. msdu_end->da_is_mcbc,
  371. msdu_end->l3_header_padding,
  372. msdu_end->ipv6_options_crc,
  373. msdu_end->tcp_seq_number,
  374. msdu_end->tcp_ack_number,
  375. msdu_end->tcp_flag,
  376. msdu_end->lro_eligible,
  377. msdu_end->window_size,
  378. msdu_end->da_offset,
  379. msdu_end->sa_offset,
  380. msdu_end->da_offset_valid,
  381. msdu_end->sa_offset_valid,
  382. msdu_end->rule_indication_31_0,
  383. msdu_end->rule_indication_63_32,
  384. msdu_end->sa_idx,
  385. msdu_end->msdu_drop,
  386. msdu_end->reo_destination_indication,
  387. msdu_end->flow_idx,
  388. msdu_end->fse_metadata,
  389. msdu_end->cce_metadata,
  390. msdu_end->sa_sw_peer_id);
  391. }
  392. /*
  393. * Get tid from RX_MPDU_START
  394. */
  395. #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
  396. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  397. RX_MPDU_INFO_3_TID_OFFSET)), \
  398. RX_MPDU_INFO_3_TID_MASK, \
  399. RX_MPDU_INFO_3_TID_LSB))
  400. static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf)
  401. {
  402. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  403. struct rx_mpdu_start *mpdu_start =
  404. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  405. uint32_t tid;
  406. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  407. return tid;
  408. }
  409. #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
  410. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  411. RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
  412. RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
  413. RX_MSDU_START_5_RECEPTION_TYPE_LSB))
  414. /*
  415. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  416. * Interval from rx_msdu_start
  417. *
  418. * @buf: pointer to the start of RX PKT TLV header
  419. * Return: uint32_t(reception_type)
  420. */
  421. static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf)
  422. {
  423. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  424. struct rx_msdu_start *msdu_start =
  425. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  426. uint32_t reception_type;
  427. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  428. return reception_type;
  429. }
  430. /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */
  431. #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
  432. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  433. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
  434. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \
  435. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB))
  436. /**
  437. * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx
  438. * from rx_msdu_end TLV
  439. *
  440. * @ buf: pointer to the start of RX PKT TLV headers
  441. * Return: da index
  442. */
  443. static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf)
  444. {
  445. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  446. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  447. uint16_t da_idx;
  448. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  449. return da_idx;
  450. }