tcl_gse_cmd.h 8.7 KB

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  1. /*
  2. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _TCL_GSE_CMD_H_
  19. #define _TCL_GSE_CMD_H_
  20. #if !defined(__ASSEMBLER__)
  21. #endif
  22. #define NUM_OF_DWORDS_TCL_GSE_CMD 8
  23. struct tcl_gse_cmd {
  24. uint32_t control_buffer_addr_31_0 : 32;
  25. uint32_t control_buffer_addr_39_32 : 8,
  26. gse_ctrl : 4,
  27. gse_sel : 1,
  28. status_destination_ring_id : 1,
  29. swap : 1,
  30. index_search_en : 1,
  31. cache_set_num : 4,
  32. reserved_1a : 12;
  33. uint32_t tcl_cmd_type : 1,
  34. reserved_2a : 31;
  35. uint32_t cmd_meta_data_31_0 : 32;
  36. uint32_t cmd_meta_data_63_32 : 32;
  37. uint32_t reserved_5a : 32;
  38. uint32_t reserved_6a : 32;
  39. uint32_t reserved_7a : 20,
  40. ring_id : 8,
  41. looping_count : 4;
  42. };
  43. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
  44. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
  45. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
  46. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
  47. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
  48. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
  49. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
  50. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
  51. #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
  52. #define TCL_GSE_CMD_GSE_CTRL_LSB 8
  53. #define TCL_GSE_CMD_GSE_CTRL_MSB 11
  54. #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
  55. #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
  56. #define TCL_GSE_CMD_GSE_SEL_LSB 12
  57. #define TCL_GSE_CMD_GSE_SEL_MSB 12
  58. #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
  59. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
  60. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
  61. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
  62. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
  63. #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
  64. #define TCL_GSE_CMD_SWAP_LSB 14
  65. #define TCL_GSE_CMD_SWAP_MSB 14
  66. #define TCL_GSE_CMD_SWAP_MASK 0x00004000
  67. #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
  68. #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
  69. #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
  70. #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
  71. #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
  72. #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
  73. #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
  74. #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
  75. #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
  76. #define TCL_GSE_CMD_RESERVED_1A_LSB 20
  77. #define TCL_GSE_CMD_RESERVED_1A_MSB 31
  78. #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
  79. #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
  80. #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
  81. #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
  82. #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
  83. #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
  84. #define TCL_GSE_CMD_RESERVED_2A_LSB 1
  85. #define TCL_GSE_CMD_RESERVED_2A_MSB 31
  86. #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
  87. #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
  88. #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
  89. #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
  90. #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
  91. #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
  92. #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
  93. #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
  94. #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
  95. #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
  96. #define TCL_GSE_CMD_RESERVED_5A_LSB 0
  97. #define TCL_GSE_CMD_RESERVED_5A_MSB 31
  98. #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
  99. #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
  100. #define TCL_GSE_CMD_RESERVED_6A_LSB 0
  101. #define TCL_GSE_CMD_RESERVED_6A_MSB 31
  102. #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
  103. #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
  104. #define TCL_GSE_CMD_RESERVED_7A_LSB 0
  105. #define TCL_GSE_CMD_RESERVED_7A_MSB 19
  106. #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
  107. #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
  108. #define TCL_GSE_CMD_RING_ID_LSB 20
  109. #define TCL_GSE_CMD_RING_ID_MSB 27
  110. #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
  111. #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
  112. #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
  113. #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
  114. #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
  115. #endif