96d2d41c87
Removed qdf exports on functions defined in target specific header files and defined those functions as static. Revert changes on hal_rx_msdu_end_sa_idx_get and make hal_rx_msdu_end_da_idx_get target specific Change-Id: I2858b1d77118f0a26b54bf983bd342c7a4fe757d
350 baris
10 KiB
C
350 baris
10 KiB
C
/*
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* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HAL_INTERNAL_H_
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#define _HAL_INTERNAL_H_
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#include "qdf_types.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "pld_common.h"
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/* TBD: This should be movded to shared HW header file */
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enum hal_srng_ring_id {
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/* UMAC rings */
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HAL_SRNG_REO2SW1 = 0,
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HAL_SRNG_REO2SW2 = 1,
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HAL_SRNG_REO2SW3 = 2,
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HAL_SRNG_REO2SW4 = 3,
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HAL_SRNG_REO2TCL = 4,
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HAL_SRNG_SW2REO = 5,
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/* 6-7 unused */
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HAL_SRNG_REO_CMD = 8,
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HAL_SRNG_REO_STATUS = 9,
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/* 10-15 unused */
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HAL_SRNG_SW2TCL1 = 16,
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HAL_SRNG_SW2TCL2 = 17,
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HAL_SRNG_SW2TCL3 = 18,
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HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */
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/* 20-23 unused */
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HAL_SRNG_SW2TCL_CMD = 24,
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HAL_SRNG_TCL_STATUS = 25,
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/* 26-31 unused */
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HAL_SRNG_CE_0_SRC = 32,
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HAL_SRNG_CE_1_SRC = 33,
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HAL_SRNG_CE_2_SRC = 34,
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HAL_SRNG_CE_3_SRC = 35,
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HAL_SRNG_CE_4_SRC = 36,
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HAL_SRNG_CE_5_SRC = 37,
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HAL_SRNG_CE_6_SRC = 38,
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HAL_SRNG_CE_7_SRC = 39,
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HAL_SRNG_CE_8_SRC = 40,
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HAL_SRNG_CE_9_SRC = 41,
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HAL_SRNG_CE_10_SRC = 42,
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HAL_SRNG_CE_11_SRC = 43,
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/* 44-55 unused */
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HAL_SRNG_CE_0_DST = 56,
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HAL_SRNG_CE_1_DST = 57,
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HAL_SRNG_CE_2_DST = 58,
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HAL_SRNG_CE_3_DST = 59,
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HAL_SRNG_CE_4_DST = 60,
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HAL_SRNG_CE_5_DST = 61,
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HAL_SRNG_CE_6_DST = 62,
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HAL_SRNG_CE_7_DST = 63,
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HAL_SRNG_CE_8_DST = 64,
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HAL_SRNG_CE_9_DST = 65,
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HAL_SRNG_CE_10_DST = 66,
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HAL_SRNG_CE_11_DST = 67,
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/* 68-79 unused */
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HAL_SRNG_CE_0_DST_STATUS = 80,
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HAL_SRNG_CE_1_DST_STATUS = 81,
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HAL_SRNG_CE_2_DST_STATUS = 82,
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HAL_SRNG_CE_3_DST_STATUS = 83,
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HAL_SRNG_CE_4_DST_STATUS = 84,
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HAL_SRNG_CE_5_DST_STATUS = 85,
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HAL_SRNG_CE_6_DST_STATUS = 86,
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HAL_SRNG_CE_7_DST_STATUS = 87,
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HAL_SRNG_CE_8_DST_STATUS = 88,
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HAL_SRNG_CE_9_DST_STATUS = 89,
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HAL_SRNG_CE_10_DST_STATUS = 90,
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HAL_SRNG_CE_11_DST_STATUS = 91,
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/* 92-103 unused */
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HAL_SRNG_WBM_IDLE_LINK = 104,
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HAL_SRNG_WBM_SW_RELEASE = 105,
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HAL_SRNG_WBM2SW0_RELEASE = 106,
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HAL_SRNG_WBM2SW1_RELEASE = 107,
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HAL_SRNG_WBM2SW2_RELEASE = 108,
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HAL_SRNG_WBM2SW3_RELEASE = 109,
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/* 110-127 unused */
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HAL_SRNG_UMAC_ID_END = 127,
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/* LMAC rings - The following set will be replicated for each LMAC */
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HAL_SRNG_LMAC1_ID_START = 128,
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HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
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#ifdef IPA_OFFLOAD
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HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1),
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HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2),
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HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1),
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#else
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HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1),
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#endif
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HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1),
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HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1),
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HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF =
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(HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1),
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HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1),
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HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1),
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HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1),
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#ifdef WLAN_FEATURE_CIF_CFR
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HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
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HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1),
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#else
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HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
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#endif
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/* -142 unused */
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HAL_SRNG_LMAC1_ID_END = 143
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};
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#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
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#define HAL_MAX_LMACS 3
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#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
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#define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
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#define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS)
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enum hal_srng_dir {
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HAL_SRNG_SRC_RING,
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HAL_SRNG_DST_RING
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};
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/* Lock wrappers for SRNG */
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#define hal_srng_lock_t qdf_spinlock_t
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#define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
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#define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
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#define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
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#define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
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struct hal_soc;
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#define MAX_SRNG_REG_GROUPS 2
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/* Common SRNG ring structure for source and destination rings */
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struct hal_srng {
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/* Unique SRNG ring ID */
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uint8_t ring_id;
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/* Ring initialization done */
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uint8_t initialized;
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/* Interrupt/MSI value assigned to this ring */
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int irq;
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/* Physical base address of the ring */
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qdf_dma_addr_t ring_base_paddr;
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/* Virtual base address of the ring */
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uint32_t *ring_base_vaddr;
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/* Number of entries in ring */
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uint32_t num_entries;
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/* Ring size */
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uint32_t ring_size;
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/* Ring size mask */
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uint32_t ring_size_mask;
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/* Size of ring entry */
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uint32_t entry_size;
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/* Interrupt timer threshold – in micro seconds */
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uint32_t intr_timer_thres_us;
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/* Interrupt batch counter threshold – in number of ring entries */
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uint32_t intr_batch_cntr_thres_entries;
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/* MSI Address */
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qdf_dma_addr_t msi_addr;
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/* MSI data */
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uint32_t msi_data;
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/* Misc flags */
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uint32_t flags;
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/* Lock for serializing ring index updates */
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hal_srng_lock_t lock;
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/* Start offset of SRNG register groups for this ring
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* TBD: See if this is required - register address can be derived
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* from ring ID
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*/
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void *hwreg_base[MAX_SRNG_REG_GROUPS];
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/* Source or Destination ring */
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enum hal_srng_dir ring_dir;
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union {
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struct {
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/* SW tail pointer */
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uint32_t tp;
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/* Shadow head pointer location to be updated by HW */
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uint32_t *hp_addr;
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/* Cached head pointer */
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uint32_t cached_hp;
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/* Tail pointer location to be updated by SW – This
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* will be a register address and need not be
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* accessed through SW structure */
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uint32_t *tp_addr;
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/* Current SW loop cnt */
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uint32_t loop_cnt;
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/* max transfer size */
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uint16_t max_buffer_length;
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} dst_ring;
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struct {
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/* SW head pointer */
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uint32_t hp;
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/* SW reap head pointer */
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uint32_t reap_hp;
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/* Shadow tail pointer location to be updated by HW */
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uint32_t *tp_addr;
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/* Cached tail pointer */
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uint32_t cached_tp;
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/* Head pointer location to be updated by SW – This
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* will be a register address and need not be accessed
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* through SW structure */
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uint32_t *hp_addr;
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/* Low threshold – in number of ring entries */
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uint32_t low_threshold;
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} src_ring;
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} u;
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struct hal_soc *hal_soc;
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};
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/* HW SRNG configuration table */
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struct hal_hw_srng_config {
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int start_ring_id;
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uint16_t max_rings;
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uint16_t entry_size;
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uint32_t reg_start[MAX_SRNG_REG_GROUPS];
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uint16_t reg_size[MAX_SRNG_REG_GROUPS];
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uint8_t lmac_ring;
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enum hal_srng_dir ring_dir;
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uint32_t max_size;
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};
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#define MAX_SHADOW_REGISTERS 36
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struct hal_hw_txrx_ops {
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/* tx */
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void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
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void (*hal_tx_set_dscp_tid_map)(void *hal_soc, uint8_t *map,
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uint8_t id);
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void (*hal_tx_update_dscp_tid)(void *hal_soc, uint8_t tid, uint8_t id,
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uint8_t dscp);
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void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
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/* rx */
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uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
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void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
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struct mon_rx_status *rs);
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uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
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void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
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void *ppdu_info_handle);
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void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level);
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void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end,
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uint8_t dbg_level);
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uint32_t (*hal_get_link_desc_size)(void);
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uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
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uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
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uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
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};
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/**
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* HAL context to be used to access SRNG APIs (currently used by data path
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* and transport (CE) modules)
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*/
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struct hal_soc {
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/* HIF handle to access HW registers */
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void *hif_handle;
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/* QDF device handle */
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qdf_device_t qdf_dev;
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/* Device base address */
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void *dev_base_addr;
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/* HAL internal state for all SRNG rings.
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* TODO: See if this is required
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*/
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struct hal_srng srng_list[HAL_SRNG_ID_MAX];
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/* Remote pointer memory for HW/FW updates */
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uint32_t *shadow_rdptr_mem_vaddr;
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qdf_dma_addr_t shadow_rdptr_mem_paddr;
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/* Shared memory for ring pointer updates from host to FW */
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uint32_t *shadow_wrptr_mem_vaddr;
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qdf_dma_addr_t shadow_wrptr_mem_paddr;
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/* REO blocking resource index */
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uint8_t reo_res_bitmap;
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uint8_t index;
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uint32_t target_type;
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/* shadow register configuration */
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struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS];
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int num_shadow_registers_configured;
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bool use_register_windowing;
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uint32_t register_window;
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qdf_spinlock_t register_access_lock;
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/* srng table */
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struct hal_hw_srng_config *hw_srng_table;
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int32_t *hal_hw_reg_offset;
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struct hal_hw_txrx_ops *ops;
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};
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void hal_qca6390_attach(struct hal_soc *hal_soc);
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void hal_qca6290_attach(struct hal_soc *hal_soc);
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void hal_qca8074_attach(struct hal_soc *hal_soc);
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#endif /* _HAL_INTERNAL_H_ */
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